di: optimize di pre mif config

PD#170980: di: optimize di pre mif config

1.add protect for di pre reset
2.add pre de done check when unreg
3.merge afbc hold line from alishan code
4.optimize pre mif enable sequence

Change-Id: I18851ad644aaee7c6c1d76c69f41a91f9599a36d
Signed-off-by: Dezhi Kong <dezhi.kong@amlogic.com>

2 files changed, 38 insertions, 16 deletions

diff --git a/drivers/amlogic/media/deinterlace/deinterlace.c b/drivers/amlogic/media/deinterlace/deinterlace.c
index 4168c25..e1e19e7 100644
--- a/drivers/amlogic/media/deinterlace/deinterlace.c
+++ b/drivers/amlogic/media/deinterlace/deinterlace.c
@@ -124,7 +124,7 @@ static di_dev_t *de_devp;
 static dev_t di_devno;
 static struct class *di_clsp;
 
-static const char version_s[] = "2018-08-03a";
+static const char version_s[] = "2018-08-06a";
 
 static int bypass_state = 1;
 static int bypass_all;
@@ -2271,7 +2271,6 @@ static void di_uninit_buf(unsigned int disable_mirror)
 	for (i = 0; i < MAX_IN_BUF_NUM; i++)
 		vframe_in[i] = NULL;
 	di_pre_stru.pre_de_process_done = 0;
-	di_pre_stru.pre_de_busy = 0;
 	di_pre_stru.pre_de_process_flag = 0;
 	if (post_wr_en && post_wr_support) {
 		di_post_stru.cur_post_buf = NULL;
@@ -2860,6 +2859,7 @@ static void pre_inp_canvas_config(struct vframe_s *vf);
 #endif
 static void pre_de_process(void)
 {
+	ulong irq_flag2 = 0;
 	unsigned short pre_width = 0, pre_height = 0;
 	unsigned char chan2_field_num = 1;
 	int canvases_idex = di_pre_stru.field_count_for_cont % 2;
@@ -3024,7 +3024,10 @@ static void pre_de_process(void)
 			vdin_ops->tvin_vdin_func(0, &vdin_arg);
 	}
 #endif
-	enable_di_pre_mif(true, mcpre_en);
+	/* must make sure follow part issue without iterrupts,
+	 * otherwise may cause watch dog reboot
+	 */
+	di_lock_irqfiq_save(irq_flag2);
 	if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
 		pre_frame_reset_g12(di_pre_stru.madi_enable,
 			di_pre_stru.mcdi_enable);
@@ -3033,6 +3036,7 @@ static void pre_de_process(void)
 		/* enable mc pre mif*/
 		enable_di_pre_mif(true, mcpre_en);
 	}
+	di_unlock_irqfiq_restore(irq_flag2);
 	/*reinit pre busy flag*/
 	di_pre_stru.pre_de_busy_timer_count = 0;
 	di_pre_stru.pre_de_busy = 1;
@@ -5905,7 +5909,6 @@ static void di_unreg_process(void)
 		if (unreg_cnt > 0x3fffffff)
 			unreg_cnt = 0;
 		pr_dbg("%s unreg stop %d.\n", __func__, reg_flag);
-		di_pre_stru.pre_de_busy = 0;
 		di_pre_stru.unreg_req_flag_irq = 1;
 		reg_flag = 0;
 		trigger_pre_di_process(TRIGGER_PRE_BY_UNREG);
@@ -6194,7 +6197,7 @@ static void di_reg_process_irq(void)
 				di_top_gate_control(true, false);
 			}
 			de_devp->flags |= DI_VPU_CLKB_SET;
-			enable_di_pre_mif(true, mcpre_en);
+			enable_di_pre_mif(false, mcpre_en);
 			di_pre_gate_control(true, mcpre_en);
 			nr_gate_control(true);
 		} else {
@@ -6500,7 +6503,12 @@ static void di_pre_process_irq(struct di_pre_stru_s *pre_stru_p)
 	int i;
 
 	if (active_flag) {
-		if (pre_stru_p->unreg_req_flag_irq)
+		/* must wait pre de done or time out to clear the de_busy
+		 * otherwise may appear watch dog reboot probablity
+		 * caused by disable mif in unreg_process_irq
+		 */
+		if (pre_stru_p->unreg_req_flag_irq &&
+			(di_pre_stru.pre_de_busy == 0))
 			di_unreg_process_irq();
 		if (init_flag == 0 && pre_stru_p->reg_req_flag_irq == 0)
 			di_reg_process_irq();
diff --git a/drivers/amlogic/media/deinterlace/deinterlace_hw.c b/drivers/amlogic/media/deinterlace/deinterlace_hw.c
index 935bec9..7545e368 100644
--- a/drivers/amlogic/media/deinterlace/deinterlace_hw.c
+++ b/drivers/amlogic/media/deinterlace/deinterlace_hw.c
@@ -785,7 +785,7 @@ void enable_afbc_input(struct vframe_s *vf)
 
 	if (vf->type & VIDTYPE_COMPRESS) {
 		r = (3 << 24) |
-		    (17 << 16) |
+		    (10 << 16) |
 		    (1 << 14) | /*burst1 1*/
 		    vf->bitdepth;
 
@@ -796,7 +796,6 @@ void enable_afbc_input(struct vframe_s *vf)
 			r |= 0x88;
 
 		RDMA_WR(AFBC_MODE, r);
-		RDMA_WR(AFBC_ENABLE, 0x1700);
 		RDMA_WR(AFBC_CONV_CTRL, 0x100);
 		u = (vf->bitdepth >> (BITDEPTH_U_SHIFT)) & 0x3;
 		v = (vf->bitdepth >> (BITDEPTH_V_SHIFT)) & 0x3;
@@ -834,19 +833,25 @@ void enable_afbc_input(struct vframe_s *vf)
 		RDMA_WR_BITS(DI_INP_GEN_REG, 0, 0, 1);
 		/* afbc to di enable */
 		if (!cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
-			if (Rd_reg_bits(VIU_MISC_CTRL0, 19, 1) != 1)
-				RDMA_WR_BITS(VIU_MISC_CTRL0, 1, 19, 1);
 			/* DI inp(current data) switch to AFBC */
-			RDMA_WR_BITS(VIUB_MISC_CTRL0, 1, 16, 1);
+			if (RDMA_RD_BITS(VIU_MISC_CTRL0, 29, 1) != 1)
+				RDMA_WR_BITS(VIU_MISC_CTRL0, 1, 29, 1);
+			if (RDMA_RD_BITS(VIUB_MISC_CTRL0, 16, 1) != 1)
+				RDMA_WR_BITS(VIUB_MISC_CTRL0, 1, 16, 1);
+			if (RDMA_RD_BITS(VIU_MISC_CTRL1, 0, 1) != 1)
+				RDMA_WR_BITS(VIU_MISC_CTRL1, 1, 0, 1);
+			if (RDMA_RD(VD2_AFBC_ENABLE) != 0x1600)
+				RDMA_WR(VD2_AFBC_ENABLE, 0x1600);
 		}
 	} else {
 		RDMA_WR(AFBC_ENABLE, 0);
 		/* afbc to vpp(replace vd1) enable */
 		if (!cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
-			if (Rd_reg_bits(VIU_MISC_CTRL0, 19, 1) != 0)
-				RDMA_WR_BITS(VIU_MISC_CTRL0, 0, 19, 1);
-			/* DI inp(current data) switch to memory */
-			RDMA_WR_BITS(VIUB_MISC_CTRL0, 0, 16, 1);
+			if (RDMA_RD_BITS(VIU_MISC_CTRL1, 0, 1) != 0 ||
+				RDMA_RD_BITS(VIUB_MISC_CTRL0, 16, 1) != 0) {
+				RDMA_WR_BITS(VIU_MISC_CTRL1, 0, 0, 1);
+				RDMA_WR_BITS(VIUB_MISC_CTRL0, 0, 16, 1);
+			}
 		}
 	}
 }
@@ -2985,7 +2990,13 @@ static void di_pre_data_mif_ctrl(bool enable)
 		/* enable input mif*/
 		DI_Wr(DI_CHAN2_GEN_REG, Rd(DI_CHAN2_GEN_REG) | 0x1);
 		DI_Wr(DI_MEM_GEN_REG, Rd(DI_MEM_GEN_REG) | 0x1);
-		DI_Wr(DI_INP_GEN_REG, Rd(DI_INP_GEN_REG) | 0x1);
+		if (Rd_reg_bits(VIU_MISC_CTRL1, 0, 1) == 1) {
+			DI_Wr(DI_INP_GEN_REG, Rd(DI_INP_GEN_REG) & ~0x1);
+			RDMA_WR_BITS(VD2_AFBC_ENABLE, 1, 8, 1);
+		} else {
+			DI_Wr(DI_INP_GEN_REG, Rd(DI_INP_GEN_REG) | 0x1);
+			RDMA_WR_BITS(VD2_AFBC_ENABLE, 0, 8, 1);
+		}
 		/* nrwr no clk gate en=0 */
 		RDMA_WR_BITS(DI_NRWR_CTRL, 0, 24, 1);
 	} else {
@@ -2997,6 +3008,9 @@ static void di_pre_data_mif_ctrl(bool enable)
 		DI_Wr(DI_CHAN2_GEN_REG, Rd(DI_CHAN2_GEN_REG) & ~0x1);
 		DI_Wr(DI_MEM_GEN_REG, Rd(DI_MEM_GEN_REG) & ~0x1);
 		DI_Wr(DI_INP_GEN_REG, Rd(DI_INP_GEN_REG) & ~0x1);
+		/* disable AFBC input */
+		if (Rd_reg_bits(VIU_MISC_CTRL1, 0, 1) == 1)
+			RDMA_WR_BITS(VD2_AFBC_ENABLE, 0, 8, 1);
 	}
 }