| author | Kaifu Hu <kaifu.hu@amlogic.com> | 2018-04-17 03:06:47 (GMT) |
|---|---|---|
| committer | Xindong Xu <xindong.xu@amlogic.com> | 2018-04-19 05:59:58 (GMT) |
| commit | aafdd4bd3fef0a00ca72093c13ea2cc4eff3b4af (patch) | |
| tree | 92c30edfe94d2eaaad9f0f62e86341d7ae141dc8 | |
| parent | 59082b165f7ec3efac16a5e3eab43bb69f481e0f (diff) | |
| download | common-aafdd4bd3fef0a00ca72093c13ea2cc4eff3b4af.zip common-aafdd4bd3fef0a00ca72093c13ea2cc4eff3b4af.tar.gz common-aafdd4bd3fef0a00ca72093c13ea2cc4eff3b4af.tar.bz2 | |
hdmitx: config DDC to 100kHz
PD#164530: hdmitx: config DDC to 100kHz
Config DDC to 100kHz for HDMI I2C.
Change-Id: I9b450bb8f9b727a3f468f55138aa64596abe92ef
Signed-off-by: Kaifu Hu <kaifu.hu@amlogic.com>
| -rw-r--r-- | arch/arm64/boot/dts/amlogic/mesong12a.dtsi | 1 | ||||
| -rw-r--r-- | drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c | 4 |
2 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/amlogic/mesong12a.dtsi b/arch/arm64/boot/dts/amlogic/mesong12a.dtsi index 4ba62be..0f4239e 100644 --- a/arch/arm64/boot/dts/amlogic/mesong12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/mesong12a.dtsi @@ -2108,6 +2108,7 @@ "hdmitx_sck"; function = "hdmitx"; bias-disable; + drive-strength = <3>; }; }; diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c index 3cd84fe..92ce220 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c @@ -593,9 +593,9 @@ static void hdmi_hwi_init(struct hdmitx_dev *hdev) hdmitx_wr_reg(HDMITX_DWC_I2CM_DIV, data32); hdmitx_wr_reg(HDMITX_DWC_I2CM_SS_SCL_HCNT_1, 0); - hdmitx_wr_reg(HDMITX_DWC_I2CM_SS_SCL_HCNT_0, 0x67); + hdmitx_wr_reg(HDMITX_DWC_I2CM_SS_SCL_HCNT_0, 0x68); hdmitx_wr_reg(HDMITX_DWC_I2CM_SS_SCL_LCNT_1, 0); - hdmitx_wr_reg(HDMITX_DWC_I2CM_SS_SCL_LCNT_0, 0x78); + hdmitx_wr_reg(HDMITX_DWC_I2CM_SS_SCL_LCNT_0, 0x79); hdmitx_wr_reg(HDMITX_DWC_I2CM_FS_SCL_HCNT_1, 0); hdmitx_wr_reg(HDMITX_DWC_I2CM_FS_SCL_HCNT_0, 0x0f); hdmitx_wr_reg(HDMITX_DWC_I2CM_FS_SCL_LCNT_1, 0); |