| author | Yi Zhou <yi.zhou@amlogic.com> | 2018-04-09 12:21:46 (GMT) |
|---|---|---|
| committer | Xindong Xu <xindong.xu@amlogic.com> | 2018-04-19 06:00:50 (GMT) |
| commit | b137491461ddd47d6cd5cab0acbce039a0bfc233 (patch) | |
| tree | e4fd46127ebf8c19d9f9044a87e57469b421aee0 | |
| parent | 03cc19c2a2326f32b5fdca2024e1604025a6a0bd (diff) | |
| download | common-b137491461ddd47d6cd5cab0acbce039a0bfc233.zip common-b137491461ddd47d6cd5cab0acbce039a0bfc233.tar.gz common-b137491461ddd47d6cd5cab0acbce039a0bfc233.tar.bz2 | |
hdmitx: update hdmitx pll parameter
PD#163960: hdmitx: update hdmitx pll parameter
Change-Id: I4a770a976586d42b510c128586a5239ade54a7c0
Signed-off-by: Yi Zhou <yi.zhou@amlogic.com>
| -rw-r--r-- | drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c | 21 |
1 files changed, 12 insertions, 9 deletions
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c index 4fb43bb..2b5ad47 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c @@ -91,13 +91,14 @@ static bool set_hpll_hclk_v1(unsigned int m, unsigned int frac_val) { int ret = 0; - hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b3a0400 | (m & 0xff)); + hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x0b3a0400 | (m & 0xff)); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x3, 28, 2); hd_write_reg(P_HHI_HDMI_PLL_CNTL1, frac_val); hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000); - hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x2a29dc00); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a68dc00); hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x65771290); hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39272000); - hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540000); hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1); WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0); pr_info("HPLLv1: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); @@ -110,13 +111,14 @@ static bool set_hpll_hclk_v2(unsigned int m, unsigned int frac_val) { int ret = 0; - hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b3a0400 | (m & 0xff)); + hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x0b3a0400 | (m & 0xff)); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x3, 28, 2); hd_write_reg(P_HHI_HDMI_PLL_CNTL1, frac_val); hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000); - hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0xeaa9dc00); - hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x95771290); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0xea68dc00); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x65771290); hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39272000); - hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x55540028); + hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540000); hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1); WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0); pr_info("HPLLv2: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); @@ -129,10 +131,11 @@ static bool set_hpll_hclk_v3(unsigned int m, unsigned int frac_val) { int ret = 0; - hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b3a0400 | (m & 0xff)); + hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x0b3a0400 | (m & 0xff)); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x3, 28, 2); hd_write_reg(P_HHI_HDMI_PLL_CNTL1, frac_val); hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000); - hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0xea29dc00); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0xea68dc00); hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x65771290); hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39272000); hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x55540000); |