blob: 456156294df13e02b3fc04c3b7a8acd838567039
1 | /* |
2 | * drivers/amlogic/cec/hdmi_ao_cec.c |
3 | * |
4 | * Copyright (C) 2017 Amlogic, Inc. All rights reserved. |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify |
7 | * it under the terms of the GNU General Public License as published by |
8 | * the Free Software Foundation; either version 2 of the License, or |
9 | * (at your option) any later version. |
10 | * |
11 | * This program is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty |
13 | * of MERCHANTABILITY orFITNESS FOR A PARTICULAR PURPOSE. |
14 | * See the GNU General Public License for more details. |
15 | */ |
16 | |
17 | #include <linux/version.h> |
18 | #include <linux/module.h> |
19 | #include <linux/irq.h> |
20 | #include <linux/types.h> |
21 | #include <linux/input.h> |
22 | #include <linux/kernel.h> |
23 | #include <linux/kthread.h> |
24 | #include <linux/delay.h> |
25 | #include <linux/uaccess.h> |
26 | #include <linux/interrupt.h> |
27 | #include <linux/fs.h> |
28 | #include <linux/init.h> |
29 | #include <linux/device.h> |
30 | #include <linux/mm.h> |
31 | #include <linux/major.h> |
32 | #include <linux/platform_device.h> |
33 | #include <linux/mutex.h> |
34 | #include <linux/cdev.h> |
35 | #include <linux/io.h> |
36 | #include <linux/slab.h> |
37 | #include <linux/list.h> |
38 | #include <linux/spinlock.h> |
39 | #include <linux/spinlock_types.h> |
40 | #include <linux/workqueue.h> |
41 | #include <linux/timer.h> |
42 | #include <linux/atomic.h> |
43 | #include <linux/of.h> |
44 | #include <linux/of_device.h> |
45 | #include <linux/of_address.h> |
46 | #include <linux/of_irq.h> |
47 | #include <linux/reboot.h> |
48 | #include <linux/notifier.h> |
49 | #include <linux/random.h> |
50 | #include <linux/pinctrl/consumer.h> |
51 | |
52 | #include <linux/amlogic/media/frame_provider/tvin/tvin.h> |
53 | #include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_cec_20.h> |
54 | #include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h> |
55 | #include <linux/amlogic/pm.h> |
56 | #include <linux/amlogic/cpu_version.h> |
57 | #include <linux/amlogic/jtag.h> |
58 | #include <linux/amlogic/scpi_protocol.h> |
59 | |
60 | #ifdef CONFIG_HAS_EARLYSUSPEND |
61 | #include <linux/earlysuspend.h> |
62 | static struct early_suspend aocec_suspend_handler; |
63 | #endif |
64 | #include "hdmi_ao_cec.h" |
65 | |
66 | |
67 | #define CEC_FRAME_DELAY msecs_to_jiffies(400) |
68 | #define CEC_DEV_NAME "cec" |
69 | |
70 | #define CEC_POWER_ON (0 << 0) |
71 | #define CEC_EARLY_SUSPEND (1 << 0) |
72 | #define CEC_DEEP_SUSPEND (1 << 1) |
73 | #define CEC_POWER_RESUME (1 << 2) |
74 | |
75 | #define HR_DELAY(n) (ktime_set(0, n * 1000 * 1000)) |
76 | #define MAX_INT 0x7ffffff |
77 | |
78 | struct cec_platform_data_s { |
79 | unsigned char line_reg;/*cec gpio_i reg:0 ao;1 periph*/ |
80 | unsigned int line_bit;/*cec gpio position in reg*/ |
81 | bool ee_to_ao;/*ee cec hw module mv to ao;ao cec delete*/ |
82 | }; |
83 | |
84 | struct cec_wakeup_t { |
85 | unsigned int wk_logic_addr:8; |
86 | unsigned int wk_phy_addr:16; |
87 | unsigned int wk_port_id:8; |
88 | }; |
89 | |
90 | /* global struct for tx and rx */ |
91 | struct ao_cec_dev { |
92 | unsigned long dev_type; |
93 | struct device_node *node; |
94 | unsigned int port_num; /*total input hdmi port number*/ |
95 | unsigned int cec_num; |
96 | unsigned int arc_port; |
97 | unsigned int output; |
98 | unsigned int hal_flag; |
99 | unsigned int phy_addr; |
100 | unsigned int port_seq; |
101 | unsigned int cpu_type; |
102 | unsigned long irq_cec; |
103 | void __iomem *exit_reg; |
104 | void __iomem *cec_reg; |
105 | void __iomem *hdmi_rxreg; |
106 | void __iomem *hhi_reg; |
107 | void __iomem *periphs_reg; |
108 | struct hdmitx_dev *tx_dev; |
109 | struct workqueue_struct *cec_thread; |
110 | struct device *dbg_dev; |
111 | const char *pin_name; |
112 | struct delayed_work cec_work; |
113 | struct completion rx_ok; |
114 | struct completion tx_ok; |
115 | spinlock_t cec_reg_lock; |
116 | struct mutex cec_mutex; |
117 | struct mutex cec_ioctl_mutex; |
118 | struct cec_wakeup_t wakup_data; |
119 | unsigned int wakeup_reason; |
120 | #ifdef CONFIG_PM |
121 | int cec_suspend; |
122 | #endif |
123 | struct vendor_info_data v_data; |
124 | struct cec_global_info_t cec_info; |
125 | struct cec_platform_data_s *plat_data; |
126 | }; |
127 | |
128 | struct cec_msg_last { |
129 | unsigned char msg[MAX_MSG]; |
130 | int len; |
131 | int last_result; |
132 | unsigned long last_jiffies; |
133 | }; |
134 | static struct cec_msg_last *last_cec_msg; |
135 | static struct dbgflg stdbgflg; |
136 | |
137 | static int phy_addr_test; |
138 | |
139 | /* from android cec hal */ |
140 | enum { |
141 | HDMI_OPTION_WAKEUP = 1, |
142 | HDMI_OPTION_ENABLE_CEC = 2, |
143 | HDMI_OPTION_SYSTEM_CEC_CONTROL = 3, |
144 | HDMI_OPTION_SET_LANG = 5, |
145 | HDMI_OPTION_SERVICE_FLAG = 16, |
146 | }; |
147 | |
148 | static struct ao_cec_dev *cec_dev; |
149 | static int cec_tx_result; |
150 | |
151 | static int cec_line_cnt; |
152 | static struct hrtimer start_bit_check; |
153 | |
154 | static unsigned char rx_msg[MAX_MSG]; |
155 | static unsigned char rx_len; |
156 | static unsigned int new_msg; |
157 | static bool wake_ok = 1; |
158 | static bool ee_cec; |
159 | static bool pin_status; |
160 | static unsigned int cec_msg_dbg_en; |
161 | |
162 | #define CEC_ERR(format, args...) \ |
163 | {if (cec_dev->dbg_dev) \ |
164 | dev_err(cec_dev->dbg_dev, format, ##args); \ |
165 | } |
166 | |
167 | #define CEC_INFO(format, args...) \ |
168 | {if (cec_msg_dbg_en && cec_dev->dbg_dev) \ |
169 | dev_info(cec_dev->dbg_dev, format, ##args); \ |
170 | } |
171 | |
172 | #define CEC_INFO_L(level, format, args...) \ |
173 | {if ((cec_msg_dbg_en >= level) && cec_dev->dbg_dev) \ |
174 | dev_info(cec_dev->dbg_dev, format, ##args); \ |
175 | } |
176 | |
177 | static unsigned char msg_log_buf[128] = { 0 }; |
178 | |
179 | #define waiting_aocec_free(r) \ |
180 | do {\ |
181 | unsigned long cnt = 0;\ |
182 | while (readl(cec_dev->cec_reg + r) & (1<<23)) {\ |
183 | if (cnt++ == 3500) { \ |
184 | pr_info("waiting aocec %x free time out\n", r);\ |
185 | cec_hw_reset();\ |
186 | break;\ |
187 | } \ |
188 | } \ |
189 | } while (0) |
190 | |
191 | static void cec_set_reg_bits(unsigned int addr, unsigned int value, |
192 | unsigned int offset, unsigned int len) |
193 | { |
194 | unsigned int data32 = 0; |
195 | |
196 | data32 = readl(cec_dev->cec_reg + addr); |
197 | data32 &= ~(((1 << len) - 1) << offset); |
198 | data32 |= (value & ((1 << len) - 1)) << offset; |
199 | writel(data32, cec_dev->cec_reg + addr); |
200 | } |
201 | |
202 | unsigned int aocec_rd_reg(unsigned long addr) |
203 | { |
204 | unsigned int data32; |
205 | unsigned long flags; |
206 | |
207 | spin_lock_irqsave(&cec_dev->cec_reg_lock, flags); |
208 | waiting_aocec_free(AO_CEC_RW_REG); |
209 | data32 = 0; |
210 | data32 |= 0 << 16; /* [16] cec_reg_wr */ |
211 | data32 |= 0 << 8; /* [15:8] cec_reg_wrdata */ |
212 | data32 |= addr << 0; /* [7:0] cec_reg_addr */ |
213 | writel(data32, cec_dev->cec_reg + AO_CEC_RW_REG); |
214 | |
215 | waiting_aocec_free(AO_CEC_RW_REG); |
216 | data32 = ((readl(cec_dev->cec_reg + AO_CEC_RW_REG)) >> 24) & 0xff; |
217 | spin_unlock_irqrestore(&cec_dev->cec_reg_lock, flags); |
218 | return data32; |
219 | } /* aocec_rd_reg */ |
220 | |
221 | void aocec_wr_reg(unsigned long addr, unsigned long data) |
222 | { |
223 | unsigned long data32; |
224 | unsigned long flags; |
225 | |
226 | spin_lock_irqsave(&cec_dev->cec_reg_lock, flags); |
227 | waiting_aocec_free(AO_CEC_RW_REG); |
228 | data32 = 0; |
229 | data32 |= 1 << 16; /* [16] cec_reg_wr */ |
230 | data32 |= data << 8; /* [15:8] cec_reg_wrdata */ |
231 | data32 |= addr << 0; /* [7:0] cec_reg_addr */ |
232 | writel(data32, cec_dev->cec_reg + AO_CEC_RW_REG); |
233 | spin_unlock_irqrestore(&cec_dev->cec_reg_lock, flags); |
234 | } /* aocec_wr_only_reg */ |
235 | |
236 | /*------------for AO_CECB------------------*/ |
237 | static unsigned int aocecb_rd_reg(unsigned long addr) |
238 | { |
239 | unsigned int data32; |
240 | unsigned long flags; |
241 | |
242 | spin_lock_irqsave(&cec_dev->cec_reg_lock, flags); |
243 | data32 = 0; |
244 | data32 |= 0 << 16; /* [16] cec_reg_wr */ |
245 | data32 |= 0 << 8; /* [15:8] cec_reg_wrdata */ |
246 | data32 |= addr << 0; /* [7:0] cec_reg_addr */ |
247 | writel(data32, cec_dev->cec_reg + AO_CECB_RW_REG); |
248 | |
249 | data32 = ((readl(cec_dev->cec_reg + AO_CECB_RW_REG)) >> 24) & 0xff; |
250 | spin_unlock_irqrestore(&cec_dev->cec_reg_lock, flags); |
251 | return data32; |
252 | } /* aocecb_rd_reg */ |
253 | |
254 | static void aocecb_wr_reg(unsigned long addr, unsigned long data) |
255 | { |
256 | unsigned long data32; |
257 | unsigned long flags; |
258 | |
259 | spin_lock_irqsave(&cec_dev->cec_reg_lock, flags); |
260 | data32 = 0; |
261 | data32 |= 1 << 16; /* [16] cec_reg_wr */ |
262 | data32 |= data << 8; /* [15:8] cec_reg_wrdata */ |
263 | data32 |= addr << 0; /* [7:0] cec_reg_addr */ |
264 | writel(data32, cec_dev->cec_reg + AO_CECB_RW_REG); |
265 | spin_unlock_irqrestore(&cec_dev->cec_reg_lock, flags); |
266 | } /* aocecb_wr_only_reg */ |
267 | |
268 | /*----------------- low level for EE cec rx/tx support ----------------*/ |
269 | static inline void hdmirx_set_bits_top(uint32_t reg, uint32_t bits, |
270 | uint32_t start, uint32_t len) |
271 | { |
272 | unsigned int tmp; |
273 | |
274 | tmp = hdmirx_rd_top(reg); |
275 | tmp &= ~(((1 << len) - 1) << start); |
276 | tmp |= (bits << start); |
277 | hdmirx_wr_top(reg, tmp); |
278 | } |
279 | |
280 | static unsigned int hdmirx_cec_read(unsigned int reg) |
281 | { |
282 | /* |
283 | * TXLX has moved ee cec to ao domain |
284 | */ |
285 | if (reg >= DWC_CEC_CTRL && cec_dev->plat_data->ee_to_ao) |
286 | return aocecb_rd_reg((reg - DWC_CEC_CTRL) / 4); |
287 | else |
288 | return hdmirx_rd_dwc(reg); |
289 | } |
290 | |
291 | /*only for ee cec*/ |
292 | static void hdmirx_cec_write(unsigned int reg, unsigned int value) |
293 | { |
294 | /* |
295 | * TXLX has moved ee cec to ao domain |
296 | */ |
297 | if (reg >= DWC_CEC_CTRL && cec_dev->plat_data->ee_to_ao) |
298 | aocecb_wr_reg((reg - DWC_CEC_CTRL) / 4, value); |
299 | else |
300 | hdmirx_wr_dwc(reg, value); |
301 | } |
302 | |
303 | static inline void hdmirx_set_bits_dwc(uint32_t reg, uint32_t bits, |
304 | uint32_t start, uint32_t len) |
305 | { |
306 | unsigned int tmp; |
307 | |
308 | tmp = hdmirx_cec_read(reg); |
309 | tmp &= ~(((1 << len) - 1) << start); |
310 | tmp |= (bits << start); |
311 | hdmirx_cec_write(reg, tmp); |
312 | } |
313 | |
314 | void cec_dbg_init(void) |
315 | { |
316 | stdbgflg.hal_cmd_bypass = 0; |
317 | } |
318 | |
319 | void cecb_hw_reset(void) |
320 | { |
321 | /* cec disable */ |
322 | if (!cec_dev->plat_data->ee_to_ao) |
323 | hdmirx_set_bits_dwc(DWC_DMI_DISABLE_IF, 0, 5, 1); |
324 | else |
325 | cec_set_reg_bits(AO_CECB_GEN_CNTL, 0, 0, 1); |
326 | udelay(500); |
327 | } |
328 | |
329 | static void cecrx_check_irq_enable(void) |
330 | { |
331 | unsigned int reg32; |
332 | |
333 | /* irq on chip txlx has sperate from EE cec, no need check */ |
334 | if (cec_dev->plat_data->ee_to_ao) |
335 | return; |
336 | |
337 | reg32 = hdmirx_cec_read(DWC_AUD_CEC_IEN); |
338 | if ((reg32 & EE_CEC_IRQ_EN_MASK) != EE_CEC_IRQ_EN_MASK) { |
339 | CEC_INFO("irq_en is wrong:%x, checker:%pf\n", |
340 | reg32, (void *)_RET_IP_); |
341 | hdmirx_cec_write(DWC_AUD_CEC_IEN_SET, EE_CEC_IRQ_EN_MASK); |
342 | } |
343 | } |
344 | |
345 | static int cecb_trigle_tx(const unsigned char *msg, unsigned char len) |
346 | { |
347 | int i = 0, size = 0; |
348 | int lock; |
349 | |
350 | cecrx_check_irq_enable(); |
351 | while (1) { |
352 | /* send is in process */ |
353 | lock = hdmirx_cec_read(DWC_CEC_LOCK); |
354 | if (lock) { |
355 | CEC_ERR("recevie msg in tx\n"); |
356 | cecb_irq_handle(); |
357 | return -1; |
358 | } |
359 | if (hdmirx_cec_read(DWC_CEC_CTRL) & 0x01) |
360 | i++; |
361 | else |
362 | break; |
363 | if (i > 25) { |
364 | CEC_ERR("waiting busy timeout\n"); |
365 | return -1; |
366 | } |
367 | msleep(20); |
368 | } |
369 | size += sprintf(msg_log_buf + size, "CEC tx msg len %d:", len); |
370 | for (i = 0; i < len; i++) { |
371 | hdmirx_cec_write(DWC_CEC_TX_DATA0 + i * 4, msg[i]); |
372 | size += sprintf(msg_log_buf + size, " %02x", msg[i]); |
373 | } |
374 | msg_log_buf[size] = '\0'; |
375 | CEC_INFO("%s\n", msg_log_buf); |
376 | /* start send */ |
377 | hdmirx_cec_write(DWC_CEC_TX_CNT, len); |
378 | hdmirx_set_bits_dwc(DWC_CEC_CTRL, 3, 0, 3); |
379 | return 0; |
380 | } |
381 | |
382 | int cec_has_irq(void) |
383 | { |
384 | unsigned int intr_cec; |
385 | |
386 | if (!cec_dev->plat_data->ee_to_ao) { |
387 | intr_cec = hdmirx_cec_read(DWC_AUD_CEC_ISTS); |
388 | intr_cec &= EE_CEC_IRQ_EN_MASK; |
389 | } else { |
390 | intr_cec = readl(cec_dev->cec_reg + AO_CECB_INTR_STAT); |
391 | intr_cec &= CECB_IRQ_EN_MASK; |
392 | } |
393 | return intr_cec; |
394 | } |
395 | |
396 | static inline void cecrx_clear_irq(unsigned int flags) |
397 | { |
398 | if (!cec_dev->plat_data->ee_to_ao) |
399 | hdmirx_cec_write(DWC_AUD_CEC_ICLR, flags); |
400 | else |
401 | writel(flags, cec_dev->cec_reg + AO_CECB_INTR_CLR); |
402 | } |
403 | |
404 | static int cecb_pick_msg(unsigned char *msg, unsigned char *out_len) |
405 | { |
406 | int i, size; |
407 | int len; |
408 | struct delayed_work *dwork; |
409 | |
410 | dwork = &cec_dev->cec_work; |
411 | |
412 | len = hdmirx_cec_read(DWC_CEC_RX_CNT); |
413 | size = sprintf(msg_log_buf, "CEC RX len %d:", len); |
414 | for (i = 0; i < len; i++) { |
415 | msg[i] = hdmirx_cec_read(DWC_CEC_RX_DATA0 + i * 4); |
416 | size += sprintf(msg_log_buf + size, " %02x", msg[i]); |
417 | } |
418 | size += sprintf(msg_log_buf + size, "\n"); |
419 | msg_log_buf[size] = '\0'; |
420 | /* clr CEC lock bit */ |
421 | hdmirx_cec_write(DWC_CEC_LOCK, 0); |
422 | mod_delayed_work(cec_dev->cec_thread, dwork, 0); |
423 | CEC_INFO("%s", msg_log_buf); |
424 | if (((msg[0] & 0xf0) >> 4) == cec_dev->cec_info.log_addr) { |
425 | *out_len = 0; |
426 | CEC_ERR("bad iniator with self:%s", msg_log_buf); |
427 | } else |
428 | *out_len = len; |
429 | pin_status = 1; |
430 | return 0; |
431 | } |
432 | |
433 | void cecb_irq_handle(void) |
434 | { |
435 | uint32_t intr_cec; |
436 | uint32_t lock; |
437 | int shift = 0; |
438 | |
439 | intr_cec = cec_has_irq(); |
440 | |
441 | /* clear irq */ |
442 | if (intr_cec != 0) |
443 | cecrx_clear_irq(intr_cec); |
444 | |
445 | if (!ee_cec) |
446 | return; |
447 | if (cec_dev->plat_data->ee_to_ao) |
448 | shift = 16; |
449 | /* TX DONE irq, increase tx buffer pointer */ |
450 | if (intr_cec & CEC_IRQ_TX_DONE) { |
451 | cec_tx_result = CEC_FAIL_NONE; |
452 | complete(&cec_dev->tx_ok); |
453 | } |
454 | lock = hdmirx_cec_read(DWC_CEC_LOCK); |
455 | /* EOM irq, message is coming */ |
456 | if ((intr_cec & CEC_IRQ_RX_EOM) || lock) { |
457 | cecb_pick_msg(rx_msg, &rx_len); |
458 | complete(&cec_dev->rx_ok); |
459 | } |
460 | |
461 | /* TX error irq flags */ |
462 | if ((intr_cec & CEC_IRQ_TX_NACK) || |
463 | (intr_cec & CEC_IRQ_TX_ARB_LOST) || |
464 | (intr_cec & CEC_IRQ_TX_ERR_INITIATOR)) { |
465 | if (intr_cec & CEC_IRQ_TX_NACK) { |
466 | cec_tx_result = CEC_FAIL_NACK; |
467 | CEC_INFO_L(L_2, "warning:TX_NACK\n"); |
468 | } else if (intr_cec & CEC_IRQ_TX_ARB_LOST) { |
469 | cec_tx_result = CEC_FAIL_BUSY; |
470 | /* clear start */ |
471 | hdmirx_cec_write(DWC_CEC_TX_CNT, 0); |
472 | hdmirx_set_bits_dwc(DWC_CEC_CTRL, 0, 0, 3); |
473 | CEC_ERR("warning:ARB_LOST\n"); |
474 | } else if (intr_cec & CEC_IRQ_TX_ERR_INITIATOR) { |
475 | CEC_ERR("warning:INITIATOR\n"); |
476 | cec_tx_result = CEC_FAIL_OTHER; |
477 | } else |
478 | cec_tx_result = CEC_FAIL_OTHER; |
479 | complete(&cec_dev->tx_ok); |
480 | } |
481 | |
482 | /* RX error irq flag */ |
483 | if (intr_cec & CEC_IRQ_RX_ERR_FOLLOWER) { |
484 | CEC_ERR("warning:FOLLOWER\n"); |
485 | hdmirx_cec_write(DWC_CEC_LOCK, 0); |
486 | /* TODO: need reset cec hw logic? */ |
487 | } |
488 | |
489 | /* wakeup op code will triger this int*/ |
490 | if (intr_cec & CEC_IRQ_RX_WAKEUP) { |
491 | CEC_ERR("warning:RX_WAKEUP\n"); |
492 | hdmirx_cec_write(DWC_CEC_WKUPCTRL, WAKEUP_EN_MASK); |
493 | /* TODO: wake up system if needed */ |
494 | } |
495 | } |
496 | |
497 | static irqreturn_t cecb_isr(int irq, void *dev_instance) |
498 | { |
499 | cecb_irq_handle(); |
500 | return IRQ_HANDLED; |
501 | } |
502 | |
503 | static void ao_cecb_init(void) |
504 | { |
505 | unsigned long data32; |
506 | unsigned int reg; |
507 | |
508 | cecb_hw_reset(); |
509 | |
510 | if (!cec_dev->plat_data->ee_to_ao) { |
511 | /* set cec clk 32768k */ |
512 | data32 = readl(cec_dev->hhi_reg + HHI_32K_CLK_CNTL); |
513 | data32 = 0; |
514 | /* |
515 | * [17:16] clk_sel: 0=oscin; 1=slow_oscin; |
516 | * 2=fclk_div3; 3=fclk_div5. |
517 | */ |
518 | data32 |= 0 << 16; |
519 | /* [ 15] clk_en */ |
520 | data32 |= 1 << 15; |
521 | /* [13: 0] clk_div */ |
522 | data32 |= (732-1) << 0; |
523 | writel(data32, cec_dev->hhi_reg + HHI_32K_CLK_CNTL); |
524 | hdmirx_wr_top(TOP_EDID_ADDR_CEC, EDID_CEC_ID_ADDR); |
525 | |
526 | /* hdmirx_cecclk_en */ |
527 | hdmirx_set_bits_top(TOP_CLK_CNTL, 1, 2, 1); |
528 | hdmirx_set_bits_top(TOP_EDID_GEN_CNTL, EDID_AUTO_CEC_EN, 11, 1); |
529 | |
530 | /* enable all cec irq */ |
531 | cec_irq_enable(true); |
532 | /* clear all wake up source */ |
533 | hdmirx_cec_write(DWC_CEC_WKUPCTRL, 0); |
534 | /* cec enable */ |
535 | hdmirx_set_bits_dwc(DWC_DMI_DISABLE_IF, 1, 5, 1); |
536 | } else { |
537 | reg = (0 << 31) | |
538 | (0 << 30) | |
539 | (1 << 28) | /* clk_div0/clk_div1 in turn */ |
540 | ((732-1) << 12) |/* Div_tcnt1 */ |
541 | ((733-1) << 0); /* Div_tcnt0 */ |
542 | writel(reg, cec_dev->cec_reg + AO_CECB_CLK_CNTL_REG0); |
543 | reg = (0 << 13) | |
544 | ((11-1) << 12) | |
545 | ((8-1) << 0); |
546 | writel(reg, cec_dev->cec_reg + AO_CECB_CLK_CNTL_REG1); |
547 | |
548 | reg = readl(cec_dev->cec_reg + AO_CECB_CLK_CNTL_REG0); |
549 | reg |= (1 << 31); |
550 | writel(reg, cec_dev->cec_reg + AO_CECB_CLK_CNTL_REG0); |
551 | |
552 | udelay(200); |
553 | reg |= (1 << 30); |
554 | writel(reg, cec_dev->cec_reg + AO_CECB_CLK_CNTL_REG0); |
555 | |
556 | reg = readl(cec_dev->cec_reg + AO_RTI_PWR_CNTL_REG0); |
557 | reg |= (0x01 << 14); /* xtal gate */ |
558 | writel(reg, cec_dev->cec_reg + AO_RTI_PWR_CNTL_REG0); |
559 | |
560 | data32 = 0; |
561 | data32 |= (7 << 12); /* filter_del */ |
562 | data32 |= (1 << 8); /* filter_tick: 1us */ |
563 | data32 |= (1 << 3); /* enable system clock */ |
564 | data32 |= 0 << 1; /* [2:1] cntl_clk: */ |
565 | /* 0=Disable clk (Power-off mode); */ |
566 | /* 1=Enable gated clock (Normal mode); */ |
567 | /* 2=Enable free-run clk (Debug mode). */ |
568 | data32 |= 1 << 0; /* [0] sw_reset: 1=Reset */ |
569 | writel(data32, cec_dev->cec_reg + AO_CECB_GEN_CNTL); |
570 | /* Enable gated clock (Normal mode). */ |
571 | cec_set_reg_bits(AO_CECB_GEN_CNTL, 1, 1, 1); |
572 | /* Release SW reset */ |
573 | cec_set_reg_bits(AO_CECB_GEN_CNTL, 0, 0, 1); |
574 | |
575 | /* Enable all AO_CECB interrupt sources */ |
576 | cec_irq_enable(true); |
577 | hdmirx_cec_write(DWC_CEC_WKUPCTRL, WAKEUP_EN_MASK); |
578 | } |
579 | } |
580 | |
581 | void eecec_irq_enable(bool enable) |
582 | { |
583 | if (cec_dev->cpu_type < MESON_CPU_MAJOR_ID_TXLX) { |
584 | if (enable) |
585 | hdmirx_cec_write(DWC_AUD_CEC_IEN_SET, |
586 | EE_CEC_IRQ_EN_MASK); |
587 | else { |
588 | hdmirx_cec_write(DWC_AUD_CEC_ICLR, |
589 | (~(hdmirx_cec_read(DWC_AUD_CEC_IEN)) | |
590 | EE_CEC_IRQ_EN_MASK)); |
591 | hdmirx_cec_write(DWC_AUD_CEC_IEN_SET, |
592 | hdmirx_cec_read(DWC_AUD_CEC_IEN) & |
593 | ~EE_CEC_IRQ_EN_MASK); |
594 | hdmirx_cec_write(DWC_AUD_CEC_IEN_CLR, |
595 | (~(hdmirx_cec_read(DWC_AUD_CEC_IEN)) | |
596 | EE_CEC_IRQ_EN_MASK)); |
597 | } |
598 | CEC_INFO("ee enable:int mask:0x%x\n", |
599 | hdmirx_cec_read(DWC_AUD_CEC_IEN)); |
600 | } else { |
601 | if (enable) |
602 | writel(CECB_IRQ_EN_MASK, |
603 | cec_dev->cec_reg + AO_CECB_INTR_MASKN); |
604 | else |
605 | writel(readl(cec_dev->cec_reg + AO_CECB_INTR_MASKN) |
606 | & ~CECB_IRQ_EN_MASK, |
607 | cec_dev->cec_reg + AO_CECB_INTR_MASKN); |
608 | CEC_INFO("ao enable:int mask:0x%x\n", |
609 | readl(cec_dev->cec_reg + AO_CECB_INTR_MASKN)); |
610 | } |
611 | } |
612 | |
613 | void cec_irq_enable(bool enable) |
614 | { |
615 | if (ee_cec) |
616 | eecec_irq_enable(enable); |
617 | else |
618 | aocec_irq_enable(enable); |
619 | } |
620 | /* |
621 | int cecrx_hw_init(void) |
622 | { |
623 | unsigned int data32; |
624 | |
625 | if (!ee_cec) |
626 | return -1; |
627 | |
628 | cecb_hw_reset(); |
629 | |
630 | ao_cecb_init(); |
631 | |
632 | cec_logicaddr_set(cec_dev->cec_info.log_addr); |
633 | return 0; |
634 | } |
635 | */ |
636 | static int dump_cecrx_reg(char *b) |
637 | { |
638 | int i = 0, s = 0; |
639 | unsigned char reg; |
640 | unsigned int reg32; |
641 | |
642 | if (!cec_dev->plat_data->ee_to_ao) { |
643 | reg32 = readl(cec_dev->hhi_reg + HHI_32K_CLK_CNTL); |
644 | s += sprintf(b + s, "HHI_32K_CLK_CNTL: 0x%08x\n", reg32); |
645 | reg32 = hdmirx_rd_top(TOP_EDID_ADDR_CEC); |
646 | s += sprintf(b + s, "TOP_EDID_ADDR_CEC: 0x%08x\n", reg32); |
647 | reg32 = hdmirx_rd_top(TOP_EDID_GEN_CNTL); |
648 | s += sprintf(b + s, "TOP_EDID_GEN_CNTL: 0x%08x\n", reg32); |
649 | reg32 = hdmirx_cec_read(DWC_AUD_CEC_IEN); |
650 | s += sprintf(b + s, "DWC_AUD_CEC_IEN: 0x%08x\n", reg32); |
651 | reg32 = hdmirx_cec_read(DWC_AUD_CEC_ISTS); |
652 | s += sprintf(b + s, "DWC_AUD_CEC_ISTS: 0x%08x\n", reg32); |
653 | reg32 = hdmirx_cec_read(DWC_DMI_DISABLE_IF); |
654 | s += sprintf(b + s, "DWC_DMI_DISABLE_IF: 0x%08x\n", reg32); |
655 | reg32 = hdmirx_rd_top(TOP_CLK_CNTL); |
656 | s += sprintf(b + s, "TOP_CLK_CNTL: 0x%08x\n", reg32); |
657 | } else { |
658 | reg32 = readl(cec_dev->cec_reg + AO_CECB_CLK_CNTL_REG0); |
659 | s += sprintf(b + s, "AO_CECB_CLK_CNTL_REG0: 0x%08x\n", reg32); |
660 | reg32 = readl(cec_dev->cec_reg + AO_CECB_CLK_CNTL_REG1); |
661 | s += sprintf(b + s, "AO_CECB_CLK_CNTL_REG1: 0x%08x\n", reg32); |
662 | reg32 = readl(cec_dev->cec_reg + AO_CECB_GEN_CNTL); |
663 | s += sprintf(b + s, "AO_CECB_GEN_CNTL: 0x%08x\n", reg32); |
664 | reg32 = readl(cec_dev->cec_reg + AO_CECB_RW_REG); |
665 | s += sprintf(b + s, "AO_CECB_RW_REG: 0x%08x\n", reg32); |
666 | reg32 = readl(cec_dev->cec_reg + AO_CECB_INTR_MASKN); |
667 | s += sprintf(b + s, "AO_CECB_INTR_MASKN: 0x%08x\n", reg32); |
668 | reg32 = readl(cec_dev->cec_reg + AO_CECB_INTR_STAT); |
669 | s += sprintf(b + s, "AO_CECB_INTR_STAT: 0x%08x\n", reg32); |
670 | } |
671 | |
672 | s += sprintf(b + s, "CEC MODULE REGS:\n"); |
673 | s += sprintf(b + s, "CEC_CTRL = 0x%02x\n", hdmirx_cec_read(0x1f00)); |
674 | s += sprintf(b + s, "CEC_MASK = 0x%02x\n", hdmirx_cec_read(0x1f08)); |
675 | s += sprintf(b + s, "CEC_ADDR_L = 0x%02x\n", hdmirx_cec_read(0x1f14)); |
676 | s += sprintf(b + s, "CEC_ADDR_H = 0x%02x\n", hdmirx_cec_read(0x1f18)); |
677 | s += sprintf(b + s, "CEC_TX_CNT = 0x%02x\n", hdmirx_cec_read(0x1f1c)); |
678 | s += sprintf(b + s, "CEC_RX_CNT = 0x%02x\n", hdmirx_cec_read(0x1f20)); |
679 | s += sprintf(b + s, "CEC_LOCK = 0x%02x\n", hdmirx_cec_read(0x1fc0)); |
680 | s += sprintf(b + s, "CEC_WKUPCTRL = 0x%02x\n", hdmirx_cec_read(0x1fc4)); |
681 | |
682 | s += sprintf(b + s, "%s", "RX buffer:"); |
683 | for (i = 0; i < 16; i++) { |
684 | reg = (hdmirx_cec_read(0x1f80 + i * 4) & 0xff); |
685 | s += sprintf(b + s, " %02x", reg); |
686 | } |
687 | s += sprintf(b + s, "\n"); |
688 | |
689 | s += sprintf(b + s, "%s", "TX buffer:"); |
690 | for (i = 0; i < 16; i++) { |
691 | reg = (hdmirx_cec_read(0x1f40 + i * 4) & 0xff); |
692 | s += sprintf(b + s, " %02x", reg); |
693 | } |
694 | s += sprintf(b + s, "\n"); |
695 | return s; |
696 | } |
697 | |
698 | /*--------------------- END of EE CEC --------------------*/ |
699 | |
700 | void aocec_irq_enable(bool enable) |
701 | { |
702 | if (enable) |
703 | cec_set_reg_bits(AO_CEC_INTR_MASKN, 0x6, 0, 3); |
704 | else |
705 | cec_set_reg_bits(AO_CEC_INTR_MASKN, 0x0, 0, 3); |
706 | CEC_INFO("ao enable:int mask:0x%x\n", |
707 | readl(cec_dev->cec_reg + AO_CEC_INTR_MASKN)); |
708 | } |
709 | |
710 | static void cec_hw_buf_clear(void) |
711 | { |
712 | aocec_wr_reg(CEC_RX_MSG_CMD, RX_DISABLE); |
713 | aocec_wr_reg(CEC_TX_MSG_CMD, TX_ABORT); |
714 | aocec_wr_reg(CEC_RX_CLEAR_BUF, 1); |
715 | aocec_wr_reg(CEC_TX_CLEAR_BUF, 1); |
716 | udelay(100); |
717 | aocec_wr_reg(CEC_RX_CLEAR_BUF, 0); |
718 | aocec_wr_reg(CEC_TX_CLEAR_BUF, 0); |
719 | udelay(100); |
720 | aocec_wr_reg(CEC_RX_MSG_CMD, RX_NO_OP); |
721 | aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP); |
722 | } |
723 | |
724 | void cec_logicaddr_set(int l_add) |
725 | { |
726 | /* save logical address for suspend/wake up */ |
727 | cec_set_reg_bits(AO_DEBUG_REG1, l_add, 16, 4); |
728 | cec_dev->cec_info.addr_enable = (1 << l_add); |
729 | if (ee_cec) { |
730 | /* set ee_cec logical addr */ |
731 | if (l_add < 8) |
732 | hdmirx_cec_write(DWC_CEC_ADDR_L, 1 << l_add); |
733 | else |
734 | hdmirx_cec_write(DWC_CEC_ADDR_H, 1 << (l_add - 8)|0x80); |
735 | |
736 | CEC_INFO("set cecb logical addr:0x%x\n", l_add); |
737 | } else { |
738 | /*clear all logical address*/ |
739 | aocec_wr_reg(CEC_LOGICAL_ADDR0, 0); |
740 | aocec_wr_reg(CEC_LOGICAL_ADDR1, 0); |
741 | aocec_wr_reg(CEC_LOGICAL_ADDR2, 0); |
742 | aocec_wr_reg(CEC_LOGICAL_ADDR3, 0); |
743 | aocec_wr_reg(CEC_LOGICAL_ADDR4, 0); |
744 | |
745 | cec_hw_buf_clear(); |
746 | aocec_wr_reg(CEC_LOGICAL_ADDR0, (l_add & 0xf)); |
747 | udelay(100); |
748 | aocec_wr_reg(CEC_LOGICAL_ADDR0, (0x1 << 4) | (l_add & 0xf)); |
749 | if (cec_msg_dbg_en) |
750 | CEC_INFO("set cec alogical addr:0x%x\n", |
751 | aocec_rd_reg(CEC_LOGICAL_ADDR0)); |
752 | } |
753 | } |
754 | |
755 | void ceca_addr_add(unsigned int l_add) |
756 | { |
757 | unsigned int addr; |
758 | unsigned int i; |
759 | |
760 | /* check if the logical addr is exist ? */ |
761 | for (i = CEC_LOGICAL_ADDR0; i <= CEC_LOGICAL_ADDR4; i++) { |
762 | addr = aocec_rd_reg(i); |
763 | if ((addr & 0xf) == (l_add & 0xf)) { |
764 | CEC_INFO("add 0x%x exist\n", l_add); |
765 | return; |
766 | } |
767 | } |
768 | |
769 | /* find a empty place */ |
770 | for (i = CEC_LOGICAL_ADDR0; i <= CEC_LOGICAL_ADDR4; i++) { |
771 | addr = aocec_rd_reg(i); |
772 | if (addr & 0x10) { |
773 | CEC_INFO(" skip 0x%x ,val=0x%x\n", i, addr); |
774 | continue; |
775 | } else { |
776 | cec_hw_buf_clear(); |
777 | aocec_wr_reg(i, (l_add & 0xf)); |
778 | udelay(100); |
779 | aocec_wr_reg(i, (l_add & 0xf)|0x10); |
780 | CEC_INFO("cec a add addr %d at 0x%x\n", |
781 | l_add, i); |
782 | break; |
783 | } |
784 | } |
785 | } |
786 | |
787 | void cecb_addr_add(unsigned int l_add) |
788 | { |
789 | unsigned int addr; |
790 | |
791 | if (l_add < 8) { |
792 | addr = hdmirx_cec_read(DWC_CEC_ADDR_L); |
793 | addr |= (1 << l_add); |
794 | hdmirx_cec_write(DWC_CEC_ADDR_L, addr); |
795 | } else { |
796 | addr = hdmirx_cec_read(DWC_CEC_ADDR_H); |
797 | addr |= (1 << (l_add - 8))|0x80; |
798 | hdmirx_cec_write(DWC_CEC_ADDR_H, addr); |
799 | } |
800 | CEC_INFO("cec b add addr %d\n", l_add); |
801 | } |
802 | |
803 | void cec_logicaddr_add(unsigned int cec_sel, unsigned int l_add) |
804 | { |
805 | if (cec_sel) |
806 | cecb_addr_add(l_add); |
807 | else |
808 | ceca_addr_add(l_add); |
809 | } |
810 | |
811 | void cec_logicaddr_remove(unsigned int l_add) |
812 | { |
813 | unsigned int addr; |
814 | unsigned int i; |
815 | |
816 | if (ee_cec) { |
817 | if (l_add < 8) { |
818 | addr = hdmirx_cec_read(DWC_CEC_ADDR_L); |
819 | addr &= ~(1 << l_add); |
820 | hdmirx_cec_write(DWC_CEC_ADDR_L, addr); |
821 | } else { |
822 | addr = hdmirx_cec_read(DWC_CEC_ADDR_H); |
823 | addr &= ~(1 << (l_add - 8)); |
824 | hdmirx_cec_write(DWC_CEC_ADDR_H, addr); |
825 | } |
826 | CEC_INFO("cec b remove addr %d\n", l_add); |
827 | } else { |
828 | for (i = CEC_LOGICAL_ADDR0; i <= CEC_LOGICAL_ADDR4; i++) { |
829 | addr = aocec_rd_reg(i); |
830 | if ((addr & 0xf) == (l_add & 0xf)) { |
831 | aocec_wr_reg(i, (addr & 0xf)); |
832 | udelay(100); |
833 | aocec_wr_reg(i, 0); |
834 | cec_hw_buf_clear(); |
835 | CEC_INFO("cec a rm addr %d at 0x%x\n", |
836 | l_add, i); |
837 | } |
838 | } |
839 | } |
840 | } |
841 | |
842 | void cec_restore_logical_addr(unsigned int addr_en) |
843 | { |
844 | unsigned int i; |
845 | unsigned int addr_enable = addr_en; |
846 | |
847 | cec_clear_all_logical_addr(ee_cec); |
848 | for (i = 0; i < 15; i++) { |
849 | if (addr_enable & 0x1) |
850 | cec_logicaddr_add(ee_cec, i); |
851 | |
852 | addr_enable = addr_enable >> 1; |
853 | } |
854 | } |
855 | |
856 | void cec_hw_reset(void) |
857 | { |
858 | if (ee_cec) { |
859 | ao_cecb_init(); |
860 | /* cec_logicaddr_set(cec_dev->cec_info.log_addr); */ |
861 | } else { |
862 | writel(0x1, cec_dev->cec_reg + AO_CEC_GEN_CNTL); |
863 | /* Enable gated clock (Normal mode). */ |
864 | cec_set_reg_bits(AO_CEC_GEN_CNTL, 1, 1, 1); |
865 | /* Release SW reset */ |
866 | udelay(100); |
867 | cec_set_reg_bits(AO_CEC_GEN_CNTL, 0, 0, 1); |
868 | |
869 | /* Enable all AO_CEC interrupt sources */ |
870 | cec_irq_enable(true); |
871 | |
872 | /* cec_logicaddr_set(cec_dev->cec_info.log_addr); */ |
873 | |
874 | /* Cec arbitration 3/5/7 bit time set. */ |
875 | cec_arbit_bit_time_set(3, 0x118, 0); |
876 | cec_arbit_bit_time_set(5, 0x000, 0); |
877 | cec_arbit_bit_time_set(7, 0x2aa, 0); |
878 | } |
879 | /* cec_logicaddr_set(cec_dev->cec_info.log_addr); */ |
880 | cec_restore_logical_addr(cec_dev->cec_info.addr_enable); |
881 | } |
882 | |
883 | void cec_rx_buf_clear(void) |
884 | { |
885 | aocec_wr_reg(CEC_RX_CLEAR_BUF, 0x1); |
886 | aocec_wr_reg(CEC_RX_CLEAR_BUF, 0x0); |
887 | } |
888 | |
889 | static inline bool is_poll_message(unsigned char header) |
890 | { |
891 | unsigned char initiator, follower; |
892 | |
893 | initiator = (header >> 4) & 0xf; |
894 | follower = (header) & 0xf; |
895 | return initiator == follower; |
896 | } |
897 | |
898 | static inline bool is_feature_abort_msg(const unsigned char *msg, int len) |
899 | { |
900 | if (!msg || len < 2) |
901 | return false; |
902 | if (msg[1] == CEC_OC_FEATURE_ABORT) |
903 | return true; |
904 | return false; |
905 | } |
906 | |
907 | static inline bool is_report_phy_addr_msg(const unsigned char *msg, int len) |
908 | { |
909 | if (!msg || len < 4) |
910 | return false; |
911 | if (msg[1] == CEC_OC_REPORT_PHYSICAL_ADDRESS) |
912 | return true; |
913 | return false; |
914 | } |
915 | |
916 | static bool need_nack_repeat_msg(const unsigned char *msg, int len, int t) |
917 | { |
918 | if (len == last_cec_msg->len && |
919 | (is_poll_message(msg[0]) || is_feature_abort_msg(msg, len) || |
920 | is_report_phy_addr_msg(msg, len)) && |
921 | last_cec_msg->last_result == CEC_FAIL_NACK && |
922 | jiffies - last_cec_msg->last_jiffies < t) { |
923 | return true; |
924 | } |
925 | return false; |
926 | } |
927 | |
928 | void cec_clear_all_logical_addr(unsigned int cec_sel) |
929 | { |
930 | CEC_INFO("clear all logical addr\n"); |
931 | |
932 | if (cec_sel) { |
933 | hdmirx_cec_write(DWC_CEC_ADDR_L, 0); |
934 | hdmirx_cec_write(DWC_CEC_ADDR_H, 0x80); |
935 | } else { |
936 | aocec_wr_reg(CEC_LOGICAL_ADDR0, 0); |
937 | aocec_wr_reg(CEC_LOGICAL_ADDR1, 0); |
938 | aocec_wr_reg(CEC_LOGICAL_ADDR2, 0); |
939 | aocec_wr_reg(CEC_LOGICAL_ADDR3, 0); |
940 | aocec_wr_reg(CEC_LOGICAL_ADDR4, 0); |
941 | } |
942 | /*udelay(100);*/ |
943 | } |
944 | |
945 | void cec_enable_arc_pin(bool enable) |
946 | { |
947 | /* select arc according arg */ |
948 | if (enable) |
949 | hdmirx_wr_top(TOP_ARCTX_CNTL, 0x01); |
950 | else |
951 | hdmirx_wr_top(TOP_ARCTX_CNTL, 0x00); |
952 | CEC_INFO("set arc en:%d, reg:%lx\n", |
953 | enable, hdmirx_rd_top(TOP_ARCTX_CNTL)); |
954 | } |
955 | EXPORT_SYMBOL(cec_enable_arc_pin); |
956 | |
957 | int cec_rx_buf_check(void) |
958 | { |
959 | unsigned int rx_num_msg; |
960 | |
961 | if (ee_cec) { |
962 | cecrx_check_irq_enable(); |
963 | cecb_irq_handle(); |
964 | return 0; |
965 | } |
966 | |
967 | rx_num_msg = aocec_rd_reg(CEC_RX_NUM_MSG); |
968 | if (rx_num_msg) |
969 | CEC_INFO("rx msg num:0x%02x\n", rx_num_msg); |
970 | |
971 | return rx_num_msg; |
972 | } |
973 | |
974 | int cec_ll_rx(unsigned char *msg, unsigned char *len) |
975 | { |
976 | int i; |
977 | int ret = -1; |
978 | int pos; |
979 | int rx_stat; |
980 | |
981 | rx_stat = aocec_rd_reg(CEC_RX_MSG_STATUS); |
982 | if ((rx_stat != RX_DONE) || (aocec_rd_reg(CEC_RX_NUM_MSG) != 1)) { |
983 | CEC_INFO("rx status:%x\n", rx_stat); |
984 | writel((1 << 2), cec_dev->cec_reg + AO_CEC_INTR_CLR); |
985 | aocec_wr_reg(CEC_RX_MSG_CMD, RX_ACK_CURRENT); |
986 | aocec_wr_reg(CEC_RX_MSG_CMD, RX_NO_OP); |
987 | cec_rx_buf_clear(); |
988 | return ret; |
989 | } |
990 | |
991 | *len = aocec_rd_reg(CEC_RX_MSG_LENGTH) + 1; |
992 | |
993 | for (i = 0; i < (*len) && i < MAX_MSG; i++) |
994 | msg[i] = aocec_rd_reg(CEC_RX_MSG_0_HEADER + i); |
995 | |
996 | ret = rx_stat; |
997 | |
998 | /* ignore ping message */ |
999 | if (cec_msg_dbg_en && *len > 1) { |
1000 | pos = 0; |
1001 | pos += sprintf(msg_log_buf + pos, |
1002 | "CEC: rx msg len: %d dat: ", *len); |
1003 | for (i = 0; i < (*len); i++) |
1004 | pos += sprintf(msg_log_buf + pos, "%02x ", msg[i]); |
1005 | pos += sprintf(msg_log_buf + pos, "\n"); |
1006 | msg_log_buf[pos] = '\0'; |
1007 | CEC_INFO("%s", msg_log_buf); |
1008 | } |
1009 | last_cec_msg->len = 0; /* invalid back up msg when rx */ |
1010 | writel((1 << 2), cec_dev->cec_reg + AO_CEC_INTR_CLR); |
1011 | aocec_wr_reg(CEC_RX_MSG_CMD, RX_ACK_CURRENT); |
1012 | aocec_wr_reg(CEC_RX_MSG_CMD, RX_NO_OP); |
1013 | cec_rx_buf_clear(); |
1014 | pin_status = 1; |
1015 | return ret; |
1016 | } |
1017 | |
1018 | /************************ cec arbitration cts code **************************/ |
1019 | /* using the cec pin as fiq gpi to assist the bus arbitration */ |
1020 | |
1021 | /* return value: 1: successful 0: error */ |
1022 | static int ceca_trigle_tx(const unsigned char *msg, int len) |
1023 | { |
1024 | int i; |
1025 | unsigned int n; |
1026 | int pos; |
1027 | int reg; |
1028 | unsigned int j = 40; |
1029 | unsigned int tx_stat; |
1030 | static int cec_timeout_cnt = 1; |
1031 | |
1032 | while (1) { |
1033 | tx_stat = aocec_rd_reg(CEC_TX_MSG_STATUS); |
1034 | if (tx_stat != TX_BUSY) |
1035 | break; |
1036 | |
1037 | if (!(j--)) { |
1038 | CEC_INFO("waiting busy timeout\n"); |
1039 | aocec_wr_reg(CEC_TX_MSG_CMD, TX_ABORT); |
1040 | cec_timeout_cnt++; |
1041 | if (cec_timeout_cnt > 0x08) |
1042 | cec_hw_reset(); |
1043 | break; |
1044 | } |
1045 | msleep(20); |
1046 | } |
1047 | |
1048 | reg = aocec_rd_reg(CEC_TX_MSG_STATUS); |
1049 | if (reg == TX_IDLE || reg == TX_DONE) { |
1050 | for (i = 0; i < len; i++) |
1051 | aocec_wr_reg(CEC_TX_MSG_0_HEADER + i, msg[i]); |
1052 | |
1053 | aocec_wr_reg(CEC_TX_MSG_LENGTH, len-1); |
1054 | aocec_wr_reg(CEC_TX_MSG_CMD, TX_REQ_CURRENT); |
1055 | |
1056 | if (cec_msg_dbg_en) { |
1057 | pos = 0; |
1058 | pos += sprintf(msg_log_buf + pos, |
1059 | "CEC: tx msg len: %d dat: ", len); |
1060 | for (n = 0; n < len; n++) { |
1061 | pos += sprintf(msg_log_buf + pos, |
1062 | "%02x ", msg[n]); |
1063 | } |
1064 | |
1065 | pos += sprintf(msg_log_buf + pos, "\n"); |
1066 | |
1067 | msg_log_buf[pos] = '\0'; |
1068 | pr_info("%s", msg_log_buf); |
1069 | } |
1070 | cec_timeout_cnt = 0; |
1071 | return 0; |
1072 | } |
1073 | CEC_ERR("error msg sts:0x%x\n", reg); |
1074 | return -1; |
1075 | } |
1076 | |
1077 | void tx_irq_handle(void) |
1078 | { |
1079 | unsigned int tx_status = aocec_rd_reg(CEC_TX_MSG_STATUS); |
1080 | |
1081 | cec_tx_result = -1; |
1082 | switch (tx_status) { |
1083 | case TX_DONE: |
1084 | aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP); |
1085 | cec_tx_result = CEC_FAIL_NONE; |
1086 | break; |
1087 | |
1088 | case TX_BUSY: |
1089 | CEC_ERR("TX_BUSY\n"); |
1090 | cec_tx_result = CEC_FAIL_BUSY; |
1091 | break; |
1092 | |
1093 | case TX_ERROR: |
1094 | if (cec_msg_dbg_en) |
1095 | CEC_ERR("TX ERROR!!!\n"); |
1096 | aocec_wr_reg(CEC_TX_MSG_CMD, TX_ABORT); |
1097 | cec_hw_reset(); |
1098 | cec_tx_result = CEC_FAIL_NACK; |
1099 | break; |
1100 | |
1101 | case TX_IDLE: |
1102 | CEC_ERR("TX_IDLE\n"); |
1103 | cec_tx_result = CEC_FAIL_OTHER; |
1104 | break; |
1105 | default: |
1106 | break; |
1107 | } |
1108 | writel((1 << 1), cec_dev->cec_reg + AO_CEC_INTR_CLR); |
1109 | complete(&cec_dev->tx_ok); |
1110 | } |
1111 | |
1112 | static int get_line(void) |
1113 | { |
1114 | int reg, ret = -EINVAL; |
1115 | |
1116 | if (cec_dev->plat_data->line_reg == 1) |
1117 | reg = readl(cec_dev->periphs_reg + PREG_PAD_GPIO3_I); |
1118 | else |
1119 | reg = readl(cec_dev->cec_reg + AO_GPIO_I); |
1120 | ret = (reg & (1 << cec_dev->plat_data->line_bit)); |
1121 | |
1122 | return ret; |
1123 | } |
1124 | |
1125 | static enum hrtimer_restart cec_line_check(struct hrtimer *timer) |
1126 | { |
1127 | if (get_line() == 0) |
1128 | cec_line_cnt++; |
1129 | hrtimer_forward_now(timer, HR_DELAY(1)); |
1130 | return HRTIMER_RESTART; |
1131 | } |
1132 | |
1133 | static int check_confilct(void) |
1134 | { |
1135 | int i; |
1136 | |
1137 | for (i = 0; i < 200; i++) { |
1138 | /* |
1139 | * sleep 20ms and using hrtimer to check cec line every 1ms |
1140 | */ |
1141 | cec_line_cnt = 0; |
1142 | hrtimer_start(&start_bit_check, HR_DELAY(1), HRTIMER_MODE_REL); |
1143 | msleep(20); |
1144 | hrtimer_cancel(&start_bit_check); |
1145 | if (cec_line_cnt == 0) |
1146 | break; |
1147 | CEC_INFO("line busy:%d\n", cec_line_cnt); |
1148 | } |
1149 | if (i >= 200) |
1150 | return -EBUSY; |
1151 | else |
1152 | return 0; |
1153 | } |
1154 | |
1155 | static bool check_physical_addr_valid(int timeout) |
1156 | { |
1157 | while (timeout > 0) { |
1158 | if (cec_dev->dev_type == CEC_TV_ADDR) |
1159 | break; |
1160 | if (phy_addr_test) |
1161 | break; |
1162 | /* physical address for box */ |
1163 | if (cec_dev->tx_dev->hdmi_info.vsdb_phy_addr.valid == 0) { |
1164 | msleep(100); |
1165 | timeout--; |
1166 | } else |
1167 | break; |
1168 | } |
1169 | if (timeout <= 0) |
1170 | return false; |
1171 | return true; |
1172 | } |
1173 | |
1174 | /* Return value: < 0: fail, > 0: success */ |
1175 | int cec_ll_tx(const unsigned char *msg, unsigned char len) |
1176 | { |
1177 | int ret = -1; |
1178 | int t = msecs_to_jiffies(ee_cec ? 2000 : 5000); |
1179 | int retry = 2; |
1180 | |
1181 | if (len == 0) |
1182 | return CEC_FAIL_NONE; |
1183 | |
1184 | if (is_poll_message(msg[0])) |
1185 | cec_clear_all_logical_addr(ee_cec); |
1186 | |
1187 | /* |
1188 | * for CEC CTS 9.3. Android will try 3 poll message if got NACK |
1189 | * but AOCEC will retry 4 tx for each poll message. Framework |
1190 | * repeat this poll message so quick makes 12 sequential poll |
1191 | * waveform seen on CEC bus. And did not pass CTS |
1192 | * specification of 9.3 |
1193 | */ |
1194 | if (!ee_cec && need_nack_repeat_msg(msg, len, t)) { |
1195 | if (!memcmp(msg, last_cec_msg->msg, len)) { |
1196 | CEC_INFO("NACK repeat message:%x\n", len); |
1197 | return CEC_FAIL_NACK; |
1198 | } |
1199 | } |
1200 | |
1201 | mutex_lock(&cec_dev->cec_mutex); |
1202 | /* make sure we got valid physical address */ |
1203 | if (len >= 2 && msg[1] == CEC_OC_REPORT_PHYSICAL_ADDRESS) |
1204 | check_physical_addr_valid(3); |
1205 | |
1206 | try_again: |
1207 | reinit_completion(&cec_dev->tx_ok); |
1208 | /* |
1209 | * CEC controller won't ack message if it is going to send |
1210 | * state. If we detect cec line is low during waiting signal |
1211 | * free time, that means a send is already started by other |
1212 | * device, we should wait it finished. |
1213 | */ |
1214 | if (check_confilct()) { |
1215 | CEC_ERR("bus confilct too long\n"); |
1216 | mutex_unlock(&cec_dev->cec_mutex); |
1217 | return CEC_FAIL_BUSY; |
1218 | } |
1219 | |
1220 | if (ee_cec) |
1221 | ret = cecb_trigle_tx(msg, len); |
1222 | else |
1223 | ret = ceca_trigle_tx(msg, len); |
1224 | if (ret < 0) { |
1225 | /* we should increase send idx if busy */ |
1226 | CEC_INFO("tx busy\n"); |
1227 | if (retry > 0) { |
1228 | retry--; |
1229 | msleep(100 + (prandom_u32() & 0x07) * 10); |
1230 | goto try_again; |
1231 | } |
1232 | mutex_unlock(&cec_dev->cec_mutex); |
1233 | return CEC_FAIL_BUSY; |
1234 | } |
1235 | cec_tx_result = -1; |
1236 | ret = wait_for_completion_timeout(&cec_dev->tx_ok, t); |
1237 | if (ret <= 0) { |
1238 | /* timeout or interrupt */ |
1239 | if (ret == 0) { |
1240 | CEC_ERR("tx timeout\n"); |
1241 | cec_hw_reset(); |
1242 | } |
1243 | ret = CEC_FAIL_OTHER; |
1244 | } else { |
1245 | ret = cec_tx_result; |
1246 | } |
1247 | if (ret != CEC_FAIL_NONE && ret != CEC_FAIL_NACK) { |
1248 | if (retry > 0) { |
1249 | retry--; |
1250 | msleep(100 + (prandom_u32() & 0x07) * 10); |
1251 | goto try_again; |
1252 | } |
1253 | } |
1254 | mutex_unlock(&cec_dev->cec_mutex); |
1255 | |
1256 | if (!ee_cec) { |
1257 | last_cec_msg->last_result = ret; |
1258 | if (ret == CEC_FAIL_NACK) { |
1259 | memcpy(last_cec_msg->msg, msg, len); |
1260 | last_cec_msg->len = len; |
1261 | last_cec_msg->last_jiffies = jiffies; |
1262 | } |
1263 | } |
1264 | return ret; |
1265 | } |
1266 | |
1267 | /* -------------------------------------------------------------------------- */ |
1268 | /* AO CEC0 config */ |
1269 | /* -------------------------------------------------------------------------- */ |
1270 | static void ao_ceca_init(void) |
1271 | { |
1272 | unsigned long data32; |
1273 | unsigned int reg; |
1274 | unsigned int chiptype; |
1275 | |
1276 | chiptype = get_meson_cpu_version(MESON_CPU_VERSION_LVL_MAJOR); |
1277 | |
1278 | /*CEC_INFO("chiptype=0x%x\n", chiptype);*/ |
1279 | if (chiptype >= MESON_CPU_MAJOR_ID_GXBB) { |
1280 | if (cec_dev->plat_data->ee_to_ao) { |
1281 | reg = (0 << 31) | |
1282 | (0 << 30) | |
1283 | (1 << 28) | /* clk_div0/clk_div1 in turn */ |
1284 | ((732-1) << 12) |/* Div_tcnt1 */ |
1285 | ((733-1) << 0); /* Div_tcnt0 */ |
1286 | writel(reg, cec_dev->cec_reg + AO_CEC_CLK_CNTL_REG0); |
1287 | reg = (0 << 13) | |
1288 | ((11-1) << 12) | |
1289 | ((8-1) << 0); |
1290 | writel(reg, cec_dev->cec_reg + AO_CEC_CLK_CNTL_REG1); |
1291 | /*enable clk in*/ |
1292 | reg = readl(cec_dev->cec_reg + AO_CEC_CLK_CNTL_REG0); |
1293 | reg |= (1 << 31); |
1294 | writel(reg, cec_dev->cec_reg + AO_CEC_CLK_CNTL_REG0); |
1295 | /*enable clk out*/ |
1296 | udelay(200); |
1297 | reg |= (1 << 30); |
1298 | writel(reg, cec_dev->cec_reg + AO_CEC_CLK_CNTL_REG0); |
1299 | } else { |
1300 | reg = (0 << 31) | |
1301 | (0 << 30) | |
1302 | (1 << 28) | /* clk_div0/clk_div1 in turn */ |
1303 | ((732-1) << 12) |/* Div_tcnt1 */ |
1304 | ((733-1) << 0); /* Div_tcnt0 */ |
1305 | writel(reg, cec_dev->cec_reg + AO_RTC_ALT_CLK_CNTL0); |
1306 | reg = (0 << 13) | |
1307 | ((11-1) << 12) | |
1308 | ((8-1) << 0); |
1309 | writel(reg, cec_dev->cec_reg + AO_RTC_ALT_CLK_CNTL1); |
1310 | |
1311 | /*enable clk in*/ |
1312 | reg = readl(cec_dev->cec_reg + AO_RTC_ALT_CLK_CNTL0); |
1313 | reg |= (1 << 31); |
1314 | writel(reg, cec_dev->cec_reg + AO_RTC_ALT_CLK_CNTL0); |
1315 | /*enable clk out*/ |
1316 | udelay(200); |
1317 | reg |= (1 << 30); |
1318 | writel(reg, cec_dev->cec_reg + AO_RTC_ALT_CLK_CNTL0); |
1319 | } |
1320 | |
1321 | if (cec_dev->plat_data->ee_to_ao) { |
1322 | reg = readl(cec_dev->cec_reg + AO_RTI_PWR_CNTL_REG0); |
1323 | reg |= (0x01 << 14);/* enable the crystal clock*/ |
1324 | writel(reg, cec_dev->cec_reg + AO_RTI_PWR_CNTL_REG0); |
1325 | } else { |
1326 | reg = readl(cec_dev->cec_reg + AO_CRT_CLK_CNTL1); |
1327 | reg |= (0x800 << 16);/* select cts_rtc_oscin_clk */ |
1328 | writel(reg, cec_dev->cec_reg + AO_CRT_CLK_CNTL1); |
1329 | |
1330 | reg = readl(cec_dev->cec_reg + AO_RTI_PWR_CNTL_REG0); |
1331 | reg &= ~(0x07 << 10); |
1332 | reg |= (0x04 << 10);/* XTAL generate 32k */ |
1333 | writel(reg, cec_dev->cec_reg + AO_RTI_PWR_CNTL_REG0); |
1334 | } |
1335 | } |
1336 | |
1337 | if (cec_dev->plat_data->ee_to_ao) { |
1338 | data32 = 0; |
1339 | data32 |= (7 << 12); /* filter_del */ |
1340 | data32 |= (1 << 8); /* filter_tick: 1us */ |
1341 | data32 |= (1 << 3); /* enable system clock*/ |
1342 | data32 |= 0 << 1; /* [2:1] cntl_clk: */ |
1343 | /* 0=Disable clk (Power-off mode); */ |
1344 | /* 1=Enable gated clock (Normal mode);*/ |
1345 | /* 2=Enable free-run clk (Debug mode).*/ |
1346 | data32 |= 1 << 0; /* [0] sw_reset: 1=Reset*/ |
1347 | writel(data32, cec_dev->cec_reg + AO_CEC_GEN_CNTL); |
1348 | } else { |
1349 | data32 = 0; |
1350 | data32 |= 0 << 1; /* [2:1] cntl_clk:*/ |
1351 | /* 0=Disable clk (Power-off mode);*/ |
1352 | /* 1=Enable gated clock (Normal mode);*/ |
1353 | /* 2=Enable free-run clk (Debug mode).*/ |
1354 | data32 |= 1 << 0; /* [0] sw_reset: 1=Reset */ |
1355 | writel(data32, cec_dev->cec_reg + AO_CEC_GEN_CNTL); |
1356 | } |
1357 | /* Enable gated clock (Normal mode). */ |
1358 | cec_set_reg_bits(AO_CEC_GEN_CNTL, 1, 1, 1); |
1359 | /* Release SW reset */ |
1360 | cec_set_reg_bits(AO_CEC_GEN_CNTL, 0, 0, 1); |
1361 | |
1362 | /* Enable all AO_CEC interrupt sources */ |
1363 | cec_irq_enable(true); |
1364 | |
1365 | cec_arbit_bit_time_set(3, 0x118, 0); |
1366 | cec_arbit_bit_time_set(5, 0x000, 0); |
1367 | cec_arbit_bit_time_set(7, 0x2aa, 0); |
1368 | } |
1369 | |
1370 | void cec_arbit_bit_time_set(unsigned int bit_set, |
1371 | unsigned int time_set, unsigned int flag) |
1372 | { /* 11bit:bit[10:0] */ |
1373 | if (flag) { |
1374 | CEC_INFO("bit_set:0x%x;time_set:0x%x\n", |
1375 | bit_set, time_set); |
1376 | } |
1377 | |
1378 | switch (bit_set) { |
1379 | case 3: |
1380 | /* 3 bit */ |
1381 | if (flag) { |
1382 | CEC_INFO("read 3 bit:0x%x%x\n", |
1383 | aocec_rd_reg(AO_CEC_TXTIME_4BIT_BIT10_8), |
1384 | aocec_rd_reg(AO_CEC_TXTIME_4BIT_BIT7_0)); |
1385 | } |
1386 | aocec_wr_reg(AO_CEC_TXTIME_4BIT_BIT7_0, time_set & 0xff); |
1387 | aocec_wr_reg(AO_CEC_TXTIME_4BIT_BIT10_8, (time_set >> 8) & 0x7); |
1388 | if (flag) { |
1389 | CEC_INFO("write 3 bit:0x%x%x\n", |
1390 | aocec_rd_reg(AO_CEC_TXTIME_4BIT_BIT10_8), |
1391 | aocec_rd_reg(AO_CEC_TXTIME_4BIT_BIT7_0)); |
1392 | } |
1393 | break; |
1394 | /* 5 bit */ |
1395 | case 5: |
1396 | if (flag) { |
1397 | CEC_INFO("read 5 bit:0x%x%x\n", |
1398 | aocec_rd_reg(AO_CEC_TXTIME_2BIT_BIT10_8), |
1399 | aocec_rd_reg(AO_CEC_TXTIME_2BIT_BIT7_0)); |
1400 | } |
1401 | aocec_wr_reg(AO_CEC_TXTIME_2BIT_BIT7_0, time_set & 0xff); |
1402 | aocec_wr_reg(AO_CEC_TXTIME_2BIT_BIT10_8, (time_set >> 8) & 0x7); |
1403 | if (flag) { |
1404 | CEC_INFO("write 5 bit:0x%x%x\n", |
1405 | aocec_rd_reg(AO_CEC_TXTIME_2BIT_BIT10_8), |
1406 | aocec_rd_reg(AO_CEC_TXTIME_2BIT_BIT7_0)); |
1407 | } |
1408 | break; |
1409 | /* 7 bit */ |
1410 | case 7: |
1411 | if (flag) { |
1412 | CEC_INFO("read 7 bit:0x%x%x\n", |
1413 | aocec_rd_reg(AO_CEC_TXTIME_17MS_BIT10_8), |
1414 | aocec_rd_reg(AO_CEC_TXTIME_17MS_BIT7_0)); |
1415 | } |
1416 | aocec_wr_reg(AO_CEC_TXTIME_17MS_BIT7_0, time_set & 0xff); |
1417 | aocec_wr_reg(AO_CEC_TXTIME_17MS_BIT10_8, (time_set >> 8) & 0x7); |
1418 | if (flag) { |
1419 | CEC_INFO("write 7 bit:0x%x%x\n", |
1420 | aocec_rd_reg(AO_CEC_TXTIME_17MS_BIT10_8), |
1421 | aocec_rd_reg(AO_CEC_TXTIME_17MS_BIT7_0)); |
1422 | } |
1423 | break; |
1424 | default: |
1425 | break; |
1426 | } |
1427 | } |
1428 | |
1429 | static unsigned int ao_cec_intr_stat(void) |
1430 | { |
1431 | return readl(cec_dev->cec_reg + AO_CEC_INTR_STAT); |
1432 | } |
1433 | |
1434 | unsigned int cec_intr_stat(void) |
1435 | { |
1436 | return ao_cec_intr_stat(); |
1437 | } |
1438 | |
1439 | /* |
1440 | *wr_flag: 1 write; value valid |
1441 | * 0 read; value invalid |
1442 | */ |
1443 | unsigned int cec_config(unsigned int value, bool wr_flag) |
1444 | { |
1445 | if (wr_flag) |
1446 | cec_set_reg_bits(AO_DEBUG_REG0, value, 0, 8); |
1447 | |
1448 | return readl(cec_dev->cec_reg + AO_DEBUG_REG0) & 0xff; |
1449 | } |
1450 | |
1451 | /* |
1452 | *wr_flag:1 write; value valid |
1453 | * 0 read; value invalid |
1454 | */ |
1455 | unsigned int cec_phyaddr_config(unsigned int value, bool wr_flag) |
1456 | { |
1457 | if (wr_flag) |
1458 | cec_set_reg_bits(AO_DEBUG_REG1, value, 0, 16); |
1459 | |
1460 | return readl(cec_dev->cec_reg + AO_DEBUG_REG1); |
1461 | } |
1462 | |
1463 | void cec_keep_reset(void) |
1464 | { |
1465 | if (ee_cec) |
1466 | cecb_hw_reset(); |
1467 | else |
1468 | writel(0x1, cec_dev->cec_reg + AO_CEC_GEN_CNTL); |
1469 | } |
1470 | /* |
1471 | * cec hw module init before allocate logical address |
1472 | */ |
1473 | static void cec_pre_init(void) |
1474 | { |
1475 | unsigned int reg = readl(cec_dev->cec_reg + AO_RTI_STATUS_REG1); |
1476 | |
1477 | reg &= 0xfffff; |
1478 | if ((reg & 0xffff) == 0xffff) |
1479 | wake_ok = 0; |
1480 | pr_info("cec: wake up flag:%x\n", reg); |
1481 | |
1482 | if (ee_cec) { |
1483 | ao_cecb_init(); |
1484 | /*cec_logicaddr_set(cec_dev->cec_info.log_addr);*/ |
1485 | } else { |
1486 | ao_ceca_init(); |
1487 | } |
1488 | |
1489 | //need restore all logical address |
1490 | cec_restore_logical_addr(cec_dev->cec_info.addr_enable); |
1491 | } |
1492 | |
1493 | static int cec_late_check_rx_buffer(void) |
1494 | { |
1495 | int ret; |
1496 | /*struct delayed_work *dwork = &cec_dev->cec_work;*/ |
1497 | |
1498 | ret = cec_rx_buf_check(); |
1499 | if (!ret) |
1500 | return 0; |
1501 | /* |
1502 | * start another check if rx buffer is full |
1503 | */ |
1504 | if ((-1) == cec_ll_rx(rx_msg, &rx_len)) { |
1505 | CEC_INFO("buffer got unrecorgnized msg\n"); |
1506 | cec_rx_buf_clear(); |
1507 | return 0; |
1508 | } |
1509 | return 1; |
1510 | } |
1511 | |
1512 | void cec_key_report(int suspend) |
1513 | { |
1514 | input_event(cec_dev->cec_info.remote_cec_dev, EV_KEY, KEY_POWER, 1); |
1515 | input_sync(cec_dev->cec_info.remote_cec_dev); |
1516 | input_event(cec_dev->cec_info.remote_cec_dev, EV_KEY, KEY_POWER, 0); |
1517 | input_sync(cec_dev->cec_info.remote_cec_dev); |
1518 | if (!suspend) |
1519 | CEC_INFO("== WAKE UP BY CEC ==\n") |
1520 | else |
1521 | CEC_INFO("== SLEEP by CEC==\n") |
1522 | } |
1523 | |
1524 | void cec_give_version(unsigned int dest) |
1525 | { |
1526 | unsigned char index = cec_dev->cec_info.log_addr; |
1527 | unsigned char msg[3]; |
1528 | |
1529 | if (dest != 0xf) { |
1530 | msg[0] = ((index & 0xf) << 4) | dest; |
1531 | msg[1] = CEC_OC_CEC_VERSION; |
1532 | msg[2] = cec_dev->cec_info.cec_version; |
1533 | cec_ll_tx(msg, 3); |
1534 | } |
1535 | } |
1536 | |
1537 | void cec_report_physical_address_smp(void) |
1538 | { |
1539 | unsigned char msg[5]; |
1540 | unsigned char index = cec_dev->cec_info.log_addr; |
1541 | unsigned char phy_addr_ab, phy_addr_cd; |
1542 | |
1543 | phy_addr_ab = (cec_dev->phy_addr >> 8) & 0xff; |
1544 | phy_addr_cd = (cec_dev->phy_addr >> 0) & 0xff; |
1545 | msg[0] = ((index & 0xf) << 4) | CEC_BROADCAST_ADDR; |
1546 | msg[1] = CEC_OC_REPORT_PHYSICAL_ADDRESS; |
1547 | msg[2] = phy_addr_ab; |
1548 | msg[3] = phy_addr_cd; |
1549 | msg[4] = cec_dev->dev_type; |
1550 | |
1551 | cec_ll_tx(msg, 5); |
1552 | } |
1553 | |
1554 | void cec_device_vendor_id(void) |
1555 | { |
1556 | unsigned char index = cec_dev->cec_info.log_addr; |
1557 | unsigned char msg[5]; |
1558 | unsigned int vendor_id; |
1559 | |
1560 | vendor_id = cec_dev->v_data.vendor_id; |
1561 | msg[0] = ((index & 0xf) << 4) | CEC_BROADCAST_ADDR; |
1562 | msg[1] = CEC_OC_DEVICE_VENDOR_ID; |
1563 | msg[2] = (vendor_id >> 16) & 0xff; |
1564 | msg[3] = (vendor_id >> 8) & 0xff; |
1565 | msg[4] = (vendor_id >> 0) & 0xff; |
1566 | |
1567 | cec_ll_tx(msg, 5); |
1568 | } |
1569 | |
1570 | void cec_give_deck_status(unsigned int dest) |
1571 | { |
1572 | unsigned char index = cec_dev->cec_info.log_addr; |
1573 | unsigned char msg[3]; |
1574 | |
1575 | msg[0] = ((index & 0xf) << 4) | dest; |
1576 | msg[1] = CEC_OC_DECK_STATUS; |
1577 | msg[2] = 0x1a; |
1578 | cec_ll_tx(msg, 3); |
1579 | } |
1580 | |
1581 | void cec_menu_status_smp(int dest, int status) |
1582 | { |
1583 | unsigned char msg[3]; |
1584 | unsigned char index = cec_dev->cec_info.log_addr; |
1585 | |
1586 | msg[0] = ((index & 0xf) << 4) | dest; |
1587 | msg[1] = CEC_OC_MENU_STATUS; |
1588 | if (status == DEVICE_MENU_ACTIVE) |
1589 | msg[2] = DEVICE_MENU_ACTIVE; |
1590 | else |
1591 | msg[2] = DEVICE_MENU_INACTIVE; |
1592 | cec_ll_tx(msg, 3); |
1593 | } |
1594 | |
1595 | void cec_inactive_source(int dest) |
1596 | { |
1597 | unsigned char index = cec_dev->cec_info.log_addr; |
1598 | unsigned char msg[4]; |
1599 | unsigned char phy_addr_ab, phy_addr_cd; |
1600 | |
1601 | phy_addr_ab = (cec_dev->phy_addr >> 8) & 0xff; |
1602 | phy_addr_cd = (cec_dev->phy_addr >> 0) & 0xff; |
1603 | msg[0] = ((index & 0xf) << 4) | dest; |
1604 | msg[1] = CEC_OC_INACTIVE_SOURCE; |
1605 | msg[2] = phy_addr_ab; |
1606 | msg[3] = phy_addr_cd; |
1607 | |
1608 | cec_ll_tx(msg, 4); |
1609 | } |
1610 | |
1611 | void cec_set_osd_name(int dest) |
1612 | { |
1613 | unsigned char index = cec_dev->cec_info.log_addr; |
1614 | unsigned char osd_len = strlen(cec_dev->cec_info.osd_name); |
1615 | unsigned char msg[16]; |
1616 | |
1617 | if (dest != 0xf) { |
1618 | msg[0] = ((index & 0xf) << 4) | dest; |
1619 | msg[1] = CEC_OC_SET_OSD_NAME; |
1620 | memcpy(&msg[2], cec_dev->cec_info.osd_name, osd_len); |
1621 | |
1622 | cec_ll_tx(msg, 2 + osd_len); |
1623 | } |
1624 | } |
1625 | |
1626 | void cec_active_source_smp(void) |
1627 | { |
1628 | unsigned char msg[4]; |
1629 | unsigned char index = cec_dev->cec_info.log_addr; |
1630 | unsigned char phy_addr_ab; |
1631 | unsigned char phy_addr_cd; |
1632 | |
1633 | phy_addr_ab = (cec_dev->phy_addr >> 8) & 0xff; |
1634 | phy_addr_cd = (cec_dev->phy_addr >> 0) & 0xff; |
1635 | msg[0] = ((index & 0xf) << 4) | CEC_BROADCAST_ADDR; |
1636 | msg[1] = CEC_OC_ACTIVE_SOURCE; |
1637 | msg[2] = phy_addr_ab; |
1638 | msg[3] = phy_addr_cd; |
1639 | cec_ll_tx(msg, 4); |
1640 | } |
1641 | |
1642 | void cec_request_active_source(void) |
1643 | { |
1644 | unsigned char msg[2]; |
1645 | unsigned char index = cec_dev->cec_info.log_addr; |
1646 | |
1647 | msg[0] = ((index & 0xf) << 4) | CEC_BROADCAST_ADDR; |
1648 | msg[1] = CEC_OC_REQUEST_ACTIVE_SOURCE; |
1649 | cec_ll_tx(msg, 2); |
1650 | } |
1651 | |
1652 | void cec_set_stream_path(unsigned char *msg) |
1653 | { |
1654 | unsigned int phy_addr_active; |
1655 | |
1656 | phy_addr_active = (unsigned int)(msg[2] << 8 | msg[3]); |
1657 | if (phy_addr_active == cec_dev->phy_addr) { |
1658 | cec_active_source_smp(); |
1659 | /* |
1660 | * some types of TV such as panasonic need to send menu status, |
1661 | * otherwise it will not send remote key event to control |
1662 | * device's menu |
1663 | */ |
1664 | cec_menu_status_smp(msg[0] >> 4, DEVICE_MENU_ACTIVE); |
1665 | } |
1666 | } |
1667 | |
1668 | void cec_report_power_status(int dest, int status) |
1669 | { |
1670 | unsigned char index = cec_dev->cec_info.log_addr; |
1671 | unsigned char msg[3]; |
1672 | |
1673 | msg[0] = ((index & 0xf) << 4) | dest; |
1674 | msg[1] = CEC_OC_REPORT_POWER_STATUS; |
1675 | msg[2] = status; |
1676 | cec_ll_tx(msg, 3); |
1677 | } |
1678 | |
1679 | static void cec_rx_process(void) |
1680 | { |
1681 | int len = rx_len; |
1682 | int initiator, follower; |
1683 | int opcode; |
1684 | unsigned char msg[MAX_MSG] = {}; |
1685 | int dest_phy_addr; |
1686 | |
1687 | if (len < 2 || !new_msg) /* ignore ping message */ |
1688 | return; |
1689 | |
1690 | memcpy(msg, rx_msg, len); |
1691 | initiator = ((msg[0] >> 4) & 0xf); |
1692 | follower = msg[0] & 0xf; |
1693 | if (follower != 0xf && follower != cec_dev->cec_info.log_addr) { |
1694 | CEC_ERR("wrong rx message of bad follower:%x", follower); |
1695 | return; |
1696 | } |
1697 | opcode = msg[1]; |
1698 | switch (opcode) { |
1699 | case CEC_OC_ACTIVE_SOURCE: |
1700 | if (wake_ok == 0) { |
1701 | int phy_addr = msg[2] << 8 | msg[3]; |
1702 | |
1703 | if (phy_addr == 0xffff) |
1704 | break; |
1705 | wake_ok = 1; |
1706 | phy_addr |= (initiator << 16); |
1707 | writel(phy_addr, cec_dev->cec_reg + AO_RTI_STATUS_REG1); |
1708 | CEC_INFO("found wake up source:%x", phy_addr); |
1709 | } |
1710 | break; |
1711 | |
1712 | case CEC_OC_ROUTING_CHANGE: |
1713 | dest_phy_addr = msg[4] << 8 | msg[5]; |
1714 | if ((dest_phy_addr == cec_dev->phy_addr) && |
1715 | (cec_dev->cec_suspend != CEC_POWER_ON)) { |
1716 | CEC_INFO("wake up by ROUTING_CHANGE\n"); |
1717 | cec_key_report(0); |
1718 | } |
1719 | break; |
1720 | |
1721 | case CEC_OC_GET_CEC_VERSION: |
1722 | cec_give_version(initiator); |
1723 | break; |
1724 | |
1725 | case CEC_OC_GIVE_DECK_STATUS: |
1726 | cec_give_deck_status(initiator); |
1727 | break; |
1728 | |
1729 | case CEC_OC_GIVE_PHYSICAL_ADDRESS: |
1730 | cec_report_physical_address_smp(); |
1731 | break; |
1732 | |
1733 | case CEC_OC_GIVE_DEVICE_VENDOR_ID: |
1734 | cec_device_vendor_id(); |
1735 | break; |
1736 | |
1737 | case CEC_OC_GIVE_OSD_NAME: |
1738 | cec_set_osd_name(initiator); |
1739 | break; |
1740 | |
1741 | case CEC_OC_STANDBY: |
1742 | cec_inactive_source(initiator); |
1743 | cec_menu_status_smp(initiator, DEVICE_MENU_INACTIVE); |
1744 | break; |
1745 | |
1746 | case CEC_OC_SET_STREAM_PATH: |
1747 | cec_set_stream_path(msg); |
1748 | /* wake up if in early suspend */ |
1749 | dest_phy_addr = (unsigned int)(msg[2] << 8 | msg[3]); |
1750 | CEC_ERR("phyaddr:0x%x, 0x%x\n", |
1751 | cec_dev->phy_addr, dest_phy_addr); |
1752 | if ((dest_phy_addr != 0xffff) && |
1753 | (dest_phy_addr == cec_dev->phy_addr) && |
1754 | (cec_dev->cec_suspend != CEC_POWER_ON)) |
1755 | cec_key_report(0); |
1756 | break; |
1757 | |
1758 | case CEC_OC_REQUEST_ACTIVE_SOURCE: |
1759 | if (cec_dev->cec_suspend == CEC_POWER_ON) |
1760 | cec_active_source_smp(); |
1761 | break; |
1762 | |
1763 | case CEC_OC_GIVE_DEVICE_POWER_STATUS: |
1764 | if (cec_dev->cec_suspend == CEC_DEEP_SUSPEND) |
1765 | cec_report_power_status(initiator, POWER_STANDBY); |
1766 | else if (cec_dev->cec_suspend == CEC_EARLY_SUSPEND) |
1767 | cec_report_power_status(initiator, TRANS_ON_TO_STANDBY); |
1768 | else if (cec_dev->cec_suspend == CEC_POWER_RESUME) |
1769 | cec_report_power_status(initiator, TRANS_STANDBY_TO_ON); |
1770 | else |
1771 | cec_report_power_status(initiator, POWER_ON); |
1772 | break; |
1773 | |
1774 | case CEC_OC_USER_CONTROL_PRESSED: |
1775 | /* wake up by key function */ |
1776 | if (cec_dev->cec_suspend != CEC_POWER_ON) { |
1777 | if (msg[2] == 0x40 || msg[2] == 0x6d) |
1778 | cec_key_report(0); |
1779 | } |
1780 | break; |
1781 | |
1782 | case CEC_OC_MENU_REQUEST: |
1783 | if (cec_dev->cec_suspend != CEC_POWER_ON) |
1784 | cec_menu_status_smp(initiator, DEVICE_MENU_INACTIVE); |
1785 | else |
1786 | cec_menu_status_smp(initiator, DEVICE_MENU_ACTIVE); |
1787 | break; |
1788 | |
1789 | case CEC_OC_IMAGE_VIEW_ON: |
1790 | case CEC_OC_TEXT_VIEW_ON: |
1791 | /* request active source needed */ |
1792 | dest_phy_addr = 0xffff; |
1793 | dest_phy_addr = (dest_phy_addr << 0) | (initiator << 16); |
1794 | writel(dest_phy_addr, cec_dev->cec_reg + AO_RTI_STATUS_REG1); |
1795 | CEC_INFO("weak up by otp\n"); |
1796 | cec_key_report(0); |
1797 | break; |
1798 | |
1799 | default: |
1800 | CEC_ERR("unsupported command:%x\n", opcode); |
1801 | CEC_ERR("wake_ok=%d,hal_flag=0x%x\n", |
1802 | wake_ok, cec_dev->hal_flag); |
1803 | break; |
1804 | } |
1805 | new_msg = 0; |
1806 | } |
1807 | |
1808 | static bool cec_service_suspended(void) |
1809 | { |
1810 | /* service is not enabled */ |
1811 | if (!(cec_dev->hal_flag & (1 << HDMI_OPTION_SERVICE_FLAG))) |
1812 | return false; |
1813 | if (!(cec_dev->hal_flag & (1 << HDMI_OPTION_SYSTEM_CEC_CONTROL))) |
1814 | return true; |
1815 | return false; |
1816 | } |
1817 | |
1818 | static void cec_task(struct work_struct *work) |
1819 | { |
1820 | struct delayed_work *dwork = &cec_dev->cec_work; |
1821 | unsigned int cec_cfg; |
1822 | |
1823 | cec_cfg = cec_config(0, 0); |
1824 | if (cec_cfg & CEC_FUNC_CFG_CEC_ON) { |
1825 | /*cec module on*/ |
1826 | if (cec_dev && (!wake_ok || cec_service_suspended())) |
1827 | cec_rx_process(); |
1828 | |
1829 | /*for check rx buffer for old chip version, cec rx irq process*/ |
1830 | /*in internal hdmi rx, for avoid msg lose*/ |
1831 | if ((cec_dev->cpu_type < MESON_CPU_MAJOR_ID_TXLX) && |
1832 | (cec_cfg == CEC_FUNC_CFG_ALL)) { |
1833 | if (cec_late_check_rx_buffer()) { |
1834 | /*msg in*/ |
1835 | mod_delayed_work(cec_dev->cec_thread, dwork, 0); |
1836 | return; |
1837 | } |
1838 | } |
1839 | } |
1840 | /*triger next process*/ |
1841 | queue_delayed_work(cec_dev->cec_thread, dwork, CEC_FRAME_DELAY); |
1842 | } |
1843 | |
1844 | static irqreturn_t ceca_isr(int irq, void *dev_instance) |
1845 | { |
1846 | unsigned int intr_stat = 0; |
1847 | struct delayed_work *dwork; |
1848 | |
1849 | dwork = &cec_dev->cec_work; |
1850 | intr_stat = cec_intr_stat(); |
1851 | if (intr_stat & (1<<1)) { /* aocec tx intr */ |
1852 | tx_irq_handle(); |
1853 | return IRQ_HANDLED; |
1854 | } |
1855 | if ((-1) == cec_ll_rx(rx_msg, &rx_len)) |
1856 | return IRQ_HANDLED; |
1857 | |
1858 | complete(&cec_dev->rx_ok); |
1859 | /* check rx buffer is full */ |
1860 | new_msg = 1; |
1861 | mod_delayed_work(cec_dev->cec_thread, dwork, 0); |
1862 | return IRQ_HANDLED; |
1863 | } |
1864 | /* |
1865 | static void check_wake_up(void) |
1866 | { |
1867 | if (wake_ok == 0) |
1868 | cec_request_active_source(); |
1869 | } |
1870 | */ |
1871 | |
1872 | /******************** cec class interface *************************/ |
1873 | static ssize_t device_type_show(struct class *cla, |
1874 | struct class_attribute *attr, char *buf) |
1875 | { |
1876 | return sprintf(buf, "%ld\n", cec_dev->dev_type); |
1877 | } |
1878 | |
1879 | static ssize_t device_type_store(struct class *cla, |
1880 | struct class_attribute *attr, const char *buf, size_t count) |
1881 | { |
1882 | unsigned int type; |
1883 | |
1884 | if (kstrtouint(buf, 10, &type) != 0) |
1885 | return -EINVAL; |
1886 | |
1887 | cec_dev->dev_type = type; |
1888 | CEC_ERR("set dev_type to %d\n", type); |
1889 | return count; |
1890 | } |
1891 | |
1892 | static ssize_t menu_language_show(struct class *cla, |
1893 | struct class_attribute *attr, char *buf) |
1894 | { |
1895 | char a, b, c; |
1896 | |
1897 | a = ((cec_dev->cec_info.menu_lang >> 16) & 0xff); |
1898 | b = ((cec_dev->cec_info.menu_lang >> 8) & 0xff); |
1899 | c = ((cec_dev->cec_info.menu_lang >> 0) & 0xff); |
1900 | return sprintf(buf, "%c%c%c\n", a, b, c); |
1901 | } |
1902 | |
1903 | static ssize_t menu_language_store(struct class *cla, |
1904 | struct class_attribute *attr, const char *buf, size_t count) |
1905 | { |
1906 | char a, b, c; |
1907 | |
1908 | if (sscanf(buf, "%c%c%c", &a, &b, &c) != 3) |
1909 | return -EINVAL; |
1910 | |
1911 | cec_dev->cec_info.menu_lang = (a << 16) | (b << 8) | c; |
1912 | CEC_ERR("set menu_language to %s\n", buf); |
1913 | return count; |
1914 | } |
1915 | |
1916 | static ssize_t vendor_id_show(struct class *cla, |
1917 | struct class_attribute *attr, char *buf) |
1918 | { |
1919 | return sprintf(buf, "%x\n", cec_dev->cec_info.vendor_id); |
1920 | } |
1921 | |
1922 | static ssize_t vendor_id_store(struct class *cla, struct class_attribute *attr, |
1923 | const char *buf, size_t count) |
1924 | { |
1925 | unsigned int id; |
1926 | |
1927 | if (kstrtouint(buf, 16, &id) != 0) |
1928 | return -EINVAL; |
1929 | cec_dev->cec_info.vendor_id = id; |
1930 | return count; |
1931 | } |
1932 | |
1933 | static ssize_t port_num_show(struct class *cla, |
1934 | struct class_attribute *attr, char *buf) |
1935 | { |
1936 | return sprintf(buf, "%d\n", cec_dev->port_num); |
1937 | } |
1938 | |
1939 | static const char * const cec_reg_name1[] = { |
1940 | "CEC_TX_MSG_LENGTH", |
1941 | "CEC_TX_MSG_CMD", |
1942 | "CEC_TX_WRITE_BUF", |
1943 | "CEC_TX_CLEAR_BUF", |
1944 | "CEC_RX_MSG_CMD", |
1945 | "CEC_RX_CLEAR_BUF", |
1946 | "CEC_LOGICAL_ADDR0", |
1947 | "CEC_LOGICAL_ADDR1", |
1948 | "CEC_LOGICAL_ADDR2", |
1949 | "CEC_LOGICAL_ADDR3", |
1950 | "CEC_LOGICAL_ADDR4", |
1951 | "CEC_CLOCK_DIV_H", |
1952 | "CEC_CLOCK_DIV_L" |
1953 | }; |
1954 | |
1955 | static const char * const cec_reg_name2[] = { |
1956 | "CEC_RX_MSG_LENGTH", |
1957 | "CEC_RX_MSG_STATUS", |
1958 | "CEC_RX_NUM_MSG", |
1959 | "CEC_TX_MSG_STATUS", |
1960 | "CEC_TX_NUM_MSG" |
1961 | }; |
1962 | |
1963 | static ssize_t dump_reg_show(struct class *cla, |
1964 | struct class_attribute *attr, char *b) |
1965 | { |
1966 | int i, s = 0; |
1967 | |
1968 | if (ee_cec) |
1969 | return dump_cecrx_reg(b); |
1970 | |
1971 | s += sprintf(b + s, "TX buffer:\n"); |
1972 | for (i = 0; i <= CEC_TX_MSG_F_OP14; i++) |
1973 | s += sprintf(b + s, "%2d:%2x\n", i, aocec_rd_reg(i)); |
1974 | |
1975 | for (i = 0; i < ARRAY_SIZE(cec_reg_name1); i++) { |
1976 | s += sprintf(b + s, "%s:%2x\n", |
1977 | cec_reg_name1[i], aocec_rd_reg(i + 0x10)); |
1978 | } |
1979 | |
1980 | s += sprintf(b + s, "RX buffer:\n"); |
1981 | for (i = 0; i <= CEC_TX_MSG_F_OP14; i++) |
1982 | s += sprintf(b + s, "%2d:%2x\n", i, aocec_rd_reg(i + 0x80)); |
1983 | |
1984 | for (i = 0; i < ARRAY_SIZE(cec_reg_name2); i++) { |
1985 | s += sprintf(b + s, "%s:%2x\n", |
1986 | cec_reg_name2[i], aocec_rd_reg(i + 0x90)); |
1987 | } |
1988 | return s; |
1989 | } |
1990 | |
1991 | static ssize_t arc_port_show(struct class *cla, |
1992 | struct class_attribute *attr, char *buf) |
1993 | { |
1994 | return sprintf(buf, "%x\n", cec_dev->arc_port); |
1995 | } |
1996 | |
1997 | static ssize_t osd_name_show(struct class *cla, |
1998 | struct class_attribute *attr, char *buf) |
1999 | { |
2000 | return sprintf(buf, "%s\n", cec_dev->cec_info.osd_name); |
2001 | } |
2002 | |
2003 | static ssize_t port_seq_store(struct class *cla, |
2004 | struct class_attribute *attr, |
2005 | const char *buf, size_t count) |
2006 | { |
2007 | unsigned int seq; |
2008 | |
2009 | if (kstrtouint(buf, 16, &seq) != 0) |
2010 | return -EINVAL; |
2011 | |
2012 | CEC_ERR("port_seq:%x\n", seq); |
2013 | cec_dev->port_seq = seq; |
2014 | return count; |
2015 | } |
2016 | |
2017 | static ssize_t port_seq_show(struct class *cla, |
2018 | struct class_attribute *attr, char *buf) |
2019 | { |
2020 | return sprintf(buf, "%x\n", cec_dev->port_seq); |
2021 | } |
2022 | |
2023 | static ssize_t port_status_show(struct class *cla, |
2024 | struct class_attribute *attr, char *buf) |
2025 | { |
2026 | unsigned int tmp; |
2027 | unsigned int tx_hpd; |
2028 | |
2029 | tx_hpd = cec_dev->tx_dev->hpd_state; |
2030 | if (cec_dev->dev_type != CEC_TV_ADDR) { |
2031 | tmp = tx_hpd; |
2032 | return sprintf(buf, "%x\n", tmp); |
2033 | } |
2034 | tmp = hdmirx_rd_top(TOP_HPD_PWR5V); |
2035 | CEC_INFO("TOP_HPD_PWR5V:%x\n", tmp); |
2036 | tmp >>= 20; |
2037 | tmp &= 0xf; |
2038 | tmp |= (tx_hpd << 16); |
2039 | return sprintf(buf, "%x\n", tmp); |
2040 | } |
2041 | |
2042 | static ssize_t pin_status_show(struct class *cla, |
2043 | struct class_attribute *attr, char *buf) |
2044 | { |
2045 | unsigned int tx_hpd; |
2046 | char p; |
2047 | |
2048 | tx_hpd = cec_dev->tx_dev->hpd_state; |
2049 | if (cec_dev->dev_type != CEC_TV_ADDR) { |
2050 | if (!tx_hpd) { |
2051 | pin_status = 0; |
2052 | return sprintf(buf, "%s\n", "disconnected"); |
2053 | } |
2054 | if (pin_status == 0) { |
2055 | p = (cec_dev->cec_info.log_addr << 4) | CEC_TV_ADDR; |
2056 | if (cec_ll_tx(&p, 1) == CEC_FAIL_NONE) |
2057 | return sprintf(buf, "%s\n", "ok"); |
2058 | else |
2059 | return sprintf(buf, "%s\n", "fail"); |
2060 | } else |
2061 | return sprintf(buf, "%s\n", "ok"); |
2062 | } else { |
2063 | return sprintf(buf, "%s\n", pin_status ? "ok" : "fail"); |
2064 | } |
2065 | } |
2066 | |
2067 | static ssize_t physical_addr_show(struct class *cla, |
2068 | struct class_attribute *attr, char *buf) |
2069 | { |
2070 | unsigned int tmp = cec_dev->phy_addr; |
2071 | |
2072 | return sprintf(buf, "%04x\n", tmp); |
2073 | } |
2074 | |
2075 | static ssize_t physical_addr_store(struct class *cla, |
2076 | struct class_attribute *attr, |
2077 | const char *buf, size_t count) |
2078 | { |
2079 | int addr; |
2080 | |
2081 | if (kstrtouint(buf, 16, &addr) != 0) |
2082 | return -EINVAL; |
2083 | |
2084 | if (addr > 0xffff || addr < 0) { |
2085 | CEC_ERR("invalid input:%s\n", buf); |
2086 | phy_addr_test = 0; |
2087 | return -EINVAL; |
2088 | } |
2089 | cec_dev->phy_addr = addr; |
2090 | phy_addr_test = 1; |
2091 | return count; |
2092 | } |
2093 | |
2094 | static ssize_t dbg_en_show(struct class *cla, |
2095 | struct class_attribute *attr, char *buf) |
2096 | { |
2097 | return sprintf(buf, "%x\n", cec_msg_dbg_en); |
2098 | } |
2099 | |
2100 | static ssize_t dbg_en_store(struct class *cla, struct class_attribute *attr, |
2101 | const char *buf, size_t count) |
2102 | { |
2103 | int en; |
2104 | |
2105 | if (kstrtouint(buf, 16, &en) != 0) |
2106 | return -EINVAL; |
2107 | |
2108 | cec_msg_dbg_en = en; |
2109 | return count; |
2110 | } |
2111 | |
2112 | static ssize_t cmd_store(struct class *cla, struct class_attribute *attr, |
2113 | const char *bu, size_t count) |
2114 | { |
2115 | char buf[20] = {}; |
2116 | int tmpbuf[20] = {}; |
2117 | int i; |
2118 | int cnt; |
2119 | |
2120 | cnt = sscanf(bu, "%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x", |
2121 | &tmpbuf[0], &tmpbuf[1], &tmpbuf[2], &tmpbuf[3], |
2122 | &tmpbuf[4], &tmpbuf[5], &tmpbuf[6], &tmpbuf[7], |
2123 | &tmpbuf[8], &tmpbuf[9], &tmpbuf[10], &tmpbuf[11], |
2124 | &tmpbuf[12], &tmpbuf[13], &tmpbuf[14], &tmpbuf[15]); |
2125 | if (cnt < 0) |
2126 | return -EINVAL; |
2127 | if (cnt > 16) |
2128 | cnt = 16; |
2129 | |
2130 | for (i = 0; i < cnt; i++) |
2131 | buf[i] = (char)tmpbuf[i]; |
2132 | |
2133 | /*CEC_ERR("cnt=%d\n", cnt);*/ |
2134 | cec_ll_tx(buf, cnt); |
2135 | return count; |
2136 | } |
2137 | |
2138 | static ssize_t wake_up_show(struct class *cla, |
2139 | struct class_attribute *attr, char *buf) |
2140 | { |
2141 | unsigned int reg = readl(cec_dev->cec_reg + AO_RTI_STATUS_REG1); |
2142 | |
2143 | return sprintf(buf, "%x\n", reg & 0xfffff); |
2144 | } |
2145 | |
2146 | static ssize_t fun_cfg_store(struct class *cla, struct class_attribute *attr, |
2147 | const char *bu, size_t count) |
2148 | { |
2149 | int cnt, val; |
2150 | |
2151 | cnt = kstrtouint(bu, 16, &val); |
2152 | if (cnt < 0 || val > 0xff) |
2153 | return -EINVAL; |
2154 | cec_config(val, 1); |
2155 | if (val == 0) |
2156 | cec_clear_all_logical_addr(ee_cec);/*cec_keep_reset();*/ |
2157 | else |
2158 | cec_pre_init(); |
2159 | return count; |
2160 | } |
2161 | |
2162 | static ssize_t fun_cfg_show(struct class *cla, |
2163 | struct class_attribute *attr, char *buf) |
2164 | { |
2165 | unsigned int reg = cec_config(0, 0); |
2166 | |
2167 | return sprintf(buf, "0x%x\n", reg & 0xff); |
2168 | } |
2169 | |
2170 | static ssize_t cec_version_show(struct class *cla, |
2171 | struct class_attribute *attr, char *buf) |
2172 | { |
2173 | CEC_INFO("driver date:%s\n", CEC_DRIVER_VERSION); |
2174 | return sprintf(buf, "%d\n", cec_dev->cec_info.cec_version); |
2175 | } |
2176 | |
2177 | static ssize_t log_addr_store(struct class *cla, struct class_attribute *attr, |
2178 | const char *bu, size_t count) |
2179 | { |
2180 | int cnt, val; |
2181 | |
2182 | cnt = kstrtoint(bu, 16, &val); |
2183 | if (cnt < 0 || val > 0xf) |
2184 | return -EINVAL; |
2185 | cec_logicaddr_set(val); |
2186 | /* add by hal, to init some data structure */ |
2187 | cec_dev->cec_info.log_addr = val; |
2188 | cec_dev->cec_info.power_status = POWER_ON; |
2189 | |
2190 | return count; |
2191 | } |
2192 | |
2193 | static ssize_t log_addr_show(struct class *cla, |
2194 | struct class_attribute *attr, char *buf) |
2195 | { |
2196 | return sprintf(buf, "0x%x\n", cec_dev->cec_info.log_addr); |
2197 | } |
2198 | |
2199 | static ssize_t dbg_store(struct class *cla, struct class_attribute *attr, |
2200 | const char *bu, size_t count) |
2201 | { |
2202 | const char *delim = " "; |
2203 | char *token; |
2204 | char *cur = (char *)bu; |
2205 | struct dbgflg *dbg = &stdbgflg; |
2206 | unsigned int addr, val; |
2207 | |
2208 | token = strsep(&cur, delim); |
2209 | if (token && strncmp(token, "bypass", 6) == 0) { |
2210 | /*get the second param*/ |
2211 | token = strsep(&cur, delim); |
2212 | /*string to int*/ |
2213 | if (!token || kstrtouint(token, 16, &val) < 0) |
2214 | return count; |
2215 | |
2216 | dbg->hal_cmd_bypass = val ? 1 : 0; |
2217 | CEC_ERR("cmdbypass:%d\n", val); |
2218 | } else if (token && strncmp(token, "dbgen", 5) == 0) { |
2219 | token = strsep(&cur, delim); |
2220 | /*string to int*/ |
2221 | if (!token || kstrtouint(token, 16, &val) < 0) |
2222 | return count; |
2223 | |
2224 | cec_msg_dbg_en = val; |
2225 | CEC_ERR("msg_dbg_en:%d\n", val); |
2226 | } else if (token && strncmp(token, "ra", 2) == 0) { |
2227 | token = strsep(&cur, delim); |
2228 | /*string to int*/ |
2229 | if (!token || kstrtouint(token, 16, &addr) < 0) |
2230 | return count; |
2231 | |
2232 | CEC_ERR("rd ceca reg:0x%x val:0x%x\n", addr, |
2233 | aocec_rd_reg(addr)); |
2234 | } else if (token && strncmp(token, "wa", 2) == 0) { |
2235 | token = strsep(&cur, delim); |
2236 | /*string to int*/ |
2237 | if (!token || kstrtouint(token, 16, &addr) < 0) |
2238 | return count; |
2239 | |
2240 | token = strsep(&cur, delim); |
2241 | /*string to int*/ |
2242 | if (!token || kstrtouint(token, 16, &val) < 0) |
2243 | return count; |
2244 | |
2245 | CEC_ERR("wa ceca reg:0x%x val:0x%x\n", addr, val); |
2246 | aocec_wr_reg(addr, val); |
2247 | } else if (token && strncmp(token, "rb", 2) == 0) { |
2248 | token = strsep(&cur, delim); |
2249 | /*string to int*/ |
2250 | if (!token || kstrtouint(token, 16, &addr) < 0) |
2251 | return count; |
2252 | |
2253 | CEC_ERR("rd cecb reg:0x%x val:0x%x\n", addr, |
2254 | hdmirx_cec_read(addr)); |
2255 | } else if (token && strncmp(token, "wb", 2) == 0) { |
2256 | token = strsep(&cur, delim); |
2257 | /*string to int*/ |
2258 | if (!token || kstrtouint(token, 16, &addr) < 0) |
2259 | return count; |
2260 | |
2261 | token = strsep(&cur, delim); |
2262 | /*string to int*/ |
2263 | if (!token || kstrtouint(token, 16, &val) < 0) |
2264 | return count; |
2265 | |
2266 | CEC_ERR("wb cecb reg:0x%x val:0x%x\n", addr, val); |
2267 | hdmirx_cec_write(addr, val); |
2268 | } else if (token && strncmp(token, "dump", 4) == 0) { |
2269 | dump_reg(); |
2270 | } else if (token && strncmp(token, "status", 6) == 0) { |
2271 | cec_dump_info(); |
2272 | } else if (token && strncmp(token, "rao", 3) == 0) { |
2273 | token = strsep(&cur, delim); |
2274 | /*string to int*/ |
2275 | if (!token || kstrtouint(token, 16, &addr) < 0) |
2276 | return count; |
2277 | |
2278 | val = readl(cec_dev->cec_reg + addr); |
2279 | CEC_ERR("rao addr:0x%x, val:0x%x", val, addr); |
2280 | } else if (token && strncmp(token, "wao", 3) == 0) { |
2281 | token = strsep(&cur, delim); |
2282 | /*string to int*/ |
2283 | if (!token || kstrtouint(token, 16, &addr) < 0) |
2284 | return count; |
2285 | |
2286 | token = strsep(&cur, delim); |
2287 | /*string to int*/ |
2288 | if (!token || kstrtouint(token, 16, &val) < 0) |
2289 | return count; |
2290 | |
2291 | writel(val, cec_dev->cec_reg + addr); |
2292 | CEC_ERR("wao addr:0x%x, val:0x%x", val, addr); |
2293 | } else if (token && strncmp(token, "preinit", 7) == 0) { |
2294 | cec_pre_init(); |
2295 | } else if (token && strncmp(token, "setaddr", 7) == 0) { |
2296 | token = strsep(&cur, delim); |
2297 | /*string to int*/ |
2298 | if (!token || kstrtouint(token, 16, &addr) < 0) |
2299 | return count; |
2300 | |
2301 | cec_logicaddr_set(addr); |
2302 | } else if (token && strncmp(token, "clraddr", 7) == 0) { |
2303 | cec_dev->cec_info.addr_enable = 0; |
2304 | cec_clear_all_logical_addr(ee_cec); |
2305 | } else if (token && strncmp(token, "addaddr", 7) == 0) { |
2306 | token = strsep(&cur, delim); |
2307 | /*string to int*/ |
2308 | if (!token || kstrtouint(token, 16, &addr) < 0) |
2309 | return count; |
2310 | cec_dev->cec_info.addr_enable |= (1 << (addr & 0xf)); |
2311 | cec_logicaddr_add(ee_cec, addr); |
2312 | } else if (token && strncmp(token, "rmaddr", 6) == 0) { |
2313 | token = strsep(&cur, delim); |
2314 | /*string to int*/ |
2315 | if (!token || kstrtouint(token, 16, &addr) < 0) |
2316 | return count; |
2317 | |
2318 | cec_dev->cec_info.addr_enable &= ~(1 << (addr & 0xf)); |
2319 | cec_logicaddr_remove(addr); |
2320 | } else { |
2321 | if (token) |
2322 | CEC_ERR("no cmd:%s\n", token); |
2323 | } |
2324 | |
2325 | return count; |
2326 | } |
2327 | |
2328 | static ssize_t dbg_show(struct class *cla, |
2329 | struct class_attribute *attr, char *buf) |
2330 | { |
2331 | CEC_INFO("dbg_show\n"); |
2332 | return 0; |
2333 | } |
2334 | |
2335 | |
2336 | static struct class_attribute aocec_class_attr[] = { |
2337 | __ATTR_WO(cmd), |
2338 | __ATTR_RO(port_num), |
2339 | __ATTR_RO(osd_name), |
2340 | __ATTR_RO(dump_reg), |
2341 | __ATTR_RO(port_status), |
2342 | __ATTR_RO(pin_status), |
2343 | __ATTR_RO(cec_version), |
2344 | __ATTR_RO(arc_port), |
2345 | __ATTR_RO(wake_up), |
2346 | __ATTR(port_seq, 0664, port_seq_show, port_seq_store), |
2347 | __ATTR(physical_addr, 0664, physical_addr_show, physical_addr_store), |
2348 | __ATTR(vendor_id, 0664, vendor_id_show, vendor_id_store), |
2349 | __ATTR(menu_language, 0664, menu_language_show, menu_language_store), |
2350 | __ATTR(device_type, 0664, device_type_show, device_type_store), |
2351 | __ATTR(dbg_en, 0664, dbg_en_show, dbg_en_store), |
2352 | __ATTR(log_addr, 0664, log_addr_show, log_addr_store), |
2353 | __ATTR(fun_cfg, 0664, fun_cfg_show, fun_cfg_store), |
2354 | __ATTR(dbg, 0664, dbg_show, dbg_store), |
2355 | __ATTR_NULL |
2356 | }; |
2357 | |
2358 | /******************** cec hal interface ***************************/ |
2359 | static int hdmitx_cec_open(struct inode *inode, struct file *file) |
2360 | { |
2361 | if (atomic_add_return(1, &cec_dev->cec_info.open_count)) { |
2362 | cec_dev->cec_info.hal_ctl = 1; |
2363 | /* set default logical addr flag for uboot */ |
2364 | cec_set_reg_bits(AO_DEBUG_REG1, 0xf, 16, 4); |
2365 | } |
2366 | return 0; |
2367 | } |
2368 | |
2369 | static int hdmitx_cec_release(struct inode *inode, struct file *file) |
2370 | { |
2371 | if (!atomic_sub_return(1, &cec_dev->cec_info.open_count)) |
2372 | cec_dev->cec_info.hal_ctl = 0; |
2373 | return 0; |
2374 | } |
2375 | |
2376 | static ssize_t hdmitx_cec_read(struct file *f, char __user *buf, |
2377 | size_t size, loff_t *p) |
2378 | { |
2379 | int ret; |
2380 | |
2381 | if ((cec_dev->hal_flag & (1 << HDMI_OPTION_SYSTEM_CEC_CONTROL))) |
2382 | rx_len = 0; |
2383 | ret = wait_for_completion_timeout(&cec_dev->rx_ok, CEC_FRAME_DELAY); |
2384 | if (ret <= 0) |
2385 | return ret; |
2386 | if (rx_len == 0) |
2387 | return 0; |
2388 | |
2389 | if (copy_to_user(buf, rx_msg, rx_len)) |
2390 | return -EINVAL; |
2391 | return rx_len; |
2392 | } |
2393 | |
2394 | static ssize_t hdmitx_cec_write(struct file *f, const char __user *buf, |
2395 | size_t size, loff_t *p) |
2396 | { |
2397 | unsigned char tempbuf[16] = {}; |
2398 | int ret = CEC_FAIL_OTHER; |
2399 | unsigned int cec_cfg; |
2400 | |
2401 | if (stdbgflg.hal_cmd_bypass) |
2402 | return -EINVAL; |
2403 | |
2404 | if (size > 16) |
2405 | size = 16; |
2406 | if (size <= 0) |
2407 | return -EINVAL; |
2408 | |
2409 | if (copy_from_user(tempbuf, buf, size)) |
2410 | return -EINVAL; |
2411 | |
2412 | cec_cfg = cec_config(0, 0); |
2413 | if (cec_cfg & CEC_FUNC_CFG_CEC_ON) { |
2414 | /*cec module on*/ |
2415 | ret = cec_ll_tx(tempbuf, size); |
2416 | } else { |
2417 | CEC_ERR("err:cec module disabled\n"); |
2418 | } |
2419 | |
2420 | return ret; |
2421 | } |
2422 | |
2423 | static void init_cec_port_info(struct hdmi_port_info *port, |
2424 | struct ao_cec_dev *cec_dev) |
2425 | { |
2426 | unsigned int a, b, c = 0, d, e = 0; |
2427 | unsigned int phy_head = 0xf000, phy_app = 0x1000, phy_addr; |
2428 | struct hdmitx_dev *tx_dev; |
2429 | |
2430 | /* physical address for TV or repeator */ |
2431 | tx_dev = cec_dev->tx_dev; |
2432 | if (tx_dev == NULL || cec_dev->dev_type == CEC_TV_ADDR) { |
2433 | phy_addr = 0; |
2434 | } else if (tx_dev->hdmi_info.vsdb_phy_addr.valid == 1) { |
2435 | /* get phy address from tx module */ |
2436 | a = tx_dev->hdmi_info.vsdb_phy_addr.a; |
2437 | b = tx_dev->hdmi_info.vsdb_phy_addr.b; |
2438 | c = tx_dev->hdmi_info.vsdb_phy_addr.c; |
2439 | d = tx_dev->hdmi_info.vsdb_phy_addr.d; |
2440 | phy_addr = ((a << 12) | (b << 8) | (c << 4) | (d)); |
2441 | } else |
2442 | phy_addr = 0; |
2443 | |
2444 | /* found physical address append for repeator */ |
2445 | for (a = 0; a < 4; a++) { |
2446 | if (phy_addr & phy_head) { |
2447 | phy_head >>= 4; |
2448 | phy_app >>= 4; |
2449 | } else |
2450 | break; |
2451 | } |
2452 | |
2453 | CEC_ERR("%s phy_addr:%x, port num:%x\n", __func__, phy_addr, |
2454 | cec_dev->port_num); |
2455 | CEC_ERR("port_seq=0x%x\n", cec_dev->port_seq); |
2456 | /* init for port info */ |
2457 | for (a = 0; a < sizeof(cec_dev->port_seq) * 2; a++) { |
2458 | /* set port physical address according port sequence */ |
2459 | if (cec_dev->port_seq) { |
2460 | c = (cec_dev->port_seq >> (4 * a)) & 0xf; |
2461 | if (c == 0xf) { /* not used */ |
2462 | CEC_INFO("port %d is not used\n", a); |
2463 | continue; |
2464 | } |
2465 | port[e].physical_address = (c) * phy_app + phy_addr; |
2466 | } else { |
2467 | /* asending order if port_seq is not set */ |
2468 | port[e].physical_address = (a + 1) * phy_app + phy_addr; |
2469 | } |
2470 | |
2471 | /* select input / output port*/ |
2472 | if ((e + cec_dev->output) == cec_dev->port_num) { |
2473 | port[e].physical_address = phy_addr; |
2474 | port[e].port_id = 0; |
2475 | port[e].type = HDMI_OUTPUT; |
2476 | } else { |
2477 | port[e].type = HDMI_INPUT; |
2478 | port[e].port_id = c;/*a + 1; phy port - ui id*/ |
2479 | } |
2480 | port[e].cec_supported = 1; |
2481 | /* set ARC feature according mask */ |
2482 | if (cec_dev->arc_port & (1 << e)) |
2483 | port[e].arc_supported = 1; |
2484 | else |
2485 | port[e].arc_supported = 0; |
2486 | CEC_ERR("portinfo id:%d arc:%d phy:%x,type:%d\n", |
2487 | port[e].port_id, port[e].arc_supported, |
2488 | port[e].physical_address, |
2489 | port[e].type); |
2490 | e++; |
2491 | if (e >= cec_dev->port_num) |
2492 | break; |
2493 | } |
2494 | } |
2495 | |
2496 | |
2497 | void cec_dump_info(void) |
2498 | { |
2499 | struct hdmi_port_info *port; |
2500 | |
2501 | CEC_ERR("driver date:%s\n", CEC_DRIVER_VERSION); |
2502 | CEC_ERR("cec sel:%d\n", ee_cec); |
2503 | CEC_ERR("cec_num:%d\n", cec_dev->cec_num); |
2504 | CEC_ERR("dev_type:%d\n", (unsigned int)cec_dev->dev_type); |
2505 | CEC_ERR("wk_logic_addr:0x%x\n", cec_dev->wakup_data.wk_logic_addr); |
2506 | CEC_ERR("wk_phy_addr:0x%x\n", cec_dev->wakup_data.wk_phy_addr); |
2507 | CEC_ERR("wk_port_id:0x%x\n", cec_dev->wakup_data.wk_port_id); |
2508 | CEC_ERR("wakeup_reason:0x%x\n", cec_dev->wakeup_reason); |
2509 | CEC_ERR("phy_addr:0x%x\n", cec_dev->phy_addr); |
2510 | CEC_ERR("cec_version:0x%x\n", cec_dev->cec_info.cec_version); |
2511 | CEC_ERR("hal_ctl:0x%x\n", cec_dev->cec_info.hal_ctl); |
2512 | CEC_ERR("menu_lang:0x%x\n", cec_dev->cec_info.menu_lang); |
2513 | CEC_ERR("menu_status:0x%x\n", cec_dev->cec_info.menu_status); |
2514 | CEC_ERR("open_count:%d\n", cec_dev->cec_info.open_count.counter); |
2515 | CEC_ERR("vendor_id:0x%x\n", cec_dev->v_data.vendor_id); |
2516 | CEC_ERR("port_num:0x%x\n", cec_dev->port_num); |
2517 | CEC_ERR("output:0x%x\n", cec_dev->output); |
2518 | CEC_ERR("arc_port:0x%x\n", cec_dev->arc_port); |
2519 | CEC_ERR("hal_flag:0x%x\n", cec_dev->hal_flag); |
2520 | CEC_ERR("hpd_state:0x%x\n", cec_dev->tx_dev->hpd_state); |
2521 | CEC_ERR("cec_config:0x%x\n", cec_config(0, 0)); |
2522 | CEC_ERR("log_addr:0x%x\n", cec_dev->cec_info.log_addr); |
2523 | port = kcalloc(cec_dev->port_num, sizeof(*port), GFP_KERNEL); |
2524 | if (port) { |
2525 | init_cec_port_info(port, cec_dev); |
2526 | kfree(port); |
2527 | } |
2528 | |
2529 | if (ee_cec) { |
2530 | CEC_ERR("addrL 0x%x\n", hdmirx_cec_read(DWC_CEC_ADDR_L)); |
2531 | CEC_ERR("addrH 0x%x\n", hdmirx_cec_read(DWC_CEC_ADDR_H)); |
2532 | } else { |
2533 | CEC_ERR("addr0 0x%x\n", aocec_rd_reg(CEC_LOGICAL_ADDR0)); |
2534 | CEC_ERR("addr1 0x%x\n", aocec_rd_reg(CEC_LOGICAL_ADDR1)); |
2535 | CEC_ERR("addr2 0x%x\n", aocec_rd_reg(CEC_LOGICAL_ADDR2)); |
2536 | CEC_ERR("addr3 0x%x\n", aocec_rd_reg(CEC_LOGICAL_ADDR3)); |
2537 | CEC_ERR("addr4 0x%x\n", aocec_rd_reg(CEC_LOGICAL_ADDR4)); |
2538 | } |
2539 | CEC_ERR("addr_enable:0x%x\n", cec_dev->cec_info.addr_enable); |
2540 | } |
2541 | |
2542 | unsigned int cec_get_cur_phy_addr(void) |
2543 | { |
2544 | struct hdmitx_dev *tx_dev; |
2545 | unsigned int a, b, c, d; |
2546 | unsigned int tmp; |
2547 | |
2548 | tx_dev = cec_dev->tx_dev; |
2549 | if (!tx_dev || cec_dev->dev_type == CEC_TV_ADDR) |
2550 | tmp = 0; |
2551 | else { |
2552 | /*hpd attach and wait read edid*/ |
2553 | a = tx_dev->hdmi_info.vsdb_phy_addr.a; |
2554 | b = tx_dev->hdmi_info.vsdb_phy_addr.b; |
2555 | c = tx_dev->hdmi_info.vsdb_phy_addr.c; |
2556 | d = tx_dev->hdmi_info.vsdb_phy_addr.d; |
2557 | tmp = ((a << 12) | (b << 8) | (c << 4) | (d)); |
2558 | } |
2559 | |
2560 | return tmp; |
2561 | } |
2562 | |
2563 | static long hdmitx_cec_ioctl(struct file *f, |
2564 | unsigned int cmd, unsigned long arg) |
2565 | { |
2566 | void __user *argp = (void __user *)arg; |
2567 | unsigned int tmp; |
2568 | struct hdmi_port_info *port; |
2569 | unsigned int a, i = 0; |
2570 | /*struct hdmitx_dev *tx_dev;*/ |
2571 | /*unsigned int tx_hpd;*/ |
2572 | |
2573 | mutex_lock(&cec_dev->cec_ioctl_mutex); |
2574 | switch (cmd) { |
2575 | case CEC_IOC_GET_PHYSICAL_ADDR: |
2576 | check_physical_addr_valid(20); |
2577 | /* physical address for TV or repeator */ |
2578 | tmp = cec_get_cur_phy_addr(); |
2579 | if ((cec_dev->dev_type != CEC_TV_ADDR) && (tmp != 0) && |
2580 | tmp != 0xffff) |
2581 | cec_dev->phy_addr = tmp; |
2582 | |
2583 | if (!phy_addr_test) { |
2584 | cec_phyaddr_config(cec_dev->phy_addr, 1); |
2585 | CEC_INFO("type %d, save phy_addr:0x%x\n", |
2586 | (unsigned int)cec_dev->dev_type, |
2587 | cec_dev->phy_addr); |
2588 | } else |
2589 | tmp = cec_dev->phy_addr; |
2590 | |
2591 | if (copy_to_user(argp, &cec_dev->phy_addr, _IOC_SIZE(cmd))) { |
2592 | mutex_unlock(&cec_dev->cec_ioctl_mutex); |
2593 | return -EINVAL; |
2594 | } |
2595 | break; |
2596 | |
2597 | case CEC_IOC_GET_VERSION: |
2598 | tmp = cec_dev->cec_info.cec_version; |
2599 | if (copy_to_user(argp, &tmp, _IOC_SIZE(cmd))) { |
2600 | mutex_unlock(&cec_dev->cec_ioctl_mutex); |
2601 | return -EINVAL; |
2602 | } |
2603 | break; |
2604 | |
2605 | case CEC_IOC_GET_VENDOR_ID: |
2606 | tmp = cec_dev->v_data.vendor_id; |
2607 | if (copy_to_user(argp, &tmp, _IOC_SIZE(cmd))) { |
2608 | mutex_unlock(&cec_dev->cec_ioctl_mutex); |
2609 | return -EINVAL; |
2610 | } |
2611 | break; |
2612 | |
2613 | case CEC_IOC_GET_PORT_NUM: |
2614 | tmp = cec_dev->port_num; |
2615 | if (copy_to_user(argp, &tmp, _IOC_SIZE(cmd))) { |
2616 | mutex_unlock(&cec_dev->cec_ioctl_mutex); |
2617 | return -EINVAL; |
2618 | } |
2619 | break; |
2620 | |
2621 | case CEC_IOC_GET_PORT_INFO: |
2622 | port = kcalloc(cec_dev->port_num, sizeof(*port), GFP_KERNEL); |
2623 | if (!port) { |
2624 | CEC_ERR("no memory\n"); |
2625 | mutex_unlock(&cec_dev->cec_ioctl_mutex); |
2626 | return -EINVAL; |
2627 | } |
2628 | check_physical_addr_valid(20); /*delay time:20 x 100ms*/ |
2629 | init_cec_port_info(port, cec_dev); |
2630 | if (copy_to_user(argp, port, sizeof(*port) * |
2631 | cec_dev->port_num)) |
2632 | CEC_ERR("err get port info\n"); |
2633 | |
2634 | kfree(port); |
2635 | break; |
2636 | |
2637 | case CEC_IOC_SET_OPTION_WAKEUP: |
2638 | tmp = cec_config(0, 0); |
2639 | if (arg) |
2640 | tmp |= CEC_FUNC_CFG_AUTO_POWER_ON; |
2641 | else |
2642 | tmp &= ~(CEC_FUNC_CFG_AUTO_POWER_ON); |
2643 | cec_config(tmp, 1); |
2644 | break; |
2645 | |
2646 | case CEC_IOC_SET_AUTO_DEVICE_OFF: |
2647 | tmp = cec_config(0, 0); |
2648 | if (arg) |
2649 | tmp |= CEC_FUNC_CFG_AUTO_STANDBY; |
2650 | else |
2651 | tmp &= ~(CEC_FUNC_CFG_AUTO_STANDBY); |
2652 | cec_config(tmp, 1); |
2653 | break; |
2654 | |
2655 | case CEC_IOC_SET_OPTION_ENALBE_CEC: |
2656 | a = cec_config(0, 0); |
2657 | if (arg) |
2658 | a |= CEC_FUNC_CFG_CEC_ON; |
2659 | else |
2660 | a &= ~(CEC_FUNC_CFG_CEC_ON); |
2661 | cec_config(a, 1); |
2662 | |
2663 | tmp = (1 << HDMI_OPTION_ENABLE_CEC); |
2664 | if (arg) { |
2665 | cec_dev->hal_flag |= tmp; |
2666 | cec_pre_init(); |
2667 | } else { |
2668 | cec_dev->hal_flag &= ~(tmp); |
2669 | CEC_INFO("disable CEC\n"); |
2670 | /*cec_keep_reset();*/ |
2671 | cec_clear_all_logical_addr(ee_cec); |
2672 | } |
2673 | break; |
2674 | |
2675 | case CEC_IOC_SET_OPTION_SYS_CTRL: |
2676 | tmp = (1 << HDMI_OPTION_SYSTEM_CEC_CONTROL); |
2677 | if (arg) { |
2678 | cec_dev->hal_flag |= tmp; |
2679 | /*cec_config(CEC_FUNC_CFG_ALL, 1);*/ |
2680 | } else |
2681 | cec_dev->hal_flag &= ~(tmp); |
2682 | cec_dev->hal_flag |= (1 << HDMI_OPTION_SERVICE_FLAG); |
2683 | break; |
2684 | |
2685 | case CEC_IOC_SET_OPTION_SET_LANG: |
2686 | cec_dev->cec_info.menu_lang = arg; |
2687 | break; |
2688 | |
2689 | case CEC_IOC_GET_CONNECT_STATUS: |
2690 | if (copy_from_user(&a, argp, _IOC_SIZE(cmd))) { |
2691 | mutex_unlock(&cec_dev->cec_ioctl_mutex); |
2692 | return -EINVAL; |
2693 | } |
2694 | |
2695 | /* mixed for rx & tx */ |
2696 | /* a is current port idx, 0: tx device */ |
2697 | if (a != 0) { |
2698 | tmp = hdmirx_get_connect_info() & 0xF; |
2699 | for (i = 0; i < CEC_PHY_PORT_NUM; i++) { |
2700 | if (((cec_dev->port_seq >> i*4) & 0xF) == a) |
2701 | break; |
2702 | } |
2703 | //CEC_INFO("phy port:%d, ui port:%d\n", i, a); |
2704 | |
2705 | if ((tmp & (1 << i)) && (a != 0xF)) |
2706 | tmp = 1; |
2707 | else |
2708 | tmp = 0; |
2709 | } else { |
2710 | tmp = cec_dev->tx_dev->hpd_state; |
2711 | } |
2712 | /*CEC_ERR("port id:%d, sts:%d\n", a, tmp);*/ |
2713 | if (copy_to_user(argp, &tmp, _IOC_SIZE(cmd))) { |
2714 | mutex_unlock(&cec_dev->cec_ioctl_mutex); |
2715 | return -EINVAL; |
2716 | } |
2717 | break; |
2718 | |
2719 | case CEC_IOC_ADD_LOGICAL_ADDR: |
2720 | /* tmp = arg & 0xf;*/ |
2721 | /*cec_logicaddr_set(tmp);*/ |
2722 | cec_logicaddr_add(ee_cec, arg & 0xf); |
2723 | cec_dev->cec_info.addr_enable |= (1 << (arg & 0xf)); |
2724 | |
2725 | /* add by hal, to init some data structure */ |
2726 | cec_dev->cec_info.log_addr = tmp; |
2727 | cec_dev->cec_info.power_status = POWER_ON; |
2728 | cec_dev->cec_info.vendor_id = cec_dev->v_data.vendor_id; |
2729 | strncpy(cec_dev->cec_info.osd_name, |
2730 | cec_dev->v_data.cec_osd_string, 14); |
2731 | break; |
2732 | |
2733 | case CEC_IOC_CLR_LOGICAL_ADDR: |
2734 | cec_clear_all_logical_addr(ee_cec); |
2735 | cec_dev->cec_info.addr_enable = 0; |
2736 | break; |
2737 | |
2738 | case CEC_IOC_CLR_LOGICAL_ADDR_PLUS: |
2739 | cec_logicaddr_remove(arg & 0xf); |
2740 | cec_dev->cec_info.addr_enable &= ~(1 << (arg & 0xf)); |
2741 | break; |
2742 | |
2743 | case CEC_IOC_SET_DEV_TYPE: |
2744 | cec_dev->dev_type = arg; |
2745 | break; |
2746 | |
2747 | case CEC_IOC_SET_ARC_ENABLE: |
2748 | CEC_INFO("Ioc set arc pin\n"); |
2749 | cec_enable_arc_pin(arg); |
2750 | break; |
2751 | |
2752 | case CEC_IOC_GET_BOOT_ADDR: |
2753 | tmp = (cec_dev->wakup_data.wk_logic_addr << 16) | |
2754 | cec_dev->wakup_data.wk_phy_addr; |
2755 | CEC_ERR("Boot addr:%#x\n", (unsigned int)tmp); |
2756 | if (copy_to_user(argp, &tmp, _IOC_SIZE(cmd))) { |
2757 | mutex_unlock(&cec_dev->cec_ioctl_mutex); |
2758 | return -EINVAL; |
2759 | } |
2760 | break; |
2761 | |
2762 | case CEC_IOC_GET_BOOT_REASON: |
2763 | tmp = cec_dev->wakeup_reason; |
2764 | CEC_ERR("Boot reason:%#x\n", (unsigned int)tmp); |
2765 | if (copy_to_user(argp, &tmp, _IOC_SIZE(cmd))) { |
2766 | mutex_unlock(&cec_dev->cec_ioctl_mutex); |
2767 | return -EINVAL; |
2768 | } |
2769 | break; |
2770 | |
2771 | default: |
2772 | CEC_ERR("error ioctrl\n"); |
2773 | break; |
2774 | } |
2775 | mutex_unlock(&cec_dev->cec_ioctl_mutex); |
2776 | return 0; |
2777 | } |
2778 | |
2779 | #ifdef CONFIG_COMPAT |
2780 | static long hdmitx_cec_compat_ioctl(struct file *f, |
2781 | unsigned int cmd, unsigned long arg) |
2782 | { |
2783 | arg = (unsigned long)compat_ptr(arg); |
2784 | return hdmitx_cec_ioctl(f, cmd, arg); |
2785 | } |
2786 | #endif |
2787 | |
2788 | /* for improve rw permission */ |
2789 | static char *aml_cec_class_devnode(struct device *dev, umode_t *mode) |
2790 | { |
2791 | if (mode) { |
2792 | *mode = 0666; |
2793 | CEC_INFO("mode is %x\n", *mode); |
2794 | } else |
2795 | CEC_INFO("mode is null\n"); |
2796 | return NULL; |
2797 | } |
2798 | |
2799 | static struct class aocec_class = { |
2800 | .name = CEC_DEV_NAME, |
2801 | .class_attrs = aocec_class_attr, |
2802 | .devnode = aml_cec_class_devnode, |
2803 | }; |
2804 | |
2805 | |
2806 | static const struct file_operations hdmitx_cec_fops = { |
2807 | .owner = THIS_MODULE, |
2808 | .open = hdmitx_cec_open, |
2809 | .read = hdmitx_cec_read, |
2810 | .write = hdmitx_cec_write, |
2811 | .release = hdmitx_cec_release, |
2812 | .unlocked_ioctl = hdmitx_cec_ioctl, |
2813 | #ifdef CONFIG_COMPAT |
2814 | .compat_ioctl = hdmitx_cec_compat_ioctl, |
2815 | #endif |
2816 | }; |
2817 | |
2818 | /************************ cec high level code *****************************/ |
2819 | #ifdef CONFIG_HAS_EARLYSUSPEND |
2820 | static void aocec_early_suspend(struct early_suspend *h) |
2821 | { |
2822 | /*unsigned int tempaddr;*/ |
2823 | |
2824 | cec_dev->cec_suspend = CEC_EARLY_SUSPEND; |
2825 | #if 0 |
2826 | tempaddr = cec_get_cur_phy_addr(); |
2827 | if ((cec_dev->dev_type != CEC_TV_ADDR) && (tempaddr != 0) && |
2828 | tempaddr != 0xffff) |
2829 | cec_dev->phy_addr = tempaddr; |
2830 | CEC_ERR("%s sts:%d type:0x%x, phyaddr:0x%x (0x%x)\n", __func__, |
2831 | cec_dev->cec_suspend, (unsigned int)cec_dev->dev_type, |
2832 | cec_dev->phy_addr, tempaddr); |
2833 | if ((cec_dev->dev_type != CEC_TV_ADDR) && (cec_dev->phy_addr == 0)) { |
2834 | CEC_ERR("err phyaddr 0\n"); |
2835 | cec_dev->phy_addr = 0x1000; |
2836 | } |
2837 | cec_phyaddr_config(cec_dev->phy_addr, 1); |
2838 | #endif |
2839 | CEC_INFO("%s, suspend:%d\n", __func__, cec_dev->cec_suspend); |
2840 | } |
2841 | |
2842 | static void aocec_late_resume(struct early_suspend *h) |
2843 | { |
2844 | cec_dev->cec_suspend = CEC_POWER_ON; |
2845 | CEC_INFO("%s, suspend:%d\n", __func__, cec_dev->cec_suspend); |
2846 | |
2847 | } |
2848 | #endif |
2849 | |
2850 | #ifdef CONFIG_OF |
2851 | static const struct cec_platform_data_s cec_gxl_data = { |
2852 | .line_reg = 0, |
2853 | .line_bit = 8, |
2854 | .ee_to_ao = 0, |
2855 | }; |
2856 | |
2857 | static const struct cec_platform_data_s cec_txlx_data = { |
2858 | .line_reg = 0, |
2859 | .line_bit = 7, |
2860 | .ee_to_ao = 1, |
2861 | }; |
2862 | |
2863 | static const struct cec_platform_data_s cec_g12a_data = { |
2864 | .line_reg = 1, |
2865 | .line_bit = 3, |
2866 | .ee_to_ao = 1, |
2867 | }; |
2868 | |
2869 | static const struct cec_platform_data_s cec_txl_data = { |
2870 | .line_reg = 0, |
2871 | .line_bit = 7, |
2872 | .ee_to_ao = 0, |
2873 | }; |
2874 | |
2875 | static const struct of_device_id aml_cec_dt_match[] = { |
2876 | { |
2877 | .compatible = "amlogic, amlogic-aocec", |
2878 | .data = &cec_gxl_data, |
2879 | }, |
2880 | { |
2881 | .compatible = "amlogic, aocec-txlx", |
2882 | .data = &cec_txlx_data, |
2883 | }, |
2884 | { |
2885 | .compatible = "amlogic, aocec-g12a", |
2886 | .data = &cec_g12a_data, |
2887 | }, |
2888 | { |
2889 | .compatible = "amlogic, aocec-txl", |
2890 | .data = &cec_txl_data, |
2891 | }, |
2892 | }; |
2893 | #endif |
2894 | |
2895 | static void cec_node_val_init(void) |
2896 | { |
2897 | /* initial main logical address */ |
2898 | cec_dev->cec_info.log_addr = 0; |
2899 | /* all logical address disable */ |
2900 | cec_dev->cec_info.addr_enable = 0; |
2901 | cec_dev->cec_info.open_count.counter = 0; |
2902 | } |
2903 | |
2904 | static int aml_cec_probe(struct platform_device *pdev) |
2905 | { |
2906 | struct device *cdev; |
2907 | int ret = 0; |
2908 | const struct of_device_id *of_id; |
2909 | #ifdef CONFIG_OF |
2910 | struct device_node *node = pdev->dev.of_node; |
2911 | int irq_idx = 0, r; |
2912 | const char *irq_name = NULL; |
2913 | struct pinctrl *pin; |
2914 | struct vendor_info_data *vend; |
2915 | struct resource *res; |
2916 | resource_size_t *base; |
2917 | #endif |
2918 | |
2919 | cec_dev = devm_kzalloc(&pdev->dev, sizeof(struct ao_cec_dev), |
2920 | GFP_KERNEL); |
2921 | if (IS_ERR(cec_dev)) { |
2922 | dev_err(&pdev->dev, "device malloc err!\n"); |
2923 | ret = -ENOMEM; |
2924 | goto tag_cec_devm_err; |
2925 | } |
2926 | |
2927 | /*will replace by CEC_IOC_SET_DEV_TYPE*/ |
2928 | cec_dev->dev_type = CEC_PLAYBACK_DEVICE_1_ADDR; |
2929 | cec_dev->dbg_dev = &pdev->dev; |
2930 | cec_dev->tx_dev = get_hdmitx_device(); |
2931 | cec_dev->cpu_type = get_cpu_type(); |
2932 | cec_dev->node = pdev->dev.of_node; |
2933 | phy_addr_test = 0; |
2934 | CEC_ERR("cec driver date:%s\n", CEC_DRIVER_VERSION); |
2935 | cec_dbg_init(); |
2936 | /* cdev registe */ |
2937 | r = class_register(&aocec_class); |
2938 | if (r) { |
2939 | CEC_ERR("regist class failed\n"); |
2940 | ret = -EINVAL; |
2941 | goto tag_cec_class_reg; |
2942 | } |
2943 | pdev->dev.class = &aocec_class; |
2944 | r = register_chrdev(0, CEC_DEV_NAME, |
2945 | &hdmitx_cec_fops); |
2946 | if (r < 0) { |
2947 | CEC_ERR("alloc chrdev failed\n"); |
2948 | ret = -EINVAL; |
2949 | goto tag_cec_chr_reg_err; |
2950 | } |
2951 | cec_dev->cec_info.dev_no = r; |
2952 | CEC_INFO("alloc chrdev %x\n", cec_dev->cec_info.dev_no); |
2953 | cdev = device_create(&aocec_class, &pdev->dev, |
2954 | MKDEV(cec_dev->cec_info.dev_no, 0), |
2955 | NULL, CEC_DEV_NAME); |
2956 | if (IS_ERR(cdev)) { |
2957 | CEC_ERR("create chrdev failed, dev:%p\n", cdev); |
2958 | ret = -EINVAL; |
2959 | goto tag_cec_device_create_err; |
2960 | } |
2961 | |
2962 | /*get compatible matched device, to get chip related data*/ |
2963 | of_id = of_match_device(aml_cec_dt_match, &pdev->dev); |
2964 | if (of_id != NULL) |
2965 | cec_dev->plat_data = (struct cec_platform_data_s *)of_id->data; |
2966 | else |
2967 | CEC_ERR("unable to get matched device\n"); |
2968 | |
2969 | cec_node_val_init(); |
2970 | init_completion(&cec_dev->rx_ok); |
2971 | init_completion(&cec_dev->tx_ok); |
2972 | mutex_init(&cec_dev->cec_mutex); |
2973 | mutex_init(&cec_dev->cec_ioctl_mutex); |
2974 | spin_lock_init(&cec_dev->cec_reg_lock); |
2975 | cec_dev->cec_thread = create_workqueue("cec_work"); |
2976 | if (cec_dev->cec_thread == NULL) { |
2977 | CEC_INFO("create work queue failed\n"); |
2978 | ret = -EFAULT; |
2979 | goto tag_cec_threat_err; |
2980 | } |
2981 | INIT_DELAYED_WORK(&cec_dev->cec_work, cec_task); |
2982 | cec_dev->cec_info.remote_cec_dev = input_allocate_device(); |
2983 | if (!cec_dev->cec_info.remote_cec_dev) { |
2984 | CEC_INFO("No enough memory\n"); |
2985 | ret = -ENOMEM; |
2986 | goto tag_cec_alloc_input_err; |
2987 | } |
2988 | |
2989 | cec_dev->cec_info.remote_cec_dev->name = "cec_input"; |
2990 | |
2991 | cec_dev->cec_info.remote_cec_dev->evbit[0] = BIT_MASK(EV_KEY); |
2992 | cec_dev->cec_info.remote_cec_dev->keybit[BIT_WORD(BTN_0)] = |
2993 | BIT_MASK(BTN_0); |
2994 | cec_dev->cec_info.remote_cec_dev->id.bustype = BUS_ISA; |
2995 | cec_dev->cec_info.remote_cec_dev->id.vendor = 0x1b8e; |
2996 | cec_dev->cec_info.remote_cec_dev->id.product = 0x0cec; |
2997 | cec_dev->cec_info.remote_cec_dev->id.version = 0x0001; |
2998 | |
2999 | set_bit(KEY_POWER, cec_dev->cec_info.remote_cec_dev->keybit); |
3000 | |
3001 | if (input_register_device(cec_dev->cec_info.remote_cec_dev)) { |
3002 | CEC_INFO("Failed to register device\n"); |
3003 | input_free_device(cec_dev->cec_info.remote_cec_dev); |
3004 | } |
3005 | |
3006 | #ifdef CONFIG_OF |
3007 | /* if using EE CEC */ |
3008 | if (of_property_read_bool(node, "ee_cec")) |
3009 | ee_cec = 1; |
3010 | else |
3011 | ee_cec = 0; |
3012 | CEC_ERR("using cec:%d\n", ee_cec); |
3013 | /* pinmux set */ |
3014 | if (of_get_property(node, "pinctrl-names", NULL)) { |
3015 | pin = devm_pinctrl_get(&pdev->dev); |
3016 | /*get sleep state*/ |
3017 | cec_dev->dbg_dev->pins->sleep_state = |
3018 | pinctrl_lookup_state(pin, "cec_pin_sleep"); |
3019 | if (IS_ERR(cec_dev->dbg_dev->pins->sleep_state)) |
3020 | CEC_ERR("get sleep state error!\n"); |
3021 | /*get active state*/ |
3022 | if (ee_cec) { |
3023 | cec_dev->dbg_dev->pins->default_state = |
3024 | pinctrl_lookup_state(pin, "hdmitx_aocecb"); |
3025 | if (IS_ERR(cec_dev->dbg_dev->pins->default_state)) { |
3026 | CEC_ERR("get aocecb error!\n"); |
3027 | cec_dev->dbg_dev->pins->default_state = |
3028 | pinctrl_lookup_state(pin, "default"); |
3029 | if (IS_ERR( |
3030 | cec_dev->dbg_dev->pins->default_state)) |
3031 | CEC_ERR("get default error0\n"); |
3032 | CEC_ERR("use default cec\n"); |
3033 | /*force use default*/ |
3034 | ee_cec = 0; |
3035 | } |
3036 | } else { |
3037 | cec_dev->dbg_dev->pins->default_state = |
3038 | pinctrl_lookup_state(pin, "default"); |
3039 | if (IS_ERR(cec_dev->dbg_dev->pins->default_state)) |
3040 | CEC_ERR("get default error1!\n"); |
3041 | } |
3042 | /*select pin state*/ |
3043 | ret = pinctrl_pm_select_default_state(&pdev->dev); |
3044 | if (ret > 0) |
3045 | CEC_ERR("select state error:0x%x\n", ret); |
3046 | } |
3047 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ao_exit"); |
3048 | if (res) { |
3049 | base = devm_ioremap(&pdev->dev, res->start, |
3050 | res->end - res->start); |
3051 | if (!base) { |
3052 | CEC_ERR("Unable to map ao_exit base\n"); |
3053 | goto tag_cec_reg_map_err; |
3054 | } |
3055 | cec_dev->exit_reg = (void *)base; |
3056 | } else |
3057 | CEC_ERR("no ao_exit regs\n") |
3058 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ao"); |
3059 | if (res) { |
3060 | base = devm_ioremap(&pdev->dev, res->start, |
3061 | res->end - res->start); |
3062 | if (!base) { |
3063 | CEC_ERR("Unable to map ao base\n"); |
3064 | goto tag_cec_reg_map_err; |
3065 | } |
3066 | cec_dev->cec_reg = (void *)base; |
3067 | } else { |
3068 | CEC_ERR("no ao regs\n"); |
3069 | goto tag_cec_reg_map_err; |
3070 | } |
3071 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmirx"); |
3072 | if (res) { |
3073 | base = devm_ioremap(&pdev->dev, res->start, |
3074 | res->end - res->start); |
3075 | if (!base) { |
3076 | CEC_ERR("Unable to map hdmirx base\n"); |
3077 | goto tag_cec_reg_map_err; |
3078 | } |
3079 | cec_dev->hdmi_rxreg = (void *)base; |
3080 | } else |
3081 | CEC_ERR("no hdmirx regs\n") |
3082 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hhi"); |
3083 | if (res) { |
3084 | base = devm_ioremap(&pdev->dev, res->start, |
3085 | res->end - res->start); |
3086 | if (!base) { |
3087 | CEC_ERR("Unable to map hhi base\n"); |
3088 | goto tag_cec_reg_map_err; |
3089 | } |
3090 | cec_dev->hhi_reg = (void *)base; |
3091 | } else |
3092 | CEC_ERR("no hhi regs\n"); |
3093 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "periphs"); |
3094 | if (res) { |
3095 | base = devm_ioremap(&pdev->dev, res->start, |
3096 | res->end - res->start); |
3097 | if (!base) { |
3098 | CEC_ERR("Unable to map periphs base\n"); |
3099 | goto tag_cec_reg_map_err; |
3100 | } |
3101 | cec_dev->periphs_reg = (void *)base; |
3102 | } else |
3103 | CEC_ERR("no periphs regs\n") |
3104 | r = of_property_read_u32(node, "port_num", &(cec_dev->port_num)); |
3105 | if (r) { |
3106 | CEC_ERR("not find 'port_num'\n"); |
3107 | cec_dev->port_num = 1; |
3108 | } |
3109 | r = of_property_read_u32(node, "arc_port_mask", &(cec_dev->arc_port)); |
3110 | if (r) { |
3111 | CEC_ERR("not find 'arc_port_mask'\n"); |
3112 | cec_dev->arc_port = 0; |
3113 | } |
3114 | r = of_property_read_u32(node, "output", &(cec_dev->output)); |
3115 | if (r) { |
3116 | CEC_ERR("not find 'output'\n"); |
3117 | cec_dev->output = 0; |
3118 | } |
3119 | vend = &cec_dev->v_data; |
3120 | r = of_property_read_string(node, "vendor_name", |
3121 | (const char **)&(vend->vendor_name)); |
3122 | if (r) |
3123 | CEC_INFO("not find vendor name\n"); |
3124 | |
3125 | r = of_property_read_u32(node, "vendor_id", &(vend->vendor_id)); |
3126 | if (r) |
3127 | CEC_INFO("not find vendor id\n"); |
3128 | |
3129 | r = of_property_read_string(node, "product_desc", |
3130 | (const char **)&(vend->product_desc)); |
3131 | if (r) |
3132 | CEC_INFO("not find product desc\n"); |
3133 | |
3134 | r = of_property_read_string(node, "cec_osd_string", |
3135 | (const char **)&(vend->cec_osd_string)); |
3136 | if (r) { |
3137 | CEC_INFO("not find cec osd string\n"); |
3138 | strcpy(vend->cec_osd_string, "AML TV/BOX"); |
3139 | } |
3140 | r = of_property_read_u32(node, "cec_version", |
3141 | &(cec_dev->cec_info.cec_version)); |
3142 | if (r) { |
3143 | /* default set to 2.0 */ |
3144 | CEC_INFO("not find cec_version\n"); |
3145 | cec_dev->cec_info.cec_version = CEC_VERSION_14A; |
3146 | } |
3147 | |
3148 | /* irq set */ |
3149 | cec_irq_enable(false); |
3150 | if (of_irq_count(node) > 1) { |
3151 | if (ee_cec) |
3152 | irq_idx = of_irq_get(node, 0); |
3153 | else |
3154 | irq_idx = of_irq_get(node, 1); |
3155 | } else { |
3156 | irq_idx = of_irq_get(node, 0); |
3157 | } |
3158 | cec_dev->irq_cec = irq_idx; |
3159 | CEC_ERR("irq cnt:%d,cur no:%d\n", of_irq_count(node), irq_idx); |
3160 | if (of_get_property(node, "interrupt-names", NULL)) { |
3161 | r = of_property_read_string(node, "interrupt-names", &irq_name); |
3162 | if (!r && !ee_cec) { |
3163 | r = request_irq(irq_idx, &ceca_isr, IRQF_SHARED, |
3164 | irq_name, (void *)cec_dev); |
3165 | if (r < 0) |
3166 | CEC_INFO("aocec irq request fail\n"); |
3167 | } |
3168 | if (!r && ee_cec) { |
3169 | r = request_irq(irq_idx, &cecb_isr, IRQF_SHARED, |
3170 | irq_name, (void *)cec_dev); |
3171 | if (r < 0) |
3172 | CEC_INFO("cecb irq request fail\n"); |
3173 | } |
3174 | } |
3175 | #endif |
3176 | |
3177 | if (!ee_cec) { |
3178 | last_cec_msg = devm_kzalloc(&pdev->dev, |
3179 | sizeof(*last_cec_msg), GFP_KERNEL); |
3180 | if (!last_cec_msg) { |
3181 | CEC_ERR("allocate last_cec_msg failed\n"); |
3182 | ret = -ENOMEM; |
3183 | goto tag_cec_msg_alloc_err; |
3184 | } |
3185 | } |
3186 | |
3187 | #ifdef CONFIG_HAS_EARLYSUSPEND |
3188 | aocec_suspend_handler.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN - 20; |
3189 | aocec_suspend_handler.suspend = aocec_early_suspend; |
3190 | aocec_suspend_handler.resume = aocec_late_resume; |
3191 | aocec_suspend_handler.param = cec_dev; |
3192 | register_early_suspend(&aocec_suspend_handler); |
3193 | #endif |
3194 | hrtimer_init(&start_bit_check, CLOCK_MONOTONIC, HRTIMER_MODE_REL); |
3195 | start_bit_check.function = cec_line_check; |
3196 | /* for init */ |
3197 | cec_pre_init(); |
3198 | /* default enable all function*/ |
3199 | cec_config(CEC_FUNC_CFG_ALL, 1); |
3200 | queue_delayed_work(cec_dev->cec_thread, &cec_dev->cec_work, 0); |
3201 | scpi_get_wakeup_reason(&cec_dev->wakeup_reason); |
3202 | CEC_ERR("wakeup_reason:0x%x\n", cec_dev->wakeup_reason); |
3203 | scpi_get_cec_val(SCPI_CMD_GET_CEC1, |
3204 | (unsigned int *)&cec_dev->wakup_data); |
3205 | scpi_get_cec_val(SCPI_CMD_GET_CEC2, &r); |
3206 | CEC_ERR("cev val1: %#x;val2: %#x\n", |
3207 | *((unsigned int *)&cec_dev->wakup_data), r); |
3208 | CEC_ERR("%s success end\n", __func__); |
3209 | return 0; |
3210 | |
3211 | tag_cec_msg_alloc_err: |
3212 | free_irq(cec_dev->irq_cec, (void *)cec_dev); |
3213 | tag_cec_reg_map_err: |
3214 | input_free_device(cec_dev->cec_info.remote_cec_dev); |
3215 | tag_cec_alloc_input_err: |
3216 | destroy_workqueue(cec_dev->cec_thread); |
3217 | tag_cec_threat_err: |
3218 | device_destroy(&aocec_class, |
3219 | MKDEV(cec_dev->cec_info.dev_no, 0)); |
3220 | tag_cec_device_create_err: |
3221 | unregister_chrdev(cec_dev->cec_info.dev_no, CEC_DEV_NAME); |
3222 | tag_cec_chr_reg_err: |
3223 | class_unregister(&aocec_class); |
3224 | tag_cec_class_reg: |
3225 | devm_kfree(&pdev->dev, cec_dev); |
3226 | tag_cec_devm_err: |
3227 | return ret; |
3228 | } |
3229 | |
3230 | static int aml_cec_remove(struct platform_device *pdev) |
3231 | { |
3232 | CEC_INFO("cec uninit!\n"); |
3233 | free_irq(cec_dev->irq_cec, (void *)cec_dev); |
3234 | kfree(last_cec_msg); |
3235 | |
3236 | if (cec_dev->cec_thread) { |
3237 | cancel_delayed_work_sync(&cec_dev->cec_work); |
3238 | destroy_workqueue(cec_dev->cec_thread); |
3239 | } |
3240 | input_unregister_device(cec_dev->cec_info.remote_cec_dev); |
3241 | unregister_chrdev(cec_dev->cec_info.dev_no, CEC_DEV_NAME); |
3242 | class_unregister(&aocec_class); |
3243 | kfree(cec_dev); |
3244 | return 0; |
3245 | } |
3246 | |
3247 | #ifdef CONFIG_PM |
3248 | static int aml_cec_pm_prepare(struct device *dev) |
3249 | { |
3250 | cec_dev->cec_suspend = CEC_DEEP_SUSPEND; |
3251 | CEC_INFO("%s, cec_suspend:%d\n", __func__, cec_dev->cec_suspend); |
3252 | return 0; |
3253 | } |
3254 | |
3255 | static void aml_cec_pm_complete(struct device *dev) |
3256 | { |
3257 | int exit = 0; |
3258 | |
3259 | if (cec_dev->exit_reg) { |
3260 | exit = readl(cec_dev->exit_reg); |
3261 | CEC_INFO("wake up flag:%x\n", exit); |
3262 | } |
3263 | if (((exit >> 28) & 0xf) == CEC_WAKEUP) |
3264 | cec_key_report(0); |
3265 | } |
3266 | |
3267 | static int aml_cec_suspend_noirq(struct device *dev) |
3268 | { |
3269 | int ret = 0; |
3270 | /*unsigned int tempaddr;*/ |
3271 | |
3272 | CEC_INFO("cec suspend noirq\n"); |
3273 | #if 0 |
3274 | tempaddr = cec_get_cur_phy_addr(); |
3275 | if (cec_dev->dev_type != CEC_TV_ADDR && (tempaddr != 0) && |
3276 | tempaddr != 0xffff) |
3277 | cec_dev->phy_addr = tempaddr; |
3278 | CEC_ERR("%s type:0x%x phyaddr:0x%x(0x%x)\n", __func__, |
3279 | (unsigned int)cec_dev->dev_type, |
3280 | cec_dev->phy_addr, tempaddr); |
3281 | if ((cec_dev->dev_type != CEC_TV_ADDR) && (cec_dev->phy_addr == 0)) { |
3282 | CEC_ERR("err phyaddr 0\n"); |
3283 | cec_dev->phy_addr = 0x1000; |
3284 | } |
3285 | cec_phyaddr_config(cec_dev->phy_addr, 1); |
3286 | #endif |
3287 | cec_clear_all_logical_addr(ee_cec); |
3288 | |
3289 | if (!IS_ERR(cec_dev->dbg_dev->pins->sleep_state)) |
3290 | ret = pinctrl_pm_select_sleep_state(cec_dev->dbg_dev); |
3291 | else |
3292 | CEC_ERR("pinctrl sleep_state error\n"); |
3293 | return 0; |
3294 | } |
3295 | |
3296 | static int aml_cec_resume_noirq(struct device *dev) |
3297 | { |
3298 | int ret = 0; |
3299 | unsigned int temp; |
3300 | |
3301 | CEC_INFO("cec resume noirq!\n"); |
3302 | |
3303 | cec_dev->cec_info.power_status = TRANS_STANDBY_TO_ON; |
3304 | |
3305 | scpi_get_wakeup_reason(&cec_dev->wakeup_reason); |
3306 | CEC_ERR("wakeup_reason:0x%x\n", cec_dev->wakeup_reason); |
3307 | |
3308 | scpi_get_cec_val(SCPI_CMD_GET_CEC1, |
3309 | (unsigned int *)&cec_dev->wakup_data); |
3310 | scpi_get_cec_val(SCPI_CMD_GET_CEC2, &temp); |
3311 | CEC_ERR("cev val1: %#x;val2: %#x\n", |
3312 | *((unsigned int *)&cec_dev->wakup_data), |
3313 | temp); |
3314 | |
3315 | cec_dev->cec_info.power_status = TRANS_STANDBY_TO_ON; |
3316 | cec_dev->cec_suspend = CEC_POWER_RESUME; |
3317 | if (!IS_ERR(cec_dev->dbg_dev->pins->default_state)) |
3318 | ret = pinctrl_pm_select_default_state(cec_dev->dbg_dev); |
3319 | else |
3320 | CEC_ERR("pinctrl default_state error\n"); |
3321 | return 0; |
3322 | } |
3323 | |
3324 | static const struct dev_pm_ops aml_cec_pm = { |
3325 | .prepare = aml_cec_pm_prepare, |
3326 | .complete = aml_cec_pm_complete, |
3327 | .suspend_noirq = aml_cec_suspend_noirq, |
3328 | .resume_noirq = aml_cec_resume_noirq, |
3329 | }; |
3330 | #endif |
3331 | |
3332 | static struct platform_driver aml_cec_driver = { |
3333 | .driver = { |
3334 | .name = "cectx", |
3335 | .owner = THIS_MODULE, |
3336 | #ifdef CONFIG_PM |
3337 | .pm = &aml_cec_pm, |
3338 | #endif |
3339 | #ifdef CONFIG_OF |
3340 | .of_match_table = aml_cec_dt_match, |
3341 | #endif |
3342 | }, |
3343 | .probe = aml_cec_probe, |
3344 | .remove = aml_cec_remove, |
3345 | }; |
3346 | |
3347 | static int __init cec_init(void) |
3348 | { |
3349 | int ret; |
3350 | |
3351 | ret = platform_driver_register(&aml_cec_driver); |
3352 | return ret; |
3353 | } |
3354 | |
3355 | static void __exit cec_uninit(void) |
3356 | { |
3357 | platform_driver_unregister(&aml_cec_driver); |
3358 | } |
3359 | |
3360 | module_init(cec_init); |
3361 | module_exit(cec_uninit); |
3362 | MODULE_DESCRIPTION("AMLOGIC HDMI TX CEC driver"); |
3363 | MODULE_LICENSE("GPL"); |
3364 |