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path: root/drivers/amlogic/cec/hdmi_ao_cec.h (plain)
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1/*
2 * drivers/amlogic/cec/hdmi_ao_cec.h
3 *
4 * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17
18#ifndef __AO_CEC_H__
19#define __AO_CEC_H__
20
21
22#define CEC_DRIVER_VERSION "Ver 2019/05/24\n"
23
24#define CEC_FRAME_DELAY msecs_to_jiffies(400)
25#define CEC_DEV_NAME "cec"
26
27#define CEC_EARLY_SUSPEND (1 << 0)
28#define CEC_DEEP_SUSPEND (1 << 1)
29#define CEC_PHY_PORT_NUM 4
30#define HR_DELAY(n) (ktime_set(0, n * 1000 * 1000))
31
32#define L_1 1
33#define L_2 2
34#define L_3 3
35/*
36#define CEC_FUNC_MASK 0
37#define ONE_TOUCH_PLAY_MASK 1
38#define ONE_TOUCH_STANDBY_MASK 2
39#define AUTO_POWER_ON_MASK 3
40*/
41#define CEC_FUNC_CFG_CEC_ON 0x01
42#define CEC_FUNC_CFG_OTP_ON 0x02
43#define CEC_FUNC_CFG_AUTO_STANDBY 0x04
44#define CEC_FUNC_CFG_AUTO_POWER_ON 0x08
45#define CEC_FUNC_CFG_ALL 0x2f
46#define CEC_FUNC_CFG_NONE 0x0
47
48/*#define AO_BASE 0xc8100000*/
49
50#define AO_GPIO_I ((0x0A << 2))
51#define PREG_PAD_GPIO3_I (0x01b << 2)
52
53
54#define AO_CEC_GEN_CNTL ((0x40 << 2))
55#define AO_CEC_RW_REG ((0x41 << 2))
56#define AO_CEC_INTR_MASKN ((0x42 << 2))
57#define AO_CEC_INTR_CLR ((0x43 << 2))
58#define AO_CEC_INTR_STAT ((0x44 << 2))
59
60#define AO_RTI_PWR_CNTL_REG0 ((0x04 << 2))
61#define AO_CRT_CLK_CNTL1 ((0x1a << 2))
62#define AO_RTC_ALT_CLK_CNTL0 ((0x25 << 2))
63#define AO_RTC_ALT_CLK_CNTL1 ((0x26 << 2))
64
65/* for TXLX, same as AO_RTC_ALT_CLK_CNTLx */
66#define AO_CEC_CLK_CNTL_REG0 ((0x1d << 2))
67#define AO_CEC_CLK_CNTL_REG1 ((0x1e << 2))
68
69#define AO_RTI_STATUS_REG1 ((0x01 << 2))
70#define AO_DEBUG_REG0 ((0x28 << 2))
71#define AO_DEBUG_REG1 ((0x29 << 2))
72#define AO_DEBUG_REG2 ((0x2a << 2))
73#define AO_DEBUG_REG3 ((0x2b << 2))
74/* for new add after g12a/b ...*/
75#define AO_CEC_STICKY_DATA0 ((0xca << 2))
76#define AO_CEC_STICKY_DATA1 ((0xcb << 2))
77#define AO_CEC_STICKY_DATA2 ((0xcc << 2))
78#define AO_CEC_STICKY_DATA3 ((0xcd << 2))
79#define AO_CEC_STICKY_DATA4 ((0xce << 2))
80#define AO_CEC_STICKY_DATA5 ((0xcf << 2))
81#define AO_CEC_STICKY_DATA6 ((0xd0 << 2))
82#define AO_CEC_STICKY_DATA7 ((0xd1 << 2))
83
84/*
85 * AOCEC_B
86 */
87#define AO_CECB_CLK_CNTL_REG0 ((0xa0 << 2))
88#define AO_CECB_CLK_CNTL_REG1 ((0xa1 << 2))
89#define AO_CECB_GEN_CNTL ((0xa2 << 2))
90#define AO_CECB_RW_REG ((0xa3 << 2))
91#define AO_CECB_INTR_MASKN ((0xa4 << 2))
92#define AO_CECB_INTR_CLR ((0xa5 << 2))
93#define AO_CECB_INTR_STAT ((0xa6 << 2))
94
95/* read/write */
96#define CEC_TX_MSG_0_HEADER 0x00
97#define CEC_TX_MSG_1_OPCODE 0x01
98#define CEC_TX_MSG_2_OP1 0x02
99#define CEC_TX_MSG_3_OP2 0x03
100#define CEC_TX_MSG_4_OP3 0x04
101#define CEC_TX_MSG_5_OP4 0x05
102#define CEC_TX_MSG_6_OP5 0x06
103#define CEC_TX_MSG_7_OP6 0x07
104#define CEC_TX_MSG_8_OP7 0x08
105#define CEC_TX_MSG_9_OP8 0x09
106#define CEC_TX_MSG_A_OP9 0x0A
107#define CEC_TX_MSG_B_OP10 0x0B
108#define CEC_TX_MSG_C_OP11 0x0C
109#define CEC_TX_MSG_D_OP12 0x0D
110#define CEC_TX_MSG_E_OP13 0x0E
111#define CEC_TX_MSG_F_OP14 0x0F
112
113/* read/write */
114#define CEC_TX_MSG_LENGTH 0x10
115#define CEC_TX_MSG_CMD 0x11
116#define CEC_TX_WRITE_BUF 0x12
117#define CEC_TX_CLEAR_BUF 0x13
118#define CEC_RX_MSG_CMD 0x14
119#define CEC_RX_CLEAR_BUF 0x15
120#define CEC_LOGICAL_ADDR0 0x16
121#define CEC_LOGICAL_ADDR1 0x17
122#define CEC_LOGICAL_ADDR2 0x18
123#define CEC_LOGICAL_ADDR3 0x19
124#define CEC_LOGICAL_ADDR4 0x1A
125#define CEC_CLOCK_DIV_H 0x1B
126#define CEC_CLOCK_DIV_L 0x1C
127
128/* The following registers are for fine tuning CEC bit timing parameters.
129 * They are only valid in AO CEC, NOT valid in HDMITX CEC.
130 * The AO CEC's timing parameters are already set default to work with
131 * 32768Hz clock, so hopefully SW never need to program these registers.
132 * The timing registers are made programmable just in case.
133 */
134#define AO_CEC_QUIESCENT_25MS_BIT7_0 0x20
135#define AO_CEC_QUIESCENT_25MS_BIT11_8 0x21
136#define AO_CEC_STARTBITMINL2H_3MS5_BIT7_0 0x22
137#define AO_CEC_STARTBITMINL2H_3MS5_BIT8 0x23
138#define AO_CEC_STARTBITMAXL2H_3MS9_BIT7_0 0x24
139#define AO_CEC_STARTBITMAXL2H_3MS9_BIT8 0x25
140#define AO_CEC_STARTBITMINH_0MS6_BIT7_0 0x26
141#define AO_CEC_STARTBITMINH_0MS6_BIT8 0x27
142#define AO_CEC_STARTBITMAXH_1MS0_BIT7_0 0x28
143#define AO_CEC_STARTBITMAXH_1MS0_BIT8 0x29
144#define AO_CEC_STARTBITMINTOTAL_4MS3_BIT7_0 0x2A
145#define AO_CEC_STARTBITMINTOTAL_4MS3_BIT9_8 0x2B
146#define AO_CEC_STARTBITMAXTOTAL_4MS7_BIT7_0 0x2C
147#define AO_CEC_STARTBITMAXTOTAL_4MS7_BIT9_8 0x2D
148#define AO_CEC_LOGIC1MINL2H_0MS4_BIT7_0 0x2E
149#define AO_CEC_LOGIC1MINL2H_0MS4_BIT8 0x2F
150#define AO_CEC_LOGIC1MAXL2H_0MS8_BIT7_0 0x30
151#define AO_CEC_LOGIC1MAXL2H_0MS8_BIT8 0x31
152#define AO_CEC_LOGIC0MINL2H_1MS3_BIT7_0 0x32
153#define AO_CEC_LOGIC0MINL2H_1MS3_BIT8 0x33
154#define AO_CEC_LOGIC0MAXL2H_1MS7_BIT7_0 0x34
155#define AO_CEC_LOGIC0MAXL2H_1MS7_BIT8 0x35
156#define AO_CEC_LOGICMINTOTAL_2MS05_BIT7_0 0x36
157#define AO_CEC_LOGICMINTOTAL_2MS05_BIT9_8 0x37
158#define AO_CEC_LOGICMAXHIGH_2MS8_BIT7_0 0x38
159#define AO_CEC_LOGICMAXHIGH_2MS8_BIT8 0x39
160#define AO_CEC_LOGICERRLOW_3MS4_BIT7_0 0x3A
161#define AO_CEC_LOGICERRLOW_3MS4_BIT8 0x3B
162#define AO_CEC_NOMSMPPOINT_1MS05 0x3C
163#define AO_CEC_DELCNTR_LOGICERR 0x3E
164#define AO_CEC_TXTIME_17MS_BIT7_0 0x40
165#define AO_CEC_TXTIME_17MS_BIT10_8 0x41
166#define AO_CEC_TXTIME_2BIT_BIT7_0 0x42
167#define AO_CEC_TXTIME_2BIT_BIT10_8 0x43
168#define AO_CEC_TXTIME_4BIT_BIT7_0 0x44
169#define AO_CEC_TXTIME_4BIT_BIT10_8 0x45
170#define AO_CEC_STARTBITNOML2H_3MS7_BIT7_0 0x46
171#define AO_CEC_STARTBITNOML2H_3MS7_BIT8 0x47
172#define AO_CEC_STARTBITNOMH_0MS8_BIT7_0 0x48
173#define AO_CEC_STARTBITNOMH_0MS8_BIT8 0x49
174#define AO_CEC_LOGIC1NOML2H_0MS6_BIT7_0 0x4A
175#define AO_CEC_LOGIC1NOML2H_0MS6_BIT8 0x4B
176#define AO_CEC_LOGIC0NOML2H_1MS5_BIT7_0 0x4C
177#define AO_CEC_LOGIC0NOML2H_1MS5_BIT8 0x4D
178#define AO_CEC_LOGIC1NOMH_1MS8_BIT7_0 0x4E
179#define AO_CEC_LOGIC1NOMH_1MS8_BIT8 0x4F
180#define AO_CEC_LOGIC0NOMH_0MS9_BIT7_0 0x50
181#define AO_CEC_LOGIC0NOMH_0MS9_BIT8 0x51
182#define AO_CEC_LOGICERRLOW_3MS6_BIT7_0 0x52
183#define AO_CEC_LOGICERRLOW_3MS6_BIT8 0x53
184#define AO_CEC_CHKCONTENTION_0MS1 0x54
185#define AO_CEC_PREPARENXTBIT_0MS05_BIT7_0 0x56
186#define AO_CEC_PREPARENXTBIT_0MS05_BIT8 0x57
187#define AO_CEC_NOMSMPACKPOINT_0MS45 0x58
188#define AO_CEC_ACK0NOML2H_1MS5_BIT7_0 0x5A
189#define AO_CEC_ACK0NOML2H_1MS5_BIT8 0x5B
190
191#define AO_CEC_BUGFIX_DISABLE_0 0x60
192#define AO_CEC_BUGFIX_DISABLE_1 0x61
193
194/* read only */
195#define CEC_RX_MSG_0_HEADER 0x80
196#define CEC_RX_MSG_1_OPCODE 0x81
197#define CEC_RX_MSG_2_OP1 0x82
198#define CEC_RX_MSG_3_OP2 0x83
199#define CEC_RX_MSG_4_OP3 0x84
200#define CEC_RX_MSG_5_OP4 0x85
201#define CEC_RX_MSG_6_OP5 0x86
202#define CEC_RX_MSG_7_OP6 0x87
203#define CEC_RX_MSG_8_OP7 0x88
204#define CEC_RX_MSG_9_OP8 0x89
205#define CEC_RX_MSG_A_OP9 0x8A
206#define CEC_RX_MSG_B_OP10 0x8B
207#define CEC_RX_MSG_C_OP11 0x8C
208#define CEC_RX_MSG_D_OP12 0x8D
209#define CEC_RX_MSG_E_OP13 0x8E
210#define CEC_RX_MSG_F_OP14 0x8F
211
212/* read only */
213#define CEC_RX_MSG_LENGTH 0x90
214#define CEC_RX_MSG_STATUS 0x91
215#define CEC_RX_NUM_MSG 0x92
216#define CEC_TX_MSG_STATUS 0x93
217#define CEC_TX_NUM_MSG 0x94
218
219/* tx_msg_cmd definition */
220#define TX_NO_OP 0 /* No transaction */
221#define TX_REQ_CURRENT 1 /* Transmit earliest message in buffer */
222#define TX_ABORT 2 /* Abort transmitting earliest message */
223/* Overwrite earliest message in buffer and transmit next message */
224#define TX_REQ_NEXT 3
225
226/* tx_msg_status definition */
227#define TX_IDLE 0 /* No transaction */
228#define TX_BUSY 1 /* Transmitter is busy */
229/* Message has been successfully transmitted */
230#define TX_DONE 2
231#define TX_ERROR 3 /* Message has been transmitted with error */
232
233/* rx_msg_cmd */
234#define RX_NO_OP 0 /* No transaction */
235#define RX_ACK_CURRENT 1 /* Read earliest message in buffer */
236#define RX_DISABLE 2 /* Disable receiving latest message */
237/* Clear earliest message from buffer and read next message */
238#define RX_ACK_NEXT 3
239
240/* rx_msg_status */
241#define RX_IDLE 0 /* No transaction */
242#define RX_BUSY 1 /* Receiver is busy */
243#define RX_DONE 2 /* Message has been received successfully */
244#define RX_ERROR 3 /* Message has been received with error */
245
246#define TOP_HPD_PWR5V 0x002
247#define TOP_ARCTX_CNTL 0x010
248#define TOP_CLK_CNTL 0x001
249#define TOP_EDID_GEN_CNTL 0x004
250#define TOP_EDID_ADDR_CEC 0x005
251
252/** Register address: audio clock interrupt clear enable */
253#define DWC_AUD_CEC_IEN_CLR (0xF90UL)
254/** Register address: audio clock interrupt set enable */
255#define DWC_AUD_CEC_IEN_SET (0xF94UL)
256/** Register address: audio clock interrupt status */
257#define DWC_AUD_CEC_ISTS (0xF98UL)
258/** Register address: audio clock interrupt enable */
259#define DWC_AUD_CEC_IEN (0xF9CUL)
260/** Register address: audio clock interrupt clear status */
261#define DWC_AUD_CEC_ICLR (0xFA0UL)
262/** Register address: audio clock interrupt set status */
263#define DWC_AUD_CEC_ISET (0xFA4UL)
264/** Register address: DMI disable interface */
265#define DWC_DMI_DISABLE_IF (0xFF4UL)
266
267/*---- registers for EE CEC ----*/
268#define DWC_CEC_CTRL 0x1F00
269#define DWC_CEC_STAT 0x1F04
270#define DWC_CEC_MASK 0x1F08
271#define DWC_CEC_POLARITY 0x1F0C
272#define DWC_CEC_INT 0x1F10
273#define DWC_CEC_ADDR_L 0x1F14
274#define DWC_CEC_ADDR_H 0x1F18
275#define DWC_CEC_TX_CNT 0x1F1C
276#define DWC_CEC_RX_CNT 0x1F20
277#define DWC_CEC_TX_DATA0 0x1F40
278#define DWC_CEC_TX_DATA1 0x1F44
279#define DWC_CEC_TX_DATA2 0x1F48
280#define DWC_CEC_TX_DATA3 0x1F4C
281#define DWC_CEC_TX_DATA4 0x1F50
282#define DWC_CEC_TX_DATA5 0x1F54
283#define DWC_CEC_TX_DATA6 0x1F58
284#define DWC_CEC_TX_DATA7 0x1F5C
285#define DWC_CEC_TX_DATA8 0x1F60
286#define DWC_CEC_TX_DATA9 0x1F64
287#define DWC_CEC_TX_DATA10 0x1F68
288#define DWC_CEC_TX_DATA11 0x1F6C
289#define DWC_CEC_TX_DATA12 0x1F70
290#define DWC_CEC_TX_DATA13 0x1F74
291#define DWC_CEC_TX_DATA14 0x1F78
292#define DWC_CEC_TX_DATA15 0x1F7C
293#define DWC_CEC_RX_DATA0 0x1F80
294#define DWC_CEC_RX_DATA1 0x1F84
295#define DWC_CEC_RX_DATA2 0x1F88
296#define DWC_CEC_RX_DATA3 0x1F8C
297#define DWC_CEC_RX_DATA4 0x1F90
298#define DWC_CEC_RX_DATA5 0x1F94
299#define DWC_CEC_RX_DATA6 0x1F98
300#define DWC_CEC_RX_DATA7 0x1F9C
301#define DWC_CEC_RX_DATA8 0x1FA0
302#define DWC_CEC_RX_DATA9 0x1FA4
303#define DWC_CEC_RX_DATA10 0x1FA8
304#define DWC_CEC_RX_DATA11 0x1FAC
305#define DWC_CEC_RX_DATA12 0x1FB0
306#define DWC_CEC_RX_DATA13 0x1FB4
307#define DWC_CEC_RX_DATA14 0x1FB8
308#define DWC_CEC_RX_DATA15 0x1FBC
309#define DWC_CEC_LOCK 0x1FC0
310#define DWC_CEC_WKUPCTRL 0x1FC4
311
312/* FOR AO_CECB */
313#define AO_CECB_CTRL_ADDR 0x00
314#define AO_CECB_INTR_MASK_ADDR 0x02
315#define AO_CECB_LADD_LOW_ADDR 0x05
316#define AO_CECB_LADD_HIGH_ADDR 0x06
317#define AO_CECB_TX_CNT_ADDR 0x07
318#define AO_CECB_RX_CNT_ADDR 0x08
319#define AO_CECB_TX_DATA00_ADDR 0x10
320#define AO_CECB_TX_DATA01_ADDR 0x11
321#define AO_CECB_TX_DATA02_ADDR 0x12
322#define AO_CECB_TX_DATA03_ADDR 0x13
323#define AO_CECB_TX_DATA04_ADDR 0x14
324#define AO_CECB_TX_DATA05_ADDR 0x15
325#define AO_CECB_TX_DATA06_ADDR 0x16
326#define AO_CECB_TX_DATA07_ADDR 0x17
327#define AO_CECB_TX_DATA08_ADDR 0x18
328#define AO_CECB_TX_DATA09_ADDR 0x19
329#define AO_CECB_TX_DATA10_ADDR 0x1A
330#define AO_CECB_TX_DATA11_ADDR 0x1B
331#define AO_CECB_TX_DATA12_ADDR 0x1C
332#define AO_CECB_TX_DATA13_ADDR 0x1D
333#define AO_CECB_TX_DATA14_ADDR 0x1E
334#define AO_CECB_TX_DATA15_ADDR 0x1F
335#define AO_CECB_RX_DATA00_ADDR 0x20
336#define AO_CECB_RX_DATA01_ADDR 0x21
337#define AO_CECB_RX_DATA02_ADDR 0x22
338#define AO_CECB_RX_DATA03_ADDR 0x23
339#define AO_CECB_RX_DATA04_ADDR 0x24
340#define AO_CECB_RX_DATA05_ADDR 0x25
341#define AO_CECB_RX_DATA06_ADDR 0x26
342#define AO_CECB_RX_DATA07_ADDR 0x27
343#define AO_CECB_RX_DATA08_ADDR 0x28
344#define AO_CECB_RX_DATA09_ADDR 0x29
345#define AO_CECB_RX_DATA10_ADDR 0x2A
346#define AO_CECB_RX_DATA11_ADDR 0x2B
347#define AO_CECB_RX_DATA12_ADDR 0x2C
348#define AO_CECB_RX_DATA13_ADDR 0x2D
349#define AO_CECB_RX_DATA14_ADDR 0x2E
350#define AO_CECB_RX_DATA15_ADDR 0x2F
351#define AO_CECB_LOCK_BUF_ADDR 0x30
352#define AO_CECB_WAKEUPCTRL_ADDR 0x31
353
354/* cec ip irq flags bit discription */
355#define EECEC_IRQ_TX_DONE (1 << 16)
356#define EECEC_IRQ_RX_EOM (1 << 17)
357#define EECEC_IRQ_TX_NACK (1 << 18)
358#define EECEC_IRQ_TX_ARB_LOST (1 << 19)
359#define EECEC_IRQ_TX_ERR_INITIATOR (1 << 20)
360#define EECEC_IRQ_RX_ERR_FOLLOWER (1 << 21)
361#define EECEC_IRQ_RX_WAKEUP (1 << 22)
362#define EE_CEC_IRQ_EN_MASK (0x3f << 16)
363
364/* cec irq bit flags for AO_CEC_B */
365#define CECB_IRQ_TX_DONE (1 << 0)
366#define CECB_IRQ_RX_EOM (1 << 1)
367#define CECB_IRQ_TX_NACK (1 << 2)
368#define CECB_IRQ_TX_ARB_LOST (1 << 3)
369#define CECB_IRQ_TX_ERR_INITIATOR (1 << 4)
370#define CECB_IRQ_RX_ERR_FOLLOWER (1 << 5)
371#define CECB_IRQ_RX_WAKEUP (1 << 6)
372#define CECB_IRQ_EN_MASK (0x3f << 0)
373
374/* common mask */
375#define CEC_IRQ_TX_DONE (1 << (16 - shift))
376#define CEC_IRQ_RX_EOM (1 << (17 - shift))
377#define CEC_IRQ_TX_NACK (1 << (18 - shift))
378#define CEC_IRQ_TX_ARB_LOST (1 << (19 - shift))
379#define CEC_IRQ_TX_ERR_INITIATOR (1 << (20 - shift))
380#define CEC_IRQ_RX_ERR_FOLLOWER (1 << (21 - shift))
381#define CEC_IRQ_RX_WAKEUP (1 << (22 - shift))
382
383/* wakeup mask */
384#define WAKEUP_OP_86_EN (1 << 7)
385#define WAKEUP_OP_82_EN (1 << 6)
386#define WAKEUP_OP_70_EN (1 << 5)
387#define WAKEUP_OP_44_EN (1 << 4)
388#define WAKEUP_OP_42_EN (1 << 3)
389#define WAKEUP_OP_41_EN (1 << 2)
390#define WAKEUP_OP_0D_EN (1 << 1)
391#define WAKEUP_OP_04_EN (1 << 0)
392#define WAKEUP_DIS_MASK 0
393#define WAKEUP_EN_MASK (WAKEUP_OP_86_EN | \
394 WAKEUP_OP_0D_EN | \
395 WAKEUP_OP_04_EN)
396
397#define EDID_CEC_ID_ADDR 0x00a100a0
398#define EDID_AUTO_CEC_EN 0
399
400#define HHI_32K_CLK_CNTL (0x89 << 2)
401
402struct dbgflg {
403 unsigned int hal_cmd_bypass:1;
404
405};
406
407#ifdef CONFIG_AMLOGIC_MEDIA_TVIN_HDMI
408extern unsigned long hdmirx_rd_top(unsigned long addr);
409extern void hdmirx_wr_top(unsigned long addr, unsigned long data);
410extern uint32_t hdmirx_rd_dwc(uint16_t addr);
411extern void hdmirx_wr_dwc(uint16_t addr, uint32_t data);
412#else
413static inline unsigned long hdmirx_rd_top(unsigned long addr)
414{
415 return 0;
416}
417
418static inline void hdmirx_wr_top(unsigned long addr, unsigned long data)
419{
420}
421
422static inline uint32_t hdmirx_rd_dwc(uint16_t addr)
423{
424 return 0;
425}
426static inline void hdmirx_wr_dwc(uint16_t addr, uint32_t data)
427{
428}
429#endif
430
431extern int hdmirx_get_connect_info(void);
432int __attribute__((weak))hdmirx_get_connect_info(void)
433{
434 return 0;
435}
436
437#ifdef CONFIG_AMLOGIC_AO_CEC
438unsigned int aocec_rd_reg(unsigned long addr);
439void aocec_wr_reg(unsigned long addr, unsigned long data);
440void cecb_irq_handle(void);
441void cec_logicaddr_set(int l_add);
442void cec_arbit_bit_time_set(unsigned int bit_set,
443 unsigned int time_set, unsigned int flag);
444void cec_irq_enable(bool enable);
445void aocec_irq_enable(bool enable);
446extern void dump_reg(void);
447#endif
448extern void cec_dump_info(void);
449extern void cec_hw_reset(void);
450extern void cec_restore_logical_addr(unsigned int addr_en);
451extern void cec_logicaddr_add(unsigned int cec_sel, unsigned int l_add);
452extern void cec_clear_all_logical_addr(unsigned int cec_sel);
453#endif /* __AO_CEC_H__ */
454
generated by cgit at 2024-05-17 03:19:54 (GMT)