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authorshihong.zheng <shihong.zheng@amlogic.com>2020-03-12 07:48:25 (GMT)
committer shihong.zheng <shihong.zheng@amlogic.com>2020-03-20 11:35:52 (GMT)
commit9725693635142a93013f884674a5b62e0916e356 (patch)
treea9642e4f06c22df200f6c025d77daecd93354f22
parent0ae85c6c97ba25fa6a320bd6473cb6341e538f18 (diff)
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decoder: add tm2 revb bringup code. [2/3]
PD#SWPL-18751 Problem: tm2 revb decoder bringup. Solution: 1. add new dmc reg define for tm2 revb. 2. add AV1 decoder driver code. Verify: tm2 revb ptm Change-Id: I08f760049de2b926f14721ea53f8578d7b28b178 Signed-off-by: shihong.zheng <shihong.zheng@amlogic.com>
Diffstat
-rw-r--r--[-rwxr-xr-x]Media.mk1
-rw-r--r--drivers/common/chips/chips.c1
-rw-r--r--drivers/common/chips/decoder_cpu_ver_info.c8
-rw-r--r--drivers/common/chips/decoder_cpu_ver_info.h1
-rw-r--r--drivers/common/firmware/firmware_type.c1
-rw-r--r--drivers/common/firmware/firmware_type.h1
-rw-r--r--drivers/common/media_clock/clk/clk.c3
-rw-r--r--drivers/common/media_clock/clk/clkg12.c5
-rw-r--r--drivers/frame_provider/decoder/Makefile1
-rw-r--r--drivers/frame_provider/decoder/utils/amvdec.c5
-rw-r--r--drivers/frame_provider/decoder/utils/vdec.c58
-rw-r--r--drivers/frame_provider/decoder/vav1/Makefile2
-rw-r--r--drivers/frame_provider/decoder/vav1/aom_av1_define.h171
-rw-r--r--drivers/frame_provider/decoder/vav1/av1_bufmgr.c3394
-rw-r--r--drivers/frame_provider/decoder/vav1/av1_global.h2307
-rw-r--r--drivers/frame_provider/decoder/vav1/vav1.c8977
-rw-r--r--drivers/frame_provider/decoder/vav1/vav1.h22
-rw-r--r--drivers/stream_input/amports/amstream.c7
-rw-r--r--firmware/video_ucode.bin41781
19 files changed, 36069 insertions, 20677 deletions
diff --git a/Media.mk b/Media.mk
index 7fa3c48..25e8622 100755..100644
--- a/Media.mk
+++ b/Media.mk
@@ -20,6 +20,7 @@ CONFIGS := CONFIG_AMLOGIC_MEDIA_VDEC_MPEG12=m \
CONFIG_AMLOGIC_MEDIA_VDEC_AVS=m \
CONFIG_AMLOGIC_MEDIA_VDEC_AVS_MULTI=m \
CONFIG_AMLOGIC_MEDIA_VDEC_AVS2=m \
+ CONFIG_AMLOGIC_MEDIA_VDEC_AV1=m \
CONFIG_AMLOGIC_MEDIA_VENC_H264=m \
CONFIG_AMLOGIC_MEDIA_VENC_H265=m
diff --git a/drivers/common/chips/chips.c b/drivers/common/chips/chips.c
index 63d55ba..a55d640 100644
--- a/drivers/common/chips/chips.c
+++ b/drivers/common/chips/chips.c
@@ -145,6 +145,7 @@ static const struct type_name vformat_type_name[] = {
{VFORMAT_JPEG_ENC, "jpeg_enc"},
{VFORMAT_VP9, "vp9"},
{VFORMAT_AVS2, "avs2"},
+ {VFORMAT_AV1, "av1"},
{VFORMAT_YUV, "yuv"},
{0, NULL},
};
diff --git a/drivers/common/chips/decoder_cpu_ver_info.c b/drivers/common/chips/decoder_cpu_ver_info.c
index 7818a21..894bd74 100644
--- a/drivers/common/chips/decoder_cpu_ver_info.c
+++ b/drivers/common/chips/decoder_cpu_ver_info.c
@@ -159,3 +159,11 @@ enum AM_MESON_CPU_MAJOR_ID get_cpu_major_id(void)
return cpu_ver_id;
}
EXPORT_SYMBOL(get_cpu_major_id);
+
+bool is_cpu_tm2_revb(void)
+{
+ return ((get_cpu_major_id() == AM_MESON_CPU_MAJOR_ID_TM2) &&
+ (is_meson_rev_b()));
+}
+EXPORT_SYMBOL(is_cpu_tm2_revb);
+
diff --git a/drivers/common/chips/decoder_cpu_ver_info.h b/drivers/common/chips/decoder_cpu_ver_info.h
index 494f5f6..83e8274 100644
--- a/drivers/common/chips/decoder_cpu_ver_info.h
+++ b/drivers/common/chips/decoder_cpu_ver_info.h
@@ -52,4 +52,5 @@ enum AM_MESON_CPU_MAJOR_ID
};
enum AM_MESON_CPU_MAJOR_ID get_cpu_major_id(void);
+bool is_cpu_tm2_revb(void);
#endif
diff --git a/drivers/common/firmware/firmware_type.c b/drivers/common/firmware/firmware_type.c
index e781a51..ac35859 100644
--- a/drivers/common/firmware/firmware_type.c
+++ b/drivers/common/firmware/firmware_type.c
@@ -55,6 +55,7 @@ static const struct format_name_s format_name[] = {
{VIDEO_DEC_VP9_G12A, "vp9_g12a"},
{VIDEO_DEC_AVS2, "avs2"},
{VIDEO_DEC_AVS2_MMU, "avs2_mmu"},
+ {VIDEO_DEC_AV1_MMU, "av1_mmu"},
{VIDEO_ENC_H264, "h264_enc"},
{VIDEO_ENC_JPEG, "jpeg_enc"},
{FIRMWARE_MAX, "unknown"},
diff --git a/drivers/common/firmware/firmware_type.h b/drivers/common/firmware/firmware_type.h
index c2ef01a..e997057 100644
--- a/drivers/common/firmware/firmware_type.h
+++ b/drivers/common/firmware/firmware_type.h
@@ -65,6 +65,7 @@
#define VIDEO_DEC_H263_MULTI TAG('2', '6', '3', 'M')
#define VIDEO_DEC_HEVC_MMU_SWAP TAG('2', '6', '5', 'S')
#define VIDEO_DEC_AVS_MULTI TAG('A', 'V', 'S', 'M')
+#define VIDEO_DEC_AV1_MMU TAG('A', 'V', '1', 'M')
/* ... */
#define FIRMWARE_MAX (UINT_MAX)
diff --git a/drivers/common/media_clock/clk/clk.c b/drivers/common/media_clock/clk/clk.c
index b60a08d..144006c 100644
--- a/drivers/common/media_clock/clk/clk.c
+++ b/drivers/common/media_clock/clk/clk.c
@@ -334,7 +334,8 @@ int vdec_source_changed_for_clk_set(int format, int width, int height, int fps)
*/
if (format == VFORMAT_HEVC || format == VFORMAT_VP9
- || format == VFORMAT_AVS2) {
+ || format == VFORMAT_AVS2
+ || format == VFORMAT_AV1) {
ret_clk = hevc_clock_set(clk);
clock_source_wxhxfps_saved[VDEC_HEVC] = width * height * fps;
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
diff --git a/drivers/common/media_clock/clk/clkg12.c b/drivers/common/media_clock/clk/clkg12.c
index f045bd3..9694959 100644
--- a/drivers/common/media_clock/clk/clkg12.c
+++ b/drivers/common/media_clock/clk/clkg12.c
@@ -403,6 +403,11 @@ static struct clk_set_setting clks_for_formats[] = {
{1920*1080*60, 166}, {4096*2048*30, 333},
{4096*2048*60, 630}, {INT_MAX, 630},}
},
+ {/*VFORMAT_AV1*/
+ {{1280*720*30, 100}, {1920*1080*30, 100},
+ {1920*1080*60, 166}, {4096*2048*30, 333},
+ {4096*2048*60, 630}, {INT_MAX, 630},}
+ },
};
diff --git a/drivers/frame_provider/decoder/Makefile b/drivers/frame_provider/decoder/Makefile
index 6511f25..349d381 100644
--- a/drivers/frame_provider/decoder/Makefile
+++ b/drivers/frame_provider/decoder/Makefile
@@ -11,3 +11,4 @@ obj-y += real/
obj-y += avs/
obj-y += avs2/
obj-y += avs_multi/
+obj-y += vav1/
diff --git a/drivers/frame_provider/decoder/utils/amvdec.c b/drivers/frame_provider/decoder/utils/amvdec.c
index bf8955e..c37b473 100644
--- a/drivers/frame_provider/decoder/utils/amvdec.c
+++ b/drivers/frame_provider/decoder/utils/amvdec.c
@@ -425,6 +425,11 @@ s32 optee_load_fw(enum vformat_e type, const char *fw_name)
vdec = OPTEE_VDEC_HEVC;
break;
+ case VFORMAT_AV1:
+ format = VIDEO_DEC_AV1_MMU;
+ vdec = OPTEE_VDEC_HEVC;
+ break;
+
case VFORMAT_HEVC:
if (!strcmp(name, "h265_mmu"))
format = VIDEO_DEC_HEVC_MMU;
diff --git a/drivers/frame_provider/decoder/utils/vdec.c b/drivers/frame_provider/decoder/utils/vdec.c
index f98ea39..ffc7c6a 100644
--- a/drivers/frame_provider/decoder/utils/vdec.c
+++ b/drivers/frame_provider/decoder/utils/vdec.c
@@ -644,9 +644,15 @@ static void vdec_disable_DMC(struct vdec_s *vdec)
codec_dmcbus_read(DMC_REQ_CTRL) & ~mask);
spin_unlock_irqrestore(&vdec_spin_lock, flags);
- while (!(codec_dmcbus_read(DMC_CHAN_STS)
+ if (is_cpu_tm2_revb()) {
+ while (!(codec_dmcbus_read(TM2_REVB_DMC_CHAN_STS)
& mask))
;
+ } else {
+ while (!(codec_dmcbus_read(DMC_CHAN_STS)
+ & mask))
+ ;
+ }
pr_debug("%s input->target= 0x%x\n", __func__, input->target);
}
@@ -687,6 +693,7 @@ static int vdec_get_hw_type(int value)
case VFORMAT_HEVC:
case VFORMAT_VP9:
case VFORMAT_AVS2:
+ case VFORMAT_AV1:
type = CORE_MASK_HEVC;
break;
@@ -922,7 +929,8 @@ static const char * const vdec_device_name[] = {
"amvenc_avc", "amvenc_avc",
"jpegenc", "jpegenc",
"amvdec_vp9", "ammvdec_vp9",
- "amvdec_avs2", "ammvdec_avs2"
+ "amvdec_avs2", "ammvdec_avs2",
+ "amvdec_av1", "ammvdec_av1",
};
@@ -1046,7 +1054,8 @@ int vdec_set_decinfo(struct vdec_s *vdec, struct dec_sysinfo *p)
sprintf(fmt, "m%s", ++str);
if (is_support_profile(fmt) &&
- vdec->sys_info->format != VIDEO_DEC_FORMAT_H263)
+ vdec->sys_info->format != VIDEO_DEC_FORMAT_H263 &&
+ vdec->format != VFORMAT_AV1)
vdec->type = VDEC_TYPE_STREAM_PARSER;
}
@@ -1768,9 +1777,15 @@ void hevc_wait_ddr(void)
codec_dmcbus_read(DMC_REQ_CTRL) & ~mask);
spin_unlock_irqrestore(&vdec_spin_lock, flags);
- while (!(codec_dmcbus_read(DMC_CHAN_STS)
- & mask))
- ;
+ if (is_cpu_tm2_revb()) {
+ while (!(codec_dmcbus_read(TM2_REVB_DMC_CHAN_STS)
+ & mask))
+ ;
+ } else {
+ while (!(codec_dmcbus_read(DMC_CHAN_STS)
+ & mask))
+ ;
+ }
}
void vdec_save_input_context(struct vdec_s *vdec)
@@ -2155,7 +2170,9 @@ s32 vdec_init(struct vdec_s *vdec, int is_4k)
vdec_input_set_type(&vdec->input, vdec->type,
(vdec->format == VFORMAT_HEVC ||
vdec->format == VFORMAT_AVS2 ||
- vdec->format == VFORMAT_VP9) ?
+ vdec->format == VFORMAT_VP9 ||
+ vdec->format == VFORMAT_AV1
+ ) ?
VDEC_INPUT_TARGET_HEVC :
VDEC_INPUT_TARGET_VLD);
if (vdec_single(vdec) || (vdec_get_debug_flags() & 0x2))
@@ -2427,7 +2444,8 @@ s32 vdec_init(struct vdec_s *vdec, int is_4k)
}
p->dolby_meta_with_el = 0;
- pr_debug("vdec_init, vf_provider_name = %s\n", p->vf_provider_name);
+ pr_debug("vdec_init, vf_provider_name = %s, b %d\n",
+ p->vf_provider_name, is_cpu_tm2_revb());
vdec_input_prepare_bufs(/*prepared buffer for fast playing.*/
&vdec->input,
vdec->sys_info->width,
@@ -3912,9 +3930,15 @@ void vdec_reset_core(struct vdec_s *vdec)
codec_dmcbus_read(DMC_REQ_CTRL) & ~mask);
spin_unlock_irqrestore(&vdec_spin_lock, flags);
- while (!(codec_dmcbus_read(DMC_CHAN_STS)
- & mask))
- ;
+ if (is_cpu_tm2_revb()) {
+ while (!(codec_dmcbus_read(TM2_REVB_DMC_CHAN_STS)
+ & mask))
+ ;
+ } else {
+ while (!(codec_dmcbus_read(DMC_CHAN_STS)
+ & mask))
+ ;
+ }
/*
* 2: assist
* 3: vld_reset
@@ -3995,9 +4019,15 @@ void hevc_reset_core(struct vdec_s *vdec)
codec_dmcbus_read(DMC_REQ_CTRL) & ~mask);
spin_unlock_irqrestore(&vdec_spin_lock, flags);
- while (!(codec_dmcbus_read(DMC_CHAN_STS)
- & mask))
- ;
+ if (is_cpu_tm2_revb()) {
+ while (!(codec_dmcbus_read(TM2_REVB_DMC_CHAN_STS)
+ & mask))
+ ;
+ } else {
+ while (!(codec_dmcbus_read(DMC_CHAN_STS)
+ & mask))
+ ;
+ }
if (vdec == NULL || input_frame_based(vdec))
WRITE_VREG(HEVC_STREAM_CONTROL, 0);
diff --git a/drivers/frame_provider/decoder/vav1/Makefile b/drivers/frame_provider/decoder/vav1/Makefile
new file mode 100644
index 0000000..64a4973
--- a/dev/null
+++ b/drivers/frame_provider/decoder/vav1/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_AMLOGIC_MEDIA_VDEC_AV1) += amvdec_av1.o
+amvdec_av1-objs += vav1.o av1_bufmgr.o
diff --git a/drivers/frame_provider/decoder/vav1/aom_av1_define.h b/drivers/frame_provider/decoder/vav1/aom_av1_define.h
new file mode 100644
index 0000000..8a67885
--- a/dev/null
+++ b/drivers/frame_provider/decoder/vav1/aom_av1_define.h
@@ -0,0 +1,171 @@
+enum NalUnitType
+{
+ NAL_UNIT_CODED_SLICE_TRAIL_N = 0, // 0
+ NAL_UNIT_CODED_SLICE_TRAIL_R, // 1
+
+ NAL_UNIT_CODED_SLICE_TSA_N, // 2
+ NAL_UNIT_CODED_SLICE_TLA, // 3 // Current name in the spec: TSA_R
+
+ NAL_UNIT_CODED_SLICE_STSA_N, // 4
+ NAL_UNIT_CODED_SLICE_STSA_R, // 5
+
+ NAL_UNIT_CODED_SLICE_RADL_N, // 6
+ NAL_UNIT_CODED_SLICE_DLP, // 7 // Current name in the spec: RADL_R
+
+ NAL_UNIT_CODED_SLICE_RASL_N, // 8
+ NAL_UNIT_CODED_SLICE_TFD, // 9 // Current name in the spec: RASL_R
+
+ NAL_UNIT_RESERVED_10,
+ NAL_UNIT_RESERVED_11,
+ NAL_UNIT_RESERVED_12,
+ NAL_UNIT_RESERVED_13,
+ NAL_UNIT_RESERVED_14,
+ NAL_UNIT_RESERVED_15,
+
+ NAL_UNIT_CODED_SLICE_BLA, // 16 // Current name in the spec: BLA_W_LP
+ NAL_UNIT_CODED_SLICE_BLANT, // 17 // Current name in the spec: BLA_W_DLP
+ NAL_UNIT_CODED_SLICE_BLA_N_LP, // 18
+ NAL_UNIT_CODED_SLICE_IDR, // 19 // Current name in the spec: IDR_W_DLP
+ NAL_UNIT_CODED_SLICE_IDR_N_LP, // 20
+ NAL_UNIT_CODED_SLICE_CRA, // 21
+ NAL_UNIT_RESERVED_22,
+ NAL_UNIT_RESERVED_23,
+
+ NAL_UNIT_RESERVED_24,
+ NAL_UNIT_RESERVED_25,
+ NAL_UNIT_RESERVED_26,
+ NAL_UNIT_RESERVED_27,
+ NAL_UNIT_RESERVED_28,
+ NAL_UNIT_RESERVED_29,
+ NAL_UNIT_RESERVED_30,
+ NAL_UNIT_RESERVED_31,
+
+ NAL_UNIT_VPS, // 32
+ NAL_UNIT_SPS, // 33
+ NAL_UNIT_PPS, // 34
+ NAL_UNIT_ACCESS_UNIT_DELIMITER, // 35
+ NAL_UNIT_EOS, // 36
+ NAL_UNIT_EOB, // 37
+ NAL_UNIT_FILLER_DATA, // 38
+ NAL_UNIT_SEI, // 39 Prefix SEI
+ NAL_UNIT_SEI_SUFFIX, // 40 Suffix SEI
+ NAL_UNIT_RESERVED_41,
+ NAL_UNIT_RESERVED_42,
+ NAL_UNIT_RESERVED_43,
+ NAL_UNIT_RESERVED_44,
+ NAL_UNIT_RESERVED_45,
+ NAL_UNIT_RESERVED_46,
+ NAL_UNIT_RESERVED_47,
+ NAL_UNIT_UNSPECIFIED_48,
+ NAL_UNIT_UNSPECIFIED_49,
+ NAL_UNIT_UNSPECIFIED_50,
+ NAL_UNIT_UNSPECIFIED_51,
+ NAL_UNIT_UNSPECIFIED_52,
+ NAL_UNIT_UNSPECIFIED_53,
+ NAL_UNIT_UNSPECIFIED_54,
+ NAL_UNIT_UNSPECIFIED_55,
+ NAL_UNIT_UNSPECIFIED_56,
+ NAL_UNIT_UNSPECIFIED_57,
+ NAL_UNIT_UNSPECIFIED_58,
+ NAL_UNIT_UNSPECIFIED_59,
+ NAL_UNIT_UNSPECIFIED_60,
+ NAL_UNIT_UNSPECIFIED_61,
+ NAL_UNIT_UNSPECIFIED_62,
+ NAL_UNIT_UNSPECIFIED_63,
+ NAL_UNIT_INVALID,
+};
+
+int forbidden_zero_bit;
+int m_nalUnitType;
+int m_reservedZero6Bits;
+int m_temporalId;
+
+//---------------------------------------------------
+// Amrisc Software Interrupt
+//---------------------------------------------------
+#define AMRISC_STREAM_EMPTY_REQ 0x01
+#define AMRISC_PARSER_REQ 0x02
+#define AMRISC_MAIN_REQ 0x04
+
+//---------------------------------------------------
+// AOM_AV1_DEC_STATUS (HEVC_DEC_STATUS) define
+//---------------------------------------------------
+ /*command*/
+#define AOM_AV1_DEC_IDLE 0
+#define AOM_AV1_DEC_FRAME_HEADER 1
+#define AOM_AV1_DEC_TILE_END 2
+#define AOM_AV1_DEC_TG_END 3
+#define AOM_AV1_DEC_LCU_END 4
+#define AOM_AV1_DECODE_SLICE 5
+#define AOM_AV1_SEARCH_HEAD 6
+#define AOM_AV1_DUMP_LMEM 7
+#define AOM_AV1_FGS_PARAM_CONT 8
+#define AOM_AV1_FGS_PARAM_CONT 8
+#define AOM_AV1_PIC_END_CONT 9
+ /*status*/
+#define AOM_AV1_DEC_PIC_END 0xe0
+ /*AOM_AV1_FGS_PARA:
+ Bit[11] - 0 Read, 1 - Write
+ Bit[10:8] - film_grain_params_ref_idx, For Write request
+ */
+#define AOM_AV1_FGS_PARAM 0xe1
+#define AOM_AV1_DEC_PIC_END_PRE 0xe2
+#define AOM_AV1_HEAD_PARSER_DONE 0xf0
+#define AOM_AV1_HEAD_SEARCH_DONE 0xf1
+#define AOM_AV1_SEQ_HEAD_PARSER_DONE 0xf2
+#define AOM_AV1_FRAME_HEAD_PARSER_DONE 0xf3
+#define AOM_AV1_FRAME_PARSER_DONE 0xf4
+#define AOM_AV1_REDUNDANT_FRAME_HEAD_PARSER_DONE 0xf5
+#define HEVC_ACTION_DONE 0xff
+
+
+//---------------------------------------------------
+// Include "parser_cmd.h"
+//---------------------------------------------------
+#define PARSER_CMD_SKIP_CFG_0 0x0000090b
+
+#define PARSER_CMD_SKIP_CFG_1 0x1b14140f
+
+#define PARSER_CMD_SKIP_CFG_2 0x001b1910
+
+#define PARSER_CMD_NUMBER 37
+
+unsigned short parser_cmd[PARSER_CMD_NUMBER] = {
+0x0401,
+0x8401,
+0x0800,
+0x0402,
+0x9002,
+0x1423,
+0x8CC3,
+0x1423,
+0x8804,
+0x9825,
+0x0800,
+0x04FE,
+0x8406,
+0x8411,
+0x1800,
+0x8408,
+0x8409,
+0x8C2A,
+0x9C2B,
+0x1C00,
+0x840F,
+0x8407,
+0x8000,
+0x8408,
+0x2000,
+0xA800,
+0x8410,
+0x04DE,
+0x840C,
+0x840D,
+0xAC00,
+0xA000,
+0x08C0,
+0x08E0,
+0xA40E,
+0xFC00,
+0x7C00
+};
diff --git a/drivers/frame_provider/decoder/vav1/av1_bufmgr.c b/drivers/frame_provider/decoder/vav1/av1_bufmgr.c
new file mode 100644
index 0000000..619cd2d
--- a/dev/null
+++ b/drivers/frame_provider/decoder/vav1/av1_bufmgr.c
@@ -0,0 +1,3394 @@
+#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#else
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/spinlock.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include <linux/amlogic/media/canvas/canvas.h>
+
+#undef pr_info
+#define pr_info printk
+
+#define __COMPARE(context, p1, p2) comp(p1, p2)
+#define __SHORTSORT(lo, hi, width, comp, context) \
+ shortsort(lo, hi, width, comp)
+#define CUTOFF 8 /* testing shows that this is good value */
+#define STKSIZ (8*sizeof(void *) - 2)
+
+#undef swap
+static void swap(char *a, char *b, size_t width)
+{
+ char tmp;
+
+ if (a != b)
+ /* Do the swap one character at a time to avoid potential
+ * alignment problems.
+ */
+ while (width--) {
+ tmp = *a;
+ *a++ = *b;
+ *b++ = tmp;
+ }
+}
+
+static void shortsort(char *lo, char *hi, size_t width,
+ int (*comp)(const void *, const void *))
+{
+ char *p, *max;
+
+ /* Note: in assertions below, i and j are alway inside original
+ * bound of array to sort.
+ */
+ while (hi > lo) {
+ /* A[i] <= A[j] for i <= j, j > hi */
+ max = lo;
+ for (p = lo + width; p <= hi; p += width) {
+ /* A[i] <= A[max] for lo <= i < p */
+ if (__COMPARE(context, p, max) > 0)
+ max = p;
+ /* A[i] <= A[max] for lo <= i <= p */
+ }
+ /* A[i] <= A[max] for lo <= i <= hi */
+ swap(max, hi, width);
+
+ /* A[i] <= A[hi] for i <= hi, so A[i] <= A[j] for i <= j,
+ * j >= hi
+ */
+ hi -= width;
+
+ /* A[i] <= A[j] for i <= j, j > hi, loop top condition
+ * established
+ */
+ }
+}
+
+static void qsort(void *base, size_t num, size_t width,
+ int (*comp)(const void *, const void *))
+{
+ char *lo, *hi; /* ends of sub-array currently sorting */
+ char *mid; /* points to middle of subarray */
+ char *loguy, *higuy; /* traveling pointers for partition step */
+ size_t size; /* size of the sub-array */
+ char *lostk[STKSIZ], *histk[STKSIZ];
+ int stkptr;
+
+/* stack for saving sub-array to be
+ * processed
+ */
+#if 0
+ /* validation section */
+ _VALIDATE_RETURN_VOID(base != NULL || num == 0, EINVAL);
+ _VALIDATE_RETURN_VOID(width > 0, EINVAL);
+ _VALIDATE_RETURN_VOID(comp != NULL, EINVAL);
+#endif
+ if (num < 2)
+ return; /* nothing to do */
+
+ stkptr = 0; /* initialize stack */
+ lo = (char *)base;
+ hi = (char *)base + width * (num - 1); /* initialize limits */
+
+ /* this entry point is for pseudo-recursion calling: setting
+ * lo and hi and jumping to here is like recursion, but stkptr is
+ * preserved, locals aren't, so we preserve stuff on the stack
+ */
+recurse:
+
+ size = (hi - lo) / width + 1; /* number of el's to sort */
+
+ /* below a certain size, it is faster to use a O(n^2) sorting method */
+ if (size <= CUTOFF) {
+ __SHORTSORT(lo, hi, width, comp, context);
+ } else {
+ /* First we pick a partitioning element. The efficiency of
+ * the algorithm demands that we find one that is approximately
+ * the median of the values, but also that we select one fast.
+ * We choose the median of the first, middle, and last
+ * elements, to avoid bad performance in the face of already
+ * sorted data, or data that is made up of multiple sorted
+ * runs appended together. Testing shows that a
+ * median-of-three algorithm provides better performance than
+ * simply picking the middle element for the latter case.
+ */
+
+ mid = lo + (size / 2) * width; /* find middle element */
+
+ /* Sort the first, middle, last elements into order */
+ if (__COMPARE(context, lo, mid) > 0)
+ swap(lo, mid, width);
+ if (__COMPARE(context, lo, hi) > 0)
+ swap(lo, hi, width);
+ if (__COMPARE(context, mid, hi) > 0)
+ swap(mid, hi, width);
+
+ /* We now wish to partition the array into three pieces, one
+ * consisting of elements <= partition element, one of elements
+ * equal to the partition element, and one of elements > than
+ * it. This is done below; comments indicate conditions
+ * established at every step.
+ */
+
+ loguy = lo;
+ higuy = hi;
+
+ /* Note that higuy decreases and loguy increases on every
+ * iteration, so loop must terminate.
+ */
+ for (;;) {
+ /* lo <= loguy < hi, lo < higuy <= hi,
+ * A[i] <= A[mid] for lo <= i <= loguy,
+ * A[i] > A[mid] for higuy <= i < hi,
+ * A[hi] >= A[mid]
+ */
+
+ /* The doubled loop is to avoid calling comp(mid,mid),
+ * since some existing comparison funcs don't work
+ * when passed the same value for both pointers.
+ */
+
+ if (mid > loguy) {
+ do {
+ loguy += width;
+ } while (loguy < mid &&
+ __COMPARE(context, loguy, mid) <= 0);
+ }
+ if (mid <= loguy) {
+ do {
+ loguy += width;
+ } while (loguy <= hi &&
+ __COMPARE(context, loguy, mid) <= 0);
+ }
+
+ /* lo < loguy <= hi+1, A[i] <= A[mid] for
+ * lo <= i < loguy,
+ * either loguy > hi or A[loguy] > A[mid]
+ */
+
+ do {
+ higuy -= width;
+ } while (higuy > mid &&
+ __COMPARE(context, higuy, mid) > 0);
+
+ /* lo <= higuy < hi, A[i] > A[mid] for higuy < i < hi,
+ * either higuy == lo or A[higuy] <= A[mid]
+ */
+
+ if (higuy < loguy)
+ break;
+
+ /* if loguy > hi or higuy == lo, then we would have
+ * exited, so A[loguy] > A[mid], A[higuy] <= A[mid],
+ * loguy <= hi, higuy > lo
+ */
+
+ swap(loguy, higuy, width);
+
+ /* If the partition element was moved, follow it.
+ * Only need to check for mid == higuy, since before
+ * the swap, A[loguy] > A[mid] implies loguy != mid.
+ */
+
+ if (mid == higuy)
+ mid = loguy;
+
+ /* A[loguy] <= A[mid], A[higuy] > A[mid]; so condition
+ * at top of loop is re-established
+ */
+ }
+
+ /* A[i] <= A[mid] for lo <= i < loguy,
+ * A[i] > A[mid] for higuy < i < hi,
+ * A[hi] >= A[mid]
+ * higuy < loguy
+ * implying:
+ * higuy == loguy-1
+ * or higuy == hi - 1, loguy == hi + 1, A[hi] == A[mid]
+ */
+
+ /* Find adjacent elements equal to the partition element. The
+ * doubled loop is to avoid calling comp(mid,mid), since some
+ * existing comparison funcs don't work when passed the same
+ * value for both pointers.
+ */
+
+ higuy += width;
+ if (mid < higuy) {
+ do {
+ higuy -= width;
+ } while (higuy > mid &&
+ __COMPARE(context, higuy, mid) == 0);
+ }
+ if (mid >= higuy) {
+ do {
+ higuy -= width;
+ } while (higuy > lo &&
+ __COMPARE(context, higuy, mid) == 0);
+ }
+
+ /* OK, now we have the following:
+ * higuy < loguy
+ * lo <= higuy <= hi
+ * A[i] <= A[mid] for lo <= i <= higuy
+ * A[i] == A[mid] for higuy < i < loguy
+ * A[i] > A[mid] for loguy <= i < hi
+ * A[hi] >= A[mid]
+ */
+
+ /* We've finished the partition, now we want to sort the
+ * subarrays [lo, higuy] and [loguy, hi].
+ * We do the smaller one first to minimize stack usage.
+ * We only sort arrays of length 2 or more.
+ */
+
+ if (higuy - lo >= hi - loguy) {
+ if (lo < higuy) {
+ lostk[stkptr] = lo;
+ histk[stkptr] = higuy;
+ ++stkptr;
+ } /* save big recursion for later */
+
+ if (loguy < hi) {
+ lo = loguy;
+ goto recurse; /* do small recursion */
+ }
+ } else {
+ if (loguy < hi) {
+ lostk[stkptr] = loguy;
+ histk[stkptr] = hi;
+ ++stkptr; /* save big recursion for later */
+ }
+
+ if (lo < higuy) {
+ hi = higuy;
+ goto recurse; /* do small recursion */
+ }
+ }
+ }
+
+ /* We have sorted the array, except for any pending sorts on the stack.
+ * Check if there are any, and do them.
+ */
+
+ --stkptr;
+ if (stkptr >= 0) {
+ lo = lostk[stkptr];
+ hi = histk[stkptr];
+ goto recurse; /* pop subarray from stack */
+ } else
+ return; /* all subarrays done */
+}
+
+#endif
+
+#include "av1_global.h"
+int aom_realloc_frame_buffer(AV1_COMMON *cm, PIC_BUFFER_CONFIG *pic,
+ int width, int height, unsigned int order_hint);
+void dump_params(AV1Decoder *pbi, union param_u *params);
+
+#define assert(a)
+#define IMPLIES(a)
+
+int new_compressed_data_count = 0;
+
+static int valid_ref_frame_size(int ref_width, int ref_height,
+ int this_width, int this_height) {
+ return 2 * this_width >= ref_width && 2 * this_height >= ref_height &&
+ this_width <= 16 * ref_width && this_height <= 16 * ref_height;
+}
+
+#ifdef SUPPORT_SCALE_FACTOR
+// Note: Expect val to be in q4 precision
+static inline int scaled_x(int val, const struct scale_factors *sf) {
+ const int off =
+ (sf->x_scale_fp - (1 << REF_SCALE_SHIFT)) * (1 << (SUBPEL_BITS - 1));
+ const int64_t tval = (int64_t)val * sf->x_scale_fp + off;
+ return (int)ROUND_POWER_OF_TWO_SIGNED_64(tval,
+ REF_SCALE_SHIFT - SCALE_EXTRA_BITS);
+}
+
+// Note: Expect val to be in q4 precision
+static inline int scaled_y(int val, const struct scale_factors *sf) {
+ const int off =
+ (sf->y_scale_fp - (1 << REF_SCALE_SHIFT)) * (1 << (SUBPEL_BITS - 1));
+ const int64_t tval = (int64_t)val * sf->y_scale_fp + off;
+ return (int)ROUND_POWER_OF_TWO_SIGNED_64(tval,
+ REF_SCALE_SHIFT - SCALE_EXTRA_BITS);
+}
+
+// Note: Expect val to be in q4 precision
+static int unscaled_value(int val, const struct scale_factors *sf) {
+ (void)sf;
+ return val << SCALE_EXTRA_BITS;
+}
+
+static int get_fixed_point_scale_factor(int other_size, int this_size) {
+ // Calculate scaling factor once for each reference frame
+ // and use fixed point scaling factors in decoding and encoding routines.
+ // Hardware implementations can calculate scale factor in device driver
+ // and use multiplication and shifting on hardware instead of division.
+ return ((other_size << REF_SCALE_SHIFT) + this_size / 2) / this_size;
+}
+
+// Given the fixed point scale, calculate coarse point scale.
+static int fixed_point_scale_to_coarse_point_scale(int scale_fp) {
+ return ROUND_POWER_OF_TWO(scale_fp, REF_SCALE_SHIFT - SCALE_SUBPEL_BITS);
+}
+
+
+void av1_setup_scale_factors_for_frame(struct scale_factors *sf, int other_w,
+ int other_h, int this_w, int this_h) {
+ if (!valid_ref_frame_size(other_w, other_h, this_w, this_h)) {
+ sf->x_scale_fp = REF_INVALID_SCALE;
+ sf->y_scale_fp = REF_INVALID_SCALE;
+ return;
+ }
+
+ sf->x_scale_fp = get_fixed_point_scale_factor(other_w, this_w);
+ sf->y_scale_fp = get_fixed_point_scale_factor(other_h, this_h);
+
+ sf->x_step_q4 = fixed_point_scale_to_coarse_point_scale(sf->x_scale_fp);
+ sf->y_step_q4 = fixed_point_scale_to_coarse_point_scale(sf->y_scale_fp);
+
+ if (av1_is_scaled(sf)) {
+ sf->scale_value_x = scaled_x;
+ sf->scale_value_y = scaled_y;
+ } else {
+ sf->scale_value_x = unscaled_value;
+ sf->scale_value_y = unscaled_value;
+ }
+#ifdef ORI_CODE
+ // AV1 convolve functions
+ // Special case convolve functions should produce the same result as
+ // av1_convolve_2d.
+ // subpel_x_qn == 0 && subpel_y_qn == 0
+ sf->convolve[0][0][0] = av1_convolve_2d_copy_sr;
+ // subpel_x_qn == 0
+ sf->convolve[0][1][0] = av1_convolve_y_sr;
+ // subpel_y_qn == 0
+ sf->convolve[1][0][0] = av1_convolve_x_sr;
+ // subpel_x_qn != 0 && subpel_y_qn != 0
+ sf->convolve[1][1][0] = av1_convolve_2d_sr;
+ // subpel_x_qn == 0 && subpel_y_qn == 0
+ sf->convolve[0][0][1] = av1_dist_wtd_convolve_2d_copy;
+ // subpel_x_qn == 0
+ sf->convolve[0][1][1] = av1_dist_wtd_convolve_y;
+ // subpel_y_qn == 0
+ sf->convolve[1][0][1] = av1_dist_wtd_convolve_x;
+ // subpel_x_qn != 0 && subpel_y_qn != 0
+ sf->convolve[1][1][1] = av1_dist_wtd_convolve_2d;
+ // AV1 High BD convolve functions
+ // Special case convolve functions should produce the same result as
+ // av1_highbd_convolve_2d.
+ // subpel_x_qn == 0 && subpel_y_qn == 0
+ sf->highbd_convolve[0][0][0] = av1_highbd_convolve_2d_copy_sr;
+ // subpel_x_qn == 0
+ sf->highbd_convolve[0][1][0] = av1_highbd_convolve_y_sr;
+ // subpel_y_qn == 0
+ sf->highbd_convolve[1][0][0] = av1_highbd_convolve_x_sr;
+ // subpel_x_qn != 0 && subpel_y_qn != 0
+ sf->highbd_convolve[1][1][0] = av1_highbd_convolve_2d_sr;
+ // subpel_x_qn == 0 && subpel_y_qn == 0
+ sf->highbd_convolve[0][0][1] = av1_highbd_dist_wtd_convolve_2d_copy;
+ // subpel_x_qn == 0
+ sf->highbd_convolve[0][1][1] = av1_highbd_dist_wtd_convolve_y;
+ // subpel_y_qn == 0
+ sf->highbd_convolve[1][0][1] = av1_highbd_dist_wtd_convolve_x;
+ // subpel_x_qn != 0 && subpel_y_qn != 0
+ sf->highbd_convolve[1][1][1] = av1_highbd_dist_wtd_convolve_2d;
+#endif
+}
+#endif
+
+
+static int get_free_fb(AV1_COMMON *cm) {
+ RefCntBuffer *const frame_bufs = cm->buffer_pool->frame_bufs;
+ int i;
+ unsigned long flags;
+ lock_buffer_pool(cm->buffer_pool, flags);
+ for (i = 0; i < FRAME_BUFFERS; ++i)
+ if (frame_bufs[i].ref_count == 0
+#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
+ && frame_bufs[i].buf.vf_ref == 0
+#endif
+ )
+ break;
+
+ if (i != FRAME_BUFFERS) {
+ if (frame_bufs[i].buf.use_external_reference_buffers) {
+ // If this frame buffer's y_buffer, u_buffer, and v_buffer point to the
+ // external reference buffers. Restore the buffer pointers to point to the
+ // internally allocated memory.
+ PIC_BUFFER_CONFIG *ybf = &frame_bufs[i].buf;
+ ybf->y_buffer = ybf->store_buf_adr[0];
+ ybf->u_buffer = ybf->store_buf_adr[1];
+ ybf->v_buffer = ybf->store_buf_adr[2];
+ ybf->use_external_reference_buffers = 0;
+ }
+
+ frame_bufs[i].ref_count = 1;
+ } else {
+ // We should never run out of free buffers. If this assertion fails, there
+ // is a reference leak.
+ assert(0 && "Ran out of free frame buffers. Likely a reference leak.");
+ // Reset i to be INVALID_IDX to indicate no free buffer found.
+ i = INVALID_IDX;
+ }
+
+ unlock_buffer_pool(cm->buffer_pool, flags);
+ return i;
+}
+
+static RefCntBuffer *assign_cur_frame_new_fb(AV1_COMMON *const cm) {
+ // Release the previously-used frame-buffer
+ int new_fb_idx;
+ if (cm->cur_frame != NULL) {
+ --cm->cur_frame->ref_count;
+ cm->cur_frame = NULL;
+ }
+
+ // Assign a new framebuffer
+ new_fb_idx = get_free_fb(cm);
+ if (new_fb_idx == INVALID_IDX) return NULL;
+
+ cm->cur_frame = &cm->buffer_pool->frame_bufs[new_fb_idx];
+ cm->cur_frame->buf.buf_8bit_valid = 0;
+#ifdef AML
+ cm->cur_frame->buf.index = new_fb_idx;
+#endif
+#ifdef ORI_CODE
+ av1_zero(cm->cur_frame->interp_filter_selected);
+#endif
+ return cm->cur_frame;
+}
+
+// Modify 'lhs_ptr' to reference the buffer at 'rhs_ptr', and update the ref
+// counts accordingly.
+static void assign_frame_buffer_p(RefCntBuffer **lhs_ptr,
+ RefCntBuffer *rhs_ptr) {
+ RefCntBuffer *const old_ptr = *lhs_ptr;
+ if (old_ptr != NULL) {
+ assert(old_ptr->ref_count > 0);
+ // One less reference to the buffer at 'old_ptr', so decrease ref count.
+ --old_ptr->ref_count;
+ }
+
+ *lhs_ptr = rhs_ptr;
+ // One more reference to the buffer at 'rhs_ptr', so increase ref count.
+ ++rhs_ptr->ref_count;
+}
+
+AV1Decoder *av1_decoder_create(BufferPool *const pool) {
+ int i;
+ AV1_COMMON *cm;
+
+#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
+ AV1Decoder *pbi = (AV1Decoder *)malloc(sizeof(*pbi));
+#else
+ AV1Decoder *pbi = (AV1Decoder *)vmalloc(sizeof(AV1Decoder));
+#endif
+ if (!pbi) return NULL;
+ memset(pbi, 0, sizeof(*pbi));
+
+ cm = &pbi->common;
+
+ // The jmp_buf is valid only for the duration of the function that calls
+ // setjmp(). Therefore, this function must reset the 'setjmp' field to 0
+ // before it returns.
+
+ cm->error.setjmp = 1;
+
+#ifdef ORI_CODE
+ memset(cm->fc, 0, sizeof(*cm->fc));
+ memset(cm->default_frame_context, 0, sizeof(*cm->default_frame_context));
+#endif
+ pbi->need_resync = 1;
+
+ // Initialize the references to not point to any frame buffers.
+ for (i = 0; i < REF_FRAMES; i++) {
+ cm->ref_frame_map[i] = NULL;
+ cm->next_ref_frame_map[i] = NULL;
+#ifdef AML
+ cm->next_used_ref_frame_map[i] = NULL;
+#endif
+ }
+
+ cm->current_frame.frame_number = 0;
+ pbi->decoding_first_frame = 1;
+ pbi->common.buffer_pool = pool;
+
+ cm->seq_params.bit_depth = AOM_BITS_8;
+
+#ifdef ORI_CODE
+ cm->alloc_mi = dec_alloc_mi;
+ cm->free_mi = dec_free_mi;
+ cm->setup_mi = dec_setup_mi;
+
+ av1_loop_filter_init(cm);
+
+ av1_qm_init(cm);
+ av1_loop_restoration_precal();
+#if CONFIG_ACCOUNTING
+ pbi->acct_enabled = 1;
+ aom_accounting_init(&pbi->accounting);
+#endif
+#endif
+ cm->error.setjmp = 0;
+
+#ifdef ORI_CODE
+ aom_get_worker_interface()->init(&pbi->lf_worker);
+ pbi->lf_worker.thread_name = "aom lf worker";
+#endif
+
+ return pbi;
+}
+
+int release_fb_cb(void *cb_priv, aom_codec_frame_buffer_t *fb) {
+#if 0
+ InternalFrameBuffer *const int_fb = (InternalFrameBuffer *)fb->priv;
+ (void)cb_priv;
+ if (int_fb) int_fb->in_use = 0;
+#endif
+ return 0;
+}
+
+static void decrease_ref_count(AV1Decoder *pbi, RefCntBuffer *const buf,
+ BufferPool *const pool) {
+ if (buf != NULL) {
+ --buf->ref_count;
+ // Reference counts should never become negative. If this assertion fails,
+ // there is a bug in our reference count management.
+ assert(buf->ref_count >= 0);
+ // A worker may only get a free framebuffer index when calling get_free_fb.
+ // But the raw frame buffer is not set up until we finish decoding header.
+ // So if any error happens during decoding header, frame_bufs[idx] will not
+ // have a valid raw frame buffer.
+ if (buf->ref_count == 0
+#ifdef ORI_CODE
+ && buf->raw_frame_buffer.data
+#endif
+ ) {
+#ifdef AML
+ av1_release_buf(pbi, buf);
+#endif
+ release_fb_cb(pool->cb_priv, &buf->raw_frame_buffer);
+ buf->raw_frame_buffer.data = NULL;
+ buf->raw_frame_buffer.size = 0;
+ buf->raw_frame_buffer.priv = NULL;
+ }
+ }
+}
+
+static void swap_frame_buffers(AV1Decoder *pbi, int frame_decoded) {
+ int ref_index = 0, mask;
+ AV1_COMMON *const cm = &pbi->common;
+ BufferPool *const pool = cm->buffer_pool;
+ unsigned long flags;
+
+ if (frame_decoded) {
+ int check_on_show_existing_frame;
+ lock_buffer_pool(pool, flags);
+
+ // In ext-tile decoding, the camera frame header is only decoded once. So,
+ // we don't release the references here.
+ if (!pbi->camera_frame_header_ready) {
+ // If we are not holding reference buffers in cm->next_ref_frame_map,
+ // assert that the following two for loops are no-ops.
+ assert(IMPLIES(!pbi->hold_ref_buf,
+ cm->current_frame.refresh_frame_flags == 0));
+ assert(IMPLIES(!pbi->hold_ref_buf,
+ cm->show_existing_frame && !pbi->reset_decoder_state));
+
+ // The following two for loops need to release the reference stored in
+ // cm->ref_frame_map[ref_index] before transferring the reference stored
+ // in cm->next_ref_frame_map[ref_index] to cm->ref_frame_map[ref_index].
+ for (mask = cm->current_frame.refresh_frame_flags; mask; mask >>= 1) {
+ decrease_ref_count(pbi, cm->ref_frame_map[ref_index], pool);
+ cm->ref_frame_map[ref_index] = cm->next_ref_frame_map[ref_index];
+ cm->next_ref_frame_map[ref_index] = NULL;
+ ++ref_index;
+ }
+
+ check_on_show_existing_frame =
+ !cm->show_existing_frame || pbi->reset_decoder_state;
+ for (; ref_index < REF_FRAMES && check_on_show_existing_frame;
+ ++ref_index) {
+ decrease_ref_count(pbi, cm->ref_frame_map[ref_index], pool);
+ cm->ref_frame_map[ref_index] = cm->next_ref_frame_map[ref_index];
+ cm->next_ref_frame_map[ref_index] = NULL;
+ }
+ }
+
+ if (cm->show_existing_frame || cm->show_frame) {
+ if (pbi->output_all_layers) {
+ // Append this frame to the output queue
+ if (pbi->num_output_frames >= MAX_NUM_SPATIAL_LAYERS) {
+ // We can't store the new frame anywhere, so drop it and return an
+ // error
+ cm->cur_frame->buf.corrupted = 1;
+ decrease_ref_count(pbi, cm->cur_frame, pool);
+ cm->error.error_code = AOM_CODEC_UNSUP_BITSTREAM;
+ } else {
+ pbi->output_frames[pbi->num_output_frames] = cm->cur_frame;
+ pbi->num_output_frames++;
+ }
+ } else {
+ // Replace any existing output frame
+ assert(pbi->num_output_frames == 0 || pbi->num_output_frames == 1);
+ if (pbi->num_output_frames > 0) {
+ decrease_ref_count(pbi, pbi->output_frames[0], pool);
+ }
+ pbi->output_frames[0] = cm->cur_frame;
+ pbi->num_output_frames = 1;
+ }
+ } else {
+ decrease_ref_count(pbi, cm->cur_frame, pool);
+ }
+
+ unlock_buffer_pool(pool, flags);
+ } else {
+ // The code here assumes we are not holding reference buffers in
+ // cm->next_ref_frame_map. If this assertion fails, we are leaking the
+ // frame buffer references in cm->next_ref_frame_map.
+ assert(IMPLIES(!pbi->camera_frame_header_ready, !pbi->hold_ref_buf));
+ // Nothing was decoded, so just drop this frame buffer
+ lock_buffer_pool(pool, flags);
+ decrease_ref_count(pbi, cm->cur_frame, pool);
+ unlock_buffer_pool(pool, flags);
+ }
+ cm->cur_frame = NULL;
+
+ if (!pbi->camera_frame_header_ready) {
+ pbi->hold_ref_buf = 0;
+
+ // Invalidate these references until the next frame starts.
+ for (ref_index = 0; ref_index < INTER_REFS_PER_FRAME; ref_index++) {
+ cm->remapped_ref_idx[ref_index] = INVALID_IDX;
+ }
+ }
+}
+
+void aom_internal_error(struct aom_internal_error_info *info,
+ aom_codec_err_t error, const char *fmt, ...) {
+ va_list ap;
+
+ info->error_code = error;
+ info->has_detail = 0;
+
+ if (fmt) {
+ size_t sz = sizeof(info->detail);
+
+ info->has_detail = 1;
+ va_start(ap, fmt);
+ vsnprintf(info->detail, sz - 1, fmt, ap);
+ va_end(ap);
+ info->detail[sz - 1] = '\0';
+ }
+#ifdef ORI_CODE
+ if (info->setjmp) longjmp(info->jmp, info->error_code);
+#endif
+}
+
+#ifdef ORI_CODE
+void av1_zero_unused_internal_frame_buffers(InternalFrameBufferList *list) {
+ int i;
+
+ assert(list != NULL);
+
+ for (i = 0; i < list->num_internal_frame_buffers; ++i) {
+ if (list->int_fb[i].data && !list->int_fb[i].in_use)
+ memset(list->int_fb[i].data, 0, list->int_fb[i].size);
+ }
+}
+#endif
+
+// Release the references to the frame buffers in cm->ref_frame_map and reset
+// all elements of cm->ref_frame_map to NULL.
+static void reset_ref_frame_map(AV1Decoder *const pbi) {
+ AV1_COMMON *const cm = &pbi->common;
+ BufferPool *const pool = cm->buffer_pool;
+ int i;
+
+ for (i = 0; i < REF_FRAMES; i++) {
+ decrease_ref_count(pbi, cm->ref_frame_map[i], pool);
+ cm->ref_frame_map[i] = NULL;
+#ifdef AML
+ cm->next_used_ref_frame_map[i] = NULL;
+#endif
+ }
+}
+
+// Generate next_ref_frame_map.
+static void generate_next_ref_frame_map(AV1Decoder *const pbi) {
+ AV1_COMMON *const cm = &pbi->common;
+ BufferPool *const pool = cm->buffer_pool;
+ unsigned long flags;
+ int ref_index = 0;
+ int mask;
+
+ lock_buffer_pool(pool, flags);
+ // cm->next_ref_frame_map holds references to frame buffers. After storing a
+ // frame buffer index in cm->next_ref_frame_map, we need to increase the
+ // frame buffer's ref_count.
+ for (mask = cm->current_frame.refresh_frame_flags; mask; mask >>= 1) {
+ if (mask & 1) {
+ cm->next_ref_frame_map[ref_index] = cm->cur_frame;
+ } else {
+ cm->next_ref_frame_map[ref_index] = cm->ref_frame_map[ref_index];
+ }
+ if (cm->next_ref_frame_map[ref_index] != NULL)
+ ++cm->next_ref_frame_map[ref_index]->ref_count;
+ ++ref_index;
+ }
+
+ for (; ref_index < REF_FRAMES; ++ref_index) {
+ cm->next_ref_frame_map[ref_index] = cm->ref_frame_map[ref_index];
+ if (cm->next_ref_frame_map[ref_index] != NULL)
+ ++cm->next_ref_frame_map[ref_index]->ref_count;
+ }
+ unlock_buffer_pool(pool, flags);
+ pbi->hold_ref_buf = 1;
+}
+
+// If the refresh_frame_flags bitmask is set, update reference frame id values
+// and mark frames as valid for reference.
+static void update_ref_frame_id(AV1_COMMON *const cm, int frame_id) {
+ int i;
+ int refresh_frame_flags = cm->current_frame.refresh_frame_flags;
+ assert(cm->seq_params.frame_id_numbers_present_flag);
+ for (i = 0; i < REF_FRAMES; i++) {
+ if ((refresh_frame_flags >> i) & 1) {
+ cm->ref_frame_id[i] = frame_id;
+ cm->valid_for_referencing[i] = 1;
+ }
+ }
+}
+
+static void show_existing_frame_reset(AV1Decoder *const pbi,
+ int existing_frame_idx) {
+ AV1_COMMON *const cm = &pbi->common;
+ int i;
+ assert(cm->show_existing_frame);
+
+ cm->current_frame.frame_type = KEY_FRAME;
+
+ cm->current_frame.refresh_frame_flags = (1 << REF_FRAMES) - 1;
+
+ for (i = 0; i < INTER_REFS_PER_FRAME; ++i) {
+ cm->remapped_ref_idx[i] = INVALID_IDX;
+ }
+
+ if (pbi->need_resync) {
+ reset_ref_frame_map(pbi);
+ pbi->need_resync = 0;
+ }
+
+ // Note that the displayed frame must be valid for referencing in order to
+ // have been selected.
+ if (cm->seq_params.frame_id_numbers_present_flag) {
+ cm->current_frame_id = cm->ref_frame_id[existing_frame_idx];
+ update_ref_frame_id(cm, cm->current_frame_id);
+ }
+
+ cm->refresh_frame_context = REFRESH_FRAME_CONTEXT_DISABLED;
+
+ generate_next_ref_frame_map(pbi);
+
+#ifdef ORI_CODE
+ // Reload the adapted CDFs from when we originally coded this keyframe
+ *cm->fc = cm->next_ref_frame_map[existing_frame_idx]->frame_context;
+#endif
+}
+
+static void reset_frame_buffers(AV1Decoder *const pbi) {
+ AV1_COMMON *const cm = &pbi->common;
+ RefCntBuffer *const frame_bufs = cm->buffer_pool->frame_bufs;
+ int i;
+ unsigned long flags;
+
+ // We have not stored any references to frame buffers in
+ // cm->next_ref_frame_map, so we can directly reset it to all NULL.
+ for (i = 0; i < REF_FRAMES; ++i) {
+ cm->next_ref_frame_map[i] = NULL;
+ }
+
+ lock_buffer_pool(cm->buffer_pool, flags);
+ reset_ref_frame_map(pbi);
+ assert(cm->cur_frame->ref_count == 1);
+ for (i = 0; i < FRAME_BUFFERS; ++i) {
+ // Reset all unreferenced frame buffers. We can also reset cm->cur_frame
+ // because we are the sole owner of cm->cur_frame.
+ if (frame_bufs[i].ref_count > 0 && &frame_bufs[i] != cm->cur_frame) {
+ continue;
+ }
+ frame_bufs[i].order_hint = 0;
+ av1_zero(frame_bufs[i].ref_order_hints);
+ }
+#ifdef ORI_CODE
+ av1_zero_unused_internal_frame_buffers(&cm->buffer_pool->int_frame_buffers);
+#endif
+ unlock_buffer_pool(cm->buffer_pool, flags);
+}
+
+static int frame_is_intra_only(const AV1_COMMON *const cm) {
+ return cm->current_frame.frame_type == KEY_FRAME ||
+ cm->current_frame.frame_type == INTRA_ONLY_FRAME;
+}
+
+static int frame_is_sframe(const AV1_COMMON *cm) {
+ return cm->current_frame.frame_type == S_FRAME;
+}
+
+// These functions take a reference frame label between LAST_FRAME and
+// EXTREF_FRAME inclusive. Note that this is different to the indexing
+// previously used by the frame_refs[] array.
+static int get_ref_frame_map_idx(const AV1_COMMON *const cm,
+ const MV_REFERENCE_FRAME ref_frame) {
+ return (ref_frame >= LAST_FRAME && ref_frame <= EXTREF_FRAME)
+ ? cm->remapped_ref_idx[ref_frame - LAST_FRAME]
+ : INVALID_IDX;
+}
+
+static RefCntBuffer *get_ref_frame_buf(
+ const AV1_COMMON *const cm, const MV_REFERENCE_FRAME ref_frame) {
+ const int map_idx = get_ref_frame_map_idx(cm, ref_frame);
+ return (map_idx != INVALID_IDX) ? cm->ref_frame_map[map_idx] : NULL;
+}
+#ifdef SUPPORT_SCALE_FACTOR
+static struct scale_factors *get_ref_scale_factors(
+ AV1_COMMON *const cm, const MV_REFERENCE_FRAME ref_frame) {
+ const int map_idx = get_ref_frame_map_idx(cm, ref_frame);
+ return (map_idx != INVALID_IDX) ? &cm->ref_scale_factors[map_idx] : NULL;
+}
+#endif
+static RefCntBuffer *get_primary_ref_frame_buf(
+ const AV1_COMMON *const cm) {
+ int map_idx;
+ if (cm->primary_ref_frame == PRIMARY_REF_NONE) return NULL;
+ map_idx = get_ref_frame_map_idx(cm, cm->primary_ref_frame + 1);
+ return (map_idx != INVALID_IDX) ? cm->ref_frame_map[map_idx] : NULL;
+}
+
+static int get_relative_dist(const OrderHintInfo *oh, int a, int b) {
+ int bits;
+ int m;
+ int diff;
+ if (!oh->enable_order_hint) return 0;
+
+ bits = oh->order_hint_bits_minus_1 + 1;
+
+ assert(bits >= 1);
+ assert(a >= 0 && a < (1 << bits));
+ assert(b >= 0 && b < (1 << bits));
+
+ diff = a - b;
+ m = 1 << (bits - 1);
+ diff = (diff & (m - 1)) - (diff & m);
+ return diff;
+}
+
+
+void av1_read_frame_size(union param_u *params, int num_bits_width,
+ int num_bits_height, int *width, int *height, int* dec_width) {
+ *width = params->p.frame_width;
+ *height = params->p.frame_height;//aom_rb_read_literal(rb, num_bits_height) + 1;
+#ifdef AML
+ *dec_width = params->p.dec_frame_width;
+#endif
+}
+
+static REFERENCE_MODE read_frame_reference_mode(
+ const AV1_COMMON *cm, union param_u *params) {
+ if (frame_is_intra_only(cm)) {
+ return SINGLE_REFERENCE;
+ } else {
+ return params->p.reference_mode ? REFERENCE_MODE_SELECT : SINGLE_REFERENCE;
+ }
+}
+
+static inline int calc_mi_size(int len) {
+ // len is in mi units. Align to a multiple of SBs.
+ return ALIGN_POWER_OF_TWO(len, MAX_MIB_SIZE_LOG2);
+}
+
+void av1_set_mb_mi(AV1_COMMON *cm, int width, int height) {
+ // Ensure that the decoded width and height are both multiples of
+ // 8 luma pixels (note: this may only be a multiple of 4 chroma pixels if
+ // subsampling is used).
+ // This simplifies the implementation of various experiments,
+ // eg. cdef, which operates on units of 8x8 luma pixels.
+ const int aligned_width = ALIGN_POWER_OF_TWO(width, 3);
+ const int aligned_height = ALIGN_POWER_OF_TWO(height, 3);
+ av1_print2(VP9_DEBUG_BUFMGR_DETAIL, " [PICTURE] av1_set_mb_mi (%d X %d)\n", width, height);
+
+ cm->mi_cols = aligned_width >> MI_SIZE_LOG2;
+ cm->mi_rows = aligned_height >> MI_SIZE_LOG2;
+ cm->mi_stride = calc_mi_size(cm->mi_cols);
+
+ cm->mb_cols = (cm->mi_cols + 2) >> 2;
+ cm->mb_rows = (cm->mi_rows + 2) >> 2;
+ cm->MBs = cm->mb_rows * cm->mb_cols;
+
+#if CONFIG_LPF_MASK
+ alloc_loop_filter_mask(cm);
+#endif
+}
+
+int av1_alloc_context_buffers(AV1_COMMON *cm, int width, int height) {
+#ifdef ORI_CODE
+ int new_mi_size;
+#endif
+ av1_set_mb_mi(cm, width, height);
+#ifdef ORI_CODE
+ new_mi_size = cm->mi_stride * calc_mi_size(cm->mi_rows);
+ if (cm->mi_alloc_size < new_mi_size) {
+ cm->free_mi(cm);
+ if (cm->alloc_mi(cm, new_mi_size)) goto fail;
+ }
+#endif
+ return 0;
+
+#ifdef ORI_CODE
+fail:
+#endif
+ // clear the mi_* values to force a realloc on resync
+ av1_set_mb_mi(cm, 0, 0);
+#ifdef ORI_CODE
+ av1_free_context_buffers(cm);
+#endif
+ return 1;
+}
+
+#ifndef USE_SCALED_WIDTH_FROM_UCODE
+static void calculate_scaled_size_helper(int *dim, int denom) {
+ if (denom != SCALE_NUMERATOR) {
+ // We need to ensure the constraint in "Appendix A" of the spec:
+ // * FrameWidth is greater than or equal to 16
+ // * FrameHeight is greater than or equal to 16
+ // For this, we clamp the downscaled dimension to at least 16. One
+ // exception: if original dimension itself was < 16, then we keep the
+ // downscaled dimension to be same as the original, to ensure that resizing
+ // is valid.
+ const int min_dim = AOMMIN(16, *dim);
+ // Use this version if we need *dim to be even
+ // *width = (*width * SCALE_NUMERATOR + denom) / (2 * denom);
+ // *width <<= 1;
+ *dim = (*dim * SCALE_NUMERATOR + denom / 2) / (denom);
+ *dim = AOMMAX(*dim, min_dim);
+ }
+}
+#ifdef ORI_CODE
+void av1_calculate_scaled_size(int *width, int *height, int resize_denom) {
+ calculate_scaled_size_helper(width, resize_denom);
+ calculate_scaled_size_helper(height, resize_denom);
+}
+#endif
+void av1_calculate_scaled_superres_size(int *width, int *height,
+ int superres_denom) {
+ (void)height;
+ calculate_scaled_size_helper(width, superres_denom);
+}
+#endif
+
+static void setup_superres(AV1_COMMON *const cm, union param_u *params,
+ int *width, int *height) {
+#ifdef USE_SCALED_WIDTH_FROM_UCODE
+ cm->superres_upscaled_width = params->p.frame_width_scaled;
+ cm->superres_upscaled_height = params->p.frame_height;
+
+
+ *width = params->p.dec_frame_width;
+ *height = params->p.frame_height;
+ av1_print2(VP9_DEBUG_BUFMGR_DETAIL, " [PICTURE] set decoding size to (%d X %d) scaled size to (%d X %d)\n",
+ *width, *height,
+ cm->superres_upscaled_width,
+ cm->superres_upscaled_height);
+#else
+ cm->superres_upscaled_width = *width;
+ cm->superres_upscaled_height = *height;
+
+ const SequenceHeader *const seq_params = &cm->seq_params;
+ if (!seq_params->enable_superres) return;
+
+ //if (aom_rb_read_bit(-1, defmark, rb)) {
+ if (params->p.superres_scale_denominator != SCALE_NUMERATOR) {
+#ifdef ORI_CODE
+ cm->superres_scale_denominator =
+ (uint8_t)aom_rb_read_literal(-1, defmark, rb, SUPERRES_SCALE_BITS);
+ cm->superres_scale_denominator += SUPERRES_SCALE_DENOMINATOR_MIN;
+#else
+ cm->superres_scale_denominator = params->p.superres_scale_denominator;
+#endif
+ // Don't edit cm->width or cm->height directly, or the buffers won't get
+ // resized correctly
+ av1_calculate_scaled_superres_size(width, height,
+ cm->superres_scale_denominator);
+ } else {
+ // 1:1 scaling - ie. no scaling, scale not provided
+ cm->superres_scale_denominator = SCALE_NUMERATOR;
+ }
+/*!USE_SCALED_WIDTH_FROM_UCODE*/
+#endif
+}
+
+static void resize_context_buffers(AV1_COMMON *cm, int width, int height) {
+#if CONFIG_SIZE_LIMIT
+ if (width > DECODE_WIDTH_LIMIT || height > DECODE_HEIGHT_LIMIT)
+ aom_internal_error(&cm->error, AOM_CODEC_CORRUPT_FRAME,
+ "Dimensions of %dx%d beyond allowed size of %dx%d.",
+ width, height, DECODE_WIDTH_LIMIT, DECODE_HEIGHT_LIMIT);
+#endif
+ if (cm->width != width || cm->height != height) {
+ const int new_mi_rows =
+ ALIGN_POWER_OF_TWO(height, MI_SIZE_LOG2) >> MI_SIZE_LOG2;
+ const int new_mi_cols =
+ ALIGN_POWER_OF_TWO(width, MI_SIZE_LOG2) >> MI_SIZE_LOG2;
+
+ // Allocations in av1_alloc_context_buffers() depend on individual
+ // dimensions as well as the overall size.
+ if (new_mi_cols > cm->mi_cols || new_mi_rows > cm->mi_rows) {
+ if (av1_alloc_context_buffers(cm, width, height)) {
+ // The cm->mi_* values have been cleared and any existing context
+ // buffers have been freed. Clear cm->width and cm->height to be
+ // consistent and to force a realloc next time.
+ cm->width = 0;
+ cm->height = 0;
+ aom_internal_error(&cm->error, AOM_CODEC_MEM_ERROR,
+ "Failed to allocate context buffers");
+ }
+ } else {
+ av1_set_mb_mi(cm, width, height);
+ }
+#ifdef ORI_CODE
+ av1_init_context_buffers(cm);
+#endif
+ cm->width = width;
+ cm->height = height;
+ }
+
+#ifdef ORI_CODE
+ ensure_mv_buffer(cm->cur_frame, cm);
+#endif
+ cm->cur_frame->width = cm->width;
+ cm->cur_frame->height = cm->height;
+}
+
+static void setup_buffer_pool(AV1_COMMON *cm) {
+ BufferPool *const pool = cm->buffer_pool;
+ const SequenceHeader *const seq_params = &cm->seq_params;
+ unsigned long flags;
+
+ lock_buffer_pool(pool, flags);
+ if (aom_realloc_frame_buffer(cm, &cm->cur_frame->buf,
+ cm->width, cm->height, cm->cur_frame->order_hint)) {
+ unlock_buffer_pool(pool, flags);
+ aom_internal_error(&cm->error, AOM_CODEC_MEM_ERROR,
+ "Failed to allocate frame buffer");
+ }
+ unlock_buffer_pool(pool, flags);
+
+ cm->cur_frame->buf.bit_depth = (unsigned int)seq_params->bit_depth;
+ cm->cur_frame->buf.color_primaries = seq_params->color_primaries;
+ cm->cur_frame->buf.transfer_characteristics =
+ seq_params->transfer_characteristics;
+ cm->cur_frame->buf.matrix_coefficients = seq_params->matrix_coefficients;
+ cm->cur_frame->buf.monochrome = seq_params->monochrome;
+ cm->cur_frame->buf.chroma_sample_position =
+ seq_params->chroma_sample_position;
+ cm->cur_frame->buf.color_range = seq_params->color_range;
+ cm->cur_frame->buf.render_width = cm->render_width;
+ cm->cur_frame->buf.render_height = cm->render_height;
+}
+
+static void setup_frame_size(AV1_COMMON *cm, int frame_size_override_flag, union param_u *params) {
+ const SequenceHeader *const seq_params = &cm->seq_params;
+ int width, height, dec_width;
+
+ if (frame_size_override_flag) {
+ int num_bits_width = seq_params->num_bits_width;
+ int num_bits_height = seq_params->num_bits_height;
+ av1_read_frame_size(params, num_bits_width, num_bits_height, &width, &height, &dec_width);
+#ifdef AML
+ cm->dec_width = dec_width;
+#endif
+ if (width > seq_params->max_frame_width ||
+ height > seq_params->max_frame_height) {
+ aom_internal_error(&cm->error, AOM_CODEC_CORRUPT_FRAME,
+ "Frame dimensions are larger than the maximum values");
+ }
+ } else {
+ width = seq_params->max_frame_width;
+ height = seq_params->max_frame_height;
+#ifdef AML
+ cm->dec_width = dec_width = params->p.dec_frame_width;
+#endif
+ }
+ setup_superres(cm, params, &width, &height);
+ resize_context_buffers(cm, width, height);
+#ifdef ORI_CODE
+ setup_render_size(cm, params);
+#endif
+ setup_buffer_pool(cm);
+}
+
+static int valid_ref_frame_img_fmt(aom_bit_depth_t ref_bit_depth,
+ int ref_xss, int ref_yss,
+ aom_bit_depth_t this_bit_depth,
+ int this_xss, int this_yss) {
+ return ref_bit_depth == this_bit_depth && ref_xss == this_xss &&
+ ref_yss == this_yss;
+}
+
+static void setup_frame_size_with_refs(AV1_COMMON *cm, union param_u *params) {
+ int width, height, dec_width;
+ int found = 0;
+ int has_valid_ref_frame = 0;
+ int i;
+ SequenceHeader *seq_params;
+ for (i = LAST_FRAME; i <= ALTREF_FRAME; ++i) {
+ /*if (aom_rb_read_bit(rb)) {*/
+ if (params->p.valid_ref_frame_bits & (1<<i)) {
+ const RefCntBuffer *const ref_buf = get_ref_frame_buf(cm, i);
+ // This will never be NULL in a normal stream, as streams are required to
+ // have a shown keyframe before any inter frames, which would refresh all
+ // the reference buffers. However, it might be null if we're starting in
+ // the middle of a stream, and static analysis will error if we don't do
+ // a null check here.
+ if (ref_buf == NULL) {
+ aom_internal_error(&cm->error, AOM_CODEC_CORRUPT_FRAME,
+ "Invalid condition: invalid reference buffer");
+ } else {
+ const PIC_BUFFER_CONFIG *const buf = &ref_buf->buf;
+ width = buf->y_crop_width;
+ height = buf->y_crop_height;
+ cm->render_width = buf->render_width;
+ cm->render_height = buf->render_height;
+ setup_superres(cm, params, &width, &height);
+ resize_context_buffers(cm, width, height);
+ found = 1;
+ break;
+ }
+ }
+ }
+
+ seq_params = &cm->seq_params;
+ if (!found) {
+ int num_bits_width = seq_params->num_bits_width;
+ int num_bits_height = seq_params->num_bits_height;
+
+ av1_read_frame_size(params, num_bits_width, num_bits_height, &width, &height, &dec_width);
+#ifdef AML
+ cm->dec_width = dec_width;
+#endif
+ setup_superres(cm, params, &width, &height);
+ resize_context_buffers(cm, width, height);
+#ifdef ORI_CODE
+ setup_render_size(cm, rb);
+#endif
+ }
+
+ if (width <= 0 || height <= 0)
+ aom_internal_error(&cm->error, AOM_CODEC_CORRUPT_FRAME,
+ "Invalid frame size");
+
+ // Check to make sure at least one of frames that this frame references
+ // has valid dimensions.
+ for (i = LAST_FRAME; i <= ALTREF_FRAME; ++i) {
+ const RefCntBuffer *const ref_frame = get_ref_frame_buf(cm, i);
+ if (ref_frame != NULL) {
+ has_valid_ref_frame |=
+ valid_ref_frame_size(ref_frame->buf.y_crop_width,
+ ref_frame->buf.y_crop_height, width, height);
+ }
+ }
+ if (!has_valid_ref_frame)
+ aom_internal_error(&cm->error, AOM_CODEC_CORRUPT_FRAME,
+ "Referenced frame has invalid size");
+ for (i = LAST_FRAME; i <= ALTREF_FRAME; ++i) {
+ const RefCntBuffer *const ref_frame = get_ref_frame_buf(cm, i);
+ if (ref_frame != NULL) {
+ if (!valid_ref_frame_img_fmt(
+ ref_frame->buf.bit_depth, ref_frame->buf.subsampling_x,
+ ref_frame->buf.subsampling_y, seq_params->bit_depth,
+ seq_params->subsampling_x, seq_params->subsampling_y))
+ aom_internal_error(&cm->error, AOM_CODEC_CORRUPT_FRAME,
+ "Referenced frame has incompatible color format");
+ }
+ }
+ setup_buffer_pool(cm);
+}
+
+typedef struct {
+ int map_idx; // frame map index
+ RefCntBuffer *buf; // frame buffer
+ int sort_idx; // index based on the offset to be used for sorting
+} REF_FRAME_INFO;
+
+// Compares the sort_idx fields. If they are equal, then compares the map_idx
+// fields to break the tie. This ensures a stable sort.
+static int compare_ref_frame_info(const void *arg_a, const void *arg_b) {
+ const REF_FRAME_INFO *info_a = (REF_FRAME_INFO *)arg_a;
+ const REF_FRAME_INFO *info_b = (REF_FRAME_INFO *)arg_b;
+
+ const int sort_idx_diff = info_a->sort_idx - info_b->sort_idx;
+ if (sort_idx_diff != 0) return sort_idx_diff;
+ return info_a->map_idx - info_b->map_idx;
+}
+
+
+/*
+for av1_setup_motion_field()
+*/
+static int motion_field_projection(AV1_COMMON *cm,
+ MV_REFERENCE_FRAME start_frame, int dir) {
+#ifdef ORI_CODE
+ TPL_MV_REF *tpl_mvs_base = cm->tpl_mvs;
+ int ref_offset[REF_FRAMES] = { 0 };
+#endif
+ MV_REFERENCE_FRAME rf;
+ const RefCntBuffer *const start_frame_buf =
+ get_ref_frame_buf(cm, start_frame);
+ int start_frame_order_hint;
+ unsigned int const *ref_order_hints;
+ int cur_order_hint;
+ int start_to_current_frame_offset;
+
+#ifdef AML
+ int i;
+ //av1_print2(VP9_DEBUG_BUFMGR_DETAIL, "$$$$$$$$$$$%s:cm->mv_ref_id_index = %d, start_frame=%d\n", __func__, cm->mv_ref_id_index, start_frame);
+ cm->mv_ref_id[cm->mv_ref_id_index] = start_frame;
+ for (i = 0; i < REF_FRAMES; i++) {
+ cm->mv_ref_offset[cm->mv_ref_id_index][i]=0;
+ }
+ cm->mv_cal_tpl_mvs[cm->mv_ref_id_index]=0;
+ cm->mv_ref_id_index++;
+#endif
+ if (start_frame_buf == NULL) return 0;
+
+ if (start_frame_buf->frame_type == KEY_FRAME ||
+ start_frame_buf->frame_type == INTRA_ONLY_FRAME)
+ return 0;
+
+ if (start_frame_buf->mi_rows != cm->mi_rows ||
+ start_frame_buf->mi_cols != cm->mi_cols)
+ return 0;
+
+ start_frame_order_hint = start_frame_buf->order_hint;
+ ref_order_hints =
+ &start_frame_buf->ref_order_hints[0];
+ cur_order_hint = cm->cur_frame->order_hint;
+ start_to_current_frame_offset = get_relative_dist(
+ &cm->seq_params.order_hint_info, start_frame_order_hint, cur_order_hint);
+
+ for (rf = LAST_FRAME; rf <= INTER_REFS_PER_FRAME; ++rf) {
+ cm->mv_ref_offset[cm->mv_ref_id_index-1][rf] = get_relative_dist(&cm->seq_params.order_hint_info,
+ start_frame_order_hint,
+ ref_order_hints[rf - LAST_FRAME]);
+ }
+#ifdef AML
+ cm->mv_cal_tpl_mvs[cm->mv_ref_id_index-1]=1;
+#endif
+ if (dir == 2) start_to_current_frame_offset = -start_to_current_frame_offset;
+#ifdef ORI_CODE
+ MV_REF *mv_ref_base = start_frame_buf->mvs;
+ const int mvs_rows = (cm->mi_rows + 1) >> 1;
+ const int mvs_cols = (cm->mi_cols + 1) >> 1;
+
+ for (int blk_row = 0; blk_row < mvs_rows; ++blk_row) {
+ for (int blk_col = 0; blk_col < mvs_cols; ++blk_col) {
+ MV_REF *mv_ref = &mv_ref_base[blk_row * mvs_cols + blk_col];
+ MV fwd_mv = mv_ref->mv.as_mv;
+
+ if (mv_ref->ref_frame > INTRA_FRAME) {
+ int_mv this_mv;
+ int mi_r, mi_c;
+ const int ref_frame_offset = ref_offset[mv_ref->ref_frame];
+
+ int pos_valid =
+ abs(ref_frame_offset) <= MAX_FRAME_DISTANCE &&
+ ref_frame_offset > 0 &&
+ abs(start_to_current_frame_offset) <= MAX_FRAME_DISTANCE;
+
+ if (pos_valid) {
+ get_mv_projection(&this_mv.as_mv, fwd_mv,
+ start_to_current_frame_offset, ref_frame_offset);
+ pos_valid = get_block_position(cm, &mi_r, &mi_c, blk_row, blk_col,
+ this_mv.as_mv, dir >> 1);
+ }
+
+ if (pos_valid) {
+ const int mi_offset = mi_r * (cm->mi_stride >> 1) + mi_c;
+
+ tpl_mvs_base[mi_offset].mfmv0.as_mv.row = fwd_mv.row;
+ tpl_mvs_base[mi_offset].mfmv0.as_mv.col = fwd_mv.col;
+ tpl_mvs_base[mi_offset].ref_frame_offset = ref_frame_offset;
+ }
+ }
+ }
+ }
+#endif
+ return 1;
+}
+
+#ifdef AML
+static int setup_motion_field_debug_count = 0;
+#endif
+void av1_setup_motion_field(AV1_COMMON *cm) {
+ const OrderHintInfo *const order_hint_info = &cm->seq_params.order_hint_info;
+ int ref_frame;
+ int size;
+ int cur_order_hint;
+ const RefCntBuffer *ref_buf[INTER_REFS_PER_FRAME];
+ int ref_order_hint[INTER_REFS_PER_FRAME];
+ int ref_stamp;
+ memset(cm->ref_frame_side, 0, sizeof(cm->ref_frame_side));
+ if (!order_hint_info->enable_order_hint) return;
+#ifdef ORI_CODE
+ TPL_MV_REF *tpl_mvs_base = cm->tpl_mvs;
+#endif
+ size = ((cm->mi_rows + MAX_MIB_SIZE) >> 1) * (cm->mi_stride >> 1);
+#ifdef ORI_CODE
+ for (int idx = 0; idx < size; ++idx) {
+ tpl_mvs_base[idx].mfmv0.as_int = INVALID_MV;
+ tpl_mvs_base[idx].ref_frame_offset = 0;
+ }
+#endif
+ cur_order_hint = cm->cur_frame->order_hint;
+
+ for (ref_frame = LAST_FRAME; ref_frame <= ALTREF_FRAME; ref_frame++) {
+ const int ref_idx = ref_frame - LAST_FRAME;
+ const RefCntBuffer *const buf = get_ref_frame_buf(cm, ref_frame);
+ int order_hint = 0;
+
+ if (buf != NULL) order_hint = buf->order_hint;
+
+ ref_buf[ref_idx] = buf;
+ ref_order_hint[ref_idx] = order_hint;
+
+ if (get_relative_dist(order_hint_info, order_hint, cur_order_hint) > 0)
+ cm->ref_frame_side[ref_frame] = 1;
+ else if (order_hint == cur_order_hint)
+ cm->ref_frame_side[ref_frame] = -1;
+ }
+ ref_stamp = MFMV_STACK_SIZE - 1;
+#ifdef AML
+ cm->mv_ref_id_index = 0;
+ av1_print2(VP9_DEBUG_BUFMGR_DETAIL, "%s(%d) mi_cols %d mi_rows %d\n",
+ __func__, setup_motion_field_debug_count++,
+ cm->mi_cols,
+ cm->mi_rows
+ );
+#endif
+ if (ref_buf[LAST_FRAME - LAST_FRAME] != NULL) {
+ const int alt_of_lst_order_hint =
+ ref_buf[LAST_FRAME - LAST_FRAME]
+ ->ref_order_hints[ALTREF_FRAME - LAST_FRAME];
+
+ const int is_lst_overlay =
+ (alt_of_lst_order_hint == ref_order_hint[GOLDEN_FRAME - LAST_FRAME]);
+ if (!is_lst_overlay) motion_field_projection(cm, LAST_FRAME, 2);
+ --ref_stamp;
+ }
+
+ if (get_relative_dist(order_hint_info,
+ ref_order_hint[BWDREF_FRAME - LAST_FRAME],
+ cur_order_hint) > 0) {
+ if (motion_field_projection(cm, BWDREF_FRAME, 0)) --ref_stamp;
+ }
+
+ if (get_relative_dist(order_hint_info,
+ ref_order_hint[ALTREF2_FRAME - LAST_FRAME],
+ cur_order_hint) > 0) {
+ if (motion_field_projection(cm, ALTREF2_FRAME, 0)) --ref_stamp;
+ }
+
+ if (get_relative_dist(order_hint_info,
+ ref_order_hint[ALTREF_FRAME - LAST_FRAME],
+ cur_order_hint) > 0 &&
+ ref_stamp >= 0)
+ if (motion_field_projection(cm, ALTREF_FRAME, 0)) --ref_stamp;
+
+ if (ref_stamp >= 0) motion_field_projection(cm, LAST2_FRAME, 2);
+}
+
+
+static void set_ref_frame_info(int *remapped_ref_idx, int frame_idx,
+ REF_FRAME_INFO *ref_info) {
+ assert(frame_idx >= 0 && frame_idx < INTER_REFS_PER_FRAME);
+
+ remapped_ref_idx[frame_idx] = ref_info->map_idx;
+ av1_print2(VP9_DEBUG_BUFMGR_DETAIL, "+++++++++++++%s:remapped_ref_idx[%d]=0x%x\n", __func__, frame_idx, ref_info->map_idx);
+}
+
+
+void av1_set_frame_refs(AV1_COMMON *const cm, int *remapped_ref_idx,
+ int lst_map_idx, int gld_map_idx) {
+ int lst_frame_sort_idx = -1;
+ int gld_frame_sort_idx = -1;
+ int i;
+ //assert(cm->seq_params.order_hint_info.enable_order_hint);
+ //assert(cm->seq_params.order_hint_info.order_hint_bits_minus_1 >= 0);
+ const int cur_order_hint = (int)cm->current_frame.order_hint;
+ const int cur_frame_sort_idx =
+ 1 << cm->seq_params.order_hint_info.order_hint_bits_minus_1;
+
+ REF_FRAME_INFO ref_frame_info[REF_FRAMES];
+ int ref_flag_list[INTER_REFS_PER_FRAME] = { 0, 0, 0, 0, 0, 0, 0 };
+ int bwd_start_idx;
+ int bwd_end_idx;
+ int fwd_start_idx, fwd_end_idx;
+ int ref_idx;
+ static const MV_REFERENCE_FRAME ref_frame_list[INTER_REFS_PER_FRAME - 2] = {
+ LAST2_FRAME, LAST3_FRAME, BWDREF_FRAME, ALTREF2_FRAME, ALTREF_FRAME
+ };
+
+ for (i = 0; i < REF_FRAMES; ++i) {
+ const int map_idx = i;
+ RefCntBuffer *buf;
+ int offset;
+
+ ref_frame_info[i].map_idx = map_idx;
+ ref_frame_info[i].sort_idx = -1;
+
+ buf = cm->ref_frame_map[map_idx];
+ ref_frame_info[i].buf = buf;
+
+ if (buf == NULL) continue;
+ // If this assertion fails, there is a reference leak.
+ assert(buf->ref_count > 0);
+
+ offset = (int)buf->order_hint;
+ ref_frame_info[i].sort_idx =
+ (offset == -1) ? -1
+ : cur_frame_sort_idx +
+ get_relative_dist(&cm->seq_params.order_hint_info,
+ offset, cur_order_hint);
+ assert(ref_frame_info[i].sort_idx >= -1);
+
+ if (map_idx == lst_map_idx) lst_frame_sort_idx = ref_frame_info[i].sort_idx;
+ if (map_idx == gld_map_idx) gld_frame_sort_idx = ref_frame_info[i].sort_idx;
+ }
+
+ // Confirm both LAST_FRAME and GOLDEN_FRAME are valid forward reference
+ // frames.
+ if (lst_frame_sort_idx == -1 || lst_frame_sort_idx >= cur_frame_sort_idx) {
+ aom_internal_error(&cm->error, AOM_CODEC_CORRUPT_FRAME,
+ "Inter frame requests a look-ahead frame as LAST");
+ }
+ if (gld_frame_sort_idx == -1 || gld_frame_sort_idx >= cur_frame_sort_idx) {
+ aom_internal_error(&cm->error, AOM_CODEC_CORRUPT_FRAME,
+ "Inter frame requests a look-ahead frame as GOLDEN");
+ }
+
+ // Sort ref frames based on their frame_offset values.
+ qsort(ref_frame_info, REF_FRAMES, sizeof(REF_FRAME_INFO),
+ compare_ref_frame_info);
+
+ // Identify forward and backward reference frames.
+ // Forward reference: offset < order_hint
+ // Backward reference: offset >= order_hint
+ fwd_start_idx = 0;
+ fwd_end_idx = REF_FRAMES - 1;
+
+ for (i = 0; i < REF_FRAMES; i++) {
+ if (ref_frame_info[i].sort_idx == -1) {
+ fwd_start_idx++;
+ continue;
+ }
+
+ if (ref_frame_info[i].sort_idx >= cur_frame_sort_idx) {
+ fwd_end_idx = i - 1;
+ break;
+ }
+ }
+
+ bwd_start_idx = fwd_end_idx + 1;
+ bwd_end_idx = REF_FRAMES - 1;
+
+ // === Backward Reference Frames ===
+
+ // == ALTREF_FRAME ==
+ if (bwd_start_idx <= bwd_end_idx) {
+ set_ref_frame_info(remapped_ref_idx, ALTREF_FRAME - LAST_FRAME,
+ &ref_frame_info[bwd_end_idx]);
+ ref_flag_list[ALTREF_FRAME - LAST_FRAME] = 1;
+ bwd_end_idx--;
+ }
+
+ // == BWDREF_FRAME ==
+ if (bwd_start_idx <= bwd_end_idx) {
+ set_ref_frame_info(remapped_ref_idx, BWDREF_FRAME - LAST_FRAME,
+ &ref_frame_info[bwd_start_idx]);
+ ref_flag_list[BWDREF_FRAME - LAST_FRAME] = 1;
+ bwd_start_idx++;
+ }
+
+ // == ALTREF2_FRAME ==
+ if (bwd_start_idx <= bwd_end_idx) {
+ set_ref_frame_info(remapped_ref_idx, ALTREF2_FRAME - LAST_FRAME,
+ &ref_frame_info[bwd_start_idx]);
+ ref_flag_list[ALTREF2_FRAME - LAST_FRAME] = 1;
+ }
+
+ // === Forward Reference Frames ===
+
+ for (i = fwd_start_idx; i <= fwd_end_idx; ++i) {
+ // == LAST_FRAME ==
+ if (ref_frame_info[i].map_idx == lst_map_idx) {
+ set_ref_frame_info(remapped_ref_idx, LAST_FRAME - LAST_FRAME,
+ &ref_frame_info[i]);
+ ref_flag_list[LAST_FRAME - LAST_FRAME] = 1;
+ }
+
+ // == GOLDEN_FRAME ==
+ if (ref_frame_info[i].map_idx == gld_map_idx) {
+ set_ref_frame_info(remapped_ref_idx, GOLDEN_FRAME - LAST_FRAME,
+ &ref_frame_info[i]);
+ ref_flag_list[GOLDEN_FRAME - LAST_FRAME] = 1;
+ }
+ }
+
+ assert(ref_flag_list[LAST_FRAME - LAST_FRAME] == 1 &&
+ ref_flag_list[GOLDEN_FRAME - LAST_FRAME] == 1);
+
+ // == LAST2_FRAME ==
+ // == LAST3_FRAME ==
+ // == BWDREF_FRAME ==
+ // == ALTREF2_FRAME ==
+ // == ALTREF_FRAME ==
+
+ // Set up the reference frames in the anti-chronological order.
+ for (ref_idx = 0; ref_idx < (INTER_REFS_PER_FRAME - 2); ref_idx++) {
+ const MV_REFERENCE_FRAME ref_frame = ref_frame_list[ref_idx];
+
+ if (ref_flag_list[ref_frame - LAST_FRAME] == 1) continue;
+
+ while (fwd_start_idx <= fwd_end_idx &&
+ (ref_frame_info[fwd_end_idx].map_idx == lst_map_idx ||
+ ref_frame_info[fwd_end_idx].map_idx == gld_map_idx)) {
+ fwd_end_idx--;
+ }
+ if (fwd_start_idx > fwd_end_idx) break;
+
+ set_ref_frame_info(remapped_ref_idx, ref_frame - LAST_FRAME,
+ &ref_frame_info[fwd_end_idx]);
+ ref_flag_list[ref_frame - LAST_FRAME] = 1;
+
+ fwd_end_idx--;
+ }
+
+ // Assign all the remaining frame(s), if any, to the earliest reference frame.
+ for (; ref_idx < (INTER_REFS_PER_FRAME - 2); ref_idx++) {
+ const MV_REFERENCE_FRAME ref_frame = ref_frame_list[ref_idx];
+ if (ref_flag_list[ref_frame - LAST_FRAME] == 1) continue;
+ set_ref_frame_info(remapped_ref_idx, ref_frame - LAST_FRAME,
+ &ref_frame_info[fwd_start_idx]);
+ ref_flag_list[ref_frame - LAST_FRAME] = 1;
+ }
+
+ for (i = 0; i < INTER_REFS_PER_FRAME; i++) {
+ assert(ref_flag_list[i] == 1);
+ }
+}
+
+void av1_setup_frame_buf_refs(AV1_COMMON *cm) {
+ MV_REFERENCE_FRAME ref_frame;
+ cm->cur_frame->order_hint = cm->current_frame.order_hint;
+
+ for (ref_frame = LAST_FRAME; ref_frame <= ALTREF_FRAME; ++ref_frame) {
+ const RefCntBuffer *const buf = get_ref_frame_buf(cm, ref_frame);
+ if (buf != NULL)
+ cm->cur_frame->ref_order_hints[ref_frame - LAST_FRAME] = buf->order_hint;
+ }
+}
+
+void av1_setup_frame_sign_bias(AV1_COMMON *cm) {
+ MV_REFERENCE_FRAME ref_frame;
+ for (ref_frame = LAST_FRAME; ref_frame <= ALTREF_FRAME; ++ref_frame) {
+ const RefCntBuffer *const buf = get_ref_frame_buf(cm, ref_frame);
+ if (cm->seq_params.order_hint_info.enable_order_hint && buf != NULL) {
+ const int ref_order_hint = buf->order_hint;
+ cm->ref_frame_sign_bias[ref_frame] =
+ (get_relative_dist(&cm->seq_params.order_hint_info, ref_order_hint,
+ (int)cm->current_frame.order_hint) <= 0)
+ ? 0
+ : 1;
+ } else {
+ cm->ref_frame_sign_bias[ref_frame] = 0;
+ }
+ }
+}
+
+
+void av1_setup_skip_mode_allowed(AV1_COMMON *cm) {
+ const OrderHintInfo *const order_hint_info = &cm->seq_params.order_hint_info;
+ SkipModeInfo *const skip_mode_info = &cm->current_frame.skip_mode_info;
+ int i;
+ int cur_order_hint;
+ int ref_order_hints[2] = { -1, INT_MAX };
+ int ref_idx[2] = { INVALID_IDX, INVALID_IDX };
+
+ skip_mode_info->skip_mode_allowed = 0;
+ skip_mode_info->ref_frame_idx_0 = INVALID_IDX;
+ skip_mode_info->ref_frame_idx_1 = INVALID_IDX;
+ av1_print2(VP9_DEBUG_BUFMGR_DETAIL, "av1_setup_skip_mode_allowed %d %d %d\n", order_hint_info->enable_order_hint,
+ frame_is_intra_only(cm),
+ cm->current_frame.reference_mode);
+ if (!order_hint_info->enable_order_hint || frame_is_intra_only(cm) ||
+ cm->current_frame.reference_mode == SINGLE_REFERENCE)
+ return;
+
+ cur_order_hint = cm->current_frame.order_hint;
+
+ // Identify the nearest forward and backward references.
+ for (i = 0; i < INTER_REFS_PER_FRAME; ++i) {
+ const RefCntBuffer *const buf = get_ref_frame_buf(cm, LAST_FRAME + i);
+ int ref_order_hint;
+ if (buf == NULL) continue;
+
+ ref_order_hint = buf->order_hint;
+ if (get_relative_dist(order_hint_info, ref_order_hint, cur_order_hint) <
+ 0) {
+ // Forward reference
+ if (ref_order_hints[0] == -1 ||
+ get_relative_dist(order_hint_info, ref_order_hint,
+ ref_order_hints[0]) > 0) {
+ ref_order_hints[0] = ref_order_hint;
+ ref_idx[0] = i;
+ }
+ } else if (get_relative_dist(order_hint_info, ref_order_hint,
+ cur_order_hint) > 0) {
+ // Backward reference
+ if (ref_order_hints[1] == INT_MAX ||
+ get_relative_dist(order_hint_info, ref_order_hint,
+ ref_order_hints[1]) < 0) {
+ ref_order_hints[1] = ref_order_hint;
+ ref_idx[1] = i;
+ }
+ }
+ }
+
+ if (ref_idx[0] != INVALID_IDX && ref_idx[1] != INVALID_IDX) {
+ // == Bi-directional prediction ==
+ skip_mode_info->skip_mode_allowed = 1;
+ skip_mode_info->ref_frame_idx_0 = AOMMIN(ref_idx[0], ref_idx[1]);
+ skip_mode_info->ref_frame_idx_1 = AOMMAX(ref_idx[0], ref_idx[1]);
+ } else if (ref_idx[0] != INVALID_IDX && ref_idx[1] == INVALID_IDX) {
+ // == Forward prediction only ==
+ // Identify the second nearest forward reference.
+ ref_order_hints[1] = -1;
+ for (i = 0; i < INTER_REFS_PER_FRAME; ++i) {
+ const RefCntBuffer *const buf = get_ref_frame_buf(cm, LAST_FRAME + i);
+ int ref_order_hint;
+ if (buf == NULL) continue;
+
+ ref_order_hint = buf->order_hint;
+ if ((ref_order_hints[0] != -1 &&
+ get_relative_dist(order_hint_info, ref_order_hint,
+ ref_order_hints[0]) < 0) &&
+ (ref_order_hints[1] == -1 ||
+ get_relative_dist(order_hint_info, ref_order_hint,
+ ref_order_hints[1]) > 0)) {
+ // Second closest forward reference
+ ref_order_hints[1] = ref_order_hint;
+ ref_idx[1] = i;
+ }
+ }
+ if (ref_order_hints[1] != -1) {
+ skip_mode_info->skip_mode_allowed = 1;
+ skip_mode_info->ref_frame_idx_0 = AOMMIN(ref_idx[0], ref_idx[1]);
+ skip_mode_info->ref_frame_idx_1 = AOMMAX(ref_idx[0], ref_idx[1]);
+ }
+ }
+ av1_print2(VP9_DEBUG_BUFMGR_DETAIL,
+ "skip_mode_info: skip_mode_allowed 0x%x 0x%x 0x%x\n",
+ cm->current_frame.skip_mode_info.skip_mode_allowed,
+ cm->current_frame.skip_mode_info.ref_frame_idx_0,
+ cm->current_frame.skip_mode_info.ref_frame_idx_1);
+}
+
+static inline int frame_might_allow_ref_frame_mvs(const AV1_COMMON *cm) {
+ return !cm->error_resilient_mode &&
+ cm->seq_params.order_hint_info.enable_ref_frame_mvs &&
+ cm->seq_params.order_hint_info.enable_order_hint &&
+ !frame_is_intra_only(cm);
+}
+
+#ifdef ORI_CODE
+/*
+* segmentation
+*/
+static const int seg_feature_data_signed[SEG_LVL_MAX] = {
+ 1, 1, 1, 1, 1, 0, 0, 0
+};
+
+static const int seg_feature_data_max[SEG_LVL_MAX] = { MAXQ,
+ MAX_LOOP_FILTER,
+ MAX_LOOP_FILTER,
+ MAX_LOOP_FILTER,
+ MAX_LOOP_FILTER,
+ 7,
+ 0,
+ 0 };
+
+
+static inline void segfeatures_copy(struct segmentation *dst,
+ const struct segmentation *src) {
+ int i, j;
+ for (i = 0; i < MAX_SEGMENTS; i++) {
+ dst->feature_mask[i] = src->feature_mask[i];
+ for (j = 0; j < SEG_LVL_MAX; j++) {
+ dst->feature_data[i][j] = src->feature_data[i][j];
+ }
+ }
+ dst->segid_preskip = src->segid_preskip;
+ dst->last_active_segid = src->last_active_segid;
+}
+
+static void av1_clearall_segfeatures(struct segmentation *seg) {
+ av1_zero(seg->feature_data);
+ av1_zero(seg->feature_mask);
+}
+
+static void av1_enable_segfeature(struct segmentation *seg, int segment_id,
+ int feature_id) {
+ seg->feature_mask[segment_id] |= 1 << feature_id;
+}
+
+void av1_calculate_segdata(struct segmentation *seg) {
+ seg->segid_preskip = 0;
+ seg->last_active_segid = 0;
+ for (int i = 0; i < MAX_SEGMENTS; i++) {
+ for (int j = 0; j < SEG_LVL_MAX; j++) {
+ if (seg->feature_mask[i] & (1 << j)) {
+ seg->segid_preskip |= (j >= SEG_LVL_REF_FRAME);
+ seg->last_active_segid = i;
+ }
+ }
+ }
+}
+
+static int av1_seg_feature_data_max(int feature_id) {
+ return seg_feature_data_max[feature_id];
+}
+
+static int av1_is_segfeature_signed(int feature_id) {
+ return seg_feature_data_signed[feature_id];
+}
+
+static void av1_set_segdata(struct segmentation *seg, int segment_id,
+ int feature_id, int seg_data) {
+ if (seg_data < 0) {
+ assert(seg_feature_data_signed[feature_id]);
+ assert(-seg_data <= seg_feature_data_max[feature_id]);
+ } else {
+ assert(seg_data <= seg_feature_data_max[feature_id]);
+ }
+
+ seg->feature_data[segment_id][feature_id] = seg_data;
+}
+
+static inline int clamp(int value, int low, int high) {
+ return value < low ? low : (value > high ? high : value);
+}
+
+static void setup_segmentation(AV1_COMMON *const cm,
+ union param_u *params) {
+ struct segmentation *const seg = &cm->seg;
+
+ seg->update_map = 0;
+ seg->update_data = 0;
+ seg->temporal_update = 0;
+
+ seg->enabled = params->p.seg_enabled; //aom_rb_read_bit(-1, defmark, rb);
+ if (!seg->enabled) {
+ if (cm->cur_frame->seg_map)
+ memset(cm->cur_frame->seg_map, 0, (cm->mi_rows * cm->mi_cols));
+
+ memset(seg, 0, sizeof(*seg));
+ segfeatures_copy(&cm->cur_frame->seg, seg);
+ return;
+ }
+ if (cm->seg.enabled && cm->prev_frame &&
+ (cm->mi_rows == cm->prev_frame->mi_rows) &&
+ (cm->mi_cols == cm->prev_frame->mi_cols)) {
+ cm->last_frame_seg_map = cm->prev_frame->seg_map;
+ } else {
+ cm->last_frame_seg_map = NULL;
+ }
+ // Read update flags
+ if (cm->primary_ref_frame == PRIMARY_REF_NONE) {
+ // These frames can't use previous frames, so must signal map + features
+ seg->update_map = 1;
+ seg->temporal_update = 0;
+ seg->update_data = 1;
+ } else {
+ seg->update_map = params->p.seg_update_map; // aom_rb_read_bit(-1, defmark, rb);
+ if (seg->update_map) {
+ seg->temporal_update = params->p.seg_temporal_update; //aom_rb_read_bit(-1, defmark, rb);
+ } else {
+ seg->temporal_update = 0;
+ }
+ seg->update_data = params->p.seg_update_data; //aom_rb_read_bit(-1, defmark, rb);
+ }
+
+ // Segmentation data update
+ if (seg->update_data) {
+ av1_clearall_segfeatures(seg);
+
+ for (int i = 0; i < MAX_SEGMENTS; i++) {
+ for (int j = 0; j < SEG_LVL_MAX; j++) {
+ int data = 0;
+ const int feature_enabled = params->p.seg_feature_enabled ;//aom_rb_read_bit(-1, defmark, rb);
+ if (feature_enabled) {
+ av1_enable_segfeature(seg, i, j);
+
+ const int data_max = av1_seg_feature_data_max(j);
+ const int data_min = -data_max;
+ /*
+ const int ubits = get_unsigned_bits(data_max);
+
+ if (av1_is_segfeature_signed(j)) {
+ data = aom_rb_read_inv_signed_literal(-1, defmark, rb, ubits);
+ } else {
+ data = aom_rb_read_literal(-1, defmark, rb, ubits);
+ }*/
+ data = params->p.seg_data;
+ data = clamp(data, data_min, data_max);
+ }
+ av1_set_segdata(seg, i, j, data);
+ }
+ }
+ av1_calculate_segdata(seg);
+ } else if (cm->prev_frame) {
+ segfeatures_copy(seg, &cm->prev_frame->seg);
+ }
+ segfeatures_copy(&cm->cur_frame->seg, seg);
+}
+#endif
+
+/**/
+
+
+int av1_decode_frame_headers_and_setup(AV1Decoder *pbi, int trailing_bits_present, union param_u *params)
+{
+ AV1_COMMON *const cm = &pbi->common;
+ /*
+ read_uncompressed_header()
+ */
+ const SequenceHeader *const seq_params = &cm->seq_params;
+ CurrentFrame *const current_frame = &cm->current_frame;
+ //MACROBLOCKD *const xd = &pbi->mb;
+ BufferPool *const pool = cm->buffer_pool;
+ RefCntBuffer *const frame_bufs = pool->frame_bufs;
+ int i;
+ int frame_size_override_flag;
+ unsigned long flags;
+
+ if (!pbi->sequence_header_ready) {
+ aom_internal_error(&cm->error, AOM_CODEC_CORRUPT_FRAME,
+ "No sequence header");
+ }
+ cm->last_frame_type = current_frame->frame_type;
+
+ if (seq_params->reduced_still_picture_hdr) {
+ cm->show_existing_frame = 0;
+ cm->show_frame = 1;
+ current_frame->frame_type = KEY_FRAME;
+ if (pbi->sequence_header_changed) {
+ // This is the start of a new coded video sequence.
+ pbi->sequence_header_changed = 0;
+ pbi->decoding_first_frame = 1;
+ reset_frame_buffers(pbi);
+ }
+ cm->error_resilient_mode = 1;
+ } else {
+ cm->show_existing_frame = params->p.show_existing_frame;
+ pbi->reset_decoder_state = 0;
+ if (cm->show_existing_frame) {
+ int existing_frame_idx;
+ RefCntBuffer *frame_to_show;
+ if (pbi->sequence_header_changed) {
+ aom_internal_error(
+ &cm->error, AOM_CODEC_CORRUPT_FRAME,
+ "New sequence header starts with a show_existing_frame.");
+ }
+ // Show an existing frame directly.
+ existing_frame_idx = params->p.existing_frame_idx; //aom_rb_read_literal(rb, 3);
+ frame_to_show = cm->ref_frame_map[existing_frame_idx];
+ if (frame_to_show == NULL) {
+ aom_internal_error(&cm->error, AOM_CODEC_UNSUP_BITSTREAM,
+ "Buffer does not contain a decoded frame");
+ }
+ if (seq_params->decoder_model_info_present_flag &&
+ cm->timing_info.equal_picture_interval == 0) {
+ cm->frame_presentation_time = params->p.frame_presentation_time;
+ //read_temporal_point_info(cm);
+ }
+ if (seq_params->frame_id_numbers_present_flag) {
+ //int frame_id_length = seq_params->frame_id_length;
+ int display_frame_id = params->p.display_frame_id; //aom_rb_read_literal(rb, frame_id_length);
+ /* Compare display_frame_id with ref_frame_id and check valid for
+ * referencing */
+ if (display_frame_id != cm->ref_frame_id[existing_frame_idx] ||
+ cm->valid_for_referencing[existing_frame_idx] == 0)
+ aom_internal_error(&cm->error, AOM_CODEC_CORRUPT_FRAME,
+ "Reference buffer frame ID mismatch");
+ }
+ lock_buffer_pool(pool, flags);
+ assert(frame_to_show->ref_count > 0);
+ // cm->cur_frame should be the buffer referenced by the return value
+ // of the get_free_fb() call in av1_receive_compressed_data(), and
+ // generate_next_ref_frame_map() has not been called, so ref_count
+ // should still be 1.
+ assert(cm->cur_frame->ref_count == 1);
+ // assign_frame_buffer_p() decrements ref_count directly rather than
+ // call decrease_ref_count(). If cm->cur_frame->raw_frame_buffer has
+ // already been allocated, it will not be released by
+ // assign_frame_buffer_p()!
+ assert(!cm->cur_frame->raw_frame_buffer.data);
+ assign_frame_buffer_p(&cm->cur_frame, frame_to_show);
+ pbi->reset_decoder_state = frame_to_show->frame_type == KEY_FRAME;
+ unlock_buffer_pool(pool, flags);
+
+#ifdef ORI_CODE
+ cm->lf.filter_level[0] = 0;
+ cm->lf.filter_level[1] = 0;
+#endif
+ cm->show_frame = 1;
+
+ // Section 6.8.2: It is a requirement of bitstream conformance that when
+ // show_existing_frame is used to show a previous frame, that the value
+ // of showable_frame for the previous frame was equal to 1.
+ if (!frame_to_show->showable_frame) {
+ aom_internal_error(&cm->error, AOM_CODEC_UNSUP_BITSTREAM,
+ "Buffer does not contain a showable frame");
+ }
+ // Section 6.8.2: It is a requirement of bitstream conformance that when
+ // show_existing_frame is used to show a previous frame with
+ // RefFrameType[ frame_to_show_map_idx ] equal to KEY_FRAME, that the
+ // frame is output via the show_existing_frame mechanism at most once.
+ if (pbi->reset_decoder_state) frame_to_show->showable_frame = 0;
+
+#ifdef ORI_CODE
+ cm->film_grain_params = frame_to_show->film_grain_params;
+#endif
+ if (pbi->reset_decoder_state) {
+ show_existing_frame_reset(pbi, existing_frame_idx);
+ } else {
+ current_frame->refresh_frame_flags = 0;
+ }
+
+ return 0;
+ }
+
+ current_frame->frame_type = (FRAME_TYPE)params->p.frame_type; //aom_rb_read_literal(rb, 2);
+ if (pbi->sequence_header_changed) {
+ if (current_frame->frame_type == KEY_FRAME) {
+ // This is the start of a new coded video sequence.
+ pbi->sequence_header_changed = 0;
+ pbi->decoding_first_frame = 1;
+ reset_frame_buffers(pbi);
+ } else {
+ aom_internal_error(&cm->error, AOM_CODEC_CORRUPT_FRAME,
+ "Sequence header has changed without a keyframe.");
+ }
+ }
+ cm->show_frame = params->p.show_frame; //aom_rb_read_bit(rb);
+ if (seq_params->still_picture &&
+ (current_frame->frame_type != KEY_FRAME || !cm->show_frame)) {
+ aom_internal_error(&cm->error, AOM_CODEC_CORRUPT_FRAME,
+ "Still pictures must be coded as shown keyframes");
+ }
+ cm->showable_frame = current_frame->frame_type != KEY_FRAME;
+ if (cm->show_frame) {
+ if (seq_params->decoder_model_info_present_flag &&
+ cm->timing_info.equal_picture_interval == 0)
+ cm->frame_presentation_time = params->p.frame_presentation_time;
+ //read_temporal_point_info(cm);
+ } else {
+ // See if this frame can be used as show_existing_frame in future
+ cm->showable_frame = params->p.showable_frame;//aom_rb_read_bit(rb);
+ }
+ cm->cur_frame->showable_frame = cm->showable_frame;
+ cm->error_resilient_mode =
+ frame_is_sframe(cm) ||
+ (current_frame->frame_type == KEY_FRAME && cm->show_frame)
+ ? 1
+ : params->p.error_resilient_mode; //aom_rb_read_bit(rb);
+ }
+
+#ifdef ORI_CODE
+ cm->disable_cdf_update = aom_rb_read_bit(rb);
+ if (seq_params->force_screen_content_tools == 2) {
+ cm->allow_screen_content_tools = aom_rb_read_bit(rb);
+ } else {
+ cm->allow_screen_content_tools = seq_params->force_screen_content_tools;
+ }
+
+ if (cm->allow_screen_content_tools) {
+ if (seq_params->force_integer_mv == 2) {
+ cm->cur_frame_force_integer_mv = aom_rb_read_bit(rb);
+ } else {
+ cm->cur_frame_force_integer_mv = seq_params->force_integer_mv;
+ }
+ } else {
+ cm->cur_frame_force_integer_mv = 0;
+ }
+#endif
+
+ frame_size_override_flag = 0;
+ cm->allow_intrabc = 0;
+ cm->primary_ref_frame = PRIMARY_REF_NONE;
+
+ if (!seq_params->reduced_still_picture_hdr) {
+ if (seq_params->frame_id_numbers_present_flag) {
+ int frame_id_length = seq_params->frame_id_length;
+ int diff_len = seq_params->delta_frame_id_length;
+ int prev_frame_id = 0;
+ int have_prev_frame_id =
+ !pbi->decoding_first_frame &&
+ !(current_frame->frame_type == KEY_FRAME && cm->show_frame);
+ if (have_prev_frame_id) {
+ prev_frame_id = cm->current_frame_id;
+ }
+ cm->current_frame_id = params->p.current_frame_id; //aom_rb_read_literal(rb, frame_id_length);
+
+ if (have_prev_frame_id) {
+ int diff_frame_id;
+ if (cm->current_frame_id > prev_frame_id) {
+ diff_frame_id = cm->current_frame_id - prev_frame_id;
+ } else {
+ diff_frame_id =
+ (1 << frame_id_length) + cm->current_frame_id - prev_frame_id;
+ }
+ /* Check current_frame_id for conformance */
+ if (prev_frame_id == cm->current_frame_id ||
+ diff_frame_id >= (1 << (frame_id_length - 1))) {
+ aom_internal_error(&cm->error, AOM_CODEC_CORRUPT_FRAME,
+ "Invalid value of current_frame_id");
+ }
+ }
+ /* Check if some frames need to be marked as not valid for referencing */
+ for (i = 0; i < REF_FRAMES; i++) {
+ if (current_frame->frame_type == KEY_FRAME && cm->show_frame) {
+ cm->valid_for_referencing[i] = 0;
+ } else if (cm->current_frame_id - (1 << diff_len) > 0) {
+ if (cm->ref_frame_id[i] > cm->current_frame_id ||
+ cm->ref_frame_id[i] < cm->current_frame_id - (1 << diff_len))
+ cm->valid_for_referencing[i] = 0;
+ } else {
+ if (cm->ref_frame_id[i] > cm->current_frame_id &&
+ cm->ref_frame_id[i] < (1 << frame_id_length) +
+ cm->current_frame_id - (1 << diff_len))
+ cm->valid_for_referencing[i] = 0;
+ }
+ }
+ }
+
+ frame_size_override_flag = frame_is_sframe(cm) ? 1 : params->p.frame_size_override_flag; //aom_rb_read_bit(rb);
+
+ current_frame->order_hint = params->p.order_hint; /*aom_rb_read_literal(
+ rb, seq_params->order_hint_info.order_hint_bits_minus_1 + 1);*/
+ current_frame->frame_number = current_frame->order_hint;
+
+ if (!cm->error_resilient_mode && !frame_is_intra_only(cm)) {
+ cm->primary_ref_frame = params->p.primary_ref_frame;//aom_rb_read_literal(rb, PRIMARY_REF_BITS);
+ }
+ }
+
+ if (seq_params->decoder_model_info_present_flag) {
+ cm->buffer_removal_time_present = params->p.buffer_removal_time_present; //aom_rb_read_bit(rb);
+ if (cm->buffer_removal_time_present) {
+ int op_num;
+ for (op_num = 0;
+ op_num < seq_params->operating_points_cnt_minus_1 + 1; op_num++) {
+ if (cm->op_params[op_num].decoder_model_param_present_flag) {
+ if ((((seq_params->operating_point_idc[op_num] >>
+ cm->temporal_layer_id) &
+ 0x1) &&
+ ((seq_params->operating_point_idc[op_num] >>
+ (cm->spatial_layer_id + 8)) &
+ 0x1)) ||
+ seq_params->operating_point_idc[op_num] == 0) {
+ cm->op_frame_timing[op_num].buffer_removal_time =
+ params->p.op_frame_timing[op_num];
+ /*aom_rb_read_unsigned_literal(
+ rb, cm->buffer_model.buffer_removal_time_length);*/
+ } else {
+ cm->op_frame_timing[op_num].buffer_removal_time = 0;
+ }
+ } else {
+ cm->op_frame_timing[op_num].buffer_removal_time = 0;
+ }
+ }
+ }
+ }
+ if (current_frame->frame_type == KEY_FRAME) {
+ if (!cm->show_frame) { // unshown keyframe (forward keyframe)
+ current_frame->refresh_frame_flags = params->p.refresh_frame_flags; //aom_rb_read_literal(rb, REF_FRAMES);
+ } else { // shown keyframe
+ current_frame->refresh_frame_flags = (1 << REF_FRAMES) - 1;
+ }
+
+ for (i = 0; i < INTER_REFS_PER_FRAME; ++i) {
+ cm->remapped_ref_idx[i] = INVALID_IDX;
+ }
+ if (pbi->need_resync) {
+ reset_ref_frame_map(pbi);
+ pbi->need_resync = 0;
+ }
+ } else {
+ if (current_frame->frame_type == INTRA_ONLY_FRAME) {
+ current_frame->refresh_frame_flags = params->p.refresh_frame_flags; //aom_rb_read_literal(rb, REF_FRAMES);
+ if (current_frame->refresh_frame_flags == 0xFF) {
+ aom_internal_error(&cm->error, AOM_CODEC_UNSUP_BITSTREAM,
+ "Intra only frames cannot have refresh flags 0xFF");
+ }
+ if (pbi->need_resync) {
+ reset_ref_frame_map(pbi);
+ pbi->need_resync = 0;
+ }
+ } else if (pbi->need_resync != 1) { /* Skip if need resync */
+ current_frame->refresh_frame_flags =
+ frame_is_sframe(cm) ? 0xFF : params->p.refresh_frame_flags; //aom_rb_read_literal(rb, REF_FRAMES);
+ }
+ }
+
+ if (!frame_is_intra_only(cm) || current_frame->refresh_frame_flags != 0xFF) {
+ // Read all ref frame order hints if error_resilient_mode == 1
+ if (cm->error_resilient_mode &&
+ seq_params->order_hint_info.enable_order_hint) {
+ int ref_idx;
+ for (ref_idx = 0; ref_idx < REF_FRAMES; ref_idx++) {
+ // Read order hint from bit stream
+ unsigned int order_hint = params->p.ref_order_hint[ref_idx];/*aom_rb_read_literal(
+ rb, seq_params->order_hint_info.order_hint_bits_minus_1 + 1);*/
+ // Get buffer
+ RefCntBuffer *buf = cm->ref_frame_map[ref_idx];
+ int buf_idx;
+ if (buf == NULL || order_hint != buf->order_hint) {
+ if (buf != NULL) {
+ lock_buffer_pool(pool, flags);
+ decrease_ref_count(pbi, buf, pool);
+ unlock_buffer_pool(pool, flags);
+ }
+ // If no corresponding buffer exists, allocate a new buffer with all
+ // pixels set to neutral grey.
+ buf_idx = get_free_fb(cm);
+ if (buf_idx == INVALID_IDX) {
+ aom_internal_error(&cm->error, AOM_CODEC_MEM_ERROR,
+ "Unable to find free frame buffer");
+ }
+ buf = &frame_bufs[buf_idx];
+ lock_buffer_pool(pool, flags);
+ if (aom_realloc_frame_buffer(cm, &buf->buf, seq_params->max_frame_width,
+ seq_params->max_frame_height, buf->order_hint)) {
+ decrease_ref_count(pbi, buf, pool);
+ unlock_buffer_pool(pool, flags);
+ aom_internal_error(&cm->error, AOM_CODEC_MEM_ERROR,
+ "Failed to allocate frame buffer");
+ }
+ unlock_buffer_pool(pool, flags);
+#ifdef ORI_CODE
+ set_planes_to_neutral_grey(seq_params, &buf->buf, 0);
+#endif
+ cm->ref_frame_map[ref_idx] = buf;
+ buf->order_hint = order_hint;
+ }
+ }
+ }
+ }
+
+ if (current_frame->frame_type == KEY_FRAME) {
+ setup_frame_size(cm, frame_size_override_flag, params);
+#ifdef ORI_CODE
+ if (cm->allow_screen_content_tools && !av1_superres_scaled(cm))
+ cm->allow_intrabc = aom_rb_read_bit(rb);
+#endif
+ cm->allow_ref_frame_mvs = 0;
+ cm->prev_frame = NULL;
+ } else {
+ cm->allow_ref_frame_mvs = 0;
+
+ if (current_frame->frame_type == INTRA_ONLY_FRAME) {
+#ifdef ORI_CODE
+ cm->cur_frame->film_grain_params_present =
+ seq_params->film_grain_params_present;
+#endif
+ setup_frame_size(cm, frame_size_override_flag, params);
+#ifdef ORI_CODE
+ if (cm->allow_screen_content_tools && !av1_superres_scaled(cm))
+ cm->allow_intrabc = aom_rb_read_bit(rb);
+#endif
+ } else if (pbi->need_resync != 1) { /* Skip if need resync */
+ int frame_refs_short_signaling = 0;
+ // Frame refs short signaling is off when error resilient mode is on.
+ if (seq_params->order_hint_info.enable_order_hint)
+ frame_refs_short_signaling = params->p.frame_refs_short_signaling;//aom_rb_read_bit(rb);
+
+ if (frame_refs_short_signaling) {
+ // == LAST_FRAME ==
+ const int lst_ref = params->p.lst_ref; //aom_rb_read_literal(rb, REF_FRAMES_LOG2);
+ const RefCntBuffer *const lst_buf = cm->ref_frame_map[lst_ref];
+
+ // == GOLDEN_FRAME ==
+ const int gld_ref = params->p.gld_ref; //aom_rb_read_literal(rb, REF_FRAMES_LOG2);
+ const RefCntBuffer *const gld_buf = cm->ref_frame_map[gld_ref];
+
+ // Most of the time, streams start with a keyframe. In that case,
+ // ref_frame_map will have been filled in at that point and will not
+ // contain any NULLs. However, streams are explicitly allowed to start
+ // with an intra-only frame, so long as they don't then signal a
+ // reference to a slot that hasn't been set yet. That's what we are
+ // checking here.
+ if (lst_buf == NULL)
+ aom_internal_error(&cm->error, AOM_CODEC_CORRUPT_FRAME,
+ "Inter frame requests nonexistent reference");
+ if (gld_buf == NULL)
+ aom_internal_error(&cm->error, AOM_CODEC_CORRUPT_FRAME,
+ "Inter frame requests nonexistent reference");
+
+ av1_set_frame_refs(cm, cm->remapped_ref_idx, lst_ref, gld_ref);
+ }
+
+ for (i = 0; i < INTER_REFS_PER_FRAME; ++i) {
+ int ref = 0;
+ if (!frame_refs_short_signaling) {
+ ref = params->p.remapped_ref_idx[i];//aom_rb_read_literal(rb, REF_FRAMES_LOG2);
+
+ // Most of the time, streams start with a keyframe. In that case,
+ // ref_frame_map will have been filled in at that point and will not
+ // contain any NULLs. However, streams are explicitly allowed to start
+ // with an intra-only frame, so long as they don't then signal a
+ // reference to a slot that hasn't been set yet. That's what we are
+ // checking here.
+ if (cm->ref_frame_map[ref] == NULL)
+ aom_internal_error(&cm->error, AOM_CODEC_CORRUPT_FRAME,
+ "Inter frame requests nonexistent reference");
+ cm->remapped_ref_idx[i] = ref;
+ } else {
+ ref = cm->remapped_ref_idx[i];
+ }
+
+ cm->ref_frame_sign_bias[LAST_FRAME + i] = 0;
+
+ if (seq_params->frame_id_numbers_present_flag) {
+ int frame_id_length = seq_params->frame_id_length;
+ //int diff_len = seq_params->delta_frame_id_length;
+ int delta_frame_id_minus_1 = params->p.delta_frame_id_minus_1[i];//aom_rb_read_literal(rb, diff_len);
+ int ref_frame_id =
+ ((cm->current_frame_id - (delta_frame_id_minus_1 + 1) +
+ (1 << frame_id_length)) %
+ (1 << frame_id_length));
+ // Compare values derived from delta_frame_id_minus_1 and
+ // refresh_frame_flags. Also, check valid for referencing
+ if (ref_frame_id != cm->ref_frame_id[ref] ||
+ cm->valid_for_referencing[ref] == 0)
+ aom_internal_error(&cm->error, AOM_CODEC_CORRUPT_FRAME,
+ "Reference buffer frame ID mismatch");
+ }
+ }
+
+ if (!cm->error_resilient_mode && frame_size_override_flag) {
+ setup_frame_size_with_refs(cm, params);
+ } else {
+ setup_frame_size(cm, frame_size_override_flag, params);
+ }
+#ifdef ORI_CODE
+ if (cm->cur_frame_force_integer_mv) {
+ cm->allow_high_precision_mv = 0;
+ } else {
+ cm->allow_high_precision_mv = aom_rb_read_bit(rb);
+ }
+ cm->interp_filter = read_frame_interp_filter(rb);
+ cm->switchable_motion_mode = aom_rb_read_bit(rb);
+#endif
+ }
+
+ cm->prev_frame = get_primary_ref_frame_buf(cm);
+ if (cm->primary_ref_frame != PRIMARY_REF_NONE &&
+ get_primary_ref_frame_buf(cm) == NULL) {
+ aom_internal_error(&cm->error, AOM_CODEC_CORRUPT_FRAME,
+ "Reference frame containing this frame's initial "
+ "frame context is unavailable.");
+ }
+#if 0
+ av1_print2(VP9_DEBUG_BUFMGR_DETAIL, "%d,%d,%d,%d\n",cm->error_resilient_mode,
+ cm->seq_params.order_hint_info.enable_ref_frame_mvs,
+ cm->seq_params.order_hint_info.enable_order_hint,frame_is_intra_only(cm));
+
+ printf("frame_might_allow_ref_frame_mvs()=>%d, current_frame->frame_type=%d, pbi->need_resync=%d, params->p.allow_ref_frame_mvs=%d\n",
+ frame_might_allow_ref_frame_mvs(cm), current_frame->frame_type, pbi->need_resync,
+ params->p.allow_ref_frame_mvs);
+#endif
+ if (!(current_frame->frame_type == INTRA_ONLY_FRAME) &&
+ pbi->need_resync != 1) {
+ if (frame_might_allow_ref_frame_mvs(cm))
+ cm->allow_ref_frame_mvs = params->p.allow_ref_frame_mvs; //aom_rb_read_bit(-1, "<allow_ref_frame_mvs>", rb);
+ else
+ cm->allow_ref_frame_mvs = 0;
+
+#ifdef SUPPORT_SCALE_FACTOR
+ for (i = LAST_FRAME; i <= ALTREF_FRAME; ++i) {
+ const RefCntBuffer *const ref_buf = get_ref_frame_buf(cm, i);
+ struct scale_factors *const ref_scale_factors =
+ get_ref_scale_factors(cm, i);
+ if (ref_buf != NULL) {
+#ifdef AML
+ av1_setup_scale_factors_for_frame(
+ ref_scale_factors, ref_buf->buf.y_crop_width,
+ ref_buf->buf.y_crop_height, cm->dec_width, cm->height);
+#else
+ av1_setup_scale_factors_for_frame(
+ ref_scale_factors, ref_buf->buf.y_crop_width,
+ ref_buf->buf.y_crop_height, cm->width, cm->height);
+#endif
+ }
+ if (ref_scale_factors) {
+ if ((!av1_is_valid_scale(ref_scale_factors)))
+ aom_internal_error(&cm->error, AOM_CODEC_UNSUP_BITSTREAM,
+ "Reference frame has invalid dimensions");
+ }
+ }
+#endif
+ }
+ }
+
+ av1_setup_frame_buf_refs(cm);
+
+ av1_setup_frame_sign_bias(cm);
+
+ cm->cur_frame->frame_type = current_frame->frame_type;
+
+ if (seq_params->frame_id_numbers_present_flag) {
+ update_ref_frame_id(cm, cm->current_frame_id);
+ }
+#ifdef ORI_CODE
+ const int might_bwd_adapt =
+ !(seq_params->reduced_still_picture_hdr) && !(cm->disable_cdf_update);
+ if (might_bwd_adapt) {
+ cm->refresh_frame_context = aom_rb_read_bit(rb)
+ ? REFRESH_FRAME_CONTEXT_DISABLED
+ : REFRESH_FRAME_CONTEXT_BACKWARD;
+ } else {
+ cm->refresh_frame_context = REFRESH_FRAME_CONTEXT_DISABLED;
+ }
+#endif
+
+ cm->cur_frame->buf.bit_depth = seq_params->bit_depth;
+ cm->cur_frame->buf.color_primaries = seq_params->color_primaries;
+ cm->cur_frame->buf.transfer_characteristics =
+ seq_params->transfer_characteristics;
+ cm->cur_frame->buf.matrix_coefficients = seq_params->matrix_coefficients;
+ cm->cur_frame->buf.monochrome = seq_params->monochrome;
+ cm->cur_frame->buf.chroma_sample_position =
+ seq_params->chroma_sample_position;
+ cm->cur_frame->buf.color_range = seq_params->color_range;
+ cm->cur_frame->buf.render_width = cm->render_width;
+ cm->cur_frame->buf.render_height = cm->render_height;
+
+ if (pbi->need_resync) {
+ aom_internal_error(&cm->error, AOM_CODEC_CORRUPT_FRAME,
+ "Keyframe / intra-only frame required to reset decoder"
+ " state");
+ }
+
+ generate_next_ref_frame_map(pbi);
+
+#ifdef ORI_CODE
+ if (cm->allow_intrabc) {
+ // Set parameters corresponding to no filtering.
+ struct loopfilter *lf = &cm->lf;
+ lf->filter_level[0] = 0;
+ lf->filter_level[1] = 0;
+ cm->cdef_info.cdef_bits = 0;
+ cm->cdef_info.cdef_strengths[0] = 0;
+ cm->cdef_info.nb_cdef_strengths = 1;
+ cm->cdef_info.cdef_uv_strengths[0] = 0;
+ cm->rst_info[0].frame_restoration_type = RESTORE_NONE;
+ cm->rst_info[1].frame_restoration_type = RESTORE_NONE;
+ cm->rst_info[2].frame_restoration_type = RESTORE_NONE;
+ }
+
+ read_tile_info(pbi, rb);
+ if (!av1_is_min_tile_width_satisfied(cm)) {
+ aom_internal_error(&cm->error, AOM_CODEC_CORRUPT_FRAME,
+ "Minimum tile width requirement not satisfied");
+ }
+
+ setup_quantization(cm, rb);
+ xd->bd = (int)seq_params->bit_depth;
+
+ if (cm->num_allocated_above_context_planes < av1_num_planes(cm) ||
+ cm->num_allocated_above_context_mi_col < cm->mi_cols ||
+ cm->num_allocated_above_contexts < cm->tile_rows) {
+ av1_free_above_context_buffers(cm, cm->num_allocated_above_contexts);
+ if (av1_alloc_above_context_buffers(cm, cm->tile_rows))
+ aom_internal_error(&cm->error, AOM_CODEC_MEM_ERROR,
+ "Failed to allocate context buffers");
+ }
+
+ if (cm->primary_ref_frame == PRIMARY_REF_NONE) {
+ av1_setup_past_independence(cm);
+ }
+
+ setup_segmentation(cm, params);
+
+ cm->delta_q_info.delta_q_res = 1;
+ cm->delta_q_info.delta_lf_res = 1;
+ cm->delta_q_info.delta_lf_present_flag = 0;
+ cm->delta_q_info.delta_lf_multi = 0;
+ cm->delta_q_info.delta_q_present_flag =
+ cm->base_qindex > 0 ? aom_rb_read_bit(-1, defmark, rb) : 0;
+ if (cm->delta_q_info.delta_q_present_flag) {
+ xd->current_qindex = cm->base_qindex;
+ cm->delta_q_info.delta_q_res = 1 << aom_rb_read_literal(-1, defmark, rb, 2);
+ if (!cm->allow_intrabc)
+ cm->delta_q_info.delta_lf_present_flag = aom_rb_read_bit(-1, defmark, rb);
+ if (cm->delta_q_info.delta_lf_present_flag) {
+ cm->delta_q_info.delta_lf_res = 1 << aom_rb_read_literal(-1, defmark, rb, 2);
+ cm->delta_q_info.delta_lf_multi = aom_rb_read_bit(-1, defmark, rb);
+ av1_reset_loop_filter_delta(xd, av1_num_planes(cm));
+ }
+ }
+
+ xd->cur_frame_force_integer_mv = cm->cur_frame_force_integer_mv;
+
+ for (int i = 0; i < MAX_SEGMENTS; ++i) {
+ const int qindex = av1_get_qindex(&cm->seg, i, cm->base_qindex);
+ xd->lossless[i] = qindex == 0 && cm->y_dc_delta_q == 0 &&
+ cm->u_dc_delta_q == 0 && cm->u_ac_delta_q == 0 &&
+ cm->v_dc_delta_q == 0 && cm->v_ac_delta_q == 0;
+ xd->qindex[i] = qindex;
+ }
+ cm->coded_lossless = is_coded_lossless(cm, xd);
+ cm->all_lossless = cm->coded_lossless && !av1_superres_scaled(cm);
+ setup_segmentation_dequant(cm, xd);
+ if (cm->coded_lossless) {
+ cm->lf.filter_level[0] = 0;
+ cm->lf.filter_level[1] = 0;
+ }
+ if (cm->coded_lossless || !seq_params->enable_cdef) {
+ cm->cdef_info.cdef_bits = 0;
+ cm->cdef_info.cdef_strengths[0] = 0;
+ cm->cdef_info.cdef_uv_strengths[0] = 0;
+ }
+ if (cm->all_lossless || !seq_params->enable_restoration) {
+ cm->rst_info[0].frame_restoration_type = RESTORE_NONE;
+ cm->rst_info[1].frame_restoration_type = RESTORE_NONE;
+ cm->rst_info[2].frame_restoration_type = RESTORE_NONE;
+ }
+ setup_loopfilter(cm, rb);
+
+ if (!cm->coded_lossless && seq_params->enable_cdef) {
+ setup_cdef(cm, rb);
+ }
+ if (!cm->all_lossless && seq_params->enable_restoration) {
+ decode_restoration_mode(cm, rb);
+ }
+
+ cm->tx_mode = read_tx_mode(cm, rb);
+#endif
+
+ current_frame->reference_mode = read_frame_reference_mode(cm, params);
+
+#ifdef ORI_CODE
+ if (current_frame->reference_mode != SINGLE_REFERENCE)
+ setup_compound_reference_mode(cm);
+
+
+#endif
+
+ av1_setup_skip_mode_allowed(cm);
+
+ /*
+ the point that ucode send send_bufmgr_info
+ and wait bufmgr code to return is_skip_mode_allowed
+ */
+
+ /*
+ read_uncompressed_header() end
+ */
+
+ av1_setup_motion_field(cm);
+#ifdef AML
+ cm->cur_frame->mi_cols = cm->mi_cols;
+ cm->cur_frame->mi_rows = cm->mi_rows;
+ cm->cur_frame->dec_width = cm->dec_width;
+
+ /*
+ superres_post_decode(AV1Decoder *pbi) =>
+ av1_superres_upscale(cm, pool); =>
+ aom_realloc_frame_buffer(
+ frame_to_show, cm->superres_upscaled_width,
+ cm->superres_upscaled_height, seq_params->subsampling_x,
+ seq_params->subsampling_y, seq_params->use_highbitdepth,
+ AOM_BORDER_IN_PIXELS, cm->byte_alignment, fb, cb, cb_priv)
+ */
+ aom_realloc_frame_buffer(cm, &cm->cur_frame->buf,
+ cm->superres_upscaled_width, cm->superres_upscaled_height,
+ cm->cur_frame->order_hint);
+#endif
+ return 0;
+}
+
+static int are_seq_headers_consistent(const SequenceHeader *seq_params_old,
+ const SequenceHeader *seq_params_new) {
+ return !memcmp(seq_params_old, seq_params_new, sizeof(SequenceHeader));
+}
+
+aom_codec_err_t aom_get_num_layers_from_operating_point_idc(
+ int operating_point_idc, unsigned int *number_spatial_layers,
+ unsigned int *number_temporal_layers) {
+ // derive number of spatial/temporal layers from operating_point_idc
+
+ if (!number_spatial_layers || !number_temporal_layers)
+ return AOM_CODEC_INVALID_PARAM;
+
+ if (operating_point_idc == 0) {
+ *number_temporal_layers = 1;
+ *number_spatial_layers = 1;
+ } else {
+ int j;
+ *number_spatial_layers = 0;
+ *number_temporal_layers = 0;
+ for (j = 0; j < MAX_NUM_SPATIAL_LAYERS; j++) {
+ *number_spatial_layers +=
+ (operating_point_idc >> (j + MAX_NUM_TEMPORAL_LAYERS)) & 0x1;
+ }
+ for (j = 0; j < MAX_NUM_TEMPORAL_LAYERS; j++) {
+ *number_temporal_layers += (operating_point_idc >> j) & 0x1;
+ }
+ }
+
+ return AOM_CODEC_OK;
+}
+
+void av1_read_sequence_header(AV1_COMMON *cm, union param_u *params,
+ SequenceHeader *seq_params) {
+#ifdef ORI_CODE
+ const int num_bits_width = aom_rb_read_literal(-1, "<num_bits_width>", rb, 4) + 1;
+ const int num_bits_height = aom_rb_read_literal(-1, "<num_bits_height>", rb, 4) + 1;
+ const int max_frame_width = aom_rb_read_literal(-1, "<max_frame_width>", rb, num_bits_width) + 1;
+ const int max_frame_height = aom_rb_read_literal(-1, "<max_frame_height>", rb, num_bits_height) + 1;
+
+ seq_params->num_bits_width = num_bits_width;
+ seq_params->num_bits_height = num_bits_height;
+#endif
+ seq_params->max_frame_width = params->p.max_frame_width; //max_frame_width;
+ seq_params->max_frame_height = params->p.max_frame_height; //max_frame_height;
+
+ if (seq_params->reduced_still_picture_hdr) {
+ seq_params->frame_id_numbers_present_flag = 0;
+ } else {
+ seq_params->frame_id_numbers_present_flag = params->p.frame_id_numbers_present_flag; //aom_rb_read_bit(-1, "<frame_id_numbers_present_flag>", rb);
+ }
+ if (seq_params->frame_id_numbers_present_flag) {
+ // We must always have delta_frame_id_length < frame_id_length,
+ // in order for a frame to be referenced with a unique delta.
+ // Avoid wasting bits by using a coding that enforces this restriction.
+#ifdef ORI_CODE
+ seq_params->delta_frame_id_length = aom_rb_read_literal(-1, "<delta_frame_id_length>", rb, 4) + 2;
+ seq_params->frame_id_length = params->p.frame_id_length + aom_rb_read_literal(-1, "<frame_id_length>", rb, 3) + seq_params->delta_frame_id_length + 1;
+#else
+ seq_params->delta_frame_id_length = params->p.delta_frame_id_length;
+ seq_params->frame_id_length = params->p.frame_id_length + seq_params->delta_frame_id_length + 1;
+#endif
+ if (seq_params->frame_id_length > 16)
+ aom_internal_error(&cm->error, AOM_CODEC_CORRUPT_FRAME,
+ "Invalid frame_id_length");
+ }
+#ifdef ORI_CODE
+ setup_sb_size(seq_params, rb);
+ seq_params->enable_filter_intra = aom_rb_read_bit(-1, "<enable_filter_intra>", rb);
+ seq_params->enable_intra_edge_filter = aom_rb_read_bit(-1, "<enable_intra_edge_filter>", rb);
+#endif
+
+ if (seq_params->reduced_still_picture_hdr) {
+ seq_params->enable_interintra_compound = 0;
+ seq_params->enable_masked_compound = 0;
+ seq_params->enable_warped_motion = 0;
+ seq_params->enable_dual_filter = 0;
+ seq_params->order_hint_info.enable_order_hint = 0;
+ seq_params->order_hint_info.enable_dist_wtd_comp = 0;
+ seq_params->order_hint_info.enable_ref_frame_mvs = 0;
+ seq_params->force_screen_content_tools = 2; // SELECT_SCREEN_CONTENT_TOOLS
+ seq_params->force_integer_mv = 2; // SELECT_INTEGER_MV
+ seq_params->order_hint_info.order_hint_bits_minus_1 = -1;
+ } else {
+#ifdef ORI_CODE
+ seq_params->enable_interintra_compound = aom_rb_read_bit(-1, "<enable_interintra_compound>", rb);
+ seq_params->enable_masked_compound = aom_rb_read_bit(-1, "<enable_masked_compound>", rb);
+ seq_params->enable_warped_motion = aom_rb_read_bit(-1, "<enable_warped_motion>", rb);
+ seq_params->enable_dual_filter = aom_rb_read_bit(-1, "<enable_dual_filter>", rb);
+#endif
+ seq_params->order_hint_info.enable_order_hint = params->p.enable_order_hint; //aom_rb_read_bit(-1, "<order_hint_info.enable_order_hint>", rb);
+ seq_params->order_hint_info.enable_dist_wtd_comp =
+ seq_params->order_hint_info.enable_order_hint ? params->p.enable_dist_wtd_comp : 0; //aom_rb_read_bit(-1, "<order_hint_info.enable_dist_wtd_comp>", rb) : 0;
+ seq_params->order_hint_info.enable_ref_frame_mvs =
+ seq_params->order_hint_info.enable_order_hint ? params->p.enable_ref_frame_mvs : 0; //aom_rb_read_bit(-1, "<order_hint_info.enable_ref_frame_mvs>", rb) : 0;
+
+#ifdef ORI_CODE
+ if (aom_rb_read_bit(-1, defmark, rb)) {
+ seq_params->force_screen_content_tools =
+ 2; // SELECT_SCREEN_CONTENT_TOOLS
+ } else {
+ seq_params->force_screen_content_tools = aom_rb_read_bit(-1, defmark, rb);
+ }
+
+ if (seq_params->force_screen_content_tools > 0) {
+ if (aom_rb_read_bit(-1, defmark, rb)) {
+ seq_params->force_integer_mv = 2; // SELECT_INTEGER_MV
+ } else {
+ seq_params->force_integer_mv = aom_rb_read_bit(-1, defmark, rb);
+ }
+ } else {
+ seq_params->force_integer_mv = 2; // SELECT_INTEGER_MV
+ }
+#endif
+ seq_params->order_hint_info.order_hint_bits_minus_1 =
+ seq_params->order_hint_info.enable_order_hint
+ ? params->p.order_hint_bits_minus_1 /*aom_rb_read_literal(-1, "<order_hint_info.order_hint_bits_minus_1>", rb, 3)*/
+ : -1;
+ }
+ seq_params->enable_superres = params->p.enable_superres; //aom_rb_read_bit(-1, defmark, rb);
+
+#ifdef ORI_CODE
+ seq_params->enable_cdef = aom_rb_read_bit(-1, defmark, rb);
+ seq_params->enable_restoration = aom_rb_read_bit(-1, defmark, rb);
+#endif
+}
+
+#ifdef ORI_CODE
+void av1_read_op_parameters_info(AV1_COMMON *const cm,
+ struct aom_read_bit_buffer *rb, int op_num) {
+ // The cm->op_params array has MAX_NUM_OPERATING_POINTS + 1 elements.
+ if (op_num > MAX_NUM_OPERATING_POINTS) {
+ aom_internal_error(&cm->error, AOM_CODEC_UNSUP_BITSTREAM,
+ "AV1 does not support %d decoder model operating points",
+ op_num + 1);
+ }
+
+ cm->op_params[op_num].decoder_buffer_delay = aom_rb_read_unsigned_literal(-1, defmark,
+ rb, cm->buffer_model.encoder_decoder_buffer_delay_length);
+
+ cm->op_params[op_num].encoder_buffer_delay = aom_rb_read_unsigned_literal(-1, defmark,
+ rb, cm->buffer_model.encoder_decoder_buffer_delay_length);
+
+ cm->op_params[op_num].low_delay_mode_flag = aom_rb_read_bit(-1, defmark, rb);
+}
+#endif
+
+static int is_valid_seq_level_idx(AV1_LEVEL seq_level_idx) {
+ return seq_level_idx < SEQ_LEVELS || seq_level_idx == SEQ_LEVEL_MAX;
+}
+
+static uint32_t read_sequence_header_obu(AV1Decoder *pbi,
+ union param_u *params) {
+ AV1_COMMON *const cm = &pbi->common;
+ int i;
+ int operating_point;
+ // Verify rb has been configured to report errors.
+ //assert(rb->error_handler);
+
+ // Use a local variable to store the information as we decode. At the end,
+ // if no errors have occurred, cm->seq_params is updated.
+ SequenceHeader sh = cm->seq_params;
+ SequenceHeader *const seq_params = &sh;
+
+ seq_params->profile = params->p.profile; //av1_read_profile(rb);
+ if (seq_params->profile > CONFIG_MAX_DECODE_PROFILE) {
+ cm->error.error_code = AOM_CODEC_UNSUP_BITSTREAM;
+ return 0;
+ }
+
+ // Still picture or not
+ seq_params->still_picture = params->p.still_picture; //aom_rb_read_bit(-1, "<still_picture>", rb);
+ seq_params->reduced_still_picture_hdr = params->p.reduced_still_picture_hdr; //aom_rb_read_bit(-1, "<reduced_still_picture_hdr>", rb);
+ // Video must have reduced_still_picture_hdr = 0
+ if (!seq_params->still_picture && seq_params->reduced_still_picture_hdr) {
+ cm->error.error_code = AOM_CODEC_UNSUP_BITSTREAM;
+ return 0;
+ }
+
+ if (seq_params->reduced_still_picture_hdr) {
+ cm->timing_info_present = 0;
+ seq_params->decoder_model_info_present_flag = 0;
+ seq_params->display_model_info_present_flag = 0;
+ seq_params->operating_points_cnt_minus_1 = 0;
+ seq_params->operating_point_idc[0] = 0;
+ //if (!read_bitstream_level(0, "<seq_level_idx>", &seq_params->seq_level_idx[0], rb)) {
+ if (!is_valid_seq_level_idx(params->p.seq_level_idx[0])) {
+ cm->error.error_code = AOM_CODEC_UNSUP_BITSTREAM;
+ return 0;
+ }
+ seq_params->tier[0] = 0;
+ cm->op_params[0].decoder_model_param_present_flag = 0;
+ cm->op_params[0].display_model_param_present_flag = 0;
+ } else {
+ cm->timing_info_present = params->p.timing_info_present; //aom_rb_read_bit(-1, "<timing_info_present>", rb); // timing_info_present_flag
+ if (cm->timing_info_present) {
+#ifdef ORI_CODE
+ av1_read_timing_info_header(cm, rb);
+#endif
+ seq_params->decoder_model_info_present_flag = params->p.decoder_model_info_present_flag; //aom_rb_read_bit(-1, "<decoder_model_info_present_flag>", rb);
+#ifdef ORI_CODE
+ if (seq_params->decoder_model_info_present_flag)
+ av1_read_decoder_model_info(cm, rb);
+#endif
+ } else {
+ seq_params->decoder_model_info_present_flag = 0;
+ }
+#ifdef ORI_CODE
+ seq_params->display_model_info_present_flag = aom_rb_read_bit(-1, "<display_model_info_present_flag>", rb);
+#endif
+ seq_params->operating_points_cnt_minus_1 = params->p.operating_points_cnt_minus_1;
+ //aom_rb_read_literal(-1, "<operating_points_cnt_minus_1>", rb, OP_POINTS_CNT_MINUS_1_BITS);
+ for (i = 0; i < seq_params->operating_points_cnt_minus_1 + 1; i++) {
+ seq_params->operating_point_idc[i] = params->p.operating_point_idc[i];
+ //aom_rb_read_literal(i, "<operating_point_idc>", rb, OP_POINTS_IDC_BITS);
+ //if (!read_bitstream_level(i, "<seq_level_idx>", &seq_params->seq_level_idx[i], rb)) {
+ if (!is_valid_seq_level_idx(params->p.seq_level_idx[i])) {
+ cm->error.error_code = AOM_CODEC_UNSUP_BITSTREAM;
+ return 0;
+ }
+ // This is the seq_level_idx[i] > 7 check in the spec. seq_level_idx 7
+ // is equivalent to level 3.3.
+#ifdef ORI_CODE
+ if (seq_params->seq_level_idx[i] >= SEQ_LEVEL_4_0)
+ seq_params->tier[i] = aom_rb_read_bit(i, "<tier>", rb);
+ else
+ seq_params->tier[i] = 0;
+#endif
+ if (seq_params->decoder_model_info_present_flag) {
+ cm->op_params[i].decoder_model_param_present_flag = params->p.decoder_model_param_present_flag[i]; //aom_rb_read_bit(-1, defmark, rb);
+#ifdef ORI_CODE
+ if (cm->op_params[i].decoder_model_param_present_flag)
+ av1_read_op_parameters_info(cm, rb, i);
+#endif
+ } else {
+ cm->op_params[i].decoder_model_param_present_flag = 0;
+ }
+#ifdef ORI_CODE
+ if (cm->timing_info_present &&
+ (cm->timing_info.equal_picture_interval ||
+ cm->op_params[i].decoder_model_param_present_flag)) {
+ cm->op_params[i].bitrate = av1_max_level_bitrate(
+ seq_params->profile, seq_params->seq_level_idx[i],
+ seq_params->tier[i]);
+ // Level with seq_level_idx = 31 returns a high "dummy" bitrate to pass
+ // the check
+ if (cm->op_params[i].bitrate == 0)
+ aom_internal_error(&cm->error, AOM_CODEC_UNSUP_BITSTREAM,
+ "AV1 does not support this combination of "
+ "profile, level, and tier.");
+ // Buffer size in bits/s is bitrate in bits/s * 1 s
+ cm->op_params[i].buffer_size = cm->op_params[i].bitrate;
+ }
+#endif
+ if (cm->timing_info_present && cm->timing_info.equal_picture_interval &&
+ !cm->op_params[i].decoder_model_param_present_flag) {
+ // When the decoder_model_parameters are not sent for this op, set
+ // the default ones that can be used with the resource availability mode
+ cm->op_params[i].decoder_buffer_delay = 70000;
+ cm->op_params[i].encoder_buffer_delay = 20000;
+ cm->op_params[i].low_delay_mode_flag = 0;
+ }
+
+#ifdef ORI_CODE
+ if (seq_params->display_model_info_present_flag) {
+ cm->op_params[i].display_model_param_present_flag = aom_rb_read_bit(-1, defmark, rb);
+ if (cm->op_params[i].display_model_param_present_flag) {
+ cm->op_params[i].initial_display_delay =
+ aom_rb_read_literal(-1, defmark, rb, 4) + 1;
+ if (cm->op_params[i].initial_display_delay > 10)
+ aom_internal_error(
+ &cm->error, AOM_CODEC_UNSUP_BITSTREAM,
+ "AV1 does not support more than 10 decoded frames delay");
+ } else {
+ cm->op_params[i].initial_display_delay = 10;
+ }
+ } else {
+ cm->op_params[i].display_model_param_present_flag = 0;
+ cm->op_params[i].initial_display_delay = 10;
+ }
+#endif
+ }
+ }
+ // This decoder supports all levels. Choose operating point provided by
+ // external means
+ operating_point = pbi->operating_point;
+ if (operating_point < 0 ||
+ operating_point > seq_params->operating_points_cnt_minus_1)
+ operating_point = 0;
+ pbi->current_operating_point =
+ seq_params->operating_point_idc[operating_point];
+ if (aom_get_num_layers_from_operating_point_idc(
+ pbi->current_operating_point, &cm->number_spatial_layers,
+ &cm->number_temporal_layers) != AOM_CODEC_OK) {
+ cm->error.error_code = AOM_CODEC_ERROR;
+ return 0;
+ }
+
+ av1_read_sequence_header(cm, params, seq_params);
+#ifdef ORI_CODE
+ av1_read_color_config(rb, pbi->allow_lowbitdepth, seq_params, &cm->error);
+ if (!(seq_params->subsampling_x == 0 && seq_params->subsampling_y == 0) &&
+ !(seq_params->subsampling_x == 1 && seq_params->subsampling_y == 1) &&
+ !(seq_params->subsampling_x == 1 && seq_params->subsampling_y == 0)) {
+ aom_internal_error(&cm->error, AOM_CODEC_UNSUP_BITSTREAM,
+ "Only 4:4:4, 4:2:2 and 4:2:0 are currently supported, "
+ "%d %d subsampling is not supported.\n",
+ seq_params->subsampling_x, seq_params->subsampling_y);
+ }
+ seq_params->film_grain_params_present = aom_rb_read_bit(-1, "<film_grain_params_present>", rb);
+
+ if (av1_check_trailing_bits(pbi, rb) != 0) {
+ // cm->error.error_code is already set.
+ return 0;
+ }
+#endif
+
+ // If a sequence header has been decoded before, we check if the new
+ // one is consistent with the old one.
+ if (pbi->sequence_header_ready) {
+ if (!are_seq_headers_consistent(&cm->seq_params, seq_params))
+ pbi->sequence_header_changed = 1;
+ }
+
+ cm->seq_params = *seq_params;
+ pbi->sequence_header_ready = 1;
+ return 0;
+
+}
+
+int aom_decode_frame_from_obus(AV1Decoder *pbi, union param_u *params, int obu_type)
+{
+ AV1_COMMON *const cm = &pbi->common;
+ ObuHeader obu_header;
+ int frame_decoding_finished = 0;
+ uint32_t frame_header_size = 0;
+
+ //struct aom_read_bit_buffer rb;
+ size_t payload_size = 0;
+ size_t decoded_payload_size = 0;
+ size_t obu_payload_offset = 0;
+ //size_t bytes_read = 0;
+
+ memset(&obu_header, 0, sizeof(obu_header));
+#ifdef ORI_CODE
+ pbi->seen_frame_header = 0;
+#else
+ /* set in the test.c*/
+#endif
+
+ obu_header.type = obu_type;
+ pbi->cur_obu_type = obu_header.type;
+ if (av1_is_debug(AOM_DEBUG_PRINT_LIST_INFO))
+ dump_params(pbi, params);
+ switch (obu_header.type) {
+ case OBU_SEQUENCE_HEADER:
+ decoded_payload_size = read_sequence_header_obu(pbi, params);
+ if (cm->error.error_code != AOM_CODEC_OK) return -1;
+ break;
+
+ case OBU_FRAME_HEADER:
+ case OBU_REDUNDANT_FRAME_HEADER:
+ case OBU_FRAME:
+ if (obu_header.type == OBU_REDUNDANT_FRAME_HEADER) {
+ if (!pbi->seen_frame_header) {
+ cm->error.error_code = AOM_CODEC_CORRUPT_FRAME;
+ return -1;
+ }
+ } else {
+ // OBU_FRAME_HEADER or OBU_FRAME.
+ if (pbi->seen_frame_header) {
+ cm->error.error_code = AOM_CODEC_CORRUPT_FRAME;
+ return -1;
+ }
+ }
+ // Only decode first frame header received
+ if (!pbi->seen_frame_header ||
+ (cm->large_scale_tile && !pbi->camera_frame_header_ready)) {
+ frame_header_size = av1_decode_frame_headers_and_setup(
+ pbi, /*&rb, data, p_data_end,*/obu_header.type != OBU_FRAME, params);
+ pbi->seen_frame_header = 1;
+ if (!pbi->ext_tile_debug && cm->large_scale_tile)
+ pbi->camera_frame_header_ready = 1;
+ } else {
+ // TODO(wtc): Verify that the frame_header_obu is identical to the
+ // original frame_header_obu. For now just skip frame_header_size
+ // bytes in the bit buffer.
+ if (frame_header_size > payload_size) {
+ cm->error.error_code = AOM_CODEC_CORRUPT_FRAME;
+ return -1;
+ }
+ assert(rb.bit_offset == 0);
+#ifdef ORI_CODE
+ rb.bit_offset = 8 * frame_header_size;
+#endif
+ }
+
+ decoded_payload_size = frame_header_size;
+ pbi->frame_header_size = frame_header_size;
+
+ if (cm->show_existing_frame) {
+ if (obu_header.type == OBU_FRAME) {
+ cm->error.error_code = AOM_CODEC_UNSUP_BITSTREAM;
+ return -1;
+ }
+ frame_decoding_finished = 1;
+ pbi->seen_frame_header = 0;
+ break;
+ }
+
+ // In large scale tile coding, decode the common camera frame header
+ // before any tile list OBU.
+ if (!pbi->ext_tile_debug && pbi->camera_frame_header_ready) {
+ frame_decoding_finished = 1;
+ // Skip the rest of the frame data.
+ decoded_payload_size = payload_size;
+ // Update data_end.
+#ifdef ORI_CODE
+ *p_data_end = data_end;
+#endif
+ break;
+ }
+#if 0 //def AML
+ frame_decoding_finished = 1;
+#endif
+ if (obu_header.type != OBU_FRAME) break;
+ obu_payload_offset = frame_header_size;
+ // Byte align the reader before reading the tile group.
+ // byte_alignment() has set cm->error.error_code if it returns -1.
+#ifdef ORI_CODE
+ if (byte_alignment(cm, &rb)) return -1;
+ AOM_FALLTHROUGH_INTENDED; // fall through to read tile group.
+#endif
+ default:
+ break;
+ }
+ return frame_decoding_finished;
+}
+
+int get_buffer_index(AV1Decoder *pbi, RefCntBuffer *buffer)
+{
+ AV1_COMMON *const cm = &pbi->common;
+ int i = -1;
+
+ if (buffer) {
+ for (i = 0; i < FRAME_BUFFERS; i++) {
+ RefCntBuffer *buf =
+ &cm->buffer_pool->frame_bufs[i];
+ if (buf == buffer) {
+ break;
+ }
+ }
+ }
+ return i;
+}
+
+void dump_buffer(RefCntBuffer *buf)
+{
+ int i;
+ pr_info("ref_count %d, vf_ref %d, order_hint %d, w/h(%d,%d) showable_frame %d frame_type %d canvas(%d,%d) w/h(%d,%d) mi_c/r(%d,%d) header 0x%x ref_deltas(",
+ buf->ref_count, buf->buf.vf_ref, buf->order_hint, buf->width, buf->height, buf->showable_frame, buf->frame_type,
+ buf->buf.mc_canvas_y, buf->buf.mc_canvas_u_v,
+ buf->buf.y_crop_width, buf->buf.y_crop_height,
+ buf->mi_cols, buf->mi_rows,
+ buf->buf.header_adr);
+ for (i = 0; i < REF_FRAMES; i++)
+ pr_info("%d,", buf->ref_deltas[i]);
+ pr_info("), ref_order_hints(");
+
+ for (i = 0; i < INTER_REFS_PER_FRAME; i++)
+ pr_info("%d ", buf->ref_order_hints[i]);
+ pr_info(")");
+}
+
+void dump_ref_buffer_info(AV1Decoder *pbi, int i)
+{
+ AV1_COMMON *const cm = &pbi->common;
+ pr_info("remapped_ref_idx %d, ref_frame_sign_bias %d, ref_frame_id %d, valid_for_referencing %d ref_frame_side %d ref_frame_map idx %d, next_ref_frame_map idx %d",
+ cm->remapped_ref_idx[i],
+ cm->ref_frame_sign_bias[i],
+ cm->ref_frame_id[i],
+ cm->valid_for_referencing[i],
+ cm->ref_frame_side[i],
+ get_buffer_index(pbi, cm->ref_frame_map[i]),
+ get_buffer_index(pbi, cm->next_ref_frame_map[i]));
+}
+
+void dump_mv_refs(AV1Decoder *pbi)
+{
+ int i, j;
+ AV1_COMMON *const cm = &pbi->common;
+ for (i = 0; i < cm->mv_ref_id_index; i++) {
+ pr_info("%d: ref_id %d cal_tpl_mvs %d mv_ref_offset: ",
+ i, cm->mv_ref_id[i], cm->mv_cal_tpl_mvs[i]);
+ for (j = 0; j < REF_FRAMES; j++)
+ pr_info("%d ", cm->mv_ref_offset[i][j]);
+ pr_info("\n");
+ }
+}
+
+void dump_ref_spec_bufs(AV1Decoder *pbi)
+{
+ int i;
+ AV1_COMMON *const cm = &pbi->common;
+ for (i = 0; i < INTER_REFS_PER_FRAME; ++i) {
+ PIC_BUFFER_CONFIG *pic_config = av1_get_ref_frame_spec_buf(cm, LAST_FRAME + i);
+ if (pic_config == NULL) continue;
+ pr_info("%d: index %d order_hint %d header 0x%x dw_header 0x%x canvas(%d,%d) mv_wr_start 0x%x lcu_total %d\n",
+ i, pic_config->index,
+ pic_config->order_hint,
+ pic_config->header_adr,
+#ifdef AOM_AV1_MMU_DW
+ pic_config->header_dw_adr,
+#else
+ 0,
+#endif
+ pic_config->mc_canvas_y,
+ pic_config->mc_canvas_u_v,
+ pic_config->mpred_mv_wr_start_addr,
+ pic_config->lcu_total
+ );
+ }
+}
+
+#ifdef SUPPORT_SCALE_FACTOR
+void dump_scale_factors(AV1Decoder *pbi)
+{
+ int i;
+ AV1_COMMON *const cm = &pbi->common;
+ for (i = LAST_FRAME; i <= ALTREF_FRAME; ++i) {
+ struct scale_factors *const sf =
+ get_ref_scale_factors(cm, i);
+ if (sf)
+ pr_info("%d: is_scaled %d x_scale_fp %d, y_scale_fp %d\n",
+ i, av1_is_scaled(sf),
+ sf->x_scale_fp, sf->y_scale_fp);
+ else
+ pr_info("%d: sf null\n", i);
+ }
+}
+
+#endif
+
+void dump_buffer_status(AV1Decoder *pbi)
+{
+ int i;
+ AV1_COMMON *const cm = &pbi->common;
+ BufferPool *const pool = cm->buffer_pool;
+ unsigned long flags;
+
+ lock_buffer_pool(pool, flags);
+
+ pr_info("%s: pbi %p cm %p cur_frame %p\n", __func__, pbi, cm, cm->cur_frame);
+
+ pr_info("Buffer Pool:\n");
+ for (i = 0; i < FRAME_BUFFERS; i++) {
+ RefCntBuffer *buf =
+ &cm->buffer_pool->frame_bufs[i];
+ pr_info("%d: ", i);
+ if (buf)
+ dump_buffer(buf);
+ pr_info("\n");
+ }
+
+ if (cm->prev_frame) {
+ pr_info("prev_frame (%d): ",
+ get_buffer_index(pbi, cm->prev_frame));
+ dump_buffer(cm->prev_frame);
+ pr_info("\n");
+ }
+ if (cm->cur_frame) {
+ pr_info("cur_frame (%d): ",
+ get_buffer_index(pbi, cm->cur_frame));
+ dump_buffer(cm->cur_frame);
+ pr_info("\n");
+ }
+ pr_info("REF_FRAMES Info(ref buf is ref_frame_map[remapped_ref_idx[i-1]], i=1~7):\n");
+ for (i = 0; i < REF_FRAMES; i++) {
+ pr_info("%d: ", i);
+ dump_ref_buffer_info(pbi, i);
+ pr_info("\n");
+ }
+ pr_info("Ref Spec Buffers:\n");
+ dump_ref_spec_bufs(pbi);
+
+ pr_info("MV refs:\n");
+ dump_mv_refs(pbi);
+
+#ifdef SUPPORT_SCALE_FACTOR
+ pr_info("Scale factors:\n");
+ dump_scale_factors(pbi);
+#endif
+ unlock_buffer_pool(pool, flags);
+}
+
+
+struct param_dump_item_s {
+ unsigned int size;
+ char* name;
+ unsigned int adr_off;
+} param_dump_items[] = {
+ {1, "profile", (unsigned long)&(((union param_u *)0)->p.profile )},
+ {1, "still_picture", (unsigned long)&(((union param_u *)0)->p.still_picture )},
+ {1, "reduced_still_picture_hdr", (unsigned long)&(((union param_u *)0)->p.reduced_still_picture_hdr )},
+ {1, "decoder_model_info_present_flag", (unsigned long)&(((union param_u *)0)->p.decoder_model_info_present_flag)},
+ {1, "max_frame_width", (unsigned long)&(((union param_u *)0)->p.max_frame_width )},
+ {1, "max_frame_height", (unsigned long)&(((union param_u *)0)->p.max_frame_height )},
+ {1, "frame_id_numbers_present_flag", (unsigned long)&(((union param_u *)0)->p.frame_id_numbers_present_flag )},
+ {1, "delta_frame_id_length", (unsigned long)&(((union param_u *)0)->p.delta_frame_id_length )},
+ {1, "frame_id_length", (unsigned long)&(((union param_u *)0)->p.frame_id_length )},
+ {1, "order_hint_bits_minus_1", (unsigned long)&(((union param_u *)0)->p.order_hint_bits_minus_1 )},
+ {1, "enable_order_hint", (unsigned long)&(((union param_u *)0)->p.enable_order_hint )},
+ {1, "enable_dist_wtd_comp", (unsigned long)&(((union param_u *)0)->p.enable_dist_wtd_comp )},
+ {1, "enable_ref_frame_mvs", (unsigned long)&(((union param_u *)0)->p.enable_ref_frame_mvs )},
+ {1, "enable_superres", (unsigned long)&(((union param_u *)0)->p.enable_superres )},
+ {1, "superres_scale_denominator", (unsigned long)&(((union param_u *)0)->p.superres_scale_denominator )},
+ {1, "show_existing_frame", (unsigned long)&(((union param_u *)0)->p.show_existing_frame )},
+ {1, "frame_type", (unsigned long)&(((union param_u *)0)->p.frame_type )},
+ {1, "show_frame", (unsigned long)&(((union param_u *)0)->p.show_frame )},
+ {1, "e.r.r.o.r_resilient_mode", (unsigned long)&(((union param_u *)0)->p.error_resilient_mode )},
+ {1, "refresh_frame_flags", (unsigned long)&(((union param_u *)0)->p.refresh_frame_flags )},
+ {1, "showable_frame", (unsigned long)&(((union param_u *)0)->p.showable_frame )},
+ {1, "current_frame_id", (unsigned long)&(((union param_u *)0)->p.current_frame_id )},
+ {1, "frame_size_override_flag", (unsigned long)&(((union param_u *)0)->p.frame_size_override_flag )},
+ {1, "order_hint", (unsigned long)&(((union param_u *)0)->p.order_hint )},
+ {1, "primary_ref_frame", (unsigned long)&(((union param_u *)0)->p.primary_ref_frame )},
+ {1, "frame_refs_short_signaling", (unsigned long)&(((union param_u *)0)->p.frame_refs_short_signaling )},
+ {1, "frame_width", (unsigned long)&(((union param_u *)0)->p.frame_width )},
+ {1, "dec_frame_width", (unsigned long)&(((union param_u *)0)->p.dec_frame_width )},
+ {1, "frame_width_scaled", (unsigned long)&(((union param_u *)0)->p.frame_width_scaled )},
+ {1, "frame_height", (unsigned long)&(((union param_u *)0)->p.frame_height )},
+ {1, "reference_mode", (unsigned long)&(((union param_u *)0)->p.reference_mode )},
+ {1, "update_parameters", (unsigned long)&(((union param_u *)0)->p.update_parameters )},
+ {1, "film_grain_params_ref_idx", (unsigned long)&(((union param_u *)0)->p.film_grain_params_ref_idx )},
+ {1, "allow_ref_frame_mvs", (unsigned long)&(((union param_u *)0)->p.allow_ref_frame_mvs )},
+ {1, "lst_ref", (unsigned long)&(((union param_u *)0)->p.lst_ref )},
+ {1, "gld_ref", (unsigned long)&(((union param_u *)0)->p.gld_ref )},
+ {INTER_REFS_PER_FRAME, "remapped_ref_idx", (unsigned long)&(((union param_u *)0)->p.remapped_ref_idx[0] )},
+ {INTER_REFS_PER_FRAME, "delta_frame_id_minus_1", (unsigned long)&(((union param_u *)0)->p.delta_frame_id_minus_1[0] )},
+ {REF_FRAMES, "ref_order_hint", (unsigned long)&(((union param_u *)0)->p.ref_order_hint[0] )},
+};
+
+void dump_params(AV1Decoder *pbi, union param_u *params)
+{
+ int i, j;
+ unsigned char *start_adr = (unsigned char*)params;
+
+ pr_info("============ params:\n");
+ for (i = 0; i < sizeof(param_dump_items) / sizeof(param_dump_items[0]); i++) {
+ for (j = 0; j < param_dump_items[i].size; j++) {
+ if (param_dump_items[i].size > 1)
+ pr_info("%s(%d): 0x%x\n",
+ param_dump_items[i].name, j,
+ *((unsigned short*)(start_adr + param_dump_items[i].adr_off + j * 2)));
+ else
+ pr_info("%s: 0x%x\n", param_dump_items[i].name,
+ *((unsigned short*)(start_adr + param_dump_items[i].adr_off + j * 2)));
+ }
+ }
+}
+
+/*static void raw_write_image(AV1Decoder *pbi, PIC_BUFFER_CONFIG *sd)
+{
+ printf("$$$$$$$ output image\n");
+}*/
+
+/*
+ return 0, need decoding data
+ 1, decoding done
+ -1, decoding error
+
+*/
+int av1_bufmgr_process(AV1Decoder *pbi, union param_u *params,
+ unsigned char new_compressed_data, int obu_type)
+{
+ AV1_COMMON *const cm = &pbi->common;
+ int j;
+ // Release any pending output frames from the previous decoder_decode call.
+ // We need to do this even if the decoder is being flushed or the input
+ // arguments are invalid.
+ BufferPool *const pool = cm->buffer_pool;
+ int frame_decoded;
+ av1_print2(VP9_DEBUG_BUFMGR_DETAIL, "%s: pbi %p cm %p cur_frame %p\n", __func__, pbi, cm, cm->cur_frame);
+ av1_print2(VP9_DEBUG_BUFMGR_DETAIL, "%s: new_compressed_data= %d\n", __func__, new_compressed_data);
+ for (j = 0; j < pbi->num_output_frames; j++) {
+ decrease_ref_count(pbi, pbi->output_frames[j], pool);
+ }
+ pbi->num_output_frames = 0;
+ //
+ if (new_compressed_data) {
+ if (assign_cur_frame_new_fb(cm) == NULL) {
+ cm->error.error_code = AOM_CODEC_MEM_ERROR;
+ return -1;
+ }
+ pbi->seen_frame_header = 0;
+ av1_print2(VP9_DEBUG_BUFMGR_DETAIL, "New_compressed_data (%d)\n", new_compressed_data_count++);
+
+ }
+
+ frame_decoded =
+ aom_decode_frame_from_obus(pbi, params, obu_type);
+
+ if (pbi->cur_obu_type == OBU_FRAME_HEADER ||
+ pbi->cur_obu_type == OBU_REDUNDANT_FRAME_HEADER ||
+ pbi->cur_obu_type == OBU_FRAME) {
+ if (av1_is_debug(AOM_DEBUG_PRINT_LIST_INFO)) {
+ pr_info("after bufmgr (frame_decoded %d seen_frame_header %d): ",
+ frame_decoded, pbi->seen_frame_header);
+ dump_buffer_status(pbi);
+ }
+ }
+ av1_print2(VP9_DEBUG_BUFMGR_DETAIL, "%s: pbi %p cm %p cur_frame %p\n", __func__, pbi, cm, cm->cur_frame);
+
+ return frame_decoded;
+
+}
+
+int av1_get_raw_frame(AV1Decoder *pbi, size_t index, PIC_BUFFER_CONFIG **sd) {
+ if (index >= pbi->num_output_frames) return -1;
+ *sd = &pbi->output_frames[index]->buf;
+ //*grain_params = &pbi->output_frames[index]->film_grain_params;
+ //aom_clear_system_state();
+ return 0;
+}
+
+int av1_bufmgr_postproc(AV1Decoder *pbi, unsigned char frame_decoded)
+{
+ PIC_BUFFER_CONFIG *sd;
+ int index;
+#if 0
+ if (frame_decoded) {
+ printf("before swap_frame_buffers: ");
+ dump_buffer_status(pbi);
+ }
+#endif
+ swap_frame_buffers(pbi, frame_decoded);
+ if (frame_decoded) {
+ if (av1_is_debug(AOM_DEBUG_PRINT_LIST_INFO)) {
+ pr_info("after swap_frame_buffers: ");
+ dump_buffer_status(pbi);
+ }
+ }
+ if (frame_decoded) {
+ pbi->decoding_first_frame = 0;
+ }
+
+
+ for (index = 0;;index++) {
+ if (av1_get_raw_frame(pbi, index, &sd) < 0)
+ break;
+ av1_raw_write_image(pbi, sd);
+ }
+ return 0;
+}
+
+int aom_realloc_frame_buffer(AV1_COMMON *cm, PIC_BUFFER_CONFIG *pic,
+ int width, int height, unsigned int order_hint)
+{
+ av1_print2(VP9_DEBUG_BUFMGR_DETAIL, "%s, index 0x%x, width 0x%x, height 0x%x order_hint 0x%x\n",
+ __func__, pic->index, width, height, order_hint);
+ pic->y_crop_width = width;
+ pic->y_crop_height = height;
+ pic->order_hint = order_hint;
+ return 0;
+}
+
+
+unsigned char av1_frame_is_inter(const AV1_COMMON *const cm) {
+ unsigned char is_inter = cm->cur_frame && (cm->cur_frame->frame_type != KEY_FRAME)
+ && (cm->current_frame.frame_type != INTRA_ONLY_FRAME);
+ return is_inter;
+}
+
+PIC_BUFFER_CONFIG *av1_get_ref_frame_spec_buf(
+ const AV1_COMMON *const cm, const MV_REFERENCE_FRAME ref_frame) {
+ RefCntBuffer *buf = get_ref_frame_buf(cm, ref_frame);
+ if (buf) {
+ buf->buf.order_hint = buf->order_hint;
+ return &(buf->buf);
+ }
+ return NULL;
+}
+
+struct scale_factors *av1_get_ref_scale_factors(
+ AV1_COMMON *const cm, const MV_REFERENCE_FRAME ref_frame)
+{
+ return get_ref_scale_factors(cm, ref_frame);
+}
+
+void av1_set_next_ref_frame_map(AV1Decoder *pbi) {
+ int ref_index = 0;
+ int mask;
+ AV1_COMMON *const cm = &pbi->common;
+ int check_on_show_existing_frame;
+ av1_print2(VP9_DEBUG_BUFMGR_DETAIL, "%s, %d, mask 0x%x, show_existing_frame %d, reset_decoder_state %d\n",
+ __func__, pbi->camera_frame_header_ready,
+ cm->current_frame.refresh_frame_flags,
+ cm->show_existing_frame,
+ pbi->reset_decoder_state
+ );
+ if (!pbi->camera_frame_header_ready) {
+ for (mask = cm->current_frame.refresh_frame_flags; mask; mask >>= 1) {
+ cm->next_used_ref_frame_map[ref_index] = cm->next_ref_frame_map[ref_index];
+ ++ref_index;
+ }
+
+ check_on_show_existing_frame =
+ !cm->show_existing_frame || pbi->reset_decoder_state;
+ for (; ref_index < REF_FRAMES && check_on_show_existing_frame;
+ ++ref_index) {
+ cm->next_used_ref_frame_map[ref_index] = cm->next_ref_frame_map[ref_index];
+ }
+ }
+}
+
+unsigned int av1_get_next_used_ref_info(
+ const AV1_COMMON *const cm, int i) {
+ /*
+ i = 0~1 orde_hint map
+ i = 2~10 size map[i-2]
+ */
+ unsigned int info = 0;
+ int j;
+ if (i < 2) {
+ /*next_used_ref_frame_map has 8 items*/
+ for (j = 0; j < 4; j++) {
+ RefCntBuffer *buf =
+ cm->next_used_ref_frame_map[(i * 4) + j];
+ if (buf)
+ info |= ((buf->buf.order_hint & 0xff)
+ << (j * 8));
+ }
+ } else if (i < 10) {
+ RefCntBuffer *buf =
+ cm->next_used_ref_frame_map[i-2];
+ if (buf)
+ info = (buf->buf.y_crop_width << 16) | (buf->buf.y_crop_height & 0xffff);
+ } else {
+ for (j = 0; j < 4; j++) {
+ RefCntBuffer *buf =
+ cm->next_used_ref_frame_map[((i - 10) * 4) + j];
+ if (buf)
+ info |= ((buf->buf.index & 0xff)
+ << (j * 8));
+ }
+ }
+ return info;
+}
+
+RefCntBuffer *av1_get_primary_ref_frame_buf(
+ const AV1_COMMON *const cm)
+{
+ return get_primary_ref_frame_buf(cm);
+}
diff --git a/drivers/frame_provider/decoder/vav1/av1_global.h b/drivers/frame_provider/decoder/vav1/av1_global.h
new file mode 100644
index 0000000..b8c59cc
--- a/dev/null
+++ b/drivers/frame_provider/decoder/vav1/av1_global.h
@@ -0,0 +1,2307 @@
+#ifndef AV1_GLOBAL_H_
+#define AV1_GLOBAL_H_
+#define AOM_AV1_MMU_DW
+#ifndef HAVE_NEON
+#define HAVE_NEON 0
+#endif
+#ifndef CONFIG_ACCOUNTING
+#define CONFIG_ACCOUNTING 0
+#endif
+#ifndef CONFIG_INSPECTION
+#define CONFIG_INSPECTION 0
+#endif
+#ifndef CONFIG_LPF_MASK
+#define CONFIG_LPF_MASK 0
+#endif
+#ifndef CONFIG_SIZE_LIMIT
+#define CONFIG_SIZE_LIMIT 0
+#endif
+
+#define SUPPORT_SCALE_FACTOR
+#define USE_SCALED_WIDTH_FROM_UCODE
+#define AML
+#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
+#define AML_DEVICE
+#endif
+#ifdef BUFMGR_FOR_SIM
+#define printf io_printf
+#endif
+
+#ifndef INT_MAX
+#define INT_MAX 0x7FFFFFFF
+#endif
+#define AOMMIN(x, y) (((x) < (y)) ? (x) : (y))
+#define AOMMAX(x, y) (((x) > (y)) ? (x) : (y))
+
+//typedef char int8_t;
+//#ifndef BUFMGR_FOR_SIM
+typedef unsigned char uint8_t;
+//#endif
+typedef unsigned int uint32_t;
+//typedef int int32_t;
+//typedef long long int64_t;
+
+#ifdef AML
+#define AOM_AV1_MMU
+#define FILM_GRAIN_REG_SIZE 39
+typedef struct buff_s
+{
+ uint32_t buf_start;
+ uint32_t buf_size;
+ uint32_t buf_end;
+} buff_t;
+
+typedef struct BuffInfo_s
+{
+ uint32_t max_width;
+ uint32_t max_height;
+ uint32_t start_adr;
+ uint32_t end_adr;
+ buff_t ipp;
+ buff_t sao_abv;
+ buff_t sao_vb;
+ buff_t short_term_rps;
+ buff_t vps;
+ buff_t seg_map;
+ buff_t daala_top;
+ buff_t sao_up;
+ buff_t swap_buf;
+ buff_t cdf_buf;
+ buff_t gmc_buf;
+ buff_t scalelut;
+ buff_t dblk_para;
+ buff_t dblk_data;
+ buff_t cdef_data;
+ buff_t ups_data;
+#ifdef AOM_AV1_MMU
+ buff_t mmu_vbh;
+ buff_t cm_header;
+#endif
+#ifdef AOM_AV1_MMU_DW
+ buff_t mmu_vbh_dw;
+ buff_t cm_header_dw;
+#endif
+ buff_t fgs_table;
+ buff_t mpred_above;
+ buff_t mpred_mv;
+ buff_t rpm;
+ buff_t lmem;
+} BuffInfo_t;
+#endif
+
+#define va_start(v,l) __builtin_va_start(v,l)
+#define va_end(v) __builtin_va_end(v)
+#define va_arg(v,l) __builtin_va_arg(v,l)
+/*
+mem.h
+*/
+#if (defined(__GNUC__) && __GNUC__) || defined(__SUNPRO_C)
+#define DECLARE_ALIGNED(n, typ, val) typ val __attribute__((aligned(n)))
+#elif defined(_MSC_VER)
+#define DECLARE_ALIGNED(n, typ, val) __declspec(align(n)) typ val
+#else
+#warning No alignment directives known for this compiler.
+#define DECLARE_ALIGNED(n, typ, val) typ val
+#endif
+
+/* Indicates that the usage of the specified variable has been audited to assure
+ * that it's safe to use uninitialized. Silences 'may be used uninitialized'
+ * warnings on gcc.
+ */
+#if defined(__GNUC__) && __GNUC__
+#define UNINITIALIZED_IS_SAFE(x) x = x
+#else
+#define UNINITIALIZED_IS_SAFE(x) x
+#endif
+
+#if HAVE_NEON && defined(_MSC_VER)
+#define __builtin_prefetch(x)
+#endif
+
+/* Shift down with rounding for use when n >= 0, value >= 0 */
+#define ROUND_POWER_OF_TWO(value, n) (((value) + (((1 << (n)) >> 1))) >> (n))
+
+/* Shift down with rounding for signed integers, for use when n >= 0 */
+#define ROUND_POWER_OF_TWO_SIGNED(value, n) \
+ (((value) < 0) ? -ROUND_POWER_OF_TWO(-(value), (n)) \
+ : ROUND_POWER_OF_TWO((value), (n)))
+
+/* Shift down with rounding for use when n >= 0, value >= 0 for (64 bit) */
+#define ROUND_POWER_OF_TWO_64(value, n) \
+ (((value) + ((((int64_t)1 << (n)) >> 1))) >> (n))
+/* Shift down with rounding for signed integers, for use when n >= 0 (64 bit) */
+#define ROUND_POWER_OF_TWO_SIGNED_64(value, n) \
+ (((value) < 0) ? -ROUND_POWER_OF_TWO_64(-(value), (n)) \
+ : ROUND_POWER_OF_TWO_64((value), (n)))
+
+/* shift right or left depending on sign of n */
+#define RIGHT_SIGNED_SHIFT(value, n) \
+ ((n) < 0 ? ((value) << (-(n))) : ((value) >> (n)))
+
+#define ALIGN_POWER_OF_TWO(value, n) \
+ (((value) + ((1 << (n)) - 1)) & ~((1 << (n)) - 1))
+
+#define DIVIDE_AND_ROUND(x, y) (((x) + ((y) >> 1)) / (y))
+
+#define CONVERT_TO_SHORTPTR(x) ((uint16_t *)(((uintptr_t)(x)) << 1))
+#define CONVERT_TO_BYTEPTR(x) ((uint8_t *)(((uintptr_t)(x)) >> 1))
+
+#ifdef AML
+#define TYPEDEF typedef
+#define UENUM1BYTE(enumvar) enumvar
+#define SENUM1BYTE(enumvar) enumvar
+#define UENUM2BYTE(enumvar) enumvar
+#define SENUM2BYTE(enumvar) enumvar
+#define UENUM4BYTE(enumvar) enumvar
+#define SENUM4BYTE(enumvar) enumvar
+
+#else
+#define TYPEDEF
+/*!\brief force enum to be unsigned 1 byte*/
+#define UENUM1BYTE(enumvar) \
+ ; \
+ typedef uint8_t enumvar
+
+/*!\brief force enum to be signed 1 byte*/
+#define SENUM1BYTE(enumvar) \
+ ; \
+ typedef int8_t enumvar
+
+/*!\brief force enum to be unsigned 2 byte*/
+#define UENUM2BYTE(enumvar) \
+ ; \
+ typedef uint16_t enumvar
+
+/*!\brief force enum to be signed 2 byte*/
+#define SENUM2BYTE(enumvar) \
+ ; \
+ typedef int16_t enumvar
+
+/*!\brief force enum to be unsigned 4 byte*/
+#define UENUM4BYTE(enumvar) \
+ ; \
+ typedef uint32_t enumvar
+
+/*!\brief force enum to be unsigned 4 byte*/
+#define SENUM4BYTE(enumvar) \
+ ; \
+ typedef int32_t enumvar
+#endif
+
+
+/*
+#include "enums.h"
+*/
+#undef MAX_SB_SIZE
+
+// Max superblock size
+#define MAX_SB_SIZE_LOG2 7
+#define MAX_SB_SIZE (1 << MAX_SB_SIZE_LOG2)
+#define MAX_SB_SQUARE (MAX_SB_SIZE * MAX_SB_SIZE)
+
+// Min superblock size
+#define MIN_SB_SIZE_LOG2 6
+
+// Pixels per Mode Info (MI) unit
+#define MI_SIZE_LOG2 2
+#define MI_SIZE (1 << MI_SIZE_LOG2)
+
+// MI-units per max superblock (MI Block - MIB)
+#define MAX_MIB_SIZE_LOG2 (MAX_SB_SIZE_LOG2 - MI_SIZE_LOG2)
+#define MAX_MIB_SIZE (1 << MAX_MIB_SIZE_LOG2)
+
+// MI-units per min superblock
+#define MIN_MIB_SIZE_LOG2 (MIN_SB_SIZE_LOG2 - MI_SIZE_LOG2)
+
+// Mask to extract MI offset within max MIB
+#define MAX_MIB_MASK (MAX_MIB_SIZE - 1)
+
+// Maximum number of tile rows and tile columns
+#define MAX_TILE_ROWS 64
+#define MAX_TILE_COLS 64
+
+#define MAX_VARTX_DEPTH 2
+
+#define MI_SIZE_64X64 (64 >> MI_SIZE_LOG2)
+#define MI_SIZE_128X128 (128 >> MI_SIZE_LOG2)
+
+#define MAX_PALETTE_SQUARE (64 * 64)
+// Maximum number of colors in a palette.
+#define PALETTE_MAX_SIZE 8
+// Minimum number of colors in a palette.
+#define PALETTE_MIN_SIZE 2
+
+#define FRAME_OFFSET_BITS 5
+#define MAX_FRAME_DISTANCE ((1 << FRAME_OFFSET_BITS) - 1)
+
+// 4 frame filter levels: y plane vertical, y plane horizontal,
+// u plane, and v plane
+#define FRAME_LF_COUNT 4
+#define DEFAULT_DELTA_LF_MULTI 0
+#define MAX_MODE_LF_DELTAS 2
+
+#define DIST_PRECISION_BITS 4
+#define DIST_PRECISION (1 << DIST_PRECISION_BITS) // 16
+
+#define PROFILE_BITS 3
+// The following three profiles are currently defined.
+// Profile 0. 8-bit and 10-bit 4:2:0 and 4:0:0 only.
+// Profile 1. 8-bit and 10-bit 4:4:4
+// Profile 2. 8-bit and 10-bit 4:2:2
+// 12-bit 4:0:0, 4:2:2 and 4:4:4
+// Since we have three bits for the profiles, it can be extended later.
+TYPEDEF enum {
+ PROFILE_0,
+ PROFILE_1,
+ PROFILE_2,
+ MAX_PROFILES,
+} SENUM1BYTE(BITSTREAM_PROFILE);
+
+#define OP_POINTS_CNT_MINUS_1_BITS 5
+#define OP_POINTS_IDC_BITS 12
+
+// Note: Some enums use the attribute 'packed' to use smallest possible integer
+// type, so that we can save memory when they are used in structs/arrays.
+
+typedef enum ATTRIBUTE_PACKED {
+ BLOCK_4X4,
+ BLOCK_4X8,
+ BLOCK_8X4,
+ BLOCK_8X8,
+ BLOCK_8X16,
+ BLOCK_16X8,
+ BLOCK_16X16,
+ BLOCK_16X32,
+ BLOCK_32X16,
+ BLOCK_32X32,
+ BLOCK_32X64,
+ BLOCK_64X32,
+ BLOCK_64X64,
+ BLOCK_64X128,
+ BLOCK_128X64,
+ BLOCK_128X128,
+ BLOCK_4X16,
+ BLOCK_16X4,
+ BLOCK_8X32,
+ BLOCK_32X8,
+ BLOCK_16X64,
+ BLOCK_64X16,
+ BLOCK_SIZES_ALL,
+ BLOCK_SIZES = BLOCK_4X16,
+ BLOCK_INVALID = 255,
+ BLOCK_LARGEST = (BLOCK_SIZES - 1)
+} BLOCK_SIZE2;
+
+// 4X4, 8X8, 16X16, 32X32, 64X64, 128X128
+#define SQR_BLOCK_SIZES 6
+
+TYPEDEF enum {
+ PARTITION_NONE,
+ PARTITION_HORZ,
+ PARTITION_VERT,
+ PARTITION_SPLIT,
+ PARTITION_HORZ_A, // HORZ split and the top partition is split again
+ PARTITION_HORZ_B, // HORZ split and the bottom partition is split again
+ PARTITION_VERT_A, // VERT split and the left partition is split again
+ PARTITION_VERT_B, // VERT split and the right partition is split again
+ PARTITION_HORZ_4, // 4:1 horizontal partition
+ PARTITION_VERT_4, // 4:1 vertical partition
+ EXT_PARTITION_TYPES,
+ PARTITION_TYPES = PARTITION_SPLIT + 1,
+ PARTITION_INVALID = 255
+} UENUM1BYTE(PARTITION_TYPE);
+
+typedef char PARTITION_CONTEXT;
+#define PARTITION_PLOFFSET 4 // number of probability models per block size
+#define PARTITION_BLOCK_SIZES 5
+#define PARTITION_CONTEXTS (PARTITION_BLOCK_SIZES * PARTITION_PLOFFSET)
+
+// block transform size
+TYPEDEF enum {
+ TX_4X4, // 4x4 transform
+ TX_8X8, // 8x8 transform
+ TX_16X16, // 16x16 transform
+ TX_32X32, // 32x32 transform
+ TX_64X64, // 64x64 transform
+ TX_4X8, // 4x8 transform
+ TX_8X4, // 8x4 transform
+ TX_8X16, // 8x16 transform
+ TX_16X8, // 16x8 transform
+ TX_16X32, // 16x32 transform
+ TX_32X16, // 32x16 transform
+ TX_32X64, // 32x64 transform
+ TX_64X32, // 64x32 transform
+ TX_4X16, // 4x16 transform
+ TX_16X4, // 16x4 transform
+ TX_8X32, // 8x32 transform
+ TX_32X8, // 32x8 transform
+ TX_16X64, // 16x64 transform
+ TX_64X16, // 64x16 transform
+ TX_SIZES_ALL, // Includes rectangular transforms
+ TX_SIZES = TX_4X8, // Does NOT include rectangular transforms
+ TX_SIZES_LARGEST = TX_64X64,
+ TX_INVALID = 255 // Invalid transform size
+} UENUM1BYTE(TX_SIZE);
+
+#define TX_SIZE_LUMA_MIN (TX_4X4)
+/* We don't need to code a transform size unless the allowed size is at least
+ one more than the minimum. */
+#define TX_SIZE_CTX_MIN (TX_SIZE_LUMA_MIN + 1)
+
+// Maximum tx_size categories
+#define MAX_TX_CATS (TX_SIZES - TX_SIZE_CTX_MIN)
+#define MAX_TX_DEPTH 2
+
+#define MAX_TX_SIZE_LOG2 (6)
+#define MAX_TX_SIZE (1 << MAX_TX_SIZE_LOG2)
+#define MIN_TX_SIZE_LOG2 2
+#define MIN_TX_SIZE (1 << MIN_TX_SIZE_LOG2)
+#define MAX_TX_SQUARE (MAX_TX_SIZE * MAX_TX_SIZE)
+
+// Pad 4 extra columns to remove horizontal availability check.
+#define TX_PAD_HOR_LOG2 2
+#define TX_PAD_HOR 4
+// Pad 6 extra rows (2 on top and 4 on bottom) to remove vertical availability
+// check.
+#define TX_PAD_TOP 0
+#define TX_PAD_BOTTOM 4
+#define TX_PAD_VER (TX_PAD_TOP + TX_PAD_BOTTOM)
+// Pad 16 extra bytes to avoid reading overflow in SIMD optimization.
+#define TX_PAD_END 16
+#define TX_PAD_2D ((32 + TX_PAD_HOR) * (32 + TX_PAD_VER) + TX_PAD_END)
+
+// Number of maxium size transform blocks in the maximum size superblock
+#define MAX_TX_BLOCKS_IN_MAX_SB_LOG2 ((MAX_SB_SIZE_LOG2 - MAX_TX_SIZE_LOG2) * 2)
+#define MAX_TX_BLOCKS_IN_MAX_SB (1 << MAX_TX_BLOCKS_IN_MAX_SB_LOG2)
+
+// frame transform mode
+TYPEDEF enum {
+ ONLY_4X4, // use only 4x4 transform
+ TX_MODE_LARGEST, // transform size is the largest possible for pu size
+ TX_MODE_SELECT, // transform specified for each block
+ TX_MODES,
+} UENUM1BYTE(TX_MODE);
+
+// 1D tx types
+TYPEDEF enum {
+ DCT_1D,
+ ADST_1D,
+ FLIPADST_1D,
+ IDTX_1D,
+ TX_TYPES_1D,
+} UENUM1BYTE(TX_TYPE_1D);
+
+TYPEDEF enum {
+ DCT_DCT, // DCT in both horizontal and vertical
+ ADST_DCT, // ADST in vertical, DCT in horizontal
+ DCT_ADST, // DCT in vertical, ADST in horizontal
+ ADST_ADST, // ADST in both directions
+ FLIPADST_DCT, // FLIPADST in vertical, DCT in horizontal
+ DCT_FLIPADST, // DCT in vertical, FLIPADST in horizontal
+ FLIPADST_FLIPADST, // FLIPADST in both directions
+ ADST_FLIPADST, // ADST in vertical, FLIPADST in horizontal
+ FLIPADST_ADST, // FLIPADST in vertical, ADST in horizontal
+ IDTX, // Identity in both directions
+ V_DCT, // DCT in vertical, identity in horizontal
+ H_DCT, // Identity in vertical, DCT in horizontal
+ V_ADST, // ADST in vertical, identity in horizontal
+ H_ADST, // Identity in vertical, ADST in horizontal
+ V_FLIPADST, // FLIPADST in vertical, identity in horizontal
+ H_FLIPADST, // Identity in vertical, FLIPADST in horizontal
+ TX_TYPES,
+} UENUM1BYTE(TX_TYPE);
+
+TYPEDEF enum {
+ REG_REG,
+ REG_SMOOTH,
+ REG_SHARP,
+ SMOOTH_REG,
+ SMOOTH_SMOOTH,
+ SMOOTH_SHARP,
+ SHARP_REG,
+ SHARP_SMOOTH,
+ SHARP_SHARP,
+} UENUM1BYTE(DUAL_FILTER_TYPE);
+
+TYPEDEF enum {
+ // DCT only
+ EXT_TX_SET_DCTONLY,
+ // DCT + Identity only
+ EXT_TX_SET_DCT_IDTX,
+ // Discrete Trig transforms w/o flip (4) + Identity (1)
+ EXT_TX_SET_DTT4_IDTX,
+ // Discrete Trig transforms w/o flip (4) + Identity (1) + 1D Hor/vert DCT (2)
+ EXT_TX_SET_DTT4_IDTX_1DDCT,
+ // Discrete Trig transforms w/ flip (9) + Identity (1) + 1D Hor/Ver DCT (2)
+ EXT_TX_SET_DTT9_IDTX_1DDCT,
+ // Discrete Trig transforms w/ flip (9) + Identity (1) + 1D Hor/Ver (6)
+ EXT_TX_SET_ALL16,
+ EXT_TX_SET_TYPES
+} UENUM1BYTE(TxSetType);
+
+#define IS_2D_TRANSFORM(tx_type) (tx_type < IDTX)
+
+#define EXT_TX_SIZES 4 // number of sizes that use extended transforms
+#define EXT_TX_SETS_INTER 4 // Sets of transform selections for INTER
+#define EXT_TX_SETS_INTRA 3 // Sets of transform selections for INTRA
+
+TYPEDEF enum {
+ AOM_LAST_FLAG = 1 << 0,
+ AOM_LAST2_FLAG = 1 << 1,
+ AOM_LAST3_FLAG = 1 << 2,
+ AOM_GOLD_FLAG = 1 << 3,
+ AOM_BWD_FLAG = 1 << 4,
+ AOM_ALT2_FLAG = 1 << 5,
+ AOM_ALT_FLAG = 1 << 6,
+ AOM_REFFRAME_ALL = (1 << 7) - 1
+} UENUM1BYTE(AOM_REFFRAME);
+
+TYPEDEF enum {
+ UNIDIR_COMP_REFERENCE,
+ BIDIR_COMP_REFERENCE,
+ COMP_REFERENCE_TYPES,
+} UENUM1BYTE(COMP_REFERENCE_TYPE);
+
+/*enum { PLANE_TYPE_Y, PLANE_TYPE_UV, PLANE_TYPES } UENUM1BYTE(PLANE_TYPE);*/
+
+#define CFL_ALPHABET_SIZE_LOG2 4
+#define CFL_ALPHABET_SIZE (1 << CFL_ALPHABET_SIZE_LOG2)
+#define CFL_MAGS_SIZE ((2 << CFL_ALPHABET_SIZE_LOG2) + 1)
+#define CFL_IDX_U(idx) (idx >> CFL_ALPHABET_SIZE_LOG2)
+#define CFL_IDX_V(idx) (idx & (CFL_ALPHABET_SIZE - 1))
+
+/*enum { CFL_PRED_U, CFL_PRED_V, CFL_PRED_PLANES } UENUM1BYTE(CFL_PRED_TYPE);*/
+
+TYPEDEF enum {
+ CFL_SIGN_ZERO,
+ CFL_SIGN_NEG,
+ CFL_SIGN_POS,
+ CFL_SIGNS
+} UENUM1BYTE(CFL_SIGN_TYPE);
+
+TYPEDEF enum {
+ CFL_DISALLOWED,
+ CFL_ALLOWED,
+ CFL_ALLOWED_TYPES
+} UENUM1BYTE(CFL_ALLOWED_TYPE);
+
+// CFL_SIGN_ZERO,CFL_SIGN_ZERO is invalid
+#define CFL_JOINT_SIGNS (CFL_SIGNS * CFL_SIGNS - 1)
+// CFL_SIGN_U is equivalent to (js + 1) / 3 for js in 0 to 8
+#define CFL_SIGN_U(js) (((js + 1) * 11) >> 5)
+// CFL_SIGN_V is equivalent to (js + 1) % 3 for js in 0 to 8
+#define CFL_SIGN_V(js) ((js + 1) - CFL_SIGNS * CFL_SIGN_U(js))
+
+// There is no context when the alpha for a given plane is zero.
+// So there are 2 fewer contexts than joint signs.
+#define CFL_ALPHA_CONTEXTS (CFL_JOINT_SIGNS + 1 - CFL_SIGNS)
+#define CFL_CONTEXT_U(js) (js + 1 - CFL_SIGNS)
+// Also, the contexts are symmetric under swapping the planes.
+#define CFL_CONTEXT_V(js) \
+ (CFL_SIGN_V(js) * CFL_SIGNS + CFL_SIGN_U(js) - CFL_SIGNS)
+
+TYPEDEF enum {
+ PALETTE_MAP,
+ COLOR_MAP_TYPES,
+} UENUM1BYTE(COLOR_MAP_TYPE);
+
+TYPEDEF enum {
+ TWO_COLORS,
+ THREE_COLORS,
+ FOUR_COLORS,
+ FIVE_COLORS,
+ SIX_COLORS,
+ SEVEN_COLORS,
+ EIGHT_COLORS,
+ PALETTE_SIZES
+} UENUM1BYTE(PALETTE_SIZE);
+
+TYPEDEF enum {
+ PALETTE_COLOR_ONE,
+ PALETTE_COLOR_TWO,
+ PALETTE_COLOR_THREE,
+ PALETTE_COLOR_FOUR,
+ PALETTE_COLOR_FIVE,
+ PALETTE_COLOR_SIX,
+ PALETTE_COLOR_SEVEN,
+ PALETTE_COLOR_EIGHT,
+ PALETTE_COLORS
+} UENUM1BYTE(PALETTE_COLOR);
+
+// Note: All directional predictors must be between V_PRED and D67_PRED (both
+// inclusive).
+TYPEDEF enum {
+ DC_PRED, // Average of above and left pixels
+ V_PRED, // Vertical
+ H_PRED, // Horizontal
+ D45_PRED, // Directional 45 degree
+ D135_PRED, // Directional 135 degree
+ D113_PRED, // Directional 113 degree
+ D157_PRED, // Directional 157 degree
+ D203_PRED, // Directional 203 degree
+ D67_PRED, // Directional 67 degree
+ SMOOTH_PRED, // Combination of horizontal and vertical interpolation
+ SMOOTH_V_PRED, // Vertical interpolation
+ SMOOTH_H_PRED, // Horizontal interpolation
+ PAETH_PRED, // Predict from the direction of smallest gradient
+ NEARESTMV,
+ NEARMV,
+ GLOBALMV,
+ NEWMV,
+ // Compound ref compound modes
+ NEAREST_NEARESTMV,
+ NEAR_NEARMV,
+ NEAREST_NEWMV,
+ NEW_NEARESTMV,
+ NEAR_NEWMV,
+ NEW_NEARMV,
+ GLOBAL_GLOBALMV,
+ NEW_NEWMV,
+ MB_MODE_COUNT,
+ INTRA_MODE_START = DC_PRED,
+ INTRA_MODE_END = NEARESTMV,
+ INTRA_MODE_NUM = INTRA_MODE_END - INTRA_MODE_START,
+ SINGLE_INTER_MODE_START = NEARESTMV,
+ SINGLE_INTER_MODE_END = NEAREST_NEARESTMV,
+ SINGLE_INTER_MODE_NUM = SINGLE_INTER_MODE_END - SINGLE_INTER_MODE_START,
+ COMP_INTER_MODE_START = NEAREST_NEARESTMV,
+ COMP_INTER_MODE_END = MB_MODE_COUNT,
+ COMP_INTER_MODE_NUM = COMP_INTER_MODE_END - COMP_INTER_MODE_START,
+ INTER_MODE_START = NEARESTMV,
+ INTER_MODE_END = MB_MODE_COUNT,
+ INTRA_MODES = PAETH_PRED + 1, // PAETH_PRED has to be the last intra mode.
+ INTRA_INVALID = MB_MODE_COUNT // For uv_mode in inter blocks
+} UENUM1BYTE(PREDICTION_MODE);
+
+// TODO(ltrudeau) Do we really want to pack this?
+// TODO(ltrudeau) Do we match with PREDICTION_MODE?
+TYPEDEF enum {
+ UV_DC_PRED, // Average of above and left pixels
+ UV_V_PRED, // Vertical
+ UV_H_PRED, // Horizontal
+ UV_D45_PRED, // Directional 45 degree
+ UV_D135_PRED, // Directional 135 degree
+ UV_D113_PRED, // Directional 113 degree
+ UV_D157_PRED, // Directional 157 degree
+ UV_D203_PRED, // Directional 203 degree
+ UV_D67_PRED, // Directional 67 degree
+ UV_SMOOTH_PRED, // Combination of horizontal and vertical interpolation
+ UV_SMOOTH_V_PRED, // Vertical interpolation
+ UV_SMOOTH_H_PRED, // Horizontal interpolation
+ UV_PAETH_PRED, // Predict from the direction of smallest gradient
+ UV_CFL_PRED, // Chroma-from-Luma
+ UV_INTRA_MODES,
+ UV_MODE_INVALID, // For uv_mode in inter blocks
+} UENUM1BYTE(UV_PREDICTION_MODE);
+
+TYPEDEF enum {
+ SIMPLE_TRANSLATION,
+ OBMC_CAUSAL, // 2-sided OBMC
+ WARPED_CAUSAL, // 2-sided WARPED
+ MOTION_MODES
+} UENUM1BYTE(MOTION_MODE);
+
+TYPEDEF enum {
+ II_DC_PRED,
+ II_V_PRED,
+ II_H_PRED,
+ II_SMOOTH_PRED,
+ INTERINTRA_MODES
+} UENUM1BYTE(INTERINTRA_MODE);
+
+TYPEDEF enum {
+ COMPOUND_AVERAGE,
+ COMPOUND_DISTWTD,
+ COMPOUND_WEDGE,
+ COMPOUND_DIFFWTD,
+ COMPOUND_TYPES,
+ MASKED_COMPOUND_TYPES = 2,
+} UENUM1BYTE(COMPOUND_TYPE);
+
+TYPEDEF enum {
+ FILTER_DC_PRED,
+ FILTER_V_PRED,
+ FILTER_H_PRED,
+ FILTER_D157_PRED,
+ FILTER_PAETH_PRED,
+ FILTER_INTRA_MODES,
+} UENUM1BYTE(FILTER_INTRA_MODE);
+
+TYPEDEF enum {
+ SEQ_LEVEL_2_0,
+ SEQ_LEVEL_2_1,
+ SEQ_LEVEL_2_2,
+ SEQ_LEVEL_2_3,
+ SEQ_LEVEL_3_0,
+ SEQ_LEVEL_3_1,
+ SEQ_LEVEL_3_2,
+ SEQ_LEVEL_3_3,
+ SEQ_LEVEL_4_0,
+ SEQ_LEVEL_4_1,
+ SEQ_LEVEL_4_2,
+ SEQ_LEVEL_4_3,
+ SEQ_LEVEL_5_0,
+ SEQ_LEVEL_5_1,
+ SEQ_LEVEL_5_2,
+ SEQ_LEVEL_5_3,
+ SEQ_LEVEL_6_0,
+ SEQ_LEVEL_6_1,
+ SEQ_LEVEL_6_2,
+ SEQ_LEVEL_6_3,
+ SEQ_LEVEL_7_0,
+ SEQ_LEVEL_7_1,
+ SEQ_LEVEL_7_2,
+ SEQ_LEVEL_7_3,
+ SEQ_LEVELS,
+ SEQ_LEVEL_MAX = 31
+} UENUM1BYTE(AV1_LEVEL);
+
+#define LEVEL_BITS 5
+
+#define DIRECTIONAL_MODES 8
+#define MAX_ANGLE_DELTA 3
+#define ANGLE_STEP 3
+
+#define INTER_MODES (1 + NEWMV - NEARESTMV)
+
+#define INTER_COMPOUND_MODES (1 + NEW_NEWMV - NEAREST_NEARESTMV)
+
+#define SKIP_CONTEXTS 3
+#define SKIP_MODE_CONTEXTS 3
+
+#define COMP_INDEX_CONTEXTS 6
+#define COMP_GROUP_IDX_CONTEXTS 6
+
+#define NMV_CONTEXTS 3
+
+#define NEWMV_MODE_CONTEXTS 6
+#define GLOBALMV_MODE_CONTEXTS 2
+#define REFMV_MODE_CONTEXTS 6
+#define DRL_MODE_CONTEXTS 3
+
+#define GLOBALMV_OFFSET 3
+#define REFMV_OFFSET 4
+
+#define NEWMV_CTX_MASK ((1 << GLOBALMV_OFFSET) - 1)
+#define GLOBALMV_CTX_MASK ((1 << (REFMV_OFFSET - GLOBALMV_OFFSET)) - 1)
+#define REFMV_CTX_MASK ((1 << (8 - REFMV_OFFSET)) - 1)
+
+#define COMP_NEWMV_CTXS 5
+#define INTER_MODE_CONTEXTS 8
+
+#define DELTA_Q_SMALL 3
+#define DELTA_Q_PROBS (DELTA_Q_SMALL)
+#define DEFAULT_DELTA_Q_RES_PERCEPTUAL 4
+#define DEFAULT_DELTA_Q_RES_OBJECTIVE 4
+
+#define DELTA_LF_SMALL 3
+#define DELTA_LF_PROBS (DELTA_LF_SMALL)
+#define DEFAULT_DELTA_LF_RES 2
+
+/* Segment Feature Masks */
+#define MAX_MV_REF_CANDIDATES 2
+
+#define MAX_REF_MV_STACK_SIZE 8
+#define REF_CAT_LEVEL 640
+
+#define INTRA_INTER_CONTEXTS 4
+#define COMP_INTER_CONTEXTS 5
+#define REF_CONTEXTS 3
+
+#define COMP_REF_TYPE_CONTEXTS 5
+#define UNI_COMP_REF_CONTEXTS 3
+
+#define TXFM_PARTITION_CONTEXTS ((TX_SIZES - TX_8X8) * 6 - 3)
+#ifdef ORI_CODE
+typedef uint8_t TXFM_CONTEXT;
+#endif
+// An enum for single reference types (and some derived values).
+enum {
+ NONE_FRAME = -1,
+ INTRA_FRAME,
+ LAST_FRAME,
+ LAST2_FRAME,
+ LAST3_FRAME,
+ GOLDEN_FRAME,
+ BWDREF_FRAME,
+ ALTREF2_FRAME,
+ ALTREF_FRAME,
+ REF_FRAMES,
+
+ // Extra/scratch reference frame. It may be:
+ // - used to update the ALTREF2_FRAME ref (see lshift_bwd_ref_frames()), or
+ // - updated from ALTREF2_FRAME ref (see rshift_bwd_ref_frames()).
+ EXTREF_FRAME = REF_FRAMES,
+
+ // Number of inter (non-intra) reference types.
+ INTER_REFS_PER_FRAME = ALTREF_FRAME - LAST_FRAME + 1,
+
+ // Number of forward (aka past) reference types.
+ FWD_REFS = GOLDEN_FRAME - LAST_FRAME + 1,
+
+ // Number of backward (aka future) reference types.
+ BWD_REFS = ALTREF_FRAME - BWDREF_FRAME + 1,
+
+ SINGLE_REFS = FWD_REFS + BWD_REFS,
+};
+
+#define REF_FRAMES_LOG2 3
+
+// REF_FRAMES for the cm->ref_frame_map array, 1 scratch frame for the new
+// frame in cm->cur_frame, INTER_REFS_PER_FRAME for scaled references on the
+// encoder in the cpi->scaled_ref_buf array.
+#define FRAME_BUFFERS (REF_FRAMES + 1 + INTER_REFS_PER_FRAME)
+
+#define FWD_RF_OFFSET(ref) (ref - LAST_FRAME)
+#define BWD_RF_OFFSET(ref) (ref - BWDREF_FRAME)
+
+TYPEDEF enum {
+ LAST_LAST2_FRAMES, // { LAST_FRAME, LAST2_FRAME }
+ LAST_LAST3_FRAMES, // { LAST_FRAME, LAST3_FRAME }
+ LAST_GOLDEN_FRAMES, // { LAST_FRAME, GOLDEN_FRAME }
+ BWDREF_ALTREF_FRAMES, // { BWDREF_FRAME, ALTREF_FRAME }
+ LAST2_LAST3_FRAMES, // { LAST2_FRAME, LAST3_FRAME }
+ LAST2_GOLDEN_FRAMES, // { LAST2_FRAME, GOLDEN_FRAME }
+ LAST3_GOLDEN_FRAMES, // { LAST3_FRAME, GOLDEN_FRAME }
+ BWDREF_ALTREF2_FRAMES, // { BWDREF_FRAME, ALTREF2_FRAME }
+ ALTREF2_ALTREF_FRAMES, // { ALTREF2_FRAME, ALTREF_FRAME }
+ TOTAL_UNIDIR_COMP_REFS,
+ // NOTE: UNIDIR_COMP_REFS is the number of uni-directional reference pairs
+ // that are explicitly signaled.
+ UNIDIR_COMP_REFS = BWDREF_ALTREF_FRAMES + 1,
+} UENUM1BYTE(UNIDIR_COMP_REF);
+
+#define TOTAL_COMP_REFS (FWD_REFS * BWD_REFS + TOTAL_UNIDIR_COMP_REFS)
+
+#define COMP_REFS (FWD_REFS * BWD_REFS + UNIDIR_COMP_REFS)
+
+// NOTE: A limited number of unidirectional reference pairs can be signalled for
+// compound prediction. The use of skip mode, on the other hand, makes it
+// possible to have a reference pair not listed for explicit signaling.
+#define MODE_CTX_REF_FRAMES (REF_FRAMES + TOTAL_COMP_REFS)
+
+// Note: It includes single and compound references. So, it can take values from
+// NONE_FRAME to (MODE_CTX_REF_FRAMES - 1). Hence, it is not defined as an enum.
+typedef int8_t MV_REFERENCE_FRAME;
+
+TYPEDEF enum {
+ RESTORE_NONE,
+ RESTORE_WIENER,
+ RESTORE_SGRPROJ,
+ RESTORE_SWITCHABLE,
+ RESTORE_SWITCHABLE_TYPES = RESTORE_SWITCHABLE,
+ RESTORE_TYPES = 4,
+} UENUM1BYTE(RestorationType);
+
+// Picture prediction structures (0-12 are predefined) in scalability metadata.
+TYPEDEF enum {
+ SCALABILITY_L1T2 = 0,
+ SCALABILITY_L1T3 = 1,
+ SCALABILITY_L2T1 = 2,
+ SCALABILITY_L2T2 = 3,
+ SCALABILITY_L2T3 = 4,
+ SCALABILITY_S2T1 = 5,
+ SCALABILITY_S2T2 = 6,
+ SCALABILITY_S2T3 = 7,
+ SCALABILITY_L2T1h = 8,
+ SCALABILITY_L2T2h = 9,
+ SCALABILITY_L2T3h = 10,
+ SCALABILITY_S2T1h = 11,
+ SCALABILITY_S2T2h = 12,
+ SCALABILITY_S2T3h = 13,
+ SCALABILITY_SS = 14
+} UENUM1BYTE(SCALABILITY_STRUCTURES);
+
+#define SUPERRES_SCALE_BITS 3
+#define SUPERRES_SCALE_DENOMINATOR_MIN (SCALE_NUMERATOR + 1)
+
+// In large_scale_tile coding, external references are used.
+#define MAX_EXTERNAL_REFERENCES 128
+#define MAX_TILES 512
+
+
+#define CONFIG_MULTITHREAD 0
+#define CONFIG_ENTROPY_STATS 0
+
+#define CONFIG_MAX_DECODE_PROFILE 2
+
+/*
+from:
+seg_common.h
+*/
+#ifdef ORI_CODE
+
+#define MAX_SEGMENTS 8
+#define SEG_TREE_PROBS (MAX_SEGMENTS - 1)
+
+#define SEG_TEMPORAL_PRED_CTXS 3
+#define SPATIAL_PREDICTION_PROBS 3
+
+enum {
+ SEG_LVL_ALT_Q, // Use alternate Quantizer ....
+ SEG_LVL_ALT_LF_Y_V, // Use alternate loop filter value on y plane vertical
+ SEG_LVL_ALT_LF_Y_H, // Use alternate loop filter value on y plane horizontal
+ SEG_LVL_ALT_LF_U, // Use alternate loop filter value on u plane
+ SEG_LVL_ALT_LF_V, // Use alternate loop filter value on v plane
+ SEG_LVL_REF_FRAME, // Optional Segment reference frame
+ SEG_LVL_SKIP, // Optional Segment (0,0) + skip mode
+ SEG_LVL_GLOBALMV,
+ SEG_LVL_MAX
+} UENUM1BYTE(SEG_LVL_FEATURES);
+
+struct segmentation {
+ uint8_t enabled;
+ uint8_t update_map;
+ uint8_t update_data;
+ uint8_t temporal_update;
+
+ int16_t feature_data[MAX_SEGMENTS][SEG_LVL_MAX];
+ unsigned int feature_mask[MAX_SEGMENTS];
+ int last_active_segid; // The highest numbered segment id that has some
+ // enabled feature.
+ uint8_t segid_preskip; // Whether the segment id will be read before the
+ // skip syntax element.
+ // 1: the segment id will be read first.
+ // 0: the skip syntax element will be read first.
+};
+
+/*
+from av1_loopfilter.h
+*/
+#define MAX_LOOP_FILTER 63
+
+
+/* from
+quant_common.h:
+*/
+#define MAXQ 255
+
+#endif
+
+/*
+from:
+aom/av1/common/common.h
+*/
+#define av1_zero(dest) memset(&(dest), 0, sizeof(dest))
+#define av1_zero_array(dest, n) memset(dest, 0, n * sizeof(*(dest)))
+/*
+from:
+aom/av1/common/alloccommon.h
+*/
+#define INVALID_IDX -1 // Invalid buffer index.
+
+/*
+from:
+aom/av1/common/timing.h
+*/
+typedef struct aom_timing {
+ uint32_t num_units_in_display_tick;
+ uint32_t time_scale;
+ int equal_picture_interval;
+ uint32_t num_ticks_per_picture;
+} aom_timing_info_t;
+
+typedef struct aom_dec_model_info {
+ uint32_t num_units_in_decoding_tick;
+ int encoder_decoder_buffer_delay_length;
+ int buffer_removal_time_length;
+ int frame_presentation_time_length;
+} aom_dec_model_info_t;
+
+typedef struct aom_dec_model_op_parameters {
+ int decoder_model_param_present_flag;
+ int64_t bitrate;
+ int64_t buffer_size;
+ uint32_t decoder_buffer_delay;
+ uint32_t encoder_buffer_delay;
+ int low_delay_mode_flag;
+ int display_model_param_present_flag;
+ int initial_display_delay;
+} aom_dec_model_op_parameters_t;
+
+typedef struct aom_op_timing_info_t {
+ uint32_t buffer_removal_time;
+} aom_op_timing_info_t;
+/*
+from:
+aom/aom_codec.h
+*/
+/*!\brief OBU types. */
+typedef enum {
+ OBU_SEQUENCE_HEADER = 1,
+ OBU_TEMPORAL_DELIMITER = 2,
+ OBU_FRAME_HEADER = 3,
+ OBU_TILE_GROUP = 4,
+ OBU_METADATA = 5,
+ OBU_FRAME = 6,
+ OBU_REDUNDANT_FRAME_HEADER = 7,
+ OBU_TILE_LIST = 8,
+ OBU_PADDING = 15,
+} OBU_TYPE;
+
+typedef enum aom_bit_depth {
+ AOM_BITS_8 = 8, /**< 8 bits */
+ AOM_BITS_10 = 10, /**< 10 bits */
+ AOM_BITS_12 = 12, /**< 12 bits */
+} aom_bit_depth_t;
+
+/*!\brief Algorithm return codes */
+typedef enum {
+ /*!\brief Operation completed without error */
+ AOM_CODEC_OK,
+
+ /*!\brief Unspecified error */
+ AOM_CODEC_ERROR,
+
+ /*!\brief Memory operation failed */
+ AOM_CODEC_MEM_ERROR,
+
+ /*!\brief ABI version mismatch */
+ AOM_CODEC_ABI_MISMATCH,
+
+ /*!\brief Algorithm does not have required capability */
+ AOM_CODEC_INCAPABLE,
+
+ /*!\brief The given bitstream is not supported.
+ *
+ * The bitstream was unable to be parsed at the highest level. The decoder
+ * is unable to proceed. This error \ref SHOULD be treated as fatal to the
+ * stream. */
+ AOM_CODEC_UNSUP_BITSTREAM,
+
+ /*!\brief Encoded bitstream uses an unsupported feature
+ *
+ * The decoder does not implement a feature required by the encoder. This
+ * return code should only be used for features that prevent future
+ * pictures from being properly decoded. This error \ref MAY be treated as
+ * fatal to the stream or \ref MAY be treated as fatal to the current GOP.
+ */
+ AOM_CODEC_UNSUP_FEATURE,
+
+ /*!\brief The coded data for this stream is corrupt or incomplete
+ *
+ * There was a problem decoding the current frame. This return code
+ * should only be used for failures that prevent future pictures from
+ * being properly decoded. This error \ref MAY be treated as fatal to the
+ * stream or \ref MAY be treated as fatal to the current GOP. If decoding
+ * is continued for the current GOP, artifacts may be present.
+ */
+ AOM_CODEC_CORRUPT_FRAME,
+
+ /*!\brief An application-supplied parameter is not valid.
+ *
+ */
+ AOM_CODEC_INVALID_PARAM,
+
+ /*!\brief An iterator reached the end of list.
+ *
+ */
+ AOM_CODEC_LIST_END
+
+} aom_codec_err_t;
+
+typedef struct cfg_options {
+ /*!\brief Reflects if ext_partition should be enabled
+ *
+ * If this value is non-zero it enabled the feature
+ */
+ unsigned int ext_partition;
+} cfg_options_t;
+
+/*
+from:
+aom/av1/common/obu_util.h
+*/
+typedef struct {
+ size_t size; // Size (1 or 2 bytes) of the OBU header (including the
+ // optional OBU extension header) in the bitstream.
+ OBU_TYPE type;
+ int has_size_field;
+ int has_extension;
+ // The following fields come from the OBU extension header and therefore are
+ // only used if has_extension is true.
+ int temporal_layer_id;
+ int spatial_layer_id;
+} ObuHeader;
+
+
+/*
+from:
+aom/internal/aom_codec_internal.h
+*/
+
+struct aom_internal_error_info {
+ aom_codec_err_t error_code;
+ int has_detail;
+ char detail[80];
+ int setjmp; // Boolean: whether 'jmp' is valid.
+#ifdef ORI_CODE
+ jmp_buf jmp;
+#endif
+};
+
+/*
+from:
+aom/aom_frame_buffer.h
+*/
+typedef struct aom_codec_frame_buffer {
+ uint8_t *data; /**< Pointer to the data buffer */
+ size_t size; /**< Size of data in bytes */
+ void *priv; /**< Frame's private data */
+} aom_codec_frame_buffer_t;
+
+/*
+from:
+aom/aom_image.h
+*/
+#define AOM_IMAGE_ABI_VERSION (5) /**<\hideinitializer*/
+
+#define AOM_IMG_FMT_PLANAR 0x100 /**< Image is a planar format. */
+#define AOM_IMG_FMT_UV_FLIP 0x200 /**< V plane precedes U in memory. */
+/** 0x400 used to signal alpha channel, skipping for backwards compatibility. */
+#define AOM_IMG_FMT_HIGHBITDEPTH 0x800 /**< Image uses 16bit framebuffer. */
+
+/*!\brief List of supported image formats */
+typedef enum aom_img_fmt {
+ AOM_IMG_FMT_NONE,
+ AOM_IMG_FMT_YV12 =
+ AOM_IMG_FMT_PLANAR | AOM_IMG_FMT_UV_FLIP | 1, /**< planar YVU */
+ AOM_IMG_FMT_I420 = AOM_IMG_FMT_PLANAR | 2,
+ AOM_IMG_FMT_AOMYV12 = AOM_IMG_FMT_PLANAR | AOM_IMG_FMT_UV_FLIP |
+ 3, /** < planar 4:2:0 format with aom color space */
+ AOM_IMG_FMT_AOMI420 = AOM_IMG_FMT_PLANAR | 4,
+ AOM_IMG_FMT_I422 = AOM_IMG_FMT_PLANAR | 5,
+ AOM_IMG_FMT_I444 = AOM_IMG_FMT_PLANAR | 6,
+ AOM_IMG_FMT_I42016 = AOM_IMG_FMT_I420 | AOM_IMG_FMT_HIGHBITDEPTH,
+ AOM_IMG_FMT_YV1216 = AOM_IMG_FMT_YV12 | AOM_IMG_FMT_HIGHBITDEPTH,
+ AOM_IMG_FMT_I42216 = AOM_IMG_FMT_I422 | AOM_IMG_FMT_HIGHBITDEPTH,
+ AOM_IMG_FMT_I44416 = AOM_IMG_FMT_I444 | AOM_IMG_FMT_HIGHBITDEPTH,
+} aom_img_fmt_t; /**< alias for enum aom_img_fmt */
+
+/*!\brief List of supported color primaries */
+typedef enum aom_color_primaries {
+ AOM_CICP_CP_RESERVED_0 = 0, /**< For future use */
+ AOM_CICP_CP_BT_709 = 1, /**< BT.709 */
+ AOM_CICP_CP_UNSPECIFIED = 2, /**< Unspecified */
+ AOM_CICP_CP_RESERVED_3 = 3, /**< For future use */
+ AOM_CICP_CP_BT_470_M = 4, /**< BT.470 System M (historical) */
+ AOM_CICP_CP_BT_470_B_G = 5, /**< BT.470 System B, G (historical) */
+ AOM_CICP_CP_BT_601 = 6, /**< BT.601 */
+ AOM_CICP_CP_SMPTE_240 = 7, /**< SMPTE 240 */
+ AOM_CICP_CP_GENERIC_FILM =
+ 8, /**< Generic film (color filters using illuminant C) */
+ AOM_CICP_CP_BT_2020 = 9, /**< BT.2020, BT.2100 */
+ AOM_CICP_CP_XYZ = 10, /**< SMPTE 428 (CIE 1921 XYZ) */
+ AOM_CICP_CP_SMPTE_431 = 11, /**< SMPTE RP 431-2 */
+ AOM_CICP_CP_SMPTE_432 = 12, /**< SMPTE EG 432-1 */
+ AOM_CICP_CP_RESERVED_13 = 13, /**< For future use (values 13 - 21) */
+ AOM_CICP_CP_EBU_3213 = 22, /**< EBU Tech. 3213-E */
+ AOM_CICP_CP_RESERVED_23 = 23 /**< For future use (values 23 - 255) */
+} aom_color_primaries_t; /**< alias for enum aom_color_primaries */
+
+/*!\brief List of supported transfer functions */
+typedef enum aom_transfer_characteristics {
+ AOM_CICP_TC_RESERVED_0 = 0, /**< For future use */
+ AOM_CICP_TC_BT_709 = 1, /**< BT.709 */
+ AOM_CICP_TC_UNSPECIFIED = 2, /**< Unspecified */
+ AOM_CICP_TC_RESERVED_3 = 3, /**< For future use */
+ AOM_CICP_TC_BT_470_M = 4, /**< BT.470 System M (historical) */
+ AOM_CICP_TC_BT_470_B_G = 5, /**< BT.470 System B, G (historical) */
+ AOM_CICP_TC_BT_601 = 6, /**< BT.601 */
+ AOM_CICP_TC_SMPTE_240 = 7, /**< SMPTE 240 M */
+ AOM_CICP_TC_LINEAR = 8, /**< Linear */
+ AOM_CICP_TC_LOG_100 = 9, /**< Logarithmic (100 : 1 range) */
+ AOM_CICP_TC_LOG_100_SQRT10 =
+ 10, /**< Logarithmic (100 * Sqrt(10) : 1 range) */
+ AOM_CICP_TC_IEC_61966 = 11, /**< IEC 61966-2-4 */
+ AOM_CICP_TC_BT_1361 = 12, /**< BT.1361 */
+ AOM_CICP_TC_SRGB = 13, /**< sRGB or sYCC*/
+ AOM_CICP_TC_BT_2020_10_BIT = 14, /**< BT.2020 10-bit systems */
+ AOM_CICP_TC_BT_2020_12_BIT = 15, /**< BT.2020 12-bit systems */
+ AOM_CICP_TC_SMPTE_2084 = 16, /**< SMPTE ST 2084, ITU BT.2100 PQ */
+ AOM_CICP_TC_SMPTE_428 = 17, /**< SMPTE ST 428 */
+ AOM_CICP_TC_HLG = 18, /**< BT.2100 HLG, ARIB STD-B67 */
+ AOM_CICP_TC_RESERVED_19 = 19 /**< For future use (values 19-255) */
+} aom_transfer_characteristics_t; /**< alias for enum aom_transfer_function */
+
+/*!\brief List of supported matrix coefficients */
+typedef enum aom_matrix_coefficients {
+ AOM_CICP_MC_IDENTITY = 0, /**< Identity matrix */
+ AOM_CICP_MC_BT_709 = 1, /**< BT.709 */
+ AOM_CICP_MC_UNSPECIFIED = 2, /**< Unspecified */
+ AOM_CICP_MC_RESERVED_3 = 3, /**< For future use */
+ AOM_CICP_MC_FCC = 4, /**< US FCC 73.628 */
+ AOM_CICP_MC_BT_470_B_G = 5, /**< BT.470 System B, G (historical) */
+ AOM_CICP_MC_BT_601 = 6, /**< BT.601 */
+ AOM_CICP_MC_SMPTE_240 = 7, /**< SMPTE 240 M */
+ AOM_CICP_MC_SMPTE_YCGCO = 8, /**< YCgCo */
+ AOM_CICP_MC_BT_2020_NCL =
+ 9, /**< BT.2020 non-constant luminance, BT.2100 YCbCr */
+ AOM_CICP_MC_BT_2020_CL = 10, /**< BT.2020 constant luminance */
+ AOM_CICP_MC_SMPTE_2085 = 11, /**< SMPTE ST 2085 YDzDx */
+ AOM_CICP_MC_CHROMAT_NCL =
+ 12, /**< Chromaticity-derived non-constant luminance */
+ AOM_CICP_MC_CHROMAT_CL = 13, /**< Chromaticity-derived constant luminance */
+ AOM_CICP_MC_ICTCP = 14, /**< BT.2100 ICtCp */
+ AOM_CICP_MC_RESERVED_15 = 15 /**< For future use (values 15-255) */
+} aom_matrix_coefficients_t;
+
+/*!\brief List of supported color range */
+typedef enum aom_color_range {
+ AOM_CR_STUDIO_RANGE = 0, /**< Y [16..235], UV [16..240] */
+ AOM_CR_FULL_RANGE = 1 /**< YUV/RGB [0..255] */
+} aom_color_range_t; /**< alias for enum aom_color_range */
+
+/*!\brief List of chroma sample positions */
+typedef enum aom_chroma_sample_position {
+ AOM_CSP_UNKNOWN = 0, /**< Unknown */
+ AOM_CSP_VERTICAL = 1, /**< Horizontally co-located with luma(0, 0)*/
+ /**< sample, between two vertical samples */
+ AOM_CSP_COLOCATED = 2, /**< Co-located with luma(0, 0) sample */
+ AOM_CSP_RESERVED = 3 /**< Reserved value */
+} aom_chroma_sample_position_t; /**< alias for enum aom_transfer_function */
+
+/*
+from:
+aom/aom_scale/yv12config.h
+*/
+typedef struct PIC_BUFFER_CONFIG_s {
+ union {
+ struct {
+ int y_width;
+ int uv_width;
+ };
+ int widths[2];
+ };
+ union {
+ struct {
+ int y_height;
+ int uv_height;
+ };
+ int heights[2];
+ };
+ union {
+ struct {
+ int y_crop_width;
+ int uv_crop_width;
+ };
+ int crop_widths[2];
+ };
+ union {
+ struct {
+ int y_crop_height;
+ int uv_crop_height;
+ };
+ int crop_heights[2];
+ };
+ union {
+ struct {
+ int y_stride;
+ int uv_stride;
+ };
+ int strides[2];
+ };
+ union {
+ struct {
+ uint8_t *y_buffer;
+ uint8_t *u_buffer;
+ uint8_t *v_buffer;
+ };
+ uint8_t *buffers[3];
+ };
+
+ // Indicate whether y_buffer, u_buffer, and v_buffer points to the internally
+ // allocated memory or external buffers.
+ int use_external_reference_buffers;
+ // This is needed to store y_buffer, u_buffer, and v_buffer when set reference
+ // uses an external refernece, and restore those buffer pointers after the
+ // external reference frame is no longer used.
+ uint8_t *store_buf_adr[3];
+
+ // If the frame is stored in a 16-bit buffer, this stores an 8-bit version
+ // for use in global motion detection. It is allocated on-demand.
+ uint8_t *y_buffer_8bit;
+ int buf_8bit_valid;
+
+ uint8_t *buffer_alloc;
+ size_t buffer_alloc_sz;
+ int border;
+ size_t frame_size;
+ int subsampling_x;
+ int subsampling_y;
+ unsigned int bit_depth;
+ aom_color_primaries_t color_primaries;
+ aom_transfer_characteristics_t transfer_characteristics;
+ aom_matrix_coefficients_t matrix_coefficients;
+ uint8_t monochrome;
+ aom_chroma_sample_position_t chroma_sample_position;
+ aom_color_range_t color_range;
+ int render_width;
+ int render_height;
+
+ int corrupted;
+ int flags;
+
+#ifdef AML
+ int32_t index;
+ int32_t decode_idx;
+ int32_t slice_type;
+ int32_t RefNum_L0;
+ int32_t RefNum_L1;
+ int32_t num_reorder_pic;
+ int32_t stream_offset;
+ uint8_t referenced;
+ uint8_t output_mark;
+ uint8_t recon_mark;
+ uint8_t output_ready;
+ uint8_t error_mark;
+ /**/
+ int32_t slice_idx;
+ /*buffer*/
+ uint32_t fgs_table_adr;
+#ifdef AOM_AV1_MMU
+ uint32_t header_adr;
+#endif
+#ifdef AOM_AV1_MMU_DW
+ uint32_t header_dw_adr;
+#endif
+ uint32_t mpred_mv_wr_start_addr;
+ uint32_t mc_y_adr;
+ uint32_t mc_u_v_adr;
+ int32_t mc_canvas_y;
+ int32_t mc_canvas_u_v;
+
+ int32_t lcu_total;
+ /**/
+ unsigned int order_hint;
+#endif
+#ifdef AML_DEVICE
+ int mv_buf_index;
+ unsigned long cma_alloc_addr;
+ int BUF_index;
+ int buf_size;
+ int comp_body_size;
+ unsigned int dw_y_adr;
+ unsigned int dw_u_v_adr;
+ int double_write_mode;
+ int y_canvas_index;
+ int uv_canvas_index;
+ int vf_ref;
+ struct canvas_config_s canvas_config[2];
+ char *aux_data_buf;
+ int aux_data_size;
+ u32 pts;
+ u64 pts64;
+ /* picture qos infomation*/
+ int max_qp;
+ int avg_qp;
+ int min_qp;
+ int max_skip;
+ int avg_skip;
+ int min_skip;
+ int max_mv;
+ int min_mv;
+ int avg_mv;
+#endif
+} PIC_BUFFER_CONFIG;
+
+/*
+from:
+common/blockd.h
+*/
+TYPEDEF enum {
+ KEY_FRAME = 0,
+ INTER_FRAME = 1,
+ INTRA_ONLY_FRAME = 2, // replaces intra-only
+ S_FRAME = 3,
+ FRAME_TYPES,
+} UENUM1BYTE(FRAME_TYPE);
+
+/*from:
+mv.h
+*/
+#ifdef ORI_CODE
+typedef struct mv32 {
+ int32_t row;
+ int32_t col;
+} MV32;
+#endif
+/*from:
+ aom_filter.h
+*/
+#define SUBPEL_BITS 4
+#define SUBPEL_MASK ((1 << SUBPEL_BITS) - 1)
+#define SUBPEL_SHIFTS (1 << SUBPEL_BITS)
+#define SUBPEL_TAPS 8
+
+#define SCALE_SUBPEL_BITS 10
+#define SCALE_SUBPEL_SHIFTS (1 << SCALE_SUBPEL_BITS)
+#define SCALE_SUBPEL_MASK (SCALE_SUBPEL_SHIFTS - 1)
+#define SCALE_EXTRA_BITS (SCALE_SUBPEL_BITS - SUBPEL_BITS)
+#define SCALE_EXTRA_OFF ((1 << SCALE_EXTRA_BITS) / 2)
+
+#define RS_SUBPEL_BITS 6
+#define RS_SUBPEL_MASK ((1 << RS_SUBPEL_BITS) - 1)
+#define RS_SCALE_SUBPEL_BITS 14
+#define RS_SCALE_SUBPEL_MASK ((1 << RS_SCALE_SUBPEL_BITS) - 1)
+#define RS_SCALE_EXTRA_BITS (RS_SCALE_SUBPEL_BITS - RS_SUBPEL_BITS)
+#define RS_SCALE_EXTRA_OFF (1 << (RS_SCALE_EXTRA_BITS - 1))
+
+/*from:
+scale.h
+*/
+#define SCALE_NUMERATOR 8
+
+#define REF_SCALE_SHIFT 14
+#define REF_NO_SCALE (1 << REF_SCALE_SHIFT)
+#define REF_INVALID_SCALE -1
+
+struct scale_factors {
+ int x_scale_fp; // horizontal fixed point scale factor
+ int y_scale_fp; // vertical fixed point scale factor
+ int x_step_q4;
+ int y_step_q4;
+
+ int (*scale_value_x)(int val, const struct scale_factors *sf);
+ int (*scale_value_y)(int val, const struct scale_factors *sf);
+#ifdef ORI_CODE
+ // convolve_fn_ptr[subpel_x != 0][subpel_y != 0][is_compound]
+ aom_convolve_fn_t convolve[2][2][2];
+ aom_highbd_convolve_fn_t highbd_convolve[2][2][2];
+#endif
+};
+
+#ifdef ORI_CODE
+MV32 av1_scale_mv(const MV *mv, int x, int y, const struct scale_factors *sf);
+#endif
+void av1_setup_scale_factors_for_frame(struct scale_factors *sf, int other_w,
+ int other_h, int this_w, int this_h);
+
+static inline int av1_is_valid_scale(const struct scale_factors *sf) {
+#ifdef ORI_CODE
+ assert(sf != NULL);
+#endif
+ return sf->x_scale_fp != REF_INVALID_SCALE &&
+ sf->y_scale_fp != REF_INVALID_SCALE;
+}
+
+static inline int av1_is_scaled(const struct scale_factors *sf) {
+#ifdef ORI_CODE
+ assert(sf != NULL);
+#endif
+ return av1_is_valid_scale(sf) &&
+ (sf->x_scale_fp != REF_NO_SCALE || sf->y_scale_fp != REF_NO_SCALE);
+}
+
+
+/*
+from:
+common/onyxc_int.h
+*/
+
+#define CDEF_MAX_STRENGTHS 16
+
+/* Constant values while waiting for the sequence header */
+#define FRAME_ID_LENGTH 15
+#define DELTA_FRAME_ID_LENGTH 14
+
+#define FRAME_CONTEXTS (FRAME_BUFFERS + 1)
+// Extra frame context which is always kept at default values
+#define FRAME_CONTEXT_DEFAULTS (FRAME_CONTEXTS - 1)
+#define PRIMARY_REF_BITS 3
+#define PRIMARY_REF_NONE 7
+
+#define NUM_PING_PONG_BUFFERS 2
+
+#define MAX_NUM_TEMPORAL_LAYERS 8
+#define MAX_NUM_SPATIAL_LAYERS 4
+/* clang-format off */
+// clang-format seems to think this is a pointer dereference and not a
+// multiplication.
+#define MAX_NUM_OPERATING_POINTS \
+ MAX_NUM_TEMPORAL_LAYERS * MAX_NUM_SPATIAL_LAYERS
+/* clang-format on*/
+
+// TODO(jingning): Turning this on to set up transform coefficient
+// processing timer.
+#define TXCOEFF_TIMER 0
+#define TXCOEFF_COST_TIMER 0
+
+TYPEDEF enum {
+ SINGLE_REFERENCE = 0,
+ COMPOUND_REFERENCE = 1,
+ REFERENCE_MODE_SELECT = 2,
+ REFERENCE_MODES = 3,
+} UENUM1BYTE(REFERENCE_MODE);
+
+TYPEDEF enum {
+ /**
+ * Frame context updates are disabled
+ */
+ REFRESH_FRAME_CONTEXT_DISABLED,
+ /**
+ * Update frame context to values resulting from backward probability
+ * updates based on entropy/counts in the decoded frame
+ */
+ REFRESH_FRAME_CONTEXT_BACKWARD,
+} UENUM1BYTE(REFRESH_FRAME_CONTEXT_MODE);
+
+#define MFMV_STACK_SIZE 3
+
+#ifdef AML
+#define MV_REF_SIZE 8
+#endif
+
+#ifdef ORI_CODE
+typedef struct {
+ int_mv mfmv0;
+ uint8_t ref_frame_offset;
+} TPL_MV_REF;
+typedef struct {
+ int_mv mv;
+ MV_REFERENCE_FRAME ref_frame;
+} MV_REF;
+#endif
+
+typedef struct RefCntBuffer_s {
+ // For a RefCntBuffer, the following are reference-holding variables:
+ // - cm->ref_frame_map[]
+ // - cm->cur_frame
+ // - cm->scaled_ref_buf[] (encoder only)
+ // - cm->next_ref_frame_map[] (decoder only)
+ // - pbi->output_frame_index[] (decoder only)
+ // With that definition, 'ref_count' is the number of reference-holding
+ // variables that are currently referencing this buffer.
+ // For example:
+ // - suppose this buffer is at index 'k' in the buffer pool, and
+ // - Total 'n' of the variables / array elements above have value 'k' (that
+ // is, they are pointing to buffer at index 'k').
+ // Then, pool->frame_bufs[k].ref_count = n.
+ int ref_count;
+
+ unsigned int order_hint;
+ unsigned int ref_order_hints[INTER_REFS_PER_FRAME];
+
+ int intra_only;
+ int segmentation_enabled;
+ unsigned int segment_feature[8];
+#ifdef AML
+ int segmentation_update_map;
+ int prev_segmentation_enabled;
+ int seg_mi_rows;
+ int seg_mi_cols;
+
+ unsigned int seg_lf_info_y[8];
+ unsigned int seg_lf_info_c[8];
+ int8_t ref_deltas[REF_FRAMES];
+ int8_t mode_deltas[MAX_MODE_LF_DELTAS];
+#endif
+ //MV_REF *mvs;
+ uint8_t *seg_map;
+#ifdef ORI_CODE
+ struct segmentation seg;
+#endif
+
+ int mi_rows;
+ int mi_cols;
+ // Width and height give the size of the buffer (before any upscaling, unlike
+ // the sizes that can be derived from the buf structure)
+ int width;
+ int height;
+#ifdef ORI_CODE
+ WarpedMotionParams global_motion[REF_FRAMES];
+#endif
+ int showable_frame; // frame can be used as show existing frame in future
+ uint8_t film_grain_params_present;
+#ifdef ORI_CODE
+ aom_film_grain_t film_grain_params;
+#endif
+#ifdef AML
+ int dec_width;
+ uint8_t film_grain_reg_valid;
+ uint32_t film_grain_reg[FILM_GRAIN_REG_SIZE];
+#endif
+ aom_codec_frame_buffer_t raw_frame_buffer;
+ PIC_BUFFER_CONFIG buf;
+#ifdef ORI_CODE
+ hash_table hash_table;
+#endif
+ FRAME_TYPE frame_type;
+
+ // This is only used in the encoder but needs to be indexed per ref frame
+ // so it's extremely convenient to keep it here.
+#ifdef ORI_CODE
+ int interp_filter_selected[SWITCHABLE];
+#endif
+ // Inter frame reference frame delta for loop filter
+#ifndef AML
+ int8_t ref_deltas[REF_FRAMES];
+#endif
+#ifdef ORI_CODE
+ // 0 = ZERO_MV, MV
+ int8_t mode_deltas[MAX_MODE_LF_DELTAS];
+
+ FRAME_CONTEXT frame_context;
+#endif
+} RefCntBuffer;
+
+typedef struct BufferPool_s {
+// Protect BufferPool from being accessed by several FrameWorkers at
+// the same time during frame parallel decode.
+// TODO(hkuang): Try to use atomic variable instead of locking the whole pool.
+// TODO(wtc): Remove this. See
+// https://chromium-review.googlesource.com/c/webm/libvpx/+/560630.
+#if CONFIG_MULTITHREAD
+ pthread_mutex_t pool_mutex;
+#endif
+
+ // Private data associated with the frame buffer callbacks.
+ void *cb_priv;
+#ifdef ORI_CODE
+ aom_get_frame_buffer_cb_fn_t get_fb_cb;
+ aom_release_frame_buffer_cb_fn_t release_fb_cb;
+#endif
+ RefCntBuffer frame_bufs[FRAME_BUFFERS];
+
+#ifdef ORI_CODE
+ // Frame buffers allocated internally by the codec.
+ InternalFrameBufferList int_frame_buffers;
+#endif
+#ifdef AML_DEVICE
+ spinlock_t lock;
+#endif
+} BufferPool;
+
+typedef struct {
+ int cdef_pri_damping;
+ int cdef_sec_damping;
+ int nb_cdef_strengths;
+ int cdef_strengths[CDEF_MAX_STRENGTHS];
+ int cdef_uv_strengths[CDEF_MAX_STRENGTHS];
+ int cdef_bits;
+} CdefInfo;
+
+typedef struct {
+ int delta_q_present_flag;
+ // Resolution of delta quant
+ int delta_q_res;
+ int delta_lf_present_flag;
+ // Resolution of delta lf level
+ int delta_lf_res;
+ // This is a flag for number of deltas of loop filter level
+ // 0: use 1 delta, for y_vertical, y_horizontal, u, and v
+ // 1: use separate deltas for each filter level
+ int delta_lf_multi;
+} DeltaQInfo;
+
+typedef struct {
+ int enable_order_hint; // 0 - disable order hint, and related tools
+ int order_hint_bits_minus_1; // dist_wtd_comp, ref_frame_mvs,
+ // frame_sign_bias
+ // if 0, enable_dist_wtd_comp and
+ // enable_ref_frame_mvs must be set as 0.
+ int enable_dist_wtd_comp; // 0 - disable dist-wtd compound modes
+ // 1 - enable it
+ int enable_ref_frame_mvs; // 0 - disable ref frame mvs
+ // 1 - enable it
+} OrderHintInfo;
+
+// Sequence header structure.
+// Note: All syntax elements of sequence_header_obu that need to be
+// bit-identical across multiple sequence headers must be part of this struct,
+// so that consistency is checked by are_seq_headers_consistent() function.
+typedef struct SequenceHeader {
+ int num_bits_width;
+ int num_bits_height;
+ int max_frame_width;
+ int max_frame_height;
+ uint8_t frame_id_numbers_present_flag;
+ int frame_id_length;
+ int delta_frame_id_length;
+ BLOCK_SIZE2 sb_size; // Size of the superblock used for this frame
+ int mib_size; // Size of the superblock in units of MI blocks
+ int mib_size_log2; // Log 2 of above.
+
+ OrderHintInfo order_hint_info;
+
+ uint8_t force_screen_content_tools; // 0 - force off
+ // 1 - force on
+ // 2 - adaptive
+ uint8_t still_picture; // Video is a single frame still picture
+ uint8_t reduced_still_picture_hdr; // Use reduced header for still picture
+ uint8_t force_integer_mv; // 0 - Don't force. MV can use subpel
+ // 1 - force to integer
+ // 2 - adaptive
+ uint8_t enable_filter_intra; // enables/disables filterintra
+ uint8_t enable_intra_edge_filter; // enables/disables edge upsampling
+ uint8_t enable_interintra_compound; // enables/disables interintra_compound
+ uint8_t enable_masked_compound; // enables/disables masked compound
+ uint8_t enable_dual_filter; // 0 - disable dual interpolation filter
+ // 1 - enable vert/horz filter selection
+ uint8_t enable_warped_motion; // 0 - disable warp for the sequence
+ // 1 - enable warp for the sequence
+ uint8_t enable_superres; // 0 - Disable superres for the sequence
+ // and no frame level superres flag
+ // 1 - Enable superres for the sequence
+ // enable per-frame superres flag
+ uint8_t enable_cdef; // To turn on/off CDEF
+ uint8_t enable_restoration; // To turn on/off loop restoration
+ BITSTREAM_PROFILE profile;
+
+ // Operating point info.
+ int operating_points_cnt_minus_1;
+ int operating_point_idc[MAX_NUM_OPERATING_POINTS];
+ uint8_t display_model_info_present_flag;
+ uint8_t decoder_model_info_present_flag;
+ AV1_LEVEL seq_level_idx[MAX_NUM_OPERATING_POINTS];
+ uint8_t tier[MAX_NUM_OPERATING_POINTS]; // seq_tier in the spec. One bit: 0
+ // or 1.
+
+ // Color config.
+ aom_bit_depth_t bit_depth; // AOM_BITS_8 in profile 0 or 1,
+ // AOM_BITS_10 or AOM_BITS_12 in profile 2 or 3.
+ uint8_t use_highbitdepth; // If true, we need to use 16bit frame buffers.
+ uint8_t monochrome; // Monochorme video
+ aom_color_primaries_t color_primaries;
+ aom_transfer_characteristics_t transfer_characteristics;
+ aom_matrix_coefficients_t matrix_coefficients;
+ int color_range;
+ int subsampling_x; // Chroma subsampling for x
+ int subsampling_y; // Chroma subsampling for y
+ aom_chroma_sample_position_t chroma_sample_position;
+ uint8_t separate_uv_delta_q;
+ uint8_t film_gry_dequant_QTXain_params_present;
+} SequenceHeader;
+
+typedef struct {
+ int skip_mode_allowed;
+ int skip_mode_flag;
+ int ref_frame_idx_0;
+ int ref_frame_idx_1;
+} SkipModeInfo;
+
+typedef struct {
+ FRAME_TYPE frame_type;
+ REFERENCE_MODE reference_mode;
+
+ unsigned int order_hint;
+ unsigned int frame_number;
+ SkipModeInfo skip_mode_info;
+ int refresh_frame_flags; // Which ref frames are overwritten by this frame
+ int frame_refs_short_signaling;
+} CurrentFrame;
+
+typedef struct AV1_Common_s {
+ CurrentFrame current_frame;
+ struct aom_internal_error_info error;
+ int width;
+ int height;
+ int render_width;
+ int render_height;
+ int timing_info_present;
+ aom_timing_info_t timing_info;
+ int buffer_removal_time_present;
+ aom_dec_model_info_t buffer_model;
+ aom_dec_model_op_parameters_t op_params[MAX_NUM_OPERATING_POINTS + 1];
+ aom_op_timing_info_t op_frame_timing[MAX_NUM_OPERATING_POINTS + 1];
+ uint32_t frame_presentation_time;
+
+ int context_update_tile_id;
+#ifdef SUPPORT_SCALE_FACTOR
+ // Scale of the current frame with respect to itself.
+ struct scale_factors sf_identity;
+#endif
+ RefCntBuffer *prev_frame;
+
+ // TODO(hkuang): Combine this with cur_buf in macroblockd.
+ RefCntBuffer *cur_frame;
+
+ // For encoder, we have a two-level mapping from reference frame type to the
+ // corresponding buffer in the buffer pool:
+ // * 'remapped_ref_idx[i - 1]' maps reference type 'i' (range: LAST_FRAME ...
+ // EXTREF_FRAME) to a remapped index 'j' (in range: 0 ... REF_FRAMES - 1)
+ // * Later, 'cm->ref_frame_map[j]' maps the remapped index 'j' to a pointer to
+ // the reference counted buffer structure RefCntBuffer, taken from the buffer
+ // pool cm->buffer_pool->frame_bufs.
+ //
+ // LAST_FRAME, ..., EXTREF_FRAME
+ // | |
+ // v v
+ // remapped_ref_idx[LAST_FRAME - 1], ..., remapped_ref_idx[EXTREF_FRAME - 1]
+ // | |
+ // v v
+ // ref_frame_map[], ..., ref_frame_map[]
+ //
+ // Note: INTRA_FRAME always refers to the current frame, so there's no need to
+ // have a remapped index for the same.
+ int remapped_ref_idx[REF_FRAMES];
+
+#ifdef SUPPORT_SCALE_FACTOR
+ struct scale_factors ref_scale_factors[REF_FRAMES];
+#endif
+ // For decoder, ref_frame_map[i] maps reference type 'i' to a pointer to
+ // the buffer in the buffer pool 'cm->buffer_pool.frame_bufs'.
+ // For encoder, ref_frame_map[j] (where j = remapped_ref_idx[i]) maps
+ // remapped reference index 'j' (that is, original reference type 'i') to
+ // a pointer to the buffer in the buffer pool 'cm->buffer_pool.frame_bufs'.
+ RefCntBuffer *ref_frame_map[REF_FRAMES];
+
+ // Prepare ref_frame_map for the next frame.
+ // Only used in frame parallel decode.
+ RefCntBuffer *next_ref_frame_map[REF_FRAMES];
+#ifdef AML
+ RefCntBuffer *next_used_ref_frame_map[REF_FRAMES];
+#endif
+ FRAME_TYPE last_frame_type; /* last frame's frame type for motion search.*/
+
+ int show_frame;
+ int showable_frame; // frame can be used as show existing frame in future
+ int show_existing_frame;
+
+ uint8_t disable_cdf_update;
+ int allow_high_precision_mv;
+ uint8_t cur_frame_force_integer_mv; // 0 the default in AOM, 1 only integer
+
+ uint8_t allow_screen_content_tools;
+ int allow_intrabc;
+ int allow_warped_motion;
+
+ // MBs, mb_rows/cols is in 16-pixel units; mi_rows/cols is in
+ // MB_MODE_INFO (8-pixel) units.
+ int MBs;
+ int mb_rows, mi_rows;
+ int mb_cols, mi_cols;
+ int mi_stride;
+
+ /* profile settings */
+ TX_MODE tx_mode;
+
+#if CONFIG_ENTROPY_STATS
+ int coef_cdf_category;
+#endif
+
+ int base_qindex;
+ int y_dc_delta_q;
+ int u_dc_delta_q;
+ int v_dc_delta_q;
+ int u_ac_delta_q;
+ int v_ac_delta_q;
+
+#ifdef ORI_CODE
+ // The dequantizers below are true dequantizers used only in the
+ // dequantization process. They have the same coefficient
+ // shift/scale as TX.
+ int16_t y_dequant_QTX[MAX_SEGMENTS][2];
+ int16_t u_dequant_QTX[MAX_SEGMENTS][2];
+ int16_t v_dequant_QTX[MAX_SEGMENTS][2];
+
+ // Global quant matrix tables
+ const qm_val_t *giqmatrix[NUM_QM_LEVELS][3][TX_SIZES_ALL];
+ const qm_val_t *gqmatrix[NUM_QM_LEVELS][3][TX_SIZES_ALL];
+
+ // Local quant matrix tables for each frame
+ const qm_val_t *y_iqmatrix[MAX_SEGMENTS][TX_SIZES_ALL];
+ const qm_val_t *u_iqmatrix[MAX_SEGMENTS][TX_SIZES_ALL];
+ const qm_val_t *v_iqmatrix[MAX_SEGMENTS][TX_SIZES_ALL];
+#endif
+ // Encoder
+ int using_qmatrix;
+ int qm_y;
+ int qm_u;
+ int qm_v;
+ int min_qmlevel;
+ int max_qmlevel;
+ int use_quant_b_adapt;
+
+ /* We allocate a MB_MODE_INFO struct for each macroblock, together with
+ an extra row on top and column on the left to simplify prediction. */
+ int mi_alloc_size;
+
+#ifdef ORI_CODE
+ MB_MODE_INFO *mip; /* Base of allocated array */
+ MB_MODE_INFO *mi; /* Corresponds to upper left visible macroblock */
+
+ // TODO(agrange): Move prev_mi into encoder structure.
+ // prev_mip and prev_mi will only be allocated in encoder.
+ MB_MODE_INFO *prev_mip; /* MB_MODE_INFO array 'mip' from last decoded frame */
+ MB_MODE_INFO *prev_mi; /* 'mi' from last frame (points into prev_mip) */
+
+ // Separate mi functions between encoder and decoder.
+ int (*alloc_mi)(struct AV1Common *cm, int mi_size);
+ void (*free_mi)(struct AV1Common *cm);
+ void (*setup_mi)(struct AV1Common *cm);
+
+ // Grid of pointers to 8x8 MB_MODE_INFO structs. Any 8x8 not in the visible
+ // area will be NULL.
+ MB_MODE_INFO **mi_grid_base;
+ MB_MODE_INFO **mi_grid_visible;
+ MB_MODE_INFO **prev_mi_grid_base;
+ MB_MODE_INFO **prev_mi_grid_visible;
+#endif
+ // Whether to use previous frames' motion vectors for prediction.
+ int allow_ref_frame_mvs;
+
+ uint8_t *last_frame_seg_map;
+
+#ifdef ORI_CODE
+ InterpFilter interp_filter;
+#endif
+ int switchable_motion_mode;
+#ifdef ORI_CODE
+ loop_filter_info_n lf_info;
+#endif
+ // The denominator of the superres scale; the numerator is fixed.
+ uint8_t superres_scale_denominator;
+ int superres_upscaled_width;
+ int superres_upscaled_height;
+
+#ifdef ORI_CODE
+ RestorationInfo rst_info[MAX_MB_PLANE];
+#endif
+ // Pointer to a scratch buffer used by self-guided restoration
+ int32_t *rst_tmpbuf;
+#ifdef ORI_CODE
+ RestorationLineBuffers *rlbs;
+#endif
+ // Output of loop restoration
+ PIC_BUFFER_CONFIG rst_frame;
+
+ // Flag signaling how frame contexts should be updated at the end of
+ // a frame decode
+ REFRESH_FRAME_CONTEXT_MODE refresh_frame_context;
+
+ int ref_frame_sign_bias[REF_FRAMES]; /* Two state 0, 1 */
+
+#ifdef ORI_CODE
+ struct loopfilter lf;
+ struct segmentation seg;
+#endif
+
+ int coded_lossless; // frame is fully lossless at the coded resolution.
+ int all_lossless; // frame is fully lossless at the upscaled resolution.
+
+ int reduced_tx_set_used;
+
+#ifdef ORI_CODE
+ // Context probabilities for reference frame prediction
+ MV_REFERENCE_FRAME comp_fwd_ref[FWD_REFS];
+ MV_REFERENCE_FRAME comp_bwd_ref[BWD_REFS];
+
+ FRAME_CONTEXT *fc; /* this frame entropy */
+ FRAME_CONTEXT *default_frame_context;
+#endif
+ int primary_ref_frame;
+
+ int error_resilient_mode;
+
+ int tile_cols, tile_rows;
+
+ int max_tile_width_sb;
+ int min_log2_tile_cols;
+ int max_log2_tile_cols;
+ int max_log2_tile_rows;
+ int min_log2_tile_rows;
+ int min_log2_tiles;
+ int max_tile_height_sb;
+ int uniform_tile_spacing_flag;
+ int log2_tile_cols; // only valid for uniform tiles
+ int log2_tile_rows; // only valid for uniform tiles
+ int tile_col_start_sb[MAX_TILE_COLS + 1]; // valid for 0 <= i <= tile_cols
+ int tile_row_start_sb[MAX_TILE_ROWS + 1]; // valid for 0 <= i <= tile_rows
+ int tile_width, tile_height; // In MI units
+ int min_inner_tile_width; // min width of non-rightmost tile
+
+ unsigned int large_scale_tile;
+ unsigned int single_tile_decoding;
+
+ int byte_alignment;
+ int skip_loop_filter;
+ int skip_film_grain;
+
+ // External BufferPool passed from outside.
+ BufferPool *buffer_pool;
+
+#ifdef ORI_CODE
+ PARTITION_CONTEXT **above_seg_context;
+ ENTROPY_CONTEXT **above_context[MAX_MB_PLANE];
+ TXFM_CONTEXT **above_txfm_context;
+ WarpedMotionParams global_motion[REF_FRAMES];
+ aom_film_grain_t film_grain_params;
+
+ CdefInfo cdef_info;
+ DeltaQInfo delta_q_info; // Delta Q and Delta LF parameters
+#endif
+ int num_tg;
+ SequenceHeader seq_params;
+ int current_frame_id;
+ int ref_frame_id[REF_FRAMES];
+ int valid_for_referencing[REF_FRAMES];
+#ifdef ORI_CODE
+ TPL_MV_REF *tpl_mvs;
+#endif
+ int tpl_mvs_mem_size;
+ // TODO(jingning): This can be combined with sign_bias later.
+ int8_t ref_frame_side[REF_FRAMES];
+
+ int is_annexb;
+
+ int temporal_layer_id;
+ int spatial_layer_id;
+ unsigned int number_temporal_layers;
+ unsigned int number_spatial_layers;
+ int num_allocated_above_context_mi_col;
+ int num_allocated_above_contexts;
+ int num_allocated_above_context_planes;
+
+#if TXCOEFF_TIMER
+ int64_t cum_txcoeff_timer;
+ int64_t txcoeff_timer;
+ int txb_count;
+#endif
+
+#if TXCOEFF_COST_TIMER
+ int64_t cum_txcoeff_cost_timer;
+ int64_t txcoeff_cost_timer;
+ int64_t txcoeff_cost_count;
+#endif
+ const cfg_options_t *options;
+ int is_decoding;
+#ifdef AML
+ int mv_ref_offset[MV_REF_SIZE][REF_FRAMES];
+ int mv_ref_id[MV_REF_SIZE];
+ unsigned char mv_cal_tpl_mvs[MV_REF_SIZE];
+ int mv_ref_id_index;
+ int prev_fb_idx;
+ int new_fb_idx;
+ int32_t dec_width;
+#endif
+#ifdef AML_DEVICE
+ int cur_fb_idx_mmu;
+#ifdef AOM_AV1_MMU_DW
+ int cur_fb_idx_mmu_dw;
+#endif
+ int current_video_frame;
+ int use_prev_frame_mvs;
+ int frame_type;
+ int intra_only;
+ struct RefCntBuffer_s frame_refs[INTER_REFS_PER_FRAME];
+
+#endif
+} AV1_COMMON;
+
+
+/*
+from:
+ decoder/decoder.h
+*/
+
+typedef struct EXTERNAL_REFERENCES {
+ PIC_BUFFER_CONFIG refs[MAX_EXTERNAL_REFERENCES];
+ int num;
+} EXTERNAL_REFERENCES;
+
+typedef struct AV1Decoder {
+ //DECLARE_ALIGNED(32, MACROBLOCKD, mb);
+
+ //DECLARE_ALIGNED(32, AV1_COMMON, common);
+ AV1_COMMON common;
+
+#ifdef ORI_CODE
+ AVxWorker lf_worker;
+ AV1LfSync lf_row_sync;
+ AV1LrSync lr_row_sync;
+ AV1LrStruct lr_ctxt;
+ AVxWorker *tile_workers;
+ int num_workers;
+ DecWorkerData *thread_data;
+ ThreadData td;
+ TileDataDec *tile_data;
+ int allocated_tiles;
+ TileBufferDec tile_buffers[MAX_TILE_ROWS][MAX_TILE_COLS];
+ AV1DecTileMT tile_mt_info;
+#endif
+
+ // Each time the decoder is called, we expect to receive a full temporal unit.
+ // This can contain up to one shown frame per spatial layer in the current
+ // operating point (note that some layers may be entirely omitted).
+ // If the 'output_all_layers' option is true, we save all of these shown
+ // frames so that they can be returned to the application. If the
+ // 'output_all_layers' option is false, then we only output one image per
+ // temporal unit.
+ //
+ // Note: The saved buffers are released at the start of the next time the
+ // application calls aom_codec_decode().
+ int output_all_layers;
+ RefCntBuffer *output_frames[MAX_NUM_SPATIAL_LAYERS];
+ size_t num_output_frames; // How many frames are queued up so far?
+
+ // In order to properly support random-access decoding, we need
+ // to behave slightly differently for the very first frame we decode.
+ // So we track whether this is the first frame or not.
+ int decoding_first_frame;
+
+ int allow_lowbitdepth;
+ int max_threads;
+ int inv_tile_order;
+ int need_resync; // wait for key/intra-only frame.
+ int hold_ref_buf; // Boolean: whether we are holding reference buffers in
+ // common.next_ref_frame_map.
+ int reset_decoder_state;
+
+ int tile_size_bytes;
+ int tile_col_size_bytes;
+ int dec_tile_row, dec_tile_col; // always -1 for non-VR tile encoding
+#if CONFIG_ACCOUNTING
+ int acct_enabled;
+ Accounting accounting;
+#endif
+ int tg_size; // Number of tiles in the current tilegroup
+ int tg_start; // First tile in the current tilegroup
+ int tg_size_bit_offset;
+ int sequence_header_ready;
+ int sequence_header_changed;
+#if CONFIG_INSPECTION
+ aom_inspect_cb inspect_cb;
+ void *inspect_ctx;
+#endif
+ int operating_point;
+ int current_operating_point;
+ int seen_frame_header;
+
+ // State if the camera frame header is already decoded while
+ // large_scale_tile = 1.
+ int camera_frame_header_ready;
+ size_t frame_header_size;
+#ifdef ORI_CODE
+ DataBuffer obu_size_hdr;
+#endif
+ int output_frame_width_in_tiles_minus_1;
+ int output_frame_height_in_tiles_minus_1;
+ int tile_count_minus_1;
+ uint32_t coded_tile_data_size;
+ unsigned int ext_tile_debug; // for ext-tile software debug & testing
+ unsigned int row_mt;
+ EXTERNAL_REFERENCES ext_refs;
+ PIC_BUFFER_CONFIG tile_list_outbuf;
+
+#ifdef ORI_CODE
+ CB_BUFFER *cb_buffer_base;
+#endif
+ int cb_buffer_alloc_size;
+
+ int allocated_row_mt_sync_rows;
+
+#if CONFIG_MULTITHREAD
+ pthread_mutex_t *row_mt_mutex_;
+ pthread_cond_t *row_mt_cond_;
+#endif
+
+#ifdef ORI_CODE
+ AV1DecRowMTInfo frame_row_mt_info;
+#endif
+
+#ifdef AML
+ unsigned char pred_inter_read_enable;
+ int cur_obu_type;
+ int decode_idx;
+ int bufmgr_proc_count;
+ int obu_frame_frame_head_come_after_tile;
+ uint32_t frame_width;
+ uint32_t frame_height;
+ BuffInfo_t* work_space_buf;
+ buff_t* mc_buf;
+ //unsigned short *rpm_ptr;
+ void *private_data;
+#endif
+} AV1Decoder;
+
+#define RPM_BEGIN 0x200
+#define RPM_END 0x280
+
+typedef union param_u {
+ struct {
+ unsigned short data[RPM_END - RPM_BEGIN];
+ } l;
+ struct {
+ /*sequence head*/
+ unsigned short profile;
+ unsigned short still_picture;
+ unsigned short reduced_still_picture_hdr;
+ unsigned short decoder_model_info_present_flag;
+ unsigned short max_frame_width;
+ unsigned short max_frame_height;
+ unsigned short frame_id_numbers_present_flag;
+ unsigned short delta_frame_id_length;
+ unsigned short frame_id_length;
+ unsigned short order_hint_bits_minus_1;
+ unsigned short enable_order_hint;
+ unsigned short enable_dist_wtd_comp;
+ unsigned short enable_ref_frame_mvs;
+
+ /*frame head*/
+ unsigned short show_existing_frame;
+ unsigned short frame_type;
+ unsigned short show_frame;
+ unsigned short error_resilient_mode;
+ unsigned short refresh_frame_flags;
+ unsigned short showable_frame;
+ unsigned short current_frame_id;
+ unsigned short frame_size_override_flag;
+ unsigned short order_hint;
+ unsigned short primary_ref_frame;
+ unsigned short frame_refs_short_signaling;
+ unsigned short frame_width;
+ unsigned short dec_frame_width;
+ unsigned short frame_width_scaled;
+ unsigned short frame_height;
+ unsigned short reference_mode;
+ unsigned short allow_ref_frame_mvs;
+ unsigned short superres_scale_denominator;
+ unsigned short lst_ref;
+ unsigned short gld_ref;
+ unsigned short existing_frame_idx;
+
+ unsigned short remapped_ref_idx[INTER_REFS_PER_FRAME];
+ unsigned short delta_frame_id_minus_1[INTER_REFS_PER_FRAME];
+ unsigned short ref_order_hint[REF_FRAMES];
+ /*other not in reference*/
+ unsigned short bit_depth;
+ unsigned short seq_flags;
+ unsigned short update_parameters;
+ unsigned short film_grain_params_ref_idx;
+
+ /*loop_filter & segmentation*/
+ unsigned short loop_filter_sharpness_level;
+ unsigned short loop_filter_mode_ref_delta_enabled;
+ unsigned short loop_filter_ref_deltas_0;
+ unsigned short loop_filter_ref_deltas_1;
+ unsigned short loop_filter_ref_deltas_2;
+ unsigned short loop_filter_ref_deltas_3;
+ unsigned short loop_filter_ref_deltas_4;
+ unsigned short loop_filter_ref_deltas_5;
+ unsigned short loop_filter_ref_deltas_6;
+ unsigned short loop_filter_ref_deltas_7;
+ unsigned short loop_filter_mode_deltas_0;
+ unsigned short loop_filter_mode_deltas_1;
+ unsigned short loop_filter_level_0;
+ unsigned short loop_filter_level_1;
+ unsigned short loop_filter_level_u;
+ unsigned short loop_filter_level_v;
+
+ unsigned short segmentation_enabled;
+ /*
+ SEG_LVL_ALT_LF_Y_V feature_enable: seg_lf_info_y[bit7]
+ SEG_LVL_ALT_LF_Y_V data: seg_lf_info_y[bit0~6]
+ SEG_LVL_ALT_LF_Y_H feature enable: seg_lf_info_y[bit15]
+ SEG_LVL_ALT_LF_Y_H data: seg_lf_info_y[bit8~14]
+ */
+ unsigned short seg_lf_info_y[8];
+ /*
+ SEG_LVL_ALT_LF_U feature_enable: seg_lf_info_y[bit7]
+ SEG_LVL_ALT_LF_U data: seg_lf_info_y[bit0~6]
+ SEG_LVL_ALT_LF_V feature enable: seg_lf_info_y[bit15]
+ SEG_LVL_ALT_LF_V data: seg_lf_info_y[bit8~14]
+ */
+ unsigned short seg_lf_info_c[8];
+
+ /*ucode end*/
+ /*other*/
+ unsigned short enable_superres;
+
+ /*seqence not use*/
+ unsigned short operating_points_cnt_minus_1;
+ unsigned short operating_point_idc[MAX_NUM_OPERATING_POINTS];
+ unsigned short seq_level_idx[MAX_NUM_OPERATING_POINTS];
+ unsigned short decoder_model_param_present_flag[MAX_NUM_OPERATING_POINTS];
+ unsigned short timing_info_present;
+ /*frame head not use*/
+ unsigned short display_frame_id;
+ unsigned short frame_presentation_time;
+ unsigned short buffer_removal_time_present;
+ unsigned short op_frame_timing[MAX_NUM_OPERATING_POINTS + 1];
+ unsigned short valid_ref_frame_bits;
+
+ } p;
+}param_t;
+
+PIC_BUFFER_CONFIG *av1_get_ref_frame_spec_buf(
+ const AV1_COMMON *const cm, const MV_REFERENCE_FRAME ref_frame);
+
+int av1_bufmgr_process(AV1Decoder *pbi, union param_u *params,
+ unsigned char new_compressed_data, int obu_type);
+
+struct scale_factors *av1_get_ref_scale_factors(
+ AV1_COMMON *const cm, const MV_REFERENCE_FRAME ref_frame);
+
+void av1_set_next_ref_frame_map(AV1Decoder *pbi);
+
+unsigned int av1_get_next_used_ref_info(
+ const AV1_COMMON *const cm, int i);
+
+void av1_release_buf(AV1Decoder *pbi, RefCntBuffer *const buf);
+
+int av1_bufmgr_postproc(AV1Decoder *pbi, unsigned char frame_decoded);
+
+AV1Decoder *av1_decoder_create(BufferPool *const pool);
+
+unsigned char av1_frame_is_inter(const AV1_COMMON *const cm);
+
+RefCntBuffer *av1_get_primary_ref_frame_buf(
+ const AV1_COMMON *const cm);
+
+void av1_raw_write_image(AV1Decoder *pbi, PIC_BUFFER_CONFIG *sd);
+
+#if 1
+#define lock_buffer_pool(pool, flags) \
+ spin_lock_irqsave(&pool->lock, flags)
+
+#define unlock_buffer_pool(pool, flags) \
+ spin_unlock_irqrestore(&pool->lock, flags)
+#else
+#define lock_buffer_pool(pool, flags) flags=1;
+
+#define unlock_buffer_pool(pool, flags) flags=0;
+
+#endif
+
+#define VP9_DEBUG_BUFMGR 0x01
+#define VP9_DEBUG_BUFMGR_MORE 0x02
+#define VP9_DEBUG_BUFMGR_DETAIL 0x04
+#define VP9_DEBUG_OUT_PTS 0x10
+#define AOM_DEBUG_HW_MORE 0x20
+#define AOM_DEBUG_VFRAME 0x40
+#define AOM_DEBUG_PRINT_LIST_INFO 0x80
+#define AOM_AV1_DEBUG_SEND_PARAM_WITH_REG 0x100
+#define VP9_DEBUG_IGNORE_VF_REF 0x200
+#define VP9_DEBUG_DBG_LF_PRINT 0x400
+#define VP9_DEBUG_REG 0x800
+#define AOM_DEBUG_BUFMGR_ONLY 0x1000
+#define AOM_DEBUG_AUX_DATA 0x2000
+#define VP9_DEBUG_QOS_INFO 0x4000
+#define AOM_DEBUG_DW_DISP_MAIN 0x8000
+#define VP9_DEBUG_DIS_LOC_ERROR_PROC 0x10000
+#define VP9_DEBUG_DIS_SYS_ERROR_PROC 0x20000
+#define VP9_DEBUG_DUMP_PIC_LIST 0x40000
+#define VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC 0x80000
+#define VP9_DEBUG_NO_TRIGGER_FRAME 0x100000
+#define VP9_DEBUG_LOAD_UCODE_FROM_FILE 0x200000
+#define VP9_DEBUG_FORCE_SEND_AGAIN 0x400000
+#define VP9_DEBUG_DUMP_DATA 0x800000
+#define VP9_DEBUG_CACHE 0x1000000
+#define VP9_DEBUG_CACHE_HIT_RATE 0x2000000
+#define IGNORE_PARAM_FROM_CONFIG 0x8000000
+#if 1
+/*def MULTI_INSTANCE_SUPPORT*/
+#define PRINT_FLAG_ERROR 0x0
+#define PRINT_FLAG_V4L_DETAIL 0x10000000
+#define PRINT_FLAG_VDEC_STATUS 0x20000000
+#define PRINT_FLAG_VDEC_DETAIL 0x40000000
+#define PRINT_FLAG_VDEC_DATA 0x80000000
+#endif
+
+int av1_print2(int flag, const char *fmt, ...);
+
+unsigned char av1_is_debug(int flag);
+
+#endif
+
diff --git a/drivers/frame_provider/decoder/vav1/vav1.c b/drivers/frame_provider/decoder/vav1/vav1.c
new file mode 100644
index 0000000..6e844e1
--- a/dev/null
+++ b/drivers/frame_provider/decoder/vav1/vav1.c
@@ -0,0 +1,8977 @@
+ /*
+ * drivers/amlogic/amports/vav1.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+#define DEBUG
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/semaphore.h>
+#include <linux/delay.h>
+#include <linux/timer.h>
+#include <linux/kfifo.h>
+#include <linux/kthread.h>
+#include <linux/spinlock.h>
+#include <linux/platform_device.h>
+#include <linux/amlogic/media/vfm/vframe.h>
+#include <linux/amlogic/media/utils/amstream.h>
+#include <linux/amlogic/media/utils/vformat.h>
+#include <linux/amlogic/media/frame_sync/ptsserv.h>
+#include <linux/amlogic/media/canvas/canvas.h>
+#include <linux/amlogic/media/vfm/vframe_provider.h>
+#include <linux/amlogic/media/vfm/vframe_receiver.h>
+#include <linux/dma-mapping.h>
+#include <linux/dma-contiguous.h>
+#include <linux/slab.h>
+#include <linux/amlogic/tee.h>
+#include "../../../stream_input/amports/amports_priv.h"
+#include <linux/amlogic/media/codec_mm/codec_mm.h>
+#include "../utils/decoder_mmu_box.h"
+#include "../utils/decoder_bmmu_box.h"
+
+#define MEM_NAME "codec_vp9"
+/* #include <mach/am_regs.h> */
+#include <linux/amlogic/media/utils/vdec_reg.h>
+#include "../utils/vdec.h"
+#include "../utils/amvdec.h"
+#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
+#include "../utils/vdec_profile.h"
+#endif
+
+#include <linux/amlogic/media/video_sink/video.h>
+#include <linux/amlogic/media/codec_mm/configs.h>
+#include "../utils/config_parser.h"
+#include "../utils/firmware.h"
+#include "../../../common/chips/decoder_cpu_ver_info.h"
+#include "../../../amvdec_ports/vdec_drv_base.h"
+
+#define SUPPORT_V4L2
+//#define DEBUG_USE_VP9_DEVICE_NAME
+//#define BUFMGR_ONLY_OLD_CHIP
+
+#ifdef SUPPORT_V4L2
+#include "../utils/vdec_v4l2_buffer_ops.h"
+#endif
+
+#define AML
+#include "aom_av1_define.h"
+#include "av1_global.h"
+
+#define TO_CHANGE
+#define CHANGE_DONE
+#define MIX_STREAM_SUPPORT
+#ifdef TO_CHANGE
+#define MV_USE_FIXED_BUF
+//#define USE_SPEC_BUF_FOR_MMU_HEAD
+#endif
+
+#define AOM_AV1_DBLK_INIT
+#define AOM_AV1_UPSCALE_INIT
+
+#define USE_DEC_PIC_END
+
+
+#include "vav1.h"
+
+#define FGS_TABLE_SIZE (512 * 128 / 8)
+
+#define AV1_GMC_PARAM_BUFF_ADDR 0x316d
+#define HEVCD_MPP_DECOMP_AXIURG_CTL 0x34c7
+#define HEVC_FGS_IDX 0x3660
+#define HEVC_FGS_DATA 0x3661
+#define HEVC_FGS_CTRL 0x3662
+#define AV1_SKIP_MODE_INFO 0x316c
+#define VP9_QUANT_WR 0x3146
+#define AV1_SEG_W_ADDR 0x3165
+#define AV1_SEG_R_ADDR 0x3166
+#define AV1_REF_SEG_INFO 0x3171
+#define HEVC_ASSIST_PIC_SIZE_FB_READ 0x300d
+#define PARSER_REF_SCALE_ENBL 0x316b
+#define HEVC_MPRED_MV_RPTR_1 0x3263
+#define HEVC_MPRED_MV_RPTR_2 0x3264
+#define HEVC_SAO_CTRL9 0x362d
+#define HEVC_FGS_TABLE_START 0x3666
+#define HEVC_FGS_TABLE_LENGTH 0x3667
+#define HEVC_DBLK_CDEF0 0x3515
+#define HEVC_DBLK_CDEF1 0x3516
+#define HEVC_DBLK_UPS1 0x351c
+#define HEVC_DBLK_UPS2 0x351d
+#define HEVC_DBLK_UPS3 0x351e
+#define HEVC_DBLK_UPS4 0x351f
+#define HEVC_DBLK_UPS5 0x3520
+#define AV1_UPSCALE_X0_QN 0x316e
+#define AV1_UPSCALE_STEP_QN 0x316f
+#define HEVC_DBLK_DBLK0 0x3523
+#define HEVC_DBLK_DBLK1 0x3524
+#define HEVC_DBLK_DBLK2 0x3525
+
+#define HW_MASK_FRONT 0x1
+#define HW_MASK_BACK 0x2
+
+#define VP9D_MPP_REFINFO_TBL_ACCCONFIG 0x3442
+#define VP9D_MPP_REFINFO_DATA 0x3443
+#define VP9D_MPP_REF_SCALE_ENBL 0x3441
+#define HEVC_MPRED_CTRL4 0x324c
+#define HEVC_CM_HEADER_START_ADDR 0x3628
+#define HEVC_DBLK_CFGB 0x350b
+#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464
+#define HEVC_SAO_MMU_VH1_ADDR 0x363b
+#define HEVC_SAO_MMU_VH0_ADDR 0x363a
+
+#define HEVC_MV_INFO 0x310d
+#define HEVC_QP_INFO 0x3137
+#define HEVC_SKIP_INFO 0x3136
+
+#define HEVC_CM_BODY_LENGTH2 0x3663
+#define HEVC_CM_HEADER_OFFSET2 0x3664
+#define HEVC_CM_HEADER_LENGTH2 0x3665
+
+#define HEVC_CM_HEADER_START_ADDR2 0x364a
+#define HEVC_SAO_MMU_DMA_CTRL2 0x364c
+#define HEVC_SAO_MMU_VH0_ADDR2 0x364d
+#define HEVC_SAO_MMU_VH1_ADDR2 0x364e
+#define HEVC_DW_VH0_ADDDR 0x365e
+#define HEVC_DW_VH1_ADDDR 0x365f
+
+#ifdef BUFMGR_ONLY_OLD_CHIP
+#undef AV1_SKIP_MODE_INFO
+#define AV1_SKIP_MODE_INFO HEVC_ASSIST_SCRATCH_B
+#endif
+
+
+#define AOM_AV1_DEC_IDLE 0
+#define AOM_AV1_DEC_FRAME_HEADER 1
+#define AOM_AV1_DEC_TILE_END 2
+#define AOM_AV1_DEC_TG_END 3
+#define AOM_AV1_DEC_LCU_END 4
+#define AOM_AV1_DECODE_SLICE 5
+#define AOM_AV1_SEARCH_HEAD 6
+#define AOM_AV1_DUMP_LMEM 7
+#define AOM_AV1_FGS_PARAM_CONT 8
+#define AOM_AV1_DISCARD_NAL 0x10
+
+/*status*/
+#define AOM_AV1_DEC_PIC_END 0xe0
+/*AOM_AV1_FGS_PARA:
+Bit[11] - 0 Read, 1 - Write
+Bit[10:8] - film_grain_params_ref_idx, For Write request
+*/
+#define AOM_AV1_FGS_PARAM 0xe1
+#define AOM_AV1_DEC_PIC_END_PRE 0xe2
+#define AOM_AV1_HEAD_PARSER_DONE 0xf0
+#define AOM_AV1_HEAD_SEARCH_DONE 0xf1
+#define AOM_AV1_SEQ_HEAD_PARSER_DONE 0xf2
+#define AOM_AV1_FRAME_HEAD_PARSER_DONE 0xf3
+#define AOM_AV1_FRAME_PARSER_DONE 0xf4
+#define AOM_AV1_REDUNDANT_FRAME_HEAD_PARSER_DONE 0xf5
+#define HEVC_ACTION_DONE 0xff
+
+#define AOM_DECODE_BUFEMPTY 0x20
+#define AOM_DECODE_TIMEOUT 0x21
+#define AOM_SEARCH_BUFEMPTY 0x22
+#define AOM_DECODE_OVER_SIZE 0x23
+#define AOM_EOS 0x24
+#define AOM_NAL_DECODE_DONE 0x25
+
+
+#define VF_POOL_SIZE 32
+
+#undef pr_info
+#define pr_info printk
+
+#define DECODE_MODE_SINGLE ((0x80 << 24) | 0)
+#define DECODE_MODE_MULTI_STREAMBASE ((0x80 << 24) | 1)
+#define DECODE_MODE_MULTI_FRAMEBASE ((0x80 << 24) | 2)
+#define DECODE_MODE_SINGLE_LOW_LATENCY ((0x80 << 24) | 3)
+#define DECODE_MODE_MULTI_FRAMEBASE_NOHEAD ((0x80 << 24) | 4)
+
+#define VP9_TRIGGER_FRAME_DONE 0x100
+#define VP9_TRIGGER_FRAME_ENABLE 0x200
+
+#define MV_MEM_UNIT 0x240
+/*---------------------------------------------------
+ * Include "parser_cmd.h"
+ *---------------------------------------------------
+ */
+#define PARSER_CMD_SKIP_CFG_0 0x0000090b
+
+#define PARSER_CMD_SKIP_CFG_1 0x1b14140f
+
+#define PARSER_CMD_SKIP_CFG_2 0x001b1910
+
+#define PARSER_CMD_NUMBER 37
+
+/*#define HEVC_PIC_STRUCT_SUPPORT*/
+/* to remove, fix build error */
+
+/*#define CODEC_MM_FLAGS_FOR_VDECODER 0*/
+
+#define MULTI_INSTANCE_SUPPORT
+#define SUPPORT_10BIT
+/* #define ERROR_HANDLE_DEBUG */
+
+#ifndef STAT_KTHREAD
+#define STAT_KTHREAD 0x40
+#endif
+
+#ifdef MULTI_INSTANCE_SUPPORT
+#define MAX_DECODE_INSTANCE_NUM 9
+
+#ifdef DEBUG_USE_VP9_DEVICE_NAME
+#define MULTI_DRIVER_NAME "ammvdec_vp9"
+#else
+#define MULTI_DRIVER_NAME "ammvdec_av1"
+#endif
+
+static unsigned int max_decode_instance_num
+ = MAX_DECODE_INSTANCE_NUM;
+static unsigned int decode_frame_count[MAX_DECODE_INSTANCE_NUM];
+static unsigned int display_frame_count[MAX_DECODE_INSTANCE_NUM];
+static unsigned int max_process_time[MAX_DECODE_INSTANCE_NUM];
+static unsigned int run_count[MAX_DECODE_INSTANCE_NUM];
+static unsigned int input_empty[MAX_DECODE_INSTANCE_NUM];
+static unsigned int not_run_ready[MAX_DECODE_INSTANCE_NUM];
+#ifdef AOM_AV1_MMU_DW
+static unsigned int dw_mmu_enable[MAX_DECODE_INSTANCE_NUM];
+#endif
+static u32 decode_timeout_val = 200;
+static int start_decode_buf_level = 0x8000;
+static u32 work_buf_size;
+
+static u32 mv_buf_margin;
+
+/* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */
+/* double_write_mode:
+ * 0, no double write;
+ * 1, 1:1 ratio;
+ * 2, (1/4):(1/4) ratio;
+ * 3, (1/4):(1/4) ratio, with both compressed frame included
+ * 4, (1/2):(1/2) ratio;
+ * 5, (1/2):(1/2) ratio, with both compressed frame included
+ * 0x10, double write only
+ * 0x20, mmu double write
+ * 0x100, if > 1080p,use mode 4,else use mode 1;
+ * 0x200, if > 1080p,use mode 2,else use mode 1;
+ * 0x300, if > 720p, use mode 4, else use mode 1;
+ */
+static u32 double_write_mode;
+
+#ifdef DEBUG_USE_VP9_DEVICE_NAME
+#define DRIVER_NAME "amvdec_vp9"
+#define MODULE_NAME "amvdec_vp9"
+#define DRIVER_HEADER_NAME "amvdec_vp9_header"
+#else
+#define DRIVER_NAME "amvdec_av1"
+#define MODULE_NAME "amvdec_av1"
+#define DRIVER_HEADER_NAME "amvdec_av1_header"
+#endif
+
+#define PUT_INTERVAL (HZ/100)
+#define ERROR_SYSTEM_RESET_COUNT 200
+
+#define PTS_NORMAL 0
+#define PTS_NONE_REF_USE_DURATION 1
+
+#define PTS_MODE_SWITCHING_THRESHOLD 3
+#define PTS_MODE_SWITCHING_RECOVERY_THREASHOLD 3
+
+#define DUR2PTS(x) ((x)*90/96)
+
+struct AV1HW_s;
+static int vav1_vf_states(struct vframe_states *states, void *);
+static struct vframe_s *vav1_vf_peek(void *);
+static struct vframe_s *vav1_vf_get(void *);
+static void vav1_vf_put(struct vframe_s *, void *);
+static int vav1_event_cb(int type, void *data, void *private_data);
+
+static int vav1_stop(struct AV1HW_s *hw);
+#ifdef MULTI_INSTANCE_SUPPORT
+static s32 vav1_init(struct vdec_s *vdec);
+#else
+static s32 vav1_init(struct AV1HW_s *hw);
+#endif
+static void vav1_prot_init(struct AV1HW_s *hw, u32 mask);
+static int vav1_local_init(struct AV1HW_s *hw);
+static void vav1_put_timer_func(unsigned long arg);
+static void dump_data(struct AV1HW_s *hw, int size);
+static unsigned char get_data_check_sum
+ (struct AV1HW_s *hw, int size);
+static void dump_pic_list(struct AV1HW_s *hw);
+static int av1_alloc_mmu(
+ struct AV1HW_s *hw,
+ int cur_buf_idx,
+ int pic_width,
+ int pic_height,
+ unsigned short bit_depth,
+ unsigned int *mmu_index_adr);
+
+#ifdef DEBUG_USE_VP9_DEVICE_NAME
+static const char vvp9_dec_id[] = "vvp9-dev";
+
+#define PROVIDER_NAME "decoder.vp9"
+#define MULTI_INSTANCE_PROVIDER_NAME "vdec.vp9"
+#else
+static const char vav1_dec_id[] = "vav1-dev";
+
+#define PROVIDER_NAME "decoder.av1"
+#define MULTI_INSTANCE_PROVIDER_NAME "vdec.av1"
+#endif
+
+static const struct vframe_operations_s vav1_vf_provider = {
+ .peek = vav1_vf_peek,
+ .get = vav1_vf_get,
+ .put = vav1_vf_put,
+ .event_cb = vav1_event_cb,
+ .vf_states = vav1_vf_states,
+};
+
+static struct vframe_provider_s vav1_vf_prov;
+
+static u32 bit_depth_luma;
+static u32 bit_depth_chroma;
+static u32 frame_width;
+static u32 frame_height;
+static u32 video_signal_type;
+
+static u32 on_no_keyframe_skiped;
+
+#define PROB_SIZE (496 * 2 * 4)
+#define PROB_BUF_SIZE (0x5000)
+#define COUNT_BUF_SIZE (0x300 * 4 * 4)
+/*compute_losless_comp_body_size(4096, 2304, 1) = 18874368(0x1200000)*/
+#define MAX_FRAME_4K_NUM 0x1200
+#define MAX_FRAME_8K_NUM 0x4800
+
+#define HEVC_ASSIST_MMU_MAP_ADDR 0x3009
+
+
+/*USE_BUF_BLOCK*/
+struct BUF_s {
+ int index;
+ unsigned int alloc_flag;
+ /*buffer */
+ unsigned int cma_page_count;
+ unsigned long alloc_addr;
+ unsigned long start_adr;
+ unsigned int size;
+
+ unsigned int free_start_adr;
+ ulong v4l_ref_buf_addr;
+} /*BUF_t */;
+
+struct MVBUF_s {
+ unsigned long start_adr;
+ unsigned int size;
+ int used_flag;
+} /*MVBUF_t */;
+
+/*#define TEST_WR_PTR_INC*/
+/*#define WR_PTR_INC_NUM 128*/
+#define WR_PTR_INC_NUM 1
+
+//#define SIMULATION
+#define DOS_PROJECT
+#undef MEMORY_MAP_IN_REAL_CHIP
+
+/*#undef DOS_PROJECT*/
+/*#define MEMORY_MAP_IN_REAL_CHIP*/
+
+/*#define CONFIG_HEVC_CLK_FORCED_ON*/
+/*#define ENABLE_SWAP_TEST*/
+//#define MCRCC_ENABLE
+
+
+#ifdef VP9_10B_NV21
+#else
+#define LOSLESS_COMPRESS_MODE
+#endif
+
+typedef unsigned int u32;
+typedef unsigned short u16;
+
+
+static u32 get_picture_qos;
+
+static u32 debug;
+
+static bool is_reset;
+/*for debug*/
+/*
+ udebug_flag:
+ bit 0, enable ucode print
+ bit 1, enable ucode detail print
+ bit [31:16] not 0, pos to dump lmem
+ bit 2, pop bits to lmem
+ bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
+*/
+static u32 udebug_flag;
+/*
+ when udebug_flag[1:0] is not 0
+ udebug_pause_pos not 0,
+ pause position
+*/
+static u32 udebug_pause_pos;
+/*
+ when udebug_flag[1:0] is not 0
+ and udebug_pause_pos is not 0,
+ pause only when DEBUG_REG2 is equal to this val
+*/
+static u32 udebug_pause_val;
+
+static u32 udebug_pause_decode_idx;
+
+#define DEBUG_REG
+#ifdef DEBUG_REG
+void AV1_WRITE_VREG_DBG2(unsigned int adr, unsigned int val, int line)
+{
+ if (debug & VP9_DEBUG_REG)
+ pr_info("%d:%s(%x, %x)\n", line, __func__, adr, val);
+ if (adr != 0)
+ WRITE_VREG(adr, val);
+}
+
+#undef WRITE_VREG
+#define WRITE_VREG(a,v) AV1_WRITE_VREG_DBG2(a,v,__LINE__)
+#endif
+
+#define FRAME_CNT_WINDOW_SIZE 59
+#define RATE_CORRECTION_THRESHOLD 5
+/**************************************************
+
+AV1 buffer management start
+
+***************************************************/
+
+#define MMU_COMPRESS_HEADER_SIZE 0x48000
+#define MMU_COMPRESS_HEADER_SIZE_DW MMU_COMPRESS_HEADER_SIZE
+#define MMU_COMPRESS_8K_HEADER_SIZE (0x48000*4)
+#define MAX_SIZE_8K (8192 * 4608)
+#define MAX_SIZE_4K (4096 * 2304)
+#define IS_8K_SIZE(w, h) (((w) * (h)) > MAX_SIZE_4K)
+
+#define INVALID_IDX -1 /* Invalid buffer index.*/
+
+
+/*4 scratch frames for the new frames to support a maximum of 4 cores decoding
+ *in parallel, 3 for scaled references on the encoder.
+ *TODO(hkuang): Add ondemand frame buffers instead of hardcoding the number
+ * // of framebuffers.
+ *TODO(jkoleszar): These 3 extra references could probably come from the
+ *normal reference pool.
+ */
+//#define FRAME_BUFFERS (REF_FRAMES + 16)
+#ifdef USE_SPEC_BUF_FOR_MMU_HEAD
+#define HEADER_FRAME_BUFFERS (0)
+#elif (defined AOM_AV1_MMU_DW)
+#define HEADER_FRAME_BUFFERS (2 * FRAME_BUFFERS)
+#else
+#define HEADER_FRAME_BUFFERS (FRAME_BUFFERS)
+#endif
+#define MAX_BUF_NUM (FRAME_BUFFERS)
+#define MV_BUFFER_NUM FRAME_BUFFERS
+
+//#define FRAME_CONTEXTS_LOG2 2
+//#define FRAME_CONTEXTS (1 << FRAME_CONTEXTS_LOG2)
+/*buffer + header buffer + workspace*/
+#ifdef MV_USE_FIXED_BUF
+#define MAX_BMMU_BUFFER_NUM (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + 1)
+#define VF_BUFFER_IDX(n) (n)
+#define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n)
+#define WORK_SPACE_BUF_ID (FRAME_BUFFERS + HEADER_FRAME_BUFFERS)
+#else
+#define MAX_BMMU_BUFFER_NUM \
+ (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + MV_BUFFER_NUM + 1)
+#define VF_BUFFER_IDX(n) (n)
+#define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n)
+#define MV_BUFFER_IDX(n) (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + n)
+#define WORK_SPACE_BUF_ID \
+ (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + MV_BUFFER_NUM)
+#endif
+#ifdef AOM_AV1_MMU_DW
+#define DW_HEADER_BUFFER_IDX(n) (HEADER_BUFFER_IDX(HEADER_FRAME_BUFFERS/2) + n)
+#endif
+
+
+static void set_canvas(struct AV1HW_s *hw,
+ struct PIC_BUFFER_CONFIG_s *pic_config);
+
+static void fill_frame_info(struct AV1HW_s *hw,
+ struct PIC_BUFFER_CONFIG_s *frame,
+ unsigned int framesize,
+ unsigned int pts);
+
+
+static int compute_losless_comp_body_size(int width, int height,
+ uint8_t is_bit_depth_10);
+
+
+
+#ifdef MULTI_INSTANCE_SUPPORT
+#define DEC_RESULT_NONE 0
+#define DEC_RESULT_DONE 1
+#define DEC_RESULT_AGAIN 2
+#define DEC_RESULT_CONFIG_PARAM 3
+#define DEC_RESULT_ERROR 4
+#define DEC_INIT_PICLIST 5
+#define DEC_UNINIT_PICLIST 6
+#define DEC_RESULT_GET_DATA 7
+#define DEC_RESULT_GET_DATA_RETRY 8
+#define DEC_RESULT_EOS 9
+#define DEC_RESULT_FORCE_EXIT 10
+
+#define DEC_S1_RESULT_NONE 0
+#define DEC_S1_RESULT_DONE 1
+#define DEC_S1_RESULT_FORCE_EXIT 2
+#define DEC_S1_RESULT_TEST_TRIGGER_DONE 0xf0
+
+#ifdef FB_DECODING_TEST_SCHEDULE
+#define TEST_SET_NONE 0
+#define TEST_SET_PIC_DONE 1
+#define TEST_SET_S2_DONE 2
+#endif
+
+static void av1_work(struct work_struct *work);
+#endif
+
+#ifdef AOM_AV1_DBLK_INIT
+struct loop_filter_info_n_s;
+struct loopfilter;
+struct segmentation_lf;
+#endif
+struct AV1HW_s {
+ AV1Decoder *pbi;
+ union param_u aom_param;
+ unsigned char frame_decoded;
+ unsigned char one_compressed_data_done;
+ unsigned char new_compressed_data;
+#if 1
+/*def CHECK_OBU_REDUNDANT_FRAME_HEADER*/
+ int obu_frame_frame_head_come_after_tile;
+#endif
+ unsigned char index;
+
+ struct device *cma_dev;
+ struct platform_device *platform_dev;
+ void (*vdec_cb)(struct vdec_s *, void *);
+ void *vdec_cb_arg;
+ struct vframe_chunk_s *chunk;
+ int dec_result;
+ struct work_struct work;
+ struct work_struct set_clk_work;
+ u32 start_shift_bytes;
+
+ struct BuffInfo_s work_space_buf_store;
+ unsigned long buf_start;
+ u32 buf_size;
+ u32 cma_alloc_count;
+ unsigned long cma_alloc_addr;
+ uint8_t eos;
+ unsigned long int start_process_time;
+ unsigned last_lcu_idx;
+ int decode_timeout_count;
+ unsigned timeout_num;
+ int save_buffer_mode;
+
+ int double_write_mode;
+
+ long used_4k_num;
+
+ unsigned char m_ins_flag;
+ char *provider_name;
+ union param_u param;
+ int frame_count;
+ int pic_count;
+ u32 stat;
+ struct timer_list timer;
+ u32 frame_dur;
+ u32 frame_ar;
+ int fatal_error;
+ uint8_t init_flag;
+ uint8_t config_next_ref_info_flag;
+ uint8_t first_sc_checked;
+ uint8_t process_busy;
+#define PROC_STATE_INIT 0
+#define PROC_STATE_DECODESLICE 1
+#define PROC_STATE_SENDAGAIN 2
+ uint8_t process_state;
+ u32 ucode_pause_pos;
+
+ int show_frame_num;
+ struct buff_s mc_buf_spec;
+ struct dec_sysinfo vav1_amstream_dec_info;
+ void *rpm_addr;
+ void *lmem_addr;
+ dma_addr_t rpm_phy_addr;
+ dma_addr_t lmem_phy_addr;
+ unsigned short *lmem_ptr;
+ unsigned short *debug_ptr;
+
+ void *prob_buffer_addr;
+ void *count_buffer_addr;
+ dma_addr_t prob_buffer_phy_addr;
+ dma_addr_t count_buffer_phy_addr;
+
+ void *frame_mmu_map_addr;
+ dma_addr_t frame_mmu_map_phy_addr;
+#ifdef AOM_AV1_MMU_DW
+ void *dw_frame_mmu_map_addr;
+ dma_addr_t dw_frame_mmu_map_phy_addr;
+#endif
+ unsigned int use_cma_flag;
+
+ struct BUF_s m_BUF[MAX_BUF_NUM];
+ struct MVBUF_s m_mv_BUF[MV_BUFFER_NUM];
+ u32 used_buf_num;
+ DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
+ DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
+ DECLARE_KFIFO(pending_q, struct vframe_s *, VF_POOL_SIZE);
+ struct vframe_s vfpool[VF_POOL_SIZE];
+ u32 vf_pre_count;
+ u32 vf_get_count;
+ u32 vf_put_count;
+ int buf_num;
+ int pic_num;
+ int lcu_size_log2;
+ unsigned int losless_comp_body_size;
+
+ u32 video_signal_type;
+
+ int pts_mode;
+ int last_lookup_pts;
+ int last_pts;
+ u64 last_lookup_pts_us64;
+ u64 last_pts_us64;
+ u64 shift_byte_count;
+
+ u32 pts_unstable;
+ u32 frame_cnt_window;
+ u32 pts1, pts2;
+ u32 last_duration;
+ u32 duration_from_pts_done;
+ bool av1_first_pts_ready;
+
+ u32 shift_byte_count_lo;
+ u32 shift_byte_count_hi;
+ int pts_mode_switching_count;
+ int pts_mode_recovery_count;
+
+ bool get_frame_dur;
+ u32 saved_resolution;
+
+ /**/
+ struct AV1_Common_s common;
+ struct RefCntBuffer_s *cur_buf;
+ int refresh_frame_flags;
+ uint8_t need_resync;
+ uint8_t hold_ref_buf;
+ uint8_t ready_for_new_data;
+ struct BufferPool_s av1_buffer_pool;
+
+ struct BuffInfo_s *work_space_buf;
+
+ struct buff_s *mc_buf;
+
+ unsigned int frame_width;
+ unsigned int frame_height;
+
+ unsigned short *rpm_ptr;
+ int init_pic_w;
+ int init_pic_h;
+ int lcu_total;
+
+ int current_lcu_size;
+
+ int slice_type;
+
+ int skip_flag;
+ int decode_idx;
+ int result_done_count;
+ uint8_t has_keyframe;
+ uint8_t wait_buf;
+ uint8_t error_flag;
+
+ /* bit 0, for decoding; bit 1, for displaying */
+ uint8_t ignore_bufmgr_error;
+ int PB_skip_mode;
+ int PB_skip_count_after_decoding;
+ /*hw*/
+
+ /**/
+ struct vdec_info *gvs;
+
+ u32 pre_stream_offset;
+
+ unsigned int dec_status;
+ u32 last_put_idx;
+ int new_frame_displayed;
+ void *mmu_box;
+ void *bmmu_box;
+ int mmu_enable;
+#ifdef AOM_AV1_MMU_DW
+ void *mmu_box_dw;
+ int dw_mmu_enable;
+#endif
+ struct vframe_master_display_colour_s vf_dp;
+ struct firmware_s *fw;
+ int max_pic_w;
+ int max_pic_h;
+
+ int dec_s1_result;
+ int s1_test_cmd;
+ struct work_struct s1_work;
+ int used_stage_buf_num;
+ int s1_pos;
+ int s2_pos;
+ void *stage_mmu_map_addr;
+ dma_addr_t stage_mmu_map_phy_addr;
+ unsigned char run2_busy;
+
+ int s1_mv_buf_index;
+ int s1_mv_buf_index_pre;
+ int s1_mv_buf_index_pre_pre;
+ unsigned long s1_mpred_mv_wr_start_addr;
+ unsigned long s1_mpred_mv_wr_start_addr_pre;
+ unsigned short s1_intra_only;
+ unsigned short s1_frame_type;
+ unsigned short s1_width;
+ unsigned short s1_height;
+ unsigned short s1_last_show_frame;
+ union param_u s1_param;
+ u8 back_not_run_ready;
+
+ int need_cache_size;
+ u64 sc_start_time;
+ bool postproc_done;
+ int low_latency_flag;
+ bool no_head;
+ bool pic_list_init_done;
+ bool pic_list_init_done2;
+ bool is_used_v4l;
+ void *v4l2_ctx;
+ int frameinfo_enable;
+ struct vframe_qos_s vframe_qos;
+
+#ifdef AOM_AV1_DBLK_INIT
+ /*
+ * malloc may not work in real chip, please allocate memory for the following structures
+ */
+ struct loop_filter_info_n_s *lfi;
+ struct loopfilter *lf;
+ struct segmentation_lf *seg_4lf;
+#endif
+
+};
+
+int av1_print(struct AV1HW_s *hw,
+ int flag, const char *fmt, ...)
+{
+#define HEVC_PRINT_BUF 256
+ unsigned char buf[HEVC_PRINT_BUF];
+ int len = 0;
+
+ if (hw == NULL ||
+ (flag == 0) ||
+ (debug & flag)) {
+ va_list args;
+
+ va_start(args, fmt);
+ if (hw)
+ len = sprintf(buf, "[%d]", hw->index);
+ vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
+ pr_debug("%s", buf);
+ va_end(args);
+ }
+ return 0;
+}
+
+unsigned char av1_is_debug(int flag)
+{
+ if ((flag == 0) || (debug & flag))
+ return 1;
+ return 0;
+}
+
+int av1_print2(int flag, const char *fmt, ...)
+{
+ unsigned char buf[HEVC_PRINT_BUF];
+ int len = 0;
+
+ if ((flag == 0) ||
+ (debug & flag)) {
+ va_list args;
+
+ va_start(args, fmt);
+ vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
+ pr_debug("%s", buf);
+ va_end(args);
+ }
+ return 0;
+
+}
+
+static int is_oversize(int w, int h)
+{
+ int max = (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)?
+ MAX_SIZE_8K : MAX_SIZE_4K;
+
+ if (w <= 0 || h <= 0)
+ return true;
+
+ if (h != 0 && (w > max / h))
+ return true;
+
+ return false;
+}
+
+static int v4l_get_fb(struct aml_vcodec_ctx *ctx, struct vdec_fb **out)
+{
+ int ret = 0;
+
+ ret = ctx->dec_if->get_param(ctx->drv_handle,
+ GET_PARAM_FREE_FRAME_BUFFER, out);
+
+ return ret;
+}
+
+
+static inline bool close_to(int a, int b, int m)
+{
+ return (abs(a - b) < m) ? true : false;
+}
+
+#ifdef MULTI_INSTANCE_SUPPORT
+static int av1_print_cont(struct AV1HW_s *hw,
+ int flag, const char *fmt, ...)
+{
+ unsigned char buf[HEVC_PRINT_BUF];
+ int len = 0;
+
+ if (hw == NULL ||
+ (flag == 0) ||
+ (debug & flag)) {
+ va_list args;
+
+ va_start(args, fmt);
+ vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
+ pr_debug("%s", buf);
+ va_end(args);
+ }
+ return 0;
+}
+
+static void trigger_schedule(struct AV1HW_s *hw)
+{
+ if (hw->vdec_cb)
+ hw->vdec_cb(hw_to_vdec(hw), hw->vdec_cb_arg);
+}
+
+static void reset_process_time(struct AV1HW_s *hw)
+{
+ if (hw->start_process_time) {
+ unsigned process_time =
+ 1000 * (jiffies - hw->start_process_time) / HZ;
+ hw->start_process_time = 0;
+ if (process_time > max_process_time[hw->index])
+ max_process_time[hw->index] = process_time;
+ }
+}
+
+static void start_process_time(struct AV1HW_s *hw)
+{
+ hw->start_process_time = jiffies;
+ hw->decode_timeout_count = 0;
+ hw->last_lcu_idx = 0;
+}
+
+static void timeout_process(struct AV1HW_s *hw)
+{
+ hw->timeout_num++;
+ amhevc_stop();
+ av1_print(hw,
+ 0, "%s decoder timeout\n", __func__);
+
+ hw->dec_result = DEC_RESULT_DONE;
+ reset_process_time(hw);
+ vdec_schedule_work(&hw->work);
+}
+
+static u32 get_valid_double_write_mode(struct AV1HW_s *hw)
+{
+ u32 dw = ((double_write_mode & 0x80000000) == 0) ?
+ hw->double_write_mode :
+ (double_write_mode & 0x7fffffff);
+ if ((dw & 0x20) &&
+ ((dw & 0xf) == 2 || (dw & 0xf) == 3)) {
+ pr_info("MMU doueble write 1:4 not supported !!!\n");
+ dw = 0;
+ }
+ return dw;
+}
+
+static int get_double_write_mode(struct AV1HW_s *hw)
+{
+ u32 valid_dw_mode = get_valid_double_write_mode(hw);
+ u32 dw;
+ int w, h;
+ struct AV1_Common_s *cm = &hw->pbi->common;
+ struct PIC_BUFFER_CONFIG_s *cur_pic_config;
+
+ if (!cm->cur_frame)
+ return 1;/*no valid frame,*/
+ cur_pic_config = &cm->cur_frame->buf;
+ w = cur_pic_config->y_crop_width;
+ h = cur_pic_config->y_crop_height;
+
+ dw = 0x1; /*1:1*/
+ switch (valid_dw_mode) {
+ case 0x100:
+ if (w > 1920 && h > 1088)
+ dw = 0x4; /*1:2*/
+ break;
+ case 0x200:
+ if (w > 1920 && h > 1088)
+ dw = 0x2; /*1:4*/
+ break;
+ case 0x300:
+ if (w > 1280 && h > 720)
+ dw = 0x4; /*1:2*/
+ break;
+ default:
+ dw = valid_dw_mode;
+ break;
+ }
+ return dw;
+}
+
+/* for double write buf alloc */
+static int get_double_write_mode_init(struct AV1HW_s *hw)
+{
+ u32 valid_dw_mode = get_valid_double_write_mode(hw);
+ u32 dw;
+ int w = hw->init_pic_w;
+ int h = hw->init_pic_h;
+
+ dw = 0x1; /*1:1*/
+ switch (valid_dw_mode) {
+ case 0x100:
+ if (w > 1920 && h > 1088)
+ dw = 0x4; /*1:2*/
+ break;
+ case 0x200:
+ if (w > 1920 && h > 1088)
+ dw = 0x2; /*1:4*/
+ break;
+ case 0x300:
+ if (w > 1280 && h > 720)
+ dw = 0x4; /*1:2*/
+ break;
+ default:
+ dw = valid_dw_mode;
+ break;
+ }
+ return dw;
+}
+#endif
+
+static int get_double_write_ratio(struct AV1HW_s *hw,
+ int dw_mode)
+{
+ int ratio = 1;
+ int dw_mode_ratio = dw_mode & 0xf;
+ if ((dw_mode_ratio == 2) ||
+ (dw_mode_ratio == 3))
+ ratio = 4;
+ else if (dw_mode_ratio == 4)
+ ratio = 2;
+ return ratio;
+}
+
+//#define MAX_4K_NUM 0x1200
+int av1_alloc_mmu(
+ struct AV1HW_s *hw,
+ int cur_buf_idx,
+ int pic_width,
+ int pic_height,
+ unsigned short bit_depth,
+ unsigned int *mmu_index_adr)
+{
+ int ret = 0;
+ int bit_depth_10 = (bit_depth == AOM_BITS_10);
+ int picture_size;
+ int cur_mmu_4k_number, max_frame_num;
+ if (!hw->mmu_box) {
+ pr_err("error no mmu box!\n");
+ return -1;
+ }
+ if (hw->double_write_mode & 0x10)
+ return 0;
+ if (bit_depth >= AOM_BITS_12) {
+ hw->fatal_error = DECODER_FATAL_ERROR_SIZE_OVERFLOW;
+ pr_err("fatal_error, un support bit depth 12!\n\n");
+ return -1;
+ }
+ picture_size = compute_losless_comp_body_size(pic_width, pic_height,
+ bit_depth_10);
+ cur_mmu_4k_number = ((picture_size + (1 << 12) - 1) >> 12);
+
+ if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
+ max_frame_num = MAX_FRAME_8K_NUM;
+ else
+ max_frame_num = MAX_FRAME_4K_NUM;
+
+ if (cur_mmu_4k_number > max_frame_num) {
+ pr_err("over max !! cur_mmu_4k_number 0x%x width %d height %d\n",
+ cur_mmu_4k_number, pic_width, pic_height);
+ return -1;
+ }
+ ret = decoder_mmu_box_alloc_idx(
+ hw->mmu_box,
+ cur_buf_idx,
+ cur_mmu_4k_number,
+ mmu_index_adr);
+ return ret;
+}
+
+#ifdef AOM_AV1_MMU_DW
+static int compute_losless_comp_body_size_dw(int width, int height,
+ uint8_t is_bit_depth_10);
+
+int av1_alloc_mmu_dw(
+ struct AV1HW_s *hw,
+ int cur_buf_idx,
+ int pic_width,
+ int pic_height,
+ unsigned short bit_depth,
+ unsigned int *mmu_index_adr)
+{
+ int ret = 0;
+ int bit_depth_10 = (bit_depth == AOM_BITS_10);
+ int picture_size;
+ int cur_mmu_4k_number, max_frame_num;
+ if (!hw->mmu_box_dw) {
+ pr_err("error no mmu box!\n");
+ return -1;
+ }
+ if (hw->double_write_mode & 0x10)
+ return 0;
+ if (bit_depth >= AOM_BITS_12) {
+ hw->fatal_error = DECODER_FATAL_ERROR_SIZE_OVERFLOW;
+ pr_err("fatal_error, un support bit depth 12!\n\n");
+ return -1;
+ }
+ picture_size = compute_losless_comp_body_size_dw(pic_width, pic_height,
+ bit_depth_10);
+ cur_mmu_4k_number = ((picture_size + (1 << 12) - 1) >> 12);
+
+ if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
+ max_frame_num = MAX_FRAME_8K_NUM;
+ else
+ max_frame_num = MAX_FRAME_4K_NUM;
+
+ if (cur_mmu_4k_number > max_frame_num) {
+ pr_err("over max !! cur_mmu_4k_number 0x%x width %d height %d\n",
+ cur_mmu_4k_number, pic_width, pic_height);
+ return -1;
+ }
+ ret = decoder_mmu_box_alloc_idx(
+ hw->mmu_box_dw,
+ cur_buf_idx,
+ cur_mmu_4k_number,
+ mmu_index_adr);
+ return ret;
+}
+#endif
+
+#ifndef MV_USE_FIXED_BUF
+static void dealloc_mv_bufs(struct AV1HW_s *hw)
+{
+ int i;
+ for (i = 0; i < MV_BUFFER_NUM; i++) {
+ if (hw->m_mv_BUF[i].start_adr) {
+ if (debug)
+ pr_info(
+ "dealloc mv buf(%d) adr %ld size 0x%x used_flag %d\n",
+ i, hw->m_mv_BUF[i].start_adr,
+ hw->m_mv_BUF[i].size,
+ hw->m_mv_BUF[i].used_flag);
+ decoder_bmmu_box_free_idx(
+ hw->bmmu_box,
+ MV_BUFFER_IDX(i));
+ hw->m_mv_BUF[i].start_adr = 0;
+ hw->m_mv_BUF[i].size = 0;
+ hw->m_mv_BUF[i].used_flag = 0;
+ }
+ }
+}
+
+static int alloc_mv_buf(struct AV1HW_s *hw,
+ int i, int size)
+{
+ int ret = 0;
+ if (decoder_bmmu_box_alloc_buf_phy
+ (hw->bmmu_box,
+ MV_BUFFER_IDX(i), size,
+ DRIVER_NAME,
+ &hw->m_mv_BUF[i].start_adr) < 0) {
+ hw->m_mv_BUF[i].start_adr = 0;
+ ret = -1;
+ } else {
+ hw->m_mv_BUF[i].size = size;
+ hw->m_mv_BUF[i].used_flag = 0;
+ ret = 0;
+ if (debug) {
+ pr_info(
+ "MV Buffer %d: start_adr %p size %x\n",
+ i,
+ (void *)hw->m_mv_BUF[i].start_adr,
+ hw->m_mv_BUF[i].size);
+ }
+ }
+ return ret;
+}
+
+static int init_mv_buf_list(struct AV1HW_s *hw)
+{
+ int i;
+ int ret = 0;
+ int count = MV_BUFFER_NUM;
+ int pic_width = hw->init_pic_w;
+ int pic_height = hw->init_pic_h;
+ int lcu_size = 64; /*fixed 64*/ /* !!!!! TO DO ...*/
+ int pic_width_64 = (pic_width + 63) & (~0x3f);
+ int pic_height_32 = (pic_height + 31) & (~0x1f);
+ int pic_width_lcu = (pic_width_64 % lcu_size) ?
+ pic_width_64 / lcu_size + 1
+ : pic_width_64 / lcu_size;
+ int pic_height_lcu = (pic_height_32 % lcu_size) ?
+ pic_height_32 / lcu_size + 1
+ : pic_height_32 / lcu_size;
+ int lcu_total = pic_width_lcu * pic_height_lcu;
+ int size = ((lcu_total * MV_MEM_UNIT) + 0xffff) &
+ (~0xffff);
+ if (mv_buf_margin > 0)
+ count = REF_FRAMES + mv_buf_margin;
+
+ if (hw->init_pic_w > 2048 && hw->init_pic_h > 1088)
+ count = REF_FRAMES_4K + mv_buf_margin;
+
+ if (debug) {
+ pr_info("%s w:%d, h:%d, count: %d\n",
+ __func__, hw->init_pic_w, hw->init_pic_h, count);
+ }
+
+ for (i = 0;
+ i < count && i < MV_BUFFER_NUM; i++) {
+ if (alloc_mv_buf(hw, i, size) < 0) {
+ ret = -1;
+ break;
+ }
+ }
+ return ret;
+}
+
+static int get_mv_buf(struct AV1HW_s *hw,
+ int *mv_buf_index,
+ unsigned long *mpred_mv_wr_start_addr)
+{
+ int i;
+ int ret = -1;
+ for (i = 0; i < MV_BUFFER_NUM; i++) {
+ if (hw->m_mv_BUF[i].start_adr &&
+ hw->m_mv_BUF[i].used_flag == 0) {
+ hw->m_mv_BUF[i].used_flag = 1;
+ ret = i;
+ break;
+ }
+ }
+
+ if (ret >= 0) {
+ *mv_buf_index = ret;
+ *mpred_mv_wr_start_addr =
+ (hw->m_mv_BUF[ret].start_adr + 0xffff) &
+ (~0xffff);
+ if (debug & VP9_DEBUG_BUFMGR_MORE)
+ pr_info(
+ "%s => %d (%ld) size 0x%x\n",
+ __func__, ret,
+ *mpred_mv_wr_start_addr,
+ hw->m_mv_BUF[ret].size);
+ } else {
+ pr_info(
+ "%s: Error, mv buf is not enough\n",
+ __func__);
+ }
+ return ret;
+}
+
+static void put_mv_buf(struct AV1HW_s *hw,
+ int *mv_buf_index)
+{
+ int i = *mv_buf_index;
+ if (i >= MV_BUFFER_NUM) {
+ if (debug & VP9_DEBUG_BUFMGR_MORE)
+ pr_info(
+ "%s: index %d beyond range\n",
+ __func__, i);
+ return;
+ }
+ if (debug & VP9_DEBUG_BUFMGR_MORE)
+ pr_info(
+ "%s(%d): used_flag(%d)\n",
+ __func__, i,
+ hw->m_mv_BUF[i].used_flag);
+
+ *mv_buf_index = -1;
+ if (hw->m_mv_BUF[i].start_adr &&
+ hw->m_mv_BUF[i].used_flag)
+ hw->m_mv_BUF[i].used_flag = 0;
+}
+
+static void put_un_used_mv_bufs(struct AV1HW_s *hw)
+{
+ struct AV1_Common_s *const cm = &hw->pbi->common;
+ struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
+ int i;
+ for (i = 0; i < hw->used_buf_num; ++i) {
+ if ((frame_bufs[i].ref_count == 0) &&
+ (frame_bufs[i].buf.index != -1) &&
+ (frame_bufs[i].buf.mv_buf_index >= 0)
+ )
+ put_mv_buf(hw, &frame_bufs[i].buf.mv_buf_index);
+ }
+}
+
+#endif
+
+
+static int get_free_buf_count(struct AV1HW_s *hw)
+{
+ struct AV1_Common_s *const cm = &hw->pbi->common;
+ struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
+ int i;
+ int free_buf_count = 0;
+ for (i = 0; i < hw->used_buf_num; ++i)
+ if ((frame_bufs[i].ref_count == 0) &&
+ (frame_bufs[i].buf.vf_ref == 0) &&
+ (frame_bufs[i].buf.index != -1)
+ )
+ free_buf_count++;
+ return free_buf_count;
+}
+
+
+
+int aom_bufmgr_init(struct AV1HW_s *hw, struct BuffInfo_s *buf_spec_i,
+ struct buff_s *mc_buf_i) {
+ struct AV1_Common_s *cm = &hw->pbi->common;
+ if (debug)
+ pr_info("%s %d %p\n", __func__, __LINE__, hw->pbi);
+ hw->frame_count = 0;
+ hw->pic_count = 0;
+ hw->pre_stream_offset = 0;
+ spin_lock_init(&cm->buffer_pool->lock);
+ cm->prev_fb_idx = INVALID_IDX;
+ cm->new_fb_idx = INVALID_IDX;
+ hw->used_4k_num = -1;
+ cm->cur_fb_idx_mmu = INVALID_IDX;
+ pr_debug
+ ("After aom_bufmgr_init, prev_fb_idx : %d, new_fb_idx : %d\r\n",
+ cm->prev_fb_idx, cm->new_fb_idx);
+ hw->need_resync = 1;
+
+ cm->current_video_frame = 0;
+ hw->ready_for_new_data = 1;
+
+ /* private init */
+ hw->work_space_buf = buf_spec_i;
+ if (!hw->mmu_enable)
+ hw->mc_buf = mc_buf_i;
+
+ hw->rpm_addr = NULL;
+ hw->lmem_addr = NULL;
+
+ hw->use_cma_flag = 0;
+ hw->decode_idx = 0;
+ hw->result_done_count = 0;
+ /*int m_uiMaxCUWidth = 1<<7;*/
+ /*int m_uiMaxCUHeight = 1<<7;*/
+ hw->has_keyframe = 0;
+ hw->skip_flag = 0;
+ hw->wait_buf = 0;
+ hw->error_flag = 0;
+
+ hw->pts_mode = PTS_NORMAL;
+ hw->last_pts = 0;
+ hw->last_lookup_pts = 0;
+ hw->last_pts_us64 = 0;
+ hw->last_lookup_pts_us64 = 0;
+ hw->shift_byte_count = 0;
+ hw->shift_byte_count_lo = 0;
+ hw->shift_byte_count_hi = 0;
+ hw->pts_mode_switching_count = 0;
+ hw->pts_mode_recovery_count = 0;
+
+ hw->buf_num = 0;
+ hw->pic_num = 0;
+
+ return 0;
+}
+
+
+struct AV1HW_s av1_decoder;
+union param_u av1_param;
+
+/**************************************************
+ *
+ *AV1 buffer management end
+ *
+ ***************************************************
+ */
+
+
+#define HEVC_CM_BODY_START_ADDR 0x3626
+#define HEVC_CM_BODY_LENGTH 0x3627
+#define HEVC_CM_HEADER_LENGTH 0x3629
+#define HEVC_CM_HEADER_OFFSET 0x362b
+
+#define LOSLESS_COMPRESS_MODE
+
+/*#define DECOMP_HEADR_SURGENT*/
+#ifdef VP9_10B_NV21
+static u32 mem_map_mode = 2 /* 0:linear 1:32x32 2:64x32*/
+#else
+static u32 mem_map_mode; /* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */
+#endif
+static u32 enable_mem_saving = 1;
+static u32 force_w_h;
+
+static u32 force_fps;
+
+
+const u32 av1_version = 201602101;
+static u32 debug;
+static u32 radr;
+static u32 rval;
+static u32 pop_shorts;
+static u32 dbg_cmd;
+static u32 dbg_skip_decode_index;
+static u32 endian = 0xff0;
+#ifdef ERROR_HANDLE_DEBUG
+static u32 dbg_nal_skip_flag;
+ /* bit[0], skip vps; bit[1], skip sps; bit[2], skip pps */
+static u32 dbg_nal_skip_count;
+#endif
+/*for debug*/
+static u32 decode_pic_begin;
+static uint slice_parse_begin;
+static u32 step;
+#ifdef MIX_STREAM_SUPPORT
+static u32 buf_alloc_width = 4096;
+static u32 buf_alloc_height = 2304;
+static u32 av1_max_pic_w = 4096;
+static u32 av1_max_pic_h = 2304;
+
+static u32 dynamic_buf_num_margin;
+#else
+static u32 buf_alloc_width;
+static u32 buf_alloc_height;
+static u32 dynamic_buf_num_margin = 7;
+#endif
+static u32 buf_alloc_depth = 10;
+static u32 buf_alloc_size;
+/*
+ *bit[0]: 0,
+ * bit[1]: 0, always release cma buffer when stop
+ * bit[1]: 1, never release cma buffer when stop
+ *bit[0]: 1, when stop, release cma buffer if blackout is 1;
+ *do not release cma buffer is blackout is not 1
+ *
+ *bit[2]: 0, when start decoding, check current displayed buffer
+ * (only for buffer decoded by AV1) if blackout is 0
+ * 1, do not check current displayed buffer
+ *
+ *bit[3]: 1, if blackout is not 1, do not release current
+ * displayed cma buffer always.
+ */
+/* set to 1 for fast play;
+ * set to 8 for other case of "keep last frame"
+ */
+static u32 buffer_mode = 1;
+/* buffer_mode_dbg: debug only*/
+static u32 buffer_mode_dbg = 0xffff0000;
+/**/
+
+/*
+ *bit 0, 1: only display I picture;
+ *bit 1, 1: only decode I picture;
+ */
+static u32 i_only_flag;
+
+static u32 low_latency_flag;
+
+static u32 no_head;
+
+static u32 max_decoding_time;
+/*
+ *error handling
+ */
+/*error_handle_policy:
+ *bit 0: 0, auto skip error_skip_nal_count nals before error recovery;
+ *1, skip error_skip_nal_count nals before error recovery;
+ *bit 1 (valid only when bit0 == 1):
+ *1, wait vps/sps/pps after error recovery;
+ *bit 2 (valid only when bit0 == 0):
+ *0, auto search after error recovery (av1_recover() called);
+ *1, manual search after error recovery
+ *(change to auto search after get IDR: WRITE_VREG(NAL_SEARCH_CTL, 0x2))
+ *
+ *bit 4: 0, set error_mark after reset/recover
+ * 1, do not set error_mark after reset/recover
+ *bit 5: 0, check total lcu for every picture
+ * 1, do not check total lcu
+ *
+ */
+
+static u32 error_handle_policy;
+/*static u32 parser_sei_enable = 1;*/
+#define MAX_BUF_NUM_NORMAL 12
+#define MAX_BUF_NUM_LESS 10
+static u32 max_buf_num = MAX_BUF_NUM_NORMAL;
+#define MAX_BUF_NUM_SAVE_BUF 8
+
+static u32 run_ready_min_buf_num = 2;
+
+
+static DEFINE_MUTEX(vav1_mutex);
+#ifndef MULTI_INSTANCE_SUPPORT
+static struct device *cma_dev;
+#endif
+#define HEVC_DEC_STATUS_REG HEVC_ASSIST_SCRATCH_0
+#define HEVC_RPM_BUFFER HEVC_ASSIST_SCRATCH_1
+#define AOM_AV1_ADAPT_PROB_REG HEVC_ASSIST_SCRATCH_3
+#define AOM_AV1_MMU_MAP_BUFFER HEVC_ASSIST_SCRATCH_4 // changed to use HEVC_ASSIST_MMU_MAP_ADDR
+#define AOM_AV1_DAALA_TOP_BUFFER HEVC_ASSIST_SCRATCH_5
+#define HEVC_SAO_UP HEVC_ASSIST_SCRATCH_6
+#define HEVC_STREAM_SWAP_BUFFER HEVC_ASSIST_SCRATCH_7
+#define AOM_AV1_CDF_BUFFER_W HEVC_ASSIST_SCRATCH_8
+#define AOM_AV1_CDF_BUFFER_R HEVC_ASSIST_SCRATCH_9
+#define AOM_AV1_COUNT_SWAP_BUFFER HEVC_ASSIST_SCRATCH_A
+#define AOM_AV1_SEG_MAP_BUFFER_W AV1_SEG_W_ADDR // HEVC_ASSIST_SCRATCH_B
+#define AOM_AV1_SEG_MAP_BUFFER_R AV1_SEG_R_ADDR // HEVC_ASSIST_SCRATCH_C
+//#define HEVC_sao_vb_size HEVC_ASSIST_SCRATCH_B
+//#define HEVC_SAO_VB HEVC_ASSIST_SCRATCH_C
+//#define HEVC_SCALELUT HEVC_ASSIST_SCRATCH_D
+#define HEVC_WAIT_FLAG HEVC_ASSIST_SCRATCH_E
+#define RPM_CMD_REG HEVC_ASSIST_SCRATCH_F
+#define HEVC_STREAM_SWAP_TEST HEVC_ASSIST_SCRATCH_L
+
+#ifdef MULTI_INSTANCE_SUPPORT
+#define HEVC_DECODE_COUNT HEVC_ASSIST_SCRATCH_M
+#define HEVC_DECODE_SIZE HEVC_ASSIST_SCRATCH_N
+#else
+#define HEVC_DECODE_PIC_BEGIN_REG HEVC_ASSIST_SCRATCH_M
+#define HEVC_DECODE_PIC_NUM_REG HEVC_ASSIST_SCRATCH_N
+#endif
+#define AOM_AV1_SEGMENT_FEATURE VP9_QUANT_WR
+
+#define DEBUG_REG1 HEVC_ASSIST_SCRATCH_G
+#define DEBUG_REG2 HEVC_ASSIST_SCRATCH_H
+
+#define LMEM_DUMP_ADR HEVC_ASSIST_SCRATCH_I
+#define CUR_NAL_UNIT_TYPE HEVC_ASSIST_SCRATCH_J
+#define DECODE_STOP_POS HEVC_ASSIST_SCRATCH_K
+
+#define PIC_END_LCU_COUNT HEVC_ASSIST_SCRATCH_2
+
+/*
+ *ucode parser/search control
+ *bit 0: 0, header auto parse; 1, header manual parse
+ *bit 1: 0, auto skip for noneseamless stream; 1, no skip
+ *bit [3:2]: valid when bit1==0;
+ *0, auto skip nal before first vps/sps/pps/idr;
+ *1, auto skip nal before first vps/sps/pps
+ *2, auto skip nal before first vps/sps/pps,
+ * and not decode until the first I slice (with slice address of 0)
+ *
+ *3, auto skip before first I slice (nal_type >=16 && nal_type<=21)
+ *bit [15:4] nal skip count (valid when bit0 == 1 (manual mode) )
+ *bit [16]: for NAL_UNIT_EOS when bit0 is 0:
+ * 0, send SEARCH_DONE to arm ; 1, do not send SEARCH_DONE to arm
+ *bit [17]: for NAL_SEI when bit0 is 0:
+ * 0, do not parse SEI in ucode; 1, parse SEI in ucode
+ *bit [31:20]: used by ucode for debug purpose
+ */
+#define NAL_SEARCH_CTL HEVC_ASSIST_SCRATCH_I
+ /*[31:24] chip feature
+ 31: 0, use MBOX1; 1, use MBOX0
+ [24:16] debug
+ 0x1, bufmgr only
+ */
+#define DECODE_MODE HEVC_ASSIST_SCRATCH_J
+#define DECODE_STOP_POS HEVC_ASSIST_SCRATCH_K
+
+#define RPM_BUF_SIZE ((RPM_END - RPM_BEGIN) * 2)
+#define LMEM_BUF_SIZE (0x600 * 2)
+
+#ifdef MAP_8K
+static u32 seg_map_size = 0xd8000;
+#else
+static u32 seg_map_size = 0x36000;
+#endif
+
+#define WORK_BUF_SPEC_NUM 2
+static struct BuffInfo_s aom_workbuff_spec[WORK_BUF_SPEC_NUM]={
+ { //8M bytes
+ .max_width = 1920,
+ .max_height = 1088,
+ .ipp = {
+ // IPP work space calculation : 4096 * (Y+CbCr+Flags) = 12k, round to 16k
+ .buf_size = 0x4000,
+ },
+ .sao_abv = {
+ .buf_size = 0x30000,
+ },
+ .sao_vb = {
+ .buf_size = 0x30000,
+ },
+ .short_term_rps = {
+ // SHORT_TERM_RPS - Max 64 set, 16 entry every set, total 64x16x2 = 2048 bytes (0x800)
+ .buf_size = 0x800,
+ },
+ .vps = {
+ // VPS STORE AREA - Max 16 VPS, each has 0x80 bytes, total 0x0800 bytes
+ .buf_size = 0x800,
+ },
+ .seg_map = {
+ // SEGMENT MAP AREA - 1920x1088/4/4 * 3 bits = 0xBF40 Bytes * 16 = 0xBF400
+ .buf_size = 0xBF400,
+ },
+ .daala_top = {
+ // DAALA TOP STORE AREA - 224 Bytes (use 256 Bytes for LPDDR4) per 128. Total 4096/128*256 = 0x2000
+ .buf_size = 0x2000,
+ },
+ .sao_up = {
+ // SAO UP STORE AREA - Max 640(10240/16) LCU, each has 16 bytes total 0x2800 bytes
+ .buf_size = 0x2800,
+ },
+ .swap_buf = {
+ // 256cyclex64bit = 2K bytes 0x800 (only 144 cycles valid)
+ .buf_size = 0x800,
+ },
+ .cdf_buf = {
+ // for context store/load 1024x256 x16 = 512K bytes 16*0x8000
+ .buf_size = 0x80000,
+ },
+ .gmc_buf = {
+ // for gmc_parameter store/load 128 x 16 = 2K bytes 0x800
+ .buf_size = 0x800,
+ },
+ .scalelut = {
+ // support up to 32 SCALELUT 1024x32 = 32Kbytes (0x8000)
+ .buf_size = 0x8000,
+ },
+ .dblk_para = {
+ // DBLK -> Max 256(4096/16) LCU, each para 1024bytes(total:0x40000), data 1024bytes(total:0x40000)
+ .buf_size = 0x80000,
+ },
+ .dblk_data = {
+ .buf_size = 0x80000,
+ },
+ .cdef_data = {
+ .buf_size = 0x40000,
+ },
+ .ups_data = {
+ .buf_size = 0x60000,
+ },
+ .fgs_table = {
+ .buf_size = FGS_TABLE_SIZE * FRAME_BUFFERS, // 512x128bits
+ },
+#ifdef AOM_AV1_MMU
+#define VBH_BUF_SIZE (2 * 16 * 2304)
+#define VBH_BUF_COUNT 4
+ .mmu_vbh = {
+ .buf_size = VBH_BUF_SIZE * VBH_BUF_COUNT,
+ //.buf_size = 0x5000, //2*16*(more than 2304)/4, 4K
+ },
+ .cm_header = {
+ //.buf_size = MMU_COMPRESS_HEADER_SIZE*8, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
+ .buf_size = MMU_COMPRESS_HEADER_SIZE*FRAME_BUFFERS, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
+ },
+#endif
+#ifdef AOM_AV1_MMU_DW
+ .mmu_vbh_dw = {
+ .buf_size = VBH_BUF_SIZE * VBH_BUF_COUNT,
+ //.buf_size = 0x5000, //2*16*(more than 2304)/4, 4K
+ },
+ .cm_header_dw = {
+ //.buf_size = MMU_COMPRESS_HEADER_SIZE*8, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
+ .buf_size = MMU_COMPRESS_HEADER_SIZE_DW*FRAME_BUFFERS, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
+ },
+#endif
+ .mpred_above = {
+ .buf_size = 0x10000, /* 2 * size of hevc*/
+ },
+#ifdef MV_USE_FIXED_BUF
+ .mpred_mv = {
+ .buf_size = 0x40000*FRAME_BUFFERS, //1080p, 0x40000 per buffer
+ },
+#endif
+ .rpm = {
+ .buf_size = 0x80*2,
+ },
+ .lmem = {
+ .buf_size = 0x400 * 2,
+ }
+ },
+ {
+#ifdef VPU_FILMGRAIN_DUMP
+ .max_width = 640,
+ .max_height = 480,
+#else
+ .max_width = 4096,
+ .max_height = 2304,
+#endif
+ .ipp = {
+ // IPP work space calculation : 4096 * (Y+CbCr+Flags) = 12k, round to 16k
+ .buf_size = 0x4000,
+ },
+ .sao_abv = {
+ .buf_size = 0x30000,
+ },
+ .sao_vb = {
+ .buf_size = 0x30000,
+ },
+ .short_term_rps = {
+ // SHORT_TERM_RPS - Max 64 set, 16 entry every set, total 64x16x2 = 2048 bytes (0x800)
+ .buf_size = 0x800,
+ },
+ .vps = {
+ // VPS STORE AREA - Max 16 VPS, each has 0x80 bytes, total 0x0800 bytes
+ .buf_size = 0x800,
+ },
+ .seg_map = {
+ // SEGMENT MAP AREA - 4096x2304/4/4 * 3 bits = 0x36000 Bytes * 16 = 0x360000
+ .buf_size = 0x360000,
+ },
+ .daala_top = {
+ // DAALA TOP STORE AREA - 224 Bytes (use 256 Bytes for LPDDR4) per 128. Total 4096/128*256 = 0x2000
+ .buf_size = 0x2000,
+ },
+ .sao_up = {
+ // SAO UP STORE AREA - Max 640(10240/16) LCU, each has 16 bytes total 0x2800 bytes
+ .buf_size = 0x2800,
+ },
+ .swap_buf = {
+ // 256cyclex64bit = 2K bytes 0x800 (only 144 cycles valid)
+ .buf_size = 0x800,
+ },
+ .cdf_buf = {
+ // for context store/load 1024x256 x16 = 512K bytes 16*0x8000
+ .buf_size = 0x80000,
+ },
+ .gmc_buf = {
+ // for gmc_parameter store/load 128 x 16 = 2K bytes 0x800
+ .buf_size = 0x800,
+ },
+ .scalelut = {
+ // support up to 32 SCALELUT 1024x32 = 32Kbytes (0x8000)
+ .buf_size = 0x8000,
+ },
+ .dblk_para = {
+ // DBLK -> Max 256(4096/16) LCU, each para 1024bytes(total:0x40000), data 1024bytes(total:0x40000)
+ .buf_size = 0x80000,
+ },
+ .dblk_data = {
+ .buf_size = 0x80000,
+ },
+ .cdef_data = {
+ .buf_size = 0x40000,
+ },
+ .ups_data = {
+ .buf_size = 0x60000,
+ },
+ .fgs_table = {
+ .buf_size = FGS_TABLE_SIZE * FRAME_BUFFERS, // 512x128bits
+ },
+#ifdef AOM_AV1_MMU
+ .mmu_vbh = {
+ .buf_size = VBH_BUF_SIZE * VBH_BUF_COUNT,
+ //.buf_size = 0x5000, //2*16*(more than 2304)/4, 4K
+ },
+ .cm_header = {
+ //.buf_size = MMU_COMPRESS_HEADER_SIZE*8, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
+ .buf_size = MMU_COMPRESS_HEADER_SIZE*FRAME_BUFFERS, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
+ },
+#endif
+#ifdef AOM_AV1_MMU_DW
+ .mmu_vbh_dw = {
+ .buf_size = VBH_BUF_SIZE * VBH_BUF_COUNT,
+ //.buf_size = 0x5000, //2*16*(more than 2304)/4, 4K
+ },
+ .cm_header_dw = {
+ //.buf_size = MMU_COMPRESS_HEADER_SIZE*8, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
+ .buf_size = MMU_COMPRESS_HEADER_SIZE_DW*FRAME_BUFFERS, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
+ },
+#endif
+ .mpred_above = {
+ .buf_size = 0x10000, /* 2 * size of hevc*/
+ },
+#ifdef MV_USE_FIXED_BUF
+ .mpred_mv = {
+ /* .buf_size = 0x100000*16,
+ //4k2k , 0x100000 per buffer */
+ /* 4096x2304 , 0x120000 per buffer */
+#if (defined MAP_8K)
+#define MAX_ONE_MV_BUFFER_SIZE 0x260000
+#else
+#define MAX_ONE_MV_BUFFER_SIZE 0x130000
+#endif
+ .buf_size = MAX_ONE_MV_BUFFER_SIZE * FRAME_BUFFERS,
+ },
+#endif
+ .rpm = {
+ .buf_size = 0x80*2,
+ },
+ .lmem = {
+ .buf_size = 0x400 * 2,
+ }
+
+ }
+};
+
+
+/*Losless compression body buffer size 4K per 64x32 (jt)*/
+static int compute_losless_comp_body_size(int width, int height,
+ uint8_t is_bit_depth_10)
+{
+ int width_x64;
+ int height_x32;
+ int bsize;
+
+ width_x64 = width + 63;
+ width_x64 >>= 6;
+ height_x32 = height + 31;
+ height_x32 >>= 5;
+ bsize = (is_bit_depth_10?4096:3200)*width_x64*height_x32;
+ if (debug & VP9_DEBUG_BUFMGR_MORE)
+ pr_info("%s(%d,%d,%d)=>%d\n",
+ __func__, width, height,
+ is_bit_depth_10, bsize);
+
+ return bsize;
+}
+
+/* Losless compression header buffer size 32bytes per 128x64 (jt)*/
+static int compute_losless_comp_header_size(int width, int height)
+{
+ int width_x128;
+ int height_x64;
+ int hsize;
+
+ width_x128 = width + 127;
+ width_x128 >>= 7;
+ height_x64 = height + 63;
+ height_x64 >>= 6;
+
+ hsize = 32 * width_x128 * height_x64;
+ if (debug & VP9_DEBUG_BUFMGR_MORE)
+ pr_info("%s(%d,%d)=>%d\n",
+ __func__, width, height,
+ hsize);
+
+ return hsize;
+}
+
+#ifdef AOM_AV1_MMU_DW
+static int compute_losless_comp_body_size_dw(int width, int height,
+ uint8_t is_bit_depth_10)
+{
+
+ return compute_losless_comp_body_size(width, height, is_bit_depth_10);
+}
+
+/* Losless compression header buffer size 32bytes per 128x64 (jt)*/
+static int compute_losless_comp_header_size_dw(int width, int height)
+{
+ return compute_losless_comp_header_size(width, height);
+}
+#endif
+
+static void init_buff_spec(struct AV1HW_s *hw,
+ struct BuffInfo_s *buf_spec)
+{
+ void *mem_start_virt;
+
+ buf_spec->ipp.buf_start =
+ buf_spec->start_adr;
+ buf_spec->sao_abv.buf_start =
+ buf_spec->ipp.buf_start + buf_spec->ipp.buf_size;
+
+ buf_spec->sao_vb.buf_start =
+ buf_spec->sao_abv.buf_start + buf_spec->sao_abv.buf_size;
+ buf_spec->short_term_rps.buf_start =
+ buf_spec->sao_vb.buf_start + buf_spec->sao_vb.buf_size;
+ buf_spec->vps.buf_start =
+ buf_spec->short_term_rps.buf_start + buf_spec->short_term_rps.buf_size;
+ buf_spec->seg_map.buf_start =
+ buf_spec->vps.buf_start + buf_spec->vps.buf_size;
+ buf_spec->daala_top.buf_start =
+ buf_spec->seg_map.buf_start + buf_spec->seg_map.buf_size;
+ buf_spec->sao_up.buf_start =
+ buf_spec->daala_top.buf_start + buf_spec->daala_top.buf_size;
+ buf_spec->swap_buf.buf_start =
+ buf_spec->sao_up.buf_start + buf_spec->sao_up.buf_size;
+ buf_spec->cdf_buf.buf_start =
+ buf_spec->swap_buf.buf_start + buf_spec->swap_buf.buf_size;
+ buf_spec->gmc_buf.buf_start =
+ buf_spec->cdf_buf.buf_start + buf_spec->cdf_buf.buf_size;
+ buf_spec->scalelut.buf_start =
+ buf_spec->gmc_buf.buf_start + buf_spec->gmc_buf.buf_size;
+ buf_spec->dblk_para.buf_start =
+ buf_spec->scalelut.buf_start + buf_spec->scalelut.buf_size;
+ buf_spec->dblk_data.buf_start =
+ buf_spec->dblk_para.buf_start + buf_spec->dblk_para.buf_size;
+ buf_spec->cdef_data.buf_start =
+ buf_spec->dblk_data.buf_start + buf_spec->dblk_data.buf_size;
+ buf_spec->ups_data.buf_start =
+ buf_spec->cdef_data.buf_start + buf_spec->cdef_data.buf_size;
+ buf_spec->fgs_table.buf_start =
+ buf_spec->ups_data.buf_start + buf_spec->ups_data.buf_size;
+#ifdef AOM_AV1_MMU
+ buf_spec->mmu_vbh.buf_start =
+ buf_spec->fgs_table.buf_start + buf_spec->fgs_table.buf_size;
+ buf_spec->cm_header.buf_start =
+ buf_spec->mmu_vbh.buf_start + buf_spec->mmu_vbh.buf_size;
+#ifdef AOM_AV1_MMU_DW
+ buf_spec->mmu_vbh_dw.buf_start =
+ buf_spec->cm_header.buf_start + buf_spec->cm_header.buf_size;
+ buf_spec->cm_header_dw.buf_start =
+ buf_spec->mmu_vbh_dw.buf_start + buf_spec->mmu_vbh_dw.buf_size;
+ buf_spec->mpred_above.buf_start =
+ buf_spec->cm_header_dw.buf_start + buf_spec->cm_header_dw.buf_size;
+#else
+ buf_spec->mpred_above.buf_start =
+ buf_spec->cm_header.buf_start + buf_spec->cm_header.buf_size;
+#endif
+#else
+ buf_spec->mpred_above.buf_start =
+ buf_spec->fgs_table.buf_start + buf_spec->fgs_table.buf_size;
+#endif
+
+#ifdef MV_USE_FIXED_BUF
+ buf_spec->mpred_mv.buf_start =
+ buf_spec->mpred_above.buf_start +
+ buf_spec->mpred_above.buf_size;
+
+ buf_spec->rpm.buf_start =
+ buf_spec->mpred_mv.buf_start +
+ buf_spec->mpred_mv.buf_size;
+#else
+ buf_spec->rpm.buf_start =
+ buf_spec->mpred_above.buf_start +
+ buf_spec->mpred_above.buf_size;
+
+#endif
+ buf_spec->lmem.buf_start =
+ buf_spec->rpm.buf_start +
+ buf_spec->rpm.buf_size;
+ buf_spec->end_adr =
+ buf_spec->lmem.buf_start +
+ buf_spec->lmem.buf_size;
+
+ if (!hw)
+ return;
+
+ if (!vdec_secure(hw_to_vdec(hw))) {
+ mem_start_virt =
+ codec_mm_phys_to_virt(buf_spec->dblk_para.buf_start);
+ if (mem_start_virt) {
+ memset(mem_start_virt, 0,
+ buf_spec->dblk_para.buf_size);
+ codec_mm_dma_flush(mem_start_virt,
+ buf_spec->dblk_para.buf_size,
+ DMA_TO_DEVICE);
+ } else {
+ mem_start_virt = codec_mm_vmap(
+ buf_spec->dblk_para.buf_start,
+ buf_spec->dblk_para.buf_size);
+ if (mem_start_virt) {
+ memset(mem_start_virt, 0,
+ buf_spec->dblk_para.buf_size);
+ codec_mm_dma_flush(mem_start_virt,
+ buf_spec->dblk_para.buf_size,
+ DMA_TO_DEVICE);
+ codec_mm_unmap_phyaddr(mem_start_virt);
+ } else {
+ /*not virt for tvp playing,
+ may need clear on ucode.*/
+ pr_err("mem_start_virt failed\n");
+ }
+ }
+ }
+
+ if (debug) {
+ pr_info("%s workspace (%x %x) size = %x\n", __func__,
+ buf_spec->start_adr, buf_spec->end_adr,
+ buf_spec->end_adr - buf_spec->start_adr);
+ }
+
+ if (debug) {
+ pr_info("ipp.buf_start :%x\n",
+ buf_spec->ipp.buf_start);
+ pr_info("sao_abv.buf_start :%x\n",
+ buf_spec->sao_abv.buf_start);
+ pr_info("sao_vb.buf_start :%x\n",
+ buf_spec->sao_vb.buf_start);
+ pr_info("short_term_rps.buf_start :%x\n",
+ buf_spec->short_term_rps.buf_start);
+ pr_info("vps.buf_start :%x\n",
+ buf_spec->vps.buf_start);
+ pr_info("seg_map.buf_start :%x\n",
+ buf_spec->seg_map.buf_start);
+ pr_info("daala_top.buf_start :%x\n",
+ buf_spec->daala_top.buf_start);
+ pr_info("swap_buf.buf_start :%x\n",
+ buf_spec->swap_buf.buf_start);
+ pr_info("cdf_buf.buf_start :%x\n",
+ buf_spec->cdf_buf.buf_start);
+ pr_info("gmc_buf.buf_start :%x\n",
+ buf_spec->gmc_buf.buf_start);
+ pr_info("scalelut.buf_start :%x\n",
+ buf_spec->scalelut.buf_start);
+ pr_info("dblk_para.buf_start :%x\n",
+ buf_spec->dblk_para.buf_start);
+ pr_info("dblk_data.buf_start :%x\n",
+ buf_spec->dblk_data.buf_start);
+ pr_info("cdef_data.buf_start :%x\n",
+ buf_spec->cdef_data.buf_start);
+ pr_info("ups_data.buf_start :%x\n",
+ buf_spec->ups_data.buf_start);
+
+#ifdef AOM_AV1_MMU
+ pr_info("mmu_vbh.buf_start :%x\n",
+ buf_spec->mmu_vbh.buf_start);
+#endif
+ pr_info("mpred_above.buf_start :%x\n",
+ buf_spec->mpred_above.buf_start);
+#ifdef MV_USE_FIXED_BUF
+ pr_info("mpred_mv.buf_start :%x\n",
+ buf_spec->mpred_mv.buf_start);
+#endif
+ if ((debug & AOM_AV1_DEBUG_SEND_PARAM_WITH_REG) == 0) {
+ pr_info("rpm.buf_start :%x\n",
+ buf_spec->rpm.buf_start);
+ }
+ }
+}
+
+
+
+static void uninit_mmu_buffers(struct AV1HW_s *hw)
+{
+#ifndef MV_USE_FIXED_BUF
+ dealloc_mv_bufs(hw);
+#endif
+ if (hw->mmu_box)
+ decoder_mmu_box_free(hw->mmu_box);
+ hw->mmu_box = NULL;
+
+#ifdef AOM_AV1_MMU_DW
+ if (hw->mmu_box_dw)
+ decoder_mmu_box_free(hw->mmu_box_dw);
+ hw->mmu_box_dw = NULL;
+#endif
+ if (hw->bmmu_box)
+ decoder_bmmu_box_free(hw->bmmu_box);
+ hw->bmmu_box = NULL;
+}
+
+
+static int config_pic(struct AV1HW_s *hw,
+ struct PIC_BUFFER_CONFIG_s *pic_config)
+{
+ int ret = -1;
+ int i;
+ int pic_width = hw->init_pic_w;
+ int pic_height = hw->init_pic_h;
+ //int lcu_size = ((params->p.seq_flags >> 6) & 0x1) ? 128 : 64;
+ int lcu_size = hw->current_lcu_size;
+
+ int pic_width_64 = (pic_width + 63) & (~0x3f);
+ int pic_height_32 = (pic_height + 31) & (~0x1f);
+ int pic_width_lcu = (pic_width_64 % lcu_size) ?
+ pic_width_64 / lcu_size + 1
+ : pic_width_64 / lcu_size;
+ int pic_height_lcu = (pic_height_32 % lcu_size) ?
+ pic_height_32 / lcu_size + 1
+ : pic_height_32 / lcu_size;
+ int lcu_total = pic_width_lcu * pic_height_lcu;
+#ifdef MV_USE_FIXED_BUF
+ u32 mpred_mv_end = hw->work_space_buf->mpred_mv.buf_start +
+ hw->work_space_buf->mpred_mv.buf_size;
+#ifdef USE_DYNAMIC_MV_BUFFER
+ int32_t MV_MEM_UNIT = (lcu_size == 128) ? (19*4*16) : (19*16);
+ int32_t mv_buffer_size = (lcu_total*MV_MEM_UNIT);
+#else
+ int32_t mv_buffer_size = MAX_ONE_MV_BUFFER_SIZE;
+#endif
+
+#endif
+
+ u32 y_adr = 0;
+ int buf_size = 0;
+
+ int losless_comp_header_size =
+ compute_losless_comp_header_size(pic_width,
+ pic_height);
+ int losless_comp_body_size = compute_losless_comp_body_size(pic_width,
+ pic_height, buf_alloc_depth == 10);
+ int mc_buffer_size = losless_comp_header_size + losless_comp_body_size;
+ int mc_buffer_size_h = (mc_buffer_size + 0xffff) >> 16;
+ int mc_buffer_size_u_v = 0;
+ int mc_buffer_size_u_v_h = 0;
+ int dw_mode = get_double_write_mode_init(hw);
+ struct vdec_v4l2_buffer *fb = NULL;
+
+ hw->lcu_total = lcu_total;
+
+ if (dw_mode && (dw_mode & 0x20) == 0) {
+ int pic_width_dw = pic_width /
+ get_double_write_ratio(hw, dw_mode);
+ int pic_height_dw = pic_height /
+ get_double_write_ratio(hw, dw_mode);
+
+ int pic_width_64_dw = (pic_width_dw + 63) & (~0x3f);
+ int pic_height_32_dw = (pic_height_dw + 31) & (~0x1f);
+ int pic_width_lcu_dw = (pic_width_64_dw % lcu_size) ?
+ pic_width_64_dw / lcu_size + 1
+ : pic_width_64_dw / lcu_size;
+ int pic_height_lcu_dw = (pic_height_32_dw % lcu_size) ?
+ pic_height_32_dw / lcu_size + 1
+ : pic_height_32_dw / lcu_size;
+ int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw;
+ mc_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2;
+ mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff) >> 16;
+ /*64k alignment*/
+ buf_size = ((mc_buffer_size_u_v_h << 16) * 3);
+ buf_size = ((buf_size + 0xffff) >> 16) << 16;
+ }
+
+ if (mc_buffer_size & 0xffff) /*64k alignment*/
+ mc_buffer_size_h += 1;
+ if ((!hw->mmu_enable) && ((dw_mode & 0x10) == 0))
+ buf_size += (mc_buffer_size_h << 16);
+
+#ifdef USE_SPEC_BUF_FOR_MMU_HEAD
+ if (hw->mmu_enable) {
+ pic_config->header_adr =
+ hw->work_space_buf->cm_header.buf_start +
+ (pic_config->index * MMU_COMPRESS_HEADER_SIZE);
+
+#ifdef AOM_AV1_MMU_DW
+ if (hw->dw_mmu_enable) {
+ pic_config->header_dw_adr =
+ hw->work_space_buf->cm_header_dw.buf_start +
+ (pic_config->index * MMU_COMPRESS_HEADER_SIZE_DW);
+
+ }
+#endif
+ }
+
+#else
+/*!USE_SPEC_BUF_FOR_MMU_HEAD*/
+ if (hw->mmu_enable) {
+ pic_config->header_adr = decoder_bmmu_box_get_phy_addr(
+ hw->bmmu_box, HEADER_BUFFER_IDX(pic_config->index));
+
+#ifdef AOM_AV1_MMU_DW
+ if (hw->dw_mmu_enable) {
+ pic_config->header_dw_adr = decoder_bmmu_box_get_phy_addr(
+ hw->bmmu_box, DW_HEADER_BUFFER_IDX(pic_config->index));
+
+ }
+ if (debug & VP9_DEBUG_BUFMGR_MORE) {
+ pr_info("MMU dw header_adr (%d, %d) %d: %d\n",
+ hw->dw_mmu_enable,
+ DW_HEADER_BUFFER_IDX(pic_config->index),
+ pic_config->index,
+ pic_config->header_dw_adr);
+ }
+#endif
+
+ if (debug & VP9_DEBUG_BUFMGR_MORE) {
+ pr_info("MMU header_adr %d: %d\n",
+ pic_config->index, pic_config->header_adr);
+ }
+ }
+#endif
+
+ i = pic_config->index;
+#ifdef MV_USE_FIXED_BUF
+ if ((hw->work_space_buf->mpred_mv.buf_start +
+ ((i + 1) * mv_buffer_size))
+ <= mpred_mv_end
+ ) {
+#endif
+ if (buf_size > 0) {
+ if (hw->is_used_v4l) {
+#ifdef SUPPORT_V4L2
+ ret = vdec_v4l_get_buffer(hw->v4l2_ctx, &fb);
+#endif
+ if (ret) {
+ av1_print(hw, PRINT_FLAG_ERROR,
+ "[%d] get fb fail.\n",
+ ((struct aml_vcodec_ctx *)
+ (hw->v4l2_ctx))->id);
+ return ret;
+ }
+
+ hw->m_BUF[i].v4l_ref_buf_addr = (ulong)fb;
+#ifdef SUPPORT_V4L2
+ pic_config->cma_alloc_addr = fb->m.mem[0].addr;
+#endif
+ av1_print(hw, PRINT_FLAG_V4L_DETAIL,
+ "[%d] %s(), v4l ref buf addr: 0x%x\n",
+ ((struct aml_vcodec_ctx *)
+ (hw->v4l2_ctx))->id, __func__, fb);
+ } else {
+ ret = decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box,
+ VF_BUFFER_IDX(i),
+ buf_size, DRIVER_NAME,
+ &pic_config->cma_alloc_addr);
+ if (ret < 0) {
+ pr_info(
+ "decoder_bmmu_box_alloc_buf_phy idx %d size %d fail\n",
+ VF_BUFFER_IDX(i),
+ buf_size
+ );
+ return ret;
+ }
+ }
+
+ if (pic_config->cma_alloc_addr)
+ y_adr = pic_config->cma_alloc_addr;
+ else {
+ pr_info(
+ "decoder_bmmu_box_alloc_buf_phy idx %d size %d return null\n",
+ VF_BUFFER_IDX(i),
+ buf_size
+ );
+ return -1;
+ }
+ }
+ {
+ /*ensure get_pic_by_POC()
+ not get the buffer not decoded*/
+ pic_config->BUF_index = i;
+ pic_config->lcu_total = lcu_total;
+
+ pic_config->comp_body_size = losless_comp_body_size;
+ pic_config->buf_size = buf_size;
+
+ pic_config->mc_canvas_y = pic_config->index;
+ pic_config->mc_canvas_u_v = pic_config->index;
+ if (dw_mode & 0x10) {
+ pic_config->dw_y_adr = y_adr;
+ pic_config->dw_u_v_adr = y_adr +
+ ((mc_buffer_size_u_v_h << 16) << 1);
+
+ pic_config->mc_canvas_y =
+ (pic_config->index << 1);
+ pic_config->mc_canvas_u_v =
+ (pic_config->index << 1) + 1;
+ } else if (dw_mode && (dw_mode & 0x20) == 0) {
+ pic_config->dw_y_adr = y_adr;
+ pic_config->dw_u_v_adr = pic_config->dw_y_adr +
+ ((mc_buffer_size_u_v_h << 16) << 1);
+ }
+#ifdef MV_USE_FIXED_BUF
+ pic_config->mpred_mv_wr_start_addr =
+ hw->work_space_buf->mpred_mv.buf_start +
+ (pic_config->index * mv_buffer_size);
+#endif
+ pic_config->fgs_table_adr =
+ hw->work_space_buf->fgs_table.buf_start +
+ (pic_config->index * FGS_TABLE_SIZE);
+
+ if (debug) {
+ pr_info
+ ("%s index %d BUF_index %d ",
+ __func__, pic_config->index,
+ pic_config->BUF_index);
+ pr_info
+ ("comp_body_size %x comp_buf_size %x ",
+ pic_config->comp_body_size,
+ pic_config->buf_size);
+ pr_info
+ ("mpred_mv_wr_start_adr %d\n",
+ pic_config->mpred_mv_wr_start_addr);
+ pr_info("dw_y_adr %d, pic_config->dw_u_v_adr =%d\n",
+ pic_config->dw_y_adr,
+ pic_config->dw_u_v_adr);
+ }
+ ret = 0;
+ }
+#ifdef MV_USE_FIXED_BUF
+ }
+#endif
+ return ret;
+}
+
+#ifndef USE_SPEC_BUF_FOR_MMU_HEAD
+static int vav1_mmu_compress_header_size(struct AV1HW_s *hw)
+{
+ if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
+ IS_8K_SIZE(hw->max_pic_w, hw->max_pic_h))
+ return (MMU_COMPRESS_8K_HEADER_SIZE);
+
+ return (MMU_COMPRESS_HEADER_SIZE);
+}
+#endif
+/*#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)*/
+static int vav1_frame_mmu_map_size(struct AV1HW_s *hw)
+{
+ if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
+ IS_8K_SIZE(hw->max_pic_w, hw->max_pic_h))
+ return (MAX_FRAME_8K_NUM * 4);
+
+ return (MAX_FRAME_4K_NUM * 4);
+}
+
+#ifdef AOM_AV1_MMU_DW
+static int vaom_dw_frame_mmu_map_size(struct AV1HW_s *hw)
+{
+ if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
+ IS_8K_SIZE(hw->max_pic_w, hw->max_pic_h))
+ return (MAX_FRAME_8K_NUM * 4);
+
+ return (MAX_FRAME_4K_NUM * 4);
+}
+#endif
+
+static void init_pic_list(struct AV1HW_s *hw)
+{
+ int i;
+ struct AV1_Common_s *cm = &hw->pbi->common;
+ struct PIC_BUFFER_CONFIG_s *pic_config;
+ struct vdec_s *vdec = hw_to_vdec(hw);
+
+#ifndef USE_SPEC_BUF_FOR_MMU_HEAD
+ u32 header_size;
+ if (hw->mmu_enable && ((hw->double_write_mode & 0x10) == 0)) {
+ header_size = vav1_mmu_compress_header_size(hw);
+ /*alloc AV1 compress header first*/
+ for (i = 0; i < hw->used_buf_num; i++) {
+ unsigned long buf_addr;
+ if (decoder_bmmu_box_alloc_buf_phy
+ (hw->bmmu_box,
+ HEADER_BUFFER_IDX(i), header_size,
+ DRIVER_HEADER_NAME,
+ &buf_addr) < 0) {
+ av1_print(hw, 0, "%s malloc compress header failed %d\n",
+ DRIVER_HEADER_NAME, i);
+ hw->fatal_error |= DECODER_FATAL_ERROR_NO_MEM;
+ return;
+ }
+#ifdef AOM_AV1_MMU_DW
+ if (hw->dw_mmu_enable) {
+ if (decoder_bmmu_box_alloc_buf_phy
+ (hw->bmmu_box,
+ DW_HEADER_BUFFER_IDX(i), header_size,
+ DRIVER_HEADER_NAME,
+ &buf_addr) < 0) {
+ av1_print(hw, 0, "%s malloc compress dw header failed %d\n",
+ DRIVER_HEADER_NAME, i);
+ hw->fatal_error |= DECODER_FATAL_ERROR_NO_MEM;
+ return;
+ }
+ }
+#endif
+ }
+ }
+#endif
+ for (i = 0; i < hw->used_buf_num; i++) {
+ pic_config = &cm->buffer_pool->frame_bufs[i].buf;
+ pic_config->index = i;
+ pic_config->BUF_index = -1;
+ pic_config->mv_buf_index = -1;
+ if (vdec->parallel_dec == 1) {
+ pic_config->y_canvas_index = -1;
+ pic_config->uv_canvas_index = -1;
+ }
+ if (config_pic(hw, pic_config) < 0) {
+ if (debug)
+ av1_print(hw, 0, "Config_pic %d fail\n",
+ pic_config->index);
+ pic_config->index = -1;
+ break;
+ }
+ pic_config->y_crop_width = hw->init_pic_w;
+ pic_config->y_crop_height = hw->init_pic_h;
+ pic_config->double_write_mode = get_double_write_mode(hw);
+
+ if (pic_config->double_write_mode &&
+ (pic_config->double_write_mode & 0x20) == 0) {
+ set_canvas(hw, pic_config);
+ }
+ }
+ for (; i < hw->used_buf_num; i++) {
+ pic_config = &cm->buffer_pool->frame_bufs[i].buf;
+ pic_config->index = -1;
+ pic_config->BUF_index = -1;
+ pic_config->mv_buf_index = -1;
+ if (vdec->parallel_dec == 1) {
+ pic_config->y_canvas_index = -1;
+ pic_config->uv_canvas_index = -1;
+ }
+ }
+ av1_print(hw, VP9_DEBUG_BUFMGR, "%s ok, used_buf_num = %d\n",
+ __func__, hw->used_buf_num);
+
+}
+
+static void init_pic_list_hw(struct AV1HW_s *hw)
+{
+ int i;
+ struct AV1_Common_s *cm = &hw->pbi->common;
+ struct PIC_BUFFER_CONFIG_s *pic_config;
+ /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x0);*/
+ WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
+ (0x1 << 1) | (0x1 << 2));
+
+
+ for (i = 0; i < hw->used_buf_num; i++) {
+ pic_config = &cm->buffer_pool->frame_bufs[i].buf;
+ if (pic_config->index < 0)
+ break;
+
+ if (hw->mmu_enable && ((pic_config->double_write_mode & 0x10) == 0)) {
+
+ WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
+ pic_config->header_adr >> 5);
+ } else {
+ /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
+ * pic_config->mc_y_adr
+ * | (pic_config->mc_canvas_y << 8) | 0x1);
+ */
+ WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
+ pic_config->dw_y_adr >> 5);
+ }
+#ifndef LOSLESS_COMPRESS_MODE
+ /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
+ * pic_config->mc_u_v_adr
+ * | (pic_config->mc_canvas_u_v << 8)| 0x1);
+ */
+ WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
+ pic_config->dw_u_v_adr >> 5);
+#else
+ if (pic_config->double_write_mode & 0x10) {
+ WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
+ pic_config->dw_u_v_adr >> 5);
+ }
+#endif
+ }
+ WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
+
+#ifdef CHANGE_REMOVED
+ /*Zero out canvas registers in IPP -- avoid simulation X*/
+ WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
+ (0 << 8) | (0 << 1) | 1);
+#else
+ WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
+ (1 << 8) | (0 << 1) | 1);
+#endif
+ for (i = 0; i < 32; i++)
+ WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
+}
+
+
+static void dump_pic_list(struct AV1HW_s *hw)
+{
+ struct AV1_Common_s *const cm = &hw->pbi->common;
+ struct PIC_BUFFER_CONFIG_s *pic_config;
+ int i;
+ for (i = 0; i < FRAME_BUFFERS; i++) {
+ pic_config = &cm->buffer_pool->frame_bufs[i].buf;
+ av1_print(hw, 0,
+ "Buf(%d) index %d mv_buf_index %d ref_count %d vf_ref %d dec_idx %d slice_type %d w/h %d/%d adr%ld\n",
+ i,
+ pic_config->index,
+#ifndef MV_USE_FIXED_BUF
+ pic_config->mv_buf_index,
+#else
+ -1,
+#endif
+ cm->buffer_pool->
+ frame_bufs[i].ref_count,
+ pic_config->vf_ref,
+ pic_config->decode_idx,
+ pic_config->slice_type,
+ pic_config->y_crop_width,
+ pic_config->y_crop_height,
+ pic_config->cma_alloc_addr
+ );
+ }
+ return;
+}
+
+void av1_release_buf(AV1Decoder *pbi, RefCntBuffer *const buf)
+{
+
+#if 0
+ //def CHANGE_DONE
+ struct AV1HW_s *hw = (struct AV1HW_s *)(pbi->private_data);
+ if (!hw->mmu_enable)
+ return;
+ //release_buffer_4k(&av1_mmumgr_m, buf->buf.index);
+ decoder_mmu_box_free_idx(hw->mmu_box, buf->buf.index);
+#ifdef AOM_AV1_MMU_DW
+ //release_buffer_4k(&av1_mmumgr_dw, buf->buf.index);
+ decoder_mmu_box_free_idx(hw->mmu_box_dw, buf->buf.index);
+#endif
+
+#endif
+}
+
+void av1_release_bufs(struct AV1HW_s *hw) {
+ /*struct AV1HW_s *hw = (struct AV1HW_s *)(pbi->private_data);*/
+ AV1_COMMON *cm = &hw->pbi->common;
+ RefCntBuffer *const frame_bufs = cm->buffer_pool->frame_bufs;
+ int i;
+ if (!hw->mmu_enable)
+ return;
+
+ for (i = 0; i < FRAME_BUFFERS; ++i) {
+ if (frame_bufs[i].buf.vf_ref == 0 &&
+ frame_bufs[i].ref_count == 0 &&
+ frame_bufs[i].buf.index >= 0) {
+ //release_buffer_4k(&av1_mmumgr_m, i);
+ decoder_mmu_box_free_idx(hw->mmu_box, i);
+#ifdef AOM_AV1_MMU_DW
+ //release_buffer_4k(&av1_mmumgr_dw, i);
+ if (hw->dw_mmu_enable)
+ decoder_mmu_box_free_idx(hw->mmu_box_dw, i);
+#endif
+ }
+ }
+}
+
+static int config_pic_size(struct AV1HW_s *hw, unsigned short bit_depth)
+{
+ uint32_t data32;
+ struct AV1_Common_s *cm = &hw->pbi->common;
+ struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf;
+ int losless_comp_header_size, losless_comp_body_size;
+#ifdef AOM_AV1_MMU_DW
+ int losless_comp_header_size_dw, losless_comp_body_size_dw;
+#endif
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ " #### config_pic_size ####, bit_depth = %d\n", bit_depth);
+
+ frame_width = cur_pic_config->y_crop_width;
+ frame_height = cur_pic_config->y_crop_height;
+ cur_pic_config->bit_depth = bit_depth;
+ cur_pic_config->double_write_mode = get_double_write_mode(hw);
+
+ /* use fixed maximum size // 128x128/4/4*3-bits = 384 Bytes
+ seg_map_size =
+ ((frame_width + 127) >> 7) * ((frame_height + 127) >> 7) * 384 ;
+ */
+ WRITE_VREG(HEVC_PARSER_PICTURE_SIZE,
+ (frame_height << 16) | frame_width);
+#ifdef DUAL_DECODE
+#else
+ WRITE_VREG(HEVC_ASSIST_PIC_SIZE_FB_READ,
+ (frame_height << 16) | frame_width);
+#endif
+#ifdef AOM_AV1_MMU
+
+ //alloc_mmu(&av1_mmumgr_m, cm->cur_frame->buf.index, frame_width, frame_height, bit_depth);
+#endif
+#ifdef AOM_AV1_MMU_DW
+
+ //alloc_mmu(&av1_mmumgr_dw, cm->cur_frame->buf.index, frame_width, frame_height, bit_depth);
+ losless_comp_header_size_dw =
+ compute_losless_comp_header_size_dw(frame_width, frame_height);
+ losless_comp_body_size_dw =
+ compute_losless_comp_body_size_dw(frame_width, frame_height,
+ (bit_depth == AOM_BITS_10));
+#endif
+
+ losless_comp_header_size =
+ compute_losless_comp_header_size
+ (frame_width, frame_height);
+ losless_comp_body_size =
+ compute_losless_comp_body_size(frame_width,
+ frame_height, (bit_depth == AOM_BITS_10));
+
+ cur_pic_config->comp_body_size = losless_comp_body_size;
+
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "%s: width %d height %d depth %d head_size 0x%x body_size 0x%x\r\n",
+ __func__, frame_width, frame_height, bit_depth,
+ losless_comp_header_size, losless_comp_body_size);
+#ifdef LOSLESS_COMPRESS_MODE
+ data32 = READ_VREG(HEVC_SAO_CTRL5);
+ if (bit_depth == AOM_BITS_10)
+ data32 &= ~(1<<9);
+ else
+ data32 |= (1<<9);
+
+ WRITE_VREG(HEVC_SAO_CTRL5, data32);
+
+ if (hw->mmu_enable) {
+ WRITE_VREG(HEVCD_MPP_DECOMP_CTL1,(0x1<< 4)); // bit[4] : paged_mem_mode
+ } else {
+ if (bit_depth == AOM_BITS_10)
+ WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0<<3)); // bit[3] smem mdoe
+ else
+ WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (1<<3)); // bit[3] smem mdoe
+ }
+ WRITE_VREG(HEVCD_MPP_DECOMP_CTL2,
+ (losless_comp_body_size >> 5));
+ /*
+ WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,
+ (0xff<<20) | (0xff<<10) | 0xff); //8-bit mode
+ */
+ WRITE_VREG(HEVC_CM_BODY_LENGTH,
+ losless_comp_body_size);
+ WRITE_VREG(HEVC_CM_HEADER_OFFSET,
+ losless_comp_body_size);
+ WRITE_VREG(HEVC_CM_HEADER_LENGTH,
+ losless_comp_header_size);
+
+ if (get_double_write_mode(hw) & 0x10)
+ WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
+
+#else
+ WRITE_VREG(HEVCD_MPP_DECOMP_CTL1,0x1 << 31);
+#endif
+#ifdef AOM_AV1_MMU_DW
+ if (hw->dw_mmu_enable) {
+ WRITE_VREG(HEVC_CM_BODY_LENGTH2, losless_comp_body_size_dw);
+ WRITE_VREG(HEVC_CM_HEADER_OFFSET2, losless_comp_body_size_dw);
+ WRITE_VREG(HEVC_CM_HEADER_LENGTH2, losless_comp_header_size_dw);
+ }
+#endif
+ return 0;
+
+}
+
+static int config_mc_buffer(struct AV1HW_s *hw, unsigned short bit_depth, unsigned char inter_flag)
+{
+ int32_t i;
+ AV1_COMMON *cm = &hw->pbi->common;
+ PIC_BUFFER_CONFIG* cur_pic_config = &cm->cur_frame->buf;
+ uint8_t scale_enable = 0;
+
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ " #### config_mc_buffer %s ####\n",
+ inter_flag ? "inter" : "intra");
+
+#ifdef DEBUG_PRINT
+ if (debug&AOM_AV1_DEBUG_BUFMGR)
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "config_mc_buffer entered .....\n");
+#endif
+
+ WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
+ (0 << 8) | (0<<1) | 1);
+ WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
+ (cur_pic_config->order_hint<<24) |
+ (cur_pic_config->mc_canvas_u_v<<16) |
+ (cur_pic_config->mc_canvas_u_v<<8)|
+ cur_pic_config->mc_canvas_y);
+ for (i = LAST_FRAME; i <= ALTREF_FRAME; i++) {
+ PIC_BUFFER_CONFIG *pic_config; //cm->frame_refs[i].buf;
+ if (inter_flag)
+ pic_config = av1_get_ref_frame_spec_buf(cm, i);
+ else
+ pic_config = cur_pic_config;
+ if (pic_config) {
+ WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
+ (pic_config->order_hint<<24) |
+ (pic_config->mc_canvas_u_v<<16) |
+ (pic_config->mc_canvas_u_v<<8) |
+ pic_config->mc_canvas_y);
+ if (inter_flag)
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "refid 0x%x mc_canvas_u_v 0x%x mc_canvas_y 0x%x order_hint 0x%x\n",
+ i, pic_config->mc_canvas_u_v,
+ pic_config->mc_canvas_y, pic_config->order_hint);
+ } else {
+ WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
+ }
+ }
+
+ WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
+ (16 << 8) | (0 << 1) | 1);
+ WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
+ (cur_pic_config->order_hint << 24) |
+ (cur_pic_config->mc_canvas_u_v << 16) |
+ (cur_pic_config->mc_canvas_u_v << 8) |
+ cur_pic_config->mc_canvas_y);
+ for (i = LAST_FRAME; i <= ALTREF_FRAME; i++) {
+ PIC_BUFFER_CONFIG *pic_config;
+ if (inter_flag)
+ pic_config = av1_get_ref_frame_spec_buf(cm, i);
+ else
+ pic_config = cur_pic_config;
+
+ if (pic_config) {
+ WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
+ (pic_config->order_hint << 24)|
+ (pic_config->mc_canvas_u_v << 16) |
+ (pic_config->mc_canvas_u_v << 8) |
+ pic_config->mc_canvas_y);
+ } else {
+ WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
+ }
+ }
+
+ WRITE_VREG(VP9D_MPP_REFINFO_TBL_ACCCONFIG,
+ (0x1 << 2) | (0x0 <<3)); // auto_inc start index:0 field:0
+ for (i = 0; i <= ALTREF_FRAME; i++) {
+ int32_t ref_pic_body_size;
+ struct scale_factors * sf = NULL;
+ PIC_BUFFER_CONFIG *pic_config;
+
+ if (inter_flag && i >= LAST_FRAME)
+ pic_config = av1_get_ref_frame_spec_buf(cm, i);
+ else
+ pic_config = cur_pic_config;
+
+ if (pic_config) {
+ ref_pic_body_size =
+ compute_losless_comp_body_size(pic_config->y_crop_width,
+ pic_config->y_crop_height, (bit_depth == AOM_BITS_10));
+
+ WRITE_VREG(VP9D_MPP_REFINFO_DATA, pic_config->y_crop_width);
+ WRITE_VREG(VP9D_MPP_REFINFO_DATA, pic_config->y_crop_height);
+ if (inter_flag && i >= LAST_FRAME) {
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "refid %d: ref width/height(%d,%d), cur width/height(%d,%d) ref_pic_body_size 0x%x\n",
+ i, pic_config->y_crop_width, pic_config->y_crop_height,
+ cur_pic_config->y_crop_width, cur_pic_config->y_crop_height,
+ ref_pic_body_size);
+ }
+ } else {
+ ref_pic_body_size = 0;
+ WRITE_VREG(VP9D_MPP_REFINFO_DATA, 0);
+ WRITE_VREG(VP9D_MPP_REFINFO_DATA, 0);
+ }
+
+ if (inter_flag && i >= LAST_FRAME)
+ sf = av1_get_ref_scale_factors(cm, i);
+
+ if ((sf != NULL) && av1_is_scaled(sf)) {
+ scale_enable |= (1 << i);
+ }
+
+ if (sf) {
+ WRITE_VREG(VP9D_MPP_REFINFO_DATA, sf->x_scale_fp);
+ WRITE_VREG(VP9D_MPP_REFINFO_DATA, sf->y_scale_fp);
+
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "x_scale_fp %d, y_scale_fp %d\n",
+ sf->x_scale_fp, sf->y_scale_fp);
+ } else {
+ WRITE_VREG(VP9D_MPP_REFINFO_DATA, REF_NO_SCALE); //1<<14
+ WRITE_VREG(VP9D_MPP_REFINFO_DATA, REF_NO_SCALE);
+ }
+ if (hw->mmu_enable)
+ WRITE_VREG(VP9D_MPP_REFINFO_DATA, 0);
+ else
+ WRITE_VREG(VP9D_MPP_REFINFO_DATA,
+ ref_pic_body_size >> 5);
+ }
+ WRITE_VREG(VP9D_MPP_REF_SCALE_ENBL, scale_enable);
+ WRITE_VREG(PARSER_REF_SCALE_ENBL, scale_enable);
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "WRITE_VREG(PARSER_REF_SCALE_ENBL, 0x%x)\n",
+ scale_enable);
+ return 0;
+}
+
+static void clear_mpred_hw(struct AV1HW_s *hw)
+{
+ unsigned int data32;
+
+ data32 = READ_VREG(HEVC_MPRED_CTRL4);
+ data32 &= (~(1 << 6));
+ WRITE_VREG(HEVC_MPRED_CTRL4, data32);
+}
+
+static void config_mpred_hw(struct AV1HW_s *hw, unsigned char inter_flag)
+{
+ AV1_COMMON *cm = &hw->pbi->common;
+ PIC_BUFFER_CONFIG *cur_pic_config = &cm->cur_frame->buf;
+ //PIC_BUFFER_CONFIG *last_frame_pic_config = NULL;
+ int i, j, pos, reg_i;
+ int mv_cal_tpl_count = 0;
+ unsigned int mv_ref_id[MFMV_STACK_SIZE] = {0, 0, 0};
+ unsigned ref_offset_reg[] = {
+ HEVC_MPRED_L0_REF06_POC,
+ HEVC_MPRED_L0_REF07_POC,
+ HEVC_MPRED_L0_REF08_POC,
+ HEVC_MPRED_L0_REF09_POC,
+ HEVC_MPRED_L0_REF10_POC,
+ HEVC_MPRED_L0_REF11_POC,
+ };
+ unsigned ref_buf_reg[] = {
+ HEVC_MPRED_L0_REF03_POC,
+ HEVC_MPRED_L0_REF04_POC,
+ HEVC_MPRED_L0_REF05_POC
+ };
+ unsigned ref_offset_val[6] =
+ {0, 0, 0, 0, 0, 0};
+ unsigned ref_buf_val[3] = {0, 0, 0};
+
+ uint32_t data32;
+ int32_t mpred_curr_lcu_x;
+ int32_t mpred_curr_lcu_y;
+ //int32_t mpred_mv_rd_end_addr;
+
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ " #### config_mpred_hw ####\n");
+
+ /*if (cm->prev_frame)
+ last_frame_pic_config = &cm->prev_frame->buf;
+ mpred_mv_rd_end_addr = last_frame_pic_config->mpred_mv_wr_start_addr
+ + (last_frame_pic_config->lcu_total * MV_MEM_UNIT);
+ */
+
+ data32 = READ_VREG(HEVC_MPRED_CURR_LCU);
+ mpred_curr_lcu_x =data32 & 0xffff;
+ mpred_curr_lcu_y =(data32>>16) & 0xffff;
+
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "cur pic index %d\n", cur_pic_config->index);
+ /*printk("cur pic index %d col pic index %d\n",
+ cur_pic_config->index, last_frame_pic_config->index);*/
+
+ //WRITE_VREG(HEVC_MPRED_CTRL3,0x24122412);
+ WRITE_VREG(HEVC_MPRED_CTRL3, 0x13151315); // 'd19, 'd21 for AV1
+ WRITE_VREG(HEVC_MPRED_ABV_START_ADDR,
+ hw->pbi->work_space_buf->mpred_above.buf_start);
+
+#if 0
+ data32 = READ_VREG(HEVC_MPRED_CTRL4);
+ data32 &= (~(1<<6));
+ data32 |= (cm->use_prev_frame_mvs << 6);
+ WRITE_VREG(HEVC_MPRED_CTRL4, data32);
+#endif
+ if (inter_flag) {
+ /* config sign_bias */
+ //data32 = (cm->cur_frame_force_integer_mv & 0x1) << 9;
+ data32 = READ_VREG(HEVC_MPRED_CTRL4);
+ data32 &= (~(0xff << 12));
+ //for (i = LAST_FRAME; i <= ALTREF_FRAME; i++) {
+ /* HEVC_MPRED_CTRL4[bit 12] is for cm->ref_frame_sign_bias[0]
+ instead of cm->ref_frame_sign_bias[LAST_FRAME] */
+ for (i = 0; i <= ALTREF_FRAME; i++) {
+ data32 |= ((cm->ref_frame_sign_bias[i] & 0x1) << (12 + i));
+ }
+ WRITE_VREG(HEVC_MPRED_CTRL4, data32);
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "WRITE_VREG(HEVC_MPRED_CTRL4, 0x%x)\n", data32);
+ }
+#if 1
+ data32 = (
+ (cm->seq_params.order_hint_info.enable_order_hint << 27) |
+ (cm->seq_params.order_hint_info.order_hint_bits_minus_1 << 24) |
+ (cm->cur_frame->order_hint <<16 ) |
+ (0x13 << 8) | (0x13 << 0));
+#else
+ data32 = READ_VREG(HEVC_MPRED_L0_REF00_POC);
+ data32 &= (~(0xff << 16));
+ data32 |= (cm->cur_frame->order_hint & 0xff);
+ data32 &= (~(1 << 27));
+ data32 |= (cm->seq_params.order_hint_info.enable_order_hint << 27);
+#endif
+ WRITE_VREG(HEVC_MPRED_L0_REF00_POC, data32);
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "WRITE_VREG(HEVC_MPRED_L0_REF00_POC, 0x%x)\n", data32);
+
+ if (inter_flag) {
+ /* config ref_buf id and order hint */
+ data32 = 0;
+ pos = 25;
+ reg_i = 0;
+ for (i = ALTREF_FRAME; i >= LAST_FRAME; i--) {
+ PIC_BUFFER_CONFIG *pic_config =
+ av1_get_ref_frame_spec_buf(cm, i);
+ if (pic_config) {
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "pic_config for %d th ref: index %d, reg[%d] pos %d\n",
+ i, pic_config->index, reg_i, pos);
+ data32 |= ((pic_config->index < 0)? 0 : pic_config->index) << pos;
+ } else
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "pic_config is null for %d th ref\n", i);
+ if (pos == 0) {
+ //WRITE_VREG(ref_buf_reg[reg_i], data32);
+ ref_buf_val[reg_i] = data32;
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "ref_buf_reg[%d], WRITE_VREG(0x%x, 0x%x)\n",
+ reg_i, ref_buf_reg[reg_i], data32);
+ reg_i++;
+ data32 = 0;
+ pos = 24; //for P_HEVC_MPRED_L0_REF04_POC
+ } else {
+ if (pos == 24)
+ pos -= 8; //for P_HEVC_MPRED_L0_REF04_POC
+ else
+ pos -= 5; //for P_HEVC_MPRED_L0_REF03_POC
+ }
+ }
+ for (i = ALTREF_FRAME; i >= LAST_FRAME; i--) {
+ PIC_BUFFER_CONFIG *pic_config =
+ av1_get_ref_frame_spec_buf(cm, i);
+ if (pic_config) {
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "pic_config for %d th ref: order_hint %d, reg[%d] pos %d\n",
+ i, pic_config->order_hint, reg_i, pos);
+ data32 |= ((pic_config->index < 0)? 0 : pic_config->order_hint) << pos;
+ } else
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "pic_config is null for %d th ref\n", i);
+ if (pos == 0) {
+ //WRITE_VREG(ref_buf_reg[reg_i], data32);
+ ref_buf_val[reg_i] = data32;
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "ref_buf_reg[%d], WRITE_VREG(0x%x, 0x%x)\n",
+ reg_i, ref_buf_reg[reg_i], data32);
+ reg_i++;
+ data32 = 0;
+ pos = 24;
+ } else
+ pos -= 8;
+ }
+ if (pos != 24) {
+ //WRITE_VREG(ref_buf_reg[reg_i], data32);
+ ref_buf_val[reg_i] = data32;
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "ref_buf_reg[%d], WRITE_VREG(0x%x, 0x%x)\n",
+ reg_i, ref_buf_reg[reg_i], data32);
+ }
+ /* config ref_offset */
+ data32 = 0;
+ pos = 24;
+ mv_cal_tpl_count = 0;
+ reg_i = 0;
+ for (i = 0; i < cm->mv_ref_id_index; i++) {
+ if (cm->mv_cal_tpl_mvs[i]) {
+ mv_ref_id[mv_cal_tpl_count] = cm->mv_ref_id[i];
+ mv_cal_tpl_count++;
+ for (j = LAST_FRAME; j <= ALTREF_FRAME; j++) {
+ /*offset can be negative*/
+ unsigned char offval =
+ cm->mv_ref_offset[i][j] & 0xff;
+ data32 |= (offval << pos);
+ if (pos == 0) {
+ //WRITE_VREG(ref_offset_reg[reg_i], data32);
+ ref_offset_val[reg_i] = data32;
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "ref_offset_reg[%d], WRITE_VREG(0x%x, 0x%x)\n",
+ reg_i, ref_offset_reg[reg_i], data32);
+ reg_i++;
+ data32 = 0;
+ pos = 24;
+ } else
+ pos -= 8;
+ }
+ }
+ }
+ if (pos != 24) {
+ //WRITE_VREG(ref_offset_reg[reg_i], data32);
+ ref_offset_val[reg_i] = data32;
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "ref_offset_reg[%d], WRITE_VREG(0x%x, 0x%x)\n",
+ reg_i, ref_offset_reg[reg_i], data32);
+ }
+
+ data32 = ref_offset_val[5] | //READ_VREG(HEVC_MPRED_L0_REF11_POC) |
+ mv_cal_tpl_count | (mv_ref_id[0] << 2) |
+ (mv_ref_id[1] << 5) | (mv_ref_id[2] << 8);
+ ref_offset_val[5] = data32;
+ //WRITE_VREG(HEVC_MPRED_L0_REF11_POC, data32);
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "WRITE_VREG(HEVC_MPRED_L0_REF11_POC 0x%x, 0x%x)\n",
+ HEVC_MPRED_L0_REF11_POC, data32);
+ }
+ for (i = 0; i < 3; i++)
+ WRITE_VREG(ref_buf_reg[i], ref_buf_val[i]);
+ for (i = 0; i < 6; i++)
+ WRITE_VREG(ref_offset_reg[i], ref_offset_val[i]);
+
+ WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR,
+ cur_pic_config->mpred_mv_wr_start_addr);
+ WRITE_VREG(HEVC_MPRED_MV_WPTR,
+ cur_pic_config->mpred_mv_wr_start_addr);
+
+ if (inter_flag) {
+ for (i = 0; i < mv_cal_tpl_count; i++) {
+ PIC_BUFFER_CONFIG *pic_config =
+ av1_get_ref_frame_spec_buf(cm, mv_ref_id[i]);
+ if (pic_config == NULL)
+ continue;
+ if (i == 0) {
+ WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR,
+ pic_config->mpred_mv_wr_start_addr);
+ WRITE_VREG(HEVC_MPRED_MV_RPTR,
+ pic_config->mpred_mv_wr_start_addr);
+ } else if (i == 1) {
+ WRITE_VREG(HEVC_MPRED_L0_REF01_POC,
+ pic_config->mpred_mv_wr_start_addr);
+ WRITE_VREG(HEVC_MPRED_MV_RPTR_1,
+ pic_config->mpred_mv_wr_start_addr);
+ } else if (i == 2) {
+ WRITE_VREG(HEVC_MPRED_L0_REF02_POC,
+ pic_config->mpred_mv_wr_start_addr);
+ WRITE_VREG(HEVC_MPRED_MV_RPTR_2,
+ pic_config->mpred_mv_wr_start_addr);
+ } else {
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "%s: mv_ref_id error\n", __func__);
+ }
+ }
+ }
+ data32 = READ_VREG(HEVC_MPRED_CTRL0);
+ data32 &= ~((1 << 10) | (1 << 11));
+ data32 |= (1 << 10); /*write enable*/
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "current_frame.frame_type=%d, cur_frame->frame_type=%d, allow_ref_frame_mvs=%d\n",
+ cm->current_frame.frame_type, cm->cur_frame->frame_type,
+ cm->allow_ref_frame_mvs);
+
+ if (av1_frame_is_inter(&hw->pbi->common)) {
+ if (cm->allow_ref_frame_mvs) {
+ data32 |= (1 << 11); /*read enable*/
+ }
+ }
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "WRITE_VREG(HEVC_MPRED_CTRL0 0x%x, 0x%x)\n",
+ HEVC_MPRED_CTRL0, data32);
+ WRITE_VREG(HEVC_MPRED_CTRL0, data32);
+ /*
+ printk("config_mpred: (%x) wr_start_addr %x from indx %d;
+ (%x) rd_start_addr %x from index %d\n",
+ cur_pic_config, cur_pic_config->mpred_mv_wr_start_addr, cur_pic_config->index,
+ last_frame_pic_config, last_frame_pic_config->mpred_mv_wr_start_addr, last_frame_pic_config->index);
+ data32 = ((pbi->lcu_x_num - pbi->tile_width_lcu)*MV_MEM_UNIT);
+ WRITE_VREG(HEVC_MPRED_MV_WR_ROW_JUMP,data32);
+ WRITE_VREG(HEVC_MPRED_MV_RD_ROW_JUMP,data32);
+
+ WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR, mpred_mv_rd_end_addr);
+ */
+}
+
+static void config_sao_hw(struct AV1HW_s *hw, union param_u *params)
+{
+ /*
+ !!!!!!!!!!!!!!!!!!!!!!!!!TODO .... !!!!!!!!!!!
+ mem_map_mode, endian, get_double_write_mode
+ */
+ AV1_COMMON *cm = &hw->pbi->common;
+ PIC_BUFFER_CONFIG* pic_config = &cm->cur_frame->buf;
+ uint32_t data32;
+ int32_t lcu_size =
+ ((params->p.seq_flags >> 6) & 0x1) ? 128 : 64;
+ int32_t mc_buffer_size_u_v =
+ pic_config->lcu_total*lcu_size*lcu_size/2;
+ int32_t mc_buffer_size_u_v_h =
+ (mc_buffer_size_u_v + 0xffff)>>16; //64k alignment
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "[test.c] #### config_sao_hw ####, lcu_size %d\n", lcu_size);
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "[config_sao_hw] lcu_total : %d\n", pic_config->lcu_total);
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "[config_sao_hw] mc_y_adr : 0x%x\n", pic_config->mc_y_adr);
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "[config_sao_hw] mc_u_v_adr : 0x%x\n", pic_config->mc_u_v_adr);
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "[config_sao_hw] header_adr : 0x%x\n", pic_config->header_adr);
+#ifdef AOM_AV1_MMU_DW
+ if (hw->dw_mmu_enable)
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "[config_sao_hw] header_dw_adr : 0x%x\n", pic_config->header_dw_adr);
+#endif
+ data32 = READ_VREG(HEVC_SAO_CTRL9) | (1 << 1);
+ WRITE_VREG(HEVC_SAO_CTRL9, data32);
+
+ data32 = READ_VREG(HEVC_SAO_CTRL5);
+ data32 |= (0x1 << 14); /* av1 mode */
+ data32 |= (0xff << 16); /* dw {v1,v0,h1,h0} ctrl_y_cbus */
+ WRITE_VREG(HEVC_SAO_CTRL5, data32);
+
+ WRITE_VREG(HEVC_SAO_CTRL0,
+ lcu_size == 128 ? 0x7 : 0x6); /*lcu_size_log2*/
+#ifdef LOSLESS_COMPRESS_MODE
+ WRITE_VREG(HEVC_CM_BODY_START_ADDR, pic_config->mc_y_adr);
+#ifdef AOM_AV1_MMU
+ WRITE_VREG(HEVC_CM_HEADER_START_ADDR, pic_config->header_adr);
+#endif
+#ifdef AOM_AV1_MMU_DW
+ if (hw->dw_mmu_enable)
+ WRITE_VREG(HEVC_CM_HEADER_START_ADDR2, pic_config->header_dw_adr);
+#endif
+#else
+/*!LOSLESS_COMPRESS_MODE*/
+ WRITE_VREG(HEVC_SAO_Y_START_ADDR, pic_config->mc_y_adr);
+#endif
+
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "[config_sao_hw] sao_body_addr:%x\n", pic_config->mc_y_adr);
+ //printk("[config_sao_hw] sao_header_addr:%x\n", pic_config->mc_y_adr + losless_comp_body_size );
+
+#ifdef VPU_FILMGRAIN_DUMP
+ // Let Microcode to increase
+ // WRITE_VREG(HEVC_FGS_TABLE_START, pic_config->fgs_table_adr);
+#else
+ WRITE_VREG(HEVC_FGS_TABLE_START, pic_config->fgs_table_adr);
+#endif
+ WRITE_VREG(HEVC_FGS_TABLE_LENGTH, FGS_TABLE_SIZE * 8);
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "[config_sao_hw] fgs_table adr:0x%x , length 0x%x bits\n",
+ pic_config->fgs_table_adr, FGS_TABLE_SIZE * 8);
+
+ data32 = (mc_buffer_size_u_v_h<<16)<<1;
+ //printk("data32 = %x, mc_buffer_size_u_v_h = %x, lcu_total = %x\n", data32, mc_buffer_size_u_v_h, pic_config->lcu_total);
+ WRITE_VREG(HEVC_SAO_Y_LENGTH ,data32);
+
+#ifndef LOSLESS_COMPRESS_MODE
+ WRITE_VREG(HEVC_SAO_C_START_ADDR, pic_config->mc_u_v_adr);
+#else
+#endif
+
+ data32 = (mc_buffer_size_u_v_h<<16);
+ WRITE_VREG(HEVC_SAO_C_LENGTH ,data32);
+
+#ifndef LOSLESS_COMPRESS_MODE
+ /* multi tile to do... */
+ WRITE_VREG(HEVC_SAO_Y_WPTR, pic_config->mc_y_adr);
+
+ WRITE_VREG(HEVC_SAO_C_WPTR, pic_config->mc_u_v_adr);
+#else
+ if (get_double_write_mode(hw) &&
+ (get_double_write_mode(hw) & 0x20) == 0) {
+ WRITE_VREG(HEVC_SAO_Y_START_ADDR, pic_config->dw_y_adr);
+ WRITE_VREG(HEVC_SAO_C_START_ADDR, pic_config->dw_u_v_adr);
+ WRITE_VREG(HEVC_SAO_Y_WPTR, pic_config->dw_y_adr);
+ WRITE_VREG(HEVC_SAO_C_WPTR, pic_config->dw_u_v_adr);
+ } else {
+ //WRITE_VREG(HEVC_SAO_Y_START_ADDR, 0xffffffff);
+ //WRITE_VREG(HEVC_SAO_C_START_ADDR, 0xffffffff);
+ }
+#endif
+
+
+#ifndef AOM_AV1_NV21
+#ifdef AOM_AV1_MMU_DW
+ if (hw->dw_mmu_enable) {
+ }
+#endif
+#endif
+
+#ifdef AOM_AV1_NV21
+#ifdef DOS_PROJECT
+ data32 = READ_VREG(HEVC_SAO_CTRL1);
+ data32 &= (~0x3000);
+ data32 |= (MEM_MAP_MODE << 12); // [13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32
+ data32 &= (~0x3);
+ data32 |= 0x1; // [1]:dw_disable [0]:cm_disable
+ WRITE_VREG(HEVC_SAO_CTRL1, data32);
+
+ data32 = READ_VREG(HEVC_SAO_CTRL5); // [23:22] dw_v1_ctrl [21:20] dw_v0_ctrl [19:18] dw_h1_ctrl [17:16] dw_h0_ctrl
+ data32 &= ~(0xff << 16); // set them all 0 for AOM_AV1_NV21 (no down-scale)
+ WRITE_VREG(HEVC_SAO_CTRL5, data32);
+
+ data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
+ data32 &= (~0x30);
+ data32 |= (MEM_MAP_MODE << 4); // [5:4] -- address_format 00:linear 01:32x32 10:64x32
+ WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
+#else
+// m8baby test1902
+ data32 = READ_VREG(HEVC_SAO_CTRL1);
+ data32 &= (~0x3000);
+ data32 |= (MEM_MAP_MODE << 12); // [13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32
+ data32 &= (~0xff0);
+ //data32 |= 0x670; // Big-Endian per 64-bit
+ data32 |= 0x880; // Big-Endian per 64-bit
+ data32 &= (~0x3);
+ data32 |= 0x1; // [1]:dw_disable [0]:cm_disable
+ WRITE_VREG(HEVC_SAO_CTRL1, data32);
+
+ data32 = READ_VREG(HEVC_SAO_CTRL5); // [23:22] dw_v1_ctrl [21:20] dw_v0_ctrl [19:18] dw_h1_ctrl [17:16] dw_h0_ctrl
+ data32 &= ~(0xff << 16); // set them all 0 for AOM_AV1_NV21 (no down-scale)
+ WRITE_VREG(HEVC_SAO_CTRL5, data32);
+
+ data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
+ data32 &= (~0x30);
+ data32 |= (MEM_MAP_MODE << 4); // [5:4] -- address_format 00:linear 01:32x32 10:64x32
+ data32 &= (~0xF);
+ data32 |= 0x8; // Big-Endian per 64-bit
+ WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
+#endif
+#else
+/*CHANGE_DONE nnn*/
+ data32 = READ_VREG(HEVC_SAO_CTRL1);
+ data32 &= (~0x3000);
+ data32 |= (mem_map_mode <<
+ 12);
+
+/* [13:12] axi_aformat, 0-Linear,
+ * 1-32x32, 2-64x32
+ */
+ data32 &= (~0xff0);
+ /* data32 |= 0x670; // Big-Endian per 64-bit */
+#ifdef AOM_AV1_MMU_DW
+ if (hw->dw_mmu_enable == 0)
+ data32 |= endian; /* Big-Endian per 64-bit */
+#else
+ data32 |= endian; /* Big-Endian per 64-bit */
+#endif
+ if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
+ data32 &= (~0x3); /*[1]:dw_disable [0]:cm_disable*/
+ if (get_double_write_mode(hw) == 0)
+ data32 |= 0x2; /*disable double write*/
+ else if (get_double_write_mode(hw) & 0x10)
+ data32 |= 0x1; /*disable cm*/
+ } else { /* >= G12A dw write control */
+ unsigned int data;
+ data = READ_VREG(HEVC_DBLK_CFGB);
+ data &= (~0x300); /*[8]:first write enable (compress) [9]:double write enable (uncompress)*/
+ if (get_double_write_mode(hw) == 0)
+ data |= (0x1 << 8); /*enable first write*/
+ else if (get_double_write_mode(hw) & 0x10)
+ data |= (0x1 << 9); /*double write only*/
+ else
+ data |= ((0x1 << 8) |(0x1 << 9));
+ WRITE_VREG(HEVC_DBLK_CFGB, data);
+ }
+ WRITE_VREG(HEVC_SAO_CTRL1, data32);
+
+ if (get_double_write_mode(hw) & 0x10) {
+ /* [23:22] dw_v1_ctrl
+ *[21:20] dw_v0_ctrl
+ *[19:18] dw_h1_ctrl
+ *[17:16] dw_h0_ctrl
+ */
+ data32 = READ_VREG(HEVC_SAO_CTRL5);
+ /*set them all 0 for H265_NV21 (no down-scale)*/
+ data32 &= ~(0xff << 16);
+ WRITE_VREG(HEVC_SAO_CTRL5, data32);
+ } else {
+ data32 = READ_VREG(HEVC_SAO_CTRL5);
+ data32 &= (~(0xff << 16));
+ if ((get_double_write_mode(hw) & 0xf) == 2 ||
+ (get_double_write_mode(hw) & 0xf) == 3)
+ data32 |= (0xff<<16);
+ else if ((get_double_write_mode(hw) & 0xf) == 4 ||
+ (get_double_write_mode(hw) & 0xf) == 5)
+ data32 |= (0x33<<16);
+ WRITE_VREG(HEVC_SAO_CTRL5, data32);
+ }
+
+ data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
+ data32 &= (~0x30);
+ /* [5:4] -- address_format 00:linear 01:32x32 10:64x32 */
+ data32 |= (mem_map_mode <<
+ 4);
+ data32 &= (~0xF);
+ data32 |= 0xf; /* valid only when double write only */
+ /*data32 |= 0x8;*/ /* Big-Endian per 64-bit */
+ WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
+
+#endif
+
+}
+
+
+#ifdef AOM_AV1_DBLK_INIT
+/*
+ * Defines, declarations, sub-functions for av1 de-block loop filter Thr/Lvl table update
+ * - struct segmentation_lf is for loop filter only (removed something)
+ * - function "av1_loop_filter_init" and "av1_loop_filter_frame_init" will be instantiated in C_Entry
+ * - av1_loop_filter_init run once before decoding start
+ * - av1_loop_filter_frame_init run before every frame decoding start
+ * - set video format to AOM_AV1 is in av1_loop_filter_init
+ */
+#define MAX_LOOP_FILTER 63
+#define MAX_MODE_LF_DELTAS 2
+#define MAX_SEGMENTS 8
+#define MAX_MB_PLANE 3
+
+typedef enum {
+ SEG_LVL_ALT_Q, // Use alternate Quantizer ....
+ SEG_LVL_ALT_LF_Y_V, // Use alternate loop filter value on y plane vertical
+ SEG_LVL_ALT_LF_Y_H, // Use alternate loop filter value on y plane horizontal
+ SEG_LVL_ALT_LF_U, // Use alternate loop filter value on u plane
+ SEG_LVL_ALT_LF_V, // Use alternate loop filter value on v plane
+ SEG_LVL_REF_FRAME, // Optional Segment reference frame
+ SEG_LVL_SKIP, // Optional Segment (0,0) + skip mode
+ SEG_LVL_GLOBALMV,
+ SEG_LVL_MAX
+} SEG_LVL_FEATURES;
+
+static const SEG_LVL_FEATURES seg_lvl_lf_lut[MAX_MB_PLANE][2] = {
+ { SEG_LVL_ALT_LF_Y_V, SEG_LVL_ALT_LF_Y_H },
+ { SEG_LVL_ALT_LF_U, SEG_LVL_ALT_LF_U },
+ { SEG_LVL_ALT_LF_V, SEG_LVL_ALT_LF_V }
+};
+
+struct segmentation_lf { // for loopfilter only
+ uint8_t enabled;
+ /*
+ SEG_LVL_ALT_LF_Y_V feature_enable: seg_lf_info_y[bit7]
+ SEG_LVL_ALT_LF_Y_V data: seg_lf_info_y[bit0~6]
+ SEG_LVL_ALT_LF_Y_H feature enable: seg_lf_info_y[bit15]
+ SEG_LVL_ALT_LF_Y_H data: seg_lf_info_y[bit8~14]
+ */
+ uint16_t seg_lf_info_y[8];
+ /*
+ SEG_LVL_ALT_LF_U feature_enable: seg_lf_info_c[bit7]
+ SEG_LVL_ALT_LF_U data: seg_lf_info_c[bit0~6]
+ SEG_LVL_ALT_LF_V feature enable: seg_lf_info_c[bit15]
+ SEG_LVL_ALT_LF_V data: seg_lf_info_c[bit8~14]
+ */
+ uint16_t seg_lf_info_c[8];
+};
+
+typedef struct {
+ uint8_t mblim;
+ uint8_t lim;
+ uint8_t hev_thr;
+} loop_filter_thresh;
+
+typedef struct loop_filter_info_n_s {
+ loop_filter_thresh lfthr[MAX_LOOP_FILTER + 1];
+ uint8_t lvl[MAX_MB_PLANE][MAX_SEGMENTS][2][REF_FRAMES][MAX_MODE_LF_DELTAS];
+} loop_filter_info_n;
+
+struct loopfilter {
+ int32_t filter_level[2];
+ int32_t filter_level_u;
+ int32_t filter_level_v;
+
+ int32_t sharpness_level;
+
+ uint8_t mode_ref_delta_enabled;
+ uint8_t mode_ref_delta_update;
+
+ // 0 = Intra, Last, Last2+Last3,
+ // GF, BRF, ARF2, ARF
+ int8_t ref_deltas[REF_FRAMES];
+
+ // 0 = ZERO_MV, MV
+ int8_t mode_deltas[MAX_MODE_LF_DELTAS];
+
+ int32_t combine_vert_horz_lf;
+
+ int32_t lf_pic_cnt;
+
+//#if LOOP_FILTER_BITMASK
+ //LoopFilterMask *lfm;
+ //size_t lfm_num;
+ //int lfm_stride;
+ //LpfSuperblockInfo neighbor_sb_lpf_info;
+//#endif // LOOP_FILTER_BITMASK
+};
+
+static int32_t myclamp(int32_t value, int32_t low, int32_t high) {
+ return value < low ? low : (value > high ? high : value);
+}
+
+/*static int8_t extend_sign_7bits(uint8_t value) {
+ return (((value>>6) & 0x1)<<7) | (value&0x7f);
+}*/
+
+// convert data to int8_t variable
+// value : signed data (with any bitwidth<8) which is assigned to uint8_t variable as an input
+// bw : bitwidth of signed data, (from 1 to 7)
+static int8_t conv2int8 (uint8_t value, uint8_t bw) {
+ if (bw<1 || bw>7) return (int8_t)value;
+ else {
+ const uint8_t data_bits = value & ((1<<bw)-1);
+ const uint8_t sign_bit = (value>>(bw-1)) & 0x1;
+ const uint8_t sign_bit_ext = sign_bit | sign_bit<<1 | sign_bit<<2 | sign_bit<<3 | sign_bit<<4 | sign_bit<<5 | sign_bit<<6 | sign_bit<<7;
+ return (int8_t)((sign_bit_ext<<bw) | data_bits);
+ }
+}
+
+static void av1_update_sharpness(loop_filter_info_n *lfi, int32_t sharpness_lvl) {
+ int32_t lvl;
+
+ // For each possible value for the loop filter fill out limits
+ for (lvl = 0; lvl <= MAX_LOOP_FILTER; lvl++) {
+ // Set loop filter parameters that control sharpness.
+ int32_t block_inside_limit =
+ lvl >> ((sharpness_lvl > 0) + (sharpness_lvl > 4));
+
+ if (sharpness_lvl > 0) {
+ if (block_inside_limit > (9 - sharpness_lvl))
+ block_inside_limit = (9 - sharpness_lvl);
+ }
+
+ if (block_inside_limit < 1)
+ block_inside_limit = 1;
+
+ lfi->lfthr[lvl].lim = (uint8_t)block_inside_limit;
+ lfi->lfthr[lvl].mblim = (uint8_t)(2 * (lvl + 2) + block_inside_limit);
+ }
+}
+
+// instantiate this function once when decode is started
+void av1_loop_filter_init(loop_filter_info_n *lfi, struct loopfilter *lf) {
+ int32_t i;
+ uint32_t data32;
+
+ // init limits for given sharpness
+ av1_update_sharpness(lfi, lf->sharpness_level);
+
+ // Write to register
+ for (i = 0; i < 32; i++) {
+ uint32_t thr;
+ thr = ((lfi->lfthr[i*2+1].lim & 0x3f)<<8) |
+ (lfi->lfthr[i*2+1].mblim & 0xff);
+ thr = (thr<<16) | ((lfi->lfthr[i*2].lim & 0x3f)<<8) |
+ (lfi->lfthr[i*2].mblim & 0xff);
+ WRITE_VREG(HEVC_DBLK_CFG9, thr);
+ }
+ // video format is AOM_AV1
+ data32 = (0x57 << 8) | // 1st/2nd write both enable
+ (0x4 << 0); // aom_av1 video format
+ WRITE_VREG(HEVC_DBLK_CFGB, data32);
+ av1_print2(AOM_DEBUG_HW_MORE,
+ "[DBLK DEBUG] CFGB : 0x%x\n", data32);
+}
+
+// perform this function per frame
+void av1_loop_filter_frame_init(AV1Decoder* pbi, struct segmentation_lf *seg,
+ loop_filter_info_n *lfi,
+ struct loopfilter *lf,
+ int32_t pic_width) {
+ BuffInfo_t* buf_spec = pbi->work_space_buf;
+ int32_t i,dir;
+ int32_t filt_lvl[MAX_MB_PLANE], filt_lvl_r[MAX_MB_PLANE];
+ int32_t plane;
+ int32_t seg_id;
+ // n_shift is the multiplier for lf_deltas
+ // the multiplier is 1 for when filter_lvl is between 0 and 31;
+ // 2 when filter_lvl is between 32 and 63
+
+ // update limits if sharpness has changed
+ av1_update_sharpness(lfi, lf->sharpness_level);
+
+ // Write to register
+ for (i = 0; i < 32; i++) {
+ uint32_t thr;
+ thr = ((lfi->lfthr[i*2+1].lim & 0x3f)<<8)
+ | (lfi->lfthr[i*2+1].mblim & 0xff);
+ thr = (thr<<16) | ((lfi->lfthr[i*2].lim & 0x3f)<<8)
+ | (lfi->lfthr[i*2].mblim & 0xff);
+ WRITE_VREG(HEVC_DBLK_CFG9, thr);
+ }
+
+ filt_lvl[0] = lf->filter_level[0];
+ filt_lvl[1] = lf->filter_level_u;
+ filt_lvl[2] = lf->filter_level_v;
+
+ filt_lvl_r[0] = lf->filter_level[1];
+ filt_lvl_r[1] = lf->filter_level_u;
+ filt_lvl_r[2] = lf->filter_level_v;
+
+#ifdef DBG_LPF_PRINT
+ printk("LF_PRINT: pic_cnt(%d) base_filter_level(%d,%d,%d,%d)\n",
+ lf->lf_pic_cnt, lf->filter_level[0],
+ lf->filter_level[1], lf->filter_level_u, lf->filter_level_v);
+#endif
+
+ for (plane = 0; plane < 3; plane++) {
+ if (plane == 0 && !filt_lvl[0] && !filt_lvl_r[0])
+ break;
+ else if (plane == 1 && !filt_lvl[1])
+ continue;
+ else if (plane == 2 && !filt_lvl[2])
+ continue;
+
+ for (seg_id = 0; seg_id < MAX_SEGMENTS; seg_id++) { // MAX_SEGMENTS==8
+ for (dir = 0; dir < 2; ++dir) {
+ int32_t lvl_seg = (dir == 0) ? filt_lvl[plane] : filt_lvl_r[plane];
+ //assert(plane >= 0 && plane <= 2);
+ const uint8_t seg_lf_info_y0 = seg->seg_lf_info_y[seg_id] & 0xff;
+ const uint8_t seg_lf_info_y1 = (seg->seg_lf_info_y[seg_id]>>8) & 0xff;
+ const uint8_t seg_lf_info_u = seg->seg_lf_info_c[seg_id] & 0xff;
+ const uint8_t seg_lf_info_v = (seg->seg_lf_info_c[seg_id]>>8) & 0xff;
+ const uint8_t seg_lf_info = (plane==2) ? seg_lf_info_v : (plane==1) ?
+ seg_lf_info_u : ((dir==0) ? seg_lf_info_y0 : seg_lf_info_y1);
+ const int8_t seg_lf_active = ((seg->enabled) && ((seg_lf_info>>7) & 0x1));
+ const int8_t seg_lf_data = conv2int8(seg_lf_info,7);
+#ifdef DBG_LPF_PRINT
+ const int8_t seg_lf_data_clip = (seg_lf_data>63) ? 63 :
+ (seg_lf_data<-63) ? -63 : seg_lf_data;
+#endif
+ if (seg_lf_active) {
+ lvl_seg = myclamp(lvl_seg + (int32_t)seg_lf_data, 0, MAX_LOOP_FILTER);
+ }
+
+#ifdef DBG_LPF_PRINT
+ printk("LF_PRINT:plane(%d) seg_id(%d) dir(%d) seg_lf_info(%d,0x%x),lvl_seg(0x%x)\n",
+ plane,seg_id,dir,seg_lf_active,seg_lf_data_clip,lvl_seg);
+#endif
+
+ if (!lf->mode_ref_delta_enabled) {
+ // we could get rid of this if we assume that deltas are set to
+ // zero when not in use; encoder always uses deltas
+ memset(lfi->lvl[plane][seg_id][dir], lvl_seg,
+ sizeof(lfi->lvl[plane][seg_id][dir]));
+ } else {
+ int32_t ref, mode;
+ const int32_t scale = 1 << (lvl_seg >> 5);
+ const int32_t intra_lvl = lvl_seg + lf->ref_deltas[INTRA_FRAME] * scale;
+ lfi->lvl[plane][seg_id][dir][INTRA_FRAME][0] =
+ myclamp(intra_lvl, 0, MAX_LOOP_FILTER);
+#ifdef DBG_LPF_PRINT
+ printk("LF_PRINT:ref_deltas[INTRA_FRAME](%d)\n",lf->ref_deltas[INTRA_FRAME]);
+#endif
+ for (ref = LAST_FRAME; ref < REF_FRAMES; ++ref) { // LAST_FRAME==1 REF_FRAMES==8
+ for (mode = 0; mode < MAX_MODE_LF_DELTAS; ++mode) { // MAX_MODE_LF_DELTAS==2
+ const int32_t inter_lvl =
+ lvl_seg + lf->ref_deltas[ref] * scale +
+ lf->mode_deltas[mode] * scale;
+ lfi->lvl[plane][seg_id][dir][ref][mode] =
+ myclamp(inter_lvl, 0, MAX_LOOP_FILTER);
+#ifdef DBG_LPF_PRINT
+ printk("LF_PRINT:ref_deltas(%d) mode_deltas(%d)\n",
+ lf->ref_deltas[ref], lf->mode_deltas[mode]);
+#endif
+ }
+ }
+ }
+ }
+ }
+ }
+
+#ifdef DBG_LPF_PRINT
+ for (i = 0; i <= MAX_LOOP_FILTER; i++) {
+ printk("LF_PRINT:(%2d) thr=%d,blim=%3d,lim=%2d\n",
+ i, lfi->lfthr[i].hev_thr,
+ lfi->lfthr[i].mblim, lfi->lfthr[i].lim);
+ }
+ for (plane = 0; plane < 3; plane++) {
+ for (seg_id = 0; seg_id < MAX_SEGMENTS; seg_id++) { // MAX_SEGMENTS==8
+ for (dir = 0; dir < 2; ++dir) {
+ int32_t mode;
+ for (mode = 0; mode < 2; ++mode) {
+ printk("assign {lvl[%d][%d][%d][0][%d],lvl[%d][%d][%d][1][%d],lvl[%d][%d][%d][2][%d],lvl[%d][%d][%d][3][%d],lvl[%d][%d][%d][4][%d],lvl[%d][%d][%d][5][%d],lvl[%d][%d][%d][6][%d],lvl[%d][%d][%d][7][%d]}={6'd%2d,6'd%2d,6'd%2d,6'd%2d,6'd%2d,6'd%2d,6'd%2d,6'd%2d};\n",
+ plane, seg_id, dir, mode,
+ plane, seg_id, dir, mode,
+ plane, seg_id, dir, mode,
+ plane, seg_id, dir, mode,
+ plane, seg_id, dir, mode,
+ plane, seg_id, dir, mode,
+ plane, seg_id, dir, mode,
+ plane, seg_id, dir, mode,
+ lfi->lvl[plane][seg_id][dir][0][mode],
+ lfi->lvl[plane][seg_id][dir][1][mode],
+ lfi->lvl[plane][seg_id][dir][2][mode],
+ lfi->lvl[plane][seg_id][dir][3][mode],
+ lfi->lvl[plane][seg_id][dir][4][mode],
+ lfi->lvl[plane][seg_id][dir][5][mode],
+ lfi->lvl[plane][seg_id][dir][6][mode],
+ lfi->lvl[plane][seg_id][dir][7][mode]);
+ }
+ }
+ }
+ }
+#endif
+ // Write to register
+ for (i = 0; i < 192; i++) {
+ uint32_t level;
+ level = ((lfi->lvl[i>>6&3][i>>3&7][1][i&7][1] & 0x3f)<<24) |
+ ((lfi->lvl[i>>6&3][i>>3&7][1][i&7][0] & 0x3f)<<16) |
+ ((lfi->lvl[i>>6&3][i>>3&7][0][i&7][1] & 0x3f)<<8) |
+ (lfi->lvl[i>>6&3][i>>3&7][0][i&7][0] & 0x3f);
+ if (!lf->filter_level[0] && !lf->filter_level[1])
+ level = 0;
+ WRITE_VREG(HEVC_DBLK_CFGA, level);
+ }
+#ifdef DBG_LPF_DBLK_FORCED_OFF
+ if (lf->lf_pic_cnt == 2) {
+ printk("LF_PRINT: pic_cnt(%d) dblk forced off !!!\n", lf->lf_pic_cnt);
+ WRITE_VREG(HEVC_DBLK_DBLK0, 0);
+ } else
+ WRITE_VREG(HEVC_DBLK_DBLK0,
+ lf->filter_level[0] | lf->filter_level[1] << 6 |
+ lf->filter_level_u << 12 | lf->filter_level_v << 18);
+#else
+ WRITE_VREG(HEVC_DBLK_DBLK0,
+ lf->filter_level[0] | lf->filter_level[1]<<6 |
+ lf->filter_level_u<<12 | lf->filter_level_v<<18);
+#endif
+ for (i =0; i < 10; i++)
+ WRITE_VREG(HEVC_DBLK_DBLK1,
+ ((i<2) ? lf->mode_deltas[i&1] : lf->ref_deltas[(i-2)&7]));
+ for (i = 0; i < 8; i++)
+ WRITE_VREG(HEVC_DBLK_DBLK2,
+ (uint32_t)(seg->seg_lf_info_y[i]) | (uint32_t)(seg->seg_lf_info_c[i]<<16));
+
+ // Set P_HEVC_DBLK_CFGB again
+ {
+ uint32_t lpf_data32 = READ_VREG(HEVC_DBLK_CFGB);
+ if (lf->mode_ref_delta_enabled)
+ lpf_data32 |= (0x1<<28); // mode_ref_delta_enabled
+ else
+ lpf_data32 &= ~(0x1<<28);
+ if (seg->enabled)
+ lpf_data32 |= (0x1<<29); // seg enable
+ else
+ lpf_data32 &= ~(0x1<<29);
+ if (pic_width >= 1280)
+ lpf_data32 |= (0x1 << 4); // dblk pipeline mode=1 for performance
+ else
+ lpf_data32 &= ~(0x3 << 4);
+ WRITE_VREG(HEVC_DBLK_CFGB, lpf_data32);
+ }
+ // Set CDEF
+ WRITE_VREG(HEVC_DBLK_CDEF0, buf_spec->cdef_data.buf_start);
+ {
+ uint32_t cdef_data32 = (READ_VREG(HEVC_DBLK_CDEF1) & 0xffffff00);
+ cdef_data32 |= 17; // TODO ERROR :: cdef temp dma address left offset
+ WRITE_VREG(HEVC_DBLK_CDEF1, cdef_data32);
+ }
+ // Picture count
+ lf->lf_pic_cnt++;
+}
+#endif // #ifdef AOM_AV1_DBLK_INIT
+
+#ifdef AOM_AV1_UPSCALE_INIT
+/*
+ * these functions here for upscaling updated in every picture
+ */
+#define RS_SUBPEL_BITS 6
+#define RS_SUBPEL_MASK ((1 << RS_SUBPEL_BITS) - 1)
+#define RS_SCALE_SUBPEL_BITS 14
+#define RS_SCALE_SUBPEL_MASK ((1 << RS_SCALE_SUBPEL_BITS) - 1)
+#define RS_SCALE_EXTRA_BITS (RS_SCALE_SUBPEL_BITS - RS_SUBPEL_BITS)
+#define RS_SCALE_EXTRA_OFF (1 << (RS_SCALE_EXTRA_BITS - 1))
+
+static int32_t av1_get_upscale_convolve_step(int32_t in_length, int32_t out_length) {
+ return ((in_length << RS_SCALE_SUBPEL_BITS) + out_length / 2) / out_length;
+}
+
+static int32_t get_upscale_convolve_x0(int32_t in_length, int32_t out_length,
+ int32_t x_step_qn) {
+ const int32_t err = out_length * x_step_qn - (in_length << RS_SCALE_SUBPEL_BITS);
+ const int32_t x0 =
+ (-((out_length - in_length) << (RS_SCALE_SUBPEL_BITS - 1)) +
+ out_length / 2) /
+ out_length +
+ RS_SCALE_EXTRA_OFF - err / 2;
+ return (int32_t)((uint32_t)x0 & RS_SCALE_SUBPEL_MASK);
+}
+
+void av1_upscale_frame_init(AV1Decoder* pbi, AV1_COMMON *cm, param_t* params)
+{
+ BuffInfo_t* buf_spec = pbi->work_space_buf;
+ //uint32_t data32;
+ const int32_t width = cm->dec_width;
+ const int32_t superres_upscaled_width = cm->superres_upscaled_width;
+ const int32_t x_step_qn_luma = av1_get_upscale_convolve_step(width, superres_upscaled_width);
+ const int32_t x0_qn_luma = get_upscale_convolve_x0(width, superres_upscaled_width, x_step_qn_luma);
+ const int32_t x_step_qn_chroma = av1_get_upscale_convolve_step((width+1)>>1, (superres_upscaled_width+1)>>1);
+ const int32_t x0_qn_chroma = get_upscale_convolve_x0((width+1)>>1, (superres_upscaled_width+1)>>1, x_step_qn_chroma);
+ av1_print2(AOM_DEBUG_HW_MORE,
+ "UPS_PRINT: width(%d -> %d)\n",
+ width, superres_upscaled_width);
+ av1_print2(AOM_DEBUG_HW_MORE,
+ "UPS_PRINT: xstep(%d,%d)(0x%X, 0x%X) x0qn(%d,%d)(0x%X, 0x%X)\n",
+ x_step_qn_luma,x_step_qn_chroma,
+ x_step_qn_luma,x_step_qn_chroma,
+ x0_qn_luma,x0_qn_chroma,
+ x0_qn_luma,x0_qn_chroma);
+ WRITE_VREG(HEVC_DBLK_UPS1, buf_spec->ups_data.buf_start);
+ WRITE_VREG(HEVC_DBLK_UPS2, x0_qn_luma); // x0_qn y
+ WRITE_VREG(HEVC_DBLK_UPS3, x0_qn_chroma); // x0_qn c
+ WRITE_VREG(HEVC_DBLK_UPS4, x_step_qn_luma); // x_step y
+ WRITE_VREG(HEVC_DBLK_UPS5, x_step_qn_chroma); // x_step c
+ WRITE_VREG(AV1_UPSCALE_X0_QN, (x0_qn_chroma<<16)|x0_qn_luma);
+ WRITE_VREG(AV1_UPSCALE_STEP_QN, (x_step_qn_chroma<<16)|x_step_qn_luma);
+
+/*
+ * TileR calculation here if cm needs an exactly accurate value
+ */
+//#define AV1_UPSCALE_TILER_CALCULATION
+#ifdef AV1_UPSCALE_TILER_CALCULATION
+ uint32_t upscl_enabled = 1; // 1 just for example, actually this is use_superres flag
+ uint32_t tiler_x = 192; // 192 just for example, actually this is tile end
+ uint32_t ux;
+ uint32_t ux_tiler,ux_tiler_rnd32;
+ uint32_t xqn_y;
+ uint32_t xqn_c;
+ uint32_t tiler_x_y = tiler_x - 8 - 3; // dblk/cdef left-shift-8 plus upscaling extra-3
+ uint32_t tiler_x_c = (tiler_x/2) - 4 - 3; // dblk/cdef left-shift-4 plus upscaling extra-3
+
+ xqn_y = x0_qn_luma;
+ xqn_c = x0_qn_chroma;
+ ux_tiler = 0;
+ ux_tiler_rnd32 = 0;
+ for (ux=0; ux<16384; ux+=8) {
+ uint32_t x1qn_y = xqn_y + x_step_qn_luma *( 7+3); // extra-3 is for lrf
+ uint32_t x1qn_c = xqn_c + x_step_qn_chroma*( 3+3); // extra-3 is for lrf
+ uint32_t x1qn_y_nxt = xqn_y + x_step_qn_luma *(8+7+3); // extra-3 is for lrf
+ uint32_t x1qn_c_nxt = xqn_c + x_step_qn_chroma*(4+3+3); // extra-3 is for lrf
+
+ uint32_t x1_y = upscl_enabled ? (x1qn_y>>14) : ux +7+3;
+ uint32_t x1_c = upscl_enabled ? (x1qn_c>>14) : (ux/2)+3+3;
+ uint32_t x1_y_nxt = upscl_enabled ? (x1qn_y_nxt>>14) : ux +8+7+3;
+ uint32_t x1_c_nxt = upscl_enabled ? (x1qn_c_nxt>>14) : (ux/2)+4+3+3;
+
+ if ((x1_y<tiler_x_y && x1_c<tiler_x_c) &&
+ (x1_y_nxt>=tiler_x_y || x1_c_nxt>=tiler_x_c)) {
+ ux_tiler = ux;
+ ux_tiler_rnd32 = (ux_tiler/32 + (ux_tiler%32 ? 1 : 0)) * 32;
+ break;
+ }
+
+ xqn_y += x_step_qn_luma*8;
+ xqn_c += x_step_qn_chroma*4;
+ }
+
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "UPS_PRINT: xqn_y(0x%x), xqn_c(0x%x), x1qn_y(0x%x), x1qn_c(0x%x)\n",
+ xqn_y, xqn_c, x1qn_y, x1qn_c);
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "UPS_PRINT: ux_tiler(%d)(0x%x), ux_tiler_rnd32(%d)(0x%x)\n",
+ ux_tiler, ux_tiler, ux_tiler_rnd32, ux_tiler_rnd32);
+#endif
+
+ // TEMP write lrf register here
+ //WRITE_VREG(HEVC_DBLK_LRF0, 1<<0 | 1<<2); // LRF UNIT SIZE
+ //WRITE_VREG(HEVC_DBLK_LRF1, 3<<0 | 1<<8 | 1<<16 | 1<<24); // LRF UNIT NUMBER
+
+ // TEMP Global Enables write here
+ /*
+ const uint32_t dblk_enable = (!cm->allow_intrabc && !cm->single_tile_decoding && (cm->lf.filter_level[0] || cm->lf.filter_level[1]));
+ const uint32_t cdef_enable = (!cm->allow_intrabc && !cm->single_tile_decoding && !cm->skip_loop_filter && !cm->coded_lossless && (cm->cdef_bits || cm->cdef_strengths[0] || cm->cdef_uv_strengths[0]));
+ printk("LPF_ENABLES : dblk(%d) cdef(%d)\n", dblk_enable, cdef_enable);
+ data32 = READ_VREG(HEVC_DBLK_CFGB );
+ data32 &= ~(0xf<<20);
+ data32 |= (dblk_enable<<20);
+ data32 |= (cdef_enable<<23);
+ WRITE_VREG(HEVC_DBLK_CFGB, data32);
+ */
+}
+
+#endif // #ifdef AOM_AV1_UPSCALE_INIT
+
+static void release_dblk_struct(struct AV1HW_s *hw)
+{
+#ifdef AOM_AV1_DBLK_INIT
+ if (hw->lfi)
+ vfree(hw->lfi);
+ if (hw->lf)
+ vfree(hw->lf);
+ if (hw->seg_4lf)
+ vfree(hw->seg_4lf);
+ hw->lfi = NULL;
+ hw->lf = NULL;
+ hw->seg_4lf = NULL;
+#endif
+}
+
+static int init_dblk_struc(struct AV1HW_s *hw)
+{
+#ifdef AOM_AV1_DBLK_INIT
+ hw->lfi = vmalloc(sizeof(loop_filter_info_n));
+ hw->lf = vmalloc(sizeof(struct loopfilter));
+ hw->seg_4lf = vmalloc(sizeof(struct segmentation_lf));
+
+ if (hw->lfi == NULL || hw->lf == NULL || hw->seg_4lf == NULL) {
+ printk("[test.c] aom_loop_filter init malloc error!!!\n");
+ release_dblk_struct(hw);
+ return -1;
+ }
+
+ hw->lf->mode_ref_delta_enabled = 1; // set default here
+ hw->lf->mode_ref_delta_update = 1; // set default here
+ hw->lf->sharpness_level = 0; // init to 0
+ hw->lf->lf_pic_cnt = 0; // init to 0
+#endif
+ return 0;
+}
+
+static void config_dblk_hw(struct AV1HW_s *hw)
+{
+ AV1Decoder *pbi = hw->pbi;
+ AV1_COMMON *cm = &hw->pbi->common;
+ loop_filter_info_n *lfi = hw->lfi;
+ struct loopfilter *lf = hw->lf;
+ struct segmentation_lf *seg_4lf = hw->seg_4lf;
+ BuffInfo_t* buf_spec = pbi->work_space_buf;
+ PIC_BUFFER_CONFIG* cur_pic_config = &cm->cur_frame->buf;
+ PIC_BUFFER_CONFIG* prev_pic_config = &cm->prev_frame->buf;
+ int i;
+
+#ifdef AOM_AV1_DBLK_INIT
+#ifdef DUAL_DECODE
+#else
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "[test.c ref_delta] cur_frame : %p prev_frame : %p - %p \n",
+ cm->cur_frame, cm->prev_frame,
+ av1_get_primary_ref_frame_buf(cm));
+ // get lf parameters from parser
+ lf->mode_ref_delta_enabled =
+ (hw->aom_param.p.loop_filter_mode_ref_delta_enabled & 1);
+ lf->mode_ref_delta_update =
+ ((hw->aom_param.p.loop_filter_mode_ref_delta_enabled >> 1) & 1);
+ lf->sharpness_level =
+ hw->aom_param.p.loop_filter_sharpness_level;
+ if (((hw->aom_param.p.loop_filter_mode_ref_delta_enabled)&3) == 3) { // enabled but and update
+ if (cm->prev_frame <= 0) {
+ // already initialized in Microcode
+ lf->ref_deltas[0] = conv2int8((uint8_t)(hw->aom_param.p.loop_filter_ref_deltas_0),7);
+ lf->ref_deltas[1] = conv2int8((uint8_t)(hw->aom_param.p.loop_filter_ref_deltas_0>>8),7);
+ lf->ref_deltas[2] = conv2int8((uint8_t)(hw->aom_param.p.loop_filter_ref_deltas_1),7);
+ lf->ref_deltas[3] = conv2int8((uint8_t)(hw->aom_param.p.loop_filter_ref_deltas_1>>8),7);
+ lf->ref_deltas[4] = conv2int8((uint8_t)(hw->aom_param.p.loop_filter_ref_deltas_2),7);
+ lf->ref_deltas[5] = conv2int8((uint8_t)(hw->aom_param.p.loop_filter_ref_deltas_2>>8),7);
+ lf->ref_deltas[6] = conv2int8((uint8_t)(hw->aom_param.p.loop_filter_ref_deltas_3),7);
+ lf->ref_deltas[7] = conv2int8((uint8_t)(hw->aom_param.p.loop_filter_ref_deltas_3>>8),7);
+ lf->mode_deltas[0] = conv2int8((uint8_t)(hw->aom_param.p.loop_filter_mode_deltas_0),7);
+ lf->mode_deltas[1] = conv2int8((uint8_t)(hw->aom_param.p.loop_filter_mode_deltas_0>>8),7);
+ } else {
+ lf->ref_deltas[0] = (hw->aom_param.p.loop_filter_ref_deltas_0 & 0x80) ?
+ conv2int8((uint8_t)(hw->aom_param.p.loop_filter_ref_deltas_0),7) :
+ cm->prev_frame->ref_deltas[0];
+ lf->ref_deltas[1] = (hw->aom_param.p.loop_filter_ref_deltas_0 & 0x8000) ?
+ conv2int8((uint8_t)(hw->aom_param.p.loop_filter_ref_deltas_0>>8),7) :
+ cm->prev_frame->ref_deltas[1];
+ lf->ref_deltas[2] = (hw->aom_param.p.loop_filter_ref_deltas_1 & 0x80) ?
+ conv2int8((uint8_t)(hw->aom_param.p.loop_filter_ref_deltas_1),7) :
+ cm->prev_frame->ref_deltas[2];
+ lf->ref_deltas[3] = (hw->aom_param.p.loop_filter_ref_deltas_1 & 0x8000) ?
+ conv2int8((uint8_t)(hw->aom_param.p.loop_filter_ref_deltas_1>>8),7) :
+ cm->prev_frame->ref_deltas[3];
+ lf->ref_deltas[4] = (hw->aom_param.p.loop_filter_ref_deltas_2 & 0x80) ?
+ conv2int8((uint8_t)(hw->aom_param.p.loop_filter_ref_deltas_2),7) :
+ cm->prev_frame->ref_deltas[4];
+ lf->ref_deltas[5] = (hw->aom_param.p.loop_filter_ref_deltas_2 & 0x8000) ?
+ conv2int8((uint8_t)(hw->aom_param.p.loop_filter_ref_deltas_2>>8),7) :
+ cm->prev_frame->ref_deltas[5];
+ lf->ref_deltas[6] = (hw->aom_param.p.loop_filter_ref_deltas_3 & 0x80) ?
+ conv2int8((uint8_t)(hw->aom_param.p.loop_filter_ref_deltas_3),7) :
+ cm->prev_frame->ref_deltas[6];
+ lf->ref_deltas[7] = (hw->aom_param.p.loop_filter_ref_deltas_3 & 0x8000) ?
+ conv2int8((uint8_t)(hw->aom_param.p.loop_filter_ref_deltas_3>>8),7) :
+ cm->prev_frame->ref_deltas[7];
+ lf->mode_deltas[0] = (hw->aom_param.p.loop_filter_mode_deltas_0 & 0x80) ?
+ conv2int8((uint8_t)(hw->aom_param.p.loop_filter_mode_deltas_0),7) :
+ cm->prev_frame->mode_deltas[0];
+ lf->mode_deltas[1] = (hw->aom_param.p.loop_filter_mode_deltas_0 & 0x8000) ?
+ conv2int8((uint8_t)(hw->aom_param.p.loop_filter_mode_deltas_0>>8),7) :
+ cm->prev_frame->mode_deltas[1];
+ }
+ } //else if (hw->aom_param.p.loop_filter_mode_ref_delta_enabled == 1) { // enabled but no update
+ else { // match c code -- not enabled, still need to copy prev to used for next
+ if ((cm->prev_frame <= 0) | (hw->aom_param.p.loop_filter_mode_ref_delta_enabled & 4)) {
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "[test.c] mode_ref_delta set to default\n");
+ lf->ref_deltas[0] = conv2int8((uint8_t)1,7);
+ lf->ref_deltas[1] = conv2int8((uint8_t)0,7);
+ lf->ref_deltas[2] = conv2int8((uint8_t)0,7);
+ lf->ref_deltas[3] = conv2int8((uint8_t)0,7);
+ lf->ref_deltas[4] = conv2int8((uint8_t)0xff,7);
+ lf->ref_deltas[5] = conv2int8((uint8_t)0,7);
+ lf->ref_deltas[6] = conv2int8((uint8_t)0xff,7);
+ lf->ref_deltas[7] = conv2int8((uint8_t)0xff,7);
+ lf->mode_deltas[0] = conv2int8((uint8_t)0,7);
+ lf->mode_deltas[1] = conv2int8((uint8_t)0,7);
+ } else {
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "[test.c] mode_ref_delta copy from prev_frame\n");
+ lf->ref_deltas[0] = cm->prev_frame->ref_deltas[0];
+ lf->ref_deltas[1] = cm->prev_frame->ref_deltas[1];
+ lf->ref_deltas[2] = cm->prev_frame->ref_deltas[2];
+ lf->ref_deltas[3] = cm->prev_frame->ref_deltas[3];
+ lf->ref_deltas[4] = cm->prev_frame->ref_deltas[4];
+ lf->ref_deltas[5] = cm->prev_frame->ref_deltas[5];
+ lf->ref_deltas[6] = cm->prev_frame->ref_deltas[6];
+ lf->ref_deltas[7] = cm->prev_frame->ref_deltas[7];
+ lf->mode_deltas[0] = cm->prev_frame->mode_deltas[0];
+ lf->mode_deltas[1] = cm->prev_frame->mode_deltas[1];
+ }
+ }
+ lf->filter_level[0] = hw->aom_param.p.loop_filter_level_0;
+ lf->filter_level[1] = hw->aom_param.p.loop_filter_level_1;
+ lf->filter_level_u = hw->aom_param.p.loop_filter_level_u;
+ lf->filter_level_v = hw->aom_param.p.loop_filter_level_v;
+
+ cm->cur_frame->ref_deltas[0] = lf->ref_deltas[0];
+ cm->cur_frame->ref_deltas[1] = lf->ref_deltas[1];
+ cm->cur_frame->ref_deltas[2] = lf->ref_deltas[2];
+ cm->cur_frame->ref_deltas[3] = lf->ref_deltas[3];
+ cm->cur_frame->ref_deltas[4] = lf->ref_deltas[4];
+ cm->cur_frame->ref_deltas[5] = lf->ref_deltas[5];
+ cm->cur_frame->ref_deltas[6] = lf->ref_deltas[6];
+ cm->cur_frame->ref_deltas[7] = lf->ref_deltas[7];
+ cm->cur_frame->mode_deltas[0] = lf->mode_deltas[0];
+ cm->cur_frame->mode_deltas[1] = lf->mode_deltas[1];
+
+ // get seg_4lf parameters from parser
+ seg_4lf->enabled = hw->aom_param.p.segmentation_enabled & 1;
+ cm->cur_frame->segmentation_enabled = hw->aom_param.p.segmentation_enabled & 1;
+ cm->cur_frame->intra_only = (hw->aom_param.p.segmentation_enabled >> 2) & 1;
+ cm->cur_frame->segmentation_update_map = (hw->aom_param.p.segmentation_enabled >> 3) & 1;
+
+ if (hw->aom_param.p.segmentation_enabled & 1) { // segmentation_enabled
+ if (hw->aom_param.p.segmentation_enabled & 2) { // segmentation_update_data
+ for (i = 0; i < MAX_SEGMENTS; i++) {
+ seg_4lf->seg_lf_info_y[i] = hw->aom_param.p.seg_lf_info_y[i];
+ seg_4lf->seg_lf_info_c[i] = hw->aom_param.p.seg_lf_info_c[i];
+ #ifdef DBG_LPF_PRINT
+ printk(" read seg_lf_info [%d] : 0x%x, 0x%x\n",
+ i, seg_4lf->seg_lf_info_y[i], seg_4lf->seg_lf_info_c[i]);
+ #endif
+ }
+ } // segmentation_update_data
+ else { // no segmentation_update_data
+ if (cm->prev_frame <= 0) {
+ for (i=0;i<MAX_SEGMENTS;i++) {
+ seg_4lf->seg_lf_info_y[i] = 0;
+ seg_4lf->seg_lf_info_c[i] = 0;
+ }
+ } else {
+ for (i = 0; i < MAX_SEGMENTS; i++) {
+ seg_4lf->seg_lf_info_y[i] = cm->prev_frame->seg_lf_info_y[i];
+ seg_4lf->seg_lf_info_c[i] = cm->prev_frame->seg_lf_info_c[i];
+ #ifdef DBG_LPF_PRINT
+ printk(" Refrence seg_lf_info [%d] : 0x%x, 0x%x\n",
+ i, seg_4lf->seg_lf_info_y[i], seg_4lf->seg_lf_info_c[i]);
+ #endif
+ }
+ }
+ } // no segmentation_update_data
+ } // segmentation_enabled
+ else {
+ for (i=0;i<MAX_SEGMENTS;i++) {
+ seg_4lf->seg_lf_info_y[i] = 0;
+ seg_4lf->seg_lf_info_c[i] = 0;
+ }
+ } // NOT segmentation_enabled
+ for (i=0;i<MAX_SEGMENTS;i++) {
+ cm->cur_frame->seg_lf_info_y[i] = seg_4lf->seg_lf_info_y[i];
+ cm->cur_frame->seg_lf_info_c[i] = seg_4lf->seg_lf_info_c[i];
+#ifdef DBG_LPF_PRINT
+ printk(" SAVE seg_lf_info [%d] : 0x%x, 0x%x\n",
+ i, cm->cur_frame->seg_lf_info_y[i],
+ cm->cur_frame->seg_lf_info_c[i]);
+#endif
+ }
+
+ /*
+ * Update loop filter Thr/Lvl table for every frame
+ */
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "[test.c] av1_loop_filter_frame_init (run before every frame decoding start)\n");
+ av1_loop_filter_frame_init(pbi, seg_4lf, lfi, lf, cm->dec_width);
+#endif // not DUAL_DECODE
+#endif
+
+#ifdef AOM_AV1_UPSCALE_INIT
+ /*
+ * init for upscaling
+ */
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "[test.c] av1_upscale_frame_init (run before every frame decoding start)\n");
+ av1_upscale_frame_init(pbi,
+ &pbi->common, &hw->aom_param);
+#endif // #ifdef AOM_AV1_UPSCALE_INIT
+
+ //BuffInfo_t* buf_spec = pbi->work_space_buf;
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "[test.c] cur_frame : %p prev_frame : %p - %p \n",
+ cm->cur_frame, cm->prev_frame, av1_get_primary_ref_frame_buf(cm));
+ if (cm->cur_frame <= 0) {
+ WRITE_VREG(AOM_AV1_CDF_BUFFER_W, buf_spec->cdf_buf.buf_start);
+ WRITE_VREG(AOM_AV1_SEG_MAP_BUFFER_W, buf_spec->seg_map.buf_start);
+ }
+ else {
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "[test.c] Config WRITE CDF_BUF/SEG_MAP_BUF : %d\n",
+ cur_pic_config->index);
+ WRITE_VREG(AOM_AV1_CDF_BUFFER_W,
+ buf_spec->cdf_buf.buf_start + (0x8000*cur_pic_config->index));
+ WRITE_VREG(AOM_AV1_SEG_MAP_BUFFER_W,
+ buf_spec->seg_map.buf_start + (seg_map_size*cur_pic_config->index));
+ }
+ cm->cur_frame->seg_mi_rows = cm->cur_frame->mi_rows;
+ cm->cur_frame->seg_mi_cols = cm->cur_frame->mi_cols;
+ if (cm->prev_frame <= 0) {
+ WRITE_VREG(AOM_AV1_CDF_BUFFER_R, buf_spec->cdf_buf.buf_start);
+ WRITE_VREG(AOM_AV1_SEG_MAP_BUFFER_R, buf_spec->seg_map.buf_start);
+ } else {
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "[test.c] Config READ CDF_BUF/SEG_MAP_BUF : %d\n",
+ prev_pic_config->index);
+ WRITE_VREG(AOM_AV1_CDF_BUFFER_R,
+ buf_spec->cdf_buf.buf_start + (0x8000*prev_pic_config->index));
+ WRITE_VREG(AOM_AV1_SEG_MAP_BUFFER_R,
+ buf_spec->seg_map.buf_start + (seg_map_size*prev_pic_config->index));
+
+ // segmentation_enabled but no segmentation_update_data
+ if ((hw->aom_param.p.segmentation_enabled & 3) == 1) {
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "[test.c] segfeatures_copy from prev_frame\n");
+ for (i = 0; i < 8; i++) {
+ WRITE_VREG(AOM_AV1_SEGMENT_FEATURE,
+ cm->prev_frame->segment_feature[i]);
+ }
+ }
+ // segmentation_enabled but no segmentation_update_map
+ if ((hw->aom_param.p.segmentation_enabled & 9) == 1) {
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "[test.c] seg_map_size copy from prev_frame\n");
+ cm->cur_frame->seg_mi_rows = cm->prev_frame->seg_mi_rows;
+ cm->cur_frame->seg_mi_cols = cm->prev_frame->seg_mi_cols;
+ }
+ }
+#ifdef PRINT_HEVC_DATA_PATH_MONITOR
+ {
+ uint32_t total_clk_count;
+ uint32_t path_transfer_count;
+ uint32_t path_wait_count;
+ float path_wait_ratio;
+ if (pbi->decode_idx > 1) {
+ WRITE_VREG(HEVC_PATH_MONITOR_CTRL, 0); // Disabble monitor and set rd_idx to 0
+ total_clk_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
+
+ WRITE_VREG(HEVC_PATH_MONITOR_CTRL, (1<<4)); // Disabble monitor and set rd_idx to 0
+
+ // parser --> iqit
+ path_transfer_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
+ path_wait_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
+ if (path_transfer_count == 0)
+ path_wait_ratio = 0.0;
+ else
+ path_wait_ratio =
+ (float)path_wait_count/(float)path_transfer_count;
+ printk("[P%d HEVC PATH] Parser/IQIT/IPP/DBLK/OW/DDR/CMD WAITING \% : %.2f",
+ pbi->decode_idx - 2,
+ path_wait_ratio);
+
+ // iqit --> ipp
+ path_transfer_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
+ path_wait_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
+ if (path_transfer_count == 0)
+ path_wait_ratio = 0.0;
+ else
+ path_wait_ratio = (float)path_wait_count/(float)path_transfer_count;
+ printk(" %.2f", path_wait_ratio);
+
+ // dblk <-- ipp
+ path_transfer_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
+ path_wait_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
+ if (path_transfer_count == 0)
+ path_wait_ratio = 0.0;
+ else
+ path_wait_ratio = (float)path_wait_count/(float)path_transfer_count;
+ printk(" %.2f", path_wait_ratio);
+
+ // dblk --> ow
+ path_transfer_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
+ path_wait_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
+ if (path_transfer_count == 0)
+ path_wait_ratio = 0.0;
+ else path_wait_ratio =
+ (float)path_wait_count/(float)path_transfer_count;
+ printk(" %.2f", path_wait_ratio);
+
+ // <--> DDR
+ path_transfer_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
+ path_wait_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
+ if (path_transfer_count == 0)
+ path_wait_ratio = 0.0;
+ else path_wait_ratio =
+ (float)path_wait_count/(float)path_transfer_count;
+ printk(" %.2f", path_wait_ratio);
+
+ // CMD
+ path_transfer_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
+ path_wait_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
+ if (path_transfer_count == 0)
+ path_wait_ratio = 0.0;
+ else
+ path_wait_ratio = (float)path_wait_count/(float)path_transfer_count;
+ printk(" %.2f\n", path_wait_ratio);
+ }
+ }
+
+#endif
+
+}
+
+static void aom_config_work_space_hw(struct AV1HW_s *hw, u32 mask)
+{
+ struct BuffInfo_s *buf_spec = hw->work_space_buf;
+ unsigned int data32;
+ av1_print(hw, AOM_DEBUG_HW_MORE, "%s %d\n", __func__, __LINE__);
+ if (debug && hw->init_flag == 0)
+ av1_print(hw, AOM_DEBUG_HW_MORE, "%s %x %x %x %x %x %x %x %x\n",
+ __func__,
+ buf_spec->ipp.buf_start,
+ buf_spec->start_adr,
+ buf_spec->short_term_rps.buf_start,
+ buf_spec->sao_up.buf_start,
+ buf_spec->swap_buf.buf_start,
+ buf_spec->scalelut.buf_start,
+ buf_spec->dblk_para.buf_start,
+ buf_spec->dblk_data.buf_start);
+ if (mask & HW_MASK_FRONT) {
+ av1_print(hw, AOM_DEBUG_HW_MORE, "%s %d\n", __func__, __LINE__);
+ if ((debug & AOM_AV1_DEBUG_SEND_PARAM_WITH_REG) == 0)
+ WRITE_VREG(HEVC_RPM_BUFFER, (u32)hw->rpm_phy_addr);
+
+ WRITE_VREG(HEVC_STREAM_SWAP_BUFFER,
+ buf_spec->swap_buf.buf_start);
+ WRITE_VREG(LMEM_DUMP_ADR, (u32)hw->lmem_phy_addr);
+
+ }
+
+ av1_print(hw, AOM_DEBUG_HW_MORE, "%s %d\n", __func__, __LINE__);
+
+ WRITE_VREG(AOM_AV1_DAALA_TOP_BUFFER,
+ buf_spec->daala_top.buf_start);
+ WRITE_VREG(AV1_GMC_PARAM_BUFF_ADDR,
+ buf_spec->gmc_buf.buf_start);
+
+ WRITE_VREG(HEVC_DBLK_CFG4,
+ buf_spec->dblk_para.buf_start); // cfg_addr_cif
+ WRITE_VREG(HEVC_DBLK_CFG5,
+ buf_spec->dblk_data.buf_start); // cfg_addr_xio
+
+ if (mask & HW_MASK_BACK) {
+#ifdef LOSLESS_COMPRESS_MODE
+ int losless_comp_header_size =
+ compute_losless_comp_header_size(hw->init_pic_w,
+ hw->init_pic_h);
+ int losless_comp_body_size =
+ compute_losless_comp_body_size(hw->init_pic_w,
+ hw->init_pic_h, buf_alloc_depth == 10);
+#endif
+#ifdef AOM_AV1_MMU_DW
+ int losless_comp_header_size_dw =
+ compute_losless_comp_header_size_dw(hw->init_pic_w,
+ hw->init_pic_h);
+ int losless_comp_body_size_dw =
+ compute_losless_comp_body_size_dw(hw->init_pic_w,
+ hw->init_pic_h, buf_alloc_depth == 10);
+#endif
+ WRITE_VREG(HEVCD_IPP_LINEBUFF_BASE,
+ buf_spec->ipp.buf_start);
+ WRITE_VREG(HEVC_SAO_UP, buf_spec->sao_up.buf_start);
+ //WRITE_VREG(HEVC_SCALELUT, buf_spec->scalelut.buf_start);
+#ifdef CHANGE_REMOVED
+ if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
+ /* cfg_addr_adp*/
+ WRITE_VREG(HEVC_DBLK_CFGE, buf_spec->dblk_para.buf_start);
+ if (debug & VP9_DEBUG_BUFMGR_MORE)
+ pr_info("Write HEVC_DBLK_CFGE\n");
+ }
+#endif
+ /* cfg_p_addr */
+ WRITE_VREG(HEVC_DBLK_CFG4, buf_spec->dblk_para.buf_start);
+ /* cfg_d_addr */
+ WRITE_VREG(HEVC_DBLK_CFG5, buf_spec->dblk_data.buf_start);
+
+#ifdef CHANGE_REMOVED
+ if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
+ /*
+ * data32 = (READ_VREG(HEVC_DBLK_CFG3)>>8) & 0xff; // xio left offset, default is 0x40
+ * data32 = data32 * 2;
+ * data32 = (READ_VREG(HEVC_DBLK_CFG3)>>16) & 0xff; // adp left offset, default is 0x040
+ * data32 = data32 * 2;
+ */
+ WRITE_VREG(HEVC_DBLK_CFG3, 0x808010); // make left storage 2 x 4k]
+ }
+#endif
+#ifdef LOSLESS_COMPRESS_MODE
+ if (hw->mmu_enable) {
+ /*bit[4] : paged_mem_mode*/
+ WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
+#ifdef CHANGE_REMOVED
+ if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_SM1)
+#endif
+ WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0);
+ } else {
+ /*if (cur_pic_config->bit_depth == AOM_BITS_10)
+ * WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0<<3));
+ */
+ /*bit[3] smem mdoe*/
+ /*else WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (1<<3));*/
+ /*bit[3] smem mdoe*/
+ WRITE_VREG(HEVCD_MPP_DECOMP_CTL2,
+ (losless_comp_body_size >> 5));
+ }
+ /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL2,
+ (losless_comp_body_size >> 5));*/
+ /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,
+ (0xff<<20) | (0xff<<10) | 0xff);*/
+ /*8-bit mode */
+ WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size);
+ WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size);
+ WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size);
+ if (get_double_write_mode(hw) & 0x10)
+ WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
+#else
+ WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
+#endif
+
+ if (hw->mmu_enable) {
+ WRITE_VREG(HEVC_SAO_MMU_VH0_ADDR, buf_spec->mmu_vbh.buf_start);
+ WRITE_VREG(HEVC_SAO_MMU_VH1_ADDR, buf_spec->mmu_vbh.buf_start
+ + VBH_BUF_SIZE);
+ /*data32 = READ_VREG(HEVC_SAO_CTRL9);*/
+ /*data32 |= 0x1;*/
+ /*WRITE_VREG(HEVC_SAO_CTRL9, data32);*/
+
+ /* use HEVC_CM_HEADER_START_ADDR */
+ data32 = READ_VREG(HEVC_SAO_CTRL5);
+ data32 |= (1<<10);
+ WRITE_VREG(HEVC_SAO_CTRL5, data32);
+ }
+#ifdef AOM_AV1_MMU_DW
+ data32 = READ_VREG(HEVC_SAO_CTRL5);
+ if (hw->dw_mmu_enable) {
+ data32 = READ_VREG(HEVC_SAO_CTRL9);
+ data32 |= (1<<10);
+ WRITE_VREG(HEVC_SAO_CTRL9, data32);
+
+ WRITE_VREG(HEVC_CM_BODY_LENGTH2,losless_comp_body_size_dw);
+ WRITE_VREG(HEVC_CM_HEADER_OFFSET2,losless_comp_body_size_dw);
+ WRITE_VREG(HEVC_CM_HEADER_LENGTH2,losless_comp_header_size_dw);
+
+ WRITE_VREG(HEVC_SAO_MMU_VH0_ADDR2, buf_spec->mmu_vbh_dw.buf_start);
+ WRITE_VREG(HEVC_SAO_MMU_VH1_ADDR2, buf_spec->mmu_vbh_dw.buf_start
+ + VBH_BUF_SIZE);
+
+ WRITE_VREG(HEVC_DW_VH0_ADDDR, buf_spec->mmu_vbh_dw.buf_start
+ + (2 * VBH_BUF_SIZE));
+ WRITE_VREG(HEVC_DW_VH1_ADDDR, buf_spec->mmu_vbh_dw.buf_start
+ + (3 * VBH_BUF_SIZE));
+
+ /* use HEVC_CM_HEADER_START_ADDR */
+ data32 |= (1<<15);
+ } else
+ data32 &= ~(1<<15);
+ WRITE_VREG(HEVC_SAO_CTRL5, data32);
+#endif
+
+ WRITE_VREG(LMEM_DUMP_ADR, (u32)hw->lmem_phy_addr);
+#ifdef CHANGE_REMOVED
+
+ WRITE_VREG(VP9_SEG_MAP_BUFFER, buf_spec->seg_map.buf_start);
+
+ /**/
+ WRITE_VREG(VP9_PROB_SWAP_BUFFER, hw->prob_buffer_phy_addr);
+ WRITE_VREG(VP9_COUNT_SWAP_BUFFER, hw->count_buffer_phy_addr);
+ if (hw->mmu_enable) {
+ if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A)
+ WRITE_VREG(HEVC_ASSIST_MMU_MAP_ADDR, hw->frame_mmu_map_phy_addr);
+ else
+ WRITE_VREG(VP9_MMU_MAP_BUFFER, hw->frame_mmu_map_phy_addr);
+ }
+#else
+ if (hw->mmu_enable)
+ WRITE_VREG(HEVC_SAO_MMU_DMA_CTRL, hw->frame_mmu_map_phy_addr);
+#ifdef AOM_AV1_MMU_DW
+ if (hw->dw_mmu_enable) {
+ WRITE_VREG(HEVC_SAO_MMU_DMA_CTRL2, hw->dw_frame_mmu_map_phy_addr);
+ //default of 0xffffffff will disable dw
+ WRITE_VREG(HEVC_SAO_Y_START_ADDR, 0);
+ WRITE_VREG(HEVC_SAO_C_START_ADDR, 0);
+ }
+#endif
+#endif
+ }
+}
+
+
+static void aom_init_decoder_hw(struct AV1HW_s *hw, u32 mask)
+{
+ unsigned int data32;
+ int i;
+ const unsigned short parser_cmd[PARSER_CMD_NUMBER] = {
+ 0x0401, 0x8401, 0x0800, 0x0402, 0x9002, 0x1423,
+ 0x8CC3, 0x1423, 0x8804, 0x9825, 0x0800, 0x04FE,
+ 0x8406, 0x8411, 0x1800, 0x8408, 0x8409, 0x8C2A,
+ 0x9C2B, 0x1C00, 0x840F, 0x8407, 0x8000, 0x8408,
+ 0x2000, 0xA800, 0x8410, 0x04DE, 0x840C, 0x840D,
+ 0xAC00, 0xA000, 0x08C0, 0x08E0, 0xA40E, 0xFC00,
+ 0x7C00
+ };
+#if 0
+ if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
+ /* Set MCR fetch priorities*/
+ data32 = 0x1 | (0x1 << 2) | (0x1 <<3) |
+ (24 << 4) | (32 << 11) | (24 << 18) | (32 << 25);
+ WRITE_VREG(HEVCD_MPP_DECOMP_AXIURG_CTL, data32);
+ }
+#endif
+ /*if (debug & VP9_DEBUG_BUFMGR_MORE)
+ pr_info("%s\n", __func__);*/
+ if (mask & HW_MASK_FRONT) {
+ data32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
+#ifdef CHANGE_REMOVED
+#if 1
+ /* set bit 31~29 to 3 if HEVC_STREAM_FIFO_CTL[29] is 1 */
+ data32 &= ~(7 << 29);
+ data32 |= (3 << 29);
+#endif
+ data32 = data32 |
+ (1 << 24) |/*stream_buffer_empty_int_amrisc_enable*/
+ (1 << 22) |/*stream_fifo_empty_int_amrisc_enable*/
+ (1 << 7) |/*dec_done_int_cpu_enable*/
+ (1 << 4) |/*startcode_found_int_cpu_enable*/
+ (0 << 3) |/*startcode_found_int_amrisc_enable*/
+ (1 << 0) /*parser_int_enable*/
+ ;
+#else
+ data32 = data32 & 0x1fffffff;
+ data32 = data32 |
+ (3 << 29) | // stream_buffer_empty_int_ctl ( 0x200 interrupt)
+ (1 << 24) | // stream_buffer_empty_int_amrisc_enable
+ (1 << 22) | // stream_fifo_empty_int_amrisc_enable
+ (1 << 7) | // dec_done_int_cpu_enable
+ (1 << 4) | // startcode_found_int_cpu_enable
+ (0 << 3) | // startcode_found_int_amrisc_enable
+ (1 << 0) // parser_int_enable
+ ;
+
+#endif
+ WRITE_VREG(HEVC_PARSER_INT_CONTROL, data32);
+
+ data32 = READ_VREG(HEVC_SHIFT_STATUS);
+ data32 = data32 |
+ (0 << 1) |/*emulation_check_off AV1
+ do not have emulation*/
+ (1 << 0)/*startcode_check_on*/
+ ;
+ WRITE_VREG(HEVC_SHIFT_STATUS, data32);
+ WRITE_VREG(HEVC_SHIFT_CONTROL,
+ (0 << 14) | /*disable_start_code_protect*/
+ (1 << 10) | /*length_zero_startcode_en for AV1*/
+ (1 << 9) | /*length_valid_startcode_en for AV1*/
+ (3 << 6) | /*sft_valid_wr_position*/
+ (2 << 4) | /*emulate_code_length_sub_1*/
+ (3 << 1) | /*start_code_length_sub_1
+ AV1 use 0x00000001 as startcode (4 Bytes)*/
+ (1 << 0) /*stream_shift_enable*/
+ );
+
+ WRITE_VREG(HEVC_CABAC_CONTROL,
+ (1 << 0)/*cabac_enable*/
+ );
+
+ WRITE_VREG(HEVC_PARSER_CORE_CONTROL,
+ (1 << 0)/* hevc_parser_core_clk_en*/
+ );
+
+
+ WRITE_VREG(HEVC_DEC_STATUS_REG, 0);
+
+ }
+
+ if (mask & HW_MASK_BACK) {
+ /*Initial IQIT_SCALELUT memory
+ -- just to avoid X in simulation*/
+
+ WRITE_VREG(HEVC_IQIT_SCALELUT_WR_ADDR, 0);/*cfg_p_addr*/
+ for (i = 0; i < 1024; i++)
+ WRITE_VREG(HEVC_IQIT_SCALELUT_DATA, 0);
+ }
+
+ if (mask & HW_MASK_FRONT) {
+ u32 decode_mode;
+#ifdef ENABLE_SWAP_TEST
+ WRITE_VREG(HEVC_STREAM_SWAP_TEST, 100);
+#else
+ WRITE_VREG(HEVC_STREAM_SWAP_TEST, 0);
+#endif
+#ifdef MULTI_INSTANCE_SUPPORT
+ if (!hw->m_ins_flag) {
+ if (hw->low_latency_flag)
+ decode_mode = DECODE_MODE_SINGLE_LOW_LATENCY;
+ else
+ decode_mode = DECODE_MODE_SINGLE;
+ } else if (vdec_frame_based(hw_to_vdec(hw)))
+ decode_mode = hw->no_head ?
+ DECODE_MODE_MULTI_FRAMEBASE_NOHEAD :
+ DECODE_MODE_MULTI_FRAMEBASE;
+ else
+ decode_mode = DECODE_MODE_MULTI_STREAMBASE;
+ if (debug & AOM_DEBUG_BUFMGR_ONLY)
+ decode_mode |= (1 << 16);
+ WRITE_VREG(DECODE_MODE, decode_mode);
+ WRITE_VREG(HEVC_DECODE_SIZE, 0);
+ WRITE_VREG(HEVC_DECODE_COUNT, 0);
+#else
+ WRITE_VREG(DECODE_MODE, DECODE_MODE_SINGLE);
+ WRITE_VREG(HEVC_DECODE_PIC_BEGIN_REG, 0);
+ WRITE_VREG(HEVC_DECODE_PIC_NUM_REG, 0x7fffffff); /*to remove*/
+#endif
+ /*Send parser_cmd*/
+ WRITE_VREG(HEVC_PARSER_CMD_WRITE, (1 << 16) | (0 << 0));
+ for (i = 0; i < PARSER_CMD_NUMBER; i++)
+ WRITE_VREG(HEVC_PARSER_CMD_WRITE, parser_cmd[i]);
+ WRITE_VREG(HEVC_PARSER_CMD_SKIP_0, PARSER_CMD_SKIP_CFG_0);
+ WRITE_VREG(HEVC_PARSER_CMD_SKIP_1, PARSER_CMD_SKIP_CFG_1);
+ WRITE_VREG(HEVC_PARSER_CMD_SKIP_2, PARSER_CMD_SKIP_CFG_2);
+
+
+ WRITE_VREG(HEVC_PARSER_IF_CONTROL,
+ /* (1 << 8) |*/ /*sao_sw_pred_enable*/
+ (1 << 5) | /*parser_sao_if_en*/
+ (1 << 2) | /*parser_mpred_if_en*/
+ (1 << 0) /*parser_scaler_if_en*/
+ );
+ }
+
+ if (mask & HW_MASK_BACK) {
+ /*Changed to Start MPRED in microcode*/
+ /*
+ pr_info("[test.c] Start MPRED\n");
+ WRITE_VREG(HEVC_MPRED_INT_STATUS,
+ (1<<31)
+ );
+ */
+ WRITE_VREG(HEVCD_IPP_TOP_CNTL,
+ (0 << 1) | /*enable ipp*/
+ (1 << 0) /*software reset ipp and mpp*/
+ );
+#ifdef CHANGE_REMOVED
+ WRITE_VREG(HEVCD_IPP_TOP_CNTL,
+ (1 << 1) | /*enable ipp*/
+ (0 << 0) /*software reset ipp and mpp*/
+ );
+#else
+ WRITE_VREG(HEVCD_IPP_TOP_CNTL,
+ (3 << 4) | // av1
+ (1 << 1) | /*enable ipp*/
+ (0 << 0) /*software reset ipp and mpp*/
+ );
+#endif
+ if (get_double_write_mode(hw) & 0x10) {
+ /*Enable NV21 reference read mode for MC*/
+ WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
+ }
+#ifndef TO_CHANGE
+ /*Initialize mcrcc and decomp perf counters*/
+ if (mcrcc_cache_alg_flag &&
+ hw->init_flag == 0) {
+ mcrcc_perfcount_reset();
+ decomp_perfcount_reset();
+ }
+#endif
+ }
+#ifdef CHANGE_REMOVED
+#else
+// Set MCR fetch priorities
+ data32 = 0x1 | (0x1 << 2) | (0x1 <<3) |
+ (24 << 4) | (32 << 11) | (24 << 18) | (32 << 25);
+ WRITE_VREG(HEVCD_MPP_DECOMP_AXIURG_CTL, data32);
+#endif
+ return;
+}
+
+
+#ifdef CONFIG_HEVC_CLK_FORCED_ON
+static void config_av1_clk_forced_on(void)
+{
+ unsigned int rdata32;
+ /*IQIT*/
+ rdata32 = READ_VREG(HEVC_IQIT_CLK_RST_CTRL);
+ WRITE_VREG(HEVC_IQIT_CLK_RST_CTRL, rdata32 | (0x1 << 2));
+
+ /* DBLK*/
+ rdata32 = READ_VREG(HEVC_DBLK_CFG0);
+ WRITE_VREG(HEVC_DBLK_CFG0, rdata32 | (0x1 << 2));
+
+ /* SAO*/
+ rdata32 = READ_VREG(HEVC_SAO_CTRL1);
+ WRITE_VREG(HEVC_SAO_CTRL1, rdata32 | (0x1 << 2));
+
+ /*MPRED*/
+ rdata32 = READ_VREG(HEVC_MPRED_CTRL1);
+ WRITE_VREG(HEVC_MPRED_CTRL1, rdata32 | (0x1 << 24));
+
+ /* PARSER*/
+ rdata32 = READ_VREG(HEVC_STREAM_CONTROL);
+ WRITE_VREG(HEVC_STREAM_CONTROL, rdata32 | (0x1 << 15));
+ rdata32 = READ_VREG(HEVC_SHIFT_CONTROL);
+ WRITE_VREG(HEVC_SHIFT_CONTROL, rdata32 | (0x1 << 15));
+ rdata32 = READ_VREG(HEVC_CABAC_CONTROL);
+ WRITE_VREG(HEVC_CABAC_CONTROL, rdata32 | (0x1 << 13));
+ rdata32 = READ_VREG(HEVC_PARSER_CORE_CONTROL);
+ WRITE_VREG(HEVC_PARSER_CORE_CONTROL, rdata32 | (0x1 << 15));
+ rdata32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
+ WRITE_VREG(HEVC_PARSER_INT_CONTROL, rdata32 | (0x1 << 15));
+ rdata32 = READ_VREG(HEVC_PARSER_IF_CONTROL);
+ WRITE_VREG(HEVC_PARSER_IF_CONTROL,
+ rdata32 | (0x1 << 6) | (0x1 << 3) | (0x1 << 1));
+
+ /*IPP*/
+ rdata32 = READ_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG);
+ WRITE_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG, rdata32 | 0xffffffff);
+
+ /* MCRCC*/
+ rdata32 = READ_VREG(HEVCD_MCRCC_CTL1);
+ WRITE_VREG(HEVCD_MCRCC_CTL1, rdata32 | (0x1 << 3));
+}
+#endif
+
+
+
+static void av1_local_uninit(struct AV1HW_s *hw)
+{
+ hw->rpm_ptr = NULL;
+ hw->lmem_ptr = NULL;
+ if (hw->rpm_addr) {
+ dma_free_coherent(amports_get_dma_device(),
+ RPM_BUF_SIZE,
+ hw->rpm_addr,
+ hw->rpm_phy_addr);
+ hw->rpm_addr = NULL;
+ }
+ if (hw->lmem_addr) {
+ if (hw->lmem_phy_addr)
+ dma_free_coherent(amports_get_dma_device(),
+ LMEM_BUF_SIZE, hw->lmem_addr,
+ hw->lmem_phy_addr);
+ hw->lmem_addr = NULL;
+ }
+ if (hw->prob_buffer_addr) {
+ if (hw->prob_buffer_phy_addr)
+ dma_free_coherent(amports_get_dma_device(),
+ PROB_BUF_SIZE, hw->prob_buffer_addr,
+ hw->prob_buffer_phy_addr);
+
+ hw->prob_buffer_addr = NULL;
+ }
+ if (hw->count_buffer_addr) {
+ if (hw->count_buffer_phy_addr)
+ dma_free_coherent(amports_get_dma_device(),
+ COUNT_BUF_SIZE, hw->count_buffer_addr,
+ hw->count_buffer_phy_addr);
+
+ hw->count_buffer_addr = NULL;
+ }
+ if (hw->mmu_enable) {
+ u32 mmu_map_size = vav1_frame_mmu_map_size(hw);
+ if (hw->frame_mmu_map_addr) {
+ if (hw->frame_mmu_map_phy_addr)
+ dma_free_coherent(amports_get_dma_device(),
+ mmu_map_size,
+ hw->frame_mmu_map_addr,
+ hw->frame_mmu_map_phy_addr);
+ hw->frame_mmu_map_addr = NULL;
+ }
+ }
+#ifdef AOM_AV1_MMU_DW
+ if (hw->dw_mmu_enable) {
+ u32 mmu_map_size = vaom_dw_frame_mmu_map_size(hw);
+ if (hw->dw_frame_mmu_map_addr) {
+ if (hw->dw_frame_mmu_map_phy_addr)
+ dma_free_coherent(amports_get_dma_device(),
+ mmu_map_size,
+ hw->dw_frame_mmu_map_addr,
+ hw->dw_frame_mmu_map_phy_addr);
+ hw->dw_frame_mmu_map_addr = NULL;
+ }
+ }
+#endif
+ if (hw->gvs)
+ vfree(hw->gvs);
+ hw->gvs = NULL;
+}
+
+static int av1_local_init(struct AV1HW_s *hw)
+{
+ int ret = -1;
+ /*int losless_comp_header_size, losless_comp_body_size;*/
+
+ struct BuffInfo_s *cur_buf_info = NULL;
+
+ memset(&hw->param, 0, sizeof(union param_u));
+#ifdef MULTI_INSTANCE_SUPPORT
+ cur_buf_info = &hw->work_space_buf_store;
+ hw->pbi->work_space_buf = cur_buf_info;
+
+ if (vdec_is_support_4k()) {
+ memcpy(cur_buf_info, &aom_workbuff_spec[1], /* 8k */
+ sizeof(struct BuffInfo_s));
+ } else
+ memcpy(cur_buf_info, &aom_workbuff_spec[0],/* 1080p */
+ sizeof(struct BuffInfo_s));
+
+ cur_buf_info->start_adr = hw->buf_start;
+ if (!hw->mmu_enable)
+ hw->mc_buf_spec.buf_end = hw->buf_start + hw->buf_size;
+
+#else
+/*! MULTI_INSTANCE_SUPPORT*/
+ if (vdec_is_support_4k()) {
+ if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
+ cur_buf_info = &aom_workbuff_spec[1];/* 8k work space */
+ else
+ cur_buf_info = &aom_workbuff_spec[1];/* 4k2k work space */
+ } else
+ cur_buf_info = &aom_workbuff_spec[0];/* 1080p work space */
+
+#endif
+
+ init_buff_spec(hw, cur_buf_info);
+ aom_bufmgr_init(hw, cur_buf_info, NULL);
+
+ if (!vdec_is_support_4k()
+ && (buf_alloc_width > 1920 && buf_alloc_height > 1088)) {
+ buf_alloc_width = 1920;
+ buf_alloc_height = 1088;
+ if (hw->max_pic_w > 1920 && hw->max_pic_h > 1088) {
+ hw->max_pic_w = 1920;
+ hw->max_pic_h = 1088;
+ }
+ } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
+ buf_alloc_width = 8192;
+ buf_alloc_height = 4608;
+ }
+ hw->init_pic_w = hw->max_pic_w ? hw->max_pic_w :
+ (buf_alloc_width ? buf_alloc_width :
+ (hw->vav1_amstream_dec_info.width ?
+ hw->vav1_amstream_dec_info.width :
+ hw->work_space_buf->max_width));
+ hw->init_pic_h = hw->max_pic_h ? hw->max_pic_h :
+ (buf_alloc_height ? buf_alloc_height :
+ (hw->vav1_amstream_dec_info.height ?
+ hw->vav1_amstream_dec_info.height :
+ hw->work_space_buf->max_height));
+
+ hw->pbi->frame_width = hw->init_pic_w;
+ hw->pbi->frame_height = hw->init_pic_h;
+
+ /* video is not support unaligned with 64 in tl1
+ ** vdec canvas mode will be linear when dump yuv is set
+ */
+ if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
+ (hw->double_write_mode != 0) &&
+ (((hw->max_pic_w % 64) != 0) ||
+ (hw->vav1_amstream_dec_info.width % 64) != 0)) {
+ if (hw_to_vdec(hw)->canvas_mode !=
+ CANVAS_BLKMODE_LINEAR)
+ mem_map_mode = 2;
+ else {
+ mem_map_mode = 0;
+ av1_print(hw, AOM_DEBUG_HW_MORE, "vdec blkmod linear, force mem_map_mode 0\n");
+ }
+ }
+
+#ifndef MV_USE_FIXED_BUF
+ if (init_mv_buf_list(hw) < 0) {
+ pr_err("%s: init_mv_buf_list fail\n", __func__);
+ return -1;
+ }
+#endif
+ if (hw->save_buffer_mode)
+ hw->used_buf_num = MAX_BUF_NUM_SAVE_BUF;
+ else
+ hw->used_buf_num = max_buf_num;
+
+ if (hw->used_buf_num > MAX_BUF_NUM)
+ hw->used_buf_num = MAX_BUF_NUM;
+ if (hw->used_buf_num > FRAME_BUFFERS)
+ hw->used_buf_num = FRAME_BUFFERS;
+
+ hw->pts_unstable = ((unsigned long)(hw->vav1_amstream_dec_info.param)
+ & 0x40) >> 6;
+
+ if ((debug & AOM_AV1_DEBUG_SEND_PARAM_WITH_REG) == 0) {
+ hw->rpm_addr = dma_alloc_coherent(amports_get_dma_device(),
+ RPM_BUF_SIZE,
+ &hw->rpm_phy_addr, GFP_KERNEL);
+ if (hw->rpm_addr == NULL) {
+ pr_err("%s: failed to alloc rpm buffer\n", __func__);
+ return -1;
+ }
+
+ hw->rpm_ptr = hw->rpm_addr;
+ }
+
+ hw->lmem_addr = dma_alloc_coherent(amports_get_dma_device(),
+ LMEM_BUF_SIZE,
+ &hw->lmem_phy_addr, GFP_KERNEL);
+ if (hw->lmem_addr == NULL) {
+ pr_err("%s: failed to alloc lmem buffer\n", __func__);
+ return -1;
+ }
+ hw->lmem_ptr = hw->lmem_addr;
+
+ hw->prob_buffer_addr = dma_alloc_coherent(amports_get_dma_device(),
+ PROB_BUF_SIZE,
+ &hw->prob_buffer_phy_addr, GFP_KERNEL);
+ if (hw->prob_buffer_addr == NULL) {
+ pr_err("%s: failed to alloc prob_buffer\n", __func__);
+ return -1;
+ }
+ memset(hw->prob_buffer_addr, 0, PROB_BUF_SIZE);
+ hw->count_buffer_addr = dma_alloc_coherent(amports_get_dma_device(),
+ COUNT_BUF_SIZE,
+ &hw->count_buffer_phy_addr, GFP_KERNEL);
+ if (hw->count_buffer_addr == NULL) {
+ pr_err("%s: failed to alloc count_buffer\n", __func__);
+ return -1;
+ }
+ memset(hw->count_buffer_addr, 0, COUNT_BUF_SIZE);
+
+ if (hw->mmu_enable) {
+ u32 mmu_map_size = vav1_frame_mmu_map_size(hw);
+ hw->frame_mmu_map_addr =
+ dma_alloc_coherent(amports_get_dma_device(),
+ mmu_map_size,
+ &hw->frame_mmu_map_phy_addr, GFP_KERNEL);
+ if (hw->frame_mmu_map_addr == NULL) {
+ pr_err("%s: failed to alloc count_buffer\n", __func__);
+ return -1;
+ }
+ memset(hw->frame_mmu_map_addr, 0, mmu_map_size);
+ }
+#ifdef AOM_AV1_MMU_DW
+ if (hw->dw_mmu_enable) {
+ u32 mmu_map_size = vaom_dw_frame_mmu_map_size(hw);
+ hw->dw_frame_mmu_map_addr =
+ dma_alloc_coherent(amports_get_dma_device(),
+ mmu_map_size,
+ &hw->dw_frame_mmu_map_phy_addr, GFP_KERNEL);
+ if (hw->dw_frame_mmu_map_addr == NULL) {
+ pr_err("%s: failed to alloc count_buffer\n", __func__);
+ return -1;
+ }
+ memset(hw->dw_frame_mmu_map_addr, 0, mmu_map_size);
+ }
+#endif
+ ret = 0;
+ return ret;
+}
+
+
+#define spec2canvas(x) \
+ (((x)->uv_canvas_index << 16) | \
+ ((x)->uv_canvas_index << 8) | \
+ ((x)->y_canvas_index << 0))
+
+
+static void set_canvas(struct AV1HW_s *hw,
+ struct PIC_BUFFER_CONFIG_s *pic_config)
+{
+ struct vdec_s *vdec = hw_to_vdec(hw);
+ int canvas_w = ALIGN(pic_config->y_crop_width, 64)/4;
+ int canvas_h = ALIGN(pic_config->y_crop_height, 32)/4;
+ int blkmode = mem_map_mode;
+ /*CANVAS_BLKMODE_64X32*/
+ if (pic_config->double_write_mode) {
+ canvas_w = pic_config->y_crop_width /
+ get_double_write_ratio(hw,
+ pic_config->double_write_mode);
+ canvas_h = pic_config->y_crop_height /
+ get_double_write_ratio(hw,
+ pic_config->double_write_mode);
+
+ if (mem_map_mode == 0)
+ canvas_w = ALIGN(canvas_w, 32);
+ else
+ canvas_w = ALIGN(canvas_w, 64);
+ canvas_h = ALIGN(canvas_h, 32);
+
+ if (vdec->parallel_dec == 1) {
+ if (pic_config->y_canvas_index == -1)
+ pic_config->y_canvas_index =
+ vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
+ if (pic_config->uv_canvas_index == -1)
+ pic_config->uv_canvas_index =
+ vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
+ } else {
+ pic_config->y_canvas_index = 128 + pic_config->index * 2;
+ pic_config->uv_canvas_index = 128 + pic_config->index * 2 + 1;
+ }
+
+ canvas_config_ex(pic_config->y_canvas_index,
+ pic_config->dw_y_adr, canvas_w, canvas_h,
+ CANVAS_ADDR_NOWRAP, blkmode, 0x7);
+ canvas_config_ex(pic_config->uv_canvas_index,
+ pic_config->dw_u_v_adr, canvas_w, canvas_h,
+ CANVAS_ADDR_NOWRAP, blkmode, 0x7);
+
+#ifdef MULTI_INSTANCE_SUPPORT
+ pic_config->canvas_config[0].phy_addr =
+ pic_config->dw_y_adr;
+ pic_config->canvas_config[0].width =
+ canvas_w;
+ pic_config->canvas_config[0].height =
+ canvas_h;
+ pic_config->canvas_config[0].block_mode =
+ blkmode;
+ pic_config->canvas_config[0].endian = 7;
+
+ pic_config->canvas_config[1].phy_addr =
+ pic_config->dw_u_v_adr;
+ pic_config->canvas_config[1].width =
+ canvas_w;
+ pic_config->canvas_config[1].height =
+ canvas_h;
+ pic_config->canvas_config[1].block_mode =
+ blkmode;
+ pic_config->canvas_config[1].endian = 7;
+#endif
+ }
+}
+
+static void set_frame_info(struct AV1HW_s *hw, struct vframe_s *vf)
+{
+ unsigned int ar;
+ vf->duration = hw->frame_dur;
+ vf->duration_pulldown = 0;
+ vf->flag = 0;
+ vf->prop.master_display_colour = hw->vf_dp;
+ vf->signal_type = hw->video_signal_type;
+ if (vf->compWidth && vf->compHeight)
+ hw->frame_ar = vf->compHeight * 0x100 / vf->compWidth;
+ ar = min_t(u32, hw->frame_ar, DISP_RATIO_ASPECT_RATIO_MAX);
+ vf->ratio_control = (ar << DISP_RATIO_ASPECT_RATIO_BIT);
+
+}
+
+static int vav1_vf_states(struct vframe_states *states, void *op_arg)
+{
+ struct AV1HW_s *hw = (struct AV1HW_s *)op_arg;
+
+ states->vf_pool_size = VF_POOL_SIZE;
+ states->buf_free_num = kfifo_len(&hw->newframe_q);
+ states->buf_avail_num = kfifo_len(&hw->display_q);
+
+ if (step == 2)
+ states->buf_avail_num = 0;
+ return 0;
+}
+
+static struct vframe_s *vav1_vf_peek(void *op_arg)
+{
+ struct vframe_s *vf[2] = {0, 0};
+ struct AV1HW_s *hw = (struct AV1HW_s *)op_arg;
+
+ if (step == 2)
+ return NULL;
+
+ if (kfifo_out_peek(&hw->display_q, (void *)&vf, 2)) {
+ if (vf[1]) {
+ vf[0]->next_vf_pts_valid = true;
+ vf[0]->next_vf_pts = vf[1]->pts;
+ } else
+ vf[0]->next_vf_pts_valid = false;
+ return vf[0];
+ }
+
+ return NULL;
+}
+
+static struct vframe_s *vav1_vf_get(void *op_arg)
+{
+ struct vframe_s *vf;
+ struct AV1HW_s *hw = (struct AV1HW_s *)op_arg;
+
+ if (step == 2)
+ return NULL;
+ else if (step == 1)
+ step = 2;
+
+ if (kfifo_get(&hw->display_q, &vf)) {
+ struct vframe_s *next_vf;
+ uint8_t index = vf->index & 0xff;
+ if (index < hw->used_buf_num) {
+ hw->vf_get_count++;
+ if (debug & AOM_DEBUG_VFRAME) {
+ unsigned long flags;
+ lock_buffer_pool(hw->pbi->common.buffer_pool, flags);
+ av1_print(hw, AOM_DEBUG_VFRAME, "%s index 0x%x type 0x%x w/h %d/%d, pts %d, %lld\n",
+ __func__, vf->index, vf->type,
+ vf->width, vf->height,
+ vf->pts,
+ vf->pts_us64);
+ unlock_buffer_pool(hw->pbi->common.buffer_pool, flags);
+ }
+
+ if (kfifo_peek(&hw->display_q, &next_vf)) {
+ vf->next_vf_pts_valid = true;
+ vf->next_vf_pts = next_vf->pts;
+ } else
+ vf->next_vf_pts_valid = false;
+
+ return vf;
+ }
+ }
+ return NULL;
+}
+
+static void vav1_vf_put(struct vframe_s *vf, void *op_arg)
+{
+ struct AV1HW_s *hw = (struct AV1HW_s *)op_arg;
+ uint8_t index = vf->index & 0xff;
+ unsigned long flags;
+
+ kfifo_put(&hw->newframe_q, (const struct vframe_s *)vf);
+ hw->vf_put_count++;
+ if (debug & AOM_DEBUG_VFRAME) {
+ lock_buffer_pool(hw->pbi->common.buffer_pool, flags);
+ av1_print(hw, AOM_DEBUG_VFRAME, "%s index 0x%x type 0x%x w/h %d/%d, pts %d, %lld\n",
+ __func__, vf->index, vf->type,
+ vf->width, vf->height,
+ vf->pts,
+ vf->pts_us64);
+ unlock_buffer_pool(hw->pbi->common.buffer_pool, flags);
+ }
+
+ if (index < hw->used_buf_num) {
+ struct AV1_Common_s *cm = &hw->pbi->common;
+ struct BufferPool_s *pool = cm->buffer_pool;
+
+ lock_buffer_pool(hw->pbi->common.buffer_pool, flags);
+ if ((debug & VP9_DEBUG_IGNORE_VF_REF) == 0) {
+ if (pool->frame_bufs[index].buf.vf_ref > 0)
+ pool->frame_bufs[index].buf.vf_ref--;
+ }
+ if (hw->wait_buf)
+ WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG,
+ 0x1);
+ hw->last_put_idx = index;
+ hw->new_frame_displayed++;
+ unlock_buffer_pool(hw->pbi->common.buffer_pool, flags);
+
+ }
+
+}
+
+static int vav1_event_cb(int type, void *data, void *op_arg)
+{
+ unsigned long flags;
+ struct AV1HW_s *hw = (struct AV1HW_s *)op_arg;
+ struct AV1_Common_s *cm = &hw->pbi->common;
+ struct BufferPool_s *pool = cm->buffer_pool;
+
+ if (type & VFRAME_EVENT_RECEIVER_RESET) {
+#if 0
+ unsigned long flags;
+
+ amhevc_stop();
+#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
+ vf_light_unreg_provider(&vav1_vf_prov);
+#endif
+ spin_lock_irqsave(&hw->lock, flags);
+ vav1_local_init();
+ vav1_prot_init();
+ spin_unlock_irqrestore(&hw->lock, flags);
+#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
+ vf_reg_provider(&vav1_vf_prov);
+#endif
+ amhevc_start();
+#endif
+ } else if (type & VFRAME_EVENT_RECEIVER_GET_AUX_DATA) {
+ struct provider_aux_req_s *req =
+ (struct provider_aux_req_s *)data;
+ unsigned char index;
+
+ lock_buffer_pool(hw->pbi->common.buffer_pool, flags);
+ index = req->vf->index & 0xff;
+ req->aux_buf = NULL;
+ req->aux_size = 0;
+ if (req->bot_flag)
+ index = (req->vf->index >> 8) & 0xff;
+ if (index != 0xff
+ && index < hw->used_buf_num) {
+ struct PIC_BUFFER_CONFIG_s *pic_config =
+ &pool->frame_bufs[index].buf;
+ req->aux_buf = pic_config->aux_data_buf;
+ req->aux_size = pic_config->aux_data_size;
+#if 0
+//def CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
+ if (hevc->bypass_dvenl && !dolby_meta_with_el)
+ req->dv_enhance_exist = false;
+ else
+ req->dv_enhance_exist =
+ pic_config->dv_enhance_exist;
+ av1_print(hw, AOM_DEBUG_VFRAME,
+ "query dv_enhance_exist for pic (vf 0x%p, poc %d index %d) flag => %d, aux sizd 0x%x\n",
+ req->vf,
+ pic_config->POC, index,
+ req->dv_enhance_exist, req->aux_size);
+#else
+ req->dv_enhance_exist = 0;
+#endif
+ }
+ unlock_buffer_pool(hw->pbi->common.buffer_pool, flags);
+
+ if (debug & AOM_DEBUG_AUX_DATA)
+ av1_print(hw, 0,
+ "%s(type 0x%x vf index 0x%x)=>size 0x%x\n",
+ __func__, type, index, req->aux_size);
+#if 0
+//def CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
+ } else if (type & VFRAME_EVENT_RECEIVER_DOLBY_BYPASS_EL) {
+ if ((force_bypass_dvenl & 0x80000000) == 0) {
+ av1_print(hw, 0,
+ "%s: VFRAME_EVENT_RECEIVER_DOLBY_BYPASS_EL\n",
+ __func__);
+ hw->bypass_dvenl_enable = 1;
+ }
+
+#endif
+ }
+#if 0
+ else if (type & VFRAME_EVENT_RECEIVER_GET_FILM_GRAIN_TABLE) {
+ struct provider_aux_req_s *req =
+ (struct provider_aux_req_s *)data;
+ unsigned char index = (req->vf->index >> 8) & 0xff;
+ lock_buffer_pool(hw->pbi->common.buffer_pool, flags);
+ req->aux_buf = NULL;
+ req->aux_size = 0;
+ if (index != 0xff
+ && index < hw->used_buf_num) {
+ if (pool->frame_bufs[index].film_grain_reg_valid) {
+ req->aux_buf = (char*)(&(pool->frame_bufs[index].film_grain_reg[0]));
+ req->aux_size = FILM_GRAIN_REG_SIZE * 4;
+ }
+ }
+ unlock_buffer_pool(hw->pbi->common.buffer_pool, flags);
+ }
+#endif
+ return 0;
+}
+
+void av1_inc_vf_ref(struct AV1HW_s *hw, int index)
+{
+ struct AV1_Common_s *cm = &hw->pbi->common;
+
+ if ((debug & VP9_DEBUG_IGNORE_VF_REF) == 0) {
+ cm->buffer_pool->frame_bufs[index].buf.vf_ref++;
+
+ av1_print(hw, VP9_DEBUG_BUFMGR_MORE, "%s index = %d new vf_ref = %d\r\n",
+ __func__, index,
+ cm->buffer_pool->frame_bufs[index].buf.vf_ref);
+ }
+}
+
+static int frame_duration_adapt(struct AV1HW_s *hw, struct vframe_s *vf, u32 valid)
+{
+ u32 old_duration, pts_duration = 0;
+ u32 pts = vf->pts;
+
+ if (hw->get_frame_dur == true)
+ return true;
+
+ hw->frame_cnt_window++;
+ if (!(hw->av1_first_pts_ready == 1)) {
+ if (valid) {
+ hw->pts1 = pts;
+ hw->frame_cnt_window = 0;
+ hw->duration_from_pts_done = 0;
+ hw->av1_first_pts_ready = 1;
+ } else {
+ return false;
+ }
+ } else {
+ if (pts < hw->pts1) {
+ if (hw->frame_cnt_window > FRAME_CNT_WINDOW_SIZE) {
+ hw->pts1 = pts;
+ hw->frame_cnt_window = 0;
+ }
+ }
+
+ if (valid && (hw->frame_cnt_window > FRAME_CNT_WINDOW_SIZE) &&
+ (pts > hw->pts1) && (hw->duration_from_pts_done == 0)) {
+ old_duration = hw->frame_dur;
+ hw->pts2 = pts;
+ pts_duration = (((hw->pts2 - hw->pts1) * 16) /
+ (hw->frame_cnt_window * 15));
+
+ if (close_to(pts_duration, old_duration, 2000)) {
+ hw->frame_dur = pts_duration;
+ if ((debug & VP9_DEBUG_OUT_PTS) != 0)
+ pr_info("use calc duration %d\n", pts_duration);
+ }
+
+ if (hw->duration_from_pts_done == 0) {
+ if (close_to(pts_duration, old_duration, RATE_CORRECTION_THRESHOLD)) {
+ hw->duration_from_pts_done = 1;
+ } else {
+ if (!close_to(pts_duration,
+ old_duration, 1000) &&
+ !close_to(pts_duration,
+ hw->frame_dur, 1000) &&
+ close_to(pts_duration,
+ hw->last_duration, 200)) {
+ /* frame_dur must
+ * wrong,recover it.
+ */
+ hw->frame_dur = pts_duration;
+ }
+ hw->pts1 = hw->pts2;
+ hw->frame_cnt_window = 0;
+ hw->duration_from_pts_done = 0;
+ }
+ }
+ hw->last_duration = pts_duration;
+ }
+ }
+ return true;
+}
+
+static void update_vf_memhandle(struct AV1HW_s *hw,
+ struct vframe_s *vf, struct PIC_BUFFER_CONFIG_s *pic)
+{
+ if (pic->index < 0) {
+ vf->mem_handle = NULL;
+ vf->mem_head_handle = NULL;
+ } else if (vf->type & VIDTYPE_SCATTER) {
+#ifdef AOM_AV1_MMU_DW
+ if (pic->double_write_mode & 0x20 &&
+ (debug & AOM_DEBUG_DW_DISP_MAIN) == 0) {
+ vf->mem_handle =
+ decoder_mmu_box_get_mem_handle(
+ hw->mmu_box_dw, pic->index);
+ vf->mem_head_handle =
+ decoder_bmmu_box_get_mem_handle(
+ hw->bmmu_box,
+ DW_HEADER_BUFFER_IDX(pic->BUF_index));
+ } else
+#endif
+ {
+ vf->mem_handle =
+ decoder_mmu_box_get_mem_handle(
+ hw->mmu_box, pic->index);
+ vf->mem_head_handle =
+ decoder_bmmu_box_get_mem_handle(
+ hw->bmmu_box,
+ HEADER_BUFFER_IDX(pic->BUF_index));
+ }
+#ifdef USE_SPEC_BUF_FOR_MMU_HEAD
+ vf->mem_head_handle = NULL;
+#endif
+ } else {
+ vf->mem_handle =
+ decoder_bmmu_box_get_mem_handle(
+ hw->bmmu_box, VF_BUFFER_IDX(pic->BUF_index));
+ vf->mem_head_handle = NULL;
+ /*vf->mem_head_handle =
+ *decoder_bmmu_box_get_mem_handle(
+ *hevc->bmmu_box, VF_BUFFER_IDX(BUF_index));
+ */
+ }
+}
+
+static int prepare_display_buf(struct AV1HW_s *hw,
+ struct PIC_BUFFER_CONFIG_s *pic_config)
+{
+ struct vframe_s *vf = NULL;
+ int stream_offset = pic_config->stream_offset;
+ unsigned short slice_type = pic_config->slice_type;
+ u32 pts_valid = 0, pts_us64_valid = 0;
+ u32 pts_save;
+ u64 pts_us64_save;
+ u32 frame_size;
+
+ av1_print(hw, AOM_DEBUG_VFRAME, "%s index = %d\r\n", __func__, pic_config->index);
+ if (kfifo_get(&hw->newframe_q, &vf) == 0) {
+ av1_print(hw, 0, "fatal error, no available buffer slot.");
+ return -1;
+ }
+
+ if (pic_config->double_write_mode &&
+ (pic_config->double_write_mode & 0x20) == 0)
+ set_canvas(hw, pic_config);
+
+ display_frame_count[hw->index]++;
+ if (vf) {
+ if (hw->is_used_v4l) {
+ vf->v4l_mem_handle
+ = hw->m_BUF[pic_config->BUF_index].v4l_ref_buf_addr;
+ av1_print(hw, PRINT_FLAG_V4L_DETAIL,
+ "[%d] %s(), v4l mem handle: 0x%lx\n",
+ ((struct aml_vcodec_ctx *)(hw->v4l2_ctx))->id,
+ __func__, vf->v4l_mem_handle);
+ }
+
+#ifdef MULTI_INSTANCE_SUPPORT
+ if (vdec_frame_based(hw_to_vdec(hw))) {
+ vf->pts = pic_config->pts;
+ vf->pts_us64 = pic_config->pts64;
+ if (vf->pts != 0 || vf->pts_us64 != 0) {
+ pts_valid = 1;
+ pts_us64_valid = 1;
+ } else {
+ pts_valid = 0;
+ pts_us64_valid = 0;
+ }
+ } else
+#endif
+ /* if (pts_lookup_offset(PTS_TYPE_VIDEO,
+ * stream_offset, &vf->pts, 0) != 0) {
+ */
+ if (pts_lookup_offset_us64
+ (PTS_TYPE_VIDEO, stream_offset, &vf->pts,
+ &frame_size, 0,
+ &vf->pts_us64) != 0) {
+#ifdef DEBUG_PTS
+ hw->pts_missed++;
+#endif
+ vf->pts = 0;
+ vf->pts_us64 = 0;
+ pts_valid = 0;
+ pts_us64_valid = 0;
+ } else {
+#ifdef DEBUG_PTS
+ hw->pts_hit++;
+#endif
+ pts_valid = 1;
+ pts_us64_valid = 1;
+ }
+
+ fill_frame_info(hw, pic_config, frame_size, vf->pts);
+
+ pts_save = vf->pts;
+ pts_us64_save = vf->pts_us64;
+ if (hw->pts_unstable) {
+ frame_duration_adapt(hw, vf, pts_valid);
+ if (hw->duration_from_pts_done) {
+ hw->pts_mode = PTS_NONE_REF_USE_DURATION;
+ } else {
+ if (pts_valid || pts_us64_valid)
+ hw->pts_mode = PTS_NORMAL;
+ }
+ }
+
+ if ((hw->pts_mode == PTS_NORMAL) && (vf->pts != 0)
+ && hw->get_frame_dur) {
+ int pts_diff = (int)vf->pts - hw->last_lookup_pts;
+
+ if (pts_diff < 0) {
+ hw->pts_mode_switching_count++;
+ hw->pts_mode_recovery_count = 0;
+
+ if (hw->pts_mode_switching_count >=
+ PTS_MODE_SWITCHING_THRESHOLD) {
+ hw->pts_mode =
+ PTS_NONE_REF_USE_DURATION;
+ pr_info
+ ("HEVC: switch to n_d mode.\n");
+ }
+
+ } else {
+ int p = PTS_MODE_SWITCHING_RECOVERY_THREASHOLD;
+
+ hw->pts_mode_recovery_count++;
+ if (hw->pts_mode_recovery_count > p) {
+ hw->pts_mode_switching_count = 0;
+ hw->pts_mode_recovery_count = 0;
+ }
+ }
+ }
+
+ if (vf->pts != 0)
+ hw->last_lookup_pts = vf->pts;
+
+ if ((hw->pts_mode == PTS_NONE_REF_USE_DURATION)
+ && (slice_type != KEY_FRAME))
+ vf->pts = hw->last_pts + DUR2PTS(hw->frame_dur);
+ hw->last_pts = vf->pts;
+
+ if (vf->pts_us64 != 0)
+ hw->last_lookup_pts_us64 = vf->pts_us64;
+
+ if ((hw->pts_mode == PTS_NONE_REF_USE_DURATION)
+ && (slice_type != KEY_FRAME)) {
+ vf->pts_us64 =
+ hw->last_pts_us64 +
+ (DUR2PTS(hw->frame_dur) * 100 / 9);
+ }
+ hw->last_pts_us64 = vf->pts_us64;
+ if ((debug & VP9_DEBUG_OUT_PTS) != 0) {
+ pr_info
+ ("AV1 dec out pts: pts_mode=%d,dur=%d,pts(%d,%lld)(%d,%lld)\n",
+ hw->pts_mode, hw->frame_dur, vf->pts,
+ vf->pts_us64, pts_save, pts_us64_save);
+ }
+
+ if (hw->pts_mode == PTS_NONE_REF_USE_DURATION) {
+ vf->disp_pts = vf->pts;
+ vf->disp_pts_us64 = vf->pts_us64;
+ vf->pts = pts_save;
+ vf->pts_us64 = pts_us64_save;
+ } else {
+ vf->disp_pts = 0;
+ vf->disp_pts_us64 = 0;
+ }
+
+ vf->index = 0xff00 | pic_config->index;
+
+ if (pic_config->double_write_mode & 0x10) {
+ /* double write only */
+ vf->compBodyAddr = 0;
+ vf->compHeadAddr = 0;
+ } else {
+ if (hw->mmu_enable) {
+ struct AV1_Common_s *cm = &hw->pbi->common;
+ vf->compBodyAddr = 0;
+ vf->compHeadAddr = pic_config->header_adr;
+ vf->fgs_table_adr = pic_config->fgs_table_adr;
+ vf->fgs_valid = cm->buffer_pool->
+ frame_bufs[pic_config->index].film_grain_reg_valid;
+#ifdef AOM_AV1_MMU_DW
+ if (pic_config->double_write_mode & 0x20) {
+ u32 mode = pic_config->double_write_mode & 0xf;
+ vf->dwBodyAddr = 0;
+ vf->dwHeadAddr = pic_config->header_dw_adr;
+ if ((mode == 1 || mode == 2 || mode == 4)
+ && (debug & AOM_DEBUG_DW_DISP_MAIN) == 0) {
+ vf->compHeadAddr = pic_config->header_dw_adr;
+ av1_print(hw, AOM_DEBUG_VFRAME,
+ "Use dw mmu for display\n");
+ }
+ }
+#endif
+ } else {
+ /*vf->compBodyAddr = pic_config->mc_y_adr;
+ *vf->compHeadAddr = pic_config->mc_y_adr +
+ *pic_config->comp_body_size; */
+ /*head adr*/
+ }
+ vf->canvas0Addr = vf->canvas1Addr = 0;
+ }
+ if (pic_config->double_write_mode &&
+ (pic_config->double_write_mode & 0x20) == 0) {
+ vf->type = VIDTYPE_PROGRESSIVE |
+ VIDTYPE_VIU_FIELD;
+ vf->type |= VIDTYPE_VIU_NV21;
+ if ((pic_config->double_write_mode == 3 ||
+ pic_config->double_write_mode == 5) &&
+ (!IS_8K_SIZE(pic_config->y_crop_width,
+ pic_config->y_crop_height))) {
+ vf->type |= VIDTYPE_COMPRESS;
+ if (hw->mmu_enable)
+ vf->type |= VIDTYPE_SCATTER;
+ }
+#ifdef MULTI_INSTANCE_SUPPORT
+ if (hw->m_ins_flag) {
+ vf->canvas0Addr = vf->canvas1Addr = -1;
+ vf->plane_num = 2;
+ vf->canvas0_config[0] =
+ pic_config->canvas_config[0];
+ vf->canvas0_config[1] =
+ pic_config->canvas_config[1];
+ vf->canvas1_config[0] =
+ pic_config->canvas_config[0];
+ vf->canvas1_config[1] =
+ pic_config->canvas_config[1];
+
+ } else
+#endif
+ vf->canvas0Addr = vf->canvas1Addr =
+ spec2canvas(pic_config);
+ } else {
+ vf->canvas0Addr = vf->canvas1Addr = 0;
+ vf->type = VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
+ if (hw->mmu_enable)
+ vf->type |= VIDTYPE_SCATTER;
+ }
+
+ switch (pic_config->bit_depth) {
+ case AOM_BITS_8:
+ vf->bitdepth = BITDEPTH_Y8 |
+ BITDEPTH_U8 | BITDEPTH_V8;
+ break;
+ case AOM_BITS_10:
+ case AOM_BITS_12:
+ vf->bitdepth = BITDEPTH_Y10 |
+ BITDEPTH_U10 | BITDEPTH_V10;
+ break;
+ default:
+ vf->bitdepth = BITDEPTH_Y10 |
+ BITDEPTH_U10 | BITDEPTH_V10;
+ break;
+ }
+ if ((vf->type & VIDTYPE_COMPRESS) == 0)
+ vf->bitdepth =
+ BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
+ if (pic_config->bit_depth == AOM_BITS_8)
+ vf->bitdepth |= BITDEPTH_SAVING_MODE;
+
+ /* if ((vf->width!=pic_config->width)|
+ * (vf->height!=pic_config->height))
+ */
+ /* pr_info("aaa: %d/%d, %d/%d\n",
+ vf->width,vf->height, pic_config->width,
+ pic_config->height); */
+ vf->width = pic_config->y_crop_width /
+ get_double_write_ratio(hw,
+ pic_config->double_write_mode);
+ vf->height = pic_config->y_crop_height /
+ get_double_write_ratio(hw,
+ pic_config->double_write_mode);
+ if (force_w_h != 0) {
+ vf->width = (force_w_h >> 16) & 0xffff;
+ vf->height = force_w_h & 0xffff;
+ }
+ if ((pic_config->double_write_mode & 0x20) &&
+ ((pic_config->double_write_mode & 0xf) == 2 ||
+ (pic_config->double_write_mode & 0xf) == 4)) {
+ vf->compWidth = pic_config->y_crop_width /
+ get_double_write_ratio(hw,
+ pic_config->double_write_mode);
+ vf->compHeight = pic_config->y_crop_height /
+ get_double_write_ratio(hw,
+ pic_config->double_write_mode);
+ } else {
+ vf->compWidth = pic_config->y_crop_width;
+ vf->compHeight = pic_config->y_crop_height;
+ }
+ set_frame_info(hw, vf);
+ if (force_fps & 0x100) {
+ u32 rate = force_fps & 0xff;
+
+ if (rate)
+ vf->duration = 96000/rate;
+ else
+ vf->duration = 0;
+ }
+ update_vf_memhandle(hw, vf, pic_config);
+ if (!(pic_config->y_crop_width == 196
+ && pic_config->y_crop_height == 196
+ && (debug & VP9_DEBUG_NO_TRIGGER_FRAME) == 0
+ && (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX))) {
+ av1_inc_vf_ref(hw, pic_config->index);
+ decoder_do_frame_check(hw_to_vdec(hw), vf);
+ kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
+ ATRACE_COUNTER(MODULE_NAME, vf->pts);
+ hw->vf_pre_count++;
+#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
+ /*count info*/
+ gvs->frame_dur = hw->frame_dur;
+ vdec_count_info(gvs, 0, stream_offset);
+#endif
+ hw_to_vdec(hw)->vdec_fps_detec(hw_to_vdec(hw)->id);
+ vf_notify_receiver(hw->provider_name,
+ VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
+ } else {
+ hw->stat |= VP9_TRIGGER_FRAME_DONE;
+ hevc_source_changed(VFORMAT_AV1, 196, 196, 30);
+ pr_debug("[%s %d] drop trigger frame width %d height %d state 0x%x\n",
+ __func__, __LINE__, vf->width,
+ vf->height, hw->stat);
+ }
+ }
+
+ return 0;
+}
+
+void av1_raw_write_image(AV1Decoder *pbi, PIC_BUFFER_CONFIG *sd)
+{
+ prepare_display_buf((struct AV1HW_s *)(pbi->private_data), sd);
+}
+
+static int notify_v4l_eos(struct vdec_s *vdec)
+{
+ struct AV1HW_s *hw = (struct AV1HW_s *)vdec->private;
+ struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
+ struct vframe_s *vf = NULL;
+ struct vdec_fb *fb = NULL;
+
+ if (hw->is_used_v4l && hw->eos) {
+ if (kfifo_get(&hw->newframe_q, &vf) == 0 || vf == NULL) {
+ av1_print(hw, 0,
+ "%s fatal error, no available buffer slot.\n",
+ __func__);
+ return -1;
+ }
+
+ if (v4l_get_fb(hw->v4l2_ctx, &fb)) {
+ pr_err("[%d] get fb fail.\n", ctx->id);
+ return -1;
+ }
+
+ vf->timestamp = ULONG_MAX;
+ vf->v4l_mem_handle = (unsigned long)fb;
+ vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L;
+
+ kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
+ vf_notify_receiver(vdec->vf_provider_name,
+ VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
+
+ av1_print(hw, AOM_DEBUG_HW_MORE, "[%d] AV1 EOS notify.\n", ctx->id);
+ }
+
+ return 0;
+}
+
+static void get_rpm_param(union param_u *params)
+{
+ int i;
+ unsigned int data32;
+
+ if (debug & VP9_DEBUG_BUFMGR)
+ pr_info("enter %s\r\n", __func__);
+ for (i = 0; i < 128; i++) {
+ do {
+ data32 = READ_VREG(RPM_CMD_REG);
+ /*pr_info("%x\n", data32);*/
+ } while ((data32 & 0x10000) == 0);
+ params->l.data[i] = data32&0xffff;
+ /*pr_info("%x\n", data32);*/
+ WRITE_VREG(RPM_CMD_REG, 0);
+ }
+ if (debug & VP9_DEBUG_BUFMGR)
+ pr_info("leave %s\r\n", __func__);
+}
+
+static void av1_recycle_mmu_buf_tail(struct AV1HW_s *hw)
+{
+#ifdef CHANGE_REMOVED
+ struct AV1_Common_s *const cm = &hw->pbi->common;
+ if (hw->double_write_mode & 0x10)
+ return;
+ if (cm->cur_fb_idx_mmu != INVALID_IDX) {
+ if (hw->used_4k_num == -1) {
+ hw->used_4k_num =
+ (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
+ if (hw->m_ins_flag)
+ hevc_mmu_dma_check(hw_to_vdec(hw));
+ }
+ decoder_mmu_box_free_idx_tail(hw->mmu_box,
+ cm->cur_fb_idx_mmu, hw->used_4k_num);
+ cm->cur_fb_idx_mmu = INVALID_IDX;
+ hw->used_4k_num = -1;
+ }
+#endif
+}
+
+#ifdef MULTI_INSTANCE_SUPPORT
+static void av1_recycle_mmu_buf(struct AV1HW_s *hw)
+{
+#ifdef CHANGE_REMOVED
+ struct AV1_Common_s *const cm = &hw->pbi->common;
+ if (hw->double_write_mode & 0x10)
+ return;
+ if (cm->cur_fb_idx_mmu != INVALID_IDX) {
+ decoder_mmu_box_free_idx(hw->mmu_box,
+ cm->cur_fb_idx_mmu);
+
+ cm->cur_fb_idx_mmu = INVALID_IDX;
+ hw->used_4k_num = -1;
+ }
+#endif
+}
+#endif
+
+
+static void dec_again_process(struct AV1HW_s *hw)
+{
+ amhevc_stop();
+ hw->dec_result = DEC_RESULT_AGAIN;
+ if (hw->process_state ==
+ PROC_STATE_DECODESLICE) {
+ hw->process_state =
+ PROC_STATE_SENDAGAIN;
+ if (hw->mmu_enable)
+ av1_recycle_mmu_buf(hw);
+ }
+ reset_process_time(hw);
+ vdec_schedule_work(&hw->work);
+}
+
+static void read_film_grain_reg(struct AV1HW_s *hw)
+{
+ AV1_COMMON *cm = &hw->pbi->common;
+ int i;
+ if (cm->cur_frame == NULL) {
+ av1_print(hw, AOM_DEBUG_HW_MORE, "%s, cur_frame not exist!!!\n", __func__);
+ return;
+ } else
+ av1_print(hw, AOM_DEBUG_HW_MORE, "%s\n", __func__);
+ WRITE_VREG(HEVC_FGS_IDX, 0);
+ for (i = 0; i < FILM_GRAIN_REG_SIZE; i++) {
+ cm->cur_frame->film_grain_reg[i] = READ_VREG(HEVC_FGS_DATA);
+ }
+ cm->cur_frame->film_grain_reg_valid = 1;
+}
+
+static void config_film_grain_reg(struct AV1HW_s *hw, int film_grain_params_ref_idx)
+{
+
+ AV1_COMMON *cm = &hw->pbi->common;
+ int i;
+ unsigned char found = 0;
+ RefCntBuffer *buf;
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ " ## %s frome reference idx %d\n",
+ __func__, film_grain_params_ref_idx);
+ for (i = 0; i < INTER_REFS_PER_FRAME; ++i) {
+ if (film_grain_params_ref_idx == cm->remapped_ref_idx[i]) {
+ found = 1;
+ break;
+ }
+ }
+ if (!found) {
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "%s Error, Invalid film grain reference idx %d\n",
+ __func__, film_grain_params_ref_idx);
+ return;
+ }
+ buf = cm->ref_frame_map[film_grain_params_ref_idx];
+
+ if (buf->film_grain_reg_valid == 0) {
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "%s Error, film grain register data invalid for reference idx %d\n",
+ __func__, film_grain_params_ref_idx);
+ return;
+ }
+
+ if (cm->cur_frame == NULL) {
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "%s, cur_frame not exist!!!\n", __func__);
+ }
+ WRITE_VREG(HEVC_FGS_IDX, 0);
+ for (i = 0; i < FILM_GRAIN_REG_SIZE; i++) {
+ WRITE_VREG(HEVC_FGS_DATA, buf->film_grain_reg[i]);
+ if (cm->cur_frame)
+ cm->cur_frame->film_grain_reg[i] = buf->film_grain_reg[i];
+ }
+ if (cm->cur_frame)
+ cm->cur_frame->film_grain_reg_valid = 1;
+ WRITE_VREG(HEVC_FGS_CTRL, READ_VREG(HEVC_FGS_CTRL) | 1); // set fil_grain_start
+}
+
+
+void config_next_ref_info_hw(struct AV1HW_s *hw)
+{
+ int j;
+ AV1_COMMON *const cm = &hw->pbi->common;
+ av1_set_next_ref_frame_map(hw->pbi);
+ WRITE_VREG(HEVC_PARSER_MEM_WR_ADDR, 0x1000);
+ for (j = 0; j < 12; j++) {
+ unsigned int info =
+ av1_get_next_used_ref_info(cm, j);
+ WRITE_VREG(HEVC_PARSER_MEM_RW_DATA, info);
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "config next ref info %d 0x%x\n", j, info);
+ }
+}
+
+
+
+#ifdef PRINT_HEVC_DATA_PATH_MONITOR
+void datapath_monitor(struct AV1HW_s *hw)
+{
+ uint32_t total_clk_count;
+ uint32_t path_transfer_count;
+ uint32_t path_wait_count;
+ float path_wait_ratio;
+ if (pbi->decode_idx > 1) {
+ WRITE_VREG(HEVC_PATH_MONITOR_CTRL, 0); // Disabble monitor and set rd_idx to 0
+ total_clk_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
+
+ WRITE_VREG(HEVC_PATH_MONITOR_CTRL, (1<<4)); // Disabble monitor and set rd_idx to 0
+
+// parser --> iqit
+ path_transfer_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
+ path_wait_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
+ if (path_transfer_count == 0) path_wait_ratio = 0.0;
+ else path_wait_ratio = (float)path_wait_count/(float)path_transfer_count;
+ printk("[P%d HEVC PATH] Parser/IQIT/IPP/DBLK/OW/DDR/CMD WAITING \% : %.2f",
+ pbi->decode_idx - 2, path_wait_ratio);
+
+// iqit --> ipp
+ path_transfer_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
+ path_wait_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
+ if (path_transfer_count == 0) path_wait_ratio = 0.0;
+ else path_wait_ratio = (float)path_wait_count/(float)path_transfer_count;
+ printk(" %.2f", path_wait_ratio);
+
+// dblk <-- ipp
+ path_transfer_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
+ path_wait_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
+ if (path_transfer_count == 0) path_wait_ratio = 0.0;
+ else path_wait_ratio = (float)path_wait_count/(float)path_transfer_count;
+ printk(" %.2f", path_wait_ratio);
+
+// dblk --> ow
+ path_transfer_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
+ path_wait_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
+ if (path_transfer_count == 0) path_wait_ratio = 0.0;
+ else path_wait_ratio = (float)path_wait_count/(float)path_transfer_count;
+ printk(" %.2f", path_wait_ratio);
+
+// <--> DDR
+ path_transfer_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
+ path_wait_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
+ if (path_transfer_count == 0) path_wait_ratio = 0.0;
+ else path_wait_ratio = (float)path_wait_count/(float)path_transfer_count;
+ printk(" %.2f", path_wait_ratio);
+
+// CMD
+ path_transfer_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
+ path_wait_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
+ if (path_transfer_count == 0) path_wait_ratio = 0.0;
+ else path_wait_ratio = (float)path_wait_count/(float)path_transfer_count;
+ printk(" %.2f\n", path_wait_ratio);
+ }
+}
+
+#endif
+
+int av1_continue_decoding(struct AV1HW_s *hw, int obu_type)
+{
+ int ret;
+#if 1
+ //def CHANGE_DONE
+ AV1Decoder *pbi = hw->pbi;
+ AV1_COMMON *const cm = &pbi->common;
+ int i;
+
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "%s: pbi %p cm %p cur_frame %p %d\n",
+ __func__, pbi, cm, cm->cur_frame,
+ pbi->bufmgr_proc_count);
+
+ //pre_decode_idx = pbi->decode_idx;
+ if (pbi->bufmgr_proc_count == 0 ||
+ hw->one_compressed_data_done) {
+ hw->new_compressed_data = 1;
+ hw->one_compressed_data_done = 0;
+ } else {
+ hw->new_compressed_data = 0;
+ }
+ ret = av1_bufmgr_process(pbi, &hw->aom_param,
+ hw->new_compressed_data, obu_type);
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "%s: pbi %p cm %p cur_frame %p\n",
+ __func__, pbi, cm, cm->cur_frame);
+
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "1+++++++++++++++++++++++++++++++++++%d %p\n",
+ ret, cm->cur_frame);
+ if (hw->new_compressed_data)
+ WRITE_VREG(PIC_END_LCU_COUNT, 0);
+
+ if (ret > 0) {
+ /* the case when cm->show_existing_frame is 1 */
+ /*case 3016*/
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "Decoding done (show_existing_frame = %d)\n",
+ cm->show_existing_frame);
+
+ config_next_ref_info_hw(hw);
+
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "aom_bufmgr_process=> %d,decode done, AOM_AV1_SEARCH_HEAD\r\n", ret);
+ WRITE_VREG(HEVC_DEC_STATUS_REG, AOM_AV1_SEARCH_HEAD);
+ pbi->decode_idx++;
+ pbi->bufmgr_proc_count++;
+ hw->frame_decoded = 1;
+ return 0;
+ }
+ else if (ret < 0) {
+ hw->frame_decoded = 1;
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "aom_bufmgr_process=> %d, bufmgr e.r.r.o.r., AOM_AV1_SEARCH_HEAD\r\n", ret);
+ WRITE_VREG(HEVC_DEC_STATUS_REG, AOM_AV1_SEARCH_HEAD);
+ return 0;
+ }
+ else if (ret == 0) {
+ PIC_BUFFER_CONFIG* cur_pic_config = &cm->cur_frame->buf;
+ PIC_BUFFER_CONFIG* prev_pic_config = &cm->prev_frame->buf;
+ //struct segmentation_lf *seg_4lf = &hw->seg_4lf_store;
+
+ hw->frame_decoded = 0;
+ pbi->bufmgr_proc_count++;
+ if (hw->new_compressed_data == 0) {
+ WRITE_VREG(HEVC_DEC_STATUS_REG, AOM_AV1_DECODE_SLICE);
+ return 0;
+ }
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ " [PICTURE %d] cm->cur_frame->mi_size : (%d X %d) y_crop_size :(%d X %d)\n",
+ hw->frame_count,
+ cm->cur_frame->mi_cols,
+ cm->cur_frame->mi_rows,
+ cur_pic_config->y_crop_width,
+ cur_pic_config->y_crop_height);
+ if (cm->prev_frame > 0) {
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ " [SEGMENT] cm->prev_frame->segmentation_enabled : %d\n",
+ cm->prev_frame->segmentation_enabled);
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ " [SEGMENT] cm->prev_frame->mi_size : (%d X %d)\n",
+ cm->prev_frame->mi_cols, cm->prev_frame->mi_rows);
+ }
+ cm->cur_frame->prev_segmentation_enabled = (cm->prev_frame > 0) ?
+ (cm->prev_frame->segmentation_enabled & (cm->prev_frame->segmentation_update_map
+ | cm->prev_frame->prev_segmentation_enabled) &
+ (cm->cur_frame->mi_rows == cm->prev_frame->mi_rows) &
+ (cm->cur_frame->mi_cols == cm->prev_frame->mi_cols)) : 0;
+ WRITE_VREG(AV1_SKIP_MODE_INFO,
+ (cm->cur_frame->prev_segmentation_enabled << 31) |
+ (((cm->prev_frame > 0) ? cm->prev_frame->intra_only : 0) << 30) |
+ (((cm->prev_frame > 0) ? prev_pic_config->index : 0x1f) << 24) |
+ (((cm->cur_frame > 0) ? cur_pic_config->index : 0x1f) << 16) |
+ (cm->current_frame.skip_mode_info.ref_frame_idx_0 & 0xf) |
+ ((cm->current_frame.skip_mode_info.ref_frame_idx_1 & 0xf) << 4) |
+ (cm->current_frame.skip_mode_info.skip_mode_allowed << 8));
+ cur_pic_config->decode_idx = pbi->decode_idx;
+
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "Decode Frame Data %d frame_type %d (%d) bufmgr_proc_count %d\n",
+ pbi->decode_idx,
+ cm->cur_frame->frame_type,
+ cm->current_frame.frame_type,
+ pbi->bufmgr_proc_count);
+ pbi->decode_idx++;
+ hw->frame_count++;
+#ifdef DUAL_DECODE
+#else
+ config_pic_size(hw, hw->aom_param.p.bit_depth);
+#endif
+ if (hw->mmu_enable && ((hw->double_write_mode & 0x10) == 0)) {
+ ret = av1_alloc_mmu(hw,
+ cm->cur_frame->buf.index,
+ cur_pic_config->y_crop_width,
+ cur_pic_config->y_crop_height,
+ hw->aom_param.p.bit_depth,
+ hw->frame_mmu_map_addr);
+ if (ret >= 0)
+ cm->cur_fb_idx_mmu = cm->cur_frame->buf.index;
+ else
+ pr_err("can't alloc need mmu1,idx %d ret =%d\n",
+ cm->cur_frame->buf.index, ret);
+#ifdef AOM_AV1_MMU_DW
+ if (hw->dw_mmu_enable) {
+ ret = av1_alloc_mmu_dw(hw,
+ cm->cur_frame->buf.index,
+ cur_pic_config->y_crop_width,
+ cur_pic_config->y_crop_height,
+ hw->aom_param.p.bit_depth,
+ hw->dw_frame_mmu_map_addr);
+ if (ret >= 0)
+ cm->cur_fb_idx_mmu_dw = cm->cur_frame->buf.index;
+ else
+ pr_err("can't alloc need dw mmu1,idx %d ret =%d\n",
+ cm->cur_frame->buf.index, ret);
+ }
+#endif
+ } else {
+ ret = 0;
+ }
+ if (av1_frame_is_inter(&hw->pbi->common)) {
+ //if ((pbi->common.frame_type != KEY_FRAME) && (!pbi->common.intra_only)) {
+#ifdef DUAL_DECODE
+#else
+ config_mc_buffer(hw, hw->aom_param.p.bit_depth, 1);
+#endif
+ config_mpred_hw(hw, 1);
+ }
+ else {
+ config_mc_buffer(hw, hw->aom_param.p.bit_depth, 0);
+ clear_mpred_hw(hw);
+ config_mpred_hw(hw, 0);
+ }
+#ifdef DUAL_DECODE
+#else
+#ifdef MCRCC_ENABLE
+ config_mcrcc_axi_hw(pbi);
+#endif
+ config_sao_hw(hw, &hw->aom_param);
+#endif
+
+ config_dblk_hw(hw);
+
+ av1_print(hw, AOM_DEBUG_HW_MORE, "HEVC_DEC_STATUS_REG <= AOM_AV1_DECODE_SLICE\n");
+ WRITE_VREG(HEVC_DEC_STATUS_REG, AOM_AV1_DECODE_SLICE);
+
+ // Save segment_feature while hardware decoding
+ if (hw->seg_4lf->enabled) {
+ for (i = 0; i < 8; i++) {
+ cm->cur_frame->segment_feature[i] = READ_VREG(AOM_AV1_SEGMENT_FEATURE);
+ }
+ } else {
+ for (i = 0; i < 8; i++) {
+ cm->cur_frame->segment_feature[i] = (0x80000000 | (i << 22));
+ }
+ }
+ WRITE_VREG(HEVC_PARSER_MEM_WR_ADDR, 0x1010 + (cur_pic_config->index));
+ if (hw->aom_param.p.segmentation_enabled & 1) // segmentation_enabled
+ WRITE_VREG(HEVC_PARSER_MEM_RW_DATA, READ_VREG(AV1_REF_SEG_INFO));
+ else
+ WRITE_VREG(HEVC_PARSER_MEM_RW_DATA, 0);
+ } else {
+ av1_print(hw, AOM_DEBUG_HW_MORE, "Sequence head, Search next start code\n");
+ cm->prev_fb_idx = INVALID_IDX;
+ //skip, search next start code
+ WRITE_VREG(HEVC_DEC_STATUS_REG, AOM_AV1_DECODE_SLICE);
+ }
+ return ret;
+
+#else
+
+ bit_depth_luma = av1_param.p.bit_depth;
+ bit_depth_chroma = av1_param.p.bit_depth;
+
+ if (hw->process_state != PROC_STATE_SENDAGAIN) {
+ ret = av1_bufmgr_process(hw, &av1_param);
+ if (!hw->m_ins_flag)
+ hw->result_done_count++;
+ } else {
+ union param_u *params = &av1_param;
+ if (hw->mmu_enable && ((hw->double_write_mode & 0x10) == 0)) {
+ ret = av1_alloc_mmu(hw,
+ cm->new_fb_idx,
+ params->p.width,
+ params->p.height,
+ params->p.bit_depth,
+ hw->frame_mmu_map_addr);
+ if (ret >= 0)
+ cm->cur_fb_idx_mmu = cm->new_fb_idx;
+ else
+ pr_err("can't alloc need mmu1,idx %d ret =%d\n",
+ cm->new_fb_idx, ret);
+ } else {
+ ret = 0;
+ }
+ WRITE_VREG(HEVC_PARSER_PICTURE_SIZE,
+ (params->p.height << 16) | params->p.width);
+ }
+ if (ret < 0) {
+ pr_info("av1_bufmgr_process=> %d, VP9_10B_DISCARD_NAL\r\n", ret);
+ WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DISCARD_NAL);
+ cm->show_frame = 0;
+ if (hw->mmu_enable)
+ av1_recycle_mmu_buf(hw);
+
+ if (hw->m_ins_flag) {
+ hw->dec_result = DEC_RESULT_DONE;
+ amhevc_stop();
+ vdec_schedule_work(&hw->work);
+ }
+ return ret;
+ } else if (ret == 0) {
+ struct PIC_BUFFER_CONFIG_s *cur_pic_config
+ = &cm->cur_frame->buf;
+ cur_pic_config->decode_idx = hw->frame_count;
+
+ if (hw->process_state != PROC_STATE_SENDAGAIN) {
+ if (!hw->m_ins_flag) {
+ hw->frame_count++;
+ decode_frame_count[hw->index]
+ = hw->frame_count;
+ }
+ if (hw->chunk) {
+ cur_pic_config->pts = hw->chunk->pts;
+ cur_pic_config->pts64 = hw->chunk->pts64;
+ }
+ }
+ /*pr_info("Decode Frame Data %d\n", hw->frame_count);*/
+ config_pic_size(hw, av1_param.p.bit_depth);
+
+ if ((hw->common.frame_type != KEY_FRAME)
+ && (!hw->common.intra_only)) {
+ config_mc_buffer(hw, av1_param.p.bit_depth);
+ config_mpred_hw(hw);
+ } else {
+ clear_mpred_hw(hw);
+ }
+#ifdef MCRCC_ENABLE
+ if (mcrcc_cache_alg_flag)
+ config_mcrcc_axi_hw_new(hw);
+ else
+ config_mcrcc_axi_hw(hw);
+#endif
+ config_sao_hw(hw, &av1_param);
+ /*pr_info("HEVC_DEC_STATUS_REG <= VP9_10B_DECODE_SLICE\n");*/
+ WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DECODE_SLICE);
+ } else {
+ pr_info("Skip search next start code\n");
+ cm->prev_fb_idx = INVALID_IDX;
+ /*skip, search next start code*/
+ WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DECODE_SLICE);
+ }
+ hw->process_state = PROC_STATE_DECODESLICE;
+ if (hw->mmu_enable && ((hw->double_write_mode & 0x10) == 0)) {
+ if (hw->last_put_idx < hw->used_buf_num) {
+ struct RefCntBuffer_s *frame_bufs =
+ cm->buffer_pool->frame_bufs;
+ int i = hw->last_put_idx;
+ /*free not used buffers.*/
+ if ((frame_bufs[i].ref_count == 0) &&
+ (frame_bufs[i].buf.vf_ref == 0) &&
+ (frame_bufs[i].buf.index != -1)) {
+ decoder_mmu_box_free_idx(hw->mmu_box, i);
+ }
+ hw->last_put_idx = -1;
+ }
+ }
+ return ret;
+#endif
+}
+
+static void fill_frame_info(struct AV1HW_s *hw,
+ struct PIC_BUFFER_CONFIG_s *frame,
+ unsigned int framesize,
+ unsigned int pts)
+{
+ struct vframe_qos_s *vframe_qos = &hw->vframe_qos;
+
+ if (frame->slice_type == KEY_FRAME)
+ vframe_qos->type = 1;
+ else if (frame->slice_type == INTER_FRAME)
+ vframe_qos->type = 2;
+/*
+#define SHOW_QOS_INFO
+*/
+ vframe_qos->size = framesize;
+ vframe_qos->pts = pts;
+#ifdef SHOW_QOS_INFO
+ av1_print(hw, 0, "slice:%d\n", frame->slice_type);
+#endif
+ vframe_qos->max_mv = frame->max_mv;
+ vframe_qos->avg_mv = frame->avg_mv;
+ vframe_qos->min_mv = frame->min_mv;
+#ifdef SHOW_QOS_INFO
+ av1_print(hw, 0, "mv: max:%d, avg:%d, min:%d\n",
+ vframe_qos->max_mv,
+ vframe_qos->avg_mv,
+ vframe_qos->min_mv);
+#endif
+ vframe_qos->max_qp = frame->max_qp;
+ vframe_qos->avg_qp = frame->avg_qp;
+ vframe_qos->min_qp = frame->min_qp;
+#ifdef SHOW_QOS_INFO
+ av1_print(hw, 0, "qp: max:%d, avg:%d, min:%d\n",
+ vframe_qos->max_qp,
+ vframe_qos->avg_qp,
+ vframe_qos->min_qp);
+#endif
+ vframe_qos->max_skip = frame->max_skip;
+ vframe_qos->avg_skip = frame->avg_skip;
+ vframe_qos->min_skip = frame->min_skip;
+#ifdef SHOW_QOS_INFO
+ av1_print(hw, 0, "skip: max:%d, avg:%d, min:%d\n",
+ vframe_qos->max_skip,
+ vframe_qos->avg_skip,
+ vframe_qos->min_skip);
+#endif
+ vframe_qos->num++;
+ /*
+ if (hw->frameinfo_enable)
+ vdec_fill_frame_info(vframe_qos, 1);
+ */
+}
+
+/* only when we decoded one field or one frame,
+we can call this function to get qos info*/
+static void get_picture_qos_info(struct AV1HW_s *hw)
+{
+ struct PIC_BUFFER_CONFIG_s *frame = &hw->cur_buf->buf;
+
+ if (!frame)
+ return;
+
+ if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
+ unsigned char a[3];
+ unsigned char i, j, t;
+ unsigned long data;
+
+ data = READ_VREG(HEVC_MV_INFO);
+ if (frame->slice_type == KEY_FRAME)
+ data = 0;
+ a[0] = data & 0xff;
+ a[1] = (data >> 8) & 0xff;
+ a[2] = (data >> 16) & 0xff;
+
+ for (i = 0; i < 3; i++) {
+ for (j = i+1; j < 3; j++) {
+ if (a[j] < a[i]) {
+ t = a[j];
+ a[j] = a[i];
+ a[i] = t;
+ } else if (a[j] == a[i]) {
+ a[i]++;
+ t = a[j];
+ a[j] = a[i];
+ a[i] = t;
+ }
+ }
+ }
+ frame->max_mv = a[2];
+ frame->avg_mv = a[1];
+ frame->min_mv = a[0];
+
+ av1_print(hw, VP9_DEBUG_QOS_INFO,
+ "mv data %x a[0]= %x a[1]= %x a[2]= %x\n",
+ data, a[0], a[1], a[2]);
+
+ data = READ_VREG(HEVC_QP_INFO);
+ a[0] = data & 0x1f;
+ a[1] = (data >> 8) & 0x3f;
+ a[2] = (data >> 16) & 0x7f;
+
+ for (i = 0; i < 3; i++) {
+ for (j = i+1; j < 3; j++) {
+ if (a[j] < a[i]) {
+ t = a[j];
+ a[j] = a[i];
+ a[i] = t;
+ } else if (a[j] == a[i]) {
+ a[i]++;
+ t = a[j];
+ a[j] = a[i];
+ a[i] = t;
+ }
+ }
+ }
+ frame->max_qp = a[2];
+ frame->avg_qp = a[1];
+ frame->min_qp = a[0];
+
+ av1_print(hw, VP9_DEBUG_QOS_INFO,
+ "qp data %x a[0]= %x a[1]= %x a[2]= %x\n",
+ data, a[0], a[1], a[2]);
+
+ data = READ_VREG(HEVC_SKIP_INFO);
+ a[0] = data & 0x1f;
+ a[1] = (data >> 8) & 0x3f;
+ a[2] = (data >> 16) & 0x7f;
+
+ for (i = 0; i < 3; i++) {
+ for (j = i+1; j < 3; j++) {
+ if (a[j] < a[i]) {
+ t = a[j];
+ a[j] = a[i];
+ a[i] = t;
+ } else if (a[j] == a[i]) {
+ a[i]++;
+ t = a[j];
+ a[j] = a[i];
+ a[i] = t;
+ }
+ }
+ }
+ frame->max_skip = a[2];
+ frame->avg_skip = a[1];
+ frame->min_skip = a[0];
+
+ av1_print(hw, VP9_DEBUG_QOS_INFO,
+ "skip data %x a[0]= %x a[1]= %x a[2]= %x\n",
+ data, a[0], a[1], a[2]);
+ } else {
+ uint32_t blk88_y_count;
+ uint32_t blk88_c_count;
+ uint32_t blk22_mv_count;
+ uint32_t rdata32;
+ int32_t mv_hi;
+ int32_t mv_lo;
+ uint32_t rdata32_l;
+ uint32_t mvx_L0_hi;
+ uint32_t mvy_L0_hi;
+ uint32_t mvx_L1_hi;
+ uint32_t mvy_L1_hi;
+ int64_t value;
+ uint64_t temp_value;
+ int pic_number = frame->decode_idx;
+
+ frame->max_mv = 0;
+ frame->avg_mv = 0;
+ frame->min_mv = 0;
+
+ frame->max_skip = 0;
+ frame->avg_skip = 0;
+ frame->min_skip = 0;
+
+ frame->max_qp = 0;
+ frame->avg_qp = 0;
+ frame->min_qp = 0;
+
+ av1_print(hw, VP9_DEBUG_QOS_INFO, "slice_type:%d, poc:%d\n",
+ frame->slice_type,
+ pic_number);
+
+ /* set rd_idx to 0 */
+ WRITE_VREG(HEVC_PIC_QUALITY_CTRL, 0);
+
+ blk88_y_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
+ if (blk88_y_count == 0) {
+
+ av1_print(hw, VP9_DEBUG_QOS_INFO,
+ "[Picture %d Quality] NO Data yet.\n",
+ pic_number);
+
+ /* reset all counts */
+ WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
+ return;
+ }
+ /* qp_y_sum */
+ rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
+
+ av1_print(hw, VP9_DEBUG_QOS_INFO,
+ "[Picture %d Quality] Y QP AVG : %d (%d/%d)\n",
+ pic_number, rdata32/blk88_y_count,
+ rdata32, blk88_y_count);
+
+ frame->avg_qp = rdata32/blk88_y_count;
+ /* intra_y_count */
+ rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
+
+ av1_print(hw, VP9_DEBUG_QOS_INFO,
+ "[Picture %d Quality] Y intra rate : %d%c (%d)\n",
+ pic_number, rdata32*100/blk88_y_count,
+ '%', rdata32);
+
+ /* skipped_y_count */
+ rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
+
+ av1_print(hw, VP9_DEBUG_QOS_INFO,
+ "[Picture %d Quality] Y skipped rate : %d%c (%d)\n",
+ pic_number, rdata32*100/blk88_y_count,
+ '%', rdata32);
+
+ frame->avg_skip = rdata32*100/blk88_y_count;
+ /* coeff_non_zero_y_count */
+ rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
+
+ av1_print(hw, VP9_DEBUG_QOS_INFO,
+ "[Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n",
+ pic_number, (100 - rdata32*100/(blk88_y_count*1)),
+ '%', rdata32);
+
+ /* blk66_c_count */
+ blk88_c_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
+ if (blk88_c_count == 0) {
+ av1_print(hw, VP9_DEBUG_QOS_INFO,
+ "[Picture %d Quality] NO Data yet.\n",
+ pic_number);
+ /* reset all counts */
+ WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
+ return;
+ }
+ /* qp_c_sum */
+ rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
+
+ av1_print(hw, VP9_DEBUG_QOS_INFO,
+ "[Picture %d Quality] C QP AVG : %d (%d/%d)\n",
+ pic_number, rdata32/blk88_c_count,
+ rdata32, blk88_c_count);
+
+ /* intra_c_count */
+ rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
+
+ av1_print(hw, VP9_DEBUG_QOS_INFO,
+ "[Picture %d Quality] C intra rate : %d%c (%d)\n",
+ pic_number, rdata32*100/blk88_c_count,
+ '%', rdata32);
+
+ /* skipped_cu_c_count */
+ rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
+
+ av1_print(hw, VP9_DEBUG_QOS_INFO,
+ "[Picture %d Quality] C skipped rate : %d%c (%d)\n",
+ pic_number, rdata32*100/blk88_c_count,
+ '%', rdata32);
+
+ /* coeff_non_zero_c_count */
+ rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
+
+ av1_print(hw, VP9_DEBUG_QOS_INFO,
+ "[Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n",
+ pic_number, (100 - rdata32*100/(blk88_c_count*1)),
+ '%', rdata32);
+
+ /* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0],
+ 1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */
+ rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
+
+ av1_print(hw, VP9_DEBUG_QOS_INFO,
+ "[Picture %d Quality] Y QP min : %d\n",
+ pic_number, (rdata32>>0)&0xff);
+
+ frame->min_qp = (rdata32>>0)&0xff;
+
+ av1_print(hw, VP9_DEBUG_QOS_INFO,
+ "[Picture %d Quality] Y QP max : %d\n",
+ pic_number, (rdata32>>8)&0xff);
+
+ frame->max_qp = (rdata32>>8)&0xff;
+
+ av1_print(hw, VP9_DEBUG_QOS_INFO,
+ "[Picture %d Quality] C QP min : %d\n",
+ pic_number, (rdata32>>16)&0xff);
+ av1_print(hw, VP9_DEBUG_QOS_INFO,
+ "[Picture %d Quality] C QP max : %d\n",
+ pic_number, (rdata32>>24)&0xff);
+
+ /* blk22_mv_count */
+ blk22_mv_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
+ if (blk22_mv_count == 0) {
+ av1_print(hw, VP9_DEBUG_QOS_INFO,
+ "[Picture %d Quality] NO MV Data yet.\n",
+ pic_number);
+ /* reset all counts */
+ WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
+ return;
+ }
+ /* mvy_L1_count[39:32], mvx_L1_count[39:32],
+ mvy_L0_count[39:32], mvx_L0_count[39:32] */
+ rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
+ /* should all be 0x00 or 0xff */
+ av1_print(hw, VP9_DEBUG_QOS_INFO,
+ "[Picture %d Quality] MV AVG High Bits: 0x%X\n",
+ pic_number, rdata32);
+
+ mvx_L0_hi = ((rdata32>>0)&0xff);
+ mvy_L0_hi = ((rdata32>>8)&0xff);
+ mvx_L1_hi = ((rdata32>>16)&0xff);
+ mvy_L1_hi = ((rdata32>>24)&0xff);
+
+ /* mvx_L0_count[31:0] */
+ rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
+ temp_value = mvx_L0_hi;
+ temp_value = (temp_value << 32) | rdata32_l;
+
+ if (mvx_L0_hi & 0x80)
+ value = 0xFFFFFFF000000000 | temp_value;
+ else
+ value = temp_value;
+
+ value = div_s64(value, blk22_mv_count);
+
+ av1_print(hw, VP9_DEBUG_QOS_INFO,
+ "[Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n",
+ pic_number, (int)value,
+ value, blk22_mv_count);
+
+ frame->avg_mv = value;
+
+ /* mvy_L0_count[31:0] */
+ rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
+ temp_value = mvy_L0_hi;
+ temp_value = (temp_value << 32) | rdata32_l;
+
+ if (mvy_L0_hi & 0x80)
+ value = 0xFFFFFFF000000000 | temp_value;
+ else
+ value = temp_value;
+
+ av1_print(hw, VP9_DEBUG_QOS_INFO,
+ "[Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n",
+ pic_number, rdata32_l/blk22_mv_count,
+ value, blk22_mv_count);
+
+ /* mvx_L1_count[31:0] */
+ rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
+ temp_value = mvx_L1_hi;
+ temp_value = (temp_value << 32) | rdata32_l;
+ if (mvx_L1_hi & 0x80)
+ value = 0xFFFFFFF000000000 | temp_value;
+ else
+ value = temp_value;
+
+ av1_print(hw, VP9_DEBUG_QOS_INFO,
+ "[Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n",
+ pic_number, rdata32_l/blk22_mv_count,
+ value, blk22_mv_count);
+
+ /* mvy_L1_count[31:0] */
+ rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
+ temp_value = mvy_L1_hi;
+ temp_value = (temp_value << 32) | rdata32_l;
+ if (mvy_L1_hi & 0x80)
+ value = 0xFFFFFFF000000000 | temp_value;
+ else
+ value = temp_value;
+
+ av1_print(hw, VP9_DEBUG_QOS_INFO,
+ "[Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n",
+ pic_number, rdata32_l/blk22_mv_count,
+ value, blk22_mv_count);
+
+ /* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */
+ rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
+ mv_hi = (rdata32>>16)&0xffff;
+ if (mv_hi & 0x8000)
+ mv_hi = 0x8000 - mv_hi;
+
+ av1_print(hw, VP9_DEBUG_QOS_INFO,
+ "[Picture %d Quality] MVX_L0 MAX : %d\n",
+ pic_number, mv_hi);
+
+ frame->max_mv = mv_hi;
+
+ mv_lo = (rdata32>>0)&0xffff;
+ if (mv_lo & 0x8000)
+ mv_lo = 0x8000 - mv_lo;
+
+ av1_print(hw, VP9_DEBUG_QOS_INFO,
+ "[Picture %d Quality] MVX_L0 MIN : %d\n",
+ pic_number, mv_lo);
+
+ frame->min_mv = mv_lo;
+
+ /* {mvy_L0_max, mvy_L0_min} */
+ rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
+ mv_hi = (rdata32>>16)&0xffff;
+ if (mv_hi & 0x8000)
+ mv_hi = 0x8000 - mv_hi;
+
+ av1_print(hw, VP9_DEBUG_QOS_INFO,
+ "[Picture %d Quality] MVY_L0 MAX : %d\n",
+ pic_number, mv_hi);
+
+ mv_lo = (rdata32>>0)&0xffff;
+ if (mv_lo & 0x8000)
+ mv_lo = 0x8000 - mv_lo;
+
+ av1_print(hw, VP9_DEBUG_QOS_INFO,
+ "[Picture %d Quality] MVY_L0 MIN : %d\n",
+ pic_number, mv_lo);
+
+ /* {mvx_L1_max, mvx_L1_min} */
+ rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
+ mv_hi = (rdata32>>16)&0xffff;
+ if (mv_hi & 0x8000)
+ mv_hi = 0x8000 - mv_hi;
+
+ av1_print(hw, VP9_DEBUG_QOS_INFO,
+ "[Picture %d Quality] MVX_L1 MAX : %d\n",
+ pic_number, mv_hi);
+
+ mv_lo = (rdata32>>0)&0xffff;
+ if (mv_lo & 0x8000)
+ mv_lo = 0x8000 - mv_lo;
+
+ av1_print(hw, VP9_DEBUG_QOS_INFO,
+ "[Picture %d Quality] MVX_L1 MIN : %d\n",
+ pic_number, mv_lo);
+
+ /* {mvy_L1_max, mvy_L1_min} */
+ rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
+ mv_hi = (rdata32>>16)&0xffff;
+ if (mv_hi & 0x8000)
+ mv_hi = 0x8000 - mv_hi;
+
+ av1_print(hw, VP9_DEBUG_QOS_INFO,
+ "[Picture %d Quality] MVY_L1 MAX : %d\n",
+ pic_number, mv_hi);
+
+ mv_lo = (rdata32>>0)&0xffff;
+ if (mv_lo & 0x8000)
+ mv_lo = 0x8000 - mv_lo;
+
+ av1_print(hw, VP9_DEBUG_QOS_INFO,
+ "[Picture %d Quality] MVY_L1 MIN : %d\n",
+ pic_number, mv_lo);
+
+ rdata32 = READ_VREG(HEVC_PIC_QUALITY_CTRL);
+
+ av1_print(hw, VP9_DEBUG_QOS_INFO,
+ "[Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n",
+ pic_number, rdata32);
+
+ /* reset all counts */
+ WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
+ }
+}
+
+static int load_param(struct AV1HW_s *hw, union param_u *params, uint32_t dec_status)
+{
+ int i;
+ unsigned long flags;
+ int head_type = 0;
+ if (dec_status == AOM_AV1_SEQ_HEAD_PARSER_DONE)
+ head_type = OBU_SEQUENCE_HEADER;
+ else if (dec_status == AOM_AV1_FRAME_HEAD_PARSER_DONE)
+ head_type = OBU_FRAME_HEADER;
+ else if (dec_status == AOM_AV1_FRAME_PARSER_DONE)
+ head_type = OBU_FRAME;
+ else if (dec_status == AOM_AV1_REDUNDANT_FRAME_HEAD_PARSER_DONE)
+ head_type = OBU_REDUNDANT_FRAME_HEADER;
+ else {
+ //printf("Error, dec_status of 0x%x, not supported!!!\n", dec_status);
+ return -1;
+ }
+ av1_print2(AOM_DEBUG_HW_MORE, "load_param: ret 0x%x\n", head_type);
+
+ if (debug&AOM_AV1_DEBUG_SEND_PARAM_WITH_REG) {
+ get_rpm_param(params);
+ }
+ else {
+ for (i = 0; i < (RPM_END-RPM_BEGIN); i += 4) {
+ int32_t ii;
+ for (ii = 0; ii < 4; ii++) {
+ params->l.data[i+ii]=hw->rpm_ptr[i+3-ii];
+ }
+ }
+ }
+
+ params->p.enable_ref_frame_mvs = (params->p.seq_flags >> 7) & 0x1;
+ params->p.enable_superres = (params->p.seq_flags >> 15) & 0x1;
+
+ if (debug & VP9_DEBUG_BUFMGR_MORE) {
+ lock_buffer_pool(hw->pbi->common.buffer_pool, flags);
+ pr_info("aom_param: (%d)\n", hw->pbi->decode_idx);
+ //pbi->slice_idx++;
+ for ( i = 0; i < (RPM_END-RPM_BEGIN); i++) {
+ pr_info("%04x ", params->l.data[i]);
+ if (((i + 1) & 0xf) == 0)
+ pr_info("\n");
+ }
+ unlock_buffer_pool(hw->pbi->common.buffer_pool, flags);
+ }
+ return head_type;
+}
+
+static int av1_postproc(struct AV1HW_s *hw)
+{
+ if (hw->postproc_done)
+ return 0;
+ hw->postproc_done = 1;
+ return av1_bufmgr_postproc(hw->pbi, hw->frame_decoded);
+}
+
+static irqreturn_t vav1_isr_thread_fn(int irq, void *data)
+{
+ struct AV1HW_s *hw = (struct AV1HW_s *)data;
+ unsigned int dec_status = hw->dec_status;
+ int obu_type;
+
+ /*if (hw->wait_buf)
+ * pr_info("set wait_buf to 0\r\n");
+ */
+ if (hw->eos)
+ return IRQ_HANDLED;
+ hw->wait_buf = 0;
+ if ((dec_status == AOM_NAL_DECODE_DONE) ||
+ (dec_status == AOM_SEARCH_BUFEMPTY) ||
+ (dec_status == AOM_DECODE_BUFEMPTY)
+ ) {
+ if (hw->m_ins_flag) {
+ reset_process_time(hw);
+ if (!vdec_frame_based(hw_to_vdec(hw)))
+ dec_again_process(hw);
+ else {
+ hw->dec_result = DEC_RESULT_DONE;
+ vdec_schedule_work(&hw->work);
+ }
+ }
+ hw->process_busy = 0;
+ return IRQ_HANDLED;
+ } else if (dec_status == AOM_AV1_DEC_PIC_END) {
+ if (hw->m_ins_flag) {
+#ifdef USE_DEC_PIC_END
+ if (READ_VREG(PIC_END_LCU_COUNT) != 0) {
+ hw->frame_decoded = 1;
+ /*
+ In c module, multi obus are put in one packet, which is decoded
+ with av1_receive_compressed_data().
+ For STREAM_MODE or SINGLE_MODE, there is no packet boundary,
+ we assume each packet must and only include one picture of data (LCUs)
+ or cm->show_existing_frame is 1
+ */
+ pr_info("Decoding done\n");
+ hw->config_next_ref_info_flag = 1; /*to do: low_latency_flag case*/
+ //config_next_ref_info_hw(hw);
+ }
+#endif
+
+ if (get_picture_qos)
+ get_picture_qos_info(hw);
+
+ reset_process_time(hw);
+ if (/*hw->vf_pre_count == 0 ||*/ hw->low_latency_flag)
+ av1_postproc(hw);
+
+ hw->dec_result = DEC_RESULT_DONE;
+ amhevc_stop();
+ /*if (mcrcc_cache_alg_flag)
+ dump_hit_rate(hw);*/
+ vdec_schedule_work(&hw->work);
+ } else {
+ av1_print(hw, AOM_DEBUG_HW_MORE, "PIC_END, search head ...\n");
+ WRITE_VREG(HEVC_DEC_STATUS_REG, AOM_AV1_SEARCH_HEAD);
+#ifdef USE_DEC_PIC_END
+ if (READ_VREG(PIC_END_LCU_COUNT) != 0) {
+ hw->frame_decoded = 1;
+ /*
+ In c module, multi obus are put in one packet, which is decoded
+ with av1_receive_compressed_data().
+ For STREAM_MODE or SINGLE_MODE, there is no packet boundary,
+ we assume each packet must and only include one picture of data (LCUs)
+ or cm->show_existing_frame is 1
+ */
+ av1_print(hw, AOM_DEBUG_HW_MORE, "Decoding done\n");
+ config_next_ref_info_hw(hw);
+ }
+#endif
+
+ if (hw->low_latency_flag) {
+ av1_postproc(hw);
+ vdec_profile(hw_to_vdec(hw), VDEC_PROFILE_EVENT_CB);
+ if (debug & PRINT_FLAG_VDEC_DETAIL)
+ pr_info("%s AV1 frame done \n", __func__);
+ }
+ }
+
+ hw->process_busy = 0;
+ return IRQ_HANDLED;
+ }
+
+ if (dec_status == AOM_EOS) {
+ if (hw->m_ins_flag)
+ reset_process_time(hw);
+
+ av1_print(hw, AOM_DEBUG_HW_MORE, "VP9_EOS, flush buffer\r\n");
+
+ av1_postproc(hw);
+
+ av1_print(hw, AOM_DEBUG_HW_MORE, "send VP9_10B_DISCARD_NAL\r\n");
+ WRITE_VREG(HEVC_DEC_STATUS_REG, AOM_AV1_DISCARD_NAL);
+ hw->process_busy = 0;
+ if (hw->m_ins_flag) {
+ hw->dec_result = DEC_RESULT_DONE;
+ amhevc_stop();
+ vdec_schedule_work(&hw->work);
+ }
+ return IRQ_HANDLED;
+ } else if (dec_status == AOM_DECODE_OVER_SIZE) {
+ av1_print(hw, AOM_DEBUG_HW_MORE, "av1 decode oversize !!\n");
+ debug |= (VP9_DEBUG_DIS_LOC_ERROR_PROC |
+ VP9_DEBUG_DIS_SYS_ERROR_PROC);
+ hw->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
+ hw->process_busy = 0;
+ if (hw->m_ins_flag)
+ reset_process_time(hw);
+ return IRQ_HANDLED;
+ }
+
+ obu_type = load_param(hw, &hw->aom_param, dec_status);
+ if (obu_type < 0) {
+ hw->process_busy = 0;
+ return IRQ_HANDLED;
+ }
+
+ if (obu_type == OBU_SEQUENCE_HEADER) {
+ int next_lcu_size;
+ av1_bufmgr_process(hw->pbi, &hw->aom_param, 0, obu_type);
+
+ bit_depth_luma = av1_param.p.bit_depth;
+ bit_depth_chroma = av1_param.p.bit_depth;
+
+ next_lcu_size = ((hw->aom_param.p.seq_flags >> 6) & 0x1) ? 128 : 64;
+
+ if (next_lcu_size != hw->current_lcu_size) {
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ " ## lcu_size changed from %d to %d\n",
+ hw->current_lcu_size, next_lcu_size);
+ hw->current_lcu_size = next_lcu_size;
+ }
+
+ if (!hw->pic_list_init_done) {
+#if 0
+ if (hw->m_ins_flag) {
+ /* picture list init.*/
+ hw->dec_result = DEC_INIT_PICLIST;
+ vdec_schedule_work(&hw->work);
+ } else
+#endif
+ {
+ init_pic_list(hw);
+ init_pic_list_hw(hw);
+ }
+ hw->pic_list_init_done = true;
+ }
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "AOM_AV1_SEQ_HEAD_PARSER_DONE, search head ...\n");
+ WRITE_VREG(HEVC_DEC_STATUS_REG, AOM_AV1_SEARCH_HEAD);
+ hw->process_busy = 0;
+ return IRQ_HANDLED;
+ }
+#ifndef USE_DEC_PIC_END
+ //if (pbi->wait_buf) {
+ if (pbi->bufmgr_proc_count > 0) {
+ if (READ_VREG(PIC_END_LCU_COUNT) != 0) {
+ hw->frame_decoded = 1;
+ /*
+ In c module, multi obus are put in one packet, which is decoded
+ with av1_receive_compressed_data().
+ For STREAM_MODE or SINGLE_MODE, there is no packet boundary,
+ we assume each packet must and only include one picture of data (LCUs)
+ or cm->show_existing_frame is 1
+ */
+ av1_print(hw, AOM_DEBUG_HW_MORE, "Decoding done\n");
+ }
+ }
+#endif
+#if 1
+/*def CHECK_OBU_REDUNDANT_FRAME_HEADER*/
+ if (debug & AOM_DEBUG_BUFMGR_ONLY) {
+ if (READ_VREG(PIC_END_LCU_COUNT) != 0)
+ hw->obu_frame_frame_head_come_after_tile = 0;
+
+ if (obu_type == OBU_FRAME_HEADER ||
+ obu_type == OBU_FRAME) {
+ hw->obu_frame_frame_head_come_after_tile = 1;
+ } else if (obu_type == OBU_REDUNDANT_FRAME_HEADER &&
+ hw->obu_frame_frame_head_come_after_tile == 0) {
+ if (hw->frame_decoded == 1) {
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "Warning, OBU_REDUNDANT_FRAME_HEADER come without OBU_FRAME or OBU_FRAME_HEAD\n");
+ hw->frame_decoded = 0;
+ }
+ }
+ }
+#endif
+ if (hw->frame_decoded)
+ hw->one_compressed_data_done = 1;
+
+ if (hw->m_ins_flag)
+ reset_process_time(hw);
+
+
+ if (hw->process_state != PROC_STATE_SENDAGAIN
+ ) {
+ if (hw->mmu_enable)
+ av1_recycle_mmu_buf_tail(hw);
+
+
+ if (hw->one_compressed_data_done) {
+ av1_postproc(hw);
+ av1_release_bufs(hw);
+ }
+ }
+
+ av1_continue_decoding(hw, obu_type);
+ hw->postproc_done = 0;
+ hw->process_busy = 0;
+
+ if (hw->m_ins_flag)
+ start_process_time(hw);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t vav1_isr(int irq, void *data)
+{
+ int i;
+ unsigned int dec_status;
+ struct AV1HW_s *hw = (struct AV1HW_s *)data;
+ //struct AV1_Common_s *const cm = &hw->pbi->common;
+ uint debug_tag;
+
+ WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1);
+
+ dec_status = READ_VREG(HEVC_DEC_STATUS_REG) & 0xff;
+ if (!hw)
+ return IRQ_HANDLED;
+ if (hw->init_flag == 0)
+ return IRQ_HANDLED;
+ if (hw->process_busy)/*on process.*/
+ return IRQ_HANDLED;
+ hw->dec_status = dec_status;
+ hw->process_busy = 1;
+ if (debug & VP9_DEBUG_BUFMGR)
+ av1_print(hw, VP9_DEBUG_BUFMGR,
+ "av1 isr (%d) dec status = 0x%x, lcu 0x%x shiftbyte 0x%x (%x %x lev %x, wr %x, rd %x)\n",
+ irq,
+ dec_status, READ_VREG(HEVC_PARSER_LCU_START),
+ READ_VREG(HEVC_SHIFT_BYTE_COUNT),
+ READ_VREG(HEVC_STREAM_START_ADDR),
+ READ_VREG(HEVC_STREAM_END_ADDR),
+ READ_VREG(HEVC_STREAM_LEVEL),
+ READ_VREG(HEVC_STREAM_WR_PTR),
+ READ_VREG(HEVC_STREAM_RD_PTR)
+ );
+
+ debug_tag = READ_HREG(DEBUG_REG1);
+ if (debug_tag & 0x10000) {
+ pr_info("LMEM<tag %x>:\n", READ_HREG(DEBUG_REG1));
+ for (i = 0; i < 0x400; i += 4) {
+ int ii;
+ if ((i & 0xf) == 0)
+ pr_info("%03x: ", i);
+ for (ii = 0; ii < 4; ii++) {
+ pr_info("%04x ",
+ hw->lmem_ptr[i + 3 - ii]);
+ }
+ if (((i + ii) & 0xf) == 0)
+ pr_info("\n");
+ }
+ if (((udebug_pause_pos & 0xffff)
+ == (debug_tag & 0xffff)) &&
+ (udebug_pause_decode_idx == 0 ||
+ udebug_pause_decode_idx == hw->result_done_count) &&
+ (udebug_pause_val == 0 ||
+ udebug_pause_val == READ_HREG(DEBUG_REG2))) {
+ udebug_pause_pos &= 0xffff;
+ hw->ucode_pause_pos = udebug_pause_pos;
+ }
+ else if (debug_tag & 0x20000)
+ hw->ucode_pause_pos = 0xffffffff;
+ if (hw->ucode_pause_pos)
+ reset_process_time(hw);
+ else
+ WRITE_HREG(DEBUG_REG1, 0);
+ } else if (debug_tag != 0) {
+ pr_info(
+ "dbg%x: %x lcu %x\n", READ_HREG(DEBUG_REG1),
+ READ_HREG(DEBUG_REG2),
+ READ_VREG(HEVC_PARSER_LCU_START));
+
+ if (((udebug_pause_pos & 0xffff)
+ == (debug_tag & 0xffff)) &&
+ (udebug_pause_decode_idx == 0 ||
+ udebug_pause_decode_idx == hw->result_done_count) &&
+ (udebug_pause_val == 0 ||
+ udebug_pause_val == READ_HREG(DEBUG_REG2))) {
+ udebug_pause_pos &= 0xffff;
+ hw->ucode_pause_pos = udebug_pause_pos;
+ }
+ if (hw->ucode_pause_pos)
+ reset_process_time(hw);
+ else
+ WRITE_HREG(DEBUG_REG1, 0);
+ hw->process_busy = 0;
+ return IRQ_HANDLED;
+ }
+
+ if (dec_status == AOM_AV1_FGS_PARAM) {
+ uint32_t status_val = READ_VREG(HEVC_DEC_STATUS_REG);
+ WRITE_VREG(HEVC_DEC_STATUS_REG, AOM_AV1_FGS_PARAM_CONT);
+ // Bit[11] - 0 Read, 1 - Write
+ // Bit[10:8] - film_grain_params_ref_idx // For Write request
+ if ((status_val >> 11) & 0x1) {
+ uint32_t film_grain_params_ref_idx = (status_val >> 8) & 0x7;
+ config_film_grain_reg(hw, film_grain_params_ref_idx);
+ }
+ else
+ read_film_grain_reg(hw);
+ hw->process_busy = 0;
+ return IRQ_HANDLED;
+ }
+
+ if (!hw->m_ins_flag) {
+ av1_print(hw, VP9_DEBUG_BUFMGR,
+ "error flag = %d\n", hw->error_flag);
+ if (hw->error_flag == 1) {
+ hw->error_flag = 2;
+ hw->process_busy = 0;
+ return IRQ_HANDLED;
+ } else if (hw->error_flag == 3) {
+ hw->process_busy = 0;
+ return IRQ_HANDLED;
+ }
+
+ if (get_free_buf_count(hw) <= 0) {
+ /*
+ if (hw->wait_buf == 0)
+ pr_info("set wait_buf to 1\r\n");
+ */
+ hw->wait_buf = 1;
+ hw->process_busy = 0;
+ av1_print(hw, VP9_DEBUG_BUFMGR,
+ "free buf not enough = %d\n",
+ get_free_buf_count(hw));
+ return IRQ_HANDLED;
+ }
+ }
+ return IRQ_WAKE_THREAD;
+}
+
+static void av1_set_clk(struct work_struct *work)
+{
+ struct AV1HW_s *hw = container_of(work,
+ struct AV1HW_s, set_clk_work);
+ int fps = 96000 / hw->frame_dur;
+
+ if (hevc_source_changed(VFORMAT_AV1,
+ frame_width, frame_height, fps) > 0)
+ hw->saved_resolution = frame_width *
+ frame_height * fps;
+}
+
+static void vav1_put_timer_func(unsigned long arg)
+{
+ struct AV1HW_s *hw = (struct AV1HW_s *)arg;
+ struct timer_list *timer = &hw->timer;
+ uint8_t empty_flag;
+ unsigned int buf_level;
+
+ enum receviver_start_e state = RECEIVER_INACTIVE;
+
+ if (hw->m_ins_flag) {
+ if (hw_to_vdec(hw)->next_status
+ == VDEC_STATUS_DISCONNECTED) {
+ hw->dec_result = DEC_RESULT_FORCE_EXIT;
+ vdec_schedule_work(&hw->work);
+ pr_debug(
+ "vdec requested to be disconnected\n");
+ return;
+ }
+ }
+ if (hw->init_flag == 0) {
+ if (hw->stat & STAT_TIMER_ARM) {
+ timer->expires = jiffies + PUT_INTERVAL;
+ add_timer(&hw->timer);
+ }
+ return;
+ }
+ if (hw->m_ins_flag == 0) {
+ if (vf_get_receiver(hw->provider_name)) {
+ state =
+ vf_notify_receiver(hw->provider_name,
+ VFRAME_EVENT_PROVIDER_QUREY_STATE,
+ NULL);
+ if ((state == RECEIVER_STATE_NULL)
+ || (state == RECEIVER_STATE_NONE))
+ state = RECEIVER_INACTIVE;
+ } else
+ state = RECEIVER_INACTIVE;
+
+ empty_flag = (READ_VREG(HEVC_PARSER_INT_STATUS) >> 6) & 0x1;
+ /* error watchdog */
+ if (empty_flag == 0) {
+ /* decoder has input */
+ if ((debug & VP9_DEBUG_DIS_LOC_ERROR_PROC) == 0) {
+
+ buf_level = READ_VREG(HEVC_STREAM_LEVEL);
+ /* receiver has no buffer to recycle */
+ if ((state == RECEIVER_INACTIVE) &&
+ (kfifo_is_empty(&hw->display_q) &&
+ buf_level > 0x200)
+ ) {
+ WRITE_VREG
+ (HEVC_ASSIST_MBOX0_IRQ_REG,
+ 0x1);
+ }
+ }
+
+ if ((debug & VP9_DEBUG_DIS_SYS_ERROR_PROC) == 0) {
+ /* receiver has no buffer to recycle */
+ /*if ((state == RECEIVER_INACTIVE) &&
+ * (kfifo_is_empty(&hw->display_q))) {
+ *pr_info("AV1 something error,need reset\n");
+ *}
+ */
+ }
+ }
+ }
+#ifdef MULTI_INSTANCE_SUPPORT
+ else {
+ if (
+ (decode_timeout_val > 0) &&
+ (hw->start_process_time > 0) &&
+ ((1000 * (jiffies - hw->start_process_time) / HZ)
+ > decode_timeout_val)
+ ) {
+ int current_lcu_idx =
+ READ_VREG(HEVC_PARSER_LCU_START)
+ & 0xffffff;
+ if (hw->last_lcu_idx == current_lcu_idx) {
+ if (hw->decode_timeout_count > 0)
+ hw->decode_timeout_count--;
+ if (hw->decode_timeout_count == 0) {
+ if (input_frame_based(
+ hw_to_vdec(hw)) ||
+ (READ_VREG(HEVC_STREAM_LEVEL) > 0x200))
+ timeout_process(hw);
+ else {
+ av1_print(hw, 0,
+ "timeout & empty, again\n");
+ dec_again_process(hw);
+ }
+ }
+ } else {
+ start_process_time(hw);
+ hw->last_lcu_idx = current_lcu_idx;
+ }
+ }
+ }
+#endif
+
+ if ((hw->ucode_pause_pos != 0) &&
+ (hw->ucode_pause_pos != 0xffffffff) &&
+ udebug_pause_pos != hw->ucode_pause_pos) {
+ hw->ucode_pause_pos = 0;
+ WRITE_HREG(DEBUG_REG1, 0);
+ }
+#ifdef MULTI_INSTANCE_SUPPORT
+ if (debug & VP9_DEBUG_FORCE_SEND_AGAIN) {
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "Force Send Again\r\n");
+ debug &= ~VP9_DEBUG_FORCE_SEND_AGAIN;
+ reset_process_time(hw);
+ hw->dec_result = DEC_RESULT_AGAIN;
+ if (hw->process_state ==
+ PROC_STATE_DECODESLICE) {
+ if (hw->mmu_enable)
+ av1_recycle_mmu_buf(hw);
+ hw->process_state =
+ PROC_STATE_SENDAGAIN;
+ }
+ amhevc_stop();
+
+ vdec_schedule_work(&hw->work);
+ }
+
+ if (debug & VP9_DEBUG_DUMP_DATA) {
+ debug &= ~VP9_DEBUG_DUMP_DATA;
+ av1_print(hw, 0,
+ "%s: chunk size 0x%x off 0x%x sum 0x%x\n",
+ __func__,
+ hw->chunk->size,
+ hw->chunk->offset,
+ get_data_check_sum(hw, hw->chunk->size)
+ );
+ dump_data(hw, hw->chunk->size);
+ }
+#endif
+ if (debug & VP9_DEBUG_DUMP_PIC_LIST) {
+ dump_pic_list(hw);
+ debug &= ~VP9_DEBUG_DUMP_PIC_LIST;
+ }
+ if (debug & VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC) {
+ WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1);
+ debug &= ~VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC;
+ }
+ /*if (debug & VP9_DEBUG_HW_RESET) {
+ }*/
+
+ if (radr != 0) {
+ if ((radr >> 24) != 0) {
+ int count = radr >> 24;
+ int adr = radr & 0xffffff;
+ int i;
+ for (i = 0; i < count; i++)
+ pr_info("READ_VREG(%x)=%x\n", adr+i, READ_VREG(adr+i));
+ } else if (rval != 0) {
+ WRITE_VREG(radr, rval);
+ pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
+ } else
+ pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
+ rval = 0;
+ radr = 0;
+ }
+ if (pop_shorts != 0) {
+ int i;
+ u32 sum = 0;
+
+ pr_info("pop stream 0x%x shorts\r\n", pop_shorts);
+ for (i = 0; i < pop_shorts; i++) {
+ u32 data =
+ (READ_HREG(HEVC_SHIFTED_DATA) >> 16);
+ WRITE_HREG(HEVC_SHIFT_COMMAND,
+ (1<<7)|16);
+ if ((i & 0xf) == 0)
+ pr_info("%04x:", i);
+ pr_info("%04x ", data);
+ if (((i + 1) & 0xf) == 0)
+ pr_info("\r\n");
+ sum += data;
+ }
+ pr_info("\r\nsum = %x\r\n", sum);
+ pop_shorts = 0;
+ }
+ if (dbg_cmd != 0) {
+ if (dbg_cmd == 1) {
+ u32 disp_laddr;
+
+ if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXBB &&
+ get_double_write_mode(hw) == 0) {
+ disp_laddr =
+ READ_VCBUS_REG(AFBC_BODY_BADDR) << 4;
+ } else {
+ struct canvas_s cur_canvas;
+
+ canvas_read((READ_VCBUS_REG(VD1_IF0_CANVAS0)
+ & 0xff), &cur_canvas);
+ disp_laddr = cur_canvas.addr;
+ }
+ pr_info("current displayed buffer address %x\r\n",
+ disp_laddr);
+ }
+ dbg_cmd = 0;
+ }
+ /*don't changed at start.*/
+ if (hw->get_frame_dur && hw->show_frame_num > 60 &&
+ hw->frame_dur > 0 && hw->saved_resolution !=
+ frame_width * frame_height *
+ (96000 / hw->frame_dur))
+ vdec_schedule_work(&hw->set_clk_work);
+
+ timer->expires = jiffies + PUT_INTERVAL;
+ add_timer(timer);
+}
+
+
+int vav1_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
+{
+ struct AV1HW_s *av1 =
+ (struct AV1HW_s *)vdec->private;
+
+ if (!av1)
+ return -1;
+
+ vstatus->frame_width = frame_width;
+ vstatus->frame_height = frame_height;
+ if (av1->frame_dur != 0)
+ vstatus->frame_rate = 96000 / av1->frame_dur;
+ else
+ vstatus->frame_rate = -1;
+ vstatus->error_count = 0;
+ vstatus->status = av1->stat | av1->fatal_error;
+ vstatus->frame_dur = av1->frame_dur;
+#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
+ vstatus->bit_rate = gvs->bit_rate;
+ vstatus->frame_data = gvs->frame_data;
+ vstatus->total_data = gvs->total_data;
+ vstatus->frame_count = gvs->frame_count;
+ vstatus->error_frame_count = gvs->error_frame_count;
+ vstatus->drop_frame_count = gvs->drop_frame_count;
+ vstatus->total_data = gvs->total_data;
+ vstatus->samp_cnt = gvs->samp_cnt;
+ vstatus->offset = gvs->offset;
+ snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
+ "%s", DRIVER_NAME);
+#endif
+ return 0;
+}
+
+int vav1_set_isreset(struct vdec_s *vdec, int isreset)
+{
+ is_reset = isreset;
+ return 0;
+}
+
+#if 0
+static void AV1_DECODE_INIT(void)
+{
+ /* enable av1 clocks */
+ WRITE_VREG(DOS_GCLK_EN3, 0xffffffff);
+ /* *************************************************************** */
+ /* Power ON HEVC */
+ /* *************************************************************** */
+ /* Powerup HEVC */
+ WRITE_VREG(AO_RTI_GEN_PWR_SLEEP0,
+ READ_VREG(AO_RTI_GEN_PWR_SLEEP0) & (~(0x3 << 6)));
+ WRITE_VREG(DOS_MEM_PD_HEVC, 0x0);
+ WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) | (0x3ffff << 2));
+ WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) & (~(0x3ffff << 2)));
+ /* remove isolations */
+ WRITE_VREG(AO_RTI_GEN_PWR_ISO0,
+ READ_VREG(AO_RTI_GEN_PWR_ISO0) & (~(0x3 << 10)));
+
+}
+#endif
+
+static void vav1_prot_init(struct AV1HW_s *hw, u32 mask)
+{
+ unsigned int data32;
+ /* VP9_DECODE_INIT(); */
+ av1_print(hw, AOM_DEBUG_HW_MORE, "%s %d\n", __func__, __LINE__);
+
+ aom_config_work_space_hw(hw, mask);
+ if (mask & HW_MASK_BACK) {
+ //to do: .. for single instance, called after init_pic_list()
+ if (hw->m_ins_flag)
+ init_pic_list_hw(hw);
+ }
+
+ aom_init_decoder_hw(hw, mask);
+
+#ifdef AOM_AV1_DBLK_INIT
+ av1_print(hw, AOM_DEBUG_HW_MORE,
+ "[test.c] av1_loop_filter_init (run once before decoding start)\n");
+ av1_loop_filter_init(hw->lfi, hw->lf);
+#endif
+ if ((mask & HW_MASK_FRONT) == 0)
+ return;
+#if 1
+ if (debug & VP9_DEBUG_BUFMGR_MORE)
+ pr_info("%s\n", __func__);
+ data32 = READ_VREG(HEVC_STREAM_CONTROL);
+ data32 = data32 |
+ (1 << 0)/*stream_fetch_enable*/
+ ;
+ WRITE_VREG(HEVC_STREAM_CONTROL, data32);
+
+ if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
+ if (debug & VP9_DEBUG_BUFMGR)
+ pr_info("[test.c] Config STREAM_FIFO_CTL\n");
+ data32 = READ_VREG(HEVC_STREAM_FIFO_CTL);
+ data32 = data32 |
+ (1 << 29) // stream_fifo_hole
+ ;
+ WRITE_VREG(HEVC_STREAM_FIFO_CTL, data32);
+ }
+#if 0
+ data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
+ if (data32 != 0x00000100) {
+ pr_info("av1 prot init error %d\n", __LINE__);
+ return;
+ }
+ data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
+ if (data32 != 0x00000300) {
+ pr_info("av1 prot init error %d\n", __LINE__);
+ return;
+ }
+ WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x12345678);
+ WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x9abcdef0);
+ data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
+ if (data32 != 0x12345678) {
+ pr_info("av1 prot init error %d\n", __LINE__);
+ return;
+ }
+ data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
+ if (data32 != 0x9abcdef0) {
+ pr_info("av1 prot init error %d\n", __LINE__);
+ return;
+ }
+#endif
+ WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x000000001);
+ WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x00000300);
+#endif
+
+
+
+ WRITE_VREG(HEVC_WAIT_FLAG, 1);
+
+ /* WRITE_VREG(HEVC_MPSR, 1); */
+
+ /* clear mailbox interrupt */
+ WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1);
+
+ /* enable mailbox interrupt */
+ WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 1);
+
+ /* disable PSCALE for hardware sharing */
+ WRITE_VREG(HEVC_PSCALE_CTRL, 0);
+
+ WRITE_VREG(DEBUG_REG1, 0x0);
+ /*check vps/sps/pps/i-slice in ucode*/
+ WRITE_VREG(NAL_SEARCH_CTL, 0x8);
+
+ WRITE_VREG(DECODE_STOP_POS, udebug_flag);
+}
+
+static int vav1_local_init(struct AV1HW_s *hw)
+{
+ int i;
+ int ret;
+ int width, height;
+
+ hw->gvs = vzalloc(sizeof(struct vdec_info));
+ if (NULL == hw->gvs) {
+ pr_info("the struct of vdec status malloc failed.\n");
+ return -1;
+ }
+#ifdef DEBUG_PTS
+ hw->pts_missed = 0;
+ hw->pts_hit = 0;
+#endif
+ hw->new_frame_displayed = 0;
+ hw->last_put_idx = -1;
+ hw->saved_resolution = 0;
+ hw->get_frame_dur = false;
+ on_no_keyframe_skiped = 0;
+ hw->duration_from_pts_done = 0;
+ hw->av1_first_pts_ready = 0;
+ hw->frame_cnt_window = 0;
+ width = hw->vav1_amstream_dec_info.width;
+ height = hw->vav1_amstream_dec_info.height;
+ hw->frame_dur =
+ (hw->vav1_amstream_dec_info.rate ==
+ 0) ? 3200 : hw->vav1_amstream_dec_info.rate;
+ if (width && height)
+ hw->frame_ar = height * 0x100 / width;
+/*
+ *TODO:FOR VERSION
+ */
+ pr_info("av1: ver (%d,%d) decinfo: %dx%d rate=%d\n", av1_version,
+ 0, width, height, hw->frame_dur);
+
+ if (hw->frame_dur == 0)
+ hw->frame_dur = 96000 / 24;
+
+ INIT_KFIFO(hw->display_q);
+ INIT_KFIFO(hw->newframe_q);
+
+
+ for (i = 0; i < VF_POOL_SIZE; i++) {
+ const struct vframe_s *vf = &hw->vfpool[i];
+
+ hw->vfpool[i].index = -1;
+ kfifo_put(&hw->newframe_q, vf);
+ }
+
+
+ ret = av1_local_init(hw);
+
+ if (!hw->pts_unstable) {
+ hw->pts_unstable =
+ (hw->vav1_amstream_dec_info.rate == 0)?1:0;
+ pr_info("set pts unstable\n");
+ }
+
+ return ret;
+}
+
+
+#ifdef MULTI_INSTANCE_SUPPORT
+static s32 vav1_init(struct vdec_s *vdec)
+{
+ struct AV1HW_s *hw = (struct AV1HW_s *)vdec->private;
+#else
+static s32 vav1_init(struct AV1HW_s *hw)
+{
+#endif
+ int ret;
+ int fw_size = 0x1000 * 16;
+ struct firmware_s *fw = NULL;
+
+ hw->stat |= STAT_TIMER_INIT;
+
+ if (vav1_local_init(hw) < 0)
+ return -EBUSY;
+
+ fw = vmalloc(sizeof(struct firmware_s) + fw_size);
+ if (IS_ERR_OR_NULL(fw))
+ return -ENOMEM;
+
+ av1_print(hw, AOM_DEBUG_HW_MORE, "%s %d\n", __func__, __LINE__);
+#ifdef DEBUG_USE_VP9_DEVICE_NAME
+ if (get_firmware_data(VIDEO_DEC_VP9_MMU, fw->data) < 0) {
+#else
+ if (get_firmware_data(VIDEO_DEC_AV1_MMU, fw->data) < 0) {
+#endif
+ pr_err("get firmware fail.\n");
+ printk("%s %d\n", __func__, __LINE__);
+ vfree(fw);
+ return -1;
+ }
+ av1_print(hw, AOM_DEBUG_HW_MORE, "%s %d\n", __func__, __LINE__);
+
+ fw->len = fw_size;
+
+ INIT_WORK(&hw->set_clk_work, av1_set_clk);
+ init_timer(&hw->timer);
+
+#ifdef MULTI_INSTANCE_SUPPORT
+ if (hw->m_ins_flag) {
+ hw->timer.data = (ulong) hw;
+ hw->timer.function = vav1_put_timer_func;
+ hw->timer.expires = jiffies + PUT_INTERVAL;
+
+ /*add_timer(&hw->timer);
+
+ hw->stat |= STAT_TIMER_ARM;
+ hw->stat |= STAT_ISR_REG;*/
+
+ INIT_WORK(&hw->work, av1_work);
+ hw->fw = fw;
+
+ return 0;
+ }
+#endif
+ amhevc_enable();
+
+ ret = amhevc_loadmc_ex(VFORMAT_AV1, NULL, fw->data);
+ if (ret < 0) {
+ amhevc_disable();
+ vfree(fw);
+ pr_err("AV1: the %s fw loading failed, err: %x\n",
+ tee_enabled() ? "TEE" : "local", ret);
+ return -EBUSY;
+ }
+
+ vfree(fw);
+
+ hw->stat |= STAT_MC_LOAD;
+
+ /* enable AMRISC side protocol */
+ vav1_prot_init(hw, HW_MASK_FRONT | HW_MASK_BACK);
+
+ if (vdec_request_threaded_irq(VDEC_IRQ_0,
+ vav1_isr,
+ vav1_isr_thread_fn,
+ IRQF_ONESHOT,/*run thread on this irq disabled*/
+ "vvp9-irq", (void *)hw)) {
+ pr_info("vvp9 irq register error.\n");
+ amhevc_disable();
+ return -ENOENT;
+ }
+
+ hw->stat |= STAT_ISR_REG;
+
+ hw->provider_name = PROVIDER_NAME;
+#ifdef MULTI_INSTANCE_SUPPORT
+ vf_provider_init(&vav1_vf_prov, PROVIDER_NAME,
+ &vav1_vf_provider, hw);
+ vf_reg_provider(&vav1_vf_prov);
+ vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL);
+ if (hw->frame_dur != 0) {
+ if (!is_reset)
+ vf_notify_receiver(hw->provider_name,
+ VFRAME_EVENT_PROVIDER_FR_HINT,
+ (void *)
+ ((unsigned long)hw->frame_dur));
+ }
+#else
+ vf_provider_init(&vav1_vf_prov, PROVIDER_NAME, &vav1_vf_provider,
+ hw);
+ vf_reg_provider(&vav1_vf_prov);
+ vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL);
+ if (!is_reset)
+ vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_FR_HINT,
+ (void *)((unsigned long)hw->frame_dur));
+#endif
+ hw->stat |= STAT_VF_HOOK;
+
+ hw->timer.data = (ulong)hw;
+ hw->timer.function = vav1_put_timer_func;
+ hw->timer.expires = jiffies + PUT_INTERVAL;
+
+ hw->stat |= STAT_VDEC_RUN;
+
+ add_timer(&hw->timer);
+
+ hw->stat |= STAT_TIMER_ARM;
+
+ amhevc_start();
+
+ hw->init_flag = 1;
+ hw->process_busy = 0;
+ pr_info("%d, vav1_init, RP=0x%x\n",
+ __LINE__, READ_VREG(HEVC_STREAM_RD_PTR));
+ return 0;
+}
+
+static int vmav1_stop(struct AV1HW_s *hw)
+{
+ hw->init_flag = 0;
+
+ if (hw->stat & STAT_VDEC_RUN) {
+ amhevc_stop();
+ hw->stat &= ~STAT_VDEC_RUN;
+ }
+ if (hw->stat & STAT_ISR_REG) {
+ vdec_free_irq(VDEC_IRQ_0, (void *)hw);
+ hw->stat &= ~STAT_ISR_REG;
+ }
+ if (hw->stat & STAT_TIMER_ARM) {
+ del_timer_sync(&hw->timer);
+ hw->stat &= ~STAT_TIMER_ARM;
+ }
+
+ if (hw->stat & STAT_VF_HOOK) {
+ if (!is_reset)
+ vf_notify_receiver(hw->provider_name,
+ VFRAME_EVENT_PROVIDER_FR_END_HINT,
+ NULL);
+
+ vf_unreg_provider(&vav1_vf_prov);
+ hw->stat &= ~STAT_VF_HOOK;
+ }
+ av1_local_uninit(hw);
+ reset_process_time(hw);
+ cancel_work_sync(&hw->work);
+ cancel_work_sync(&hw->set_clk_work);
+ uninit_mmu_buffers(hw);
+ if (hw->fw)
+ vfree(hw->fw);
+ hw->fw = NULL;
+ return 0;
+}
+
+static int vav1_stop(struct AV1HW_s *hw)
+{
+
+ hw->init_flag = 0;
+ hw->first_sc_checked = 0;
+ if (hw->stat & STAT_VDEC_RUN) {
+ amhevc_stop();
+ hw->stat &= ~STAT_VDEC_RUN;
+ }
+
+ if (hw->stat & STAT_ISR_REG) {
+#ifdef MULTI_INSTANCE_SUPPORT
+ if (!hw->m_ins_flag)
+#endif
+ WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0);
+ vdec_free_irq(VDEC_IRQ_0, (void *)hw);
+ hw->stat &= ~STAT_ISR_REG;
+ }
+
+ if (hw->stat & STAT_TIMER_ARM) {
+ del_timer_sync(&hw->timer);
+ hw->stat &= ~STAT_TIMER_ARM;
+ }
+
+ if (hw->stat & STAT_VF_HOOK) {
+ if (!is_reset)
+ vf_notify_receiver(hw->provider_name,
+ VFRAME_EVENT_PROVIDER_FR_END_HINT,
+ NULL);
+
+ vf_unreg_provider(&vav1_vf_prov);
+ hw->stat &= ~STAT_VF_HOOK;
+ }
+ av1_local_uninit(hw);
+
+ cancel_work_sync(&hw->set_clk_work);
+#ifdef MULTI_INSTANCE_SUPPORT
+ if (hw->m_ins_flag) {
+ cancel_work_sync(&hw->work);
+ } else
+ amhevc_disable();
+#else
+ amhevc_disable();
+#endif
+ uninit_mmu_buffers(hw);
+
+ vfree(hw->fw);
+ hw->fw = NULL;
+ return 0;
+}
+static int amvdec_av1_mmu_init(struct AV1HW_s *hw)
+{
+ int tvp_flag = vdec_secure(hw_to_vdec(hw)) ?
+ CODEC_MM_FLAGS_TVP : 0;
+ int buf_size = 48;
+
+ if ((hw->max_pic_w * hw->max_pic_h > 1280*736) &&
+ (hw->max_pic_w * hw->max_pic_h <= 1920*1088)) {
+ buf_size = 12;
+ } else if ((hw->max_pic_w * hw->max_pic_h > 0) &&
+ (hw->max_pic_w * hw->max_pic_h <= 1280*736)) {
+ buf_size = 4;
+ }
+ hw->need_cache_size = buf_size * SZ_1M;
+ hw->sc_start_time = get_jiffies_64();
+ if (hw->mmu_enable && ((hw->double_write_mode & 0x10) == 0)) {
+ int count = FRAME_BUFFERS;
+ hw->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME,
+ hw->index /* * 2*/, count,
+ hw->need_cache_size,
+ tvp_flag
+ );
+ if (!hw->mmu_box) {
+ pr_err("av1 alloc mmu box failed!!\n");
+ return -1;
+ }
+#ifdef AOM_AV1_MMU_DW
+ if (hw->dw_mmu_enable) {
+ hw->mmu_box_dw = decoder_mmu_box_alloc_box(DRIVER_NAME,
+ hw->index /** 2 + 1*/, count,
+ hw->need_cache_size,
+ tvp_flag
+ );
+ if (!hw->mmu_box_dw) {
+ pr_err("av1 alloc dw mmu box failed!!\n");
+ return -1;
+ }
+ }
+#endif
+
+ }
+ hw->bmmu_box = decoder_bmmu_box_alloc_box(
+ DRIVER_NAME,
+ hw->index,
+ MAX_BMMU_BUFFER_NUM,
+ 4 + PAGE_SHIFT,
+ CODEC_MM_FLAGS_CMA_CLEAR |
+ CODEC_MM_FLAGS_FOR_VDECODER |
+ tvp_flag);
+ av1_print(hw, VP9_DEBUG_BUFMGR,
+ "%s, MAX_BMMU_BUFFER_NUM = %d\n",
+ __func__,
+ MAX_BMMU_BUFFER_NUM);
+ if (!hw->bmmu_box) {
+ pr_err("av1 alloc bmmu box failed!!\n");
+ return -1;
+ }
+ return 0;
+}
+
+static struct AV1HW_s *gHevc;
+
+
+static int amvdec_av1_probe(struct platform_device *pdev)
+{
+ struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
+ struct BUF_s BUF[MAX_BUF_NUM];
+ struct AV1HW_s *hw;
+ AV1Decoder *pbi;
+ int ret;
+#ifndef MULTI_INSTANCE_SUPPORT
+ int i;
+#endif
+ pr_debug("%s\n", __func__);
+
+ mutex_lock(&vav1_mutex);
+ hw = vmalloc(sizeof(struct AV1HW_s));
+ if (hw == NULL) {
+ av1_print(hw, 0, "\namvdec_av1 device data allocation failed\n");
+ mutex_unlock(&vav1_mutex);
+ return -ENOMEM;
+ }
+
+ gHevc = hw;
+ memcpy(&BUF[0], &hw->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
+ memset(hw, 0, sizeof(struct AV1HW_s));
+ memcpy(&hw->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
+
+ if (init_dblk_struc(hw) < 0) {
+ av1_print(hw, 0, "\nammvdec_av1 device data allocation failed\n");
+ vfree(hw);
+ return -ENOMEM;
+ }
+
+ pbi = av1_decoder_create(&hw->av1_buffer_pool); //&aom_decoder;
+ hw->pbi = pbi;
+ if (hw->pbi == NULL) {
+ pr_info("\nammvdec_av1 device data allocation failed\n");
+ release_dblk_struct(hw);
+ vfree(hw);
+ return -ENOMEM;
+ }
+ //hw->pbi->common.buffer_pool = &hw->av1_buffer_pool; //????
+ hw->pbi->private_data = hw;
+
+ hw->init_flag = 0;
+ hw->first_sc_checked= 0;
+ if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
+ av1_max_pic_w = 8192;
+ av1_max_pic_h = 4608;
+ }
+ hw->max_pic_w = av1_max_pic_w;
+ hw->max_pic_h = av1_max_pic_h;
+
+#ifdef MULTI_INSTANCE_SUPPORT
+ hw->eos = 0;
+ hw->start_process_time = 0;
+ hw->timeout_num = 0;
+#endif
+ hw->fatal_error = 0;
+ hw->show_frame_num = 0;
+ if (pdata == NULL) {
+ av1_print(hw, 0, "\namvdec_av1 memory resource undefined.\n");
+ vfree(hw);
+ mutex_unlock(&vav1_mutex);
+ return -EFAULT;
+ }
+ hw->m_ins_flag = 0;
+#ifdef MULTI_INSTANCE_SUPPORT
+ hw->platform_dev = pdev;
+ platform_set_drvdata(pdev, pdata);
+#endif
+ hw->double_write_mode = double_write_mode;
+ hw->mmu_enable = 1;
+#ifdef AOM_AV1_MMU_DW
+ hw->dw_mmu_enable =
+ get_double_write_mode_init(hw) & 0x20 ? 1 : 0;
+#endif
+ if (amvdec_av1_mmu_init(hw) < 0) {
+ vfree(hw);
+ mutex_unlock(&vav1_mutex);
+ pr_err("av1 alloc bmmu box failed!!\n");
+ return -1;
+ }
+
+ ret = decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, WORK_SPACE_BUF_ID,
+ work_buf_size, DRIVER_NAME, &pdata->mem_start);
+ if (ret < 0) {
+ uninit_mmu_buffers(hw);
+ vfree(hw);
+ mutex_unlock(&vav1_mutex);
+ return ret;
+ }
+ hw->buf_size = work_buf_size;
+
+#ifdef MULTI_INSTANCE_SUPPORT
+ hw->buf_start = pdata->mem_start;
+#else
+ if (!hw->mmu_enable)
+ hw->mc_buf_spec.buf_end = pdata->mem_start + hw->buf_size;
+
+ for (i = 0; i < WORK_BUF_SPEC_NUM; i++)
+ aom_workbuff_spec[i].start_adr = pdata->mem_start;
+#endif
+
+
+ if (debug) {
+ av1_print(hw, AOM_DEBUG_HW_MORE, "===AV1 decoder mem resource 0x%lx size 0x%x\n",
+ pdata->mem_start, hw->buf_size);
+ }
+
+ if (pdata->sys_info)
+ hw->vav1_amstream_dec_info = *pdata->sys_info;
+ else {
+ hw->vav1_amstream_dec_info.width = 0;
+ hw->vav1_amstream_dec_info.height = 0;
+ hw->vav1_amstream_dec_info.rate = 30;
+ }
+ hw->no_head = no_head;
+#ifdef MULTI_INSTANCE_SUPPORT
+ hw->cma_dev = pdata->cma_dev;
+#else
+ cma_dev = pdata->cma_dev;
+#endif
+
+#ifdef MULTI_INSTANCE_SUPPORT
+ pdata->private = hw;
+ pdata->dec_status = vav1_dec_status;
+ pdata->set_isreset = vav1_set_isreset;
+ is_reset = 0;
+ if (vav1_init(pdata) < 0) {
+#else
+ if (vav1_init(hw) < 0) {
+#endif
+ av1_print(hw, 0, "\namvdec_av1 init failed.\n");
+ av1_local_uninit(hw);
+ uninit_mmu_buffers(hw);
+ vfree(hw);
+ pdata->dec_status = NULL;
+ mutex_unlock(&vav1_mutex);
+ return -ENODEV;
+ }
+ /*set the max clk for smooth playing...*/
+ hevc_source_changed(VFORMAT_AV1,
+ 4096, 2048, 60);
+ mutex_unlock(&vav1_mutex);
+
+ return 0;
+}
+
+static int amvdec_av1_remove(struct platform_device *pdev)
+{
+ struct AV1HW_s *hw = gHevc;
+ struct vdec_s *vdec = hw_to_vdec(hw);
+ int i;
+
+ if (debug)
+ av1_print(hw, AOM_DEBUG_HW_MORE, "amvdec_av1_remove\n");
+
+ mutex_lock(&vav1_mutex);
+
+ vav1_stop(hw);
+
+ hevc_source_changed(VFORMAT_AV1, 0, 0, 0);
+
+ if (vdec->parallel_dec == 1) {
+ for (i = 0; i < FRAME_BUFFERS; i++) {
+ vdec->free_canvas_ex(hw->pbi->common.buffer_pool->
+ frame_bufs[i].buf.y_canvas_index, vdec->id);
+ vdec->free_canvas_ex(hw->pbi->common.buffer_pool->
+ frame_bufs[i].buf.uv_canvas_index, vdec->id);
+ }
+ }
+
+#ifdef DEBUG_PTS
+ pr_info("pts missed %ld, pts hit %ld, duration %d\n",
+ hw->pts_missed, hw->pts_hit, hw->frame_dur);
+#endif
+ vfree(hw->pbi);
+ release_dblk_struct(hw);
+ vfree(hw);
+ mutex_unlock(&vav1_mutex);
+
+ return 0;
+}
+
+/****************************************/
+#ifdef CONFIG_PM
+static int av1_suspend(struct device *dev)
+{
+ amhevc_suspend(to_platform_device(dev), dev->power.power_state);
+ return 0;
+}
+
+static int av1_resume(struct device *dev)
+{
+ amhevc_resume(to_platform_device(dev));
+ return 0;
+}
+
+static const struct dev_pm_ops av1_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(av1_suspend, av1_resume)
+};
+#endif
+
+static struct platform_driver amvdec_av1_driver = {
+ .probe = amvdec_av1_probe,
+ .remove = amvdec_av1_remove,
+ .driver = {
+ .name = DRIVER_NAME,
+#ifdef CONFIG_PM
+ .pm = &av1_pm_ops,
+#endif
+ }
+};
+
+static struct codec_profile_t amvdec_av1_profile = {
+#ifdef DEBUG_USE_VP9_DEVICE_NAME
+ .name = "vp9",
+#else
+ .name = "av1",
+#endif
+ .profile = ""
+};
+
+static struct codec_profile_t amvdec_av1_profile_mult;
+
+static unsigned char get_data_check_sum
+ (struct AV1HW_s *hw, int size)
+{
+ int jj;
+ int sum = 0;
+ u8 *data = NULL;
+
+ if (!hw->chunk->block->is_mapped)
+ data = codec_mm_vmap(hw->chunk->block->start +
+ hw->chunk->offset, size);
+ else
+ data = ((u8 *)hw->chunk->block->start_virt) +
+ hw->chunk->offset;
+
+ for (jj = 0; jj < size; jj++)
+ sum += data[jj];
+
+ if (!hw->chunk->block->is_mapped)
+ codec_mm_unmap_phyaddr(data);
+ return sum;
+}
+
+static void dump_data(struct AV1HW_s *hw, int size)
+{
+ int jj;
+ u8 *data = NULL;
+ int padding_size = hw->chunk->offset &
+ (VDEC_FIFO_ALIGN - 1);
+
+ if (!hw->chunk->block->is_mapped)
+ data = codec_mm_vmap(hw->chunk->block->start +
+ hw->chunk->offset, size);
+ else
+ data = ((u8 *)hw->chunk->block->start_virt) +
+ hw->chunk->offset;
+
+ av1_print(hw, 0, "padding: ");
+ for (jj = padding_size; jj > 0; jj--)
+ av1_print_cont(hw,
+ 0,
+ "%02x ", *(data - jj));
+ av1_print_cont(hw, 0, "data adr %p\n",
+ data);
+
+ for (jj = 0; jj < size; jj++) {
+ if ((jj & 0xf) == 0)
+ av1_print(hw,
+ 0,
+ "%06x:", jj);
+ av1_print_cont(hw,
+ 0,
+ "%02x ", data[jj]);
+ if (((jj + 1) & 0xf) == 0)
+ av1_print(hw,
+ 0,
+ "\n");
+ }
+ av1_print(hw,
+ 0,
+ "\n");
+
+ if (!hw->chunk->block->is_mapped)
+ codec_mm_unmap_phyaddr(data);
+}
+
+static void av1_work(struct work_struct *work)
+{
+ struct AV1HW_s *hw = container_of(work,
+ struct AV1HW_s, work);
+ struct vdec_s *vdec = hw_to_vdec(hw);
+ /* finished decoding one frame or error,
+ * notify vdec core to switch context
+ */
+ av1_print(hw, PRINT_FLAG_VDEC_DETAIL,
+ "%s dec_result %d %x %x %x\n",
+ __func__,
+ hw->dec_result,
+ READ_VREG(HEVC_STREAM_LEVEL),
+ READ_VREG(HEVC_STREAM_WR_PTR),
+ READ_VREG(HEVC_STREAM_RD_PTR));
+ if (((hw->dec_result == DEC_RESULT_GET_DATA) ||
+ (hw->dec_result == DEC_RESULT_GET_DATA_RETRY))
+ && (hw_to_vdec(hw)->next_status !=
+ VDEC_STATUS_DISCONNECTED)) {
+ if (!vdec_has_more_input(vdec)) {
+ hw->dec_result = DEC_RESULT_EOS;
+ vdec_schedule_work(&hw->work);
+ return;
+ }
+
+ if (hw->dec_result == DEC_RESULT_GET_DATA) {
+ av1_print(hw, PRINT_FLAG_VDEC_STATUS,
+ "%s DEC_RESULT_GET_DATA %x %x %x\n",
+ __func__,
+ READ_VREG(HEVC_STREAM_LEVEL),
+ READ_VREG(HEVC_STREAM_WR_PTR),
+ READ_VREG(HEVC_STREAM_RD_PTR));
+ vdec_vframe_dirty(vdec, hw->chunk);
+ vdec_clean_input(vdec);
+ }
+
+ if (get_free_buf_count(hw) >=
+ run_ready_min_buf_num) {
+ int r;
+ int decode_size;
+ r = vdec_prepare_input(vdec, &hw->chunk);
+ if (r < 0) {
+ hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
+
+ av1_print(hw,
+ PRINT_FLAG_VDEC_DETAIL,
+ "amvdec_vh265: Insufficient data\n");
+
+ vdec_schedule_work(&hw->work);
+ return;
+ }
+ hw->dec_result = DEC_RESULT_NONE;
+ av1_print(hw, PRINT_FLAG_VDEC_STATUS,
+ "%s: chunk size 0x%x sum 0x%x\n",
+ __func__, r,
+ (debug & PRINT_FLAG_VDEC_STATUS) ?
+ get_data_check_sum(hw, r) : 0
+ );
+
+ if (debug & PRINT_FLAG_VDEC_DATA)
+ dump_data(hw, hw->chunk->size);
+
+ decode_size = hw->chunk->size +
+ (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
+
+ WRITE_VREG(HEVC_DECODE_SIZE,
+ READ_VREG(HEVC_DECODE_SIZE) + decode_size);
+
+ vdec_enable_input(vdec);
+
+ WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
+
+ start_process_time(hw);
+
+ } else {
+ hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
+
+ av1_print(hw, PRINT_FLAG_VDEC_DETAIL,
+ "amvdec_vh265: Insufficient data\n");
+
+ vdec_schedule_work(&hw->work);
+ }
+ return;
+ } else if (hw->dec_result == DEC_RESULT_DONE) {
+ /* if (!hw->ctx_valid)
+ hw->ctx_valid = 1; */
+ hw->result_done_count++;
+ hw->process_state = PROC_STATE_INIT;
+ decode_frame_count[hw->index] = hw->frame_count;
+
+ if (hw->mmu_enable)
+ hw->used_4k_num =
+ (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
+ av1_print(hw, PRINT_FLAG_VDEC_STATUS,
+ "%s (===> %d) dec_result %d (%d) %x %x %x shiftbytes 0x%x decbytes 0x%x\n",
+ __func__,
+ hw->frame_count,
+ hw->dec_result,
+ hw->result_done_count,
+ READ_VREG(HEVC_STREAM_LEVEL),
+ READ_VREG(HEVC_STREAM_WR_PTR),
+ READ_VREG(HEVC_STREAM_RD_PTR),
+ READ_VREG(HEVC_SHIFT_BYTE_COUNT),
+ READ_VREG(HEVC_SHIFT_BYTE_COUNT) -
+ hw->start_shift_bytes
+ );
+ vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
+ } else if (hw->dec_result == DEC_RESULT_AGAIN) {
+ /*
+ stream base: stream buf empty or timeout
+ frame base: vdec_prepare_input fail
+ */
+ if (!vdec_has_more_input(vdec)) {
+ hw->dec_result = DEC_RESULT_EOS;
+ vdec_schedule_work(&hw->work);
+ return;
+ }
+ } else if (hw->dec_result == DEC_RESULT_EOS) {
+ av1_print(hw, PRINT_FLAG_VDEC_STATUS,
+ "%s: end of stream\n",
+ __func__);
+ hw->eos = 1;
+ av1_postproc(hw);
+
+ if (hw->is_used_v4l)
+ notify_v4l_eos(hw_to_vdec(hw));
+
+ vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
+ } else if (hw->dec_result == DEC_RESULT_FORCE_EXIT) {
+ av1_print(hw, PRINT_FLAG_VDEC_STATUS,
+ "%s: force exit\n",
+ __func__);
+ if (hw->stat & STAT_VDEC_RUN) {
+ amhevc_stop();
+ hw->stat &= ~STAT_VDEC_RUN;
+ }
+
+ if (hw->stat & STAT_ISR_REG) {
+#ifdef MULTI_INSTANCE_SUPPORT
+ if (!hw->m_ins_flag)
+#endif
+ WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0);
+ vdec_free_irq(VDEC_IRQ_0, (void *)hw);
+ hw->stat &= ~STAT_ISR_REG;
+ }
+ }
+ if (hw->stat & STAT_VDEC_RUN) {
+ amhevc_stop();
+ hw->stat &= ~STAT_VDEC_RUN;
+ }
+
+ if (hw->stat & STAT_TIMER_ARM) {
+ del_timer_sync(&hw->timer);
+ hw->stat &= ~STAT_TIMER_ARM;
+ }
+ /* mark itself has all HW resource released and input released */
+ if (vdec->parallel_dec == 1)
+ vdec_core_finish_run(vdec, CORE_MASK_HEVC);
+ else
+ vdec_core_finish_run(hw_to_vdec(hw), CORE_MASK_VDEC_1
+ | CORE_MASK_HEVC);
+ trigger_schedule(hw);
+}
+
+static int av1_hw_ctx_restore(struct AV1HW_s *hw)
+{
+ vav1_prot_init(hw, HW_MASK_FRONT | HW_MASK_BACK);
+ return 0;
+}
+static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask)
+{
+ struct AV1HW_s *hw =
+ (struct AV1HW_s *)vdec->private;
+ int tvp = vdec_secure(hw_to_vdec(hw)) ?
+ CODEC_MM_FLAGS_TVP : 0;
+ unsigned long ret = 0;
+
+ if (!hw->pic_list_init_done2 || hw->eos)
+ return ret;
+ if (!hw->first_sc_checked && hw->mmu_enable) {
+ int size = decoder_mmu_box_sc_check(hw->mmu_box, tvp);
+ hw->first_sc_checked = 1;
+ av1_print(hw, 0, "av1 cached=%d need_size=%d speed= %d ms\n",
+ size, (hw->need_cache_size >> PAGE_SHIFT),
+ (int)(get_jiffies_64() - hw->sc_start_time) * 1000/HZ);
+#ifdef AOM_AV1_MMU_DW
+ /*!!!!!! To do ... */
+ if (hw->dw_mmu_enable) {
+
+ }
+#endif
+ }
+
+ if (get_free_buf_count(hw) >=
+ run_ready_min_buf_num) {
+ if (vdec->parallel_dec == 1)
+ ret = CORE_MASK_HEVC;
+ else
+ ret = CORE_MASK_VDEC_1 | CORE_MASK_HEVC;
+ }
+ if (ret)
+ not_run_ready[hw->index] = 0;
+ else
+ not_run_ready[hw->index]++;
+
+ av1_print(hw,
+ PRINT_FLAG_VDEC_DETAIL, "%s mask %lx=>%lx\r\n",
+ __func__, mask, ret);
+ return ret;
+}
+
+static void run_front(struct vdec_s *vdec)
+{
+ struct AV1HW_s *hw =
+ (struct AV1HW_s *)vdec->private;
+ int ret, size;
+
+ run_count[hw->index]++;
+ /* hw->chunk = vdec_prepare_input(vdec); */
+ hevc_reset_core(vdec);
+
+ size = vdec_prepare_input(vdec, &hw->chunk);
+ if (size < 0) {
+ input_empty[hw->index]++;
+
+ hw->dec_result = DEC_RESULT_AGAIN;
+
+ av1_print(hw, PRINT_FLAG_VDEC_DETAIL,
+ "ammvdec_vh265: Insufficient data\n");
+
+ vdec_schedule_work(&hw->work);
+ return;
+ }
+ input_empty[hw->index] = 0;
+ hw->dec_result = DEC_RESULT_NONE;
+ hw->start_shift_bytes = READ_VREG(HEVC_SHIFT_BYTE_COUNT);
+
+ if (debug & PRINT_FLAG_VDEC_STATUS) {
+ /*int ii;*/
+ av1_print(hw, 0,
+ "%s (%d): size 0x%x (0x%x 0x%x) sum 0x%x (%x %x %x %x %x) bytes 0x%x\n",
+ __func__,
+ hw->frame_count, size,
+ hw->chunk ? hw->chunk->size : 0,
+ hw->chunk ? hw->chunk->offset : 0,
+ hw->chunk ? ((vdec_frame_based(vdec) &&
+ (debug & PRINT_FLAG_VDEC_STATUS)) ?
+ get_data_check_sum(hw, size) : 0) : 0,
+ READ_VREG(HEVC_STREAM_START_ADDR),
+ READ_VREG(HEVC_STREAM_END_ADDR),
+ READ_VREG(HEVC_STREAM_LEVEL),
+ READ_VREG(HEVC_STREAM_WR_PTR),
+ READ_VREG(HEVC_STREAM_RD_PTR),
+ hw->start_shift_bytes);
+#if 0
+ if (vdec_frame_based(vdec) && hw->chunk) {
+ u8 *data = NULL;
+
+ if (!hw->chunk->block->is_mapped)
+ data = codec_mm_vmap(hw->chunk->block->start +
+ hw->chunk->offset, 8);
+ else
+ data = ((u8 *)hw->chunk->block->start_virt) +
+ hw->chunk->offset;
+
+ av1_print_cont(hw, 0, "data adr %p:",
+ data);
+ for (ii = 0; ii < 8; ii++)
+ av1_print_cont(hw, 0, "%02x ",
+ data[ii]);
+
+ if (!hw->chunk->block->is_mapped)
+ codec_mm_unmap_phyaddr(data);
+ }
+ av1_print_cont(hw, 0, "\r\n");
+#endif
+ }
+ if (vdec->mc_loaded) {
+ /*firmware have load before,
+ and not changes to another.
+ ignore reload.
+ */
+ } else {
+#ifdef DEBUG_USE_VP9_DEVICE_NAME
+ ret = amhevc_loadmc_ex(VFORMAT_AV1, NULL, hw->fw->data);
+#else
+ ret = amhevc_loadmc_ex(VFORMAT_VP9, NULL, hw->fw->data);
+#endif
+ if (ret < 0) {
+ amhevc_disable();
+ av1_print(hw, PRINT_FLAG_ERROR,
+ "AV1: the %s fw loading failed, err: %x\n",
+ tee_enabled() ? "TEE" : "local", ret);
+ hw->dec_result = DEC_RESULT_FORCE_EXIT;
+ vdec_schedule_work(&hw->work);
+ return;
+ }
+ vdec->mc_loaded = 1;
+#ifdef DEBUG_USE_VP9_DEVICE_NAME
+ vdec->mc_type = VFORMAT_AV1;
+#else
+ vdec->mc_type = VFORMAT_VP9;
+#endif
+ }
+
+ if (av1_hw_ctx_restore(hw) < 0) {
+ vdec_schedule_work(&hw->work);
+ return;
+ }
+
+ vdec_enable_input(vdec);
+
+ WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
+
+ if (vdec_frame_based(vdec)) {
+ if (debug & PRINT_FLAG_VDEC_DATA)
+ dump_data(hw, hw->chunk->size);
+
+ WRITE_VREG(HEVC_SHIFT_BYTE_COUNT, 0);
+ size = hw->chunk->size +
+ (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
+ }
+ WRITE_VREG(HEVC_DECODE_SIZE, size);
+ WRITE_VREG(HEVC_DECODE_COUNT, hw->result_done_count);
+ WRITE_VREG(LMEM_DUMP_ADR, (u32)hw->lmem_phy_addr);
+ if (hw->config_next_ref_info_flag)
+ config_next_ref_info_hw(hw);
+ hw->config_next_ref_info_flag = 0;
+ hw->init_flag = 1;
+
+ av1_print(hw, PRINT_FLAG_VDEC_DETAIL,
+ "%s: start hevc (%x %x %x) HEVC_DECODE_SIZE 0x%x\n",
+ __func__,
+ READ_VREG(HEVC_DEC_STATUS_REG),
+ READ_VREG(HEVC_MPC_E),
+ READ_VREG(HEVC_MPSR),
+ READ_VREG(HEVC_DECODE_SIZE));
+
+ start_process_time(hw);
+ mod_timer(&hw->timer, jiffies);
+ hw->stat |= STAT_TIMER_ARM;
+ hw->stat |= STAT_ISR_REG;
+ amhevc_start();
+ hw->stat |= STAT_VDEC_RUN;
+}
+
+static void run(struct vdec_s *vdec, unsigned long mask,
+ void (*callback)(struct vdec_s *, void *), void *arg)
+{
+ struct AV1HW_s *hw =
+ (struct AV1HW_s *)vdec->private;
+
+ av1_print(hw,
+ PRINT_FLAG_VDEC_DETAIL, "%s mask %lx\r\n",
+ __func__, mask);
+
+ run_count[hw->index]++;
+ hw->vdec_cb_arg = arg;
+ hw->vdec_cb = callback;
+ run_front(vdec);
+}
+
+static void reset(struct vdec_s *vdec)
+{
+
+ struct AV1HW_s *hw =
+ (struct AV1HW_s *)vdec->private;
+
+ av1_print(hw,
+ PRINT_FLAG_VDEC_DETAIL, "%s\r\n", __func__);
+
+}
+
+static irqreturn_t av1_irq_cb(struct vdec_s *vdec, int irq)
+{
+ struct AV1HW_s *hw =
+ (struct AV1HW_s *)vdec->private;
+ return vav1_isr(0, hw);
+}
+
+static irqreturn_t av1_threaded_irq_cb(struct vdec_s *vdec, int irq)
+{
+ struct AV1HW_s *hw =
+ (struct AV1HW_s *)vdec->private;
+ return vav1_isr_thread_fn(0, hw);
+}
+
+static void av1_dump_state(struct vdec_s *vdec)
+{
+ struct AV1HW_s *hw =
+ (struct AV1HW_s *)vdec->private;
+ struct AV1_Common_s *const cm = &hw->pbi->common;
+ int i;
+ av1_print(hw, 0, "====== %s\n", __func__);
+
+ av1_print(hw, 0,
+ "width/height (%d/%d), used_buf_num %d\n",
+ cm->width,
+ cm->height,
+ hw->used_buf_num
+ );
+
+ av1_print(hw, 0,
+ "is_framebase(%d), eos %d, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d low_latency %d no_head %d \n",
+ input_frame_based(vdec),
+ hw->eos,
+ hw->dec_result,
+ decode_frame_count[hw->index],
+ display_frame_count[hw->index],
+ run_count[hw->index],
+ not_run_ready[hw->index],
+ input_empty[hw->index],
+ hw->low_latency_flag,
+ hw->no_head
+ );
+
+ if (vf_get_receiver(vdec->vf_provider_name)) {
+ enum receviver_start_e state =
+ vf_notify_receiver(vdec->vf_provider_name,
+ VFRAME_EVENT_PROVIDER_QUREY_STATE,
+ NULL);
+ av1_print(hw, 0,
+ "\nreceiver(%s) state %d\n",
+ vdec->vf_provider_name,
+ state);
+ }
+
+ av1_print(hw, 0,
+ "%s, newq(%d/%d), dispq(%d/%d), vf prepare/get/put (%d/%d/%d), free_buf_count %d (min %d for run_ready)\n",
+ __func__,
+ kfifo_len(&hw->newframe_q),
+ VF_POOL_SIZE,
+ kfifo_len(&hw->display_q),
+ VF_POOL_SIZE,
+ hw->vf_pre_count,
+ hw->vf_get_count,
+ hw->vf_put_count,
+ get_free_buf_count(hw),
+ run_ready_min_buf_num
+ );
+
+ dump_pic_list(hw);
+
+ for (i = 0; i < MAX_BUF_NUM; i++) {
+ av1_print(hw, 0,
+ "mv_Buf(%d) start_adr 0x%x size 0x%x used %d\n",
+ i,
+ hw->m_mv_BUF[i].start_adr,
+ hw->m_mv_BUF[i].size,
+ hw->m_mv_BUF[i].used_flag);
+ }
+
+ av1_print(hw, 0,
+ "HEVC_DEC_STATUS_REG=0x%x\n",
+ READ_VREG(HEVC_DEC_STATUS_REG));
+ av1_print(hw, 0,
+ "HEVC_MPC_E=0x%x\n",
+ READ_VREG(HEVC_MPC_E));
+ av1_print(hw, 0,
+ "DECODE_MODE=0x%x\n",
+ READ_VREG(DECODE_MODE));
+ av1_print(hw, 0,
+ "NAL_SEARCH_CTL=0x%x\n",
+ READ_VREG(NAL_SEARCH_CTL));
+ av1_print(hw, 0,
+ "HEVC_PARSER_LCU_START=0x%x\n",
+ READ_VREG(HEVC_PARSER_LCU_START));
+ av1_print(hw, 0,
+ "HEVC_DECODE_SIZE=0x%x\n",
+ READ_VREG(HEVC_DECODE_SIZE));
+ av1_print(hw, 0,
+ "HEVC_SHIFT_BYTE_COUNT=0x%x\n",
+ READ_VREG(HEVC_SHIFT_BYTE_COUNT));
+ av1_print(hw, 0,
+ "HEVC_STREAM_START_ADDR=0x%x\n",
+ READ_VREG(HEVC_STREAM_START_ADDR));
+ av1_print(hw, 0,
+ "HEVC_STREAM_END_ADDR=0x%x\n",
+ READ_VREG(HEVC_STREAM_END_ADDR));
+ av1_print(hw, 0,
+ "HEVC_STREAM_LEVEL=0x%x\n",
+ READ_VREG(HEVC_STREAM_LEVEL));
+ av1_print(hw, 0,
+ "HEVC_STREAM_WR_PTR=0x%x\n",
+ READ_VREG(HEVC_STREAM_WR_PTR));
+ av1_print(hw, 0,
+ "HEVC_STREAM_RD_PTR=0x%x\n",
+ READ_VREG(HEVC_STREAM_RD_PTR));
+ av1_print(hw, 0,
+ "PARSER_VIDEO_RP=0x%x\n",
+ READ_PARSER_REG(PARSER_VIDEO_RP));
+ av1_print(hw, 0,
+ "PARSER_VIDEO_WP=0x%x\n",
+ READ_PARSER_REG(PARSER_VIDEO_WP));
+
+ if (input_frame_based(vdec) &&
+ (debug & PRINT_FLAG_VDEC_DATA)
+ ) {
+ int jj;
+ if (hw->chunk && hw->chunk->block &&
+ hw->chunk->size > 0) {
+ u8 *data = NULL;
+
+ if (!hw->chunk->block->is_mapped)
+ data = codec_mm_vmap(
+ hw->chunk->block->start +
+ hw->chunk->offset,
+ hw->chunk->size);
+ else
+ data = ((u8 *)hw->chunk->block->start_virt)
+ + hw->chunk->offset;
+ av1_print(hw, 0,
+ "frame data size 0x%x\n",
+ hw->chunk->size);
+ for (jj = 0; jj < hw->chunk->size; jj++) {
+ if ((jj & 0xf) == 0)
+ av1_print(hw, 0,
+ "%06x:", jj);
+ av1_print_cont(hw, 0,
+ "%02x ", data[jj]);
+ if (((jj + 1) & 0xf) == 0)
+ av1_print_cont(hw, 0,
+ "\n");
+ }
+
+ if (!hw->chunk->block->is_mapped)
+ codec_mm_unmap_phyaddr(data);
+ }
+ }
+
+}
+
+static int ammvdec_av1_probe(struct platform_device *pdev)
+{
+ struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
+ int ret;
+ int config_val;
+ struct vframe_content_light_level_s content_light_level;
+ struct vframe_master_display_colour_s vf_dp;
+
+ struct BUF_s BUF[MAX_BUF_NUM];
+ struct AV1HW_s *hw = NULL;
+ pr_debug("%s\n", __func__);
+
+ if (pdata == NULL) {
+ av1_print(hw, 0, "\nammvdec_av1 memory resource undefined.\n");
+ return -EFAULT;
+ }
+ /*hw = (struct AV1HW_s *)devm_kzalloc(&pdev->dev,
+ sizeof(struct AV1HW_s), GFP_KERNEL);*/
+ memset(&vf_dp, 0, sizeof(struct vframe_master_display_colour_s));
+ hw = vmalloc(sizeof(struct AV1HW_s));
+ if (hw == NULL) {
+ av1_print(hw, 0, "\nammvdec_av1 device data allocation failed\n");
+ return -ENOMEM;
+ }
+ memset(hw, 0, sizeof(struct AV1HW_s));
+
+ if (init_dblk_struc(hw) < 0) {
+ av1_print(hw, 0, "\nammvdec_av1 device data allocation failed\n");
+ vfree(hw);
+ return -ENOMEM;
+ }
+
+ hw->pbi = av1_decoder_create(&hw->av1_buffer_pool); //&aom_decoder;
+ if (hw->pbi == NULL) {
+ av1_print(hw, 0, "\nammvdec_av1 device data allocation failed\n");
+ release_dblk_struct(hw);
+ vfree(hw);
+ return -ENOMEM;
+ }
+
+ hw->pbi->common.buffer_pool = &hw->av1_buffer_pool; //????????
+ hw->pbi->private_data = hw;
+ /* the ctx from v4l2 driver. */
+ hw->v4l2_ctx = pdata->private;
+
+ pdata->private = hw;
+ pdata->dec_status = vav1_dec_status;
+ /* pdata->set_trickmode = set_trickmode; */
+ pdata->run_ready = run_ready;
+ pdata->run = run;
+ pdata->reset = reset;
+ pdata->irq_handler = av1_irq_cb;
+ pdata->threaded_irq_handler = av1_threaded_irq_cb;
+ pdata->dump_state = av1_dump_state;
+
+ memcpy(&BUF[0], &hw->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
+ memcpy(&hw->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
+
+ hw->index = pdev->id;
+
+ if (pdata->use_vfm_path)
+ snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
+ VFM_DEC_PROVIDER_NAME);
+ else
+ snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
+ MULTI_INSTANCE_PROVIDER_NAME ".%02x", pdev->id & 0xff);
+
+ vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
+ &vav1_vf_provider, hw);
+
+ hw->provider_name = pdata->vf_provider_name;
+ platform_set_drvdata(pdev, pdata);
+
+ hw->platform_dev = pdev;
+ hw->video_signal_type = 0;
+ hw->m_ins_flag = 1;
+ if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX)
+ hw->stat |= VP9_TRIGGER_FRAME_ENABLE;
+
+ if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
+ hw->max_pic_w = 8192;
+ hw->max_pic_h = 4608;
+ } else {
+ hw->max_pic_w = 4096;
+ hw->max_pic_h = 2304;
+ }
+#if 1
+ if ((debug & IGNORE_PARAM_FROM_CONFIG) == 0 &&
+ pdata->config_len) {
+#ifdef MULTI_INSTANCE_SUPPORT
+ int av1_buf_width = 0;
+ int av1_buf_height = 0;
+ /*use ptr config for doubel_write_mode, etc*/
+ av1_print(hw, 0, "pdata->config=%s\n", pdata->config);
+ if (get_config_int(pdata->config, "av1_double_write_mode",
+ &config_val) == 0)
+ hw->double_write_mode = config_val;
+ else
+ hw->double_write_mode = double_write_mode;
+
+ if (get_config_int(pdata->config, "save_buffer_mode",
+ &config_val) == 0)
+ hw->save_buffer_mode = config_val;
+ else
+ hw->save_buffer_mode = 0;
+ if (get_config_int(pdata->config, "av1_buf_width",
+ &config_val) == 0) {
+ av1_buf_width = config_val;
+ }
+ if (get_config_int(pdata->config, "av1_buf_height",
+ &config_val) == 0) {
+ av1_buf_height = config_val;
+ }
+
+ if (get_config_int(pdata->config, "no_head",
+ &config_val) == 0)
+ hw->no_head = config_val;
+ else
+ hw->no_head = no_head;
+
+ /*use ptr config for max_pic_w, etc*/
+ if (get_config_int(pdata->config, "av1_max_pic_w",
+ &config_val) == 0) {
+ hw->max_pic_w = config_val;
+ }
+ if (get_config_int(pdata->config, "av1_max_pic_h",
+ &config_val) == 0) {
+ hw->max_pic_h = config_val;
+ }
+ if ((hw->max_pic_w * hw->max_pic_h)
+ < (av1_buf_width * av1_buf_height)) {
+ hw->max_pic_w = av1_buf_width;
+ hw->max_pic_h = av1_buf_height;
+ av1_print(hw, 0, "use buf resolution\n");
+ }
+#endif
+ if (get_config_int(pdata->config, "HDRStaticInfo",
+ &vf_dp.present_flag) == 0
+ && vf_dp.present_flag == 1) {
+ get_config_int(pdata->config, "mG.x",
+ &vf_dp.primaries[0][0]);
+ get_config_int(pdata->config, "mG.y",
+ &vf_dp.primaries[0][1]);
+ get_config_int(pdata->config, "mB.x",
+ &vf_dp.primaries[1][0]);
+ get_config_int(pdata->config, "mB.y",
+ &vf_dp.primaries[1][1]);
+ get_config_int(pdata->config, "mR.x",
+ &vf_dp.primaries[2][0]);
+ get_config_int(pdata->config, "mR.y",
+ &vf_dp.primaries[2][1]);
+ get_config_int(pdata->config, "mW.x",
+ &vf_dp.white_point[0]);
+ get_config_int(pdata->config, "mW.y",
+ &vf_dp.white_point[1]);
+ get_config_int(pdata->config, "mMaxDL",
+ &vf_dp.luminance[0]);
+ get_config_int(pdata->config, "mMinDL",
+ &vf_dp.luminance[1]);
+ vf_dp.content_light_level.present_flag = 1;
+ get_config_int(pdata->config, "mMaxCLL",
+ &content_light_level.max_content);
+ get_config_int(pdata->config, "mMaxFALL",
+ &content_light_level.max_pic_average);
+ vf_dp.content_light_level = content_light_level;
+ hw->video_signal_type = (1 << 29)
+ | (5 << 26) /* unspecified */
+ | (0 << 25) /* limit */
+ | (1 << 24) /* color available */
+ | (9 << 16) /* 2020 */
+ | (16 << 8) /* 2084 */
+ | (9 << 0); /* 2020 */
+ }
+ hw->vf_dp = vf_dp;
+ } else
+#endif
+ {
+ /*hw->vav1_amstream_dec_info.width = 0;
+ hw->vav1_amstream_dec_info.height = 0;
+ hw->vav1_amstream_dec_info.rate = 30;*/
+ hw->double_write_mode = double_write_mode;
+ }
+ if (is_oversize(hw->max_pic_w, hw->max_pic_h)) {
+ pr_err("over size: %dx%d, probe failed\n",
+ hw->max_pic_w, hw->max_pic_h);
+ return -1;
+ }
+ hw->mmu_enable = 1;
+ video_signal_type = hw->video_signal_type;
+
+ if (pdata->sys_info) {
+ hw->vav1_amstream_dec_info = *pdata->sys_info;
+ if ((unsigned long) hw->vav1_amstream_dec_info.param
+ & 0x08) {
+ hw->low_latency_flag = 1;
+ } else
+ hw->low_latency_flag = 0;
+ } else {
+ hw->vav1_amstream_dec_info.width = 0;
+ hw->vav1_amstream_dec_info.height = 0;
+ hw->vav1_amstream_dec_info.rate = 30;
+ }
+
+ hw->is_used_v4l = (((unsigned long)
+ hw->vav1_amstream_dec_info.param & 0x80) >> 7);
+ if (hw->is_used_v4l) {
+ hw->double_write_mode = 0x10;
+ hw->mmu_enable = 0;
+ hw->max_pic_w = 1920;
+ hw->max_pic_h = 1080;
+ }
+#ifdef AOM_AV1_MMU_DW
+ hw->dw_mmu_enable =
+ get_double_write_mode_init(hw) & 0x20 ? 1 : 0;
+
+#endif
+ av1_print(hw, 0,
+ "no_head %d low_latency %d\n",
+ hw->no_head, hw->low_latency_flag);
+#if 0
+ hw->buf_start = pdata->mem_start;
+ hw->buf_size = pdata->mem_end - pdata->mem_start + 1;
+#else
+ if (amvdec_av1_mmu_init(hw) < 0) {
+ pr_err("av1 alloc bmmu box failed!!\n");
+ /* devm_kfree(&pdev->dev, (void *)hw); */
+ vfree((void *)hw);
+ pdata->dec_status = NULL;
+ return -1;
+ }
+
+ hw->cma_alloc_count = PAGE_ALIGN(work_buf_size) / PAGE_SIZE;
+ ret = decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, WORK_SPACE_BUF_ID,
+ hw->cma_alloc_count * PAGE_SIZE, DRIVER_NAME,
+ &hw->cma_alloc_addr);
+ if (ret < 0) {
+ uninit_mmu_buffers(hw);
+ /* devm_kfree(&pdev->dev, (void *)hw); */
+ vfree((void *)hw);
+ pdata->dec_status = NULL;
+ return ret;
+ }
+ hw->buf_start = hw->cma_alloc_addr;
+ hw->buf_size = work_buf_size;
+#endif
+
+ hw->init_flag = 0;
+ hw->first_sc_checked = 0;
+ hw->fatal_error = 0;
+ hw->show_frame_num = 0;
+
+ if (debug) {
+ av1_print(hw, AOM_DEBUG_HW_MORE, "===AV1 decoder mem resource 0x%lx size 0x%x\n",
+ hw->buf_start,
+ hw->buf_size);
+ }
+
+ hw->cma_dev = pdata->cma_dev;
+ if (vav1_init(pdata) < 0) {
+ av1_print(hw, 0, "\namvdec_av1 init failed.\n");
+ av1_local_uninit(hw);
+ uninit_mmu_buffers(hw);
+ /* devm_kfree(&pdev->dev, (void *)hw); */
+ vfree((void *)hw);
+ pdata->dec_status = NULL;
+ return -ENODEV;
+ }
+ vdec_set_prepare_level(pdata, start_decode_buf_level);
+ hevc_source_changed(VFORMAT_AV1,
+ 4096, 2048, 60);
+
+ if (pdata->parallel_dec == 1)
+ vdec_core_request(pdata, CORE_MASK_HEVC);
+ else
+ vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
+ | CORE_MASK_COMBINE);
+
+ hw->pic_list_init_done2 = true;
+ return 0;
+}
+
+static int ammvdec_av1_remove(struct platform_device *pdev)
+{
+ struct AV1HW_s *hw = (struct AV1HW_s *)
+ (((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
+ struct vdec_s *vdec = hw_to_vdec(hw);
+ int i;
+ if (debug)
+ av1_print(hw, AOM_DEBUG_HW_MORE, "amvdec_av1_remove\n");
+
+ vmav1_stop(hw);
+
+ if (vdec->parallel_dec == 1)
+ vdec_core_release(hw_to_vdec(hw), CORE_MASK_HEVC);
+ else
+ vdec_core_release(hw_to_vdec(hw), CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
+
+ vdec_set_status(hw_to_vdec(hw), VDEC_STATUS_DISCONNECTED);
+
+ if (vdec->parallel_dec == 1) {
+ for (i = 0; i < FRAME_BUFFERS; i++) {
+ vdec->free_canvas_ex
+ (hw->pbi->common.buffer_pool->frame_bufs[i].buf.y_canvas_index,
+ vdec->id);
+ vdec->free_canvas_ex
+ (hw->pbi->common.buffer_pool->frame_bufs[i].buf.uv_canvas_index,
+ vdec->id);
+ }
+ }
+
+
+#ifdef DEBUG_PTS
+ pr_info("pts missed %ld, pts hit %ld, duration %d\n",
+ hw->pts_missed, hw->pts_hit, hw->frame_dur);
+#endif
+ /* devm_kfree(&pdev->dev, (void *)hw); */
+ vfree(hw->pbi);
+ release_dblk_struct(hw);
+ vfree((void *)hw);
+ return 0;
+}
+
+static struct platform_driver ammvdec_av1_driver = {
+ .probe = ammvdec_av1_probe,
+ .remove = ammvdec_av1_remove,
+ .driver = {
+ .name = MULTI_DRIVER_NAME,
+#ifdef CONFIG_PM
+ .pm = &av1_pm_ops,
+#endif
+ }
+};
+#endif
+static struct mconfig av1_configs[] = {
+ MC_PU32("bit_depth_luma", &bit_depth_luma),
+ MC_PU32("bit_depth_chroma", &bit_depth_chroma),
+ MC_PU32("frame_width", &frame_width),
+ MC_PU32("frame_height", &frame_height),
+ MC_PU32("debug", &debug),
+ MC_PU32("radr", &radr),
+ MC_PU32("rval", &rval),
+ MC_PU32("pop_shorts", &pop_shorts),
+ MC_PU32("dbg_cmd", &dbg_cmd),
+ MC_PU32("dbg_skip_decode_index", &dbg_skip_decode_index),
+ MC_PU32("endian", &endian),
+ MC_PU32("step", &step),
+ MC_PU32("udebug_flag", &udebug_flag),
+ MC_PU32("decode_pic_begin", &decode_pic_begin),
+ MC_PU32("slice_parse_begin", &slice_parse_begin),
+ MC_PU32("i_only_flag", &i_only_flag),
+ MC_PU32("error_handle_policy", &error_handle_policy),
+ MC_PU32("buf_alloc_width", &buf_alloc_width),
+ MC_PU32("buf_alloc_height", &buf_alloc_height),
+ MC_PU32("buf_alloc_depth", &buf_alloc_depth),
+ MC_PU32("buf_alloc_size", &buf_alloc_size),
+ MC_PU32("buffer_mode", &buffer_mode),
+ MC_PU32("buffer_mode_dbg", &buffer_mode_dbg),
+ MC_PU32("max_buf_num", &max_buf_num),
+ MC_PU32("dynamic_buf_num_margin", &dynamic_buf_num_margin),
+ MC_PU32("mem_map_mode", &mem_map_mode),
+ MC_PU32("double_write_mode", &double_write_mode),
+ MC_PU32("enable_mem_saving", &enable_mem_saving),
+ MC_PU32("force_w_h", &force_w_h),
+ MC_PU32("force_fps", &force_fps),
+ MC_PU32("max_decoding_time", &max_decoding_time),
+ MC_PU32("on_no_keyframe_skiped", &on_no_keyframe_skiped),
+ MC_PU32("start_decode_buf_level", &start_decode_buf_level),
+ MC_PU32("decode_timeout_val", &decode_timeout_val),
+ MC_PU32("av1_max_pic_w", &av1_max_pic_w),
+ MC_PU32("av1_max_pic_h", &av1_max_pic_h),
+};
+static struct mconfig_node av1_node;
+
+static int __init amvdec_av1_driver_init_module(void)
+{
+
+ struct BuffInfo_s *p_buf_info;
+#ifdef BUFMGR_ONLY_OLD_CHIP
+ debug |= AOM_DEBUG_BUFMGR_ONLY;
+#endif
+
+ if (vdec_is_support_4k()) {
+ if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
+ p_buf_info = &aom_workbuff_spec[1];
+ else
+ p_buf_info = &aom_workbuff_spec[1];
+ } else
+ p_buf_info = &aom_workbuff_spec[0];
+
+ init_buff_spec(NULL, p_buf_info);
+ work_buf_size =
+ (p_buf_info->end_adr - p_buf_info->start_adr
+ + 0xffff) & (~0xffff);
+
+ pr_debug("amvdec_av1 module init\n");
+
+ error_handle_policy = 0;
+
+#ifdef ERROR_HANDLE_DEBUG
+ dbg_nal_skip_flag = 0;
+ dbg_nal_skip_count = 0;
+#endif
+ udebug_flag = 0;
+ decode_pic_begin = 0;
+ slice_parse_begin = 0;
+ step = 0;
+ buf_alloc_size = 0;
+#ifdef MULTI_INSTANCE_SUPPORT
+ if (platform_driver_register(&ammvdec_av1_driver))
+ pr_err("failed to register ammvdec_av1 driver\n");
+
+#endif
+ if (platform_driver_register(&amvdec_av1_driver)) {
+ pr_err("failed to register amvdec_av1 driver\n");
+ return -ENODEV;
+ }
+
+ if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TM2) {
+ amvdec_av1_profile.profile =
+ "4k, 10bit, dwrite, compressed, no_head";
+ } else {
+ amvdec_av1_profile.name = "av1_unsupport";
+ }
+
+ if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A)
+ max_buf_num = MAX_BUF_NUM_LESS;
+
+ vcodec_profile_register(&amvdec_av1_profile);
+ amvdec_av1_profile_mult = amvdec_av1_profile;
+#ifdef DEBUG_USE_VP9_DEVICE_NAME
+
+ amvdec_av1_profile_mult.name = "mav1";
+ vcodec_profile_register(&amvdec_av1_profile_mult);
+ INIT_REG_NODE_CONFIGS("media.decoder", &av1_node,
+ "av1", av1_configs, CONFIG_FOR_RW);
+
+#else
+ amvdec_av1_profile_mult.name = "mav1";
+ vcodec_profile_register(&amvdec_av1_profile_mult);
+ INIT_REG_NODE_CONFIGS("media.decoder", &av1_node,
+ "av1", av1_configs, CONFIG_FOR_RW);
+#endif
+
+ return 0;
+}
+
+static void __exit amvdec_av1_driver_remove_module(void)
+{
+ pr_debug("amvdec_av1 module remove.\n");
+#ifdef MULTI_INSTANCE_SUPPORT
+ platform_driver_unregister(&ammvdec_av1_driver);
+#endif
+ platform_driver_unregister(&amvdec_av1_driver);
+}
+
+/****************************************/
+
+module_param(bit_depth_luma, uint, 0664);
+MODULE_PARM_DESC(bit_depth_luma, "\n amvdec_av1 bit_depth_luma\n");
+
+module_param(bit_depth_chroma, uint, 0664);
+MODULE_PARM_DESC(bit_depth_chroma, "\n amvdec_av1 bit_depth_chroma\n");
+
+module_param(frame_width, uint, 0664);
+MODULE_PARM_DESC(frame_width, "\n amvdec_av1 frame_width\n");
+
+module_param(frame_height, uint, 0664);
+MODULE_PARM_DESC(frame_height, "\n amvdec_av1 frame_height\n");
+
+module_param(debug, uint, 0664);
+MODULE_PARM_DESC(debug, "\n amvdec_av1 debug\n");
+
+module_param(radr, uint, 0664);
+MODULE_PARM_DESC(radr, "\n radr\n");
+
+module_param(rval, uint, 0664);
+MODULE_PARM_DESC(rval, "\n rval\n");
+
+module_param(pop_shorts, uint, 0664);
+MODULE_PARM_DESC(pop_shorts, "\n rval\n");
+
+module_param(dbg_cmd, uint, 0664);
+MODULE_PARM_DESC(dbg_cmd, "\n dbg_cmd\n");
+
+module_param(dbg_skip_decode_index, uint, 0664);
+MODULE_PARM_DESC(dbg_skip_decode_index, "\n dbg_skip_decode_index\n");
+
+module_param(endian, uint, 0664);
+MODULE_PARM_DESC(endian, "\n rval\n");
+
+module_param(step, uint, 0664);
+MODULE_PARM_DESC(step, "\n amvdec_av1 step\n");
+
+module_param(decode_pic_begin, uint, 0664);
+MODULE_PARM_DESC(decode_pic_begin, "\n amvdec_av1 decode_pic_begin\n");
+
+module_param(slice_parse_begin, uint, 0664);
+MODULE_PARM_DESC(slice_parse_begin, "\n amvdec_av1 slice_parse_begin\n");
+
+module_param(i_only_flag, uint, 0664);
+MODULE_PARM_DESC(i_only_flag, "\n amvdec_av1 i_only_flag\n");
+
+module_param(low_latency_flag, uint, 0664);
+MODULE_PARM_DESC(low_latency_flag, "\n amvdec_av1 low_latency_flag\n");
+
+module_param(no_head, uint, 0664);
+MODULE_PARM_DESC(no_head, "\n amvdec_av1 no_head\n");
+
+module_param(error_handle_policy, uint, 0664);
+MODULE_PARM_DESC(error_handle_policy, "\n amvdec_av1 error_handle_policy\n");
+
+module_param(buf_alloc_width, uint, 0664);
+MODULE_PARM_DESC(buf_alloc_width, "\n buf_alloc_width\n");
+
+module_param(buf_alloc_height, uint, 0664);
+MODULE_PARM_DESC(buf_alloc_height, "\n buf_alloc_height\n");
+
+module_param(buf_alloc_depth, uint, 0664);
+MODULE_PARM_DESC(buf_alloc_depth, "\n buf_alloc_depth\n");
+
+module_param(buf_alloc_size, uint, 0664);
+MODULE_PARM_DESC(buf_alloc_size, "\n buf_alloc_size\n");
+
+module_param(buffer_mode, uint, 0664);
+MODULE_PARM_DESC(buffer_mode, "\n buffer_mode\n");
+
+module_param(buffer_mode_dbg, uint, 0664);
+MODULE_PARM_DESC(buffer_mode_dbg, "\n buffer_mode_dbg\n");
+/*USE_BUF_BLOCK*/
+module_param(max_buf_num, uint, 0664);
+MODULE_PARM_DESC(max_buf_num, "\n max_buf_num\n");
+
+module_param(dynamic_buf_num_margin, uint, 0664);
+MODULE_PARM_DESC(dynamic_buf_num_margin, "\n dynamic_buf_num_margin\n");
+
+module_param(mv_buf_margin, uint, 0664);
+MODULE_PARM_DESC(mv_buf_margin, "\n mv_buf_margin\n");
+
+module_param(run_ready_min_buf_num, uint, 0664);
+MODULE_PARM_DESC(run_ready_min_buf_num, "\n run_ready_min_buf_num\n");
+
+/**/
+
+module_param(mem_map_mode, uint, 0664);
+MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n");
+
+#ifdef SUPPORT_10BIT
+module_param(double_write_mode, uint, 0664);
+MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n");
+
+module_param(enable_mem_saving, uint, 0664);
+MODULE_PARM_DESC(enable_mem_saving, "\n enable_mem_saving\n");
+
+module_param(force_w_h, uint, 0664);
+MODULE_PARM_DESC(force_w_h, "\n force_w_h\n");
+#endif
+
+module_param(force_fps, uint, 0664);
+MODULE_PARM_DESC(force_fps, "\n force_fps\n");
+
+module_param(max_decoding_time, uint, 0664);
+MODULE_PARM_DESC(max_decoding_time, "\n max_decoding_time\n");
+
+module_param(on_no_keyframe_skiped, uint, 0664);
+MODULE_PARM_DESC(on_no_keyframe_skiped, "\n on_no_keyframe_skiped\n");
+
+
+#ifdef MULTI_INSTANCE_SUPPORT
+module_param(start_decode_buf_level, int, 0664);
+MODULE_PARM_DESC(start_decode_buf_level,
+ "\n av1 start_decode_buf_level\n");
+
+module_param(decode_timeout_val, uint, 0664);
+MODULE_PARM_DESC(decode_timeout_val,
+ "\n av1 decode_timeout_val\n");
+
+module_param(av1_max_pic_w, uint, 0664);
+MODULE_PARM_DESC(av1_max_pic_w, "\n av1_max_pic_w\n");
+
+module_param(av1_max_pic_h, uint, 0664);
+MODULE_PARM_DESC(av1_max_pic_h, "\n av1_max_pic_h\n");
+
+module_param_array(decode_frame_count, uint,
+ &max_decode_instance_num, 0664);
+
+module_param_array(display_frame_count, uint,
+ &max_decode_instance_num, 0664);
+
+module_param_array(max_process_time, uint,
+ &max_decode_instance_num, 0664);
+
+module_param_array(run_count, uint,
+ &max_decode_instance_num, 0664);
+
+module_param_array(input_empty, uint,
+ &max_decode_instance_num, 0664);
+
+module_param_array(not_run_ready, uint,
+ &max_decode_instance_num, 0664);
+#ifdef AOM_AV1_MMU_DW
+module_param_array(dw_mmu_enable, uint,
+ &max_decode_instance_num, 0664);
+#endif
+#endif
+
+module_param(get_picture_qos, uint, 0664);
+MODULE_PARM_DESC(get_picture_qos, "\n amvdec_av1 get_picture_qos\n");
+
+module_param(udebug_flag, uint, 0664);
+MODULE_PARM_DESC(udebug_flag, "\n amvdec_h265 udebug_flag\n");
+
+module_param(udebug_pause_pos, uint, 0664);
+MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n");
+
+module_param(udebug_pause_val, uint, 0664);
+MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n");
+
+module_param(udebug_pause_decode_idx, uint, 0664);
+MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n");
+
+module_init(amvdec_av1_driver_init_module);
+module_exit(amvdec_av1_driver_remove_module);
+
+MODULE_DESCRIPTION("AMLOGIC av1 Video Decoder Driver");
+MODULE_LICENSE("GPL");
+
diff --git a/drivers/frame_provider/decoder/vav1/vav1.h b/drivers/frame_provider/decoder/vav1/vav1.h
new file mode 100644
index 0000000..0f2b765
--- a/dev/null
+++ b/drivers/frame_provider/decoder/vav1/vav1.h
@@ -0,0 +1,22 @@
+/*
+ * drivers/amlogic/amports/vav1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#ifndef VAV1_H
+#define VAV1_H
+void adapt_coef_probs(int pic_count, int prev_kf, int cur_kf, int pre_fc,
+unsigned int *prev_prob, unsigned int *cur_prob, unsigned int *count);
+#endif
diff --git a/drivers/stream_input/amports/amstream.c b/drivers/stream_input/amports/amstream.c
index 2c20e80..4c2fa85 100644
--- a/drivers/stream_input/amports/amstream.c
+++ b/drivers/stream_input/amports/amstream.c
@@ -943,6 +943,7 @@ static int amstream_port_init(struct port_priv_s *priv)
if (has_hevc_vdec()) {
if (port->vformat == VFORMAT_HEVC ||
port->vformat == VFORMAT_AVS2 ||
+ port->vformat == VFORMAT_AV1 ||
port->vformat == VFORMAT_VP9)
pvbuf = &bufs[BUF_TYPE_HEVC];
}
@@ -973,6 +974,7 @@ static int amstream_port_init(struct port_priv_s *priv)
(port->pcr_inited == 1) ? port->pcrid : 0xffff,
(port->vformat == VFORMAT_HEVC) ||
(port->vformat == VFORMAT_AVS2) ||
+ (port->vformat == VFORMAT_AV1) ||
(port->vformat == VFORMAT_VP9),
vdec);
} else {
@@ -1053,6 +1055,7 @@ static int amstream_port_release(struct port_priv_s *priv)
if (has_hevc_vdec()) {
if (port->vformat == VFORMAT_HEVC
|| port->vformat == VFORMAT_AVS2
+ || port->vformat == VFORMAT_AV1
|| port->vformat == VFORMAT_VP9)
pvbuf = &bufs[BUF_TYPE_HEVC];
}
@@ -1209,6 +1212,7 @@ static ssize_t amstream_mpts_write(struct file *file, const char *buf,
if (has_hevc_vdec()) {
pvbuf = (port->vformat == VFORMAT_HEVC ||
port->vformat == VFORMAT_AVS2 ||
+ port->vformat == VFORMAT_AV1 ||
port->vformat == VFORMAT_VP9) ?
&bufs[BUF_TYPE_HEVC] : &bufs[BUF_TYPE_VIDEO];
} else
@@ -1803,6 +1807,7 @@ static int amstream_release(struct inode *inode, struct file *file)
if ((port->vformat == VFORMAT_HEVC
|| port->vformat == VFORMAT_AVS2
+ || port->vformat == VFORMAT_AV1
|| port->vformat == VFORMAT_VP9)) {
vdec_poweroff(VDEC_HEVC);
} else {
@@ -2350,6 +2355,7 @@ static long amstream_ioctl_get_ex(struct port_priv_s *priv, ulong arg)
buf = (this->vformat == VFORMAT_HEVC ||
this->vformat == VFORMAT_AVS2 ||
+ this->vformat == VFORMAT_AV1 ||
this->vformat == VFORMAT_VP9) ?
&bufs[BUF_TYPE_HEVC] :
&bufs[BUF_TYPE_VIDEO];
@@ -2836,6 +2842,7 @@ static long amstream_do_ioctl_old(struct port_priv_s *priv,
buf = (this->vformat == VFORMAT_HEVC ||
this->vformat == VFORMAT_AVS2 ||
+ this->vformat == VFORMAT_AV1 ||
this->vformat == VFORMAT_VP9) ?
&bufs[BUF_TYPE_HEVC] :
&bufs[BUF_TYPE_VIDEO];
diff --git a/firmware/video_ucode.bin b/firmware/video_ucode.bin
index 0d3d66b..f16cb16 100644
--- a/firmware/video_ucode.bin
+++ b/firmware/video_ucode.bin
@@ -1,5606 +1,24 @@
-c,poh{ R>
-Iٹ8U/SL>=@ៀc. VٙJNBgwᖱWM9f i:~%vYkIvY5KCAP
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generated by cgit at 2024-05-19 13:39:49 (GMT)