| author | Yixin Peng <yixin.peng@amlogic.com> | 2020-08-13 05:21:41 (GMT) |
|---|---|---|
| committer | Shen Liu <shen.liu@amlogic.com> | 2020-08-14 04:30:01 (GMT) |
| commit | 2f568ccaf768e566bc45e9a78431ba92f07eb7ad (patch) | |
| tree | 211fa64b0c59dba06825c38e745b27c87560c7a9 | |
| parent | f9c065b1cb15a45e0290305f0a743998112a9a16 (diff) | |
| download | media_modules-2f568ccaf768e566bc45e9a78431ba92f07eb7ad.zip media_modules-2f568ccaf768e566bc45e9a78431ba92f07eb7ad.tar.gz media_modules-2f568ccaf768e566bc45e9a78431ba92f07eb7ad.tar.bz2 | |
vdec: hevc reset core modificatios [1/2]
PD#SWPL-28883
Problem:
system will restart when playback specific DVB stream program
Solution:
Modify some hevc reset core registers
Verify:
u212
Change-Id: I3bfc48b5de6893fc672cfa0b9c4019c4b53d901b
Signed-off-by: Peng yixin <yixin.peng@amlogic.com>
| -rw-r--r-- | drivers/frame_provider/decoder/utils/vdec.c | 43 |
1 files changed, 41 insertions, 2 deletions
diff --git a/drivers/frame_provider/decoder/utils/vdec.c b/drivers/frame_provider/decoder/utils/vdec.c index 2c2d40a..107e1a4 100644 --- a/drivers/frame_provider/decoder/utils/vdec.c +++ b/drivers/frame_provider/decoder/utils/vdec.c @@ -101,6 +101,8 @@ static DEFINE_SPINLOCK(vdec_spin_lock); #define HEVC_TEST_LIMIT 100 #define GXBB_REV_A_MINOR 0xA +#define RESET7_REGISTER_LEVEL 0x1127 + #define CANVAS_MAX_SIZE (AMVDEC_CANVAS_MAX1 - AMVDEC_CANVAS_START_INDEX + 1 + AMVDEC_CANVAS_MAX2 + 1) struct am_reg { @@ -3311,6 +3313,7 @@ void hevc_reset_core(struct vdec_s *vdec) { unsigned long flags; unsigned int mask = 0; + int cpu_type; mask = 1 << 4; /*bit4: hevc*/ if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) @@ -3329,11 +3332,16 @@ void hevc_reset_core(struct vdec_s *vdec) if (vdec == NULL || input_frame_based(vdec)) WRITE_VREG(HEVC_STREAM_CONTROL, 0); + + WRITE_VREG(HEVC_SAO_MMU_RESET_CTRL, + READ_VREG(HEVC_SAO_MMU_RESET_CTRL) | 1); + /* * 2: assist * 3: parser * 4: parser_state * 8: dblk + * 10:wrrsp lmem * 11:mcpu * 12:ccpu * 13:ddr @@ -3343,13 +3351,44 @@ void hevc_reset_core(struct vdec_s *vdec) * 18:mpred * 19:sao * 24:hevc_afifo + * 26:rst_mmu_n */ WRITE_VREG(DOS_SW_RESET3, - (1<<3)|(1<<4)|(1<<8)|(1<<11)| + (1<<3)|(1<<4)|(1<<8)|(1<<10)|(1<<11)| (1<<12)|(1<<13)|(1<<14)|(1<<15)| - (1<<17)|(1<<18)|(1<<19)|(1<<24)); + (1<<17)|(1<<18)|(1<<19)|(1<<24)|(1<<26)); WRITE_VREG(DOS_SW_RESET3, 0); + while (READ_VREG(HEVC_WRRSP_LMEM) & 0xfff) + ; + WRITE_VREG(HEVC_SAO_MMU_RESET_CTRL, + READ_VREG(HEVC_SAO_MMU_RESET_CTRL) & (~1)); + cpu_type = get_cpu_major_id(); + switch (cpu_type) { + case AM_MESON_CPU_MAJOR_ID_G12B: + WRITE_RESET_REG((RESET7_REGISTER_LEVEL), + READ_RESET_REG(RESET7_REGISTER_LEVEL) & (~((1<<13)|(1<<14)))); + WRITE_RESET_REG((RESET7_REGISTER_LEVEL), + READ_RESET_REG((RESET7_REGISTER_LEVEL)) | ((1<<13)|(1<<14))); + break; + case AM_MESON_CPU_MAJOR_ID_G12A: + case AM_MESON_CPU_MAJOR_ID_TL1: + WRITE_RESET_REG((RESET7_REGISTER_LEVEL), + READ_RESET_REG(RESET7_REGISTER_LEVEL) & (~((1<<13)))); + WRITE_RESET_REG((RESET7_REGISTER_LEVEL), + READ_RESET_REG((RESET7_REGISTER_LEVEL)) | ((1<<13))); + break; + #if 0 + case AM_MESON_CPU_MAJOR_ID_SC2: + WRITE_RESET_REG(P_RESETCTRL_RESET5_LEVEL, + READ_RESET_REG(P_RESETCTRL_RESET5_LEVEL) & (~((1<<1)|(1<<12)|(1<<13)))); + WRITE_RESET_REG(P_RESETCTRL_RESET5_LEVEL, + READ_RESET_REG(P_RESETCTRL_RESET5_LEVEL) | ((1<<1)|(1<<12)|(1<<13))); + break; + #endif + default: + break; + } spin_lock_irqsave(&vdec_spin_lock, flags); |