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1/*
2* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
3*
4* This program is free software; you can redistribute it and/or modify
5* it under the terms of the GNU General Public License as published by
6* the Free Software Foundation; either version 2 of the License, or
7* (at your option) any later version.
8*
9* This program is distributed in the hope that it will be useful, but WITHOUT
10* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12* more details.
13*
14* You should have received a copy of the GNU General Public License along
15* with this program; if not, write to the Free Software Foundation, Inc.,
16* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17*
18* Description:
19*/
20#ifndef _AML_VCODEC_DRV_H_
21#define _AML_VCODEC_DRV_H_
22
23#include <linux/platform_device.h>
24#include <linux/videodev2.h>
25#include <media/v4l2-ctrls.h>
26#include <media/v4l2-device.h>
27#include <media/v4l2-ioctl.h>
28#include <media/videobuf2-core.h>
29#include <linux/amlogic/media/vfm/vframe.h>
30#include "aml_vcodec_util.h"
31
32#define AML_VCODEC_DRV_NAME "aml_vcodec_drv"
33#define AML_VCODEC_DEC_NAME "aml-vcodec-dec"
34#define AML_VCODEC_ENC_NAME "aml-vcodec-enc"
35#define AML_PLATFORM_STR "platform:amlogic"
36
37#define AML_VCODEC_MAX_PLANES 3
38#define AML_V4L2_BENCHMARK 0
39#define WAIT_INTR_TIMEOUT_MS 1000
40
41/* codec types of get/set parms. */
42#define V4L2_CONFIG_PARM_ENCODE (0)
43#define V4L2_CONFIG_PARM_DECODE (1)
44
45/* types of decode parms. */
46#define V4L2_CONFIG_PARM_DECODE_CFGINFO (1 << 0)
47#define V4L2_CONFIG_PARM_DECODE_PSINFO (1 << 1)
48#define V4L2_CONFIG_PARM_DECODE_HDRINFO (1 << 2)
49#define V4L2_CONFIG_PARM_DECODE_CNTINFO (1 << 3)
50
51/* amlogic event define. */
52/* #define V4L2_EVENT_SRC_CH_RESOLUTION (1 << 0) */
53#define V4L2_EVENT_SRC_CH_HDRINFO (1 << 1)
54#define V4L2_EVENT_SRC_CH_PSINFO (1 << 2)
55#define V4L2_EVENT_SRC_CH_CNTINFO (1 << 3)
56
57/* exception handing */
58#define V4L2_EVENT_REQUEST_RESET (1 << 8)
59#define V4L2_EVENT_REQUEST_EXIT (1 << 9)
60
61/* eos event */
62#define V4L2_EVENT_SEND_EOS (1 << 16)
63
64/* v4l buffer pool */
65#define V4L_CAP_BUFF_MAX (32)
66#define V4L_CAP_BUFF_INVALID (0)
67#define V4L_CAP_BUFF_IN_M2M (1)
68#define V4L_CAP_BUFF_IN_DEC (2)
69
70/* v4l reset mode */
71#define V4L_RESET_MODE_NORMAL (1 << 0) /* reset vdec_input and decoder. */
72#define V4L_RESET_MODE_LIGHT (1 << 1) /* just only reset decoder. */
73
74/* m2m job queue's status */
75/* Instance is already queued on the job_queue */
76#define TRANS_QUEUED (1 << 0)
77/* Instance is currently running in hardware */
78#define TRANS_RUNNING (1 << 1)
79/* Instance is currently aborting */
80#define TRANS_ABORT (1 << 2)
81
82/**
83 * enum aml_hw_reg_idx - AML hw register base index
84 */
85enum aml_hw_reg_idx {
86 VDEC_SYS,
87 VDEC_MISC,
88 VDEC_LD,
89 VDEC_TOP,
90 VDEC_CM,
91 VDEC_AD,
92 VDEC_AV,
93 VDEC_PP,
94 VDEC_HWD,
95 VDEC_HWQ,
96 VDEC_HWB,
97 VDEC_HWG,
98 NUM_MAX_VDEC_REG_BASE,
99 /* h264 encoder */
100 VENC_SYS = NUM_MAX_VDEC_REG_BASE,
101 /* vp8 encoder */
102 VENC_LT_SYS,
103 NUM_MAX_VCODEC_REG_BASE
104};
105
106/**
107 * enum aml_instance_type - The type of an AML Vcodec instance.
108 */
109enum aml_instance_type {
110 AML_INST_DECODER = 0,
111 AML_INST_ENCODER = 1,
112};
113
114/**
115 * enum aml_instance_state - The state of an AML Vcodec instance.
116 * @AML_STATE_IDLE - default state when instance is created
117 * @AML_STATE_INIT - vcodec instance is initialized
118 * @AML_STATE_PROBE - vdec/venc had sps/pps header parsed/encoded
119 * @AML_STATE_ACTIVE - vdec is ready for work.
120 * @AML_STATE_FLUSHING - vdec is flushing. Only used by decoder
121 * @AML_STATE_FLUSHED - decoder has transacted the last frame.
122 * @AML_STATE_RESET - decoder has be reset after flush.
123 * @AML_STATE_ABORT - vcodec should be aborted
124 */
125enum aml_instance_state {
126 AML_STATE_IDLE,
127 AML_STATE_INIT,
128 AML_STATE_PROBE,
129 AML_STATE_READY,
130 AML_STATE_ACTIVE,
131 AML_STATE_FLUSHING,
132 AML_STATE_FLUSHED,
133 AML_STATE_RESET,
134 AML_STATE_ABORT,
135};
136
137/**
138 * struct aml_encode_param - General encoding parameters type
139 */
140enum aml_encode_param {
141 AML_ENCODE_PARAM_NONE = 0,
142 AML_ENCODE_PARAM_BITRATE = (1 << 0),
143 AML_ENCODE_PARAM_FRAMERATE = (1 << 1),
144 AML_ENCODE_PARAM_INTRA_PERIOD = (1 << 2),
145 AML_ENCODE_PARAM_FORCE_INTRA = (1 << 3),
146 AML_ENCODE_PARAM_GOP_SIZE = (1 << 4),
147};
148
149enum aml_fmt_type {
150 AML_FMT_DEC = 0,
151 AML_FMT_ENC = 1,
152 AML_FMT_FRAME = 2,
153};
154
155/**
156 * struct aml_video_fmt - Structure used to store information about pixelformats
157 */
158struct aml_video_fmt {
159 u32 fourcc;
160 enum aml_fmt_type type;
161 u32 num_planes;
162};
163
164/**
165 * struct aml_codec_framesizes - Structure used to store information about
166 * framesizes
167 */
168struct aml_codec_framesizes {
169 u32 fourcc;
170 struct v4l2_frmsize_stepwise stepwise;
171};
172
173/**
174 * struct aml_q_type - Type of queue
175 */
176enum aml_q_type {
177 AML_Q_DATA_SRC = 0,
178 AML_Q_DATA_DST = 1,
179};
180
181
182/**
183 * struct aml_q_data - Structure used to store information about queue
184 */
185struct aml_q_data {
186 unsigned int visible_width;
187 unsigned int visible_height;
188 unsigned int coded_width;
189 unsigned int coded_height;
190 enum v4l2_field field;
191 unsigned int bytesperline[AML_VCODEC_MAX_PLANES];
192 unsigned int sizeimage[AML_VCODEC_MAX_PLANES];
193 struct aml_video_fmt *fmt;
194 bool resolution_changed;
195};
196
197/**
198 * struct aml_enc_params - General encoding parameters
199 * @bitrate: target bitrate in bits per second
200 * @num_b_frame: number of b frames between p-frame
201 * @rc_frame: frame based rate control
202 * @rc_mb: macroblock based rate control
203 * @seq_hdr_mode: H.264 sequence header is encoded separately or joined
204 * with the first frame
205 * @intra_period: I frame period
206 * @gop_size: group of picture size, it's used as the intra frame period
207 * @framerate_num: frame rate numerator. ex: framerate_num=30 and
208 * framerate_denom=1 menas FPS is 30
209 * @framerate_denom: frame rate denominator. ex: framerate_num=30 and
210 * framerate_denom=1 menas FPS is 30
211 * @h264_max_qp: Max value for H.264 quantization parameter
212 * @h264_profile: V4L2 defined H.264 profile
213 * @h264_level: V4L2 defined H.264 level
214 * @force_intra: force/insert intra frame
215 */
216struct aml_enc_params {
217 unsigned int bitrate;
218 unsigned int num_b_frame;
219 unsigned int rc_frame;
220 unsigned int rc_mb;
221 unsigned int seq_hdr_mode;
222 unsigned int intra_period;
223 unsigned int gop_size;
224 unsigned int framerate_num;
225 unsigned int framerate_denom;
226 unsigned int h264_max_qp;
227 unsigned int h264_profile;
228 unsigned int h264_level;
229 unsigned int force_intra;
230};
231
232/**
233 * struct aml_vcodec_pm - Power management data structure
234 */
235struct aml_vcodec_pm {
236 struct clk *vdec_bus_clk_src;
237 struct clk *vencpll;
238
239 struct clk *vcodecpll;
240 struct clk *univpll_d2;
241 struct clk *clk_cci400_sel;
242 struct clk *vdecpll;
243 struct clk *vdec_sel;
244 struct clk *vencpll_d2;
245 struct clk *venc_sel;
246 struct clk *univpll1_d2;
247 struct clk *venc_lt_sel;
248 struct device *larbvdec;
249 struct device *larbvenc;
250 struct device *larbvenclt;
251 struct device *dev;
252 struct aml_vcodec_dev *amldev;
253};
254
255/**
256 * struct vdec_pic_info - picture size information
257 * @visible_width: picture width
258 * @visible_height: picture height
259 * @coded_width: picture buffer width (64 aligned up from pic_w)
260 * @coded_height: picture buffer heiht (64 aligned up from pic_h)
261 * @y_bs_sz: Y bitstream size
262 * @c_bs_sz: CbCr bitstream size
263 * @y_len_sz: additional size required to store decompress information for y
264 * plane
265 * @c_len_sz: additional size required to store decompress information for cbcr
266 * plane
267 * E.g. suppose picture size is 176x144,
268 * buffer size will be aligned to 176x160.
269 */
270struct vdec_pic_info {
271 unsigned int visible_width;
272 unsigned int visible_height;
273 unsigned int coded_width;
274 unsigned int coded_height;
275 unsigned int y_bs_sz;
276 unsigned int c_bs_sz;
277 unsigned int y_len_sz;
278 unsigned int c_len_sz;
279 int profile_idc;
280 int ref_frame_count;
281};
282
283struct aml_vdec_cfg_infos {
284 u32 double_write_mode;
285 u32 init_width;
286 u32 init_height;
287 u32 ref_buf_margin;
288 u32 canvas_mem_mode;
289 u32 canvas_mem_endian;
290};
291
292struct aml_vdec_hdr_infos {
293 /*
294 * bit 29 : present_flag
295 * bit 28-26: video_format "component", "PAL", "NTSC", "SECAM", "MAC", "unspecified"
296 * bit 25 : range "limited", "full_range"
297 * bit 24 : color_description_present_flag
298 * bit 23-16: color_primaries "unknown", "bt709", "undef", "bt601",
299 * "bt470m", "bt470bg", "smpte170m", "smpte240m", "film", "bt2020"
300 * bit 15-8 : transfer_characteristic unknown", "bt709", "undef", "bt601",
301 * "bt470m", "bt470bg", "smpte170m", "smpte240m",
302 * "linear", "log100", "log316", "iec61966-2-4",
303 * "bt1361e", "iec61966-2-1", "bt2020-10", "bt2020-12",
304 * "smpte-st-2084", "smpte-st-428"
305 * bit 7-0 : matrix_coefficient "GBR", "bt709", "undef", "bt601",
306 * "fcc", "bt470bg", "smpte170m", "smpte240m",
307 * "YCgCo", "bt2020nc", "bt2020c"
308 */
309 u32 signal_type;
310 struct vframe_master_display_colour_s color_parms;
311};
312
313struct aml_vdec_ps_infos {
314 u32 visible_width;
315 u32 visible_height;
316 u32 coded_width;
317 u32 coded_height;
318 u32 profile;
319 u32 mb_width;
320 u32 mb_height;
321 u32 dpb_size;
322 u32 ref_frames;
323 u32 reorder_frames;
324};
325
326struct aml_vdec_cnt_infos {
327 u32 bit_rate;
328 u32 frame_count;
329 u32 error_frame_count;
330 u32 drop_frame_count;
331 u32 total_data;
332};
333
334struct aml_dec_params {
335 u32 parms_status;
336 struct aml_vdec_cfg_infos cfg;
337 struct aml_vdec_ps_infos ps;
338 struct aml_vdec_hdr_infos hdr;
339 struct aml_vdec_cnt_infos cnt;
340};
341
342struct v4l2_config_parm {
343 u32 type;
344 u32 length;
345 union {
346 struct aml_dec_params dec;
347 struct aml_enc_params enc;
348 u8 data[200];
349 } parm;
350 u8 buf[4096];
351};
352
353struct v4l_buff_pool {
354 /*
355 * bit 31-16: buffer state
356 * bit 15- 0: buffer index
357 */
358 u32 seq[V4L_CAP_BUFF_MAX];
359 u32 in, out;
360};
361
362enum aml_thread_type {
363 AML_THREAD_OUTPUT,
364 AML_THREAD_CAPTURE,
365};
366
367typedef void (*aml_thread_func)(struct aml_vcodec_ctx *ctx);
368
369struct aml_vdec_thread {
370 struct list_head node;
371 spinlock_t lock;
372 struct semaphore sem;
373 struct task_struct *task;
374 enum aml_thread_type type;
375 void *priv;
376 int stop;
377
378 aml_thread_func func;
379};
380
381/**
382 * struct aml_vcodec_ctx - Context (instance) private data.
383 *
384 * @id: index of the context that this structure describes.
385 * @type: type of the instance - decoder or encoder.
386 * @dev: pointer to the aml_vcodec_dev of the device.
387 * @m2m_ctx: pointer to the v4l2_m2m_ctx of the context.
388 * @ada_ctx: pointer to the aml_vdec_adapt of the context.
389 * @dec_if: hooked decoder driver interface.
390 * @drv_handle: driver handle for specific decode instance
391 * @fh: struct v4l2_fh.
392 * @ctrl_hdl: handler for v4l2 framework.
393 * @slock: protect v4l2 codec context.
394 * @empty_flush_buf: a fake size-0 capture buffer that indicates flush.
395 * @list: link to ctx_list of aml_vcodec_dev.
396 * @q_data: store information of input and output queue of the context.
397 * @queue: waitqueue that can be used to wait for this context to finish.
398 * @lock: protect the vdec thread.
399 * @state_lock: protect the codec status.
400 * @state: state of the context.
401 * @decode_work: decoder work be used to output buffer.
402 * @output_thread_ready: indicate the output thread ready.
403 * @cap_pool: capture buffers are remark in the pool.
404 * @vdec_thread_list: vdec thread be used to capture.
405 * @dpb_size: store dpb count after header parsing
406 * @param_change: indicate encode parameter type
407 * @param_sets_from_ucode: if true indicate ps from ucode.
408 * @v4l_codec_dpb_ready: queue buffer number greater than dpb.
409 * @comp: comp be used for sync picture information with decoder.
410 * @config: used to set or get parms for application.
411 * @picinfo: store picture info after header parsing.
412 * @last_decoded_picinfo: pic information get from latest decode.
413 * @colorspace: enum v4l2_colorspace; supplemental to pixelformat.
414 * @ycbcr_enc: enum v4l2_ycbcr_encoding, Y'CbCr encoding.
415 * @quantization: enum v4l2_quantization, colorspace quantization.
416 * @xfer_func: enum v4l2_xfer_func, colorspace transfer function.
417 * @cap_pix_fmt: the picture format used to switch nv21 or nv12.
418 * @has_receive_eos: if receive last frame of capture that be set.
419 * @is_drm_mode: decoding work on drm mode if that set.
420 * @is_stream_mode: vdec input used to stream mode, default frame mode.
421 * @is_stream_off: the value used to handle reset active.
422 * @receive_cmd_stop: if receive the cmd flush decoder.
423 * @reset_flag: reset mode includes lightly and normal mode.
424 * @decoded_frame_cnt: the capture buffer deque number to be count.
425 * @buf_used_count: means that decode allocate how many buffs from v4l.
426 */
427struct aml_vcodec_ctx {
428 int id;
429 enum aml_instance_type type;
430 struct aml_vcodec_dev *dev;
431 struct v4l2_m2m_ctx *m2m_ctx;
432 struct aml_vdec_adapt *ada_ctx;
433 const struct vdec_common_if *dec_if;
434 ulong drv_handle;
435 struct v4l2_fh fh;
436 struct v4l2_ctrl_handler ctrl_hdl;
437 spinlock_t slock;
438 struct aml_video_dec_buf *empty_flush_buf;
439 struct list_head list;
440
441 struct aml_q_data q_data[2];
442 wait_queue_head_t queue;
443 struct mutex lock, state_lock;
444 enum aml_instance_state state;
445 struct work_struct decode_work;
446 bool output_thread_ready;
447 struct v4l_buff_pool cap_pool;
448 struct list_head vdec_thread_list;
449
450 int dpb_size;
451 bool param_sets_from_ucode;
452 bool v4l_codec_dpb_ready;
453 struct completion comp;
454 struct v4l2_config_parm config;
455 struct vdec_pic_info picinfo;
456 struct vdec_pic_info last_decoded_picinfo;
457 enum v4l2_colorspace colorspace;
458 enum v4l2_ycbcr_encoding ycbcr_enc;
459 enum v4l2_quantization quantization;
460 enum v4l2_xfer_func xfer_func;
461 u32 cap_pix_fmt;
462
463 bool has_receive_eos;
464 bool is_drm_mode;
465 bool output_dma_mode;
466 bool is_stream_off;
467 bool receive_cmd_stop;
468 int reset_flag;
469 int decoded_frame_cnt;
470 int buf_used_count;
471};
472
473/**
474 * struct aml_vcodec_dev - driver data
475 * @v4l2_dev: V4L2 device to register video devices for.
476 * @vfd_dec: Video device for decoder
477 * @vfd_enc: Video device for encoder.
478 *
479 * @m2m_dev_dec: m2m device for decoder
480 * @m2m_dev_enc: m2m device for encoder.
481 * @plat_dev: platform device
482 * @vpu_plat_dev: aml vpu platform device
483 * @alloc_ctx: VB2 allocator context
484 * (for allocations without kernel mapping).
485 * @ctx_list: list of struct aml_vcodec_ctx
486 * @irqlock: protect data access by irq handler and work thread
487 * @curr_ctx: The context that is waiting for codec hardware
488 *
489 * @reg_base: Mapped address of AML Vcodec registers.
490 *
491 * @id_counter: used to identify current opened instance
492 *
493 * @encode_workqueue: encode work queue
494 *
495 * @int_cond: used to identify interrupt condition happen
496 * @int_type: used to identify what kind of interrupt condition happen
497 * @dev_mutex: video_device lock
498 * @queue: waitqueue for waiting for completion of device commands
499 *
500 * @dec_irq: decoder irq resource
501 * @enc_irq: h264 encoder irq resource
502 * @enc_lt_irq: vp8 encoder irq resource
503 *
504 * @dec_mutex: decoder hardware lock
505 * @enc_mutex: encoder hardware lock.
506 *
507 * @pm: power management control
508 * @dec_capability: used to identify decode capability, ex: 4k
509 * @enc_capability: used to identify encode capability
510 */
511struct aml_vcodec_dev {
512 struct v4l2_device v4l2_dev;
513 struct video_device *vfd_dec;
514 struct video_device *vfd_enc;
515 struct file *filp;
516
517 struct v4l2_m2m_dev *m2m_dev_dec;
518 struct v4l2_m2m_dev *m2m_dev_enc;
519 struct platform_device *plat_dev;
520 struct platform_device *vpu_plat_dev;//??
521 struct vb2_alloc_ctx *alloc_ctx;//??
522 struct list_head ctx_list;
523 spinlock_t irqlock;
524 struct aml_vcodec_ctx *curr_ctx;
525 void __iomem *reg_base[NUM_MAX_VCODEC_REG_BASE];
526
527 unsigned long id_counter;
528
529 struct workqueue_struct *decode_workqueue;
530 struct workqueue_struct *encode_workqueue;
531 int int_cond;
532 int int_type;
533 struct mutex dev_mutex;
534 wait_queue_head_t queue;
535
536 int dec_irq;
537 int enc_irq;
538 int enc_lt_irq;
539
540 struct mutex dec_mutex;
541 struct mutex enc_mutex;
542
543 struct aml_vcodec_pm pm;
544 unsigned int dec_capability;
545 unsigned int enc_capability;
546};
547
548static inline struct aml_vcodec_ctx *fh_to_ctx(struct v4l2_fh *fh)
549{
550 return container_of(fh, struct aml_vcodec_ctx, fh);
551}
552
553static inline struct aml_vcodec_ctx *ctrl_to_ctx(struct v4l2_ctrl *ctrl)
554{
555 return container_of(ctrl->handler, struct aml_vcodec_ctx, ctrl_hdl);
556}
557
558#endif /* _AML_VCODEC_DRV_H_ */
559
generated by cgit at 2024-05-19 20:44:48 (GMT)