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path: root/drivers/amvdec_ports/decoder/vdec_h264_if.c (plain)
blob: 04173d6906c235ffc5ccafcbbfc337dee86da36c
1/*
2* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
3*
4* This program is free software; you can redistribute it and/or modify
5* it under the terms of the GNU General Public License as published by
6* the Free Software Foundation; either version 2 of the License, or
7* (at your option) any later version.
8*
9* This program is distributed in the hope that it will be useful, but WITHOUT
10* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12* more details.
13*
14* You should have received a copy of the GNU General Public License along
15* with this program; if not, write to the Free Software Foundation, Inc.,
16* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17*
18* Description:
19*/
20#include <linux/module.h>
21#include <linux/slab.h>
22#include <linux/timer.h>
23#include <linux/delay.h>
24#include <linux/kernel.h>
25#include <uapi/linux/swab.h>
26
27#include "../vdec_drv_if.h"
28#include "../aml_vcodec_util.h"
29#include "../aml_vcodec_dec.h"
30#include "../aml_vcodec_drv.h"
31#include "../aml_vcodec_adapt.h"
32#include "../vdec_drv_base.h"
33#include "../aml_vcodec_vfm.h"
34#include "aml_h264_parser.h"
35#include "../utils/common.h"
36
37/* h264 NALU type */
38#define NAL_NON_IDR_SLICE 0x01
39#define NAL_IDR_SLICE 0x05
40#define NAL_H264_SEI 0x06
41#define NAL_H264_SPS 0x07
42#define NAL_H264_PPS 0x08
43#define NAL_H264_AUD 0x09
44
45#define AVC_NAL_TYPE(value) ((value) & 0x1F)
46
47#define BUF_PREDICTION_SZ (64 * 1024)//(32 * 1024)
48
49#define MB_UNIT_LEN 16
50
51/* motion vector size (bytes) for every macro block */
52#define HW_MB_STORE_SZ 64
53
54#define H264_MAX_FB_NUM 17
55#define HDR_PARSING_BUF_SZ 1024
56
57#define HEADER_BUFFER_SIZE (128 * 1024)
58
59/**
60 * struct h264_fb - h264 decode frame buffer information
61 * @vdec_fb_va : virtual address of struct vdec_fb
62 * @y_fb_dma : dma address of Y frame buffer (luma)
63 * @c_fb_dma : dma address of C frame buffer (chroma)
64 * @poc : picture order count of frame buffer
65 * @reserved : for 8 bytes alignment
66 */
67struct h264_fb {
68 uint64_t vdec_fb_va;
69 uint64_t y_fb_dma;
70 uint64_t c_fb_dma;
71 int32_t poc;
72 uint32_t reserved;
73};
74
75/**
76 * struct h264_ring_fb_list - ring frame buffer list
77 * @fb_list : frame buffer arrary
78 * @read_idx : read index
79 * @write_idx : write index
80 * @count : buffer count in list
81 */
82struct h264_ring_fb_list {
83 struct h264_fb fb_list[H264_MAX_FB_NUM];
84 unsigned int read_idx;
85 unsigned int write_idx;
86 unsigned int count;
87 unsigned int reserved;
88};
89
90/**
91 * struct vdec_h264_dec_info - decode information
92 * @dpb_sz : decoding picture buffer size
93 * @realloc_mv_buf : flag to notify driver to re-allocate mv buffer
94 * @reserved : for 8 bytes alignment
95 * @bs_dma : Input bit-stream buffer dma address
96 * @y_fb_dma : Y frame buffer dma address
97 * @c_fb_dma : C frame buffer dma address
98 * @vdec_fb_va : VDEC frame buffer struct virtual address
99 */
100struct vdec_h264_dec_info {
101 uint32_t dpb_sz;
102 uint32_t realloc_mv_buf;
103 uint32_t reserved;
104 uint64_t bs_dma;
105 uint64_t y_fb_dma;
106 uint64_t c_fb_dma;
107 uint64_t vdec_fb_va;
108};
109
110/**
111 * struct vdec_h264_vsi - shared memory for decode information exchange
112 * between VPU and Host.
113 * The memory is allocated by VPU then mapping to Host
114 * in vpu_dec_init() and freed in vpu_dec_deinit()
115 * by VPU.
116 * AP-W/R : AP is writer/reader on this item
117 * VPU-W/R: VPU is write/reader on this item
118 * @dec : decode information (AP-R, VPU-W)
119 * @pic : picture information (AP-R, VPU-W)
120 * @crop : crop information (AP-R, VPU-W)
121 */
122struct vdec_h264_vsi {
123 unsigned char hdr_buf[HDR_PARSING_BUF_SZ];
124 char *header_buf;
125 int sps_size;
126 int pps_size;
127 int sei_size;
128 int head_offset;
129 struct vdec_h264_dec_info dec;
130 struct vdec_pic_info pic;
131 struct vdec_pic_info cur_pic;
132 struct v4l2_rect crop;
133 bool is_combine;
134 int nalu_pos;
135};
136
137/**
138 * struct vdec_h264_inst - h264 decoder instance
139 * @num_nalu : how many nalus be decoded
140 * @ctx : point to aml_vcodec_ctx
141 * @pred_buf : HW working predication buffer
142 * @mv_buf : HW working motion vector buffer
143 * @vpu : VPU instance
144 * @vsi : VPU shared information
145 */
146struct vdec_h264_inst {
147 unsigned int num_nalu;
148 struct aml_vcodec_ctx *ctx;
149 struct aml_vcodec_mem pred_buf;
150 struct aml_vcodec_mem mv_buf[H264_MAX_FB_NUM];
151 struct aml_vdec_adapt vdec;
152 struct vdec_h264_vsi *vsi;
153 struct vcodec_vfm_s vfm;
154 struct aml_dec_params parms;
155 struct completion comp;
156};
157
158#if 0
159#define DUMP_FILE_NAME "/data/dump/dump.tmp"
160static struct file *filp;
161static loff_t file_pos;
162
163void dump_write(const char __user *buf, size_t count)
164{
165 mm_segment_t old_fs;
166
167 if (!filp)
168 return;
169
170 old_fs = get_fs();
171 set_fs(KERNEL_DS);
172
173 if (count != vfs_write(filp, buf, count, &file_pos))
174 pr_err("Failed to write file\n");
175
176 set_fs(old_fs);
177}
178
179void dump_init(void)
180{
181 filp = filp_open(DUMP_FILE_NAME, O_CREAT | O_RDWR, 0644);
182 if (IS_ERR(filp)) {
183 pr_err("open dump file failed\n");
184 filp = NULL;
185 }
186}
187
188void dump_deinit(void)
189{
190 if (filp) {
191 filp_close(filp, current->files);
192 filp = NULL;
193 file_pos = 0;
194 }
195}
196
197void swap_uv(void *uv, int size)
198{
199 int i;
200 __u16 *p = uv;
201
202 size /= 2;
203
204 for (i = 0; i < size; i++, p++)
205 *p = __swab16(*p);
206}
207#endif
208
209static void get_pic_info(struct vdec_h264_inst *inst,
210 struct vdec_pic_info *pic)
211{
212 *pic = inst->vsi->pic;
213
214 v4l_dbg(inst->ctx, V4L_DEBUG_CODEC_EXINFO,
215 "pic(%d, %d), buf(%d, %d)\n",
216 pic->visible_width, pic->visible_height,
217 pic->coded_width, pic->coded_height);
218 v4l_dbg(inst->ctx, V4L_DEBUG_CODEC_EXINFO,
219 "Y(%d, %d), C(%d, %d)\n", pic->y_bs_sz,
220 pic->y_len_sz, pic->c_bs_sz, pic->c_len_sz);
221}
222
223static void get_crop_info(struct vdec_h264_inst *inst, struct v4l2_rect *cr)
224{
225 cr->left = inst->vsi->crop.left;
226 cr->top = inst->vsi->crop.top;
227 cr->width = inst->vsi->crop.width;
228 cr->height = inst->vsi->crop.height;
229
230 v4l_dbg(inst->ctx, V4L_DEBUG_CODEC_EXINFO,
231 "l=%d, t=%d, w=%d, h=%d\n",
232 cr->left, cr->top, cr->width, cr->height);
233}
234
235static void get_dpb_size(struct vdec_h264_inst *inst, unsigned int *dpb_sz)
236{
237 *dpb_sz = inst->vsi->dec.dpb_sz;
238 v4l_dbg(inst->ctx, V4L_DEBUG_CODEC_EXINFO, "sz=%d\n", *dpb_sz);
239}
240
241static void skip_aud_data(u8 **data, u32 *size)
242{
243 int i;
244
245 i = find_start_code(*data, *size);
246 if (i > 0 && (*data)[i++] == 0x9 && (*data)[i++] == 0xf0) {
247 *size -= i;
248 *data += i;
249 }
250}
251
252static u32 vdec_config_default_parms(u8 *parm)
253{
254 u8 *pbuf = parm;
255
256 pbuf += sprintf(pbuf, "parm_v4l_codec_enable:1;");
257 pbuf += sprintf(pbuf, "mh264_double_write_mode:16;");
258 pbuf += sprintf(pbuf, "parm_v4l_buffer_margin:7;");
259 pbuf += sprintf(pbuf, "parm_v4l_canvas_mem_mode:0;");
260 pbuf += sprintf(pbuf, "parm_v4l_canvas_mem_endian:0;");
261
262 return parm - pbuf;
263}
264
265static void vdec_parser_parms(struct vdec_h264_inst *inst)
266{
267 struct aml_vcodec_ctx *ctx = inst->ctx;
268
269 if (ctx->config.parm.dec.parms_status &
270 V4L2_CONFIG_PARM_DECODE_CFGINFO) {
271 u8 *pbuf = ctx->config.buf;
272
273 pbuf += sprintf(pbuf, "parm_v4l_codec_enable:1;");
274 pbuf += sprintf(pbuf, "mh264_double_write_mode:%d;",
275 ctx->config.parm.dec.cfg.double_write_mode);
276 pbuf += sprintf(pbuf, "parm_v4l_buffer_margin:%d;",
277 ctx->config.parm.dec.cfg.ref_buf_margin);
278 pbuf += sprintf(pbuf, "parm_v4l_canvas_mem_mode:%d;",
279 ctx->config.parm.dec.cfg.canvas_mem_mode);
280 pbuf += sprintf(pbuf, "parm_v4l_canvas_mem_endian:%d;",
281 ctx->config.parm.dec.cfg.canvas_mem_endian);
282 ctx->config.length = pbuf - ctx->config.buf;
283 } else {
284 ctx->config.parm.dec.cfg.double_write_mode = 16;
285 ctx->config.parm.dec.cfg.ref_buf_margin = 7;
286 ctx->config.length = vdec_config_default_parms(ctx->config.buf);
287 }
288
289 inst->vdec.config = ctx->config;
290 inst->parms.cfg = ctx->config.parm.dec.cfg;
291 inst->parms.parms_status |= V4L2_CONFIG_PARM_DECODE_CFGINFO;
292}
293
294static int vdec_h264_init(struct aml_vcodec_ctx *ctx, unsigned long *h_vdec)
295{
296 struct vdec_h264_inst *inst = NULL;
297 int ret = -1;
298
299 inst = kzalloc(sizeof(*inst), GFP_KERNEL);
300 if (!inst)
301 return -ENOMEM;
302
303 inst->vdec.video_type = VFORMAT_H264;
304 inst->vdec.dev = ctx->dev->vpu_plat_dev;
305 inst->vdec.filp = ctx->dev->filp;
306 inst->vdec.ctx = ctx;
307 inst->ctx = ctx;
308
309 vdec_parser_parms(inst);
310
311 /* set play mode.*/
312 if (ctx->is_drm_mode)
313 inst->vdec.port.flag |= PORT_FLAG_DRM;
314
315 /* init vfm */
316 inst->vfm.ctx = ctx;
317 inst->vfm.ada_ctx = &inst->vdec;
318 ret = vcodec_vfm_init(&inst->vfm);
319 if (ret) {
320 v4l_dbg(inst->ctx, V4L_DEBUG_CODEC_ERROR,
321 "init vfm failed.\n");
322 goto err;
323 }
324
325 ret = video_decoder_init(&inst->vdec);
326 if (ret) {
327 v4l_dbg(inst->ctx, V4L_DEBUG_CODEC_ERROR,
328 "vdec_h264 init err=%d\n", ret);
329 goto err;
330 }
331
332 /* probe info from the stream */
333 inst->vsi = kzalloc(sizeof(struct vdec_h264_vsi), GFP_KERNEL);
334 if (!inst->vsi) {
335 ret = -ENOMEM;
336 goto err;
337 }
338
339 /* alloc the header buffer to be used cache sps or spp etc.*/
340 inst->vsi->header_buf = kzalloc(HEADER_BUFFER_SIZE, GFP_KERNEL);
341 if (!inst->vsi->header_buf) {
342 ret = -ENOMEM;
343 goto err;
344 }
345
346 init_completion(&inst->comp);
347
348 v4l_dbg(inst->ctx, V4L_DEBUG_CODEC_PRINFO,
349 "H264 Instance >> %lx", (ulong) inst);
350
351 ctx->ada_ctx = &inst->vdec;
352 *h_vdec = (unsigned long)inst;
353
354 //dump_init();
355
356 return 0;
357err:
358 if (inst)
359 vcodec_vfm_release(&inst->vfm);
360 if (inst && inst->vsi && inst->vsi->header_buf)
361 kfree(inst->vsi->header_buf);
362 if (inst && inst->vsi)
363 kfree(inst->vsi);
364 if (inst)
365 kfree(inst);
366 *h_vdec = 0;
367
368 return ret;
369}
370
371#if 0
372static int refer_buffer_num(int level_idc, int max_poc_cnt,
373 int mb_width, int mb_height)
374{
375 int size;
376 int pic_size = mb_width * mb_height * 384;
377
378 switch (level_idc) {
379 case 9:
380 size = 152064;
381 break;
382 case 10:
383 size = 152064;
384 break;
385 case 11:
386 size = 345600;
387 break;
388 case 12:
389 size = 912384;
390 break;
391 case 13:
392 size = 912384;
393 break;
394 case 20:
395 size = 912384;
396 break;
397 case 21:
398 size = 1824768;
399 break;
400 case 22:
401 size = 3110400;
402 break;
403 case 30:
404 size = 3110400;
405 break;
406 case 31:
407 size = 6912000;
408 break;
409 case 32:
410 size = 7864320;
411 break;
412 case 40:
413 size = 12582912;
414 break;
415 case 41:
416 size = 12582912;
417 break;
418 case 42:
419 size = 13369344;
420 break;
421 case 50:
422 size = 42393600;
423 break;
424 case 51:
425 case 52:
426 default:
427 size = 70778880;
428 break;
429 }
430
431 size /= pic_size;
432 size = size + 1; /* need more buffers */
433
434 if (size > max_poc_cnt)
435 size = max_poc_cnt;
436
437 return size;
438}
439#endif
440
441static void vdec_config_dw_mode(struct vdec_pic_info *pic, int dw_mode)
442{
443 switch (dw_mode) {
444 case 0x1: /* (w x h) + (w/2 x h) */
445 pic->coded_width += pic->coded_width >> 1;
446 pic->y_len_sz = pic->coded_width * pic->coded_height;
447 pic->c_len_sz = pic->y_len_sz >> 1;
448 break;
449 case 0x2: /* (w x h) + (w/2 x h/2) */
450 pic->coded_width += pic->coded_width >> 1;
451 pic->coded_height += pic->coded_height >> 1;
452 pic->y_len_sz = pic->coded_width * pic->coded_height;
453 pic->c_len_sz = pic->y_len_sz >> 1;
454 break;
455 default: /* nothing to do */
456 break;
457 }
458}
459
460static void fill_vdec_params(struct vdec_h264_inst *inst, struct h264_SPS_t *sps)
461{
462 struct vdec_pic_info *pic = &inst->vsi->pic;
463 struct vdec_h264_dec_info *dec = &inst->vsi->dec;
464 struct v4l2_rect *rect = &inst->vsi->crop;
465 int dw = inst->parms.cfg.double_write_mode;
466 int margin = inst->parms.cfg.ref_buf_margin;
467 u32 mb_w, mb_h, width, height;
468
469 mb_w = sps->mb_width;
470 mb_h = sps->mb_height;
471
472 width = mb_w << 4;
473 height = mb_h << 4;
474
475 width -= (sps->crop_left + sps->crop_right);
476 height -= (sps->crop_top + sps->crop_bottom);
477
478 /* fill visible area size that be used for EGL. */
479 pic->visible_width = width;
480 pic->visible_height = height;
481
482 /* calc visible ares. */
483 rect->left = 0;
484 rect->top = 0;
485 rect->width = pic->visible_width;
486 rect->height = pic->visible_height;
487
488 /* config canvas size that be used for decoder. */
489 pic->coded_width = ALIGN(mb_w, 4) << 4;
490 pic->coded_height = ALIGN(mb_h, 4) << 4;
491 pic->y_len_sz = pic->coded_width * pic->coded_height;
492 pic->c_len_sz = pic->y_len_sz >> 1;
493 pic->profile_idc = sps->profile_idc;
494 pic->ref_frame_count= sps->ref_frame_count;
495 /* calc DPB size */
496 dec->dpb_sz = sps->num_reorder_frames + margin;
497
498 inst->parms.ps.visible_width = pic->visible_width;
499 inst->parms.ps.visible_height = pic->visible_height;
500 inst->parms.ps.coded_width = pic->coded_width;
501 inst->parms.ps.coded_height = pic->coded_height;
502 inst->parms.ps.profile = sps->profile_idc;
503 inst->parms.ps.mb_width = sps->mb_width;
504 inst->parms.ps.mb_height = sps->mb_height;
505 inst->parms.ps.ref_frames = sps->ref_frame_count;
506 inst->parms.ps.reorder_frames = sps->num_reorder_frames;
507 inst->parms.ps.dpb_size = dec->dpb_sz;
508 inst->parms.parms_status |= V4L2_CONFIG_PARM_DECODE_PSINFO;
509
510 vdec_config_dw_mode(pic, dw);
511
512 v4l_dbg(inst->ctx, V4L_DEBUG_CODEC_BUFMGR,
513 "The stream infos, dw: %d, coded:(%d x %d), visible:(%d x %d), DPB: %d, margin: %d\n",
514 dw, pic->coded_width, pic->coded_height,
515 pic->visible_width, pic->visible_height,
516 dec->dpb_sz - margin, margin);
517}
518
519static bool check_frame_combine(u8 *buf, u32 size, int *pos)
520{
521 bool combine = false;
522 int i = 0, j = 0, cnt = 0;
523 u8 *p = buf;
524
525 for (i = 4; i < size; i++) {
526 j = find_start_code(p, 7);
527 if (j > 0) {
528 if (++cnt > 1) {
529 combine = true;
530 break;
531 }
532
533 *pos = p - buf + j;
534 p += j;
535 i += j;
536 }
537 p++;
538 }
539
540 //pr_info("nal pos: %d, is_combine: %d\n",*pos, *is_combine);
541 return combine;
542}
543
544static int vdec_search_startcode(u8 *buf, u32 range)
545{
546 int pos = -1;
547 int i = 0, j = 0;
548 u8 *p = buf;
549
550 for (i = 4; i < range; i++) {
551 j = find_start_code(p, 7);
552 if (j > 0) {
553 pos = p - buf + j;
554 break;
555 }
556 p++;
557 }
558
559 return pos;
560}
561
562static int parse_stream_ucode(struct vdec_h264_inst *inst, u8 *buf, u32 size)
563{
564 int ret = 0;
565 struct aml_vdec_adapt *vdec = &inst->vdec;
566
567 ret = vdec_vframe_write(vdec, buf, size, 0);
568 if (ret < 0) {
569 v4l_dbg(inst->ctx, V4L_DEBUG_CODEC_ERROR,
570 "write frame data failed. err: %d\n", ret);
571 return ret;
572 }
573
574 /* wait ucode parse ending. */
575 wait_for_completion_timeout(&inst->comp,
576 msecs_to_jiffies(1000));
577
578 return inst->vsi->dec.dpb_sz ? 0 : -1;
579}
580
581static int parse_stream_ucode_dma(struct vdec_h264_inst *inst,
582 ulong buf, u32 size, u32 handle)
583{
584 int ret = 0;
585 struct aml_vdec_adapt *vdec = &inst->vdec;
586
587 ret = vdec_vframe_write_with_dma(vdec, buf, size, 0, handle);
588 if (ret < 0) {
589 v4l_dbg(inst->ctx, V4L_DEBUG_CODEC_ERROR,
590 "write frame data failed. err: %d\n", ret);
591 return ret;
592 }
593
594 /* wait ucode parse ending. */
595 wait_for_completion_timeout(&inst->comp,
596 msecs_to_jiffies(1000));
597
598 return inst->vsi->dec.dpb_sz ? 0 : -1;
599}
600
601static int parse_stream_cpu(struct vdec_h264_inst *inst, u8 *buf, u32 size)
602{
603 int ret = 0;
604 struct h264_param_sets *ps;
605 int nal_idx = 0;
606 bool is_combine = false;
607
608 is_combine = check_frame_combine(buf, size, &nal_idx);
609 if (nal_idx < 0)
610 return -1;
611
612 /* if the st compose from csd + slice that is the combine data. */
613 inst->vsi->is_combine = is_combine;
614 inst->vsi->nalu_pos = nal_idx;
615
616 ps = vzalloc(sizeof(struct h264_param_sets));
617 if (ps == NULL)
618 return -ENOMEM;
619
620 ret = h264_decode_extradata_ps(buf, size, ps);
621 if (ret) {
622 v4l_dbg(inst->ctx, V4L_DEBUG_CODEC_ERROR,
623 "parse extra data failed. err: %d\n", ret);
624 goto out;
625 }
626
627 if (ps->sps_parsed)
628 fill_vdec_params(inst, &ps->sps);
629
630 ret = ps->sps_parsed ? 0 : -1;
631out:
632 vfree(ps);
633
634 return ret;
635}
636
637static int vdec_h264_probe(unsigned long h_vdec,
638 struct aml_vcodec_mem *bs, void *out)
639{
640 struct vdec_h264_inst *inst =
641 (struct vdec_h264_inst *)h_vdec;
642 u8 *buf = (u8 *) bs->vaddr;
643 u32 size = bs->size;
644 int ret = 0;
645
646 if (inst->ctx->is_drm_mode) {
647 if (bs->model == VB2_MEMORY_MMAP) {
648 struct aml_video_stream *s =
649 (struct aml_video_stream *) buf;
650
651 if ((s->magic != AML_VIDEO_MAGIC) &&
652 (s->type != V4L_STREAM_TYPE_MATEDATA))
653 return -1;
654
655 if (inst->ctx->param_sets_from_ucode) {
656 ret = parse_stream_ucode(inst, s->data, s->len);
657 } else {
658 skip_aud_data((u8 **)&s->data, &s->len);
659 ret = parse_stream_cpu(inst, s->data, s->len);
660 }
661 } else if (bs->model == VB2_MEMORY_DMABUF ||
662 bs->model == VB2_MEMORY_USERPTR) {
663 ret = parse_stream_ucode_dma(inst, bs->addr, size,
664 BUFF_IDX(bs, bs->index));
665 }
666 } else {
667 if (inst->ctx->param_sets_from_ucode) {
668 ret = parse_stream_ucode(inst, buf, size);
669 } else {
670 skip_aud_data(&buf, &size);
671 ret = parse_stream_cpu(inst, buf, size);
672 }
673 }
674
675 inst->vsi->cur_pic = inst->vsi->pic;
676
677 return ret;
678}
679
680static void vdec_h264_deinit(unsigned long h_vdec)
681{
682 ulong flags;
683 struct vdec_h264_inst *inst = (struct vdec_h264_inst *)h_vdec;
684 struct aml_vcodec_ctx *ctx = inst->ctx;
685
686 video_decoder_release(&inst->vdec);
687
688 vcodec_vfm_release(&inst->vfm);
689
690 //dump_deinit();
691
692 spin_lock_irqsave(&ctx->slock, flags);
693 if (inst->vsi && inst->vsi->header_buf)
694 kfree(inst->vsi->header_buf);
695
696 if (inst->vsi)
697 kfree(inst->vsi);
698
699 kfree(inst);
700
701 ctx->drv_handle = 0;
702 spin_unlock_irqrestore(&ctx->slock, flags);
703}
704
705static int vdec_h264_get_fb(struct vdec_h264_inst *inst, struct vdec_v4l2_buffer **out)
706{
707 return get_fb_from_queue(inst->ctx, out);
708}
709
710static void vdec_h264_get_vf(struct vdec_h264_inst *inst, struct vdec_v4l2_buffer **out)
711{
712 struct vframe_s *vf = NULL;
713 struct vdec_v4l2_buffer *fb = NULL;
714
715 vf = peek_video_frame(&inst->vfm);
716 if (!vf) {
717 v4l_dbg(inst->ctx, V4L_DEBUG_CODEC_ERROR,
718 "there is no vframe.\n");
719 *out = NULL;
720 return;
721 }
722
723 vf = get_video_frame(&inst->vfm);
724 if (!vf) {
725 v4l_dbg(inst->ctx, V4L_DEBUG_CODEC_ERROR,
726 "the vframe is avalid.\n");
727 *out = NULL;
728 return;
729 }
730
731 atomic_set(&vf->use_cnt, 1);
732
733 fb = (struct vdec_v4l2_buffer *)vf->v4l_mem_handle;
734 if (fb) {
735 fb->vf_handle = (unsigned long)vf;
736 fb->status = FB_ST_DISPLAY;
737 }
738
739 *out = fb;
740
741 //pr_info("%s, %d\n", __func__, fb->base_y.bytes_used);
742 //dump_write(fb->base_y.vaddr, fb->base_y.bytes_used);
743 //dump_write(fb->base_c.vaddr, fb->base_c.bytes_used);
744
745 /* convert yuv format. */
746 //swap_uv(fb->base_c.vaddr, fb->base_c.size);
747}
748
749static int vdec_write_nalu(struct vdec_h264_inst *inst,
750 u8 *buf, u32 size, u64 ts)
751{
752 int ret = -1;
753 struct aml_vdec_adapt *vdec = &inst->vdec;
754 bool is_combine = inst->vsi->is_combine;
755 int nalu_pos;
756 u32 nal_type;
757
758 /*print_hex_debug(buf, size, 32);*/
759
760 nalu_pos = vdec_search_startcode(buf, 16);
761 if (nalu_pos < 0)
762 goto err;
763
764 nal_type = AVC_NAL_TYPE(buf[nalu_pos]);
765 //v4l_dbg(inst->ctx, V4L_DEBUG_CODEC_PRINFO, "NALU type: %d, size: %u\n", nal_type, size);
766
767 if (nal_type == NAL_H264_SPS && !is_combine) {
768 if (inst->vsi->head_offset + size > HEADER_BUFFER_SIZE) {
769 ret = -EILSEQ;
770 goto err;
771 }
772 inst->vsi->sps_size = size;
773 memcpy(inst->vsi->header_buf + inst->vsi->head_offset, buf, size);
774 inst->vsi->head_offset += inst->vsi->sps_size;
775 ret = size;
776 } else if (nal_type == NAL_H264_PPS && !is_combine) {
777 //buf_sz -= nal_start_idx;
778 if (inst->vsi->head_offset + size > HEADER_BUFFER_SIZE) {
779 ret = -EILSEQ;
780 goto err;
781 }
782 inst->vsi->pps_size = size;
783 memcpy(inst->vsi->header_buf + inst->vsi->head_offset, buf, size);
784 inst->vsi->head_offset += inst->vsi->pps_size;
785 ret = size;
786 } else if (nal_type == NAL_H264_SEI && !is_combine) {
787 if (inst->vsi->head_offset + size > HEADER_BUFFER_SIZE) {
788 ret = -EILSEQ;
789 goto err;
790 }
791 inst->vsi->sei_size = size;
792 memcpy(inst->vsi->header_buf + inst->vsi->head_offset, buf, size);
793 inst->vsi->head_offset += inst->vsi->sei_size;
794 ret = size;
795 } else if (inst->vsi->head_offset == 0) {
796 ret = vdec_vframe_write(vdec, buf, size, ts);
797 } else {
798 char *write_buf = vmalloc(inst->vsi->head_offset + size);
799 if (!write_buf) {
800 ret = -ENOMEM;
801 goto err;
802 }
803
804 memcpy(write_buf, inst->vsi->header_buf, inst->vsi->head_offset);
805 memcpy(write_buf + inst->vsi->head_offset, buf, size);
806
807 ret = vdec_vframe_write(vdec, write_buf,
808 inst->vsi->head_offset + size, ts);
809
810 memset(inst->vsi->header_buf, 0, HEADER_BUFFER_SIZE);
811 inst->vsi->head_offset = 0;
812 inst->vsi->sps_size = 0;
813 inst->vsi->pps_size = 0;
814 inst->vsi->sei_size = 0;
815
816 vfree(write_buf);
817 }
818
819 return ret;
820err:
821 v4l_dbg(inst->ctx, V4L_DEBUG_CODEC_ERROR, "err(%d)", ret);
822 return ret;
823}
824
825static bool monitor_res_change(struct vdec_h264_inst *inst, u8 *buf, u32 size)
826{
827 int ret = 0, i = 0, j = 0;
828 u8 *p = buf;
829 int len = size;
830 u32 type;
831
832 for (i = 4; i < size; i++) {
833 j = find_start_code(p, len);
834 if (j > 0) {
835 len = size - (p - buf);
836 type = AVC_NAL_TYPE(p[j]);
837 if (type != NAL_H264_AUD &&
838 (type > NAL_H264_PPS || type < NAL_H264_SEI))
839 break;
840
841 if (type == NAL_H264_SPS) {
842 ret = parse_stream_cpu(inst, p, len);
843 if (ret)
844 break;
845 }
846 p += j;
847 }
848 p++;
849 }
850
851 if (!ret && ((inst->vsi->cur_pic.coded_width !=
852 inst->vsi->pic.coded_width ||
853 inst->vsi->cur_pic.coded_height !=
854 inst->vsi->pic.coded_height) ||
855 (inst->vsi->pic.profile_idc !=
856 inst->vsi->cur_pic.profile_idc) ||
857 (inst->vsi->pic.ref_frame_count !=
858 inst->vsi->cur_pic.ref_frame_count))) {
859 v4l_dbg(inst->ctx, V4L_DEBUG_CODEC_PRINFO, "res change\n");
860 inst->vsi->cur_pic = inst->vsi->pic;
861 return true;
862 }
863
864 return false;
865}
866
867static int vdec_h264_decode(unsigned long h_vdec, struct aml_vcodec_mem *bs,
868 u64 timestamp, bool *res_chg)
869{
870 struct vdec_h264_inst *inst = (struct vdec_h264_inst *)h_vdec;
871 struct aml_vdec_adapt *vdec = &inst->vdec;
872 u8 *buf = (u8 *) bs->vaddr;
873 u32 size = bs->size;
874 int ret = -1;
875
876 if (bs == NULL)
877 return -1;
878
879 if (vdec_input_full(vdec))
880 return -EAGAIN;
881
882 if (inst->ctx->is_drm_mode) {
883 if (bs->model == VB2_MEMORY_MMAP) {
884 struct aml_video_stream *s =
885 (struct aml_video_stream *) buf;
886
887 if (s->magic != AML_VIDEO_MAGIC)
888 return -1;
889
890 if (!inst->ctx->param_sets_from_ucode &&
891 (s->type == V4L_STREAM_TYPE_MATEDATA)) {
892 if ((*res_chg = monitor_res_change(inst,
893 s->data, s->len)))
894 return 0;
895 }
896
897 ret = vdec_vframe_write(vdec,
898 s->data,
899 s->len,
900 timestamp);
901 } else if (bs->model == VB2_MEMORY_DMABUF ||
902 bs->model == VB2_MEMORY_USERPTR) {
903 ret = vdec_vframe_write_with_dma(vdec,
904 bs->addr, size, timestamp,
905 BUFF_IDX(bs, bs->index));
906 }
907 } else {
908 if (inst->ctx->param_sets_from_ucode) {
909 int nal_idx = 0;
910 /* if the st compose from csd + slice that is the combine data. */
911 inst->vsi->is_combine = check_frame_combine(buf, size, &nal_idx);
912 /*if (nal_idx < 0)
913 return -1;*/
914 } else {
915 /*checked whether the resolution changes.*/
916 if ((*res_chg = monitor_res_change(inst, buf, size))) {
917 return 0;
918 }
919 }
920 ret = vdec_write_nalu(inst, buf, size, timestamp);
921 }
922
923 return ret;
924}
925
926static void get_param_config_info(struct vdec_h264_inst *inst,
927 struct aml_dec_params *parms)
928{
929 if (inst->parms.parms_status & V4L2_CONFIG_PARM_DECODE_CFGINFO)
930 parms->cfg = inst->parms.cfg;
931 if (inst->parms.parms_status & V4L2_CONFIG_PARM_DECODE_PSINFO)
932 parms->ps = inst->parms.ps;
933 if (inst->parms.parms_status & V4L2_CONFIG_PARM_DECODE_HDRINFO)
934 parms->hdr = inst->parms.hdr;
935 if (inst->parms.parms_status & V4L2_CONFIG_PARM_DECODE_CNTINFO)
936 parms->cnt = inst->parms.cnt;
937
938 parms->parms_status |= inst->parms.parms_status;
939
940 v4l_dbg(inst->ctx, V4L_DEBUG_CODEC_PRINFO,
941 "parms status: %u\n", parms->parms_status);
942}
943
944static int vdec_h264_get_param(unsigned long h_vdec,
945 enum vdec_get_param_type type, void *out)
946{
947 int ret = 0;
948 struct vdec_h264_inst *inst = (struct vdec_h264_inst *)h_vdec;
949
950 if (!inst) {
951 v4l_dbg(inst->ctx, V4L_DEBUG_CODEC_ERROR,
952 "the h264 inst of dec is invalid.\n");
953 return -1;
954 }
955
956 switch (type) {
957 case GET_PARAM_DISP_FRAME_BUFFER:
958 vdec_h264_get_vf(inst, out);
959 break;
960
961 case GET_PARAM_FREE_FRAME_BUFFER:
962 ret = vdec_h264_get_fb(inst, out);
963 break;
964
965 case GET_PARAM_PIC_INFO:
966 get_pic_info(inst, out);
967 break;
968
969 case GET_PARAM_DPB_SIZE:
970 get_dpb_size(inst, out);
971 break;
972
973 case GET_PARAM_CROP_INFO:
974 get_crop_info(inst, out);
975 break;
976
977 case GET_PARAM_CONFIG_INFO:
978 get_param_config_info(inst, out);
979 break;
980 default:
981 v4l_dbg(inst->ctx, V4L_DEBUG_CODEC_ERROR,
982 "invalid get parameter type=%d\n", type);
983 ret = -EINVAL;
984 }
985
986 return ret;
987}
988
989static void set_param_write_sync(struct vdec_h264_inst *inst)
990{
991 complete(&inst->comp);
992}
993
994static void set_param_ps_info(struct vdec_h264_inst *inst,
995 struct aml_vdec_ps_infos *ps)
996{
997 struct vdec_pic_info *pic = &inst->vsi->pic;
998 struct vdec_h264_dec_info *dec = &inst->vsi->dec;
999 struct v4l2_rect *rect = &inst->vsi->crop;
1000 int dw = inst->parms.cfg.double_write_mode;
1001
1002 /* fill visible area size that be used for EGL. */
1003 pic->visible_width = ps->visible_width;
1004 pic->visible_height = ps->visible_height;
1005
1006 /* calc visible ares. */
1007 rect->left = 0;
1008 rect->top = 0;
1009 rect->width = pic->visible_width;
1010 rect->height = pic->visible_height;
1011
1012 /* config canvas size that be used for decoder. */
1013 pic->coded_width = ps->coded_width;
1014 pic->coded_height = ps->coded_height;
1015 pic->y_len_sz = pic->coded_width * pic->coded_height;
1016 pic->c_len_sz = pic->y_len_sz >> 1;
1017 pic->profile_idc = ps->profile;
1018 pic->ref_frame_count = ps->ref_frames;
1019 dec->dpb_sz = ps->dpb_size;
1020
1021 inst->parms.ps = *ps;
1022 inst->parms.parms_status |=
1023 V4L2_CONFIG_PARM_DECODE_PSINFO;
1024
1025 vdec_config_dw_mode(pic, dw);
1026
1027 /*wake up*/
1028 complete(&inst->comp);
1029
1030 v4l_dbg(inst->ctx, V4L_DEBUG_CODEC_PRINFO,
1031 "Parse from ucode, crop(%d x %d), coded(%d x %d) dpb: %d\n",
1032 ps->visible_width, ps->visible_height,
1033 ps->coded_width, ps->coded_height,
1034 dec->dpb_sz);
1035}
1036
1037static void set_param_hdr_info(struct vdec_h264_inst *inst,
1038 struct aml_vdec_hdr_infos *hdr)
1039{
1040 inst->parms.hdr = *hdr;
1041 if (!(inst->parms.parms_status &
1042 V4L2_CONFIG_PARM_DECODE_HDRINFO)) {
1043 inst->parms.hdr = *hdr;
1044 inst->parms.parms_status |=
1045 V4L2_CONFIG_PARM_DECODE_HDRINFO;
1046 aml_vdec_dispatch_event(inst->ctx,
1047 V4L2_EVENT_SRC_CH_HDRINFO);
1048 v4l_dbg(inst->ctx, V4L_DEBUG_CODEC_PRINFO,
1049 "H264 set HDR infos\n");
1050 }
1051}
1052
1053static void set_param_post_event(struct vdec_h264_inst *inst, u32 *event)
1054{
1055 aml_vdec_dispatch_event(inst->ctx, *event);
1056 v4l_dbg(inst->ctx, V4L_DEBUG_CODEC_PRINFO,
1057 "H264 post event: %d\n", *event);
1058}
1059
1060static int vdec_h264_set_param(unsigned long h_vdec,
1061 enum vdec_set_param_type type, void *in)
1062{
1063 int ret = 0;
1064 struct vdec_h264_inst *inst = (struct vdec_h264_inst *)h_vdec;
1065
1066 if (!inst) {
1067 v4l_dbg(inst->ctx, V4L_DEBUG_CODEC_ERROR,
1068 "the h264 inst of dec is invalid.\n");
1069 return -1;
1070 }
1071
1072 switch (type) {
1073 case SET_PARAM_WRITE_FRAME_SYNC:
1074 set_param_write_sync(inst);
1075 break;
1076
1077 case SET_PARAM_PS_INFO:
1078 set_param_ps_info(inst, in);
1079 break;
1080
1081 case SET_PARAM_HDR_INFO:
1082 set_param_hdr_info(inst, in);
1083 break;
1084
1085 case SET_PARAM_POST_EVENT:
1086 set_param_post_event(inst, in);
1087 break;
1088 default:
1089 v4l_dbg(inst->ctx, V4L_DEBUG_CODEC_ERROR,
1090 "invalid set parameter type=%d\n", type);
1091 ret = -EINVAL;
1092 }
1093
1094 return ret;
1095}
1096
1097static struct vdec_common_if vdec_h264_if = {
1098 .init = vdec_h264_init,
1099 .probe = vdec_h264_probe,
1100 .decode = vdec_h264_decode,
1101 .get_param = vdec_h264_get_param,
1102 .set_param = vdec_h264_set_param,
1103 .deinit = vdec_h264_deinit,
1104};
1105
1106struct vdec_common_if *get_h264_dec_comm_if(void);
1107
1108struct vdec_common_if *get_h264_dec_comm_if(void)
1109{
1110 return &vdec_h264_if;
1111}
1112
generated by cgit at 2024-05-19 18:41:12 (GMT)