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path: root/drivers/frame_provider/decoder/avs/avs.c (plain)
blob: b97cb33d663a8b9539e89f58248222f9354bc001
1/*
2 * drivers/amlogic/amports/vavs.c
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17#define DEBUG
18#include <linux/kernel.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/interrupt.h>
22#include <linux/timer.h>
23#include <linux/kfifo.h>
24#include <linux/delay.h>
25#include <linux/platform_device.h>
26#include <linux/amlogic/media/utils/amstream.h>
27#include <linux/amlogic/media/frame_sync/ptsserv.h>
28#include <linux/amlogic/media/canvas/canvas.h>
29#include <linux/amlogic/media/vfm/vframe_provider.h>
30#include <linux/amlogic/media/vfm/vframe_receiver.h>
31#include <linux/amlogic/media/vfm/vframe.h>
32#include <linux/amlogic/media/utils/vdec_reg.h>
33#include "../../../stream_input/parser/streambuf_reg.h"
34#include "../utils/amvdec.h"
35#include <linux/amlogic/media/registers/register.h>
36#include "../../../stream_input/amports/amports_priv.h"
37#include <linux/dma-mapping.h>
38#include <linux/amlogic/media/codec_mm/codec_mm.h>
39#include <linux/slab.h>
40#include "avs.h"
41#include <linux/amlogic/media/codec_mm/configs.h>
42#include "../utils/decoder_mmu_box.h"
43#include "../utils/decoder_bmmu_box.h"
44#include "../utils/firmware.h"
45#include "../../../common/chips/decoder_cpu_ver_info.h"
46#include <linux/amlogic/tee.h>
47
48
49#define DRIVER_NAME "amvdec_avs"
50#define MODULE_NAME "amvdec_avs"
51
52
53#if 1/* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
54#define NV21
55#endif
56
57#define USE_AVS_SEQ_INFO
58#define HANDLE_AVS_IRQ
59#define DEBUG_PTS
60
61#define I_PICTURE 0
62#define P_PICTURE 1
63#define B_PICTURE 2
64
65/* #define ORI_BUFFER_START_ADDR 0x81000000 */
66#define ORI_BUFFER_START_ADDR 0x80000000
67
68#define INTERLACE_FLAG 0x80
69#define TOP_FIELD_FIRST_FLAG 0x40
70
71/* protocol registers */
72#define AVS_PIC_RATIO AV_SCRATCH_0
73#define AVS_PIC_WIDTH AV_SCRATCH_1
74#define AVS_PIC_HEIGHT AV_SCRATCH_2
75#define AVS_FRAME_RATE AV_SCRATCH_3
76
77#define AVS_ERROR_COUNT AV_SCRATCH_6
78#define AVS_SOS_COUNT AV_SCRATCH_7
79#define AVS_BUFFERIN AV_SCRATCH_8
80#define AVS_BUFFEROUT AV_SCRATCH_9
81#define AVS_REPEAT_COUNT AV_SCRATCH_A
82#define AVS_TIME_STAMP AV_SCRATCH_B
83#define AVS_OFFSET_REG AV_SCRATCH_C
84#define MEM_OFFSET_REG AV_SCRATCH_F
85#define AVS_ERROR_RECOVERY_MODE AV_SCRATCH_G
86
87#define VF_POOL_SIZE 32
88#define PUT_INTERVAL (HZ/100)
89
90#if 1 /*MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8*/
91#define INT_AMVENCODER INT_DOS_MAILBOX_1
92#else
93/* #define AMVENC_DEV_VERSION "AML-MT" */
94#define INT_AMVENCODER INT_MAILBOX_1A
95#endif
96
97
98#define DEC_CONTROL_FLAG_FORCE_2500_1080P_INTERLACE 0x0001
99static u32 dec_control = DEC_CONTROL_FLAG_FORCE_2500_1080P_INTERLACE;
100
101
102#define VPP_VD1_POSTBLEND (1 << 10)
103
104static int debug_flag;
105
106/********************************
107firmware_sel
108 0: use avsp_trans long cabac ucode;
109 1: not use avsp_trans long cabac ucode
110********************************/
111static int firmware_sel;
112static int disable_longcabac_trans = 1;
113
114static int support_user_data = 1;
115
116int avs_get_debug_flag(void)
117{
118 return debug_flag;
119}
120
121static struct vframe_s *vavs_vf_peek(void *);
122static struct vframe_s *vavs_vf_get(void *);
123static void vavs_vf_put(struct vframe_s *, void *);
124static int vavs_vf_states(struct vframe_states *states, void *);
125
126static const char vavs_dec_id[] = "vavs-dev";
127
128#define PROVIDER_NAME "decoder.avs"
129static DEFINE_SPINLOCK(lock);
130static DEFINE_MUTEX(vavs_mutex);
131
132static const struct vframe_operations_s vavs_vf_provider = {
133 .peek = vavs_vf_peek,
134 .get = vavs_vf_get,
135 .put = vavs_vf_put,
136 .vf_states = vavs_vf_states,
137};
138static void *mm_blk_handle;
139static struct vframe_provider_s vavs_vf_prov;
140
141#define VF_BUF_NUM_MAX 16
142#define WORKSPACE_SIZE (4 * SZ_1M)
143
144#ifdef AVSP_LONG_CABAC
145#define MAX_BMMU_BUFFER_NUM (VF_BUF_NUM_MAX + 2)
146#define WORKSPACE_SIZE_A (MAX_CODED_FRAME_SIZE + LOCAL_HEAP_SIZE)
147#else
148#define MAX_BMMU_BUFFER_NUM (VF_BUF_NUM_MAX + 1)
149#endif
150
151#define RV_AI_BUFF_START_ADDR 0x01a00000
152#define LONG_CABAC_RV_AI_BUFF_START_ADDR 0x00000000
153
154static u32 vf_buf_num = 8;
155static u32 vf_buf_num_used;
156static u32 canvas_base = 128;
157#ifdef NV21
158 int canvas_num = 2; /*NV21*/
159#else
160 int canvas_num = 3;
161#endif
162
163
164static struct vframe_s vfpool[VF_POOL_SIZE];
165/*static struct vframe_s vfpool2[VF_POOL_SIZE];*/
166static struct vframe_s *cur_vfpool;
167static unsigned char recover_flag;
168static s32 vfbuf_use[VF_BUF_NUM_MAX];
169static u32 saved_resolution;
170static u32 frame_width, frame_height, frame_dur, frame_prog;
171static struct timer_list recycle_timer;
172static u32 stat;
173static u32 buf_size = 32 * 1024 * 1024;
174static u32 buf_offset;
175static u32 avi_flag;
176static u32 vavs_ratio;
177static u32 pic_type;
178static u32 pts_by_offset = 1;
179static u32 total_frame;
180static u32 next_pts;
181static unsigned char throw_pb_flag;
182#ifdef DEBUG_PTS
183static u32 pts_hit, pts_missed, pts_i_hit, pts_i_missed;
184#endif
185
186static u32 radr, rval;
187static struct dec_sysinfo vavs_amstream_dec_info;
188static struct vdec_info *gvs;
189static u32 fr_hint_status;
190static struct work_struct notify_work;
191static struct work_struct set_clk_work;
192static bool is_reset;
193
194static struct vdec_s *vdec;
195
196#ifdef AVSP_LONG_CABAC
197static struct work_struct long_cabac_wd_work;
198void *es_write_addr_virt;
199dma_addr_t es_write_addr_phy;
200
201void *bitstream_read_tmp;
202dma_addr_t bitstream_read_tmp_phy;
203void *avsp_heap_adr;
204static uint long_cabac_busy;
205#endif
206
207
208static void *user_data_buffer;
209static dma_addr_t user_data_buffer_phys;
210
211static DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
212static DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
213static DECLARE_KFIFO(recycle_q, struct vframe_s *, VF_POOL_SIZE);
214
215static inline u32 index2canvas(u32 index)
216{
217 const u32 canvas_tab[VF_BUF_NUM_MAX] = {
218 0x010100, 0x030302, 0x050504, 0x070706,
219 0x090908, 0x0b0b0a, 0x0d0d0c, 0x0f0f0e,
220 0x111110, 0x131312, 0x151514, 0x171716,
221 0x191918, 0x1b1b1a, 0x1d1d1c, 0x1f1f1e,
222 };
223 const u32 canvas_tab_3[4] = {
224 0x010100, 0x040403, 0x070706, 0x0a0a09
225 };
226
227 if (canvas_num == 2)
228 return canvas_tab[index] + (canvas_base << 16)
229 + (canvas_base << 8) + canvas_base;
230
231 return canvas_tab_3[index] + (canvas_base << 16)
232 + (canvas_base << 8) + canvas_base;
233}
234
235static const u32 frame_rate_tab[16] = {
236 96000 / 30, /* forbidden */
237 96000000 / 23976, /* 24000/1001 (23.967) */
238 96000 / 24,
239 96000 / 25,
240 9600000 / 2997, /* 30000/1001 (29.97) */
241 96000 / 30,
242 96000 / 50,
243 9600000 / 5994, /* 60000/1001 (59.94) */
244 96000 / 60,
245 /* > 8 reserved, use 24 */
246 96000 / 24, 96000 / 24, 96000 / 24, 96000 / 24,
247 96000 / 24, 96000 / 24, 96000 / 24
248};
249
250static void set_frame_info(struct vframe_s *vf, unsigned int *duration)
251{
252 int ar = 0;
253
254 unsigned int pixel_ratio = READ_VREG(AVS_PIC_RATIO);
255#ifndef USE_AVS_SEQ_INFO
256 if (vavs_amstream_dec_info.width > 0
257 && vavs_amstream_dec_info.height > 0) {
258 vf->width = vavs_amstream_dec_info.width;
259 vf->height = vavs_amstream_dec_info.height;
260 } else
261#endif
262 {
263 vf->width = READ_VREG(AVS_PIC_WIDTH);
264 vf->height = READ_VREG(AVS_PIC_HEIGHT);
265 frame_width = vf->width;
266 frame_height = vf->height;
267 /* pr_info("%s: (%d,%d)\n", __func__,vf->width, vf->height);*/
268 }
269
270#ifndef USE_AVS_SEQ_INFO
271 if (vavs_amstream_dec_info.rate > 0)
272 *duration = vavs_amstream_dec_info.rate;
273 else
274#endif
275 {
276 *duration = frame_rate_tab[READ_VREG(AVS_FRAME_RATE) & 0xf];
277 /* pr_info("%s: duration = %d\n", __func__, *duration); */
278 frame_dur = *duration;
279 schedule_work(&notify_work);
280 }
281
282 if (vavs_ratio == 0) {
283 /* always stretch to 16:9 */
284 vf->ratio_control |= (0x90 <<
285 DISP_RATIO_ASPECT_RATIO_BIT);
286 } else {
287 switch (pixel_ratio) {
288 case 1:
289 ar = (vf->height * vavs_ratio) / vf->width;
290 break;
291 case 2:
292 ar = (vf->height * 3 * vavs_ratio) / (vf->width * 4);
293 break;
294 case 3:
295 ar = (vf->height * 9 * vavs_ratio) / (vf->width * 16);
296 break;
297 case 4:
298 ar = (vf->height * 100 * vavs_ratio) / (vf->width *
299 221);
300 break;
301 default:
302 ar = (vf->height * vavs_ratio) / vf->width;
303 break;
304 }
305 }
306
307 ar = min(ar, DISP_RATIO_ASPECT_RATIO_MAX);
308
309 vf->ratio_control = (ar << DISP_RATIO_ASPECT_RATIO_BIT);
310 /*vf->ratio_control |= DISP_RATIO_FORCECONFIG | DISP_RATIO_KEEPRATIO; */
311
312 vf->flag = 0;
313}
314
315
316static struct work_struct userdata_push_work;
317/*
318#define DUMP_LAST_REPORTED_USER_DATA
319*/
320static void userdata_push_do_work(struct work_struct *work)
321{
322 unsigned int user_data_flags;
323 unsigned int user_data_wp;
324 unsigned int user_data_length;
325 struct userdata_poc_info_t user_data_poc;
326#ifdef DUMP_LAST_REPORTED_USER_DATA
327 int user_data_len;
328 int wp_start;
329 unsigned char *pdata;
330 int nLeft;
331#endif
332
333 user_data_flags = READ_VREG(AV_SCRATCH_N);
334 user_data_wp = (user_data_flags >> 16) & 0xffff;
335 user_data_length = user_data_flags & 0x7fff;
336
337#ifdef DUMP_LAST_REPORTED_USER_DATA
338 dma_sync_single_for_cpu(amports_get_dma_device(),
339 user_data_buffer_phys, USER_DATA_SIZE,
340 DMA_FROM_DEVICE);
341
342 if (user_data_length & 0x07)
343 user_data_len = (user_data_length + 8) & 0xFFFFFFF8;
344 else
345 user_data_len = user_data_length;
346
347 if (user_data_wp >= user_data_len) {
348 wp_start = user_data_wp - user_data_len;
349
350 pdata = (unsigned char *)user_data_buffer;
351 pdata += wp_start;
352 nLeft = user_data_len;
353 while (nLeft >= 8) {
354 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
355 pdata[0], pdata[1], pdata[2], pdata[3],
356 pdata[4], pdata[5], pdata[6], pdata[7]);
357 nLeft -= 8;
358 pdata += 8;
359 }
360 } else {
361 wp_start = user_data_wp +
362 USER_DATA_SIZE - user_data_len;
363
364 pdata = (unsigned char *)user_data_buffer;
365 pdata += wp_start;
366 nLeft = USER_DATA_SIZE - wp_start;
367
368 while (nLeft >= 8) {
369 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
370 pdata[0], pdata[1], pdata[2], pdata[3],
371 pdata[4], pdata[5], pdata[6], pdata[7]);
372 nLeft -= 8;
373 pdata += 8;
374 }
375
376 pdata = (unsigned char *)user_data_buffer;
377 nLeft = user_data_wp;
378 while (nLeft >= 8) {
379 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
380 pdata[0], pdata[1], pdata[2], pdata[3],
381 pdata[4], pdata[5], pdata[6], pdata[7]);
382 nLeft -= 8;
383 pdata += 8;
384 }
385 }
386#endif
387
388/*
389 pr_info("pocinfo 0x%x, poc %d, wp 0x%x, len %d\n",
390 READ_VREG(AV_SCRATCH_L), READ_VREG(AV_SCRATCH_M),
391 user_data_wp, user_data_length);
392*/
393 user_data_poc.poc_info = READ_VREG(AV_SCRATCH_L);
394 user_data_poc.poc_number = READ_VREG(AV_SCRATCH_M);
395
396 WRITE_VREG(AV_SCRATCH_N, 0);
397/*
398 wakeup_userdata_poll(user_data_poc, user_data_wp,
399 (unsigned long)user_data_buffer,
400 USER_DATA_SIZE, user_data_length);
401*/
402}
403
404static void UserDataHandler(void)
405{
406 unsigned int user_data_flags;
407
408 user_data_flags = READ_VREG(AV_SCRATCH_N);
409 if (user_data_flags & (1 << 15)) { /* data ready */
410 schedule_work(&userdata_push_work);
411 }
412}
413
414
415#ifdef HANDLE_AVS_IRQ
416static irqreturn_t vavs_isr(int irq, void *dev_id)
417#else
418static void vavs_isr(void)
419#endif
420{
421 u32 reg;
422 struct vframe_s *vf;
423 u32 dur;
424 u32 repeat_count;
425 u32 picture_type;
426 u32 buffer_index;
427 u32 frame_size;
428 bool force_interlaced_frame = false;
429 unsigned int pts, pts_valid = 0, offset = 0;
430 u64 pts_us64;
431 if (debug_flag & AVS_DEBUG_UCODE) {
432 if (READ_VREG(AV_SCRATCH_E) != 0) {
433 pr_info("dbg%x: %x\n", READ_VREG(AV_SCRATCH_E),
434 READ_VREG(AV_SCRATCH_D));
435 WRITE_VREG(AV_SCRATCH_E, 0);
436 }
437 }
438#ifdef AVSP_LONG_CABAC
439 if (firmware_sel == 0 && READ_VREG(LONG_CABAC_REQ)) {
440#ifdef PERFORMANCE_DEBUG
441 pr_info("%s:schedule long_cabac_wd_work\r\n", __func__);
442#endif
443 pr_info("schedule long_cabac_wd_work and requested from %d\n",
444 (READ_VREG(LONG_CABAC_REQ) >> 8)&0xFF);
445 schedule_work(&long_cabac_wd_work);
446 }
447#endif
448
449
450 UserDataHandler();
451
452 reg = READ_VREG(AVS_BUFFEROUT);
453
454 if (reg) {
455 if (debug_flag & AVS_DEBUG_PRINT)
456 pr_info("AVS_BUFFEROUT=%x\n", reg);
457 if (pts_by_offset) {
458 offset = READ_VREG(AVS_OFFSET_REG);
459 if (debug_flag & AVS_DEBUG_PRINT)
460 pr_info("AVS OFFSET=%x\n", offset);
461 if (pts_lookup_offset_us64(PTS_TYPE_VIDEO, offset, &pts,
462 &frame_size,
463 0, &pts_us64) == 0) {
464 pts_valid = 1;
465#ifdef DEBUG_PTS
466 pts_hit++;
467#endif
468 } else {
469#ifdef DEBUG_PTS
470 pts_missed++;
471#endif
472 }
473 }
474
475 repeat_count = READ_VREG(AVS_REPEAT_COUNT);
476 if (firmware_sel == 0)
477 buffer_index =
478 ((reg & 0x7) +
479 (((reg >> 8) & 0x3) << 3) - 1) & 0x1f;
480 else
481 buffer_index =
482 ((reg & 0x7) - 1) & 7;
483
484 picture_type = (reg >> 3) & 7;
485#ifdef DEBUG_PTS
486 if (picture_type == I_PICTURE) {
487 /* pr_info("I offset 0x%x, pts_valid %d\n",
488 * offset, pts_valid);
489 */
490 if (!pts_valid)
491 pts_i_missed++;
492 else
493 pts_i_hit++;
494 }
495#endif
496
497 if ((dec_control & DEC_CONTROL_FLAG_FORCE_2500_1080P_INTERLACE)
498 && frame_width == 1920 && frame_height == 1080) {
499 force_interlaced_frame = true;
500 }
501
502 if (throw_pb_flag && picture_type != I_PICTURE) {
503
504 if (debug_flag & AVS_DEBUG_PRINT) {
505 pr_info("picture type %d throwed\n",
506 picture_type);
507 }
508 WRITE_VREG(AVS_BUFFERIN, ~(1 << buffer_index));
509 } else if (reg & INTERLACE_FLAG || force_interlaced_frame) { /* interlace */
510 throw_pb_flag = 0;
511
512 if (debug_flag & AVS_DEBUG_PRINT) {
513 pr_info("interlace, picture type %d\n",
514 picture_type);
515 }
516
517 if (kfifo_get(&newframe_q, &vf) == 0) {
518 pr_info
519 ("fatal error, no available buffer slot.");
520 return IRQ_HANDLED;
521 }
522 set_frame_info(vf, &dur);
523 vf->bufWidth = 1920;
524 pic_type = 2;
525 if ((picture_type == I_PICTURE) && pts_valid) {
526 vf->pts = pts;
527 if ((repeat_count > 1) && avi_flag) {
528 /* next_pts = pts +
529 * (vavs_amstream_dec_info.rate *
530 * repeat_count >> 1)*15/16;
531 */
532 next_pts =
533 pts +
534 (dur * repeat_count >> 1) *
535 15 / 16;
536 } else
537 next_pts = 0;
538 } else {
539 vf->pts = next_pts;
540 if ((repeat_count > 1) && avi_flag) {
541 /* vf->duration =
542 * vavs_amstream_dec_info.rate *
543 * repeat_count >> 1;
544 */
545 vf->duration = dur * repeat_count >> 1;
546 if (next_pts != 0) {
547 next_pts +=
548 ((vf->duration) -
549 ((vf->duration) >> 4));
550 }
551 } else {
552 /* vf->duration =
553 * vavs_amstream_dec_info.rate >> 1;
554 */
555 vf->duration = dur >> 1;
556 next_pts = 0;
557 }
558 }
559 vf->signal_type = 0;
560 vf->index = buffer_index;
561 vf->duration_pulldown = 0;
562 if (force_interlaced_frame) {
563 vf->type = VIDTYPE_INTERLACE_TOP;
564 }else{
565 vf->type =
566 (reg & TOP_FIELD_FIRST_FLAG)
567 ? VIDTYPE_INTERLACE_TOP
568 : VIDTYPE_INTERLACE_BOTTOM;
569 }
570#ifdef NV21
571 vf->type |= VIDTYPE_VIU_NV21;
572#endif
573 vf->canvas0Addr = vf->canvas1Addr =
574 index2canvas(buffer_index);
575 vf->type_original = vf->type;
576
577 if (debug_flag & AVS_DEBUG_PRINT) {
578 pr_info("buffer_index %d, canvas addr %x\n",
579 buffer_index, vf->canvas0Addr);
580 }
581 vf->pts = (pts_valid)?pts:0;
582 vf->pts_us64 = (pts_valid) ? pts_us64 : 0;
583 vfbuf_use[buffer_index]++;
584 vf->mem_handle =
585 decoder_bmmu_box_get_mem_handle(
586 mm_blk_handle,
587 buffer_index);
588 decoder_do_frame_check(NULL, vf);
589 kfifo_put(&display_q,
590 (const struct vframe_s *)vf);
591 ATRACE_COUNTER(MODULE_NAME, vf->pts);
592 vf_notify_receiver(PROVIDER_NAME,
593 VFRAME_EVENT_PROVIDER_VFRAME_READY,
594 NULL);
595
596 if (kfifo_get(&newframe_q, &vf) == 0) {
597 pr_info("fatal error, no available buffer slot.");
598 return IRQ_HANDLED;
599 }
600 set_frame_info(vf, &dur);
601 vf->bufWidth = 1920;
602 if (force_interlaced_frame)
603 vf->pts = 0;
604 else
605 vf->pts = next_pts;
606
607 if ((repeat_count > 1) && avi_flag) {
608 /* vf->duration = vavs_amstream_dec_info.rate *
609 * repeat_count >> 1;
610 */
611 vf->duration = dur * repeat_count >> 1;
612 if (next_pts != 0) {
613 next_pts +=
614 ((vf->duration) -
615 ((vf->duration) >> 4));
616 }
617 } else {
618 /* vf->duration = vavs_amstream_dec_info.rate
619 * >> 1;
620 */
621 vf->duration = dur >> 1;
622 next_pts = 0;
623 }
624 vf->signal_type = 0;
625 vf->index = buffer_index;
626 vf->duration_pulldown = 0;
627 if (force_interlaced_frame) {
628 vf->type = VIDTYPE_INTERLACE_BOTTOM;
629 } else {
630 vf->type =
631 (reg & TOP_FIELD_FIRST_FLAG) ?
632 VIDTYPE_INTERLACE_BOTTOM :
633 VIDTYPE_INTERLACE_TOP;
634 }
635#ifdef NV21
636 vf->type |= VIDTYPE_VIU_NV21;
637#endif
638 vf->canvas0Addr = vf->canvas1Addr =
639 index2canvas(buffer_index);
640 vf->type_original = vf->type;
641 vf->pts_us64 = 0;
642 vfbuf_use[buffer_index]++;
643 vf->mem_handle =
644 decoder_bmmu_box_get_mem_handle(
645 mm_blk_handle,
646 buffer_index);
647 kfifo_put(&display_q,
648 (const struct vframe_s *)vf);
649 ATRACE_COUNTER(MODULE_NAME, vf->pts);
650 vf_notify_receiver(PROVIDER_NAME,
651 VFRAME_EVENT_PROVIDER_VFRAME_READY,
652 NULL);
653 total_frame++;
654 } else { /* progressive */
655 throw_pb_flag = 0;
656
657 if (debug_flag & AVS_DEBUG_PRINT) {
658 pr_info("progressive picture type %d\n",
659 picture_type);
660 }
661 if (kfifo_get(&newframe_q, &vf) == 0) {
662 pr_info
663 ("fatal error, no available buffer slot.");
664 return IRQ_HANDLED;
665 }
666 set_frame_info(vf, &dur);
667 vf->bufWidth = 1920;
668 pic_type = 1;
669
670 if ((picture_type == I_PICTURE) && pts_valid) {
671 vf->pts = pts;
672 if ((repeat_count > 1) && avi_flag) {
673 /* next_pts = pts +
674 * (vavs_amstream_dec_info.rate *
675 * repeat_count)*15/16;
676 */
677 next_pts =
678 pts +
679 (dur * repeat_count) * 15 / 16;
680 } else
681 next_pts = 0;
682 } else {
683 vf->pts = next_pts;
684 if ((repeat_count > 1) && avi_flag) {
685 /* vf->duration =
686 * vavs_amstream_dec_info.rate *
687 * repeat_count;
688 */
689 vf->duration = dur * repeat_count;
690 if (next_pts != 0) {
691 next_pts +=
692 ((vf->duration) -
693 ((vf->duration) >> 4));
694 }
695 } else {
696 /* vf->duration =
697 * vavs_amstream_dec_info.rate;
698 */
699 vf->duration = dur;
700 next_pts = 0;
701 }
702 }
703 vf->signal_type = 0;
704 vf->index = buffer_index;
705 vf->duration_pulldown = 0;
706 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD;
707#ifdef NV21
708 vf->type |= VIDTYPE_VIU_NV21;
709#endif
710 vf->canvas0Addr = vf->canvas1Addr =
711 index2canvas(buffer_index);
712 vf->type_original = vf->type;
713 vf->pts = (pts_valid)?pts:0;
714 vf->pts_us64 = (pts_valid) ? pts_us64 : 0;
715 if (debug_flag & AVS_DEBUG_PRINT) {
716 pr_info("buffer_index %d, canvas addr %x\n",
717 buffer_index, vf->canvas0Addr
718 );
719 pr_info("PicType = %d, PTS = 0x%x\n",
720 picture_type, vf->pts);
721 }
722
723 vfbuf_use[buffer_index]++;
724 vf->mem_handle =
725 decoder_bmmu_box_get_mem_handle(
726 mm_blk_handle,
727 buffer_index);
728 decoder_do_frame_check(NULL, vf);
729
730 kfifo_put(&display_q,
731 (const struct vframe_s *)vf);
732 ATRACE_COUNTER(MODULE_NAME, vf->pts);
733 vf_notify_receiver(PROVIDER_NAME,
734 VFRAME_EVENT_PROVIDER_VFRAME_READY,
735 NULL);
736 total_frame++;
737 }
738
739 /*count info*/
740 gvs->frame_dur = frame_dur;
741 vdec_count_info(gvs, 0, offset);
742
743 /* pr_info("PicType = %d, PTS = 0x%x\n",
744 * picture_type, vf->pts);
745 */
746 WRITE_VREG(AVS_BUFFEROUT, 0);
747 }
748 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
749
750#ifdef HANDLE_AVS_IRQ
751 return IRQ_HANDLED;
752#else
753 return;
754#endif
755}
756/*
757 *static int run_flag = 1;
758 *static int step_flag;
759 */
760static int error_recovery_mode; /*0: blocky 1: mosaic*/
761/*
762 *static uint error_watchdog_threshold=10;
763 *static uint error_watchdog_count;
764 *static uint error_watchdog_buf_threshold = 0x4000000;
765 */
766
767static struct vframe_s *vavs_vf_peek(void *op_arg)
768{
769 struct vframe_s *vf;
770
771 if (recover_flag)
772 return NULL;
773
774 if (kfifo_peek(&display_q, &vf))
775 return vf;
776
777 return NULL;
778
779}
780
781static struct vframe_s *vavs_vf_get(void *op_arg)
782{
783 struct vframe_s *vf;
784
785 if (recover_flag)
786 return NULL;
787
788 if (kfifo_get(&display_q, &vf))
789 return vf;
790
791 return NULL;
792
793}
794
795static void vavs_vf_put(struct vframe_s *vf, void *op_arg)
796{
797 int i;
798
799 if (recover_flag)
800 return;
801
802 for (i = 0; i < VF_POOL_SIZE; i++) {
803 if (vf == &cur_vfpool[i])
804 break;
805 }
806 if (i < VF_POOL_SIZE)
807 kfifo_put(&recycle_q, (const struct vframe_s *)vf);
808
809}
810
811int vavs_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
812{
813 if (!(stat & STAT_VDEC_RUN))
814 return -1;
815
816 vstatus->frame_width = frame_width;
817 vstatus->frame_height = frame_height;
818 if (frame_dur != 0)
819 vstatus->frame_rate = 96000 / frame_dur;
820 else
821 vstatus->frame_rate = -1;
822 vstatus->error_count = READ_VREG(AV_SCRATCH_C);
823 vstatus->status = stat;
824 vstatus->bit_rate = gvs->bit_rate;
825 vstatus->frame_dur = frame_dur;
826 vstatus->frame_data = gvs->frame_data;
827 vstatus->total_data = gvs->total_data;
828 vstatus->frame_count = gvs->frame_count;
829 vstatus->error_frame_count = gvs->error_frame_count;
830 vstatus->drop_frame_count = gvs->drop_frame_count;
831 vstatus->total_data = gvs->total_data;
832 vstatus->samp_cnt = gvs->samp_cnt;
833 vstatus->offset = gvs->offset;
834 snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
835 "%s", DRIVER_NAME);
836
837 return 0;
838}
839
840int vavs_set_isreset(struct vdec_s *vdec, int isreset)
841{
842 is_reset = isreset;
843 return 0;
844}
845
846static int vavs_vdec_info_init(void)
847{
848 gvs = kzalloc(sizeof(struct vdec_info), GFP_KERNEL);
849 if (NULL == gvs) {
850 pr_info("the struct of vdec status malloc failed.\n");
851 return -ENOMEM;
852 }
853 return 0;
854}
855/****************************************/
856static int vavs_canvas_init(void)
857{
858 int i, ret;
859 u32 canvas_width, canvas_height;
860 u32 decbuf_size, decbuf_y_size, decbuf_uv_size;
861 unsigned long buf_start;
862 int need_alloc_buf_num;
863 u32 endian;
864
865 vf_buf_num_used = vf_buf_num;
866 if (buf_size <= 0x00400000) {
867 /* SD only */
868 canvas_width = 768;
869 canvas_height = 576;
870 decbuf_y_size = 0x80000;
871 decbuf_uv_size = 0x20000;
872 decbuf_size = 0x100000;
873 } else {
874 /* HD & SD */
875 canvas_width = 1920;
876 canvas_height = 1088;
877 decbuf_y_size = 0x200000;
878 decbuf_uv_size = 0x80000;
879 decbuf_size = 0x300000;
880 }
881
882#ifdef AVSP_LONG_CABAC
883 need_alloc_buf_num = vf_buf_num_used + 2;
884#else
885 need_alloc_buf_num = vf_buf_num_used + 1;
886#endif
887 for (i = 0; i < need_alloc_buf_num; i++) {
888
889 if (i == (need_alloc_buf_num - 1))
890 decbuf_size = WORKSPACE_SIZE;
891#ifdef AVSP_LONG_CABAC
892 else if (i == (need_alloc_buf_num - 2))
893 decbuf_size = WORKSPACE_SIZE_A;
894#endif
895 ret = decoder_bmmu_box_alloc_buf_phy(mm_blk_handle, i,
896 decbuf_size, DRIVER_NAME, &buf_start);
897 if (ret < 0)
898 return ret;
899 if (i == (need_alloc_buf_num - 1)) {
900 if (firmware_sel == 1)
901 buf_offset = buf_start -
902 RV_AI_BUFF_START_ADDR;
903 else
904 buf_offset = buf_start -
905 LONG_CABAC_RV_AI_BUFF_START_ADDR;
906 continue;
907 }
908#ifdef AVSP_LONG_CABAC
909 else if (i == (need_alloc_buf_num - 2)) {
910 avsp_heap_adr = codec_mm_phys_to_virt(buf_start);
911 continue;
912 }
913#endif
914 if (vdec->canvas_mode == CANVAS_BLKMODE_LINEAR)
915 endian = 7;
916 else
917 endian = 0;
918#ifdef NV21
919 canvas_config_ex(canvas_base + canvas_num * i + 0,
920 buf_start,
921 canvas_width, canvas_height,
922 CANVAS_ADDR_NOWRAP,
923 vdec->canvas_mode, endian);
924 canvas_config_ex(canvas_base + canvas_num * i + 1,
925 buf_start +
926 decbuf_y_size, canvas_width,
927 canvas_height / 2,
928 CANVAS_ADDR_NOWRAP,
929 vdec->canvas_mode, endian);
930#else
931 canvas_config_ex(canvas_num * i + 0,
932 buf_start,
933 canvas_width, canvas_height,
934 CANVAS_ADDR_NOWRAP,
935 vdec->canvas_mode, endian);
936 canvas_config_ex(canvas_num * i + 1,
937 buf_start +
938 decbuf_y_size, canvas_width / 2,
939 canvas_height / 2,
940 CANVAS_ADDR_NOWRAP,
941 vdec->canvas_mode, endian);
942 canvas_config_ex(canvas_num * i + 2,
943 buf_start +
944 decbuf_y_size + decbuf_uv_size,
945 canvas_width / 2, canvas_height / 2,
946 CANVAS_ADDR_NOWRAP,
947 vdec->canvas_mode, endian);
948#endif
949 if (debug_flag & AVS_DEBUG_PRINT) {
950 pr_info("canvas config %d, addr %p\n", i,
951 (void *)buf_start);
952 }
953
954 }
955 return 0;
956}
957
958void vavs_recover(void)
959{
960 vavs_canvas_init();
961
962 WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6) | (1 << 4));
963 WRITE_VREG(DOS_SW_RESET0, 0);
964
965 READ_VREG(DOS_SW_RESET0);
966
967 WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6) | (1 << 4));
968 WRITE_VREG(DOS_SW_RESET0, 0);
969
970 WRITE_VREG(DOS_SW_RESET0, (1 << 9) | (1 << 8));
971 WRITE_VREG(DOS_SW_RESET0, 0);
972 WRITE_VREG(AV_SCRATCH_H, 0);
973 if (firmware_sel == 1) {
974 WRITE_VREG(POWER_CTL_VLD, 0x10);
975 WRITE_VREG_BITS(VLD_MEM_VIFIFO_CONTROL, 2,
976 MEM_FIFO_CNT_BIT, 2);
977 WRITE_VREG_BITS(VLD_MEM_VIFIFO_CONTROL, 8,
978 MEM_LEVEL_CNT_BIT, 6);
979 WRITE_VREG(AV_SCRATCH_H, 1); // 8 buf flag to ucode
980 }
981
982
983 if (firmware_sel == 0) {
984 /* fixed canvas index */
985 WRITE_VREG(AV_SCRATCH_0, canvas_base);
986 WRITE_VREG(AV_SCRATCH_1, vf_buf_num_used);
987 } else {
988 int ii;
989
990 for (ii = 0; ii < 4; ii++) {
991 WRITE_VREG(AV_SCRATCH_0 + ii,
992 (canvas_base + canvas_num * ii) |
993 ((canvas_base + canvas_num * ii + 1)
994 << 8) |
995 ((canvas_base + canvas_num * ii + 1)
996 << 16)
997 );
998 }
999 }
1000
1001 /* notify ucode the buffer offset */
1002 WRITE_VREG(AV_SCRATCH_F, buf_offset);
1003
1004 /* disable PSCALE for hardware sharing */
1005 WRITE_VREG(PSCALE_CTRL, 0);
1006
1007 WRITE_VREG(AVS_SOS_COUNT, 0);
1008 WRITE_VREG(AVS_BUFFERIN, 0);
1009 WRITE_VREG(AVS_BUFFEROUT, 0);
1010 if (error_recovery_mode)
1011 WRITE_VREG(AVS_ERROR_RECOVERY_MODE, 0);
1012 else
1013 WRITE_VREG(AVS_ERROR_RECOVERY_MODE, 1);
1014 /* clear mailbox interrupt */
1015 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
1016
1017 /* enable mailbox interrupt */
1018 WRITE_VREG(ASSIST_MBOX1_MASK, 1);
1019#if 1 /* def DEBUG_UCODE */
1020 WRITE_VREG(AV_SCRATCH_D, 0);
1021#endif
1022
1023#ifdef NV21
1024 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 17);
1025#endif
1026
1027#ifdef PIC_DC_NEED_CLEAR
1028 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 31);
1029#endif
1030
1031#ifdef AVSP_LONG_CABAC
1032 if (firmware_sel == 0) {
1033 WRITE_VREG(LONG_CABAC_DES_ADDR, es_write_addr_phy);
1034 WRITE_VREG(LONG_CABAC_REQ, 0);
1035 WRITE_VREG(LONG_CABAC_PIC_SIZE, 0);
1036 WRITE_VREG(LONG_CABAC_SRC_ADDR, 0);
1037 }
1038#endif
1039 WRITE_VREG(AV_SCRATCH_N, (u32)(user_data_buffer_phys - buf_offset));
1040 pr_info("support_user_data = %d\n", support_user_data);
1041 if (support_user_data)
1042 WRITE_VREG(AV_SCRATCH_M, 1);
1043 else
1044 WRITE_VREG(AV_SCRATCH_M, 0);
1045
1046 WRITE_VREG(AV_SCRATCH_5, 0);
1047
1048}
1049
1050static int vavs_prot_init(void)
1051{
1052 int r;
1053#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
1054 WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6) | (1 << 4));
1055 WRITE_VREG(DOS_SW_RESET0, 0);
1056
1057 READ_VREG(DOS_SW_RESET0);
1058
1059 WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6) | (1 << 4));
1060 WRITE_VREG(DOS_SW_RESET0, 0);
1061
1062 WRITE_VREG(DOS_SW_RESET0, (1 << 9) | (1 << 8));
1063 WRITE_VREG(DOS_SW_RESET0, 0);
1064
1065#else
1066 WRITE_RESET_REG(RESET0_REGISTER,
1067 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
1068 READ_RESET_REG(RESET0_REGISTER);
1069 WRITE_RESET_REG(RESET0_REGISTER,
1070 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
1071
1072 WRITE_RESET_REG(RESET2_REGISTER, RESET_PIC_DC | RESET_DBLK);
1073#endif
1074
1075 /***************** reset vld **********************************/
1076 WRITE_VREG(POWER_CTL_VLD, 0x10);
1077 WRITE_VREG_BITS(VLD_MEM_VIFIFO_CONTROL, 2, MEM_FIFO_CNT_BIT, 2);
1078 WRITE_VREG_BITS(VLD_MEM_VIFIFO_CONTROL, 8, MEM_LEVEL_CNT_BIT, 6);
1079 /*************************************************************/
1080
1081 r = vavs_canvas_init();
1082 WRITE_VREG(AV_SCRATCH_H, 0);
1083#ifdef NV21
1084 if (firmware_sel == 0) {
1085 /* fixed canvas index */
1086 WRITE_VREG(AV_SCRATCH_0, canvas_base);
1087 WRITE_VREG(AV_SCRATCH_1, vf_buf_num_used);
1088 } else {
1089 int ii;
1090
1091 for (ii = 0; ii < 4; ii++) {
1092 WRITE_VREG(AV_SCRATCH_0 + ii,
1093 (canvas_base + canvas_num * ii) |
1094 ((canvas_base + canvas_num * ii + 1)
1095 << 8) |
1096 ((canvas_base + canvas_num * ii + 1)
1097 << 16)
1098 );
1099 }
1100 WRITE_VREG(AV_SCRATCH_H, 1); // 8 buf flag to ucode
1101 }
1102#else
1103 /* index v << 16 | u << 8 | y */
1104 WRITE_VREG(AV_SCRATCH_0, 0x020100);
1105 WRITE_VREG(AV_SCRATCH_1, 0x050403);
1106 WRITE_VREG(AV_SCRATCH_2, 0x080706);
1107 WRITE_VREG(AV_SCRATCH_3, 0x0b0a09);
1108#endif
1109 /* notify ucode the buffer offset */
1110 WRITE_VREG(AV_SCRATCH_F, buf_offset);
1111
1112 /* disable PSCALE for hardware sharing */
1113 WRITE_VREG(PSCALE_CTRL, 0);
1114
1115 WRITE_VREG(AVS_SOS_COUNT, 0);
1116 WRITE_VREG(AVS_BUFFERIN, 0);
1117 WRITE_VREG(AVS_BUFFEROUT, 0);
1118 if (error_recovery_mode)
1119 WRITE_VREG(AVS_ERROR_RECOVERY_MODE, 0);
1120 else
1121 WRITE_VREG(AVS_ERROR_RECOVERY_MODE, 1);
1122 /* clear mailbox interrupt */
1123 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
1124
1125 /* enable mailbox interrupt */
1126 WRITE_VREG(ASSIST_MBOX1_MASK, 1);
1127#if 1 /* def DEBUG_UCODE */
1128 WRITE_VREG(AV_SCRATCH_D, 0);
1129#endif
1130
1131#ifdef NV21
1132 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 17);
1133#endif
1134
1135#ifdef PIC_DC_NEED_CLEAR
1136 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 31);
1137#endif
1138
1139#ifdef AVSP_LONG_CABAC
1140 if (firmware_sel == 0) {
1141 WRITE_VREG(LONG_CABAC_DES_ADDR, es_write_addr_phy);
1142 WRITE_VREG(LONG_CABAC_REQ, 0);
1143 WRITE_VREG(LONG_CABAC_PIC_SIZE, 0);
1144 WRITE_VREG(LONG_CABAC_SRC_ADDR, 0);
1145 }
1146#endif
1147
1148 WRITE_VREG(AV_SCRATCH_N, (u32)(user_data_buffer_phys - buf_offset));
1149 pr_info("support_user_data = %d\n", support_user_data);
1150 if (support_user_data)
1151 WRITE_VREG(AV_SCRATCH_M, 1);
1152 else
1153 WRITE_VREG(AV_SCRATCH_M, 0);
1154
1155 return r;
1156}
1157
1158#ifdef AVSP_LONG_CABAC
1159static unsigned char es_write_addr[MAX_CODED_FRAME_SIZE] __aligned(64);
1160#endif
1161static void vavs_local_init(bool is_reset)
1162{
1163 int i;
1164
1165 vavs_ratio = vavs_amstream_dec_info.ratio;
1166
1167 avi_flag = (unsigned long) vavs_amstream_dec_info.param;
1168
1169 frame_width = frame_height = frame_dur = frame_prog = 0;
1170
1171 throw_pb_flag = 1;
1172
1173 total_frame = 0;
1174 saved_resolution = 0;
1175 next_pts = 0;
1176
1177#ifdef DEBUG_PTS
1178 pts_hit = pts_missed = pts_i_hit = pts_i_missed = 0;
1179#endif
1180
1181 if (!is_reset) {
1182 INIT_KFIFO(display_q);
1183 INIT_KFIFO(recycle_q);
1184 INIT_KFIFO(newframe_q);
1185
1186 for (i = 0; i < VF_POOL_SIZE; i++) {
1187 const struct vframe_s *vf = &vfpool[i];
1188
1189 vfpool[i].index = vf_buf_num;
1190 vfpool[i].bufWidth = 1920;
1191 kfifo_put(&newframe_q, vf);
1192 }
1193
1194 for (i = 0; i < vf_buf_num; i++)
1195 vfbuf_use[i] = 0;
1196 }
1197
1198 cur_vfpool = vfpool;
1199
1200 if (recover_flag == 1)
1201 return;
1202
1203 if (mm_blk_handle) {
1204 decoder_bmmu_box_free(mm_blk_handle);
1205 mm_blk_handle = NULL;
1206 }
1207
1208 mm_blk_handle = decoder_bmmu_box_alloc_box(
1209 DRIVER_NAME,
1210 0,
1211 MAX_BMMU_BUFFER_NUM,
1212 4 + PAGE_SHIFT,
1213 CODEC_MM_FLAGS_CMA_CLEAR |
1214 CODEC_MM_FLAGS_FOR_VDECODER);
1215
1216}
1217
1218static int vavs_vf_states(struct vframe_states *states, void *op_arg)
1219{
1220 unsigned long flags;
1221
1222 spin_lock_irqsave(&lock, flags);
1223 states->vf_pool_size = VF_POOL_SIZE;
1224 states->buf_free_num = kfifo_len(&newframe_q);
1225 states->buf_avail_num = kfifo_len(&display_q);
1226 states->buf_recycle_num = kfifo_len(&recycle_q);
1227 spin_unlock_irqrestore(&lock, flags);
1228 return 0;
1229}
1230
1231#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
1232static void vavs_ppmgr_reset(void)
1233{
1234 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_RESET, NULL);
1235
1236 vavs_local_init(true);
1237
1238 pr_info("vavs: vf_ppmgr_reset\n");
1239}
1240#endif
1241
1242static void vavs_local_reset(void)
1243{
1244 mutex_lock(&vavs_mutex);
1245 //recover_flag = 1;
1246 pr_info("error, local reset\n");
1247 amvdec_stop();
1248 msleep(100);
1249 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_RESET, NULL);
1250 vavs_local_init(true);
1251 vavs_recover();
1252
1253
1254 reset_userdata_fifo(1);
1255
1256
1257 amvdec_start();
1258 recover_flag = 0;
1259#if 0
1260 error_watchdog_count = 0;
1261
1262 pr_info("pc %x stream buf wp %x rp %x level %x\n",
1263 READ_VREG(MPC_E),
1264 READ_VREG(VLD_MEM_VIFIFO_WP),
1265 READ_VREG(VLD_MEM_VIFIFO_RP),
1266 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
1267#endif
1268
1269
1270
1271 mutex_unlock(&vavs_mutex);
1272}
1273
1274static struct work_struct fatal_error_wd_work;
1275static struct work_struct notify_work;
1276static atomic_t error_handler_run = ATOMIC_INIT(0);
1277static void vavs_fatal_error_handler(struct work_struct *work)
1278{
1279 if (debug_flag & AVS_DEBUG_OLD_ERROR_HANDLE) {
1280 mutex_lock(&vavs_mutex);
1281 pr_info("vavs fatal error reset !\n");
1282 amvdec_stop();
1283#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
1284 vavs_ppmgr_reset();
1285#else
1286 vf_light_unreg_provider(&vavs_vf_prov);
1287 vavs_local_init(true);
1288 vf_reg_provider(&vavs_vf_prov);
1289#endif
1290 vavs_recover();
1291 amvdec_start();
1292 mutex_unlock(&vavs_mutex);
1293 } else {
1294 pr_info("avs fatal_error_handler\n");
1295 vavs_local_reset();
1296 }
1297 atomic_set(&error_handler_run, 0);
1298}
1299
1300static void vavs_notify_work(struct work_struct *work)
1301{
1302 if (fr_hint_status == VDEC_NEED_HINT) {
1303 vf_notify_receiver(PROVIDER_NAME ,
1304 VFRAME_EVENT_PROVIDER_FR_HINT ,
1305 (void *)((unsigned long)frame_dur));
1306 fr_hint_status = VDEC_HINTED;
1307 }
1308 return;
1309}
1310
1311static void avs_set_clk(struct work_struct *work)
1312{
1313 int fps = 96000 / frame_dur;
1314
1315 saved_resolution = frame_width * frame_height * fps;
1316 if (firmware_sel == 0 &&
1317 (debug_flag & AVS_DEBUG_USE_FULL_SPEED)) {
1318 vdec_source_changed(VFORMAT_AVS,
1319 4096, 2048, 60);
1320 } else {
1321 vdec_source_changed(VFORMAT_AVS,
1322 frame_width, frame_height, fps);
1323 }
1324}
1325
1326static void vavs_put_timer_func(unsigned long arg)
1327{
1328 struct timer_list *timer = (struct timer_list *)arg;
1329
1330#ifndef HANDLE_AVS_IRQ
1331 vavs_isr();
1332#endif
1333
1334 if (READ_VREG(AVS_SOS_COUNT)) {
1335 if (!error_recovery_mode) {
1336#if 0
1337 if (debug_flag & AVS_DEBUG_OLD_ERROR_HANDLE) {
1338 mutex_lock(&vavs_mutex);
1339 pr_info("vavs fatal error reset !\n");
1340 amvdec_stop();
1341#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
1342 vavs_ppmgr_reset();
1343#else
1344 vf_light_unreg_provider(&vavs_vf_prov);
1345 vavs_local_init(true);
1346 vf_reg_provider(&vavs_vf_prov);
1347#endif
1348 vavs_recover();
1349 amvdec_start();
1350 mutex_unlock(&vavs_mutex);
1351 } else {
1352 vavs_local_reset();
1353 }
1354#else
1355 if (!atomic_read(&error_handler_run)) {
1356 atomic_set(&error_handler_run, 1);
1357 pr_info("AVS_SOS_COUNT = %d\n",
1358 READ_VREG(AVS_SOS_COUNT));
1359 pr_info("WP = 0x%x, RP = 0x%x, LEVEL = 0x%x, AVAIL = 0x%x, CUR_PTR = 0x%x\n",
1360 READ_VREG(VLD_MEM_VIFIFO_WP),
1361 READ_VREG(VLD_MEM_VIFIFO_RP),
1362 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
1363 READ_VREG(VLD_MEM_VIFIFO_BYTES_AVAIL),
1364 READ_VREG(VLD_MEM_VIFIFO_CURR_PTR));
1365 schedule_work(&fatal_error_wd_work);
1366 }
1367#endif
1368 }
1369 }
1370#if 0
1371 if (long_cabac_busy == 0 &&
1372 error_watchdog_threshold > 0 &&
1373 kfifo_len(&display_q) == 0 &&
1374 READ_VREG(VLD_MEM_VIFIFO_LEVEL) >
1375 error_watchdog_buf_threshold) {
1376 pr_info("newq %d dispq %d recyq %d\r\n",
1377 kfifo_len(&newframe_q),
1378 kfifo_len(&display_q),
1379 kfifo_len(&recycle_q));
1380 pr_info("pc %x stream buf wp %x rp %x level %x\n",
1381 READ_VREG(MPC_E),
1382 READ_VREG(VLD_MEM_VIFIFO_WP),
1383 READ_VREG(VLD_MEM_VIFIFO_RP),
1384 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
1385 error_watchdog_count++;
1386 if (error_watchdog_count >= error_watchdog_threshold)
1387 vavs_local_reset();
1388 } else
1389 error_watchdog_count = 0;
1390#endif
1391 if (radr != 0) {
1392 if (rval != 0) {
1393 WRITE_VREG(radr, rval);
1394 pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
1395 } else
1396 pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
1397 rval = 0;
1398 radr = 0;
1399 }
1400
1401 if (!kfifo_is_empty(&recycle_q) && (READ_VREG(AVS_BUFFERIN) == 0)) {
1402 struct vframe_s *vf;
1403
1404 if (kfifo_get(&recycle_q, &vf)) {
1405 if ((vf->index < vf_buf_num) &&
1406 (--vfbuf_use[vf->index] == 0)) {
1407 WRITE_VREG(AVS_BUFFERIN, ~(1 << vf->index));
1408 vf->index = vf_buf_num;
1409 }
1410 kfifo_put(&newframe_q,
1411 (const struct vframe_s *)vf);
1412 }
1413 }
1414
1415 if (frame_dur > 0 && saved_resolution !=
1416 frame_width * frame_height * (96000 / frame_dur))
1417 schedule_work(&set_clk_work);
1418
1419 timer->expires = jiffies + PUT_INTERVAL;
1420
1421 add_timer(timer);
1422}
1423
1424#ifdef AVSP_LONG_CABAC
1425
1426static void long_cabac_do_work(struct work_struct *work)
1427{
1428 int status = 0;
1429#ifdef PERFORMANCE_DEBUG
1430 pr_info("enter %s buf level (new %d, display %d, recycle %d)\r\n",
1431 __func__,
1432 kfifo_len(&newframe_q),
1433 kfifo_len(&display_q),
1434 kfifo_len(&recycle_q)
1435 );
1436#endif
1437 mutex_lock(&vavs_mutex);
1438 long_cabac_busy = 1;
1439 while (READ_VREG(LONG_CABAC_REQ)) {
1440 if (process_long_cabac() < 0) {
1441 status = -1;
1442 break;
1443 }
1444 }
1445 long_cabac_busy = 0;
1446 mutex_unlock(&vavs_mutex);
1447#ifdef PERFORMANCE_DEBUG
1448 pr_info("exit %s buf level (new %d, display %d, recycle %d)\r\n",
1449 __func__,
1450 kfifo_len(&newframe_q),
1451 kfifo_len(&display_q),
1452 kfifo_len(&recycle_q)
1453 );
1454#endif
1455 if (status < 0) {
1456 pr_info("transcoding error, local reset\r\n");
1457 vavs_local_reset();
1458 }
1459
1460}
1461#endif
1462
1463#ifdef AVSP_LONG_CABAC
1464static void init_avsp_long_cabac_buf(void)
1465{
1466#if 0
1467 es_write_addr_phy = (unsigned long)codec_mm_alloc_for_dma(
1468 "vavs",
1469 PAGE_ALIGN(MAX_CODED_FRAME_SIZE)/PAGE_SIZE,
1470 0, CODEC_MM_FLAGS_DMA_CPU);
1471 es_write_addr_virt = codec_mm_phys_to_virt(es_write_addr_phy);
1472
1473#elif 0
1474 es_write_addr_virt =
1475 (void *)dma_alloc_coherent(amports_get_dma_device(),
1476 MAX_CODED_FRAME_SIZE, &es_write_addr_phy,
1477 GFP_KERNEL);
1478#else
1479 /*es_write_addr_virt = kmalloc(MAX_CODED_FRAME_SIZE, GFP_KERNEL);
1480 * es_write_addr_virt = (void *)__get_free_pages(GFP_KERNEL,
1481 * get_order(MAX_CODED_FRAME_SIZE));
1482 */
1483 es_write_addr_virt = &es_write_addr[0];
1484 if (es_write_addr_virt == NULL) {
1485 pr_err("%s: failed to alloc es_write_addr_virt buffer\n",
1486 __func__);
1487 return;
1488 }
1489
1490 es_write_addr_phy = dma_map_single(amports_get_dma_device(),
1491 es_write_addr_virt,
1492 MAX_CODED_FRAME_SIZE, DMA_BIDIRECTIONAL);
1493 if (dma_mapping_error(amports_get_dma_device(),
1494 es_write_addr_phy)) {
1495 pr_err("%s: failed to map es_write_addr_virt buffer\n",
1496 __func__);
1497 /*kfree(es_write_addr_virt);*/
1498 es_write_addr_virt = NULL;
1499 return;
1500 }
1501#endif
1502
1503
1504#ifdef BITSTREAM_READ_TMP_NO_CACHE
1505 bitstream_read_tmp =
1506 (void *)dma_alloc_coherent(amports_get_dma_device(),
1507 SVA_STREAM_BUF_SIZE, &bitstream_read_tmp_phy,
1508 GFP_KERNEL);
1509
1510#else
1511
1512 bitstream_read_tmp = kmalloc(SVA_STREAM_BUF_SIZE, GFP_KERNEL);
1513 /*bitstream_read_tmp = (void *)__get_free_pages(GFP_KERNEL,
1514 *get_order(MAX_CODED_FRAME_SIZE));
1515 */
1516 if (bitstream_read_tmp == NULL) {
1517 pr_err("%s: failed to alloc bitstream_read_tmp buffer\n",
1518 __func__);
1519 return;
1520 }
1521
1522 bitstream_read_tmp_phy = dma_map_single(amports_get_dma_device(),
1523 bitstream_read_tmp,
1524 SVA_STREAM_BUF_SIZE, DMA_FROM_DEVICE);
1525 if (dma_mapping_error(amports_get_dma_device(),
1526 bitstream_read_tmp_phy)) {
1527 pr_err("%s: failed to map rpm buffer\n", __func__);
1528 kfree(bitstream_read_tmp);
1529 bitstream_read_tmp = NULL;
1530 return;
1531 }
1532#endif
1533}
1534#endif
1535
1536
1537static s32 vavs_init(void)
1538{
1539 int ret, size = -1;
1540 char *buf = vmalloc(0x1000 * 16);
1541
1542 if (IS_ERR_OR_NULL(buf))
1543 return -ENOMEM;
1544
1545 pr_info("vavs_init\n");
1546 init_timer(&recycle_timer);
1547
1548 stat |= STAT_TIMER_INIT;
1549
1550 amvdec_enable();
1551 vavs_local_init(false);
1552
1553 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXM)
1554 size = get_firmware_data(VIDEO_DEC_AVS, buf);
1555 else {
1556 if (firmware_sel == 1)
1557 size = get_firmware_data(VIDEO_DEC_AVS_NOCABAC, buf);
1558#ifdef AVSP_LONG_CABAC
1559 else {
1560 init_avsp_long_cabac_buf();
1561 size = get_firmware_data(VIDEO_DEC_AVS, buf);
1562 }
1563#endif
1564 }
1565
1566 if (size < 0) {
1567 amvdec_disable();
1568 pr_err("get firmware fail.");
1569 vfree(buf);
1570 return -1;
1571 }
1572
1573 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXM)
1574 ret = amvdec_loadmc_ex(VFORMAT_AVS, NULL, buf);
1575 else if (firmware_sel == 1)
1576 ret = amvdec_loadmc_ex(VFORMAT_AVS, "avs_no_cabac", buf);
1577 else
1578 ret = amvdec_loadmc_ex(VFORMAT_AVS, NULL, buf);
1579
1580 if (ret < 0) {
1581 amvdec_disable();
1582 vfree(buf);
1583 pr_err("AVS: the %s fw loading failed, err: %x\n",
1584 tee_enabled() ? "TEE" : "local", ret);
1585 return -EBUSY;
1586 }
1587
1588 vfree(buf);
1589
1590 stat |= STAT_MC_LOAD;
1591
1592 /* enable AMRISC side protocol */
1593 ret = vavs_prot_init();
1594 if (ret < 0)
1595 return ret;
1596
1597#ifdef HANDLE_AVS_IRQ
1598 if (vdec_request_irq(VDEC_IRQ_1, vavs_isr,
1599 "vavs-irq", (void *)vavs_dec_id)) {
1600 amvdec_disable();
1601 pr_info("vavs irq register error.\n");
1602 return -ENOENT;
1603 }
1604#endif
1605
1606 stat |= STAT_ISR_REG;
1607
1608#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
1609 vf_provider_init(&vavs_vf_prov, PROVIDER_NAME, &vavs_vf_provider, NULL);
1610 vf_reg_provider(&vavs_vf_prov);
1611 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL);
1612#else
1613 vf_provider_init(&vavs_vf_prov, PROVIDER_NAME, &vavs_vf_provider, NULL);
1614 vf_reg_provider(&vavs_vf_prov);
1615#endif
1616
1617 if (vavs_amstream_dec_info.rate != 0) {
1618 if (!is_reset) {
1619 vf_notify_receiver(PROVIDER_NAME,
1620 VFRAME_EVENT_PROVIDER_FR_HINT,
1621 (void *)((unsigned long)
1622 vavs_amstream_dec_info.rate));
1623 fr_hint_status = VDEC_HINTED;
1624 }
1625 } else
1626 fr_hint_status = VDEC_NEED_HINT;
1627
1628 stat |= STAT_VF_HOOK;
1629
1630 recycle_timer.data = (ulong)(&recycle_timer);
1631 recycle_timer.function = vavs_put_timer_func;
1632 recycle_timer.expires = jiffies + PUT_INTERVAL;
1633
1634 add_timer(&recycle_timer);
1635
1636 stat |= STAT_TIMER_ARM;
1637
1638#ifdef AVSP_LONG_CABAC
1639 if (firmware_sel == 0)
1640 INIT_WORK(&long_cabac_wd_work, long_cabac_do_work);
1641#endif
1642 vdec_source_changed(VFORMAT_AVS,
1643 1920, 1080, 30);
1644 amvdec_start();
1645
1646 stat |= STAT_VDEC_RUN;
1647
1648 return 0;
1649}
1650
1651static int amvdec_avs_probe(struct platform_device *pdev)
1652{
1653 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
1654
1655 if (pdata == NULL) {
1656 pr_info("amvdec_avs memory resource undefined.\n");
1657 return -EFAULT;
1658 }
1659 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXM || disable_longcabac_trans)
1660 firmware_sel = 1;
1661
1662 if (firmware_sel == 1) {
1663 vf_buf_num = 8;
1664 canvas_base = 0;
1665 canvas_num = 2;
1666 } else {
1667
1668 canvas_base = 128;
1669 canvas_num = 2; /*NV21*/
1670 }
1671
1672
1673 if (pdata->sys_info)
1674 vavs_amstream_dec_info = *pdata->sys_info;
1675
1676 pr_info("%s (%d,%d) %d\n", __func__, vavs_amstream_dec_info.width,
1677 vavs_amstream_dec_info.height, vavs_amstream_dec_info.rate);
1678
1679 pdata->dec_status = vavs_dec_status;
1680 pdata->set_isreset = vavs_set_isreset;
1681 is_reset = 0;
1682
1683 pdata->user_data_read = NULL;
1684 pdata->reset_userdata_fifo = NULL;
1685
1686 vavs_vdec_info_init();
1687
1688
1689 if (NULL == user_data_buffer) {
1690 user_data_buffer =
1691 dma_alloc_coherent(amports_get_dma_device(),
1692 USER_DATA_SIZE,
1693 &user_data_buffer_phys, GFP_KERNEL);
1694 if (!user_data_buffer) {
1695 pr_info("%s: Can not allocate user_data_buffer\n",
1696 __func__);
1697 return -ENOMEM;
1698 }
1699 pr_debug("user_data_buffer = 0x%p, user_data_buffer_phys = 0x%x\n",
1700 user_data_buffer, (u32)user_data_buffer_phys);
1701 }
1702
1703 INIT_WORK(&set_clk_work, avs_set_clk);
1704 vdec = pdata;
1705 if (vavs_init() < 0) {
1706 pr_info("amvdec_avs init failed.\n");
1707 kfree(gvs);
1708 gvs = NULL;
1709 pdata->dec_status = NULL;
1710 return -ENODEV;
1711 }
1712
1713 INIT_WORK(&fatal_error_wd_work, vavs_fatal_error_handler);
1714 atomic_set(&error_handler_run, 0);
1715
1716 INIT_WORK(&userdata_push_work, userdata_push_do_work);
1717
1718 INIT_WORK(&notify_work, vavs_notify_work);
1719
1720 return 0;
1721}
1722
1723static int amvdec_avs_remove(struct platform_device *pdev)
1724{
1725 if (stat & STAT_TIMER_ARM) {
1726 del_timer_sync(&recycle_timer);
1727 stat &= ~STAT_TIMER_ARM;
1728 }
1729 cancel_work_sync(&fatal_error_wd_work);
1730 atomic_set(&error_handler_run, 0);
1731
1732 cancel_work_sync(&userdata_push_work);
1733
1734 cancel_work_sync(&notify_work);
1735 if (stat & STAT_VDEC_RUN) {
1736 amvdec_stop();
1737 stat &= ~STAT_VDEC_RUN;
1738 }
1739
1740 if (stat & STAT_ISR_REG) {
1741 vdec_free_irq(VDEC_IRQ_1, (void *)vavs_dec_id);
1742 stat &= ~STAT_ISR_REG;
1743 }
1744
1745#ifdef AVSP_LONG_CABAC
1746 if (firmware_sel == 0) {
1747 mutex_lock(&vavs_mutex);
1748 cancel_work_sync(&long_cabac_wd_work);
1749 mutex_unlock(&vavs_mutex);
1750
1751 if (es_write_addr_virt) {
1752#if 0
1753 codec_mm_free_for_dma("vavs", es_write_addr_phy);
1754#else
1755 dma_unmap_single(amports_get_dma_device(),
1756 es_write_addr_phy,
1757 MAX_CODED_FRAME_SIZE, DMA_FROM_DEVICE);
1758 /*kfree(es_write_addr_virt);*/
1759 es_write_addr_virt = NULL;
1760#endif
1761 }
1762
1763#ifdef BITSTREAM_READ_TMP_NO_CACHE
1764 if (bitstream_read_tmp) {
1765 dma_free_coherent(amports_get_dma_device(),
1766 SVA_STREAM_BUF_SIZE, bitstream_read_tmp,
1767 bitstream_read_tmp_phy);
1768 bitstream_read_tmp = NULL;
1769 }
1770#else
1771 if (bitstream_read_tmp) {
1772 dma_unmap_single(amports_get_dma_device(),
1773 bitstream_read_tmp_phy,
1774 SVA_STREAM_BUF_SIZE, DMA_FROM_DEVICE);
1775 kfree(bitstream_read_tmp);
1776 bitstream_read_tmp = NULL;
1777 }
1778#endif
1779 }
1780#endif
1781 if (stat & STAT_VF_HOOK) {
1782 if (fr_hint_status == VDEC_HINTED)
1783 vf_notify_receiver(PROVIDER_NAME,
1784 VFRAME_EVENT_PROVIDER_FR_END_HINT, NULL);
1785 fr_hint_status = VDEC_NO_NEED_HINT;
1786 vf_unreg_provider(&vavs_vf_prov);
1787 stat &= ~STAT_VF_HOOK;
1788 }
1789
1790
1791 if (user_data_buffer != NULL) {
1792 dma_free_coherent(
1793 amports_get_dma_device(),
1794 USER_DATA_SIZE,
1795 user_data_buffer,
1796 user_data_buffer_phys);
1797 user_data_buffer = NULL;
1798 user_data_buffer_phys = 0;
1799 }
1800
1801
1802 amvdec_disable();
1803 pic_type = 0;
1804 if (mm_blk_handle) {
1805 decoder_bmmu_box_free(mm_blk_handle);
1806 mm_blk_handle = NULL;
1807 }
1808#ifdef DEBUG_PTS
1809 pr_debug("pts hit %d, pts missed %d, i hit %d, missed %d\n", pts_hit,
1810 pts_missed, pts_i_hit, pts_i_missed);
1811 pr_debug("total frame %d, avi_flag %d, rate %d\n", total_frame, avi_flag,
1812 vavs_amstream_dec_info.rate);
1813#endif
1814 kfree(gvs);
1815 gvs = NULL;
1816
1817 cancel_work_sync(&set_clk_work);
1818 return 0;
1819}
1820
1821/****************************************/
1822#ifdef CONFIG_PM
1823static int avs_suspend(struct device *dev)
1824{
1825 amvdec_suspend(to_platform_device(dev), dev->power.power_state);
1826 return 0;
1827}
1828
1829static int avs_resume(struct device *dev)
1830{
1831 amvdec_resume(to_platform_device(dev));
1832 return 0;
1833}
1834
1835static const struct dev_pm_ops avs_pm_ops = {
1836 SET_SYSTEM_SLEEP_PM_OPS(avs_suspend, avs_resume)
1837};
1838#endif
1839
1840static struct platform_driver amvdec_avs_driver = {
1841 .probe = amvdec_avs_probe,
1842 .remove = amvdec_avs_remove,
1843 .driver = {
1844 .name = DRIVER_NAME,
1845#ifdef CONFIG_PM
1846 .pm = &avs_pm_ops,
1847#endif
1848 }
1849};
1850
1851static struct codec_profile_t amvdec_avs_profile = {
1852 .name = "avs",
1853 .profile = ""
1854};
1855
1856static struct mconfig avs_configs[] = {
1857 MC_PU32("stat", &stat),
1858 MC_PU32("debug_flag", &debug_flag),
1859 MC_PU32("error_recovery_mode", &error_recovery_mode),
1860 MC_PU32("pic_type", &pic_type),
1861 MC_PU32("radr", &radr),
1862 MC_PU32("vf_buf_num", &vf_buf_num),
1863 MC_PU32("vf_buf_num_used", &vf_buf_num_used),
1864 MC_PU32("canvas_base", &canvas_base),
1865 MC_PU32("firmware_sel", &firmware_sel),
1866};
1867static struct mconfig_node avs_node;
1868
1869
1870static int __init amvdec_avs_driver_init_module(void)
1871{
1872 pr_debug("amvdec_avs module init\n");
1873
1874 if (platform_driver_register(&amvdec_avs_driver)) {
1875 pr_info("failed to register amvdec_avs driver\n");
1876 return -ENODEV;
1877 }
1878
1879 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXBB)
1880 amvdec_avs_profile.profile = "avs+";
1881
1882 vcodec_profile_register(&amvdec_avs_profile);
1883 INIT_REG_NODE_CONFIGS("media.decoder", &avs_node,
1884 "avs", avs_configs, CONFIG_FOR_RW);
1885 return 0;
1886}
1887
1888static void __exit amvdec_avs_driver_remove_module(void)
1889{
1890 pr_debug("amvdec_avs module remove.\n");
1891
1892 platform_driver_unregister(&amvdec_avs_driver);
1893}
1894
1895/****************************************/
1896
1897module_param(stat, uint, 0664);
1898MODULE_PARM_DESC(stat, "\n amvdec_avs stat\n");
1899
1900/******************************************
1901 *module_param(run_flag, uint, 0664);
1902 *MODULE_PARM_DESC(run_flag, "\n run_flag\n");
1903 *
1904 *module_param(step_flag, uint, 0664);
1905 *MODULE_PARM_DESC(step_flag, "\n step_flag\n");
1906 *******************************************
1907 */
1908
1909module_param(debug_flag, uint, 0664);
1910MODULE_PARM_DESC(debug_flag, "\n debug_flag\n");
1911
1912module_param(error_recovery_mode, uint, 0664);
1913MODULE_PARM_DESC(error_recovery_mode, "\n error_recovery_mode\n");
1914
1915/******************************************
1916 *module_param(error_watchdog_threshold, uint, 0664);
1917 *MODULE_PARM_DESC(error_watchdog_threshold, "\n error_watchdog_threshold\n");
1918 *
1919 *module_param(error_watchdog_buf_threshold, uint, 0664);
1920 *MODULE_PARM_DESC(error_watchdog_buf_threshold,
1921 * "\n error_watchdog_buf_threshold\n");
1922 *******************************************
1923 */
1924
1925module_param(pic_type, uint, 0444);
1926MODULE_PARM_DESC(pic_type, "\n amdec_vas picture type\n");
1927
1928module_param(radr, uint, 0664);
1929MODULE_PARM_DESC(radr, "\nradr\n");
1930
1931module_param(rval, uint, 0664);
1932MODULE_PARM_DESC(rval, "\nrval\n");
1933
1934module_param(vf_buf_num, uint, 0664);
1935MODULE_PARM_DESC(vf_buf_num, "\nvf_buf_num\n");
1936
1937module_param(vf_buf_num_used, uint, 0664);
1938MODULE_PARM_DESC(vf_buf_num_used, "\nvf_buf_num_used\n");
1939
1940module_param(canvas_base, uint, 0664);
1941MODULE_PARM_DESC(canvas_base, "\ncanvas_base\n");
1942
1943
1944module_param(firmware_sel, uint, 0664);
1945MODULE_PARM_DESC(firmware_sel, "\n firmware_sel\n");
1946
1947module_param(disable_longcabac_trans, uint, 0664);
1948MODULE_PARM_DESC(disable_longcabac_trans, "\n disable_longcabac_trans\n");
1949
1950module_param(dec_control, uint, 0664);
1951MODULE_PARM_DESC(dec_control, "\n amvdec_vavs decoder control\n");
1952
1953module_param(support_user_data, uint, 0664);
1954MODULE_PARM_DESC(support_user_data, "\n support_user_data\n");
1955
1956module_init(amvdec_avs_driver_init_module);
1957module_exit(amvdec_avs_driver_remove_module);
1958
1959MODULE_DESCRIPTION("AMLOGIC AVS Video Decoder Driver");
1960MODULE_LICENSE("GPL");
1961MODULE_AUTHOR("Qi Wang <qi.wang@amlogic.com>");
1962
generated by cgit at 2024-05-19 21:11:08 (GMT)