path: root/drivers/frame_provider/decoder/avs_multi/avs_multi.c (plain)
blob: 11813addf0323115405fb475b538eb6cbd638626

1	/*
2	* drivers/amlogic/amports/vavs.c
3	*
4	* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5	*
6	* This program is free software; you can redistribute it and/or modify
7	* it under the terms of the GNU General Public License as published by
8	* the Free Software Foundation; either version 2 of the License, or
9	* (at your option) any later version.
10	*
11	* This program is distributed in the hope that it will be useful, but WITHOUT
12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14	* more details.
15	*
16	*/
17	#define DEBUG
18	#include <linux/kernel.h>
19	#include <linux/types.h>
20	#include <linux/errno.h>
21	#include <linux/interrupt.h>
22	#include <linux/semaphore.h>
23	#include <linux/timer.h>
24	#include <linux/kfifo.h>
25	#include <linux/delay.h>
26	#include <linux/platform_device.h>
27	#include <linux/amlogic/media/utils/amstream.h>
28	#include <linux/amlogic/media/frame_sync/ptsserv.h>
29	#include <linux/amlogic/media/canvas/canvas.h>
30	#include <linux/amlogic/media/vfm/vframe_provider.h>
31	#include <linux/amlogic/media/vfm/vframe_receiver.h>
32	#include <linux/amlogic/media/vfm/vframe.h>
33	#include <linux/amlogic/media/utils/vdec_reg.h>
34	#include "../../../stream_input/parser/streambuf_reg.h"
35	#include "../utils/amvdec.h"
36	#include <linux/amlogic/media/registers/register.h>
37	#include "../../../stream_input/amports/amports_priv.h"
38	#include <linux/dma-mapping.h>
39	#include <linux/amlogic/media/codec_mm/codec_mm.h>
40	#include <linux/slab.h>
41	#include "avs_multi.h"
42	#include <linux/amlogic/media/codec_mm/configs.h>
43	#include "../utils/decoder_mmu_box.h"
44	#include "../utils/decoder_bmmu_box.h"
45	#include "../utils/firmware.h"
46	#include "../../../common/chips/decoder_cpu_ver_info.h"
47	#include <linux/amlogic/tee.h>
48
49	#define DEBUG_MULTI_FLAG 0
50
51	#define DRIVER_NAME "amvdec_avs"
52	#define MODULE_NAME "amvdec_avs"
53
54	#define MULTI_DRIVER_NAME "ammvdec_avs"
55
56	#define ENABLE_USER_DATA
57
58	#if 1/* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
59	#define NV21
60	#endif
61
62	#define USE_AVS_SEQ_INFO
63	#define HANDLE_AVS_IRQ
64	#define DEBUG_PTS
65
66	#define CHECK_INTERVAL (HZ/100)
67
68	#define I_PICTURE 0
69	#define P_PICTURE 1
70	#define B_PICTURE 2
71
72	#define LMEM_BUF_SIZE (0x500 * 2)
73
74	/* #define ORI_BUFFER_START_ADDR 0x81000000 */
75	#define ORI_BUFFER_START_ADDR 0x80000000
76
77	#define INTERLACE_FLAG 0x80
78	#define TOP_FIELD_FIRST_FLAG 0x40
79
80	/* protocol registers */
81	#define AVS_PIC_RATIO AV_SCRATCH_0
82	#define AVS_PIC_WIDTH AV_SCRATCH_1
83	#define AVS_PIC_HEIGHT AV_SCRATCH_2
84	#define AVS_FRAME_RATE AV_SCRATCH_3
85
86	/*#define AVS_ERROR_COUNT AV_SCRATCH_6*/
87	#define AVS_SOS_COUNT AV_SCRATCH_7
88	#define AVS_BUFFERIN AV_SCRATCH_8
89	#define AVS_BUFFEROUT AV_SCRATCH_9
90	#define AVS_REPEAT_COUNT AV_SCRATCH_A
91	#define AVS_TIME_STAMP AV_SCRATCH_B
92	#define AVS_OFFSET_REG AV_SCRATCH_C
93	#define MEM_OFFSET_REG AV_SCRATCH_F
94	#define AVS_ERROR_RECOVERY_MODE AV_SCRATCH_G
95
96	#define DECODE_MODE AV_SCRATCH_6
97	#define DECODE_MODE_SINGLE 0x0
98	#define DECODE_MODE_MULTI_FRAMEBASE 0x1
99	#define DECODE_MODE_MULTI_STREAMBASE 0x2
100
101	#define DECODE_STATUS AV_SCRATCH_H
102	#define DECODE_STATUS_PIC_DONE 0x1
103	#define DECODE_STATUS_DECODE_BUF_EMPTY 0x2
104	#define DECODE_STATUS_SEARCH_BUF_EMPTY 0x3
105	#define DECODE_SEARCH_HEAD 0xff
106
107	#define DECODE_STOP_POS AV_SCRATCH_J
108
109	#define DECODE_LMEM_BUF_ADR AV_SCRATCH_I
110
111	#define VF_POOL_SIZE 32
112	#define PUT_INTERVAL (HZ/100)
113
114	#if 1 /*MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8*/
115	#define INT_AMVENCODER INT_DOS_MAILBOX_1
116	#else
117	/* #define AMVENC_DEV_VERSION "AML-MT" */
118	#define INT_AMVENCODER INT_MAILBOX_1A
119	#endif
120
121
122	static void check_timer_func(unsigned long arg);
123	static void vavs_work(struct work_struct *work);
124
125	#define DEC_CONTROL_FLAG_FORCE_2500_1080P_INTERLACE 0x0001
126	static u32 dec_control = DEC_CONTROL_FLAG_FORCE_2500_1080P_INTERLACE;
127
128
129	#define VPP_VD1_POSTBLEND (1 << 10)
130
131	static int debug;
132	#define debug_flag debug
133	static unsigned int debug_mask = 0xff;
134
135	/*for debug*/
136	/*
137	udebug_flag:
138	bit 0, enable ucode print
139	bit 1, enable ucode detail print
140	bit [31:16] not 0, pos to dump lmem
141	bit 2, pop bits to lmem
142	bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
143	*/
144	static u32 udebug_flag;
145	/*
146	when udebug_flag[1:0] is not 0
147	udebug_pause_pos not 0,
148	pause position
149	*/
150	static u32 udebug_pause_pos;
151	/*
152	when udebug_flag[1:0] is not 0
153	and udebug_pause_pos is not 0,
154	pause only when DEBUG_REG2 is equal to this val
155	*/
156	static u32 udebug_pause_val;
157
158	static u32 udebug_pause_decode_idx;
159
160	static u32 force_fps;
161
162	static u32 step;
163
164	#define AVS_DEV_NUM 9
165	static unsigned int max_decode_instance_num = AVS_DEV_NUM;
166	static unsigned int max_process_time[AVS_DEV_NUM];
167	static unsigned int max_get_frame_interval[AVS_DEV_NUM];
168
169	static unsigned int decode_timeout_val = 100;
170	static unsigned int start_decode_buf_level = 0x8000;
171
172	/********************************
173	firmware_sel
174	0: use avsp_trans long cabac ucode;
175	1: not use avsp_trans long cabac ucode
176	in ucode:
177	#define USE_EXT_BUFFER_ASSIGNMENT
178	#undef USE_DYNAMIC_BUF_NUM
179	********************************/
180	static int firmware_sel;
181	static int disable_longcabac_trans = 1;
182
183
184	int avs_get_debug_flag(void)
185	{
186	return debug_flag;
187	}
188
189	static struct vframe_s *vavs_vf_peek(void *);
190	static struct vframe_s *vavs_vf_get(void *);
191	static void vavs_vf_put(struct vframe_s *, void *);
192	static int vavs_vf_states(struct vframe_states *states, void *);
193	static int vavs_event_cb(int type, void *data, void *private_data);
194
195	static const char vavs_dec_id[] = "vavs-dev";
196
197	#define PROVIDER_NAME "decoder.avs"
198	static DEFINE_SPINLOCK(lock);
199	static DEFINE_MUTEX(vavs_mutex);
200
201	static const struct vframe_operations_s vavs_vf_provider = {
202	.peek = vavs_vf_peek,
203	.get = vavs_vf_get,
204	.put = vavs_vf_put,
205	.event_cb = vavs_event_cb,
206	.vf_states = vavs_vf_states,
207	};
208	/*
209	static void *mm_blk_handle;
210	*/
211	static struct vframe_provider_s vavs_vf_prov;
212
213	#define VF_BUF_NUM_MAX 16
214	#define WORKSPACE_SIZE (4 * SZ_1M)
215
216	#ifdef AVSP_LONG_CABAC
217	#define MAX_BMMU_BUFFER_NUM (VF_BUF_NUM_MAX + 2)
218	#define WORKSPACE_SIZE_A (MAX_CODED_FRAME_SIZE + LOCAL_HEAP_SIZE)
219	#else
220	#define MAX_BMMU_BUFFER_NUM (VF_BUF_NUM_MAX + 1)
221	#endif
222
223	#define RV_AI_BUFF_START_ADDR 0x01a00000
224	#define LONG_CABAC_RV_AI_BUFF_START_ADDR 0x00000000
225
226	static u32 vf_buf_num = 4;
227	/*static u32 vf_buf_num_used;*/
228	static u32 canvas_base = 128;
229	#ifdef NV21
230	int canvas_num = 2; /*NV21*/
231	#else
232	int canvas_num = 3;
233	#endif
234
235	#if 0
236	static struct vframe_s vfpool[VF_POOL_SIZE];
237	/*static struct vframe_s vfpool2[VF_POOL_SIZE];*/
238	static struct vframe_s *cur_vfpool;
239	static unsigned char recover_flag;
240	static s32 vfbuf_use[VF_BUF_NUM_MAX];
241	static u32 saved_resolution;
242	static u32 frame_width, frame_height, frame_dur, frame_prog;
243	static struct timer_list recycle_timer;
244	static u32 stat;
245	#endif
246	static u32 buf_size = 32 * 1024 * 1024;
247	#if 0
248	static u32 buf_offset;
249	static u32 avi_flag;
250	static u32 vavs_ratio;
251	static u32 pic_type;
252	#endif
253	static u32 pts_by_offset = 1;
254	#if 0
255	static u32 total_frame;
256	static u32 next_pts;
257	static unsigned char throw_pb_flag;
258	#ifdef DEBUG_PTS
259	static u32 pts_hit, pts_missed, pts_i_hit, pts_i_missed;
260	#endif
261	#endif
262	static u32 radr, rval;
263	static u32 dbg_cmd;
264	#if 0
265	static struct dec_sysinfo vavs_amstream_dec_info;
266	static struct vdec_info *gvs;
267	static u32 fr_hint_status;
268	static struct work_struct notify_work;
269	static struct work_struct set_clk_work;
270	static bool is_reset;
271	#endif
272	/*static struct vdec_s *vdec;*/
273
274	#ifdef AVSP_LONG_CABAC
275	static struct work_struct long_cabac_wd_work;
276	void *es_write_addr_virt;
277	dma_addr_t es_write_addr_phy;
278
279	void *bitstream_read_tmp;
280	dma_addr_t bitstream_read_tmp_phy;
281	void *avsp_heap_adr;
282	static uint long_cabac_busy;
283	#endif
284
285	#if 0
286	#ifdef ENABLE_USER_DATA
287	static void *user_data_buffer;
288	static dma_addr_t user_data_buffer_phys;
289	#endif
290	static DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
291	static DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
292	static DECLARE_KFIFO(recycle_q, struct vframe_s *, VF_POOL_SIZE);
293	#endif
294	static inline u32 index2canvas(u32 index)
295	{
296	const u32 canvas_tab[VF_BUF_NUM_MAX] = {
297	0x010100, 0x030302, 0x050504, 0x070706,
298	0x090908, 0x0b0b0a, 0x0d0d0c, 0x0f0f0e,
299	0x111110, 0x131312, 0x151514, 0x171716,
300	0x191918, 0x1b1b1a, 0x1d1d1c, 0x1f1f1e,
301	};
302	const u32 canvas_tab_3[4] = {
303	0x010100, 0x040403, 0x070706, 0x0a0a09
304	};
305
306	if (canvas_num == 2)
307	return canvas_tab[index] + (canvas_base << 16)
308	+ (canvas_base << 8) + canvas_base;
309
310	return canvas_tab_3[index] + (canvas_base << 16)
311	+ (canvas_base << 8) + canvas_base;
312	}
313
314	static const u32 frame_rate_tab[16] = {
315	96000 / 30, /* forbidden */
316	96000000 / 23976, /* 24000/1001 (23.967) */
317	96000 / 24,
318	96000 / 25,
319	9600000 / 2997, /* 30000/1001 (29.97) */
320	96000 / 30,
321	96000 / 50,
322	9600000 / 5994, /* 60000/1001 (59.94) */
323	96000 / 60,
324	/* > 8 reserved, use 24 */
325	96000 / 24, 96000 / 24, 96000 / 24, 96000 / 24,
326	96000 / 24, 96000 / 24, 96000 / 24
327	};
328
329	#define DECODE_BUFFER_NUM_MAX VF_BUF_NUM_MAX
330	struct vdec_avs_hw_s {
331	spinlock_t lock;
332	unsigned char m_ins_flag;
333	struct platform_device *platform_dev;
334	DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
335	DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
336	DECLARE_KFIFO(recycle_q, struct vframe_s *, VF_POOL_SIZE);
337	struct vframe_s vfpool[VF_POOL_SIZE];
338	s32 vfbuf_use[VF_BUF_NUM_MAX];
339	unsigned char again_flag;
340	unsigned char recover_flag;
341	u32 frame_width;
342	u32 frame_height;
343	u32 frame_dur;
344	u32 frame_prog;
345	u32 saved_resolution;
346	u32 avi_flag;
347	u32 vavs_ratio;
348	u32 pic_type;
349
350	u32 vf_buf_num_used;
351	u32 total_frame;
352	u32 next_pts;
353	unsigned char throw_pb_flag;
354	#ifdef DEBUG_PTS
355	u32 pts_hit;
356	u32 pts_missed;
357	u32 pts_i_hit;
358	u32 pts_i_missed;
359	#endif
360	#ifdef ENABLE_USER_DATA
361	struct work_struct userdata_push_work;
362	void *user_data_buffer;
363	dma_addr_t user_data_buffer_phys;
364	#endif
365	void *lmem_addr;
366	dma_addr_t lmem_phy_addr;
367
368	u32 buf_offset;
369
370	struct dec_sysinfo vavs_amstream_dec_info;
371	struct vdec_info *gvs;
372	u32 fr_hint_status;
373	struct work_struct set_clk_work;
374	bool is_reset;
375
376	/*debug*/
377	u32 ucode_pause_pos;
378	/**/
379	u32 decode_pic_count;
380	u8 reset_decode_flag;
381	u32 display_frame_count;
382	u32 buf_status;
383	/*
384	buffer_status &= ~buf_recycle_status
385	*/
386	u32 buf_recycle_status;
387	u32 seqinfo;
388	u32 ctx_valid;
389	u32 dec_control;
390	void *mm_blk_handle;
391	struct vframe_chunk_s *chunk;
392	u32 stat;
393	u8 init_flag;
394	unsigned long buf_start;
395	u32 buf_size;
396
397	u32 reg_scratch_0;
398	u32 reg_scratch_1;
399	u32 reg_scratch_2;
400	u32 reg_scratch_3;
401	u32 reg_scratch_4;
402	u32 reg_scratch_5;
403	u32 reg_scratch_6;
404	u32 reg_scratch_7;
405	u32 reg_scratch_8;
406	u32 reg_scratch_9;
407	u32 reg_scratch_A;
408	u32 reg_scratch_B;
409	u32 reg_scratch_C;
410	u32 reg_scratch_D;
411	u32 reg_scratch_E;
412	u32 reg_scratch_F;
413	u32 reg_scratch_G;
414	u32 reg_scratch_H;
415	u32 reg_scratch_I;
416	u32 reg_mb_width;
417	u32 reg_viff_bit_cnt;
418	u32 reg_canvas_addr;
419	u32 reg_dbkr_canvas_addr;
420	u32 reg_dbkw_canvas_addr;
421	u32 reg_anc2_canvas_addr;
422	u32 reg_anc0_canvas_addr;
423	u32 reg_anc1_canvas_addr;
424	u32 slice_ver_pos_pic_type;
425	u32 vc1_control_reg;
426	u32 avs_co_mb_wr_addr;
427	u32 slice_start_byte_01;
428	u32 slice_start_byte_23;
429	u32 vcop_ctrl_reg;
430	u32 iqidct_control;
431	u32 rv_ai_mb_count;
432	u32 slice_qp;
433	u32 dc_scaler;
434	u32 avsp_iq_wq_param_01;
435	u32 avsp_iq_wq_param_23;
436	u32 avsp_iq_wq_param_45;
437	u32 avs_co_mb_rd_addr;
438	u32 dblk_mb_wid_height;
439	u32 mc_pic_w_h;
440	u32 avs_co_mb_rw_ctl;
441	u32 vld_decode_control;
442
443	struct timer_list check_timer;
444	u32 decode_timeout_count;
445	unsigned long int start_process_time;
446	u32 last_vld_level;
447	u32 eos;
448	u32 canvas_spec[DECODE_BUFFER_NUM_MAX];
449	struct canvas_config_s canvas_config[DECODE_BUFFER_NUM_MAX][2];
450
451	s32 refs[2];
452	int dec_result;
453	struct timer_list recycle_timer;
454	struct work_struct work;
455	struct work_struct notify_work;
456	atomic_t error_handler_run;
457	struct work_struct fatal_error_wd_work;
458	void (*vdec_cb)(struct vdec_s *, void *);
459	void *vdec_cb_arg;
460	/* for error handling */
461	u32 first_i_frame_ready;
462	u32 run_count;
463	u32 not_run_ready;
464	u32 input_empty;
465	u32 prepare_num;
466	u32 put_num;
467	u32 peek_num;
468	u32 get_num;
469	u32 drop_frame_count;
470	u32 buffer_not_ready;
471	int frameinfo_enable;
472	struct firmware_s *fw;
473	};
474
475	static void reset_process_time(struct vdec_avs_hw_s *hw);
476	static void start_process_time(struct vdec_avs_hw_s *hw);
477	static void vavs_save_regs(struct vdec_avs_hw_s *hw);
478
479	struct vdec_avs_hw_s *ghw;
480
481	#define MULTI_INSTANCE_PROVIDER_NAME "vdec.avs"
482
483	#define DEC_RESULT_NONE 0
484	#define DEC_RESULT_DONE 1
485	#define DEC_RESULT_AGAIN 2
486	#define DEC_RESULT_ERROR 3
487	#define DEC_RESULT_FORCE_EXIT 4
488	#define DEC_RESULT_EOS 5
489	#define DEC_RESULT_GET_DATA 6
490	#define DEC_RESULT_GET_DATA_RETRY 7
491	#define DEC_RESULT_USERDATA 8
492
493	#define DECODE_ID(hw) (hw->m_ins_flag? 0 : hw_to_vdec(hw)->id)
494
495	#define PRINT_FLAG_ERROR 0x0
496	#define PRINT_FLAG_RUN_FLOW 0X0001
497	#define PRINT_FLAG_DECODING 0x0002
498	#define PRINT_FLAG_VFRAME_DETAIL 0x0010
499	#define PRINT_FLAG_VLD_DETAIL 0x0020
500	#define PRINT_FLAG_DEC_DETAIL 0x0040
501	#define PRINT_FLAG_BUFFER_DETAIL 0x0080
502	#define PRINT_FLAG_FORCE_DONE 0x0100
503	#define PRINT_FLAG_COUNTER 0X0200
504	#define PRINT_FRAMEBASE_DATA 0x0400
505	#define PRINT_FLAG_PARA_DATA 0x1000
506	#define DEBUG_FLAG_PREPARE_MORE_INPUT 0x2000
507	#define DEBUG_FLAG_DISABLE_TIMEOUT 0x10000
508	#define DEBUG_WAIT_DECODE_DONE_WHEN_STOP 0x20000
509
510	#undef pr_info
511	#define pr_info printk
512	static int debug_print(struct vdec_avs_hw_s *hw,
513	int flag, const char *fmt, ...)
514	{
515	#define AVS_PRINT_BUF 256
516	unsigned char buf[AVS_PRINT_BUF];
517	int len = 0;
518	int index = hw->m_ins_flag ? DECODE_ID(hw) : 0;
519	if (hw == NULL ||
520	(flag == 0) ||
521	((debug_mask &
522	(1 << index))
523	&& (debug & flag))) {
524	va_list args;
525
526	va_start(args, fmt);
527	if (hw)
528	len = sprintf(buf, "[%d]", index);
529	vsnprintf(buf + len, AVS_PRINT_BUF - len, fmt, args);
530	pr_debug("%s", buf);
531	va_end(args);
532	}
533	return 0;
534	}
535
536	static int debug_print_cont(struct vdec_avs_hw_s *hw,
537	int flag, const char *fmt, ...)
538	{
539	unsigned char buf[AVS_PRINT_BUF];
540	int len = 0;
541	int index = hw->m_ins_flag ? DECODE_ID(hw) : 0;
542	if (hw == NULL ||
543	(flag == 0) ||
544	((debug_mask &
545	(1 << index))
546	&& (debug & flag))) {
547	va_list args;
548
549	va_start(args, fmt);
550	vsnprintf(buf + len, AVS_PRINT_BUF - len, fmt, args);
551	pr_info("%s", buf);
552	va_end(args);
553	}
554	return 0;
555	}
556
557	static void set_frame_info(struct vdec_avs_hw_s *hw, struct vframe_s *vf,
558	unsigned int *duration)
559	{
560	int ar = 0;
561
562	unsigned int pixel_ratio = READ_VREG(AVS_PIC_RATIO);
563	hw->prepare_num++;
564	#ifndef USE_AVS_SEQ_INFO
565	if (hw->vavs_amstream_dec_info.width > 0
566	&& hw->vavs_amstream_dec_info.height > 0) {
567	vf->width = hw->vavs_amstream_dec_info.width;
568	vf->height = hw->vavs_amstream_dec_info.height;
569	} else
570	#endif
571	{
572	vf->width = READ_VREG(AVS_PIC_WIDTH);
573	vf->height = READ_VREG(AVS_PIC_HEIGHT);
574	hw->frame_width = vf->width;
575	hw->frame_height = vf->height;
576	/* pr_info("%s: (%d,%d)\n", __func__,vf->width, vf->height);*/
577	}
578
579	#ifndef USE_AVS_SEQ_INFO
580	if (hw->vavs_amstream_dec_info.rate > 0)
581	*duration = hw->vavs_amstream_dec_info.rate;
582	else
583	#endif
584	{
585	*duration = frame_rate_tab[READ_VREG(AVS_FRAME_RATE) & 0xf];
586	/* pr_info("%s: duration = %d\n", __func__, *duration); */
587	hw->frame_dur = *duration;
588	schedule_work(&hw->notify_work);
589	}
590
591	if (hw->vavs_ratio == 0) {
592	/* always stretch to 16:9 */
593	vf->ratio_control |= (0x90 <<
594	DISP_RATIO_ASPECT_RATIO_BIT);
595	} else {
596	switch (pixel_ratio) {
597	case 1:
598	ar = (vf->height * hw->vavs_ratio) / vf->width;
599	break;
600	case 2:
601	ar = (vf->height * 3 * hw->vavs_ratio) / (vf->width * 4);
602	break;
603	case 3:
604	ar = (vf->height * 9 * hw->vavs_ratio) / (vf->width * 16);
605	break;
606	case 4:
607	ar = (vf->height * 100 * hw->vavs_ratio) / (vf->width *
608	221);
609	break;
610	default:
611	ar = (vf->height * hw->vavs_ratio) / vf->width;
612	break;
613	}
614	}
615
616	ar = min(ar, DISP_RATIO_ASPECT_RATIO_MAX);
617
618	vf->ratio_control = (ar << DISP_RATIO_ASPECT_RATIO_BIT);
619	/*vf->ratio_control |= DISP_RATIO_FORCECONFIG | DISP_RATIO_KEEPRATIO; */
620
621	vf->flag = 0;
622	}
623
624	#ifdef ENABLE_USER_DATA
625
626	/*static struct work_struct userdata_push_work;*/
627	/*
628	#define DUMP_LAST_REPORTED_USER_DATA
629	*/
630	static void userdata_push_process(struct vdec_avs_hw_s *hw)
631	{
632	unsigned int user_data_flags;
633	unsigned int user_data_wp;
634	unsigned int user_data_length;
635	struct userdata_poc_info_t user_data_poc;
636	#ifdef DUMP_LAST_REPORTED_USER_DATA
637	int user_data_len;
638	int wp_start;
639	unsigned char *pdata;
640	int nLeft;
641	#endif
642
643	user_data_flags = READ_VREG(AV_SCRATCH_N);
644	user_data_wp = (user_data_flags >> 16) & 0xffff;
645	user_data_length = user_data_flags & 0x7fff;
646
647	#ifdef DUMP_LAST_REPORTED_USER_DATA
648	dma_sync_single_for_cpu(amports_get_dma_device(),
649	hw->user_data_buffer_phys, USER_DATA_SIZE,
650	DMA_FROM_DEVICE);
651
652	if (user_data_length & 0x07)
653	user_data_len = (user_data_length + 8) & 0xFFFFFFF8;
654	else
655	user_data_len = user_data_length;
656
657	if (user_data_wp >= user_data_len) {
658	wp_start = user_data_wp - user_data_len;
659
660	pdata = (unsigned char *)hw->user_data_buffer;
661	pdata += wp_start;
662	nLeft = user_data_len;
663	while (nLeft >= 8) {
664	pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
665	pdata[0], pdata[1], pdata[2], pdata[3],
666	pdata[4], pdata[5], pdata[6], pdata[7]);
667	nLeft -= 8;
668	pdata += 8;
669	}
670	} else {
671	wp_start = user_data_wp +
672	USER_DATA_SIZE - user_data_len;
673
674	pdata = (unsigned char *)hw->user_data_buffer;
675	pdata += wp_start;
676	nLeft = USER_DATA_SIZE - wp_start;
677
678	while (nLeft >= 8) {
679	pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
680	pdata[0], pdata[1], pdata[2], pdata[3],
681	pdata[4], pdata[5], pdata[6], pdata[7]);
682	nLeft -= 8;
683	pdata += 8;
684	}
685
686	pdata = (unsigned char *)hw->user_data_buffer;
687	nLeft = user_data_wp;
688	while (nLeft >= 8) {
689	pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
690	pdata[0], pdata[1], pdata[2], pdata[3],
691	pdata[4], pdata[5], pdata[6], pdata[7]);
692	nLeft -= 8;
693	pdata += 8;
694	}
695	}
696	#endif
697
698	/*
699	pr_info("pocinfo 0x%x, poc %d, wp 0x%x, len %d\n",
700	READ_VREG(AV_SCRATCH_L), READ_VREG(AV_SCRATCH_M),
701	user_data_wp, user_data_length);
702	*/
703	user_data_poc.poc_info = READ_VREG(AV_SCRATCH_L);
704	user_data_poc.poc_number = READ_VREG(AV_SCRATCH_M);
705
706	WRITE_VREG(AV_SCRATCH_N, 0);
707	/*
708	wakeup_userdata_poll(user_data_poc, user_data_wp,
709	(unsigned long)hw->user_data_buffer,
710	USER_DATA_SIZE, user_data_length);
711	*/
712	}
713
714	static void userdata_push_do_work(struct work_struct *work)
715	{
716	struct vdec_avs_hw_s *hw =
717	container_of(work, struct vdec_avs_hw_s, userdata_push_work);
718	userdata_push_process(hw);
719	}
720
721	static u8 UserDataHandler(struct vdec_avs_hw_s *hw)
722	{
723	unsigned int user_data_flags;
724
725	user_data_flags = READ_VREG(AV_SCRATCH_N);
726	if (user_data_flags & (1 << 15)) { /* data ready */
727	if (hw->m_ins_flag) {
728	hw->dec_result = DEC_RESULT_USERDATA;
729	vdec_schedule_work(&hw->work);
730	return 1;
731	} else
732	schedule_work(&hw->userdata_push_work);
733	}
734	return 0;
735	}
736	#endif
737
738	#ifdef HANDLE_AVS_IRQ
739	static irqreturn_t vavs_isr(int irq, void *dev_id)
740	#else
741	static void vavs_isr(void)
742	#endif
743	{
744	u32 reg;
745	struct vframe_s *vf;
746	u32 dur;
747	u32 repeat_count;
748	u32 picture_type;
749	u32 buffer_index;
750	u32 frame_size;
751	bool force_interlaced_frame = false;
752	unsigned int pts, pts_valid = 0, offset = 0;
753	u64 pts_us64;
754	u32 debug_tag;
755	u32 buffer_status_debug;
756	struct vdec_avs_hw_s *hw = (struct vdec_avs_hw_s *)dev_id;
757
758	/*if (debug_flag & AVS_DEBUG_UCODE) {
759	if (READ_VREG(AV_SCRATCH_E) != 0) {
760	pr_info("dbg%x: %x\n", READ_VREG(AV_SCRATCH_E),
761	READ_VREG(AV_SCRATCH_D));
762	WRITE_VREG(AV_SCRATCH_E, 0);
763	}
764	}*/
765	#define DEBUG_REG1 AV_SCRATCH_E
766	#define DEBUG_REG2 AV_SCRATCH_D
767
768	debug_tag = READ_VREG(DEBUG_REG1);
769	buffer_status_debug = debug_tag >> 24;
770	debug_tag &= 0xffffff;
771	if (debug_tag & 0x10000) {
772	int i;
773	dma_sync_single_for_cpu(
774	amports_get_dma_device(),
775	hw->lmem_phy_addr,
776	LMEM_BUF_SIZE,
777	DMA_FROM_DEVICE);
778
779	debug_print(hw, 0,
780	"LMEM<tag %x>:\n", debug_tag);
781
782	for (i = 0; i < 0x400; i += 4) {
783	int ii;
784	unsigned short *lmem_ptr = hw->lmem_addr;
785	if ((i & 0xf) == 0)
786	debug_print_cont(hw, 0, "%03x: ", i);
787	for (ii = 0; ii < 4; ii++) {
788	debug_print_cont(hw, 0, "%04x ",
789	lmem_ptr[i + 3 - ii]);
790	}
791	if (((i + ii) & 0xf) == 0)
792	debug_print_cont(hw, 0, "\n");
793	}
794
795	if (((udebug_pause_pos & 0xffff)
796	== (debug_tag & 0xffff)) &&
797	(udebug_pause_decode_idx == 0 ||
798	udebug_pause_decode_idx == hw->decode_pic_count) &&
799	(udebug_pause_val == 0 ||
800	udebug_pause_val == READ_VREG(DEBUG_REG2))) {
801	udebug_pause_pos &= 0xffff;
802	hw->ucode_pause_pos = udebug_pause_pos;
803	}
804	else if (debug_tag & 0x20000)
805	hw->ucode_pause_pos = 0xffffffff;
806	if (hw->ucode_pause_pos)
807	reset_process_time(hw);
808	else
809	WRITE_VREG(DEBUG_REG1, 0);
810	} else if (debug_tag != 0) {
811	debug_print(hw, 0,
812	"dbg%x: %x buffer_status 0x%x l/w/r %x %x %x bitcnt %x\n",
813	debug_tag,
814	READ_VREG(DEBUG_REG2),
815	buffer_status_debug,
816	READ_VREG(VLD_MEM_VIFIFO_LEVEL),
817	READ_VREG(VLD_MEM_VIFIFO_WP),
818	READ_VREG(VLD_MEM_VIFIFO_RP),
819	READ_VREG(VIFF_BIT_CNT));
820	if (((udebug_pause_pos & 0xffff)
821	== (debug_tag & 0xffff)) &&
822	(udebug_pause_decode_idx == 0 ||
823	udebug_pause_decode_idx == hw->decode_pic_count) &&
824	(udebug_pause_val == 0 ||
825	udebug_pause_val == READ_VREG(DEBUG_REG2))) {
826	udebug_pause_pos &= 0xffff;
827	hw->ucode_pause_pos = udebug_pause_pos;
828	}
829	if (hw->ucode_pause_pos)
830	reset_process_time(hw);
831	else
832	WRITE_VREG(DEBUG_REG1, 0);
833	//return IRQ_HANDLED;
834	} else {
835	debug_print(hw, PRINT_FLAG_DECODING,
836	"%s decode_status 0x%x, buffer_status 0x%x\n",
837	__func__,
838	READ_VREG(DECODE_STATUS),
839	buffer_status_debug);
840	}
841
842	#ifdef AVSP_LONG_CABAC
843	if (firmware_sel == 0 && READ_VREG(LONG_CABAC_REQ)) {
844	#ifdef PERFORMANCE_DEBUG
845	pr_info("%s:schedule long_cabac_wd_work\r\n", __func__);
846	#endif
847	pr_info("schedule long_cabac_wd_work and requested from %d\n",
848	(READ_VREG(LONG_CABAC_REQ) >> 8)&0xFF);
849	schedule_work(&long_cabac_wd_work);
850	}
851	#endif
852
853	#ifdef ENABLE_USER_DATA
854	if (UserDataHandler(hw))
855	return IRQ_HANDLED;
856	#endif
857	reg = READ_VREG(AVS_BUFFEROUT);
858	if (reg) {
859	if (debug_flag & AVS_DEBUG_PRINT)
860	pr_info("AVS_BUFFEROUT=%x\n", reg);
861	if (pts_by_offset) {
862	offset = READ_VREG(AVS_OFFSET_REG);
863	if (debug_flag & AVS_DEBUG_PRINT)
864	pr_info("AVS OFFSET=%x\n", offset);
865	if (pts_lookup_offset_us64(PTS_TYPE_VIDEO, offset, &pts,
866	&frame_size,
867	0, &pts_us64) == 0) {
868	pts_valid = 1;
869	#ifdef DEBUG_PTS
870	hw->pts_hit++;
871	#endif
872	} else {
873	#ifdef DEBUG_PTS
874	hw->pts_missed++;
875	#endif
876	}
877	}
878
879	repeat_count = READ_VREG(AVS_REPEAT_COUNT);
880	if (firmware_sel == 0)
881	buffer_index =
882	((reg & 0x7) +
883	(((reg >> 8) & 0x3) << 3) - 1) & 0x1f;
884	else
885	buffer_index =
886	((reg & 0x7) - 1) & 3;
887
888	picture_type = (reg >> 3) & 7;
889	#ifdef DEBUG_PTS
890	if (picture_type == I_PICTURE) {
891	/* pr_info("I offset 0x%x, pts_valid %d\n",
892	* offset, pts_valid);
893	*/
894	if (!pts_valid)
895	hw->pts_i_missed++;
896	else
897	hw->pts_i_hit++;
898	}
899	#endif
900
901	if ((dec_control & DEC_CONTROL_FLAG_FORCE_2500_1080P_INTERLACE)
902	&& hw->frame_width == 1920 && hw->frame_height == 1080) {
903	force_interlaced_frame = true;
904	}
905
906	if (hw->throw_pb_flag && picture_type != I_PICTURE) {
907
908	debug_print(hw, PRINT_FLAG_DECODING,
909	"%s WRITE_VREG(AVS_BUFFERIN, 0x%x) for throwing picture with type of %d\n",
910	__func__,
911	~(1 << buffer_index), picture_type);
912
913	WRITE_VREG(AVS_BUFFERIN, ~(1 << buffer_index));
914	} else if (reg & INTERLACE_FLAG || force_interlaced_frame) { /* interlace */
915	hw->throw_pb_flag = 0;
916
917	if (debug_flag & AVS_DEBUG_PRINT) {
918	pr_info("interlace, picture type %d\n",
919	picture_type);
920	}
921
922	if (kfifo_get(&hw->newframe_q, &vf) == 0) {
923	pr_info
924	("fatal error, no available buffer slot.");
925	return IRQ_HANDLED;
926	}
927	set_frame_info(hw, vf, &dur);
928	vf->bufWidth = 1920;
929	hw->pic_type = 2;
930	if ((picture_type == I_PICTURE) && pts_valid) {
931	vf->pts = pts;
932	if ((repeat_count > 1) && hw->avi_flag) {
933	/* hw->next_pts = pts +
934	* (hw->vavs_amstream_dec_info.rate *
935	* repeat_count >> 1)*15/16;
936	*/
937	hw->next_pts =
938	pts +
939	(dur * repeat_count >> 1) *
940	15 / 16;
941	} else
942	hw->next_pts = 0;
943	} else {
944	vf->pts = hw->next_pts;
945	if ((repeat_count > 1) && hw->avi_flag) {
946	/* vf->duration =
947	* hw->vavs_amstream_dec_info.rate *
948	* repeat_count >> 1;
949	*/
950	vf->duration = dur * repeat_count >> 1;
951	if (hw->next_pts != 0) {
952	hw->next_pts +=
953	((vf->duration) -
954	((vf->duration) >> 4));
955	}
956	} else {
957	/* vf->duration =
958	* hw->vavs_amstream_dec_info.rate >> 1;
959	*/
960	vf->duration = dur >> 1;
961	hw->next_pts = 0;
962	}
963	}
964	vf->signal_type = 0;
965	vf->index = buffer_index;
966	vf->duration_pulldown = 0;
967	if (force_interlaced_frame) {
968	vf->type = VIDTYPE_INTERLACE_TOP;
969	}else{
970	vf->type =
971	(reg & TOP_FIELD_FIRST_FLAG)
972	? VIDTYPE_INTERLACE_TOP
973	: VIDTYPE_INTERLACE_BOTTOM;
974	}
975	#ifdef NV21
976	vf->type |= VIDTYPE_VIU_NV21;
977	#endif
978	if (hw->m_ins_flag) {
979	vf->canvas0Addr = vf->canvas1Addr = -1;
980	vf->plane_num = 2;
981
982	vf->canvas0_config[0] = hw->canvas_config[buffer_index][0];
983	vf->canvas0_config[1] = hw->canvas_config[buffer_index][1];
984
985	vf->canvas1_config[0] = hw->canvas_config[buffer_index][0];
986	vf->canvas1_config[1] = hw->canvas_config[buffer_index][1];
987	} else
988	vf->canvas0Addr = vf->canvas1Addr =
989	index2canvas(buffer_index);
990	vf->type_original = vf->type;
991
992	if (debug_flag & AVS_DEBUG_PRINT) {
993	pr_info("buffer_index %d, canvas addr %x\n",
994	buffer_index, vf->canvas0Addr);
995	}
996	vf->pts_us64 = (pts_valid) ? pts_us64 : 0;
997	hw->vfbuf_use[buffer_index]++;
998	vf->mem_handle =
999	decoder_bmmu_box_get_mem_handle(
1000	hw->mm_blk_handle,
1001	buffer_index);
1002
1003	kfifo_put(&hw->display_q,
1004	(const struct vframe_s *)vf);
1005	vf_notify_receiver(PROVIDER_NAME,
1006	VFRAME_EVENT_PROVIDER_VFRAME_READY,
1007	NULL);
1008
1009	if (kfifo_get(&hw->newframe_q, &vf) == 0) {
1010	pr_info("fatal error, no available buffer slot.");
1011	return IRQ_HANDLED;
1012	}
1013	set_frame_info(hw, vf, &dur);
1014	vf->bufWidth = 1920;
1015	if (force_interlaced_frame)
1016	vf->pts = 0;
1017	else
1018	vf->pts = hw->next_pts;
1019
1020	if ((repeat_count > 1) && hw->avi_flag) {
1021	/* vf->duration = hw->vavs_amstream_dec_info.rate *
1022	* repeat_count >> 1;
1023	*/
1024	vf->duration = dur * repeat_count >> 1;
1025	if (hw->next_pts != 0) {
1026	hw->next_pts +=
1027	((vf->duration) -
1028	((vf->duration) >> 4));
1029	}
1030	} else {
1031	/* vf->duration = hw->vavs_amstream_dec_info.rate
1032	* >> 1;
1033	*/
1034	vf->duration = dur >> 1;
1035	hw->next_pts = 0;
1036	}
1037	vf->signal_type = 0;
1038	vf->index = buffer_index;
1039	vf->duration_pulldown = 0;
1040	if (force_interlaced_frame) {
1041	vf->type = VIDTYPE_INTERLACE_BOTTOM;
1042	} else {
1043	vf->type =
1044	(reg & TOP_FIELD_FIRST_FLAG) ?
1045	VIDTYPE_INTERLACE_BOTTOM :
1046	VIDTYPE_INTERLACE_TOP;
1047	}
1048	#ifdef NV21
1049	vf->type |= VIDTYPE_VIU_NV21;
1050	#endif
1051	if (hw->m_ins_flag) {
1052	vf->canvas0Addr = vf->canvas1Addr = -1;
1053	vf->plane_num = 2;
1054
1055	vf->canvas0_config[0] = hw->canvas_config[buffer_index][0];
1056	vf->canvas0_config[1] = hw->canvas_config[buffer_index][1];
1057
1058	vf->canvas1_config[0] = hw->canvas_config[buffer_index][0];
1059	vf->canvas1_config[1] = hw->canvas_config[buffer_index][1];
1060	} else
1061	vf->canvas0Addr = vf->canvas1Addr =
1062	index2canvas(buffer_index);
1063	vf->type_original = vf->type;
1064	vf->pts_us64 = 0;
1065	hw->vfbuf_use[buffer_index]++;
1066	vf->mem_handle =
1067	decoder_bmmu_box_get_mem_handle(
1068	hw->mm_blk_handle,
1069	buffer_index);
1070
1071	kfifo_put(&hw->display_q,
1072	(const struct vframe_s *)vf);
1073	vf_notify_receiver(PROVIDER_NAME,
1074	VFRAME_EVENT_PROVIDER_VFRAME_READY,
1075	NULL);
1076	hw->total_frame++;
1077	} else { /* progressive */
1078	hw->throw_pb_flag = 0;
1079
1080	if (debug_flag & AVS_DEBUG_PRINT) {
1081	pr_info("progressive picture type %d\n",
1082	picture_type);
1083	}
1084	if (kfifo_get(&hw->newframe_q, &vf) == 0) {
1085	pr_info
1086	("fatal error, no available buffer slot.");
1087	return IRQ_HANDLED;
1088	}
1089	set_frame_info(hw, vf, &dur);
1090	vf->bufWidth = 1920;
1091	hw->pic_type = 1;
1092
1093	if ((picture_type == I_PICTURE) && pts_valid) {
1094	vf->pts = pts;
1095	if ((repeat_count > 1) && hw->avi_flag) {
1096	/* hw->next_pts = pts +
1097	* (hw->vavs_amstream_dec_info.rate *
1098	* repeat_count)*15/16;
1099	*/
1100	hw->next_pts =
1101	pts +
1102	(dur * repeat_count) * 15 / 16;
1103	} else
1104	hw->next_pts = 0;
1105	} else {
1106	vf->pts = hw->next_pts;
1107	if ((repeat_count > 1) && hw->avi_flag) {
1108	/* vf->duration =
1109	* hw->vavs_amstream_dec_info.rate *
1110	* repeat_count;
1111	*/
1112	vf->duration = dur * repeat_count;
1113	if (hw->next_pts != 0) {
1114	hw->next_pts +=
1115	((vf->duration) -
1116	((vf->duration) >> 4));
1117	}
1118	} else {
1119	/* vf->duration =
1120	* hw->vavs_amstream_dec_info.rate;
1121	*/
1122	vf->duration = dur;
1123	hw->next_pts = 0;
1124	}
1125	}
1126	vf->signal_type = 0;
1127	vf->index = buffer_index;
1128	vf->duration_pulldown = 0;
1129	vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD;
1130	#ifdef NV21
1131	vf->type |= VIDTYPE_VIU_NV21;
1132	#endif
1133	if (hw->m_ins_flag) {
1134	vf->canvas0Addr = vf->canvas1Addr = -1;
1135	vf->plane_num = 2;
1136
1137	vf->canvas0_config[0] = hw->canvas_config[buffer_index][0];
1138	vf->canvas0_config[1] = hw->canvas_config[buffer_index][1];
1139
1140	vf->canvas1_config[0] = hw->canvas_config[buffer_index][0];
1141	vf->canvas1_config[1] = hw->canvas_config[buffer_index][1];
1142	} else
1143	vf->canvas0Addr = vf->canvas1Addr =
1144	index2canvas(buffer_index);
1145	vf->type_original = vf->type;
1146
1147	vf->pts_us64 = (pts_valid) ? pts_us64 : 0;
1148	if (debug_flag & AVS_DEBUG_PRINT) {
1149	pr_info("buffer_index %d, canvas addr %x\n",
1150	buffer_index, vf->canvas0Addr);
1151	}
1152
1153	hw->vfbuf_use[buffer_index]++;
1154	vf->mem_handle =
1155	decoder_bmmu_box_get_mem_handle(
1156	hw->mm_blk_handle,
1157	buffer_index);
1158	kfifo_put(&hw->display_q,
1159	(const struct vframe_s *)vf);
1160	vf_notify_receiver(PROVIDER_NAME,
1161	VFRAME_EVENT_PROVIDER_VFRAME_READY,
1162	NULL);
1163	hw->total_frame++;
1164	}
1165
1166	/*count info*/
1167	hw->gvs->frame_dur = hw->frame_dur;
1168	vdec_count_info(hw->gvs, 0, offset);
1169
1170	/* pr_info("PicType = %d, PTS = 0x%x\n",
1171	* picture_type, vf->pts);
1172	*/
1173	WRITE_VREG(AVS_BUFFEROUT, 0);
1174	}
1175	WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
1176
1177
1178	if (hw->m_ins_flag) {
1179	u32 status_reg = READ_VREG(DECODE_STATUS);
1180	u32 decode_status = status_reg & 0xff;
1181	if (hw->dec_result == DEC_RESULT_DONE ||
1182	hw->dec_result == DEC_RESULT_AGAIN) {
1183	debug_print(hw, PRINT_FLAG_DECODING,
1184	"%s !!! decode_status 0x%x, buf_status 0x%x, dec_result = 0x%x, decode_pic_count = %d\n",
1185	__func__, decode_status,
1186	hw->buf_status,
1187	hw->dec_result, hw->decode_pic_count);
1188	return IRQ_HANDLED;
1189	} else if (decode_status == DECODE_STATUS_PIC_DONE) {
1190	hw->buf_status = (status_reg >> 8) & 0xffff;
1191	hw->decode_pic_count++;
1192	reset_process_time(hw);
1193	hw->dec_result = DEC_RESULT_DONE;
1194	#if DEBUG_MULTI_FLAG == 1
1195	WRITE_VREG(DECODE_STATUS, 0);
1196	#else
1197	amvdec_stop();
1198	#endif
1199	vavs_save_regs(hw);
1200	debug_print(hw, PRINT_FLAG_DECODING,
1201	"%s DECODE_STATUS_PIC_DONE, decode_status 0x%x, buf_status 0x%x, dec_result = 0x%x, decode_pic_count = %d\n",
1202	__func__, decode_status,
1203	hw->buf_status,
1204	hw->dec_result, hw->decode_pic_count);
1205	vdec_schedule_work(&hw->work);
1206	return IRQ_HANDLED;
1207	} else if (decode_status == DECODE_STATUS_DECODE_BUF_EMPTY ||
1208	decode_status == DECODE_STATUS_SEARCH_BUF_EMPTY) {
1209	hw->buf_status = (status_reg >> 8) & 0xffff;
1210	reset_process_time(hw);
1211	hw->dec_result = DEC_RESULT_AGAIN;
1212	#if DEBUG_MULTI_FLAG == 1
1213	WRITE_VREG(DECODE_STATUS, 0);
1214	#else
1215	amvdec_stop();
1216	#endif
1217	debug_print(hw, PRINT_FLAG_DECODING,
1218	"%s BUF_EMPTY, decode_status 0x%x, buf_status 0x%x, dec_result = 0x%x, decode_pic_count = %d\n",
1219	__func__, decode_status,
1220	hw->buf_status,
1221	hw->dec_result, hw->decode_pic_count);
1222	vdec_schedule_work(&hw->work);
1223	return IRQ_HANDLED;
1224	}
1225	}
1226
1227
1228	#ifdef HANDLE_AVS_IRQ
1229	return IRQ_HANDLED;
1230	#else
1231	return;
1232	#endif
1233	}
1234	/*
1235	*static int run_flag = 1;
1236	*static int step_flag;
1237	*/
1238	static int error_recovery_mode; /*0: blocky 1: mosaic*/
1239	/*
1240	*static uint error_watchdog_threshold=10;
1241	*static uint error_watchdog_count;
1242	*static uint error_watchdog_buf_threshold = 0x4000000;
1243	*/
1244
1245	static struct vframe_s *vavs_vf_peek(void *op_arg)
1246	{
1247	struct vframe_s *vf;
1248	struct vdec_avs_hw_s *hw =
1249	(struct vdec_avs_hw_s *)op_arg;
1250	hw->peek_num++;
1251	if (step == 2)
1252	return NULL;
1253	if (hw->recover_flag)
1254	return NULL;
1255
1256	if (kfifo_peek(&hw->display_q, &vf)) {
1257	if (vf) {
1258	if (force_fps & 0x100) {
1259	u32 rate = force_fps & 0xff;
1260
1261	if (rate)
1262	vf->duration = 96000/rate;
1263	else
1264	vf->duration = 0;
1265	}
1266
1267	}
1268	return vf;
1269	}
1270
1271	return NULL;
1272
1273	}
1274
1275	static struct vframe_s *vavs_vf_get(void *op_arg)
1276	{
1277	struct vframe_s *vf;
1278	struct vdec_avs_hw_s *hw =
1279	(struct vdec_avs_hw_s *)op_arg;
1280
1281	if (hw->recover_flag)
1282	return NULL;
1283
1284	if (step == 2)
1285	return NULL;
1286	else if (step == 1)
1287	step = 2;
1288
1289	if (kfifo_get(&hw->display_q, &vf)) {
1290	if (vf) {
1291	hw->get_num++;
1292	if (force_fps & 0x100) {
1293	u32 rate = force_fps & 0xff;
1294
1295	if (rate)
1296	vf->duration = 96000/rate;
1297	else
1298	vf->duration = 0;
1299	}
1300
1301	debug_print(hw, PRINT_FLAG_VFRAME_DETAIL,
1302	"%s, index = %d, w %d h %d, type 0x%x\n",
1303	__func__,
1304	vf->index,
1305	vf->width,
1306	vf->height,
1307	vf->type);
1308	}
1309	return vf;
1310	}
1311
1312	return NULL;
1313
1314	}
1315
1316	static void vavs_vf_put(struct vframe_s *vf, void *op_arg)
1317	{
1318	int i;
1319	struct vdec_avs_hw_s *hw =
1320	(struct vdec_avs_hw_s *)op_arg;
1321
1322	if (vf) {
1323	hw->put_num++;
1324	debug_print(hw, PRINT_FLAG_VFRAME_DETAIL,
1325	"%s, index = %d, w %d h %d, type 0x%x\n",
1326	__func__,
1327	vf->index,
1328	vf->width,
1329	vf->height,
1330	vf->type);
1331	}
1332	if (hw->recover_flag)
1333	return;
1334
1335	for (i = 0; i < VF_POOL_SIZE; i++) {
1336	if (vf == &hw->vfpool[i])
1337	break;
1338	}
1339	if (i < VF_POOL_SIZE)
1340
1341	kfifo_put(&hw->recycle_q, (const struct vframe_s *)vf);
1342
1343	}
1344
1345	static int vavs_event_cb(int type, void *data, void *private_data)
1346	{
1347	return 0;
1348	}
1349
1350	int vavs_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
1351	{
1352	struct vdec_avs_hw_s *hw =
1353	(struct vdec_avs_hw_s *)vdec->private;
1354	/*if (!(hw->stat & STAT_VDEC_RUN))
1355	return -1;*/
1356	if (!hw)
1357	return -1;
1358
1359	vstatus->frame_width = hw->frame_width;
1360	vstatus->frame_height = hw->frame_height;
1361	if (hw->frame_dur != 0)
1362	vstatus->frame_rate = 96000 / hw->frame_dur;
1363	else
1364	vstatus->frame_rate = -1;
1365	vstatus->error_count = READ_VREG(AV_SCRATCH_C);
1366	vstatus->status = hw->stat;
1367	vstatus->bit_rate = hw->gvs->bit_rate;
1368	vstatus->frame_dur = hw->frame_dur;
1369	vstatus->frame_data = hw->gvs->frame_data;
1370	vstatus->total_data = hw->gvs->total_data;
1371	vstatus->frame_count = hw->gvs->frame_count;
1372	vstatus->error_frame_count = hw->gvs->error_frame_count;
1373	vstatus->drop_frame_count = hw->gvs->drop_frame_count;
1374	vstatus->total_data = hw->gvs->total_data;
1375	vstatus->samp_cnt = hw->gvs->samp_cnt;
1376	vstatus->offset = hw->gvs->offset;
1377	snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
1378	"%s", DRIVER_NAME);
1379
1380	return 0;
1381	}
1382
1383	int vavs_set_isreset(struct vdec_s *vdec, int isreset)
1384	{
1385	struct vdec_avs_hw_s *hw =
1386	(struct vdec_avs_hw_s *)vdec->private;
1387
1388	hw->is_reset = isreset;
1389	return 0;
1390	}
1391
1392	static int vavs_vdec_info_init(struct vdec_avs_hw_s *hw)
1393	{
1394	pr_info("%s %d\n", __func__, __LINE__);
1395
1396	hw->gvs = kzalloc(sizeof(struct vdec_info), GFP_KERNEL);
1397	if (NULL == hw->gvs) {
1398	pr_info("the struct of vdec status malloc failed.\n");
1399	return -ENOMEM;
1400	}
1401	pr_info("%s %d\n", __func__, __LINE__);
1402
1403	return 0;
1404	}
1405	/****************************************/
1406	static int vavs_canvas_init(struct vdec_avs_hw_s *hw)
1407	{
1408	int i, ret;
1409	u32 canvas_width, canvas_height;
1410	u32 decbuf_size, decbuf_y_size, decbuf_uv_size;
1411	unsigned long buf_start;
1412	int need_alloc_buf_num;
1413	struct vdec_s *vdec = NULL;
1414
1415	if (hw->m_ins_flag)
1416	vdec = hw_to_vdec(hw);
1417
1418	hw->vf_buf_num_used = vf_buf_num;
1419	if (buf_size <= 0x00400000) {
1420	/* SD only */
1421	canvas_width = 768;
1422	canvas_height = 576;
1423	decbuf_y_size = 0x80000;
1424	decbuf_uv_size = 0x20000;
1425	decbuf_size = 0x100000;
1426	} else {
1427	/* HD & SD */
1428	canvas_width = 1920;
1429	canvas_height = 1088;
1430	decbuf_y_size = 0x200000;
1431	decbuf_uv_size = 0x80000;
1432	decbuf_size = 0x300000;
1433	}
1434
1435	#ifdef AVSP_LONG_CABAC
1436	need_alloc_buf_num = hw->vf_buf_num_used + 2;
1437	#else
1438	need_alloc_buf_num = hw->vf_buf_num_used + 1;
1439	#endif
1440	for (i = 0; i < need_alloc_buf_num; i++) {
1441
1442	if (i == (need_alloc_buf_num - 1))
1443	decbuf_size = WORKSPACE_SIZE;
1444	#ifdef AVSP_LONG_CABAC
1445	else if (i == (need_alloc_buf_num - 2))
1446	decbuf_size = WORKSPACE_SIZE_A;
1447	#endif
1448	ret = decoder_bmmu_box_alloc_buf_phy(hw->mm_blk_handle, i,
1449	decbuf_size, DRIVER_NAME, &buf_start);
1450	if (ret < 0)
1451	return ret;
1452	if (i == (need_alloc_buf_num - 1)) {
1453	if (firmware_sel == 1)
1454	hw->buf_offset = buf_start -
1455	RV_AI_BUFF_START_ADDR;
1456	else
1457	hw->buf_offset = buf_start -
1458	LONG_CABAC_RV_AI_BUFF_START_ADDR;
1459	continue;
1460	}
1461	#ifdef AVSP_LONG_CABAC
1462	else if (i == (need_alloc_buf_num - 2)) {
1463	avsp_heap_adr = codec_mm_phys_to_virt(buf_start);
1464	continue;
1465	}
1466	#endif
1467	if (hw->m_ins_flag) {
1468	unsigned canvas;
1469
1470	if (vdec->parallel_dec == 1) {
1471	unsigned tmp;
1472	if (canvas_u(hw->canvas_spec[i]) == 0xff) {
1473	tmp =
1474	vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
1475	hw->canvas_spec[i] &= ~(0xffff << 8);
1476	hw->canvas_spec[i] |= tmp << 8;
1477	hw->canvas_spec[i] |= tmp << 16;
1478	}
1479	if (canvas_y(hw->canvas_spec[i]) == 0xff) {
1480	tmp =
1481	vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
1482	hw->canvas_spec[i] &= ~0xff;
1483	hw->canvas_spec[i] |= tmp;
1484	}
1485	canvas = hw->canvas_spec[i];
1486	} else {
1487	canvas = vdec->get_canvas(i, 2);
1488	hw->canvas_spec[i] = canvas;
1489	}
1490
1491	hw->canvas_config[i][0].phy_addr =
1492	buf_start;
1493	hw->canvas_config[i][0].width =
1494	canvas_width;
1495	hw->canvas_config[i][0].height =
1496	canvas_height;
1497	hw->canvas_config[i][0].block_mode =
1498	CANVAS_BLKMODE_32X32;
1499
1500	hw->canvas_config[i][1].phy_addr =
1501	buf_start + decbuf_y_size;
1502	hw->canvas_config[i][1].width =
1503	canvas_width;
1504	hw->canvas_config[i][1].height =
1505	canvas_height / 2;
1506	hw->canvas_config[i][1].block_mode =
1507	CANVAS_BLKMODE_32X32;
1508
1509	} else {
1510	#ifdef NV21
1511	canvas_config(canvas_base + canvas_num * i + 0,
1512	buf_start,
1513	canvas_width, canvas_height,
1514	CANVAS_ADDR_NOWRAP,
1515	CANVAS_BLKMODE_32X32);
1516	canvas_config(canvas_base + canvas_num * i + 1,
1517	buf_start +
1518	decbuf_y_size, canvas_width,
1519	canvas_height / 2,
1520	CANVAS_ADDR_NOWRAP,
1521	CANVAS_BLKMODE_32X32);
1522	#else
1523	canvas_config(canvas_num * i + 0,
1524	buf_start,
1525	canvas_width, canvas_height,
1526	CANVAS_ADDR_NOWRAP,
1527	CANVAS_BLKMODE_32X32);
1528	canvas_config(canvas_num * i + 1,
1529	buf_start +
1530	decbuf_y_size, canvas_width / 2,
1531	canvas_height / 2,
1532	CANVAS_ADDR_NOWRAP,
1533	CANVAS_BLKMODE_32X32);
1534	canvas_config(canvas_num * i + 2,
1535	buf_start +
1536	decbuf_y_size + decbuf_uv_size,
1537	canvas_width / 2, canvas_height / 2,
1538	CANVAS_ADDR_NOWRAP,
1539	CANVAS_BLKMODE_32X32);
1540	#endif
1541	if (debug_flag & AVS_DEBUG_PRINT) {
1542	pr_info("canvas config %d, addr %p\n", i,
1543	(void *)buf_start);
1544	}
1545	}
1546	}
1547	return 0;
1548	}
1549
1550	void vavs_recover(struct vdec_avs_hw_s *hw)
1551	{
1552	vavs_canvas_init(hw);
1553
1554	WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6) | (1 << 4));
1555	WRITE_VREG(DOS_SW_RESET0, 0);
1556
1557	READ_VREG(DOS_SW_RESET0);
1558
1559	WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6) | (1 << 4));
1560	WRITE_VREG(DOS_SW_RESET0, 0);
1561
1562	WRITE_VREG(DOS_SW_RESET0, (1 << 9) | (1 << 8));
1563	WRITE_VREG(DOS_SW_RESET0, 0);
1564
1565	if (firmware_sel == 1) {
1566	WRITE_VREG(POWER_CTL_VLD, 0x10);
1567	WRITE_VREG_BITS(VLD_MEM_VIFIFO_CONTROL, 2,
1568	MEM_FIFO_CNT_BIT, 2);
1569	WRITE_VREG_BITS(VLD_MEM_VIFIFO_CONTROL, 8,
1570	MEM_LEVEL_CNT_BIT, 6);
1571	}
1572
1573
1574	if (firmware_sel == 0) {
1575	/* fixed canvas index */
1576	WRITE_VREG(AV_SCRATCH_0, canvas_base);
1577	WRITE_VREG(AV_SCRATCH_1, hw->vf_buf_num_used);
1578	} else {
1579	int ii;
1580
1581	for (ii = 0; ii < 4; ii++) {
1582	WRITE_VREG(AV_SCRATCH_0 + ii,
1583	(canvas_base + canvas_num * ii) |
1584	((canvas_base + canvas_num * ii + 1)
1585	<< 8) |
1586	((canvas_base + canvas_num * ii + 1)
1587	<< 16)
1588	);
1589	}
1590	}
1591
1592	/* notify ucode the buffer offset */
1593	WRITE_VREG(AV_SCRATCH_F, hw->buf_offset);
1594
1595	/* disable PSCALE for hardware sharing */
1596	WRITE_VREG(PSCALE_CTRL, 0);
1597
1598	WRITE_VREG(AVS_SOS_COUNT, 0);
1599	WRITE_VREG(AVS_BUFFERIN, 0);
1600	WRITE_VREG(AVS_BUFFEROUT, 0);
1601	if (error_recovery_mode)
1602	WRITE_VREG(AVS_ERROR_RECOVERY_MODE, 0);
1603	else
1604	WRITE_VREG(AVS_ERROR_RECOVERY_MODE, 1);
1605	/* clear mailbox interrupt */
1606	WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
1607
1608	/* enable mailbox interrupt */
1609	WRITE_VREG(ASSIST_MBOX1_MASK, 1);
1610	#if 1 /* def DEBUG_UCODE */
1611	WRITE_VREG(AV_SCRATCH_D, 0);
1612	#endif
1613
1614	#ifdef NV21
1615	SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 17);
1616	#endif
1617
1618	#ifdef PIC_DC_NEED_CLEAR
1619	CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 31);
1620	#endif
1621
1622	#ifdef AVSP_LONG_CABAC
1623	if (firmware_sel == 0) {
1624	WRITE_VREG(LONG_CABAC_DES_ADDR, es_write_addr_phy);
1625	WRITE_VREG(LONG_CABAC_REQ, 0);
1626	WRITE_VREG(LONG_CABAC_PIC_SIZE, 0);
1627	WRITE_VREG(LONG_CABAC_SRC_ADDR, 0);
1628	}
1629	#endif
1630	WRITE_VREG(AV_SCRATCH_5, 0);
1631
1632	}
1633
1634	#define MBY_MBX MB_MOTION_MODE /*0xc07*/
1635	#define AVS_CO_MB_WR_ADDR 0xc38
1636	#define AVS_CO_MB_RW_CTL 0xc3d
1637	#define AVS_CO_MB_RD_ADDR 0xc39
1638	#define AVSP_IQ_WQ_PARAM_01 0x0e19
1639	#define AVSP_IQ_WQ_PARAM_23 0x0e1a
1640	#define AVSP_IQ_WQ_PARAM_45 0x0e1b
1641
1642	static void vavs_save_regs(struct vdec_avs_hw_s *hw)
1643	{
1644	hw->reg_scratch_0 = READ_VREG(AV_SCRATCH_0);
1645	hw->reg_scratch_1 = READ_VREG(AV_SCRATCH_1);
1646	hw->reg_scratch_2 = READ_VREG(AV_SCRATCH_2);
1647	hw->reg_scratch_3 = READ_VREG(AV_SCRATCH_3);
1648	hw->reg_scratch_4 = READ_VREG(AV_SCRATCH_4);
1649	hw->reg_scratch_5 = READ_VREG(AV_SCRATCH_5);
1650	hw->reg_scratch_6 = READ_VREG(AV_SCRATCH_6);
1651	hw->reg_scratch_7 = READ_VREG(AV_SCRATCH_7);
1652	hw->reg_scratch_8 = READ_VREG(AV_SCRATCH_8);
1653	hw->reg_scratch_9 = READ_VREG(AV_SCRATCH_9);
1654	hw->reg_scratch_A = READ_VREG(AV_SCRATCH_A);
1655	hw->reg_scratch_B = READ_VREG(AV_SCRATCH_B);
1656	hw->reg_scratch_C = READ_VREG(AV_SCRATCH_C);
1657	hw->reg_scratch_D = READ_VREG(AV_SCRATCH_D);
1658	hw->reg_scratch_E = READ_VREG(AV_SCRATCH_E);
1659	hw->reg_scratch_F = READ_VREG(AV_SCRATCH_F);
1660	hw->reg_scratch_G = READ_VREG(AV_SCRATCH_G);
1661	hw->reg_scratch_H = READ_VREG(AV_SCRATCH_H);
1662	hw->reg_scratch_I = READ_VREG(AV_SCRATCH_I);
1663
1664	hw->reg_mb_width = READ_VREG(MB_WIDTH);
1665	hw->reg_viff_bit_cnt = READ_VREG(VIFF_BIT_CNT);
1666
1667	hw->reg_canvas_addr = READ_VREG(REC_CANVAS_ADDR);
1668	hw->reg_dbkr_canvas_addr = READ_VREG(DBKR_CANVAS_ADDR);
1669	hw->reg_dbkw_canvas_addr = READ_VREG(DBKW_CANVAS_ADDR);
1670	hw->reg_anc2_canvas_addr = READ_VREG(ANC2_CANVAS_ADDR);
1671	hw->reg_anc0_canvas_addr = READ_VREG(ANC0_CANVAS_ADDR);
1672	hw->reg_anc1_canvas_addr = READ_VREG(ANC1_CANVAS_ADDR);
1673
1674	hw->slice_ver_pos_pic_type = READ_VREG(SLICE_VER_POS_PIC_TYPE);
1675
1676	hw->vc1_control_reg = READ_VREG(VC1_CONTROL_REG);
1677	hw->avs_co_mb_wr_addr = READ_VREG(AVS_CO_MB_WR_ADDR);
1678	hw->slice_start_byte_01 = READ_VREG(SLICE_START_BYTE_01);
1679	hw->slice_start_byte_23 = READ_VREG(SLICE_START_BYTE_23);
1680	hw->vcop_ctrl_reg = READ_VREG(VCOP_CTRL_REG);
1681	hw->iqidct_control = READ_VREG(IQIDCT_CONTROL);
1682	hw->rv_ai_mb_count = READ_VREG(RV_AI_MB_COUNT);
1683	hw->slice_qp = READ_VREG(SLICE_QP);
1684
1685	hw->dc_scaler = READ_VREG(DC_SCALER);
1686	hw->avsp_iq_wq_param_01 = READ_VREG(AVSP_IQ_WQ_PARAM_01);
1687	hw->avsp_iq_wq_param_23 = READ_VREG(AVSP_IQ_WQ_PARAM_23);
1688	hw->avsp_iq_wq_param_45 = READ_VREG(AVSP_IQ_WQ_PARAM_45);
1689	hw->avs_co_mb_rd_addr = READ_VREG(AVS_CO_MB_RD_ADDR);
1690	hw->dblk_mb_wid_height = READ_VREG(DBLK_MB_WID_HEIGHT);
1691	hw->mc_pic_w_h = READ_VREG(MC_PIC_W_H);
1692	hw->avs_co_mb_rw_ctl = READ_VREG(AVS_CO_MB_RW_CTL);
1693
1694	hw->vld_decode_control = READ_VREG(VLD_DECODE_CONTROL);
1695	}
1696
1697	static void vavs_restore_regs(struct vdec_avs_hw_s *hw)
1698	{
1699	WRITE_VREG(AV_SCRATCH_0, hw->reg_scratch_0);
1700	WRITE_VREG(AV_SCRATCH_1, hw->reg_scratch_1);
1701	WRITE_VREG(AV_SCRATCH_2, hw->reg_scratch_2);
1702	WRITE_VREG(AV_SCRATCH_3, hw->reg_scratch_3);
1703	WRITE_VREG(AV_SCRATCH_4, hw->reg_scratch_4);
1704	WRITE_VREG(AV_SCRATCH_5, hw->reg_scratch_5);
1705	WRITE_VREG(AV_SCRATCH_6, hw->reg_scratch_6);
1706	WRITE_VREG(AV_SCRATCH_7, hw->reg_scratch_7);
1707	WRITE_VREG(AV_SCRATCH_8, hw->reg_scratch_8);
1708	WRITE_VREG(AV_SCRATCH_9, hw->reg_scratch_9);
1709	WRITE_VREG(AV_SCRATCH_A, hw->reg_scratch_A);
1710	WRITE_VREG(AV_SCRATCH_B, hw->reg_scratch_B);
1711	WRITE_VREG(AV_SCRATCH_C, hw->reg_scratch_C);
1712	WRITE_VREG(AV_SCRATCH_D, hw->reg_scratch_D);
1713	WRITE_VREG(AV_SCRATCH_E, hw->reg_scratch_E);
1714	WRITE_VREG(AV_SCRATCH_F, hw->reg_scratch_F);
1715	WRITE_VREG(AV_SCRATCH_G, hw->reg_scratch_G);
1716	WRITE_VREG(AV_SCRATCH_H, hw->reg_scratch_H);
1717	WRITE_VREG(AV_SCRATCH_I, hw->reg_scratch_I);
1718
1719	WRITE_VREG(MB_WIDTH, hw->reg_mb_width);
1720	WRITE_VREG(VIFF_BIT_CNT, hw->reg_viff_bit_cnt);
1721
1722	WRITE_VREG(REC_CANVAS_ADDR, hw->reg_canvas_addr);
1723	WRITE_VREG(DBKR_CANVAS_ADDR, hw->reg_dbkr_canvas_addr);
1724	WRITE_VREG(DBKW_CANVAS_ADDR, hw->reg_dbkw_canvas_addr);
1725	WRITE_VREG(ANC2_CANVAS_ADDR, hw->reg_anc2_canvas_addr);
1726	WRITE_VREG(ANC0_CANVAS_ADDR, hw->reg_anc0_canvas_addr);
1727	WRITE_VREG(ANC1_CANVAS_ADDR, hw->reg_anc1_canvas_addr);
1728
1729	WRITE_VREG(SLICE_VER_POS_PIC_TYPE, hw->slice_ver_pos_pic_type);
1730
1731	WRITE_VREG(VC1_CONTROL_REG, hw->vc1_control_reg);
1732	WRITE_VREG(AVS_CO_MB_WR_ADDR, hw->avs_co_mb_wr_addr);
1733	WRITE_VREG(SLICE_START_BYTE_01, hw->slice_start_byte_01);
1734	WRITE_VREG(SLICE_START_BYTE_23, hw->slice_start_byte_23);
1735	WRITE_VREG(VCOP_CTRL_REG, hw->vcop_ctrl_reg);
1736	WRITE_VREG(IQIDCT_CONTROL, hw->iqidct_control);
1737	WRITE_VREG(RV_AI_MB_COUNT, hw->rv_ai_mb_count);
1738	WRITE_VREG(SLICE_QP, hw->slice_qp);
1739
1740	WRITE_VREG(DC_SCALER, hw->dc_scaler);
1741	WRITE_VREG(AVSP_IQ_WQ_PARAM_01, hw->avsp_iq_wq_param_01);
1742	WRITE_VREG(AVSP_IQ_WQ_PARAM_23, hw->avsp_iq_wq_param_23);
1743	WRITE_VREG(AVSP_IQ_WQ_PARAM_45, hw->avsp_iq_wq_param_45);
1744	WRITE_VREG(AVS_CO_MB_RD_ADDR, hw->avs_co_mb_rd_addr);
1745	WRITE_VREG(DBLK_MB_WID_HEIGHT, hw->dblk_mb_wid_height);
1746	WRITE_VREG(MC_PIC_W_H, hw->mc_pic_w_h);
1747	WRITE_VREG(AVS_CO_MB_RW_CTL, hw->avs_co_mb_rw_ctl);
1748
1749	WRITE_VREG(VLD_DECODE_CONTROL, hw->vld_decode_control);
1750
1751	}
1752
1753	static int vavs_prot_init(struct vdec_avs_hw_s *hw)
1754	{
1755	int r = 0;
1756	#if DEBUG_MULTI_FLAG > 0
1757	if (hw->decode_pic_count == 0) {
1758	#endif
1759	#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
1760	WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6) | (1 << 4));
1761	WRITE_VREG(DOS_SW_RESET0, 0);
1762
1763	READ_VREG(DOS_SW_RESET0);
1764
1765	WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6) | (1 << 4));
1766	WRITE_VREG(DOS_SW_RESET0, 0);
1767
1768	WRITE_VREG(DOS_SW_RESET0, (1 << 9) | (1 << 8));
1769	WRITE_VREG(DOS_SW_RESET0, 0);
1770
1771	#else
1772	WRITE_RESET_REG(RESET0_REGISTER,
1773	RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
1774	READ_RESET_REG(RESET0_REGISTER);
1775	WRITE_RESET_REG(RESET0_REGISTER,
1776	RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
1777
1778	WRITE_RESET_REG(RESET2_REGISTER, RESET_PIC_DC | RESET_DBLK);
1779	#endif
1780	#if DEBUG_MULTI_FLAG > 0
1781	}
1782	#endif
1783	/***************** reset vld **********************************/
1784	WRITE_VREG(POWER_CTL_VLD, 0x10);
1785	WRITE_VREG_BITS(VLD_MEM_VIFIFO_CONTROL, 2, MEM_FIFO_CNT_BIT, 2);
1786	WRITE_VREG_BITS(VLD_MEM_VIFIFO_CONTROL, 8, MEM_LEVEL_CNT_BIT, 6);
1787	/*************************************************************/
1788	if (hw->m_ins_flag) {
1789	int i;
1790	if (hw->decode_pic_count == 0) {
1791	r = vavs_canvas_init(hw);
1792	for (i = 0; i < 4; i++) {
1793	WRITE_VREG(AV_SCRATCH_0 + i,
1794	hw->canvas_spec[i]
1795	);
1796	}
1797	} else
1798	vavs_restore_regs(hw);
1799
1800	for (i = 0; i < 4; i++) {
1801	canvas_config_ex(canvas_y(hw->canvas_spec[i]),
1802	hw->canvas_config[i][0].phy_addr,
1803	hw->canvas_config[i][0].width,
1804	hw->canvas_config[i][0].height,
1805	CANVAS_ADDR_NOWRAP,
1806	hw->canvas_config[i][0].block_mode,
1807	0);
1808
1809	canvas_config_ex(canvas_u(hw->canvas_spec[i]),
1810	hw->canvas_config[i][1].phy_addr,
1811	hw->canvas_config[i][1].width,
1812	hw->canvas_config[i][1].height,
1813	CANVAS_ADDR_NOWRAP,
1814	hw->canvas_config[i][1].block_mode,
1815	0);
1816	}
1817	} else {
1818	r = vavs_canvas_init(hw);
1819	#ifdef NV21
1820	if (firmware_sel == 0) {
1821	/* fixed canvas index */
1822	WRITE_VREG(AV_SCRATCH_0, canvas_base);
1823	WRITE_VREG(AV_SCRATCH_1, hw->vf_buf_num_used);
1824	} else {
1825	int ii;
1826
1827	for (ii = 0; ii < 4; ii++) {
1828	WRITE_VREG(AV_SCRATCH_0 + ii,
1829	(canvas_base + canvas_num * ii) |
1830	((canvas_base + canvas_num * ii + 1)
1831	<< 8) |
1832	((canvas_base + canvas_num * ii + 1)
1833	<< 16)
1834	);
1835	}
1836	/*
1837	*WRITE_VREG(AV_SCRATCH_0, 0x010100);
1838	*WRITE_VREG(AV_SCRATCH_1, 0x040403);
1839	*WRITE_VREG(AV_SCRATCH_2, 0x070706);
1840	*WRITE_VREG(AV_SCRATCH_3, 0x0a0a09);
1841	*/
1842	}
1843	#else
1844	/* index v << 16 | u << 8 | y */
1845	WRITE_VREG(AV_SCRATCH_0, 0x020100);
1846	WRITE_VREG(AV_SCRATCH_1, 0x050403);
1847	WRITE_VREG(AV_SCRATCH_2, 0x080706);
1848	WRITE_VREG(AV_SCRATCH_3, 0x0b0a09);
1849	#endif
1850	}
1851	/* notify ucode the buffer offset */
1852	if (hw->decode_pic_count == 0)
1853	WRITE_VREG(AV_SCRATCH_F, hw->buf_offset);
1854
1855	/* disable PSCALE for hardware sharing */
1856	WRITE_VREG(PSCALE_CTRL, 0);
1857
1858	if (hw->decode_pic_count == 0) {
1859	WRITE_VREG(AVS_SOS_COUNT, 0);
1860	WRITE_VREG(AVS_BUFFERIN, 0);
1861	WRITE_VREG(AVS_BUFFEROUT, 0);
1862	}
1863	if (error_recovery_mode)
1864	WRITE_VREG(AVS_ERROR_RECOVERY_MODE, 0);
1865	else
1866	WRITE_VREG(AVS_ERROR_RECOVERY_MODE, 1);
1867	/* clear mailbox interrupt */
1868	WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
1869
1870	/* enable mailbox interrupt */
1871	WRITE_VREG(ASSIST_MBOX1_MASK, 1);
1872	#if 1 /* def DEBUG_UCODE */
1873	if (hw->decode_pic_count == 0)
1874	WRITE_VREG(AV_SCRATCH_D, 0);
1875	#endif
1876
1877	#ifdef NV21
1878	SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 17);
1879	#endif
1880
1881	#ifdef PIC_DC_NEED_CLEAR
1882	CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 31);
1883	#endif
1884
1885	#ifdef AVSP_LONG_CABAC
1886	if (firmware_sel == 0) {
1887	WRITE_VREG(LONG_CABAC_DES_ADDR, es_write_addr_phy);
1888	WRITE_VREG(LONG_CABAC_REQ, 0);
1889	WRITE_VREG(LONG_CABAC_PIC_SIZE, 0);
1890	WRITE_VREG(LONG_CABAC_SRC_ADDR, 0);
1891	}
1892	#endif
1893
1894	#ifdef ENABLE_USER_DATA
1895	if (firmware_sel == 0) {
1896	WRITE_VREG(AV_SCRATCH_N, (u32)(hw->user_data_buffer_phys - hw->buf_offset));
1897	pr_debug("AV_SCRATCH_N = 0x%x\n", READ_VREG(AV_SCRATCH_N));
1898	}
1899	#endif
1900	if (hw->m_ins_flag) {
1901	if (vdec_frame_based(hw_to_vdec(hw)))
1902	WRITE_VREG(DECODE_MODE, DECODE_MODE_MULTI_FRAMEBASE);
1903	else
1904	WRITE_VREG(DECODE_MODE, DECODE_MODE_MULTI_STREAMBASE);
1905	WRITE_VREG(DECODE_LMEM_BUF_ADR, hw->lmem_phy_addr);
1906	} else
1907	WRITE_VREG(DECODE_MODE, DECODE_MODE_SINGLE);
1908	//WRITE_VREG(DECODE_MODE, DECODE_MODE_SINGLE);
1909	WRITE_VREG(DECODE_STOP_POS, udebug_flag);
1910
1911	return r;
1912	}
1913
1914	#if DEBUG_MULTI_FLAG > 0
1915	static int vavs_prot_init_vld_only(struct vdec_avs_hw_s *hw)
1916	{
1917	int r = 0;
1918	/***************** reset vld **********************************/
1919	WRITE_VREG(POWER_CTL_VLD, 0x10);
1920	WRITE_VREG_BITS(VLD_MEM_VIFIFO_CONTROL, 2, MEM_FIFO_CNT_BIT, 2);
1921	WRITE_VREG_BITS(VLD_MEM_VIFIFO_CONTROL, 8, MEM_LEVEL_CNT_BIT, 6);
1922	/*************************************************************/
1923	if (hw->m_ins_flag) {
1924	int i;
1925	if (hw->decode_pic_count == 0) {
1926	r = vavs_canvas_init(hw);
1927	for (i = 0; i < 4; i++) {
1928	WRITE_VREG(AV_SCRATCH_0 + i,
1929	hw->canvas_spec[i]
1930	);
1931	}
1932	} else
1933	vavs_restore_regs(hw);
1934
1935	for (i = 0; i < 4; i++) {
1936	canvas_config_ex(canvas_y(hw->canvas_spec[i]),
1937	hw->canvas_config[i][0].phy_addr,
1938	hw->canvas_config[i][0].width,
1939	hw->canvas_config[i][0].height,
1940	CANVAS_ADDR_NOWRAP,
1941	hw->canvas_config[i][0].block_mode,
1942	0);
1943
1944	canvas_config_ex(canvas_u(hw->canvas_spec[i]),
1945	hw->canvas_config[i][1].phy_addr,
1946	hw->canvas_config[i][1].width,
1947	hw->canvas_config[i][1].height,
1948	CANVAS_ADDR_NOWRAP,
1949	hw->canvas_config[i][1].block_mode,
1950	0);
1951	}
1952	}
1953	/* notify ucode the buffer offset */
1954	#if DEBUG_MULTI_FLAG == 0
1955	/* disable PSCALE for hardware sharing */
1956	WRITE_VREG(PSCALE_CTRL, 0);
1957
1958	if (hw->decode_pic_count == 0) {
1959	WRITE_VREG(AVS_SOS_COUNT, 0);
1960	WRITE_VREG(AVS_BUFFERIN, 0);
1961	WRITE_VREG(AVS_BUFFEROUT, 0);
1962	}
1963	if (error_recovery_mode)
1964	WRITE_VREG(AVS_ERROR_RECOVERY_MODE, 0);
1965	else
1966	WRITE_VREG(AVS_ERROR_RECOVERY_MODE, 1);
1967	/* clear mailbox interrupt */
1968	WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
1969
1970	/* enable mailbox interrupt */
1971	WRITE_VREG(ASSIST_MBOX1_MASK, 1);
1972
1973	#ifdef NV21
1974	SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 17);
1975	#endif
1976
1977	#ifdef PIC_DC_NEED_CLEAR
1978	CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 31);
1979	#endif
1980	#endif
1981	if (hw->m_ins_flag) {
1982	if (vdec_frame_based(hw_to_vdec(hw)))
1983	WRITE_VREG(DECODE_MODE, DECODE_MODE_MULTI_FRAMEBASE);
1984	else
1985	WRITE_VREG(DECODE_MODE, DECODE_MODE_MULTI_STREAMBASE);
1986	WRITE_VREG(DECODE_LMEM_BUF_ADR, hw->lmem_phy_addr);
1987	} else
1988	WRITE_VREG(DECODE_MODE, DECODE_MODE_SINGLE);
1989	//WRITE_VREG(DECODE_MODE, DECODE_MODE_SINGLE);
1990	WRITE_VREG(DECODE_STOP_POS, udebug_flag);
1991
1992	return r;
1993	}
1994	#endif
1995
1996	#ifdef AVSP_LONG_CABAC
1997	static unsigned char es_write_addr[MAX_CODED_FRAME_SIZE] __aligned(64);
1998	#endif
1999	static void vavs_local_init(struct vdec_avs_hw_s *hw)
2000	{
2001	int i;
2002
2003	hw->vavs_ratio = hw->vavs_amstream_dec_info.ratio;
2004
2005	hw->avi_flag = (unsigned long) hw->vavs_amstream_dec_info.param;
2006
2007	hw->frame_width = hw->frame_height = hw->frame_dur = hw->frame_prog = 0;
2008
2009	hw->throw_pb_flag = 1;
2010
2011	hw->total_frame = 0;
2012	hw->saved_resolution = 0;
2013	hw->next_pts = 0;
2014
2015	#ifdef DEBUG_PTS
2016	hw->pts_hit = hw->pts_missed = hw->pts_i_hit = hw->pts_i_missed = 0;
2017	#endif
2018	INIT_KFIFO(hw->display_q);
2019	INIT_KFIFO(hw->recycle_q);
2020	INIT_KFIFO(hw->newframe_q);
2021
2022	for (i = 0; i < VF_POOL_SIZE; i++) {
2023	const struct vframe_s *vf = &hw->vfpool[i];
2024
2025	hw->vfpool[i].index = vf_buf_num;
2026	hw->vfpool[i].bufWidth = 1920;
2027	kfifo_put(&hw->newframe_q, vf);
2028	}
2029	for (i = 0; i < vf_buf_num; i++)
2030	hw->vfbuf_use[i] = 0;
2031
2032	/*cur_vfpool = vfpool;*/
2033
2034	if (hw->recover_flag == 1)
2035	return;
2036
2037	if (hw->mm_blk_handle) {
2038	pr_info("decoder_bmmu_box_free\n");
2039	decoder_bmmu_box_free(hw->mm_blk_handle);
2040	hw->mm_blk_handle = NULL;
2041	}
2042
2043	hw->mm_blk_handle = decoder_bmmu_box_alloc_box(
2044	DRIVER_NAME,
2045	0,
2046	MAX_BMMU_BUFFER_NUM,
2047	4 + PAGE_SHIFT,
2048	CODEC_MM_FLAGS_CMA_CLEAR |
2049	CODEC_MM_FLAGS_FOR_VDECODER);
2050	if (hw->mm_blk_handle == NULL)
2051	pr_info("Error, decoder_bmmu_box_alloc_box fail\n");
2052
2053	}
2054
2055	static int vavs_vf_states(struct vframe_states *states, void *op_arg)
2056	{
2057	unsigned long flags;
2058	struct vdec_avs_hw_s *hw =
2059	(struct vdec_avs_hw_s *)op_arg;
2060
2061
2062	spin_lock_irqsave(&lock, flags);
2063	states->vf_pool_size = VF_POOL_SIZE;
2064	states->buf_free_num = kfifo_len(&hw->newframe_q);
2065	states->buf_avail_num = kfifo_len(&hw->display_q);
2066	states->buf_recycle_num = kfifo_len(&hw->recycle_q);
2067	if (step == 2)
2068	states->buf_avail_num = 0;
2069	spin_unlock_irqrestore(&lock, flags);
2070	return 0;
2071	}
2072
2073	#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
2074	static void vavs_ppmgr_reset(void)
2075	{
2076	vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_RESET, NULL);
2077
2078	vavs_local_init(ghw);
2079
2080	pr_info("vavs: vf_ppmgr_reset\n");
2081	}
2082	#endif
2083
2084	static void vavs_local_reset(struct vdec_avs_hw_s *hw)
2085	{
2086	mutex_lock(&vavs_mutex);
2087	hw->recover_flag = 1;
2088	pr_info("error, local reset\n");
2089	amvdec_stop();
2090	msleep(100);
2091	vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_RESET, NULL);
2092	vavs_local_init(hw);
2093	vavs_recover(hw);
2094
2095	#ifdef ENABLE_USER_DATA
2096	reset_userdata_fifo(1);
2097	#endif
2098
2099	amvdec_start();
2100	hw->recover_flag = 0;
2101	#if 0
2102	error_watchdog_count = 0;
2103
2104	pr_info("pc %x stream buf wp %x rp %x level %x\n",
2105	READ_VREG(MPC_E),
2106	READ_VREG(VLD_MEM_VIFIFO_WP),
2107	READ_VREG(VLD_MEM_VIFIFO_RP),
2108	READ_VREG(VLD_MEM_VIFIFO_LEVEL));
2109	#endif
2110
2111
2112
2113	mutex_unlock(&vavs_mutex);
2114	}
2115
2116	#if 0
2117	static struct work_struct fatal_error_wd_work;
2118	static struct work_struct notify_work;
2119	static atomic_t error_handler_run = ATOMIC_INIT(0);
2120	#endif
2121	static void vavs_fatal_error_handler(struct work_struct *work)
2122	{
2123	struct vdec_avs_hw_s *hw =
2124	container_of(work, struct vdec_avs_hw_s, fatal_error_wd_work);
2125	if (debug_flag & AVS_DEBUG_OLD_ERROR_HANDLE) {
2126	mutex_lock(&vavs_mutex);
2127	pr_info("vavs fatal error reset !\n");
2128	amvdec_stop();
2129	#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
2130	vavs_ppmgr_reset();
2131	#else
2132	vf_light_unreg_provider(&vavs_vf_prov);
2133	vavs_local_init(hw);
2134	vf_reg_provider(&vavs_vf_prov);
2135	#endif
2136	vavs_recover(hw);
2137	amvdec_start();
2138	mutex_unlock(&vavs_mutex);
2139	} else {
2140	pr_info("avs fatal_error_handler\n");
2141	vavs_local_reset(hw);
2142	}
2143	atomic_set(&hw->error_handler_run, 0);
2144	}
2145
2146	static void vavs_notify_work(struct work_struct *work)
2147	{
2148	struct vdec_avs_hw_s *hw =
2149	container_of(work, struct vdec_avs_hw_s, notify_work);
2150	if (hw->fr_hint_status == VDEC_NEED_HINT) {
2151	vf_notify_receiver(PROVIDER_NAME ,
2152	VFRAME_EVENT_PROVIDER_FR_HINT ,
2153	(void *)((unsigned long)hw->frame_dur));
2154	hw->fr_hint_status = VDEC_HINTED;
2155	}
2156	return;
2157	}
2158
2159	static void avs_set_clk(struct work_struct *work)
2160	{
2161	struct vdec_avs_hw_s *hw =
2162	container_of(work, struct vdec_avs_hw_s, set_clk_work);
2163	if (hw->frame_dur > 0 && hw->saved_resolution !=
2164	hw->frame_width * hw->frame_height * (96000 / hw->frame_dur)) {
2165	int fps = 96000 / hw->frame_dur;
2166
2167	hw->saved_resolution = hw->frame_width * hw->frame_height * fps;
2168	if (firmware_sel == 0 &&
2169	(debug_flag & AVS_DEBUG_USE_FULL_SPEED)) {
2170	vdec_source_changed(VFORMAT_AVS,
2171	4096, 2048, 60);
2172	} else {
2173	vdec_source_changed(VFORMAT_AVS,
2174	hw->frame_width, hw->frame_height, fps);
2175	}
2176
2177	}
2178	}
2179
2180	static void vavs_put_timer_func(unsigned long arg)
2181	{
2182	struct vdec_avs_hw_s *hw = (struct vdec_avs_hw_s *)arg;
2183	struct timer_list *timer = &hw->recycle_timer;
2184
2185	#ifndef HANDLE_AVS_IRQ
2186	vavs_isr();
2187	#endif
2188
2189	if (READ_VREG(AVS_SOS_COUNT)) {
2190	if (!error_recovery_mode) {
2191	#if 0
2192	if (debug_flag & AVS_DEBUG_OLD_ERROR_HANDLE) {
2193	mutex_lock(&vavs_mutex);
2194	pr_info("vavs fatal error reset !\n");
2195	amvdec_stop();
2196	#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
2197	vavs_ppmgr_reset();
2198	#else
2199	vf_light_unreg_provider(&vavs_vf_prov);
2200	vavs_local_init();
2201	vf_reg_provider(&vavs_vf_prov);
2202	#endif
2203	vavs_recover();
2204	amvdec_start();
2205	mutex_unlock(&vavs_mutex);
2206	} else {
2207	vavs_local_reset();
2208	}
2209	#else
2210	if (!atomic_read(&hw->error_handler_run)) {
2211	atomic_set(&hw->error_handler_run, 1);
2212	pr_info("AVS_SOS_COUNT = %d\n",
2213	READ_VREG(AVS_SOS_COUNT));
2214	pr_info("WP = 0x%x, RP = 0x%x, LEVEL = 0x%x, AVAIL = 0x%x, CUR_PTR = 0x%x\n",
2215	READ_VREG(VLD_MEM_VIFIFO_WP),
2216	READ_VREG(VLD_MEM_VIFIFO_RP),
2217	READ_VREG(VLD_MEM_VIFIFO_LEVEL),
2218	READ_VREG(VLD_MEM_VIFIFO_BYTES_AVAIL),
2219	READ_VREG(VLD_MEM_VIFIFO_CURR_PTR));
2220	schedule_work(&hw->fatal_error_wd_work);
2221	}
2222	#endif
2223	}
2224	}
2225	#if 0
2226	if (long_cabac_busy == 0 &&
2227	error_watchdog_threshold > 0 &&
2228	kfifo_len(&hw->display_q) == 0 &&
2229	READ_VREG(VLD_MEM_VIFIFO_LEVEL) >
2230	error_watchdog_buf_threshold) {
2231	pr_info("newq %d dispq %d recyq %d\r\n",
2232	kfifo_len(&hw->newframe_q),
2233	kfifo_len(&hw->display_q),
2234	kfifo_len(&hw->recycle_q));
2235	pr_info("pc %x stream buf wp %x rp %x level %x\n",
2236	READ_VREG(MPC_E),
2237	READ_VREG(VLD_MEM_VIFIFO_WP),
2238	READ_VREG(VLD_MEM_VIFIFO_RP),
2239	READ_VREG(VLD_MEM_VIFIFO_LEVEL));
2240	error_watchdog_count++;
2241	if (error_watchdog_count >= error_watchdog_threshold)
2242	vavs_local_reset();
2243	} else
2244	error_watchdog_count = 0;
2245	#endif
2246	if (radr != 0) {
2247	if (rval != 0) {
2248	WRITE_VREG(radr, rval);
2249	pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
2250	} else
2251	pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
2252	rval = 0;
2253	radr = 0;
2254	}
2255	if ((hw->ucode_pause_pos != 0) &&
2256	(hw->ucode_pause_pos != 0xffffffff) &&
2257	udebug_pause_pos != hw->ucode_pause_pos) {
2258	hw->ucode_pause_pos = 0;
2259	WRITE_VREG(DEBUG_REG1, 0);
2260	}
2261
2262	if (!kfifo_is_empty(&hw->recycle_q) && (READ_VREG(AVS_BUFFERIN) == 0)) {
2263	struct vframe_s *vf;
2264
2265	if (kfifo_get(&hw->recycle_q, &vf)) {
2266	if ((vf->index < vf_buf_num) &&
2267	(--hw->vfbuf_use[vf->index] == 0)) {
2268	debug_print(hw, PRINT_FLAG_DECODING,
2269	"%s WRITE_VREG(AVS_BUFFERIN, 0x%x) for vf index of %d\n",
2270	__func__,
2271	~(1 << vf->index), vf->index);
2272	WRITE_VREG(AVS_BUFFERIN, ~(1 << vf->index));
2273	vf->index = vf_buf_num;
2274	}
2275	kfifo_put(&hw->newframe_q,
2276	(const struct vframe_s *)vf);
2277	}
2278
2279	}
2280
2281	schedule_work(&hw->set_clk_work);
2282
2283	timer->expires = jiffies + PUT_INTERVAL;
2284
2285	add_timer(timer);
2286	}
2287
2288	#ifdef AVSP_LONG_CABAC
2289
2290	static void long_cabac_do_work(struct work_struct *work)
2291	{
2292	int status = 0;
2293	struct vdec_avs_hw_s *hw = gw;
2294	#ifdef PERFORMANCE_DEBUG
2295	pr_info("enter %s buf level (new %d, display %d, recycle %d)\r\n",
2296	__func__,
2297	kfifo_len(&hw->newframe_q),
2298	kfifo_len(&hw->display_q),
2299	kfifo_len(&hw->recycle_q)
2300	);
2301	#endif
2302	mutex_lock(&vavs_mutex);
2303	long_cabac_busy = 1;
2304	while (READ_VREG(LONG_CABAC_REQ)) {
2305	if (process_long_cabac() < 0) {
2306	status = -1;
2307	break;
2308	}
2309	}
2310	long_cabac_busy = 0;
2311	mutex_unlock(&vavs_mutex);
2312	#ifdef PERFORMANCE_DEBUG
2313	pr_info("exit %s buf level (new %d, display %d, recycle %d)\r\n",
2314	__func__,
2315	kfifo_len(&hw->newframe_q),
2316	kfifo_len(&hw->display_q),
2317	kfifo_len(&hw->recycle_q)
2318	);
2319	#endif
2320	if (status < 0) {
2321	pr_info("transcoding error, local reset\r\n");
2322	vavs_local_reset(hw);
2323	}
2324
2325	}
2326	#endif
2327
2328	#ifdef AVSP_LONG_CABAC
2329	static void init_avsp_long_cabac_buf(void)
2330	{
2331	#if 0
2332	es_write_addr_phy = (unsigned long)codec_mm_alloc_for_dma(
2333	"vavs",
2334	PAGE_ALIGN(MAX_CODED_FRAME_SIZE)/PAGE_SIZE,
2335	0, CODEC_MM_FLAGS_DMA_CPU);
2336	es_write_addr_virt = codec_mm_phys_to_virt(es_write_addr_phy);
2337
2338	#elif 0
2339	es_write_addr_virt =
2340	(void *)dma_alloc_coherent(amports_get_dma_device(),
2341	MAX_CODED_FRAME_SIZE, &es_write_addr_phy,
2342	GFP_KERNEL);
2343	#else
2344	/*es_write_addr_virt = kmalloc(MAX_CODED_FRAME_SIZE, GFP_KERNEL);
2345	* es_write_addr_virt = (void *)__get_free_pages(GFP_KERNEL,
2346	* get_order(MAX_CODED_FRAME_SIZE));
2347	*/
2348	es_write_addr_virt = &es_write_addr[0];
2349	if (es_write_addr_virt == NULL) {
2350	pr_err("%s: failed to alloc es_write_addr_virt buffer\n",
2351	__func__);
2352	return;
2353	}
2354
2355	es_write_addr_phy = dma_map_single(amports_get_dma_device(),
2356	es_write_addr_virt,
2357	MAX_CODED_FRAME_SIZE, DMA_BIDIRECTIONAL);
2358	if (dma_mapping_error(amports_get_dma_device(),
2359	es_write_addr_phy)) {
2360	pr_err("%s: failed to map es_write_addr_virt buffer\n",
2361	__func__);
2362	/*kfree(es_write_addr_virt);*/
2363	es_write_addr_virt = NULL;
2364	return;
2365	}
2366	#endif
2367
2368
2369	#ifdef BITSTREAM_READ_TMP_NO_CACHE
2370	bitstream_read_tmp =
2371	(void *)dma_alloc_coherent(amports_get_dma_device(),
2372	SVA_STREAM_BUF_SIZE, &bitstream_read_tmp_phy,
2373	GFP_KERNEL);
2374
2375	#else
2376
2377	bitstream_read_tmp = kmalloc(SVA_STREAM_BUF_SIZE, GFP_KERNEL);
2378	/*bitstream_read_tmp = (void *)__get_free_pages(GFP_KERNEL,
2379	*get_order(MAX_CODED_FRAME_SIZE));
2380	*/
2381	if (bitstream_read_tmp == NULL) {
2382	pr_err("%s: failed to alloc bitstream_read_tmp buffer\n",
2383	__func__);
2384	return;
2385	}
2386
2387	bitstream_read_tmp_phy = dma_map_single(amports_get_dma_device(),
2388	bitstream_read_tmp,
2389	SVA_STREAM_BUF_SIZE, DMA_FROM_DEVICE);
2390	if (dma_mapping_error(amports_get_dma_device(),
2391	bitstream_read_tmp_phy)) {
2392	pr_err("%s: failed to map rpm buffer\n", __func__);
2393	kfree(bitstream_read_tmp);
2394	bitstream_read_tmp = NULL;
2395	return;
2396	}
2397	#endif
2398	}
2399	#endif
2400
2401
2402	static s32 vavs_init(struct vdec_avs_hw_s *hw)
2403	{
2404	int ret, size = -1;
2405	struct firmware_s *fw;
2406	u32 fw_size = 0x1000 * 16;
2407	/*char *buf = vmalloc(0x1000 * 16);
2408
2409	if (IS_ERR_OR_NULL(buf))
2410	return -ENOMEM;
2411	*/
2412	fw = vmalloc(sizeof(struct firmware_s) + fw_size);
2413	if (IS_ERR_OR_NULL(fw))
2414	return -ENOMEM;
2415
2416	pr_info("vavs_init\n");
2417	//init_timer(&hw->recycle_timer);
2418
2419	//hw->stat |= STAT_TIMER_INIT;
2420
2421	amvdec_enable();
2422
2423	//vdec_enable_DMC(NULL);
2424
2425	vavs_local_init(hw);
2426
2427	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXM)
2428	size = get_firmware_data(VIDEO_DEC_AVS_MULTI, fw->data);
2429	else {
2430	if (firmware_sel == 1)
2431	size = get_firmware_data(VIDEO_DEC_AVS_NOCABAC, fw->data);
2432	#ifdef AVSP_LONG_CABAC
2433	else {
2434	init_avsp_long_cabac_buf();
2435	size = get_firmware_data(VIDEO_DEC_AVS_MULTI, fw->data);
2436	}
2437	#endif
2438	}
2439
2440	if (size < 0) {
2441	amvdec_disable();
2442	pr_err("get firmware fail.");
2443	/*vfree(buf);*/
2444	return -1;
2445	}
2446
2447	fw->len = size;
2448	hw->fw = fw;
2449
2450	if (hw->m_ins_flag) {
2451	init_timer(&hw->check_timer);
2452	hw->check_timer.data = (ulong) hw;
2453	hw->check_timer.function = check_timer_func;
2454	hw->check_timer.expires = jiffies + CHECK_INTERVAL;
2455
2456
2457	//add_timer(&hw->check_timer);
2458	hw->stat |= STAT_TIMER_ARM;
2459
2460	INIT_WORK(&hw->work, vavs_work);
2461
2462	hw->fw = fw;
2463	return 0;
2464	}
2465
2466	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXM)
2467	ret = amvdec_loadmc_ex(VFORMAT_AVS, NULL, fw->data);
2468	else if (firmware_sel == 1)
2469	ret = amvdec_loadmc_ex(VFORMAT_AVS, "avs_no_cabac", fw->data);
2470	else
2471	ret = amvdec_loadmc_ex(VFORMAT_AVS, NULL, fw->data);
2472
2473	if (ret < 0) {
2474	amvdec_disable();
2475	/*vfree(buf);*/
2476	pr_err("AVS: the %s fw loading failed, err: %x\n",
2477	tee_enabled() ? "TEE" : "local", ret);
2478	return -EBUSY;
2479	}
2480
2481	/*vfree(buf);*/
2482
2483	hw->stat |= STAT_MC_LOAD;
2484
2485
2486	/* enable AMRISC side protocol */
2487	ret = vavs_prot_init(hw);
2488	if (ret < 0)
2489	return ret;
2490
2491	#ifdef HANDLE_AVS_IRQ
2492	if (vdec_request_irq(VDEC_IRQ_1, vavs_isr,
2493	"vavs-irq", (void *)hw)) {
2494	amvdec_disable();
2495	pr_info("vavs irq register error.\n");
2496	return -ENOENT;
2497	}
2498	#endif
2499
2500	hw->stat |= STAT_ISR_REG;
2501	pr_info("%s %d\n", __func__, __LINE__);
2502
2503	#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
2504	vf_provider_init(&vavs_vf_prov, PROVIDER_NAME, &vavs_vf_provider, hw);
2505	vf_reg_provider(&vavs_vf_prov);
2506	vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL);
2507	#else
2508	vf_provider_init(&vavs_vf_prov, PROVIDER_NAME, &vavs_vf_provider, hw);
2509	vf_reg_provider(&vavs_vf_prov);
2510	#endif
2511	pr_info("%s %d\n", __func__, __LINE__);
2512
2513	if (hw->vavs_amstream_dec_info.rate != 0) {
2514	if (!hw->is_reset)
2515	vf_notify_receiver(PROVIDER_NAME,
2516	VFRAME_EVENT_PROVIDER_FR_HINT,
2517	(void *)((unsigned long)
2518	hw->vavs_amstream_dec_info.rate));
2519	hw->fr_hint_status = VDEC_HINTED;
2520	} else
2521	hw->fr_hint_status = VDEC_NEED_HINT;
2522
2523	hw->stat |= STAT_VF_HOOK;
2524
2525	hw->recycle_timer.data = (ulong)(hw);
2526	hw->recycle_timer.function = vavs_put_timer_func;
2527	hw->recycle_timer.expires = jiffies + PUT_INTERVAL;
2528	pr_info("%s %d\n", __func__, __LINE__);
2529
2530	add_timer(&hw->recycle_timer);
2531
2532	hw->stat |= STAT_TIMER_ARM;
2533
2534	#ifdef AVSP_LONG_CABAC
2535	if (firmware_sel == 0)
2536	INIT_WORK(&long_cabac_wd_work, long_cabac_do_work);
2537	#endif
2538	vdec_source_changed(VFORMAT_AVS,
2539	1920, 1080, 30);
2540	amvdec_start();
2541
2542	hw->stat |= STAT_VDEC_RUN;
2543	pr_info("%s %d\n", __func__, __LINE__);
2544	return 0;
2545	}
2546
2547	static int amvdec_avs_probe(struct platform_device *pdev)
2548	{
2549	struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
2550	struct vdec_avs_hw_s *hw = NULL;
2551
2552	if (pdata == NULL) {
2553	pr_info("amvdec_avs memory resource undefined.\n");
2554	return -EFAULT;
2555	}
2556
2557	hw = (struct vdec_avs_hw_s *)devm_kzalloc(&pdev->dev,
2558	sizeof(struct vdec_avs_hw_s), GFP_KERNEL);
2559	if (hw == NULL) {
2560	pr_info("\nammvdec_avs decoder driver alloc failed\n");
2561	return -ENOMEM;
2562	}
2563	pdata->private = hw;
2564	ghw = hw;
2565	atomic_set(&hw->error_handler_run, 0);
2566	hw->m_ins_flag = 0;
2567
2568	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXM || disable_longcabac_trans)
2569	firmware_sel = 1;
2570
2571	if (firmware_sel == 1) {
2572	vf_buf_num = 4;
2573	canvas_base = 0;
2574	canvas_num = 3;
2575	} else {
2576
2577	canvas_base = 128;
2578	canvas_num = 2; /*NV21*/
2579	}
2580
2581
2582	if (pdata->sys_info)
2583	hw->vavs_amstream_dec_info = *pdata->sys_info;
2584
2585	pr_info("%s (%d,%d) %d\n", __func__, hw->vavs_amstream_dec_info.width,
2586	hw->vavs_amstream_dec_info.height, hw->vavs_amstream_dec_info.rate);
2587
2588	pdata->dec_status = vavs_dec_status;
2589	pdata->set_isreset = vavs_set_isreset;
2590	hw->is_reset = 0;
2591
2592	pdata->user_data_read = NULL;
2593	pdata->reset_userdata_fifo = NULL;
2594
2595	vavs_vdec_info_init(hw);
2596
2597	#ifdef ENABLE_USER_DATA
2598	if (NULL == hw->user_data_buffer) {
2599	hw->user_data_buffer =
2600	dma_alloc_coherent(amports_get_dma_device(),
2601	USER_DATA_SIZE,
2602	&hw->user_data_buffer_phys, GFP_KERNEL);
2603	if (!hw->user_data_buffer) {
2604	pr_info("%s: Can not allocate hw->user_data_buffer\n",
2605	__func__);
2606	return -ENOMEM;
2607	}
2608	pr_debug("hw->user_data_buffer = 0x%p, hw->user_data_buffer_phys = 0x%x\n",
2609	hw->user_data_buffer, (u32)hw->user_data_buffer_phys);
2610	}
2611	#endif
2612	INIT_WORK(&hw->set_clk_work, avs_set_clk);
2613	if (vavs_init(hw) < 0) {
2614	pr_info("amvdec_avs init failed.\n");
2615	kfree(hw->gvs);
2616	hw->gvs = NULL;
2617	pdata->dec_status = NULL;
2618	return -ENODEV;
2619	}
2620	/*vdec = pdata;*/
2621
2622	INIT_WORK(&hw->fatal_error_wd_work, vavs_fatal_error_handler);
2623	atomic_set(&hw->error_handler_run, 0);
2624	#ifdef ENABLE_USER_DATA
2625	INIT_WORK(&hw->userdata_push_work, userdata_push_do_work);
2626	#endif
2627	INIT_WORK(&hw->notify_work, vavs_notify_work);
2628
2629	return 0;
2630	}
2631
2632	static int amvdec_avs_remove(struct platform_device *pdev)
2633	{
2634	struct vdec_avs_hw_s *hw = ghw;
2635
2636	cancel_work_sync(&hw->fatal_error_wd_work);
2637	atomic_set(&hw->error_handler_run, 0);
2638	#ifdef ENABLE_USER_DATA
2639	cancel_work_sync(&hw->userdata_push_work);
2640	#endif
2641	cancel_work_sync(&hw->notify_work);
2642	cancel_work_sync(&hw->set_clk_work);
2643	if (hw->stat & STAT_VDEC_RUN) {
2644	amvdec_stop();
2645	hw->stat &= ~STAT_VDEC_RUN;
2646	}
2647
2648	if (hw->stat & STAT_ISR_REG) {
2649	vdec_free_irq(VDEC_IRQ_1, (void *)vavs_dec_id);
2650	hw->stat &= ~STAT_ISR_REG;
2651	}
2652
2653	if (hw->stat & STAT_TIMER_ARM) {
2654	del_timer_sync(&hw->recycle_timer);
2655	hw->stat &= ~STAT_TIMER_ARM;
2656	}
2657	#ifdef AVSP_LONG_CABAC
2658	if (firmware_sel == 0) {
2659	mutex_lock(&vavs_mutex);
2660	cancel_work_sync(&long_cabac_wd_work);
2661	mutex_unlock(&vavs_mutex);
2662
2663	if (es_write_addr_virt) {
2664	#if 0
2665	codec_mm_free_for_dma("vavs", es_write_addr_phy);
2666	#else
2667	dma_unmap_single(amports_get_dma_device(),
2668	es_write_addr_phy,
2669	MAX_CODED_FRAME_SIZE, DMA_FROM_DEVICE);
2670	/*kfree(es_write_addr_virt);*/
2671	es_write_addr_virt = NULL;
2672	#endif
2673	}
2674
2675	#ifdef BITSTREAM_READ_TMP_NO_CACHE
2676	if (bitstream_read_tmp) {
2677	dma_free_coherent(amports_get_dma_device(),
2678	SVA_STREAM_BUF_SIZE, bitstream_read_tmp,
2679	bitstream_read_tmp_phy);
2680	bitstream_read_tmp = NULL;
2681	}
2682	#else
2683	if (bitstream_read_tmp) {
2684	dma_unmap_single(amports_get_dma_device(),
2685	bitstream_read_tmp_phy,
2686	SVA_STREAM_BUF_SIZE, DMA_FROM_DEVICE);
2687	kfree(bitstream_read_tmp);
2688	bitstream_read_tmp = NULL;
2689	}
2690	#endif
2691	}
2692	#endif
2693	if (hw->stat & STAT_VF_HOOK) {
2694	if (hw->fr_hint_status == VDEC_HINTED && !hw->is_reset)
2695	vf_notify_receiver(PROVIDER_NAME,
2696	VFRAME_EVENT_PROVIDER_FR_END_HINT, NULL);
2697	hw->fr_hint_status = VDEC_NO_NEED_HINT;
2698	vf_unreg_provider(&vavs_vf_prov);
2699	hw->stat &= ~STAT_VF_HOOK;
2700	}
2701
2702	#ifdef ENABLE_USER_DATA
2703	if (hw->user_data_buffer != NULL) {
2704	dma_free_coherent(
2705	amports_get_dma_device(),
2706	USER_DATA_SIZE,
2707	hw->user_data_buffer,
2708	hw->user_data_buffer_phys);
2709	hw->user_data_buffer = NULL;
2710	hw->user_data_buffer_phys = 0;
2711	}
2712	#endif
2713
2714	if (hw->fw) {
2715	vfree(hw->fw);
2716	hw->fw = NULL;
2717	}
2718
2719	amvdec_disable();
2720	//vdec_disable_DMC(NULL);
2721
2722	hw->pic_type = 0;
2723	if (hw->mm_blk_handle) {
2724	decoder_bmmu_box_free(hw->mm_blk_handle);
2725	hw->mm_blk_handle = NULL;
2726	}
2727	#ifdef DEBUG_PTS
2728	pr_debug("pts hit %d, pts missed %d, i hit %d, missed %d\n", hw->pts_hit,
2729	hw->pts_missed, hw->pts_i_hit, hw->pts_i_missed);
2730	pr_debug("total frame %d, hw->avi_flag %d, rate %d\n", hw->total_frame, hw->avi_flag,
2731	hw->vavs_amstream_dec_info.rate);
2732	#endif
2733	kfree(hw->gvs);
2734	hw->gvs = NULL;
2735
2736	return 0;
2737	}
2738
2739	/****************************************/
2740
2741	static struct platform_driver amvdec_avs_driver = {
2742	.probe = amvdec_avs_probe,
2743	.remove = amvdec_avs_remove,
2744	.driver = {
2745	.name = DRIVER_NAME,
2746	}
2747	};
2748
2749
2750	static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask)
2751	{
2752	struct vdec_avs_hw_s *hw =
2753	(struct vdec_avs_hw_s *)vdec->private;
2754	int ret = 1;
2755
2756	if ((hw->buf_status & 0xf) == 0xf &&
2757	kfifo_len(&hw->recycle_q) == 0)
2758	ret = 0;
2759
2760	if (ret)
2761	hw->not_run_ready = 0;
2762	else
2763	hw->not_run_ready++;
2764
2765	if (ret != 0) {
2766	if (vdec->parallel_dec == 1)
2767	return (unsigned long)(CORE_MASK_VDEC_1);
2768	else
2769	return (unsigned long)(CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
2770	} else
2771	return 0;
2772	}
2773
2774	static void vavs_work(struct work_struct *work)
2775	{
2776	struct vdec_avs_hw_s *hw =
2777	container_of(work, struct vdec_avs_hw_s, work);
2778	struct vdec_s *vdec = hw_to_vdec(hw);
2779	if (hw->dec_result != DEC_RESULT_AGAIN)
2780	debug_print(hw, PRINT_FLAG_RUN_FLOW,
2781	"ammvdec_avs: vavs_work,result=%d,status=%d\n",
2782	hw->dec_result, hw_to_vdec(hw)->next_status);
2783	hw->again_flag = 0;
2784	if (hw->dec_result == DEC_RESULT_USERDATA) {
2785	userdata_push_process(hw);
2786	return;
2787	} else if (hw->dec_result == DEC_RESULT_DONE) {
2788	hw->buf_recycle_status = 0;
2789	if (!hw->ctx_valid)
2790	hw->ctx_valid = 1;
2791	vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
2792	} else if (hw->dec_result == DEC_RESULT_AGAIN
2793	&& (hw_to_vdec(hw)->next_status !=
2794	VDEC_STATUS_DISCONNECTED)) {
2795	/*
2796	stream base: stream buf empty or timeout
2797	frame base: vdec_prepare_input fail
2798	*/
2799	hw->again_flag = 1;
2800	if (!vdec_has_more_input(hw_to_vdec(hw))) {
2801	hw->dec_result = DEC_RESULT_EOS;
2802	vdec_schedule_work(&hw->work);
2803	return;
2804	}
2805	} else if (hw->dec_result == DEC_RESULT_GET_DATA
2806	&& (hw_to_vdec(hw)->next_status !=
2807	VDEC_STATUS_DISCONNECTED)) {
2808	if (!vdec_has_more_input(hw_to_vdec(hw))) {
2809	hw->dec_result = DEC_RESULT_EOS;
2810	vdec_schedule_work(&hw->work);
2811	return;
2812	}
2813	debug_print(hw, PRINT_FLAG_VLD_DETAIL,
2814	"%s DEC_RESULT_GET_DATA %x %x %x\n",
2815	__func__,
2816	READ_VREG(VLD_MEM_VIFIFO_LEVEL),
2817	READ_VREG(VLD_MEM_VIFIFO_WP),
2818	READ_VREG(VLD_MEM_VIFIFO_RP));
2819	vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
2820	vdec_clean_input(hw_to_vdec(hw));
2821	return;
2822	} else if (hw->dec_result == DEC_RESULT_FORCE_EXIT) {
2823	debug_print(hw, PRINT_FLAG_ERROR,
2824	"%s: force exit\n", __func__);
2825	if (hw->stat & STAT_ISR_REG) {
2826	amvdec_stop();
2827	/*disable mbox interrupt */
2828	WRITE_VREG(ASSIST_MBOX1_MASK, 0);
2829	vdec_free_irq(VDEC_IRQ_1, (void *)hw);
2830	hw->stat &= ~STAT_ISR_REG;
2831	}
2832	} else if (hw->dec_result == DEC_RESULT_EOS) {
2833	pr_info("%s: end of stream\n", __func__);
2834	if (hw->stat & STAT_VDEC_RUN) {
2835	amvdec_stop();
2836	hw->stat &= ~STAT_VDEC_RUN;
2837	}
2838	hw->eos = 1;
2839	vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
2840	vdec_clean_input(hw_to_vdec(hw));
2841	}
2842	if (hw->stat & STAT_VDEC_RUN) {
2843	#if DEBUG_MULTI_FLAG == 1
2844	#else
2845	amvdec_stop();
2846	#endif
2847	hw->stat &= ~STAT_VDEC_RUN;
2848	}
2849	/*wait_vmmpeg12_search_done(hw);*/
2850	if (hw->stat & STAT_TIMER_ARM) {
2851	del_timer_sync(&hw->check_timer);
2852	hw->stat &= ~STAT_TIMER_ARM;
2853	}
2854
2855	if (vdec->parallel_dec == 1)
2856	vdec_core_finish_run(hw_to_vdec(hw), CORE_MASK_VDEC_1);
2857	else
2858	vdec_core_finish_run(hw_to_vdec(hw), CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
2859
2860	if (hw->vdec_cb) {
2861	hw->vdec_cb(hw_to_vdec(hw), hw->vdec_cb_arg);
2862	debug_print(hw, 0x80000,
2863	"%s:\n", __func__);
2864	}
2865	}
2866
2867
2868	static void reset_process_time(struct vdec_avs_hw_s *hw)
2869	{
2870	if (!hw->m_ins_flag)
2871	return;
2872	if (hw->start_process_time) {
2873	unsigned process_time =
2874	1000 * (jiffies - hw->start_process_time) / HZ;
2875	hw->start_process_time = 0;
2876	if (process_time > max_process_time[DECODE_ID(hw)])
2877	max_process_time[DECODE_ID(hw)] = process_time;
2878	}
2879	}
2880	static void start_process_time(struct vdec_avs_hw_s *hw)
2881	{
2882	hw->decode_timeout_count = 2;
2883	hw->start_process_time = jiffies;
2884	}
2885
2886	static void handle_decoding_error(struct vdec_avs_hw_s *hw)
2887	{
2888	int i;
2889	unsigned long flags;
2890	struct vframe_s *vf;
2891	spin_lock_irqsave(&lock, flags);
2892	for (i = 0; i < VF_POOL_SIZE; i++) {
2893	vf = &hw->vfpool[i];
2894	if (vf->index < vf_buf_num)
2895	vf->index = -1;
2896	}
2897	for (i = 0; i < vf_buf_num; i++)
2898	hw->vfbuf_use[i] = 0;
2899	hw->reset_decode_flag = 1;
2900	hw->buf_status = 0;
2901	spin_unlock_irqrestore(&lock, flags);
2902	}
2903
2904	static void timeout_process(struct vdec_avs_hw_s *hw)
2905	{
2906	struct vdec_s *vdec = hw_to_vdec(hw);
2907	amvdec_stop();
2908	handle_decoding_error(hw);
2909	debug_print(hw, PRINT_FLAG_ERROR,
2910	"%s decoder timeout, status=%d, level=%d\n",
2911	__func__, vdec->status, READ_VREG(VLD_MEM_VIFIFO_LEVEL));
2912	hw->dec_result = DEC_RESULT_DONE;
2913	reset_process_time(hw);
2914	hw->first_i_frame_ready = 0;
2915	vdec_schedule_work(&hw->work);
2916	}
2917
2918
2919	static void recycle_frame_bufferin(struct vdec_avs_hw_s *hw)
2920	{
2921	if (!kfifo_is_empty(&hw->recycle_q) && (READ_VREG(AVS_BUFFERIN) == 0)) {
2922	struct vframe_s *vf;
2923
2924	if (kfifo_get(&hw->recycle_q, &vf)) {
2925	if ((vf->index < vf_buf_num) &&
2926	(vf->index >= 0) &&
2927	(--hw->vfbuf_use[vf->index] == 0)) {
2928	hw->buf_recycle_status |= (1 << vf->index);
2929	WRITE_VREG(AVS_BUFFERIN, ~(1 << vf->index));
2930	debug_print(hw, PRINT_FLAG_DECODING,
2931	"%s WRITE_VREG(AVS_BUFFERIN, 0x%x) for vf index of %d => buf_recycle_status 0x%x\n",
2932	__func__,
2933	READ_VREG(AVS_BUFFERIN), vf->index,
2934	hw->buf_recycle_status);
2935	}
2936	vf->index = vf_buf_num;
2937	kfifo_put(&hw->newframe_q,
2938	(const struct vframe_s *)vf);
2939	}
2940
2941	}
2942
2943	}
2944
2945	static void recycle_frames(struct vdec_avs_hw_s *hw)
2946	{
2947	while (!kfifo_is_empty(&hw->recycle_q)) {
2948	struct vframe_s *vf;
2949
2950	if (kfifo_get(&hw->recycle_q, &vf)) {
2951	if ((vf->index < vf_buf_num) &&
2952	(vf->index >= 0) &&
2953	(--hw->vfbuf_use[vf->index] == 0)) {
2954	hw->buf_recycle_status |= (1 << vf->index);
2955	debug_print(hw, PRINT_FLAG_DECODING,
2956	"%s for vf index of %d => buf_recycle_status 0x%x\n",
2957	__func__,
2958	vf->index,
2959	hw->buf_recycle_status);
2960	}
2961	vf->index = vf_buf_num;
2962	kfifo_put(&hw->newframe_q,
2963	(const struct vframe_s *)vf);
2964	}
2965
2966	}
2967
2968	}
2969
2970
2971	static void check_timer_func(unsigned long arg)
2972	{
2973	struct vdec_avs_hw_s *hw = (struct vdec_avs_hw_s *)arg;
2974	struct vdec_s *vdec = hw_to_vdec(hw);
2975	unsigned int timeout_val = decode_timeout_val;
2976	unsigned long flags;
2977
2978	if (hw->m_ins_flag &&
2979	(debug_flag &
2980	DEBUG_WAIT_DECODE_DONE_WHEN_STOP) == 0 &&
2981	vdec->next_status ==
2982	VDEC_STATUS_DISCONNECTED) {
2983	hw->dec_result = DEC_RESULT_FORCE_EXIT;
2984	vdec_schedule_work(&hw->work);
2985	debug_print(hw,
2986	0, "vdec requested to be disconnected\n");
2987	return;
2988	}
2989
2990	/*recycle*/
2991	if (!hw->m_ins_flag ||
2992	hw->dec_result == DEC_RESULT_NONE) {
2993	spin_lock_irqsave(&lock, flags);
2994	recycle_frame_bufferin(hw);
2995	spin_unlock_irqrestore(&lock, flags);
2996	}
2997	if (radr != 0) {
2998	if (rval != 0) {
2999	WRITE_VREG(radr, rval);
3000	pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
3001	} else
3002	pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
3003	rval = 0;
3004	radr = 0;
3005	}
3006	if (dbg_cmd != 0) {
3007	if (dbg_cmd == 1) {
3008	int r = vdec_sync_input(vdec);
3009	dbg_cmd = 0;
3010	pr_info(
3011	"vdec_sync_input=>0x%x, (lev %x, wp %x rp %x, prp %x, pwp %x)\n",
3012	r,
3013	READ_VREG(VLD_MEM_VIFIFO_LEVEL),
3014	READ_VREG(VLD_MEM_VIFIFO_WP),
3015	READ_VREG(VLD_MEM_VIFIFO_RP),
3016	READ_PARSER_REG(PARSER_VIDEO_RP),
3017	READ_PARSER_REG(PARSER_VIDEO_WP));
3018	}
3019	}
3020
3021	if ((debug_flag & DEBUG_FLAG_DISABLE_TIMEOUT) == 0 &&
3022	(input_frame_based(vdec) ||
3023	(READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0x100)) &&
3024	(timeout_val > 0) &&
3025	(hw->start_process_time > 0) &&
3026	((1000 * (jiffies - hw->start_process_time) / HZ)
3027	> timeout_val)) {
3028	if (hw->last_vld_level == READ_VREG(VLD_MEM_VIFIFO_LEVEL)) {
3029	if (hw->decode_timeout_count > 0)
3030	hw->decode_timeout_count--;
3031	if (hw->decode_timeout_count == 0)
3032	timeout_process(hw);
3033	}
3034	hw->last_vld_level = READ_VREG(VLD_MEM_VIFIFO_LEVEL);
3035	}
3036
3037	if (READ_VREG(AVS_SOS_COUNT)) {
3038	if (!error_recovery_mode) {
3039	amvdec_stop();
3040	handle_decoding_error(hw);
3041	debug_print(hw, PRINT_FLAG_ERROR,
3042	"%s decoder error, status=%d, level=%d, AVS_SOS_COUNT=0x%x\n",
3043	__func__, vdec->status, READ_VREG(VLD_MEM_VIFIFO_LEVEL),
3044	READ_VREG(AVS_SOS_COUNT));
3045	hw->dec_result = DEC_RESULT_DONE;
3046	reset_process_time(hw);
3047	hw->first_i_frame_ready = 0;
3048	vdec_schedule_work(&hw->work);
3049	}
3050	}
3051
3052	if ((hw->ucode_pause_pos != 0) &&
3053	(hw->ucode_pause_pos != 0xffffffff) &&
3054	udebug_pause_pos != hw->ucode_pause_pos) {
3055	hw->ucode_pause_pos = 0;
3056	WRITE_VREG(DEBUG_REG1, 0);
3057	}
3058
3059	if (vdec->next_status == VDEC_STATUS_DISCONNECTED) {
3060	hw->dec_result = DEC_RESULT_FORCE_EXIT;
3061	vdec_schedule_work(&hw->work);
3062	pr_info("vdec requested to be disconnected\n");
3063	return;
3064	}
3065
3066	mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
3067	}
3068
3069	static int avs_hw_ctx_restore(struct vdec_avs_hw_s *hw)
3070	{
3071	/*int r = 0;*/
3072	#if DEBUG_MULTI_FLAG > 0
3073	if (hw->decode_pic_count > 0)
3074	vavs_prot_init_vld_only(hw);
3075	else
3076	#endif
3077	vavs_prot_init(hw);
3078	return 0;
3079	}
3080
3081	static unsigned char get_data_check_sum
3082	(struct vdec_avs_hw_s *hw, int size)
3083	{
3084	int jj;
3085	int sum = 0;
3086	u8 *data = NULL;
3087
3088	if (!hw->chunk->block->is_mapped)
3089	data = codec_mm_vmap(hw->chunk->block->start +
3090	hw->chunk->offset, size);
3091	else
3092	data = ((u8 *)hw->chunk->block->start_virt) +
3093	hw->chunk->offset;
3094
3095	for (jj = 0; jj < size; jj++)
3096	sum += data[jj];
3097
3098	if (!hw->chunk->block->is_mapped)
3099	codec_mm_unmap_phyaddr(data);
3100	return sum;
3101	}
3102
3103	static void run(struct vdec_s *vdec, unsigned long mask,
3104	void (*callback)(struct vdec_s *, void *),
3105	void *arg)
3106	{
3107	struct vdec_avs_hw_s *hw =
3108	(struct vdec_avs_hw_s *)vdec->private;
3109	int save_reg = READ_VREG(POWER_CTL_VLD);
3110	int size, ret;
3111	/* reset everything except DOS_TOP[1] and APB_CBUS[0]*/
3112	#if DEBUG_MULTI_FLAG > 0
3113	if (hw->decode_pic_count == 0) {
3114	#endif
3115	WRITE_VREG(DOS_SW_RESET0, 0xfffffff0);
3116	WRITE_VREG(DOS_SW_RESET0, 0);
3117	WRITE_VREG(POWER_CTL_VLD, save_reg);
3118	hw->run_count++;
3119	vdec_reset_core(vdec);
3120	#if DEBUG_MULTI_FLAG > 0
3121	}
3122	#endif
3123	hw->vdec_cb_arg = arg;
3124	hw->vdec_cb = callback;
3125
3126	size = vdec_prepare_input(vdec, &hw->chunk);
3127	if (debug & DEBUG_FLAG_PREPARE_MORE_INPUT) {
3128	if (size < start_decode_buf_level) {
3129	/*debug_print(hw, PRINT_FLAG_VLD_DETAIL,
3130	"DEC_RESULT_AGAIN %x %x %x\n",
3131	READ_VREG(VLD_MEM_VIFIFO_LEVEL),
3132	READ_VREG(VLD_MEM_VIFIFO_WP),
3133	READ_VREG(VLD_MEM_VIFIFO_RP));*/
3134
3135	hw->input_empty++;
3136	hw->dec_result = DEC_RESULT_AGAIN;
3137	vdec_schedule_work(&hw->work);
3138	return;
3139	}
3140	} else {
3141	if (size < 0) {
3142	hw->input_empty++;
3143	hw->dec_result = DEC_RESULT_AGAIN;
3144	vdec_schedule_work(&hw->work);
3145	return;
3146	}
3147	}
3148	if (input_frame_based(vdec)) {
3149	u8 *data = NULL;
3150
3151	if (!hw->chunk->block->is_mapped)
3152	data = codec_mm_vmap(hw->chunk->block->start +
3153	hw->chunk->offset, size);
3154	else
3155	data = ((u8 *)hw->chunk->block->start_virt) +
3156	hw->chunk->offset;
3157
3158	if (debug_flag & PRINT_FLAG_RUN_FLOW
3159	) {
3160	debug_print(hw, 0,
3161	"%s decode_pic_count %d buf_recycle_status 0x%x: size 0x%x sum 0x%x %02x %02x %02x %02x %02x %02x .. %02x %02x %02x %02x\n",
3162	__func__, hw->decode_pic_count,
3163	hw->buf_recycle_status,
3164	size, get_data_check_sum(hw, size),
3165	data[0], data[1], data[2], data[3],
3166	data[4], data[5], data[size - 4],
3167	data[size - 3], data[size - 2],
3168	data[size - 1]);
3169	}
3170	if (debug_flag & PRINT_FRAMEBASE_DATA
3171	) {
3172	int jj;
3173
3174	for (jj = 0; jj < size; jj++) {
3175	if ((jj & 0xf) == 0)
3176	debug_print(hw,
3177	PRINT_FRAMEBASE_DATA,
3178	"%06x:", jj);
3179	debug_print(hw,
3180	PRINT_FRAMEBASE_DATA,
3181	"%02x ", data[jj]);
3182	if (((jj + 1) & 0xf) == 0)
3183	debug_print(hw,
3184	PRINT_FRAMEBASE_DATA,
3185	"\n");
3186	}
3187	}
3188
3189	if (!hw->chunk->block->is_mapped)
3190	codec_mm_unmap_phyaddr(data);
3191	} else
3192	debug_print(hw, PRINT_FLAG_RUN_FLOW,
3193	"%s decode_pic_count %d buf_recycle_status 0x%x: %x %x %x %x %x size 0x%x\n",
3194	__func__,
3195	hw->decode_pic_count,
3196	hw->buf_recycle_status,
3197	READ_VREG(VLD_MEM_VIFIFO_LEVEL),
3198	READ_VREG(VLD_MEM_VIFIFO_WP),
3199	READ_VREG(VLD_MEM_VIFIFO_RP),
3200	READ_PARSER_REG(PARSER_VIDEO_RP),
3201	READ_PARSER_REG(PARSER_VIDEO_WP),
3202	size);
3203
3204
3205	hw->input_empty = 0;
3206	debug_print(hw, PRINT_FLAG_RUN_FLOW,
3207	"%s,%d, size=%d\n", __func__, __LINE__, size);
3208	vdec_enable_input(vdec);
3209	hw->init_flag = 1;
3210
3211	if (hw->chunk)
3212	debug_print(hw, PRINT_FLAG_RUN_FLOW,
3213	"input chunk offset %d, size %d\n",
3214	hw->chunk->offset, hw->chunk->size);
3215
3216	hw->dec_result = DEC_RESULT_NONE;
3217	/*vdec->mc_loaded = 0;*/
3218	if (vdec->mc_loaded) {
3219	/*firmware have load before,
3220	and not changes to another.
3221	ignore reload.
3222	*/
3223	} else {
3224	ret = amvdec_vdec_loadmc_buf_ex(VFORMAT_AVS, "avs_multi", vdec,
3225	hw->fw->data, hw->fw->len);
3226	if (ret < 0) {
3227	pr_err("[%d] %s: the %s fw loading failed, err: %x\n", vdec->id,
3228	hw->fw->name, tee_enabled() ? "TEE" : "local", ret);
3229	hw->dec_result = DEC_RESULT_FORCE_EXIT;
3230	vdec_schedule_work(&hw->work);
3231	return;
3232	}
3233	vdec->mc_loaded = 1;
3234	vdec->mc_type = VFORMAT_AVS;
3235	}
3236
3237	if (avs_hw_ctx_restore(hw) < 0) {
3238	hw->dec_result = DEC_RESULT_ERROR;
3239	debug_print(hw, PRINT_FLAG_ERROR,
3240	"ammvdec_avs: error HW context restore\n");
3241	vdec_schedule_work(&hw->work);
3242	return;
3243	}
3244	/*wmb();*/
3245	hw->stat |= STAT_MC_LOAD;
3246	hw->last_vld_level = 0;
3247
3248	debug_print(hw, PRINT_FLAG_DECODING,
3249	"%s READ_VREG(AVS_BUFFERIN)=0x%x, recycle_q num %d\n",
3250	__func__, READ_VREG(AVS_BUFFERIN),
3251	kfifo_len(&hw->recycle_q));
3252	recycle_frames(hw);
3253	if (hw->reset_decode_flag) {
3254	hw->buf_recycle_status = 0xff;
3255	WRITE_VREG(AVS_BUFFERIN, 0);
3256	WRITE_VREG(AVS_BUFFEROUT, 0);
3257	}
3258	WRITE_VREG(DECODE_STATUS,
3259	hw->decode_pic_count |
3260	((~hw->buf_recycle_status) << 24));
3261	hw->buf_recycle_status = 0;
3262	hw->reset_decode_flag = 0;
3263
3264	start_process_time(hw);
3265	#if DEBUG_MULTI_FLAG == 1
3266	if (hw->decode_pic_count > 0)
3267	WRITE_VREG(DECODE_STATUS, 0xff);
3268	else
3269	#endif
3270	amvdec_start();
3271	hw->stat |= STAT_VDEC_RUN;
3272
3273	hw->stat |= STAT_TIMER_ARM;
3274
3275	mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
3276	}
3277
3278	static void reset(struct vdec_s *vdec)
3279	{
3280	}
3281
3282	static irqreturn_t vmavs_isr_thread_fn(struct vdec_s *vdec, int irq)
3283	{
3284	return IRQ_HANDLED;
3285	}
3286
3287	static irqreturn_t vmavs_isr(struct vdec_s *vdec, int irq)
3288	{
3289	struct vdec_avs_hw_s *hw =
3290	(struct vdec_avs_hw_s *)vdec->private;
3291
3292	return vavs_isr(0, hw);
3293
3294	}
3295
3296	static void vmavs_dump_state(struct vdec_s *vdec)
3297	{
3298	struct vdec_avs_hw_s *hw =
3299	(struct vdec_avs_hw_s *)vdec->private;
3300
3301	debug_print(hw, 0,
3302	"====== %s\n", __func__);
3303
3304	debug_print(hw, 0,
3305	"width/height (%d/%d), dur %d\n",
3306	hw->frame_width,
3307	hw->frame_height,
3308	hw->frame_dur
3309	);
3310
3311	debug_print(hw, 0,
3312	"is_framebase(%d), decode_status 0x%x, buf_status 0x%x, buf_recycle_status 0x%x, eos %d, state 0x%x, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d\n",
3313	vdec_frame_based(vdec),
3314	READ_VREG(DECODE_STATUS) & 0xff,
3315	hw->buf_status,
3316	hw->buf_recycle_status,
3317	hw->eos,
3318	hw->stat,
3319	hw->dec_result,
3320	hw->decode_pic_count,
3321	hw->display_frame_count,
3322	hw->run_count,
3323	hw->not_run_ready,
3324	hw->input_empty
3325	);
3326
3327	if (vf_get_receiver(vdec->vf_provider_name)) {
3328	enum receviver_start_e state =
3329	vf_notify_receiver(vdec->vf_provider_name,
3330	VFRAME_EVENT_PROVIDER_QUREY_STATE,
3331	NULL);
3332	debug_print(hw, 0,
3333	"\nreceiver(%s) state %d\n",
3334	vdec->vf_provider_name,
3335	state);
3336	}
3337
3338	debug_print(hw, 0,
3339	"%s, newq(%d/%d), dispq(%d/%d)recycleq(%d/%d) drop %d vf peek %d, prepare/get/put (%d/%d/%d)\n",
3340	__func__,
3341	kfifo_len(&hw->newframe_q),
3342	VF_POOL_SIZE,
3343	kfifo_len(&hw->display_q),
3344	VF_POOL_SIZE,
3345	kfifo_len(&hw->recycle_q),
3346	VF_POOL_SIZE,
3347	hw->drop_frame_count,
3348	hw->peek_num,
3349	hw->prepare_num,
3350	hw->get_num,
3351	hw->put_num
3352	);
3353
3354	debug_print(hw, 0,
3355	"DECODE_STATUS=0x%x\n",
3356	READ_VREG(DECODE_STATUS));
3357	debug_print(hw, 0,
3358	"MPC_E=0x%x\n",
3359	READ_VREG(MPC_E));
3360	debug_print(hw, 0,
3361	"DECODE_MODE=0x%x\n",
3362	READ_VREG(DECODE_MODE));
3363	debug_print(hw, 0,
3364	"MBY_MBX=0x%x\n",
3365	READ_VREG(MBY_MBX));
3366	debug_print(hw, 0,
3367	"VIFF_BIT_CNT=0x%x\n",
3368	READ_VREG(VIFF_BIT_CNT));
3369	debug_print(hw, 0,
3370	"VLD_MEM_VIFIFO_LEVEL=0x%x\n",
3371	READ_VREG(VLD_MEM_VIFIFO_LEVEL));
3372	debug_print(hw, 0,
3373	"VLD_MEM_VIFIFO_WP=0x%x\n",
3374	READ_VREG(VLD_MEM_VIFIFO_WP));
3375	debug_print(hw, 0,
3376	"VLD_MEM_VIFIFO_RP=0x%x\n",
3377	READ_VREG(VLD_MEM_VIFIFO_RP));
3378	debug_print(hw, 0,
3379	"PARSER_VIDEO_RP=0x%x\n",
3380	READ_PARSER_REG(PARSER_VIDEO_RP));
3381	debug_print(hw, 0,
3382	"PARSER_VIDEO_WP=0x%x\n",
3383	READ_PARSER_REG(PARSER_VIDEO_WP));
3384
3385	if (vdec_frame_based(vdec) &&
3386	(debug & PRINT_FRAMEBASE_DATA)
3387	) {
3388	int jj;
3389	if (hw->chunk && hw->chunk->block &&
3390	hw->chunk->size > 0) {
3391	u8 *data = NULL;
3392
3393	if (!hw->chunk->block->is_mapped)
3394	data = codec_mm_vmap(hw->chunk->block->start +
3395	hw->chunk->offset, hw->chunk->size);
3396	else
3397	data = ((u8 *)hw->chunk->block->start_virt)
3398	+ hw->chunk->offset;
3399
3400	debug_print(hw, 0,
3401	"frame data size 0x%x\n",
3402	hw->chunk->size);
3403	for (jj = 0; jj < hw->chunk->size; jj++) {
3404	if ((jj & 0xf) == 0)
3405	debug_print(hw,
3406	PRINT_FRAMEBASE_DATA,
3407	"%06x:", jj);
3408	debug_print_cont(hw,
3409	PRINT_FRAMEBASE_DATA,
3410	"%02x ", data[jj]);
3411	if (((jj + 1) & 0xf) == 0)
3412	debug_print_cont(hw,
3413	PRINT_FRAMEBASE_DATA,
3414	"\n");
3415	}
3416
3417	if (!hw->chunk->block->is_mapped)
3418	codec_mm_unmap_phyaddr(data);
3419	}
3420	}
3421
3422	}
3423
3424	static int ammvdec_avs_probe(struct platform_device *pdev)
3425	{
3426	struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
3427	struct vdec_avs_hw_s *hw = NULL;
3428
3429	pr_info("ammvdec_avs probe start.\n");
3430
3431	if (pdata == NULL) {
3432	pr_info("ammvdec_avs platform data undefined.\n");
3433	return -EFAULT;
3434	}
3435	pr_info("%s %d\n", __func__, __LINE__);
3436
3437	hw = (struct vdec_avs_hw_s *)devm_kzalloc(&pdev->dev,
3438	sizeof(struct vdec_avs_hw_s), GFP_KERNEL);
3439	if (hw == NULL) {
3440	pr_info("\nammvdec_avs decoder driver alloc failed\n");
3441	return -ENOMEM;
3442	}
3443	pr_info("%s %d\n", __func__, __LINE__);
3444	/*atomic_set(&hw->error_handler_run, 0);*/
3445	hw->m_ins_flag = 1;
3446	pr_info("%s %d\n", __func__, __LINE__);
3447
3448	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXM || disable_longcabac_trans)
3449	firmware_sel = 1;
3450	pr_info("%s %d\n", __func__, __LINE__);
3451
3452	if (firmware_sel == 1) {
3453	vf_buf_num = 4;
3454	canvas_base = 0;
3455	canvas_num = 3;
3456	} else {
3457	pr_info("Error, do not support longcabac work around!!!");
3458	return -ENOMEM;
3459	}
3460	pr_info("%s %d\n", __func__, __LINE__);
3461
3462	if (pdata->sys_info)
3463	hw->vavs_amstream_dec_info = *pdata->sys_info;
3464	pr_info("%s %d\n", __func__, __LINE__);
3465
3466	hw->is_reset = 0;
3467	pdata->user_data_read = NULL;
3468	pdata->reset_userdata_fifo = NULL;
3469
3470	pr_info("%s %d\n", __func__, __LINE__);
3471
3472	pdata->private = hw;
3473	pdata->dec_status = vavs_dec_status;
3474	pdata->set_isreset = vavs_set_isreset;
3475	pdata->run_ready = run_ready;
3476	pdata->run = run;
3477	pdata->reset = reset;
3478	pdata->irq_handler = vmavs_isr;
3479	pdata->threaded_irq_handler = vmavs_isr_thread_fn;
3480	pdata->dump_state = vmavs_dump_state;
3481
3482	pr_info("%s %d\n", __func__, __LINE__);
3483
3484	vavs_vdec_info_init(hw);
3485
3486	pr_info("%s %d\n", __func__, __LINE__);
3487
3488	#ifdef ENABLE_USER_DATA
3489	if (NULL == hw->user_data_buffer) {
3490	hw->user_data_buffer =
3491	dma_alloc_coherent(amports_get_dma_device(),
3492	USER_DATA_SIZE,
3493	&hw->user_data_buffer_phys, GFP_KERNEL);
3494	if (!hw->user_data_buffer) {
3495	pr_info("%s: Can not allocate hw->user_data_buffer\n",
3496	__func__);
3497	return -ENOMEM;
3498	}
3499	pr_debug("hw->user_data_buffer = 0x%p, hw->user_data_buffer_phys = 0x%x\n",
3500	hw->user_data_buffer, (u32)hw->user_data_buffer_phys);
3501	}
3502	#endif
3503	hw->lmem_addr = kmalloc(LMEM_BUF_SIZE, GFP_KERNEL);
3504	if (hw->lmem_addr == NULL) {
3505	pr_err("%s: failed to alloc lmem buffer\n", __func__);
3506	return -1;
3507	}
3508	hw->lmem_phy_addr = dma_map_single(amports_get_dma_device(),
3509	hw->lmem_addr, LMEM_BUF_SIZE, DMA_FROM_DEVICE);
3510	if (dma_mapping_error(amports_get_dma_device(),
3511	hw->lmem_phy_addr)) {
3512	pr_err("%s: failed to map lmem buffer\n", __func__);
3513	kfree(hw->lmem_addr);
3514	hw->lmem_addr = NULL;
3515	return -1;
3516	}
3517
3518	pr_info("%s %d\n", __func__, __LINE__);
3519
3520	/*INIT_WORK(&hw->set_clk_work, avs_set_clk);*/
3521
3522	pr_info("%s %d\n", __func__, __LINE__);
3523
3524	if (vavs_init(hw) < 0) {
3525	pr_info("amvdec_avs init failed.\n");
3526	kfree(hw->gvs);
3527	hw->gvs = NULL;
3528	pdata->dec_status = NULL;
3529	return -ENODEV;
3530	}
3531
3532	/*INIT_WORK(&hw->fatal_error_wd_work, vavs_fatal_error_handler);
3533	atomic_set(&hw->error_handler_run, 0);*/
3534	#if 0
3535	#ifdef ENABLE_USER_DATA
3536	INIT_WORK(&hw->userdata_push_work, userdata_push_do_work);
3537	#endif
3538	#endif
3539	INIT_WORK(&hw->notify_work, vavs_notify_work);
3540
3541	if (pdata->use_vfm_path) {
3542	snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
3543	VFM_DEC_PROVIDER_NAME);
3544	hw->frameinfo_enable = 1;
3545	}
3546	else
3547	snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
3548	MULTI_INSTANCE_PROVIDER_NAME ".%02x", pdev->id & 0xff);
3549	if (pdata->parallel_dec == 1) {
3550	int i;
3551	for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++)
3552	hw->canvas_spec[i] = 0xffffff;
3553	}
3554	vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
3555	&vavs_vf_provider, hw);
3556
3557	platform_set_drvdata(pdev, pdata);
3558
3559	hw->platform_dev = pdev;
3560
3561	vdec_set_prepare_level(pdata, start_decode_buf_level);
3562
3563	if (pdata->parallel_dec == 1)
3564	vdec_core_request(pdata, CORE_MASK_VDEC_1);
3565	else {
3566	vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
3567	| CORE_MASK_COMBINE);
3568	}
3569
3570	/*INIT_WORK(&hw->userdata_push_work, userdata_push_do_work);*/
3571	return 0;
3572	}
3573
3574	static int ammvdec_avs_remove(struct platform_device *pdev)
3575	{
3576	struct vdec_avs_hw_s *hw =
3577	(struct vdec_avs_hw_s *)
3578	(((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
3579	struct vdec_s *vdec = hw_to_vdec(hw);
3580	int i;
3581
3582	if (hw->stat & STAT_VDEC_RUN) {
3583	amvdec_stop();
3584	hw->stat &= ~STAT_VDEC_RUN;
3585	}
3586
3587	if (hw->stat & STAT_ISR_REG) {
3588	vdec_free_irq(VDEC_IRQ_1, (void *)hw);
3589	hw->stat &= ~STAT_ISR_REG;
3590	}
3591
3592	if (hw->stat & STAT_TIMER_ARM) {
3593	del_timer_sync(&hw->check_timer);
3594	hw->stat &= ~STAT_TIMER_ARM;
3595	}
3596
3597	cancel_work_sync(&hw->work);
3598	cancel_work_sync(&hw->notify_work);
3599
3600	if (hw->mm_blk_handle) {
3601	decoder_bmmu_box_free(hw->mm_blk_handle);
3602	hw->mm_blk_handle = NULL;
3603	}
3604	if (vdec->parallel_dec == 1)
3605	vdec_core_release(hw_to_vdec(hw), CORE_MASK_VDEC_1);
3606	else
3607	vdec_core_release(hw_to_vdec(hw), CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
3608	vdec_set_status(hw_to_vdec(hw), VDEC_STATUS_DISCONNECTED);
3609
3610	if (vdec->parallel_dec == 1) {
3611	for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) {
3612	vdec->free_canvas_ex(canvas_y(hw->canvas_spec[i]), vdec->id);
3613	vdec->free_canvas_ex(canvas_u(hw->canvas_spec[i]), vdec->id);
3614	}
3615	}
3616	#ifdef ENABLE_USER_DATA
3617	if (hw->user_data_buffer != NULL) {
3618	dma_free_coherent(
3619	amports_get_dma_device(),
3620	USER_DATA_SIZE,
3621	hw->user_data_buffer,
3622	hw->user_data_buffer_phys);
3623	hw->user_data_buffer = NULL;
3624	hw->user_data_buffer_phys = 0;
3625	}
3626	#endif
3627	if (hw->lmem_addr) {
3628	dma_unmap_single(amports_get_dma_device(),
3629	hw->lmem_phy_addr, LMEM_BUF_SIZE, DMA_FROM_DEVICE);
3630	kfree(hw->lmem_addr);
3631	hw->lmem_addr = NULL;
3632	}
3633
3634	if (hw->fw) {
3635	vfree(hw->fw);
3636	hw->fw = NULL;
3637	}
3638
3639	pr_info("ammvdec_avs removed.\n");
3640	if (hw->gvs) {
3641	kfree(hw->gvs);
3642	hw->gvs = NULL;
3643	}
3644
3645	return 0;
3646	}
3647
3648
3649	static struct platform_driver ammvdec_avs_driver = {
3650	.probe = ammvdec_avs_probe,
3651	.remove = ammvdec_avs_remove,
3652	#ifdef CONFIG_PM
3653	.suspend = amvdec_suspend,
3654	.resume = amvdec_resume,
3655	#endif
3656	.driver = {
3657	.name = MULTI_DRIVER_NAME,
3658	}
3659	};
3660
3661	static struct codec_profile_t ammvdec_avs_profile = {
3662	.name = "mavs",
3663	.profile = ""
3664	};
3665
3666	static struct mconfig mavs_configs[] = {
3667	/*MC_PU32("stat", &stat),
3668	MC_PU32("debug_flag", &debug_flag),
3669	MC_PU32("error_recovery_mode", &error_recovery_mode),
3670	MC_PU32("hw->pic_type", &hw->pic_type),
3671	MC_PU32("radr", &radr),
3672	MC_PU32("vf_buf_num", &vf_buf_num),
3673	MC_PU32("vf_buf_num_used", &vf_buf_num_used),
3674	MC_PU32("canvas_base", &canvas_base),
3675	MC_PU32("firmware_sel", &firmware_sel),
3676	*/
3677	};
3678	static struct mconfig_node mavs_node;
3679
3680
3681	static int __init ammvdec_avs_driver_init_module(void)
3682	{
3683	pr_debug("ammvdec_avs module init\n");
3684
3685	if (platform_driver_register(&ammvdec_avs_driver))
3686	pr_err("failed to register ammvdec_avs driver\n");
3687
3688	/*if (platform_driver_register(&amvdec_avs_driver)) {
3689	pr_info("failed to register amvdec_avs driver\n");
3690	return -ENODEV;
3691	}*/
3692	amvdec_avs_driver = amvdec_avs_driver;
3693	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXBB)
3694	ammvdec_avs_profile.profile = "avs+";
3695
3696	//vcodec_profile_register(&ammvdec_avs_profile);
3697	INIT_REG_NODE_CONFIGS("media.decoder", &mavs_node,
3698	"mavs", mavs_configs, CONFIG_FOR_RW);
3699	return 0;
3700	}
3701
3702
3703
3704	static void __exit ammvdec_avs_driver_remove_module(void)
3705	{
3706	pr_debug("ammvdec_avs module remove.\n");
3707
3708	platform_driver_unregister(&ammvdec_avs_driver);
3709
3710	/*platform_driver_unregister(&amvdec_avs_driver);*/
3711	}
3712
3713	/****************************************/
3714	/*
3715	module_param(stat, uint, 0664);
3716	MODULE_PARM_DESC(stat, "\n amvdec_avs stat\n");
3717	*/
3718	/******************************************
3719	*module_param(run_flag, uint, 0664);
3720	*MODULE_PARM_DESC(run_flag, "\n run_flag\n");
3721	*
3722	*module_param(step_flag, uint, 0664);
3723	*MODULE_PARM_DESC(step_flag, "\n step_flag\n");
3724	*******************************************
3725	*/
3726	module_param(step, uint, 0664);
3727	MODULE_PARM_DESC(step, "\n step\n");
3728
3729	module_param(debug_flag, uint, 0664);
3730	MODULE_PARM_DESC(debug_flag, "\n debug_flag\n");
3731
3732	module_param(debug_mask, uint, 0664);
3733	MODULE_PARM_DESC(debug_mask, "\n debug_mask\n");
3734
3735	module_param(error_recovery_mode, uint, 0664);
3736	MODULE_PARM_DESC(error_recovery_mode, "\n error_recovery_mode\n");
3737
3738	/******************************************
3739	*module_param(error_watchdog_threshold, uint, 0664);
3740	*MODULE_PARM_DESC(error_watchdog_threshold, "\n error_watchdog_threshold\n");
3741	*
3742	*module_param(error_watchdog_buf_threshold, uint, 0664);
3743	*MODULE_PARM_DESC(error_watchdog_buf_threshold,
3744	* "\n error_watchdog_buf_threshold\n");
3745	*******************************************
3746	*/
3747	/*
3748	module_param(pic_type, uint, 0444);
3749	MODULE_PARM_DESC(pic_type, "\n amdec_vas picture type\n");
3750	*/
3751	module_param(radr, uint, 0664);
3752	MODULE_PARM_DESC(radr, "\nradr\n");
3753
3754	module_param(rval, uint, 0664);
3755	MODULE_PARM_DESC(rval, "\nrval\n");
3756
3757	module_param(dbg_cmd, uint, 0664);
3758	MODULE_PARM_DESC(dbg_cmd, "\n dbg_cmd\n");
3759
3760	module_param(vf_buf_num, uint, 0664);
3761	MODULE_PARM_DESC(vf_buf_num, "\nvf_buf_num\n");
3762
3763	/*
3764	module_param(vf_buf_num_used, uint, 0664);
3765	MODULE_PARM_DESC(vf_buf_num_used, "\nvf_buf_num_used\n");
3766	*/
3767	module_param(canvas_base, uint, 0664);
3768	MODULE_PARM_DESC(canvas_base, "\ncanvas_base\n");
3769
3770
3771	module_param(firmware_sel, uint, 0664);
3772	MODULE_PARM_DESC(firmware_sel, "\n firmware_sel\n");
3773
3774	module_param(disable_longcabac_trans, uint, 0664);
3775	MODULE_PARM_DESC(disable_longcabac_trans, "\n disable_longcabac_trans\n");
3776
3777	module_param(dec_control, uint, 0664);
3778	MODULE_PARM_DESC(dec_control, "\n amvdec_vavs decoder control\n");
3779
3780	module_param(start_decode_buf_level, int, 0664);
3781	MODULE_PARM_DESC(start_decode_buf_level,
3782	"\n avs start_decode_buf_level\n");
3783
3784	module_param(decode_timeout_val, uint, 0664);
3785	MODULE_PARM_DESC(decode_timeout_val,
3786	"\n avs decode_timeout_val\n");
3787
3788	module_param(udebug_flag, uint, 0664);
3789	MODULE_PARM_DESC(udebug_flag, "\n amvdec_h265 udebug_flag\n");
3790
3791	module_param(udebug_pause_pos, uint, 0664);
3792	MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n");
3793
3794	module_param(udebug_pause_val, uint, 0664);
3795	MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n");
3796
3797	module_param(udebug_pause_decode_idx, uint, 0664);
3798	MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n");
3799
3800	module_param(force_fps, uint, 0664);
3801	MODULE_PARM_DESC(force_fps, "\n force_fps\n");
3802
3803	module_param_array(max_process_time, uint, &max_decode_instance_num, 0664);
3804
3805	module_param_array(max_get_frame_interval, uint,
3806	&max_decode_instance_num, 0664);
3807
3808
3809	module_init(ammvdec_avs_driver_init_module);
3810	module_exit(ammvdec_avs_driver_remove_module);
3811
3812	MODULE_DESCRIPTION("AMLOGIC AVS Video Decoder Driver");
3813	MODULE_LICENSE("GPL");
3814	MODULE_AUTHOR("Qi Wang <qi.wang@amlogic.com>");
3815