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path: root/drivers/frame_provider/decoder/h264_multi/vmh264.c (plain)
blob: 91d8c1fda5d87fb5898c3c85e9f41a4febe3cc4d
1/*
2 * drivers/amlogic/amports/vh264.c
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17#define DEBUG
18#include <linux/kernel.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/interrupt.h>
22#include <linux/timer.h>
23#include <linux/kfifo.h>
24#include <linux/platform_device.h>
25#include <linux/random.h>
26
27#include <linux/amlogic/media/utils/amstream.h>
28#include <linux/amlogic/media/frame_sync/ptsserv.h>
29#include <linux/amlogic/media/canvas/canvas.h>
30#include <linux/amlogic/media/vfm/vframe.h>
31#include <linux/amlogic/media/vfm/vframe_provider.h>
32#include <linux/amlogic/media/vfm/vframe_receiver.h>
33#include <linux/amlogic/media/utils/vformat.h>
34#include <linux/amlogic/media/frame_sync/tsync.h>
35#include <linux/workqueue.h>
36#include <linux/dma-mapping.h>
37#include <linux/atomic.h>
38#include <linux/module.h>
39#include <linux/slab.h>
40#include <linux/dma-mapping.h>
41#include <linux/dma-contiguous.h>
42#include "../../../stream_input/amports/amports_priv.h"
43#include <linux/amlogic/media/codec_mm/codec_mm.h>
44
45#include "../utils/vdec_input.h"
46#include <linux/amlogic/tee.h>
47
48#include <linux/amlogic/media/utils/vdec_reg.h>
49#include "../utils/vdec.h"
50#include "../utils/amvdec.h"
51#include "../h264/vh264.h"
52#include "../../../stream_input/parser/streambuf.h"
53#include <linux/delay.h>
54#include <linux/amlogic/media/codec_mm/configs.h>
55#include "../utils/decoder_mmu_box.h"
56#include "../utils/decoder_bmmu_box.h"
57#include "../utils/firmware.h"
58#include <linux/amlogic/tee.h>
59#include <linux/uaccess.h>
60#include "../utils/config_parser.h"
61#include "../../../common/chips/decoder_cpu_ver_info.h"
62#include "../utils/vdec_v4l2_buffer_ops.h"
63#include <linux/crc32.h>
64#include <media/v4l2-mem2mem.h>
65
66#define DETECT_WRONG_MULTI_SLICE
67
68
69#undef pr_info
70#define pr_info printk
71#define VDEC_DW
72#define DEBUG_UCODE
73#define MEM_NAME "codec_m264"
74#define MULTI_INSTANCE_FRAMEWORK
75/* #define ONE_COLOCATE_BUF_PER_DECODE_BUF */
76#include "h264_dpb.h"
77/* #define SEND_PARAM_WITH_REG */
78
79#define DRIVER_NAME "ammvdec_h264"
80#define MODULE_NAME "ammvdec_h264"
81#define DRIVER_HEADER_NAME "ammvdec_h264_header"
82
83#define CHECK_INTERVAL (HZ/100)
84
85#define SEI_DATA_SIZE (8*1024)
86#define SEI_ITU_DATA_SIZE (4*1024)
87
88#define RATE_MEASURE_NUM 8
89#define RATE_CORRECTION_THRESHOLD 5
90#define RATE_2397_FPS 4004 /* 23.97 */
91#define RATE_25_FPS 3840 /* 25 */
92#define RATE_2997_FPS 3203 /* 29.97 */
93#define DUR2PTS(x) ((x)*90/96)
94#define PTS2DUR(x) ((x)*96/90)
95#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96)
96#define FIX_FRAME_RATE_CHECK_IFRAME_NUM 2
97
98#define FIX_FRAME_RATE_OFF 0
99#define FIX_FRAME_RATE_ON 1
100#define FIX_FRAME_RATE_SMOOTH_CHECKING 2
101
102#define DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE 0x0001
103#define DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE 0x0002
104#define DEC_CONTROL_FLAG_FORCE_RATE_2397_FPS_FIX_FRAME_RATE 0x0010
105#define DEC_CONTROL_FLAG_FORCE_RATE_2997_FPS_FIX_FRAME_RATE 0x0020
106
107#define DECODE_ID(hw) (hw_to_vdec(hw)->id)
108
109#define RATE_MEASURE_NUM 8
110#define RATE_CORRECTION_THRESHOLD 5
111#define RATE_24_FPS 4004 /* 23.97 */
112#define RATE_25_FPS 3840 /* 25 */
113#define DUR2PTS(x) ((x)*90/96)
114#define PTS2DUR(x) ((x)*96/90)
115#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96)
116#define FIX_FRAME_RATE_CHECK_IDRFRAME_NUM 2
117
118#define H264_DEV_NUM 9
119
120#define CONSTRAIN_MAX_BUF_NUM
121
122#define H264_MMU
123#define VIDEO_SIGNAL_TYPE_AVAILABLE_MASK 0x20000000
124#define INVALID_IDX -1 /* Invalid buffer index.*/
125
126static int mmu_enable;
127/*mmu do not support mbaff*/
128static int force_enable_mmu = 0;
129unsigned int h264_debug_flag; /* 0xa0000000; */
130unsigned int h264_debug_mask = 0xff;
131 /*
132 *h264_debug_cmd:
133 * 0x1xx, force decoder id of xx to be disconnected
134 */
135unsigned int h264_debug_cmd;
136
137static int ref_b_frame_error_max_count = 50;
138
139static unsigned int dec_control =
140 DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE |
141 DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE;
142
143static unsigned int force_rate_streambase;
144static unsigned int force_rate_framebase;
145static unsigned int force_disp_bufspec_num;
146static unsigned int fixed_frame_rate_mode;
147static unsigned int error_recovery_mode_in;
148static int start_decode_buf_level = 0x4000;
149static int pre_decode_buf_level = 0x1000;
150static int stream_mode_start_num = 4;
151
152#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
153/*to make reorder size difference of bl and el not too big*/
154static unsigned int reorder_dpb_size_margin_dv = 16;
155#endif
156static unsigned int reorder_dpb_size_margin = 6;
157static unsigned int reference_buf_margin = 4;
158
159#ifdef CONSTRAIN_MAX_BUF_NUM
160static u32 run_ready_max_vf_only_num;
161static u32 run_ready_display_q_num;
162 /*0: not check
163 0xff: mDPB.size
164 */
165static u32 run_ready_max_buf_num = 0xff;
166#endif
167
168static u32 run_ready_min_buf_num = 2;
169
170#define VDEC_ASSIST_CANVAS_BLK32 0x5
171
172
173static unsigned int max_alloc_buf_count;
174static unsigned int decode_timeout_val = 100;
175static unsigned int errordata_timeout_val = 50;
176static unsigned int get_data_timeout_val = 2000;
177#if 1
178/* H264_DATA_REQUEST does not work, disable it,
179decode has error for data in none continuous address
180*/
181static unsigned int frame_max_data_packet;
182#else
183static unsigned int frame_max_data_packet = 8;
184#endif
185static unsigned int radr;
186static unsigned int rval;
187static u32 endian = 0xff0;
188
189/*
190 udebug_flag:
191 bit 0, enable ucode print
192 bit 1, enable ucode detail print
193 bit 3, disable ucode watchdog
194 bit [31:16] not 0, pos to dump lmem
195 bit 2, pop bits to lmem
196 bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
197*/
198static u32 udebug_flag;
199/*
200 when udebug_flag[1:0] is not 0
201 udebug_pause_pos not 0,
202 pause position
203*/
204static u32 udebug_pause_pos;
205/*
206 when udebug_flag[1:0] is not 0
207 and udebug_pause_pos is not 0,
208 pause only when DEBUG_REG2 is equal to this val
209*/
210static u32 udebug_pause_val;
211
212static u32 udebug_pause_decode_idx;
213
214static unsigned int disp_vframe_valve_level;
215
216static unsigned int max_decode_instance_num = H264_DEV_NUM;
217static unsigned int decode_frame_count[H264_DEV_NUM];
218static unsigned int display_frame_count[H264_DEV_NUM];
219static unsigned int max_process_time[H264_DEV_NUM];
220static unsigned int max_get_frame_interval[H264_DEV_NUM];
221static unsigned int run_count[H264_DEV_NUM];
222static unsigned int input_empty[H264_DEV_NUM];
223static unsigned int not_run_ready[H264_DEV_NUM];
224static unsigned int ref_frame_mark_flag[H264_DEV_NUM] =
225{1, 1, 1, 1, 1, 1, 1, 1, 1};
226
227#define VDEC_CLOCK_ADJUST_FRAME 30
228static unsigned int clk_adj_frame_count;
229
230/*
231 *bit[3:0]: 0, run ; 1, pause; 3, step
232 *bit[4]: 1, schedule run
233 */
234static unsigned int step[H264_DEV_NUM];
235
236#define AUX_BUF_ALIGN(adr) ((adr + 0xf) & (~0xf))
237static u32 prefix_aux_buf_size = (16 * 1024);
238static u32 suffix_aux_buf_size;
239
240#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
241static u32 dv_toggle_prov_name;
242
243static u32 dolby_meta_with_el;
244#endif
245
246/*
247 bit[8]
248 0: use sys_info[bit 3]
249 not 0:use i_only_flag[7:0]
250 bit[7:0]:
251 bit 0, 1: only display I picture;
252 bit 1, 1: only decode I picture;
253*/
254static unsigned int i_only_flag;
255
256/*
257 error_proc_policy:
258 bit[0] send_error_frame_flag;
259 (valid when bit[31] is 1, otherwise use sysinfo)
260 bit[1] do not decode if config_decode_buf() fail
261 bit[2] force release buf if in deadlock
262 bit[3] force sliding window ref_frames_in_buffer > num_ref_frames
263 bit[4] check inactive of receiver
264 bit[5] reset buffmgr if in deadlock
265 bit[6] reset buffmgr if bufspec, collocate buf, pic alloc fail
266 bit[7] reset buffmgr if dpb error
267
268 bit[8] check total mbx/mby of decoded frame
269 bit[9] check ERROR_STATUS_REG
270 bit[10] check reference list
271 bit[11] mark error if dpb error
272 bit[12] i_only when error happen
273 bit[13] 0: mark error according to last pic, 1: ignore mark error
274 bit[14] 0: result done when timeout from ucode. 1: reset bufmgr when timeout.
275 bit[15] 1: dpb_frame_count If the dpb_frame_count difference is large, it moves out of the DPB buffer.
276 bit[16] 1: check slice header number.
277 bit[17] 1: If the decoded Mb count is insufficient but greater than the threshold, it is considered the correct frame.
278 bit[18] 1: time out status, store pic to dpb buffer.
279 bit[19] 1: If a lot b frames are wrong consecutively, the DPB queue reset.
280*/
281static unsigned int error_proc_policy = 0xfCfb6; /*0x1f14*/
282
283
284/*
285 error_skip_count:
286 bit[11:0] error skip frame count
287 bit[15:12] error skip i picture count
288*/
289static unsigned int error_skip_count = (0x2 << 12) | 0x40;
290
291static unsigned int force_sliding_margin;
292/*
293 bit[1:0]:
294 0, start playing from any frame
295 1, start playing from I frame
296 bit[15:8]: the count of skip frames after first I
297 2, start playing from second I frame (decode from the first I)
298 bit[15:8]: the max count of skip frames after first I
299 3, start playing from IDR
300*/
301static unsigned int first_i_policy = 1;
302
303/*
304 fast_output_enable:
305 bit [0], output frame if there is IDR in list
306 bit [1], output frame if the current poc is 1 big than the previous poc
307 bit [2], if even poc only, output frame ifthe cuurent poc
308 is 2 big than the previous poc
309 bit [3], ip only
310*/
311static unsigned int fast_output_enable = H264_OUTPUT_MODE_NORMAL;
312
313static unsigned int enable_itu_t35 = 1;
314
315static unsigned int frmbase_cont_bitlevel = 0x40;
316
317static unsigned int frmbase_cont_bitlevel2 = 0x1;
318
319static unsigned int check_slice_num = 30;
320
321static unsigned int mb_count_threshold = 5; /*percentage*/
322
323#define MH264_USERDATA_ENABLE
324
325/* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */
326/* hevc->double_write_mode:
327 0, no double write
328 1, 1:1 ratio
329 2, (1/4):(1/4) ratio
330 3, (1/4):(1/4) ratio, with both compressed frame included
331 4, (1/2):(1/2) ratio
332 0x10, double write only
333 0x10000: vdec dw horizotal 1/2
334 0x20000: vdec dw horizotal/vertical 1/2
335*/
336static u32 double_write_mode;
337static u32 without_display_mode;
338#define IS_VDEC_DW(hw) (hw->double_write_mode >> 16 & 0xf)
339
340static void vmh264_dump_state(struct vdec_s *vdec);
341
342#define is_in_parsing_state(status) \
343 ((status == H264_ACTION_SEARCH_HEAD) || \
344 ((status & 0xf0) == 0x80))
345
346#define is_interlace(frame) \
347 (frame->frame &&\
348 frame->top_field &&\
349 frame->bottom_field &&\
350 (!frame->frame->coded_frame))
351static inline bool close_to(int a, int b, int m)
352{
353 return (abs(a - b) < m) ? true : false;
354}
355
356#if 0
357#define h264_alloc_hw_stru(dev, size, opt) devm_kzalloc(dev, size, opt)
358#define h264_free_hw_stru(dev, hw) devm_kfree(dev, hw)
359#else
360#define h264_alloc_hw_stru(dev, size, opt) vzalloc(size)
361#define h264_free_hw_stru(dev, hw) vfree(hw)
362#endif
363
364/* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
365#define NV21
366/* #endif */
367
368/* 12M for L41 */
369#define MAX_DPB_BUFF_SIZE (12*1024*1024)
370#define DEFAULT_MEM_SIZE (32*1024*1024)
371#define AVIL_DPB_BUFF_SIZE 0x01ec2000
372
373#define DEF_BUF_START_ADDR 0x01000000
374#define mem_sps_base 0x011c3c00
375#define mem_pps_base 0x011cbc00
376/*#define V_BUF_ADDR_OFFSET (0x13e000)*/
377u32 V_BUF_ADDR_OFFSET = 0x200000;
378#define DCAC_READ_MARGIN (64 * 1024)
379
380
381#define EXTEND_SAR 0xff
382#define BUFSPEC_POOL_SIZE 64
383#define VF_POOL_SIZE 64
384#define VF_POOL_NUM 2
385#define MAX_VF_BUF_NUM 27
386#define BMMU_MAX_BUFFERS (BUFSPEC_POOL_SIZE + 3)
387#define BMMU_REF_IDX (BUFSPEC_POOL_SIZE)
388#define BMMU_DPB_IDX (BUFSPEC_POOL_SIZE + 1)
389#define BMMU_EXTIF_IDX (BUFSPEC_POOL_SIZE + 2)
390#define EXTIF_BUF_SIZE (0x10000 * 2)
391
392#define HEADER_BUFFER_IDX(n) (n)
393#define VF_BUFFER_IDX(n) (n)
394
395
396#define PUT_INTERVAL (HZ/100)
397#define NO_DISP_WD_COUNT (3 * HZ / PUT_INTERVAL)
398
399#define MMU_MAX_BUFFERS BUFSPEC_POOL_SIZE
400#define SWITCHING_STATE_OFF 0
401#define SWITCHING_STATE_ON_CMD3 1
402#define SWITCHING_STATE_ON_CMD1 2
403
404
405
406#define INCPTR(p) ptr_atomic_wrap_inc(&p)
407
408#define SLICE_TYPE_I 2
409#define SLICE_TYPE_P 5
410#define SLICE_TYPE_B 6
411
412struct buffer_spec_s {
413 /*
414 used:
415 -1, none allocated
416 0, allocated, free
417 1, used by dpb
418 2, in disp queue;
419 3, in disp queue, isolated,
420 do not use for dpb when vf_put;
421 4, to release
422 5, in disp queue, isolated (but not to release)
423 do not use for dpb when vf_put;
424 */
425 unsigned int used;
426 unsigned int info0;
427 unsigned int info1;
428 unsigned int info2;
429 unsigned int y_addr;
430 unsigned int u_addr;
431 unsigned int v_addr;
432
433 int y_canvas_index;
434 int u_canvas_index;
435 int v_canvas_index;
436
437#ifdef VDEC_DW
438 unsigned int vdec_dw_y_addr;
439 unsigned int vdec_dw_u_addr;
440 unsigned int vdec_dw_v_addr;
441
442 int vdec_dw_y_canvas_index;
443 int vdec_dw_u_canvas_index;
444 int vdec_dw_v_canvas_index;
445#ifdef NV21
446 struct canvas_config_s vdec_dw_canvas_config[2];
447#else
448 struct canvas_config_s vdec_dw_canvas_config[3];
449#endif
450#endif
451
452#ifdef NV21
453 struct canvas_config_s canvas_config[2];
454#else
455 struct canvas_config_s canvas_config[3];
456#endif
457 unsigned long cma_alloc_addr;
458 unsigned int buf_adr;
459#ifdef H264_MMU
460 unsigned long alloc_header_addr;
461#endif
462 char *aux_data_buf;
463 int aux_data_size;
464#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
465 unsigned char dv_enhance_exist;
466#endif
467 int canvas_pos;
468 int vf_ref;
469 /*unsigned int comp_body_size;*/
470 unsigned int dw_y_adr;
471 unsigned int dw_u_v_adr;
472};
473
474#define AUX_DATA_SIZE(pic) (hw->buffer_spec[pic->buf_spec_num].aux_data_size)
475#define AUX_DATA_BUF(pic) (hw->buffer_spec[pic->buf_spec_num].aux_data_buf)
476#define DEL_EXIST(h, p) (h->buffer_spec[p->buf_spec_num].dv_enhance_exist)
477
478
479#define vdec_dw_spec2canvas(x) \
480 (((x)->vdec_dw_v_canvas_index << 16) | \
481 ((x)->vdec_dw_u_canvas_index << 8) | \
482 ((x)->vdec_dw_y_canvas_index << 0))
483
484
485#define spec2canvas(x) \
486 (((x)->v_canvas_index << 16) | \
487 ((x)->u_canvas_index << 8) | \
488 ((x)->y_canvas_index << 0))
489
490#define FRAME_INDEX(vf_index) (vf_index & 0xff)
491#define BUFSPEC_INDEX(vf_index) ((vf_index >> 8) & 0xff)
492#define VF_INDEX(frm_idx, bufspec_idx) (frm_idx | (bufspec_idx << 8))
493
494static struct vframe_s *vh264_vf_peek(void *);
495static struct vframe_s *vh264_vf_get(void *);
496static void vh264_vf_put(struct vframe_s *, void *);
497static int vh264_vf_states(struct vframe_states *states, void *);
498static int vh264_event_cb(int type, void *data, void *private_data);
499static void vh264_work(struct work_struct *work);
500static void vh264_timeout_work(struct work_struct *work);
501static void vh264_notify_work(struct work_struct *work);
502#ifdef MH264_USERDATA_ENABLE
503static void user_data_ready_notify_work(struct work_struct *work);
504static void vmh264_wakeup_userdata_poll(struct vdec_s *vdec);
505#endif
506
507static const char vh264_dec_id[] = "vh264-dev";
508
509#define PROVIDER_NAME "vdec.h264"
510
511static const struct vframe_operations_s vf_provider_ops = {
512 .peek = vh264_vf_peek,
513 .get = vh264_vf_get,
514 .put = vh264_vf_put,
515 .event_cb = vh264_event_cb,
516 .vf_states = vh264_vf_states,
517};
518
519#define DEC_RESULT_NONE 0
520#define DEC_RESULT_DONE 1
521#define DEC_RESULT_AGAIN 2
522#define DEC_RESULT_CONFIG_PARAM 3
523#define DEC_RESULT_GET_DATA 4
524#define DEC_RESULT_GET_DATA_RETRY 5
525#define DEC_RESULT_ERROR 6
526#define DEC_RESULT_EOS 7
527#define DEC_RESULT_FORCE_EXIT 8
528
529/*
530 *static const char *dec_result_str[] = {
531 * "DEC_RESULT_NONE ",
532 * "DEC_RESULT_DONE ",
533 * "DEC_RESULT_AGAIN ",
534 * "DEC_RESULT_CONFIG_PARAM",
535 * "DEC_RESULT_GET_DATA ",
536 * "DEC_RESULT_GET_DA_RETRY",
537 * "DEC_RESULT_ERROR ",
538 *};
539 */
540
541#define UCODE_IP_ONLY 2
542#define UCODE_IP_ONLY_PARAM 1
543
544#define MC_OFFSET_HEADER 0x0000
545#define MC_OFFSET_DATA 0x1000
546#define MC_OFFSET_MMCO 0x2000
547#define MC_OFFSET_LIST 0x3000
548#define MC_OFFSET_SLICE 0x4000
549#define MC_OFFSET_MAIN 0x5000
550
551#define MC_TOTAL_SIZE ((20+16)*SZ_1K)
552#define MC_SWAP_SIZE (4*SZ_1K)
553#define MODE_ERROR 0
554#define MODE_FULL 1
555
556#define DFS_HIGH_THEASHOLD 3
557
558#define INIT_FLAG_REG AV_SCRATCH_2
559#define HEAD_PADING_REG AV_SCRATCH_3
560#define UCODE_WATCHDOG_REG AV_SCRATCH_7
561#define LMEM_DUMP_ADR AV_SCRATCH_L
562#define DEBUG_REG1 AV_SCRATCH_M
563#define DEBUG_REG2 AV_SCRATCH_N
564#define FRAME_COUNTER_REG AV_SCRATCH_I
565#define RPM_CMD_REG AV_SCRATCH_A
566#define H264_DECODE_SIZE AV_SCRATCH_E
567#define H264_DECODE_MODE AV_SCRATCH_4
568#define H264_DECODE_SEQINFO AV_SCRATCH_5
569#define H264_AUX_ADR AV_SCRATCH_C
570#define H264_AUX_DATA_SIZE AV_SCRATCH_H
571
572#define H264_DECODE_INFO M4_CONTROL_REG /* 0xc29 */
573#define DPB_STATUS_REG AV_SCRATCH_J
574#define ERROR_STATUS_REG AV_SCRATCH_9
575 /*
576 NAL_SEARCH_CTL: bit 0, enable itu_t35
577 NAL_SEARCH_CTL: bit 1, enable mmu
578 */
579#define NAL_SEARCH_CTL AV_SCRATCH_9
580#define MBY_MBX MB_MOTION_MODE /*0xc07*/
581
582#define DECODE_MODE_SINGLE 0x0
583#define DECODE_MODE_MULTI_FRAMEBASE 0x1
584#define DECODE_MODE_MULTI_STREAMBASE 0x2
585#define DECODE_MODE_MULTI_DVBAL 0x3
586#define DECODE_MODE_MULTI_DVENL 0x4
587static DEFINE_MUTEX(vmh264_mutex);
588
589
590
591#ifdef MH264_USERDATA_ENABLE
592
593struct mh264_userdata_record_t {
594 struct userdata_meta_info_t meta_info;
595 u32 rec_start;
596 u32 rec_len;
597};
598
599struct mh264_ud_record_wait_node_t {
600 struct list_head list;
601 struct mh264_userdata_record_t ud_record;
602};
603#define USERDATA_FIFO_NUM 256
604#define MAX_FREE_USERDATA_NODES 5
605
606struct mh264_userdata_info_t {
607 struct mh264_userdata_record_t records[USERDATA_FIFO_NUM];
608 u8 *data_buf;
609 u8 *data_buf_end;
610 u32 buf_len;
611 u32 read_index;
612 u32 write_index;
613 u32 last_wp;
614};
615
616
617#endif
618
619struct vdec_h264_hw_s {
620 spinlock_t lock;
621 spinlock_t bufspec_lock;
622 int id;
623 struct platform_device *platform_dev;
624 unsigned long cma_alloc_addr;
625 /* struct page *collocate_cma_alloc_pages; */
626 unsigned long collocate_cma_alloc_addr;
627
628 u32 prefix_aux_size;
629 u32 suffix_aux_size;
630 void *aux_addr;
631 dma_addr_t aux_phy_addr;
632
633 /* buffer for store all sei data */
634 void *sei_data_buf;
635 u32 sei_data_len;
636
637 /* buffer for storing one itu35 recored */
638 void *sei_itu_data_buf;
639 u32 sei_itu_data_len;
640
641 /* recycle buffer for user data storing all itu35 records */
642 void *sei_user_data_buffer;
643 u32 sei_user_data_wp;
644#ifdef MH264_USERDATA_ENABLE
645 struct work_struct user_data_ready_work;
646#endif
647 struct StorablePicture *last_dec_picture;
648
649 ulong lmem_phy_addr;
650 dma_addr_t lmem_addr;
651
652 void *bmmu_box;
653#ifdef H264_MMU
654 void *mmu_box;
655 void *frame_mmu_map_addr;
656 dma_addr_t frame_mmu_map_phy_addr;
657 u32 hevc_cur_buf_idx;
658 u32 losless_comp_body_size;
659 u32 losless_comp_body_size_sao;
660 u32 losless_comp_header_size;
661 u32 mc_buffer_size_u_v;
662 u32 mc_buffer_size_u_v_h;
663 u32 is_idr_frame;
664 u32 is_new_pic;
665 u32 frame_done;
666 u32 frame_busy;
667 unsigned long extif_addr;
668 int double_write_mode;
669 int mmu_enable;
670#endif
671
672 DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
673 DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
674
675 int cur_pool;
676 struct vframe_s vfpool[VF_POOL_NUM][VF_POOL_SIZE];
677 struct buffer_spec_s buffer_spec[BUFSPEC_POOL_SIZE];
678 struct vframe_s switching_fense_vf;
679 struct h264_dpb_stru dpb;
680 u8 init_flag;
681 u8 first_sc_checked;
682 u8 has_i_frame;
683 u8 config_bufmgr_done;
684 u32 max_reference_size;
685 u32 decode_pic_count;
686 u32 reflist_error_count;
687 int start_search_pos;
688 u32 reg_iqidct_control;
689 u32 reg_vcop_ctrl_reg;
690 u32 reg_rv_ai_mb_count;
691 u32 vld_dec_control;
692 struct vframe_s vframe_dummy;
693
694 unsigned char buffer_empty_flag;
695
696 u32 frame_width;
697 u32 frame_height;
698 u32 frame_dur;
699 u32 frame_prog;
700 u32 frame_packing_type;
701
702 struct vframe_chunk_s *chunk;
703
704 u32 stat;
705 unsigned long buf_start;
706 u32 buf_offset;
707 u32 buf_size;
708 /* u32 ucode_map_start; */
709 u32 pts_outside;
710 u32 sync_outside;
711 u32 vh264_ratio;
712 u32 vh264_rotation;
713 u32 use_idr_framerate;
714
715 u32 seq_info;
716 u32 seq_info2;
717 u32 video_signal_from_vui; /*to do .. */
718 u32 timing_info_present_flag;
719 u32 fixed_frame_rate_flag;
720 u32 bitstream_restriction_flag;
721 u32 num_reorder_frames;
722 u32 max_dec_frame_buffering;
723 u32 iframe_count;
724 u32 aspect_ratio_info;
725 u32 num_units_in_tick;
726 u32 time_scale;
727 u32 h264_ar;
728 bool h264_first_valid_pts_ready;
729 u32 h264pts1;
730 u32 h264pts2;
731 u32 pts_duration;
732 u32 h264_pts_count;
733 u32 duration_from_pts_done;
734 u32 pts_unstable;
735 u32 unstable_pts;
736 u32 last_checkout_pts;
737 u32 max_refer_buf;
738
739 s32 vh264_stream_switching_state;
740 struct vframe_s *p_last_vf;
741 u32 last_pts;
742 u32 last_pts_remainder;
743 u32 last_duration;
744 u32 last_mb_width, last_mb_height;
745 bool check_pts_discontinue;
746 bool pts_discontinue;
747 u32 wait_buffer_counter;
748 u32 first_offset;
749 u32 first_pts;
750 u64 first_pts64;
751 bool first_pts_cached;
752 u64 last_pts64;
753#if 0
754 void *sei_data_buffer;
755 dma_addr_t sei_data_buffer_phys;
756#endif
757
758 uint error_recovery_mode;
759 uint mb_total;
760 uint mb_width;
761 uint mb_height;
762
763 uint i_only;
764 int skip_frame_count;
765 bool no_poc_reorder_flag;
766 bool send_error_frame_flag;
767 dma_addr_t mc_dma_handle;
768 void *mc_cpu_addr;
769 int vh264_reset;
770
771 atomic_t vh264_active;
772
773 struct dec_sysinfo vh264_amstream_dec_info;
774
775 int dec_result;
776 struct work_struct work;
777 struct work_struct notify_work;
778 struct work_struct timeout_work;
779 void (*vdec_cb)(struct vdec_s *, void *);
780 void *vdec_cb_arg;
781
782 struct timer_list check_timer;
783
784 /**/
785 unsigned int last_frame_time;
786 u32 vf_pre_count;
787 u32 vf_get_count;
788 u32 vf_put_count;
789
790 /* timeout handle */
791 unsigned long int start_process_time;
792 unsigned int last_mby_mbx;
793 unsigned int last_vld_level;
794 unsigned int decode_timeout_count;
795 unsigned int timeout_num;
796 unsigned int search_dataempty_num;
797 unsigned int decode_timeout_num;
798 unsigned int decode_dataempty_num;
799 unsigned int buffer_empty_recover_num;
800
801 unsigned get_data_count;
802 unsigned get_data_start_time;
803 /**/
804
805 /*log*/
806 unsigned int packet_write_success_count;
807 unsigned int packet_write_EAGAIN_count;
808 unsigned int packet_write_ENOMEM_count;
809 unsigned int packet_write_EFAULT_count;
810 unsigned int total_read_size_pre;
811 unsigned int total_read_size;
812 unsigned int frame_count_pre;
813#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
814 u8 switch_dvlayer_flag;
815 u8 got_valid_nal;
816#endif
817 u8 eos;
818 u8 data_flag;
819 u32 no_error_count;
820 u32 no_error_i_count;
821 /*
822 NODISP_FLAG
823 */
824 u8 dec_flag;
825
826 u32 ucode_pause_pos;
827
828 u8 reset_bufmgr_flag;
829 u32 reset_bufmgr_count;
830 u32 cfg_param1;
831 u32 cfg_param2;
832 u32 cfg_param3;
833 u32 cfg_param4;
834 int valve_count;
835 u8 next_again_flag;
836 u32 pre_parser_wr_ptr;
837 struct firmware_s *fw;
838 struct firmware_s *fw_mmu;
839#ifdef MH264_USERDATA_ENABLE
840 /*user data*/
841 struct mutex userdata_mutex;
842 struct mh264_userdata_info_t userdata_info;
843 struct mh264_userdata_record_t ud_record;
844 int wait_for_udr_send;
845#endif
846 u32 no_mem_count;
847 u32 canvas_mode;
848 bool is_used_v4l;
849 void *v4l2_ctx;
850 bool v4l_params_parsed;
851 wait_queue_head_t wait_q;
852 u32 reg_g_status;
853 struct mutex chunks_mutex;
854 int need_cache_size;
855 u64 sc_start_time;
856 u8 frmbase_cont_flag;
857 struct vframe_qos_s vframe_qos;
858 int frameinfo_enable;
859 bool first_head_check_flag;
860 unsigned int height_aspect_ratio;
861 unsigned int width_aspect_ratio;
862 unsigned int first_i_policy;
863 u32 reorder_dpb_size_margin;
864 bool wait_reset_done_flag;
865#ifdef DETECT_WRONG_MULTI_SLICE
866 unsigned int multi_slice_pic_check_count;
867 /* multi_slice_pic_flag:
868 0, unknown;
869 1, single slice;
870 2, multi slice
871 */
872 unsigned int multi_slice_pic_flag;
873 unsigned int picture_slice_count;
874 unsigned int cur_picture_slice_count;
875 unsigned char force_slice_as_picture_flag;
876 unsigned int last_picture_slice_count;
877 unsigned int first_pre_frame_num;
878#endif
879 unsigned int res_ch_flag;
880 u32 b_frame_error_count;
881 struct vdec_info gvs;
882};
883
884static u32 again_threshold;
885
886static void timeout_process(struct vdec_h264_hw_s *hw);
887static void dump_bufspec(struct vdec_h264_hw_s *hw,
888 const char *caller);
889static void h264_reconfig(struct vdec_h264_hw_s *hw);
890static void h264_reset_bufmgr(struct vdec_s *vdec);
891static void vh264_local_init(struct vdec_h264_hw_s *hw, bool is_reset);
892static int vh264_hw_ctx_restore(struct vdec_h264_hw_s *hw);
893static int vh264_stop(struct vdec_h264_hw_s *hw);
894static s32 vh264_init(struct vdec_h264_hw_s *hw);
895static void set_frame_info(struct vdec_h264_hw_s *hw, struct vframe_s *vf,
896 u32 index);
897static void release_aux_data(struct vdec_h264_hw_s *hw,
898 int buf_spec_num);
899#ifdef ERROR_HANDLE_TEST
900static void h264_clear_dpb(struct vdec_h264_hw_s *hw);
901#endif
902
903#define H265_PUT_SAO_4K_SET 0x03
904#define H265_ABORT_SAO_4K_SET 0x04
905#define H265_ABORT_SAO_4K_SET_DONE 0x05
906
907#define SYS_COMMAND HEVC_ASSIST_SCRATCH_0
908#define H265_CHECK_AXI_INFO_BASE HEVC_ASSIST_SCRATCH_8
909#define H265_SAO_4K_SET_BASE HEVC_ASSIST_SCRATCH_9
910#define H265_SAO_4K_SET_COUNT HEVC_ASSIST_SCRATCH_A
911#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464
912
913
914#define HEVC_CM_HEADER_START_ADDR 0x3628
915#define HEVC_CM_BODY_START_ADDR 0x3626
916#define HEVC_CM_BODY_LENGTH 0x3627
917#define HEVC_CM_HEADER_LENGTH 0x3629
918#define HEVC_CM_HEADER_OFFSET 0x362b
919#define HEVC_SAO_CTRL9 0x362d
920#define HEVCD_MPP_DECOMP_CTL3 0x34c4
921#define HEVCD_MPP_VDEC_MCR_CTL 0x34c8
922#define HEVC_DBLK_CFGB 0x350b
923#define HEVC_ASSIST_MMU_MAP_ADDR 0x3009
924
925#define H265_DW_NO_SCALE
926#define H265_MEM_MAP_MODE 0 /*0:linear 1:32x32 2:64x32*/
927#define H265_LOSLESS_COMPRESS_MODE
928#define MAX_FRAME_4K_NUM 0x1200
929#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)
930
931/* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */
932static u32 mem_map_mode = H265_MEM_MAP_MODE;
933
934#define MAX_SIZE_4K (4096 * 2304)
935
936static int is_oversize(int w, int h)
937{
938 int max = MAX_SIZE_4K;
939
940 if (w < 0 || h < 0)
941 return true;
942
943 if (h != 0 && (w > max / h))
944 return true;
945
946 return false;
947}
948
949static void vmh264_udc_fill_vpts(struct vdec_h264_hw_s *hw,
950 int frame_type,
951 u32 vpts,
952 u32 vpts_valid);
953static int compute_losless_comp_body_size(int width,
954 int height, int bit_depth_10);
955static int compute_losless_comp_header_size(int width, int height);
956
957static int hevc_alloc_mmu(struct vdec_h264_hw_s *hw, int pic_idx,
958 int pic_width, int pic_height, u16 bit_depth,
959 unsigned int *mmu_index_adr) {
960 int cur_buf_idx;
961 int bit_depth_10 = (bit_depth != 0x00);
962 int picture_size;
963 u32 cur_mmu_4k_number;
964
965 WRITE_VREG(CURR_CANVAS_CTRL, pic_idx<<24);
966 cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL)&0xff;
967 picture_size = compute_losless_comp_body_size(pic_width,
968 pic_height, bit_depth_10);
969 cur_mmu_4k_number = ((picture_size+(1<<12)-1) >> 12);
970 dpb_print(DECODE_ID(hw),
971 PRINT_FLAG_MMU_DETAIL,
972 "alloc_mmu new_fb_idx %d picture_size %d cur_mmu_4k_number %d\n",
973 cur_buf_idx, picture_size, cur_mmu_4k_number);
974
975 if (cur_mmu_4k_number > MAX_FRAME_4K_NUM) {
976 pr_err("hevc_alloc_mmu cur_mmu_4k_number %d unsupport\n",
977 cur_mmu_4k_number);
978 return -1;
979 }
980
981 return decoder_mmu_box_alloc_idx(
982 hw->mmu_box,
983 cur_buf_idx,
984 cur_mmu_4k_number,
985 mmu_index_adr);
986}
987
988static int compute_losless_comp_body_size(int width,
989 int height, int bit_depth_10)
990{
991 int width_x64;
992 int height_x32;
993 int bsize;
994
995 width_x64 = width + 63;
996 width_x64 >>= 6;
997
998 height_x32 = height + 31;
999 height_x32 >>= 5;
1000
1001#ifdef H264_MMU
1002 bsize = (bit_depth_10 ? 4096 : 3264) * width_x64*height_x32;
1003#else
1004 bsize = (bit_depth_10 ? 4096 : 3072) * width_x64*height_x32;
1005#endif
1006 return bsize;
1007}
1008
1009static int compute_losless_comp_header_size(int width, int height)
1010{
1011 int width_x64;
1012 int width_x128;
1013 int height_x64;
1014 int hsize;
1015
1016 width_x64 = width + 63;
1017 width_x64 >>= 6;
1018
1019 width_x128 = width + 127;
1020 width_x128 >>= 7;
1021
1022 height_x64 = height + 63;
1023 height_x64 >>= 6;
1024
1025#ifdef H264_MMU
1026 hsize = 128*width_x64*height_x64;
1027#else
1028 hsize = 32*width_x128*height_x64;
1029#endif
1030 return hsize;
1031}
1032
1033static int get_double_write_ratio(struct vdec_h264_hw_s *hw)
1034{
1035 int ratio = 1;
1036 int dw_mode = hw->double_write_mode;
1037 if ((dw_mode == 2) ||
1038 (dw_mode == 3))
1039 ratio = 4;
1040 else if (dw_mode == 4)
1041 ratio = 2;
1042 return ratio;
1043}
1044
1045
1046static int get_dw_size(struct vdec_h264_hw_s *hw, u32 *pdw_buffer_size_u_v_h)
1047{
1048 int pic_width, pic_height;
1049 int lcu_size = 16;
1050 int dw_buf_size;
1051 u32 dw_buffer_size_u_v;
1052 u32 dw_buffer_size_u_v_h;
1053 int dw_mode = hw->double_write_mode;
1054
1055 pic_width = hw->frame_width;
1056 pic_height = hw->frame_height;
1057
1058 if (dw_mode) {
1059 int pic_width_dw = pic_width /
1060 get_double_write_ratio(hw);
1061 int pic_height_dw = pic_height /
1062 get_double_write_ratio(hw);
1063
1064 int pic_width_lcu_dw = (pic_width_dw % lcu_size) ?
1065 pic_width_dw / lcu_size + 1 :
1066 pic_width_dw / lcu_size;
1067 int pic_height_lcu_dw = (pic_height_dw % lcu_size) ?
1068 pic_height_dw / lcu_size + 1 :
1069 pic_height_dw / lcu_size;
1070 int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw;
1071
1072
1073 dw_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2;
1074 dw_buffer_size_u_v_h = (dw_buffer_size_u_v + 0xffff) >> 16;
1075 /*64k alignment*/
1076 dw_buf_size = ((dw_buffer_size_u_v_h << 16) * 3);
1077 *pdw_buffer_size_u_v_h = dw_buffer_size_u_v_h;
1078 } else {
1079 *pdw_buffer_size_u_v_h = 0;
1080 dw_buf_size = 0;
1081 }
1082
1083 return dw_buf_size;
1084}
1085
1086
1087static void hevc_mcr_config_canv2axitbl(struct vdec_h264_hw_s *hw, int restore)
1088{
1089 int i, size;
1090 u32 canvas_addr;
1091 unsigned long maddr;
1092 int num_buff = hw->dpb.mDPB.size;
1093 int dw_size = 0;
1094 u32 dw_buffer_size_u_v_h;
1095 u32 blkmode = hw->canvas_mode;
1096 int dw_mode = hw->double_write_mode;
1097
1098 canvas_addr = ANC0_CANVAS_ADDR;
1099 for (i = 0; i < num_buff; i++)
1100 WRITE_VREG((canvas_addr + i), i | (i << 8) | (i << 16));
1101
1102 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x1 << 1) | (0x1 << 2));
1103 size = hw->losless_comp_body_size + hw->losless_comp_header_size;
1104
1105
1106 dw_size = get_dw_size(hw, &dw_buffer_size_u_v_h);
1107 size += dw_size;
1108 if (size > 0)
1109 size += 0x10000;
1110
1111 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1112 "dw_buffer_size_u_v_h = %d, dw_size = 0x%x, size = 0x%x\n",
1113 dw_buffer_size_u_v_h, dw_size, size);
1114
1115 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1116 "body_size = %d, header_size = %d, body_size_sao = %d\n",
1117 hw->losless_comp_body_size,
1118 hw->losless_comp_header_size,
1119 hw->losless_comp_body_size_sao);
1120
1121 for (i = 0; i < num_buff; i++) {
1122 if (!restore) {
1123 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box,
1124 HEADER_BUFFER_IDX(i), size,
1125 DRIVER_HEADER_NAME, &maddr) < 0) {
1126 dpb_print(DECODE_ID(hw), 0,
1127 "%s malloc compress header failed %d\n",
1128 DRIVER_HEADER_NAME, i);
1129 return;
1130 }
1131 } else
1132 maddr = hw->buffer_spec[i].alloc_header_addr;
1133 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, maddr >> 5);
1134 hw->buffer_spec[i].alloc_header_addr = maddr;
1135 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1136 "%s : canvas: %d axiaddr:%x size 0x%x\n",
1137 __func__, i, (u32)maddr, size);
1138
1139 if (dw_mode) {
1140 u32 addr;
1141 int canvas_w;
1142 int canvas_h;
1143
1144 canvas_w = hw->frame_width /
1145 get_double_write_ratio(hw);
1146 canvas_h = hw->frame_height /
1147 get_double_write_ratio(hw);
1148
1149 if (hw->canvas_mode == 0)
1150 canvas_w = ALIGN(canvas_w, 32);
1151 else
1152 canvas_w = ALIGN(canvas_w, 64);
1153 canvas_h = ALIGN(canvas_h, 32);
1154
1155 hw->buffer_spec[i].dw_y_adr =
1156 maddr + hw->losless_comp_header_size;
1157
1158 hw->buffer_spec[i].dw_y_adr =
1159 ((hw->buffer_spec[i].dw_y_adr + 0xffff) >> 16)
1160 << 16;
1161 hw->buffer_spec[i].dw_u_v_adr =
1162 hw->buffer_spec[i].dw_y_adr
1163 + (dw_buffer_size_u_v_h << 16) * 2;
1164
1165
1166 hw->buffer_spec[i].buf_adr
1167 = hw->buffer_spec[i].dw_y_adr;
1168 addr = hw->buffer_spec[i].buf_adr;
1169
1170
1171 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1172 "dw_y_adr = 0x%x, dw_u_v_adr = 0x%x, y_addr = 0x%x, u_addr = 0x%x, v_addr = 0x%x, width = %d, height = %d\n",
1173 hw->buffer_spec[i].dw_y_adr,
1174 hw->buffer_spec[i].dw_u_v_adr,
1175 hw->buffer_spec[i].y_addr,
1176 hw->buffer_spec[i].u_addr,
1177 hw->buffer_spec[i].v_addr,
1178 canvas_w,
1179 canvas_h);
1180
1181 hw->buffer_spec[i].canvas_config[0].phy_addr =
1182 hw->buffer_spec[i].dw_y_adr;
1183 hw->buffer_spec[i].canvas_config[0].width = canvas_w;
1184 hw->buffer_spec[i].canvas_config[0].height = canvas_h;
1185 hw->buffer_spec[i].canvas_config[0].block_mode =
1186 blkmode;
1187 hw->buffer_spec[i].canvas_config[0].endian = 7;
1188
1189 hw->buffer_spec[i].canvas_config[1].phy_addr =
1190 hw->buffer_spec[i].dw_u_v_adr;
1191 hw->buffer_spec[i].canvas_config[1].width = canvas_w;
1192 hw->buffer_spec[i].canvas_config[1].height = canvas_h;
1193 hw->buffer_spec[i].canvas_config[1].block_mode =
1194 blkmode;
1195 hw->buffer_spec[i].canvas_config[1].endian = 7;
1196 }
1197 }
1198 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
1199
1200 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (0 << 8) | (0<<1) | 1);
1201 for (i = 0; i < 32; i++)
1202 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
1203 return;
1204}
1205static void hevc_mcr_config_mc_ref(struct vdec_h264_hw_s *hw)
1206{
1207 u32 i;
1208 u32 ref_canv;
1209 struct Slice *pSlice = &(hw->dpb.mSlice);
1210 /*REFLIST[0]*/
1211 for (i = 0; i < (unsigned int)(pSlice->listXsize[0]); i++) {
1212 struct StorablePicture *ref = pSlice->listX[0][i];
1213 if (ref == NULL)
1214 return;
1215 WRITE_VREG(CURR_CANVAS_CTRL, ref->buf_spec_num<<24);
1216 ref_canv = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1217 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1218 (ref->buf_spec_num & 0x3f) << 8);
1219 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ref_canv);
1220 }
1221 /*REFLIST[1]*/
1222 for (i = 0; i < (unsigned int)(pSlice->listXsize[1]); i++) {
1223 struct StorablePicture *ref = pSlice->listX[1][i];
1224 if (ref == NULL)
1225 return;
1226 WRITE_VREG(CURR_CANVAS_CTRL, ref->buf_spec_num<<24);
1227 ref_canv = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1228 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1229 (ref->buf_spec_num & 0x3f) << 8);
1230 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ref_canv);
1231 }
1232 return;
1233}
1234
1235static void hevc_mcr_config_mcrcc(struct vdec_h264_hw_s *hw)
1236{
1237 u32 rdata32;
1238 u32 rdata32_2;
1239 u32 slice_type;
1240 struct StorablePicture *ref;
1241 struct Slice *pSlice;
1242 slice_type = hw->dpb.mSlice.slice_type;
1243 pSlice = &(hw->dpb.mSlice);
1244 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2);
1245 if (slice_type == I_SLICE) {
1246 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
1247 return;
1248 }
1249 if (slice_type == B_SLICE) {
1250 ref = pSlice->listX[0][0];
1251 if (ref == NULL)
1252 return;
1253 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1254 ((ref->buf_spec_num & 0x3f) << 8));
1255 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1256 rdata32 = rdata32 & 0xffff;
1257 rdata32 = rdata32 | (rdata32 << 16);
1258 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
1259
1260 ref = pSlice->listX[1][0];
1261 if (ref == NULL)
1262 return;
1263 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1264 ((ref->buf_spec_num & 0x3f) << 8));
1265 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1266 rdata32_2 = rdata32_2 & 0xffff;
1267 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
1268 if (rdata32 == rdata32_2) {
1269 ref = pSlice->listX[1][1];
1270 if (ref == NULL)
1271 return;
1272 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1273 ((ref->buf_spec_num & 0x3f) << 8));
1274 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1275 rdata32_2 = rdata32_2 & 0xffff;
1276 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
1277 }
1278 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32_2);
1279 } else { /*P-PIC*/
1280 ref = pSlice->listX[0][0];
1281 if (ref == NULL)
1282 return;
1283 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1284 ((ref->buf_spec_num & 0x3f) << 8));
1285 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1286 rdata32 = rdata32 & 0xffff;
1287 rdata32 = rdata32 | (rdata32 << 16);
1288 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
1289
1290 ref = pSlice->listX[0][1];
1291 if (ref == NULL)
1292 return;
1293 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1294 ((ref->buf_spec_num & 0x3f) << 8));
1295 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1296 rdata32 = rdata32 & 0xffff;
1297 rdata32 = rdata32 | (rdata32 << 16);
1298 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
1299 }
1300 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0);
1301 return;
1302}
1303
1304
1305static void hevc_mcr_sao_global_hw_init(struct vdec_h264_hw_s *hw,
1306 u32 width, u32 height) {
1307 u32 data32;
1308 u32 lcu_x_num, lcu_y_num;
1309 u32 lcu_total;
1310 u32 mc_buffer_size_u_v;
1311 u32 mc_buffer_size_u_v_h;
1312 int dw_mode = hw->double_write_mode;
1313
1314 lcu_x_num = (width + 15) >> 4;
1315 lcu_y_num = (height + 15) >> 4;
1316 lcu_total = lcu_x_num * lcu_y_num;
1317
1318 hw->mc_buffer_size_u_v = mc_buffer_size_u_v = lcu_total*16*16/2;
1319 hw->mc_buffer_size_u_v_h =
1320 mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff)>>16;
1321
1322 hw->losless_comp_body_size = 0;
1323
1324 hw->losless_comp_body_size_sao =
1325 compute_losless_comp_body_size(width, height, 0);
1326 hw->losless_comp_header_size =
1327 compute_losless_comp_header_size(width, height);
1328
1329 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1); /*sw reset ipp10b_top*/
1330 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x0); /*sw reset ipp10b_top*/
1331
1332 /* setup lcu_size = 16*/
1333 WRITE_VREG(HEVCD_IPP_TOP_LCUCONFIG, 16); /*set lcu size = 16*/
1334 /*pic_width/pic_height*/
1335 WRITE_VREG(HEVCD_IPP_TOP_FRMCONFIG,
1336 (height & 0xffff) << 16 | (width & 0xffff));
1337 /* bitdepth_luma = 8*/
1338 /* bitdepth_chroma = 8*/
1339 WRITE_VREG(HEVCD_IPP_BITDEPTH_CONFIG, 0x0);/*set bit-depth 8 */
1340
1341#ifdef H265_LOSLESS_COMPRESS_MODE
1342 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
1343 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0x0);
1344#else
1345 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
1346#endif
1347 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
1348 data32 &= (~0x30);
1349 data32 |= (hw->canvas_mode << 4);
1350 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
1351
1352 WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,
1353 (0x80 << 20) | (0x80 << 10) | (0xff));
1354
1355 WRITE_VREG(HEVCD_MPP_VDEC_MCR_CTL, 0x1 | (0x1 << 4));
1356
1357 /*comfig vdec:h264:mdec to use hevc mcr/mcrcc/decomp*/
1358 WRITE_VREG(MDEC_PIC_DC_MUX_CTRL,
1359 READ_VREG(MDEC_PIC_DC_MUX_CTRL) | 0x1 << 31);
1360 /* ipp_enable*/
1361 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1 << 1);
1362
1363 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
1364 WRITE_VREG(HEVC_DBLK_CFG1, 0x2); // set ctusize==16
1365 WRITE_VREG(HEVC_DBLK_CFG2, ((height & 0xffff)<<16) | (width & 0xffff));
1366 if (dw_mode)
1367 WRITE_VREG(HEVC_DBLK_CFGB, 0x40405703);
1368 else
1369 WRITE_VREG(HEVC_DBLK_CFGB, 0x40405503);
1370 }
1371
1372 data32 = READ_VREG(HEVC_SAO_CTRL0);
1373 data32 &= (~0xf);
1374 data32 |= 0x4;
1375 WRITE_VREG(HEVC_SAO_CTRL0, data32);
1376 WRITE_VREG(HEVC_SAO_PIC_SIZE, (height & 0xffff) << 16 |
1377 (width & 0xffff));
1378 data32 = ((lcu_x_num-1) | (lcu_y_num-1) << 16);
1379
1380 WRITE_VREG(HEVC_SAO_PIC_SIZE_LCU, data32);
1381 data32 = (lcu_x_num | lcu_y_num << 16);
1382 WRITE_VREG(HEVC_SAO_TILE_SIZE_LCU, data32);
1383 data32 = (mc_buffer_size_u_v_h << 16) << 1;
1384 WRITE_VREG(HEVC_SAO_Y_LENGTH, data32);
1385 data32 = (mc_buffer_size_u_v_h << 16);
1386 WRITE_VREG(HEVC_SAO_C_LENGTH, data32);
1387
1388 data32 = READ_VREG(HEVC_SAO_CTRL1);
1389 data32 &= (~0x3000);
1390 data32 &= (~0xff0);
1391 data32 |= endian; /* Big-Endian per 64-bit */
1392
1393 if (hw->mmu_enable && dw_mode)
1394 data32 |= ((hw->canvas_mode << 12));
1395 else
1396 data32 |= ((hw->canvas_mode << 12)|2);
1397
1398 WRITE_VREG(HEVC_SAO_CTRL1, data32);
1399
1400#ifdef H265_DW_NO_SCALE
1401 WRITE_VREG(HEVC_SAO_CTRL5, READ_VREG(HEVC_SAO_CTRL5) & ~(0xff << 16));
1402 if (hw->mmu_enable && dw_mode) {
1403 data32 = READ_VREG(HEVC_SAO_CTRL5);
1404 data32 &= (~(0xff << 16));
1405 if (dw_mode == 2 ||
1406 dw_mode == 3)
1407 data32 |= (0xff<<16);
1408 else if (dw_mode == 4)
1409 data32 |= (0x33<<16);
1410 WRITE_VREG(HEVC_SAO_CTRL5, data32);
1411 }
1412
1413
1414#endif
1415
1416
1417#ifdef H265_LOSLESS_COMPRESS_MODE
1418 data32 = READ_VREG(HEVC_SAO_CTRL5);
1419 data32 |= (1<<9); /*8-bit smem-mode*/
1420 WRITE_VREG(HEVC_SAO_CTRL5, data32);
1421
1422 WRITE_VREG(HEVC_CM_BODY_LENGTH, hw->losless_comp_body_size_sao);
1423 WRITE_VREG(HEVC_CM_HEADER_OFFSET, hw->losless_comp_body_size);
1424 WRITE_VREG(HEVC_CM_HEADER_LENGTH, hw->losless_comp_header_size);
1425#endif
1426
1427#ifdef H265_LOSLESS_COMPRESS_MODE
1428 WRITE_VREG(HEVC_SAO_CTRL9, READ_VREG(HEVC_SAO_CTRL9) | (0x1 << 1));
1429 WRITE_VREG(HEVC_SAO_CTRL5, READ_VREG(HEVC_SAO_CTRL5) | (0x1 << 10));
1430#endif
1431
1432 WRITE_VREG(HEVC_SAO_CTRL9, READ_VREG(HEVC_SAO_CTRL9) | 0x1 << 7);
1433
1434 memset(hw->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE);
1435
1436 WRITE_VREG(MDEC_EXTIF_CFG0, hw->extif_addr);
1437 WRITE_VREG(MDEC_EXTIF_CFG1, 0x80000000);
1438 return;
1439}
1440
1441static void hevc_sao_set_slice_type(struct vdec_h264_hw_s *hw,
1442 u32 is_new_pic, u32 is_idr)
1443{
1444 hw->is_new_pic = is_new_pic;
1445 hw->is_idr_frame = is_idr;
1446 return;
1447}
1448
1449static void hevc_sao_set_pic_buffer(struct vdec_h264_hw_s *hw,
1450 struct StorablePicture *pic) {
1451 u32 mc_y_adr;
1452 u32 mc_u_v_adr;
1453 u32 dw_y_adr;
1454 u32 dw_u_v_adr;
1455 u32 canvas_addr;
1456 int ret;
1457 int dw_mode = hw->double_write_mode;
1458 if (hw->is_new_pic != 1)
1459 return;
1460
1461 if (hw->is_idr_frame) {
1462 /* William TBD */
1463 memset(hw->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE);
1464 }
1465
1466 WRITE_VREG(CURR_CANVAS_CTRL, pic->buf_spec_num << 24);
1467 canvas_addr = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1468 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x0 << 1) |
1469 (0x0 << 2) | ((canvas_addr & 0xff) << 8));
1470 mc_y_adr = READ_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA) << 5;
1471 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x0 << 1) |
1472 (0x0 << 2) | (((canvas_addr >> 8) & 0xff) << 8));
1473 mc_u_v_adr = READ_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA) << 5;
1474 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
1475
1476
1477 if (dw_mode) {
1478 dw_y_adr = hw->buffer_spec[pic->buf_spec_num].dw_y_adr;
1479 dw_u_v_adr = hw->buffer_spec[pic->buf_spec_num].dw_u_v_adr;
1480 } else {
1481 dw_y_adr = 0;
1482 dw_u_v_adr = 0;
1483 }
1484#ifdef H265_LOSLESS_COMPRESS_MODE
1485 if (dw_mode)
1486 WRITE_VREG(HEVC_SAO_Y_START_ADDR, dw_y_adr);
1487 WRITE_VREG(HEVC_CM_BODY_START_ADDR, mc_y_adr);
1488#ifdef H264_MMU
1489 WRITE_VREG(HEVC_CM_HEADER_START_ADDR, mc_y_adr);
1490#else
1491 WRITE_VREG(HEVC_CM_HEADER_START_ADDR,
1492 (mc_y_adr + hw->losless_comp_body_size));
1493#endif
1494#else
1495 WRITE_VREG(HEVC_SAO_Y_START_ADDR, mc_y_adr);
1496#endif
1497
1498#ifndef H265_LOSLESS_COMPRESS_MODE
1499 WRITE_VREG(HEVC_SAO_C_START_ADDR, mc_u_v_adr);
1500#else
1501 if (dw_mode)
1502 WRITE_VREG(HEVC_SAO_C_START_ADDR, dw_u_v_adr);
1503#endif
1504
1505#ifndef LOSLESS_COMPRESS_MODE
1506 if (dw_mode) {
1507 WRITE_VREG(HEVC_SAO_Y_WPTR, mc_y_adr);
1508 WRITE_VREG(HEVC_SAO_C_WPTR, mc_u_v_adr);
1509 }
1510#else
1511 WRITE_VREG(HEVC_SAO_Y_WPTR, dw_y_adr);
1512 WRITE_VREG(HEVC_SAO_C_WPTR, dw_u_v_adr);
1513#endif
1514
1515 ret = hevc_alloc_mmu(hw, pic->buf_spec_num,
1516 (hw->mb_width << 4), (hw->mb_height << 4), 0x0,
1517 hw->frame_mmu_map_addr);
1518 if (ret != 0) {
1519 dpb_print(DECODE_ID(hw),
1520 PRINT_FLAG_MMU_DETAIL, "can't alloc need mmu1,idx %d ret =%d\n",
1521 pic->buf_spec_num,
1522 ret);
1523 return;
1524 }
1525
1526 /*Reset SAO + Enable SAO slice_start*/
1527 if (hw->mmu_enable && get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A)
1528 WRITE_VREG(HEVC_DBLK_CFG0, 0x1); // reset buffer32x4 in lpf for every picture
1529 WRITE_VREG(HEVC_SAO_INT_STATUS,
1530 READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 28);
1531 WRITE_VREG(HEVC_SAO_INT_STATUS,
1532 READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 31);
1533 /*pr_info("hevc_sao_set_pic_buffer:mc_y_adr: %x\n", mc_y_adr);*/
1534 /*Send coommand to hevc-code to supply 4k buffers to sao*/
1535
1536 if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
1537 WRITE_VREG(H265_SAO_4K_SET_BASE, (u32)hw->frame_mmu_map_phy_addr);
1538 WRITE_VREG(H265_SAO_4K_SET_COUNT, MAX_FRAME_4K_NUM);
1539 } else
1540 WRITE_VREG(HEVC_ASSIST_MMU_MAP_ADDR, (u32)hw->frame_mmu_map_phy_addr);
1541 WRITE_VREG(SYS_COMMAND, H265_PUT_SAO_4K_SET);
1542 hw->frame_busy = 1;
1543 return;
1544}
1545
1546
1547static void hevc_set_unused_4k_buff_idx(struct vdec_h264_hw_s *hw,
1548 u32 buf_spec_num) {
1549 WRITE_VREG(CURR_CANVAS_CTRL, buf_spec_num<<24);
1550 hw->hevc_cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL)&0xff;
1551 dpb_print(DECODE_ID(hw),
1552 PRINT_FLAG_MMU_DETAIL, " %s cur_buf_idx %d buf_spec_num %d\n",
1553 __func__, hw->hevc_cur_buf_idx, buf_spec_num);
1554 return;
1555}
1556
1557
1558static void hevc_set_frame_done(struct vdec_h264_hw_s *hw)
1559{
1560 ulong timeout = jiffies + HZ;
1561 dpb_print(DECODE_ID(hw),
1562 PRINT_FLAG_MMU_DETAIL, "hevc_frame_done...set\n");
1563 while ((READ_VREG(HEVC_SAO_INT_STATUS) & 0x1) == 0) {
1564 if (time_after(jiffies, timeout)) {
1565 dpb_print(DECODE_ID(hw),
1566 PRINT_FLAG_MMU_DETAIL, " %s..timeout!\n", __func__);
1567 break;
1568 }
1569 }
1570 timeout = jiffies + HZ;
1571 while (READ_VREG(HEVC_CM_CORE_STATUS) & 0x1) {
1572 if (time_after(jiffies, timeout)) {
1573 dpb_print(DECODE_ID(hw),
1574 PRINT_FLAG_MMU_DETAIL, " %s cm_core..timeout!\n", __func__);
1575 break;
1576 }
1577 }
1578 WRITE_VREG(HEVC_SAO_INT_STATUS, 0x1);
1579 hw->frame_done = 1;
1580 return;
1581}
1582
1583static void release_cur_decoding_buf(struct vdec_h264_hw_s *hw)
1584{
1585 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
1586 if (p_H264_Dpb->mVideo.dec_picture) {
1587 release_picture(p_H264_Dpb,
1588 p_H264_Dpb->mVideo.dec_picture);
1589 p_H264_Dpb->mVideo.dec_picture->data_flag &= ~ERROR_FLAG;
1590 p_H264_Dpb->mVideo.dec_picture = NULL;
1591 if (hw->mmu_enable)
1592 hevc_set_frame_done(hw);
1593 }
1594}
1595
1596static void hevc_sao_wait_done(struct vdec_h264_hw_s *hw)
1597{
1598 ulong timeout = jiffies + HZ;
1599 dpb_print(DECODE_ID(hw),
1600 PRINT_FLAG_MMU_DETAIL, "hevc_sao_wait_done...start\n");
1601 while ((READ_VREG(HEVC_SAO_INT_STATUS) >> 31)) {
1602 if (time_after(jiffies, timeout)) {
1603 dpb_print(DECODE_ID(hw),
1604 PRINT_FLAG_MMU_DETAIL,
1605 "hevc_sao_wait_done...wait timeout!\n");
1606 break;
1607 }
1608 }
1609 timeout = jiffies + HZ;
1610 if ((hw->frame_busy == 1) && (hw->frame_done == 1) ) {
1611 if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
1612 WRITE_VREG(SYS_COMMAND, H265_ABORT_SAO_4K_SET);
1613 while ((READ_VREG(SYS_COMMAND) & 0xff) !=
1614 H265_ABORT_SAO_4K_SET_DONE) {
1615 if (time_after(jiffies, timeout)) {
1616 dpb_print(DECODE_ID(hw),
1617 PRINT_FLAG_MMU_DETAIL,
1618 "wait h265_abort_sao_4k_set_done timeout!\n");
1619 break;
1620 }
1621 }
1622 }
1623 amhevc_stop();
1624 hw->frame_busy = 0;
1625 hw->frame_done = 0;
1626 dpb_print(DECODE_ID(hw),
1627 PRINT_FLAG_MMU_DETAIL,
1628 "sao wait done ,hevc stop!\n");
1629 }
1630 return;
1631}
1632static void buf_spec_init(struct vdec_h264_hw_s *hw)
1633{
1634 int i;
1635 unsigned long flags;
1636 spin_lock_irqsave(&hw->bufspec_lock, flags);
1637
1638 for (i = 0; i < VF_POOL_SIZE; i++) {
1639 struct vframe_s *vf = &hw->vfpool[hw->cur_pool][i];
1640 u32 ref_idx = BUFSPEC_INDEX(vf->index);
1641 if ((vf->index != -1) &&
1642 (hw->buffer_spec[ref_idx].vf_ref == 0) &&
1643 (hw->buffer_spec[ref_idx].used != -1)) {
1644 vf->index = -1;
1645 }
1646 }
1647
1648 hw->cur_pool++;
1649 if (hw->cur_pool >= VF_POOL_NUM)
1650 hw->cur_pool = 0;
1651
1652 for (i = 0; i < VF_POOL_SIZE; i++) {
1653 struct vframe_s *vf = &hw->vfpool[hw->cur_pool][i];
1654 u32 ref_idx = BUFSPEC_INDEX(vf->index);
1655 if ((vf->index != -1) &&
1656 (hw->buffer_spec[ref_idx].vf_ref == 0) &&
1657 (hw->buffer_spec[ref_idx].used != -1)) {
1658 vf->index = -1;
1659 }
1660 }
1661
1662 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
1663 hw->buffer_spec[i].used = -1;
1664 hw->buffer_spec[i].canvas_pos = -1;
1665 }
1666
1667 if (dpb_is_debug(DECODE_ID(hw),
1668 PRINT_FLAG_DUMP_BUFSPEC))
1669 dump_bufspec(hw, __func__);
1670 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
1671}
1672
1673/*is active in buf management */
1674static unsigned char is_buf_spec_in_use(struct vdec_h264_hw_s *hw,
1675 int buf_spec_num)
1676{
1677 unsigned char ret = 0;
1678 if (hw->buffer_spec[buf_spec_num].used == 1 ||
1679 hw->buffer_spec[buf_spec_num].used == 2 ||
1680 hw->buffer_spec[buf_spec_num].used == 3 ||
1681 hw->buffer_spec[buf_spec_num].used == 5)
1682 ret = 1;
1683 return ret;
1684}
1685
1686static unsigned char is_buf_spec_in_disp_q(struct vdec_h264_hw_s *hw,
1687 int buf_spec_num)
1688{
1689 unsigned char ret = 0;
1690 if (hw->buffer_spec[buf_spec_num].used == 2 ||
1691 hw->buffer_spec[buf_spec_num].used == 3 ||
1692 hw->buffer_spec[buf_spec_num].used == 5)
1693 ret = 1;
1694 return ret;
1695}
1696
1697static int alloc_one_buf_spec(struct vdec_h264_hw_s *hw, int i)
1698{
1699 struct vdec_s *vdec = hw_to_vdec(hw);
1700 if (hw->mmu_enable) {
1701 if (hw->buffer_spec[i].alloc_header_addr)
1702 return 0;
1703 else
1704 return -1;
1705 } else {
1706
1707 int buf_size = (hw->mb_total << 8) + (hw->mb_total << 7);
1708 int addr;
1709#ifdef VDEC_DW
1710 int orig_buf_size;
1711 orig_buf_size = buf_size;
1712 if (IS_VDEC_DW(hw) == 1)
1713 buf_size += (hw->mb_total << 7) + (hw->mb_total << 6);
1714 else if (IS_VDEC_DW(hw) == 2)
1715 buf_size += (hw->mb_total << 6) + (hw->mb_total << 5);
1716#endif
1717 if (hw->buffer_spec[i].cma_alloc_addr)
1718 return 0;
1719
1720 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, i,
1721 PAGE_ALIGN(buf_size), DRIVER_NAME,
1722 &hw->buffer_spec[i].cma_alloc_addr) < 0) {
1723 hw->buffer_spec[i].cma_alloc_addr = 0;
1724 if (hw->no_mem_count++ > 3) {
1725 hw->stat |= DECODER_FATAL_ERROR_NO_MEM;
1726 hw->reset_bufmgr_flag = 1;
1727 }
1728 dpb_print(DECODE_ID(hw), 0,
1729 "%s, fail to alloc buf for bufspec%d, try later\n",
1730 __func__, i
1731 );
1732 return -1;
1733 } else {
1734 hw->no_mem_count = 0;
1735 hw->stat &= ~DECODER_FATAL_ERROR_NO_MEM;
1736 }
1737 if (!vdec_secure(vdec)) {
1738 /*init internal buf*/
1739 char *tmpbuf = (char *)codec_mm_phys_to_virt(hw->buffer_spec[i].cma_alloc_addr);
1740 if (tmpbuf) {
1741 memset(tmpbuf, 0, PAGE_ALIGN(buf_size));
1742 codec_mm_dma_flush(tmpbuf,
1743 PAGE_ALIGN(buf_size),
1744 DMA_TO_DEVICE);
1745 } else {
1746 tmpbuf = codec_mm_vmap(hw->buffer_spec[i].cma_alloc_addr, PAGE_ALIGN(buf_size));
1747 if (tmpbuf) {
1748 memset(tmpbuf, 0, PAGE_ALIGN(buf_size));
1749 codec_mm_dma_flush(tmpbuf,
1750 PAGE_ALIGN(buf_size),
1751 DMA_TO_DEVICE);
1752 codec_mm_unmap_phyaddr(tmpbuf);
1753 }
1754 }
1755 }
1756 hw->buffer_spec[i].buf_adr =
1757 hw->buffer_spec[i].cma_alloc_addr;
1758 addr = hw->buffer_spec[i].buf_adr;
1759
1760
1761 hw->buffer_spec[i].y_addr = addr;
1762 addr += hw->mb_total << 8;
1763 hw->buffer_spec[i].u_addr = addr;
1764 hw->buffer_spec[i].v_addr = addr;
1765 addr += hw->mb_total << 7;
1766
1767 hw->buffer_spec[i].canvas_config[0].phy_addr =
1768 hw->buffer_spec[i].y_addr;
1769 hw->buffer_spec[i].canvas_config[0].width =
1770 hw->mb_width << 4;
1771 hw->buffer_spec[i].canvas_config[0].height =
1772 hw->mb_height << 4;
1773 hw->buffer_spec[i].canvas_config[0].block_mode =
1774 hw->canvas_mode;
1775
1776 hw->buffer_spec[i].canvas_config[1].phy_addr =
1777 hw->buffer_spec[i].u_addr;
1778 hw->buffer_spec[i].canvas_config[1].width =
1779 hw->mb_width << 4;
1780 hw->buffer_spec[i].canvas_config[1].height =
1781 hw->mb_height << 3;
1782 hw->buffer_spec[i].canvas_config[1].block_mode =
1783 hw->canvas_mode;
1784 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
1785 "%s, alloc buf for bufspec%d\n",
1786 __func__, i
1787 );
1788#ifdef VDEC_DW
1789
1790 if (!IS_VDEC_DW(hw))
1791 return 0;
1792 else if (IS_VDEC_DW(hw) == 1) {
1793 addr = hw->buffer_spec[i].cma_alloc_addr + orig_buf_size;
1794 hw->buffer_spec[i].vdec_dw_y_addr = addr;
1795 addr += hw->mb_total << 7;
1796 hw->buffer_spec[i].vdec_dw_u_addr = addr;
1797 hw->buffer_spec[i].vdec_dw_v_addr = addr;
1798 addr += hw->mb_total << 6;
1799
1800 hw->buffer_spec[i].vdec_dw_canvas_config[0].phy_addr =
1801 hw->buffer_spec[i].vdec_dw_y_addr;
1802 hw->buffer_spec[i].vdec_dw_canvas_config[0].width =
1803 hw->mb_width << 3;
1804 hw->buffer_spec[i].vdec_dw_canvas_config[0].height =
1805 hw->mb_height << 4;
1806 hw->buffer_spec[i].vdec_dw_canvas_config[0].block_mode =
1807 CANVAS_BLKMODE_32X32;
1808
1809 hw->buffer_spec[i].vdec_dw_canvas_config[1].phy_addr =
1810 hw->buffer_spec[i].vdec_dw_u_addr;
1811 hw->buffer_spec[i].vdec_dw_canvas_config[1].width =
1812 hw->mb_width << 3;
1813 hw->buffer_spec[i].vdec_dw_canvas_config[1].height =
1814 hw->mb_height << 3;
1815 hw->buffer_spec[i].vdec_dw_canvas_config[1].block_mode =
1816 CANVAS_BLKMODE_32X32;
1817 }else {
1818 addr = hw->buffer_spec[i].cma_alloc_addr + orig_buf_size;
1819 hw->buffer_spec[i].vdec_dw_y_addr = addr;
1820 addr += hw->mb_total << 6;
1821 hw->buffer_spec[i].vdec_dw_u_addr = addr;
1822 hw->buffer_spec[i].vdec_dw_v_addr = addr;
1823 addr += hw->mb_total << 5;
1824
1825 hw->buffer_spec[i].vdec_dw_canvas_config[0].phy_addr =
1826 hw->buffer_spec[i].vdec_dw_y_addr;
1827 hw->buffer_spec[i].vdec_dw_canvas_config[0].width =
1828 hw->mb_width << 3;
1829 hw->buffer_spec[i].vdec_dw_canvas_config[0].height =
1830 hw->mb_height << 3;
1831 hw->buffer_spec[i].vdec_dw_canvas_config[0].block_mode =
1832 CANVAS_BLKMODE_32X32;
1833
1834 hw->buffer_spec[i].vdec_dw_canvas_config[1].phy_addr =
1835 hw->buffer_spec[i].vdec_dw_u_addr;
1836 hw->buffer_spec[i].vdec_dw_canvas_config[1].width =
1837 hw->mb_width << 3;
1838 hw->buffer_spec[i].vdec_dw_canvas_config[1].height =
1839 hw->mb_height << 2;
1840 hw->buffer_spec[i].vdec_dw_canvas_config[1].block_mode =
1841 CANVAS_BLKMODE_32X32;
1842 }
1843 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
1844 "%s, vdec_dw: alloc buf for bufspec%d\n",
1845 __func__, i
1846 );
1847#endif
1848 }
1849 return 0;
1850}
1851
1852static int alloc_one_buf_spec_from_queue(struct vdec_h264_hw_s *hw, int idx)
1853{
1854 int ret = 0;
1855 struct aml_vcodec_ctx *ctx = NULL;
1856 struct buffer_spec_s *bs = &hw->buffer_spec[idx];
1857 struct canvas_config_s *y_canvas_cfg = NULL;
1858 struct canvas_config_s *c_canvas_cfg = NULL;
1859 struct vdec_v4l2_buffer *fb = NULL;
1860 unsigned int y_addr = 0, c_addr = 0;
1861
1862 if (IS_ERR_OR_NULL(hw->v4l2_ctx)) {
1863 pr_err("the v4l context has err.\n");
1864 return -1;
1865 }
1866
1867 if (bs->cma_alloc_addr)
1868 return 0;
1869
1870 ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
1871 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1872 "[%d] %s(), try alloc from v4l queue buf size: %d\n",
1873 ctx->id, __func__,
1874 (hw->mb_total << 8) + (hw->mb_total << 7));
1875
1876 ret = vdec_v4l_get_buffer(hw->v4l2_ctx, &fb);
1877 if (ret < 0) {
1878 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1879 "[%d] get fb fail.\n", ctx->id);
1880 return ret;
1881 }
1882
1883 bs->cma_alloc_addr = (unsigned long)fb;
1884 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1885 "[%d] %s(), cma alloc addr: 0x%x\n",
1886 ctx->id, __func__, bs->cma_alloc_addr);
1887
1888 if (fb->num_planes == 1) {
1889 y_addr = fb->m.mem[0].addr;
1890 c_addr = fb->m.mem[0].addr + fb->m.mem[0].offset;
1891 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
1892 } else if (fb->num_planes == 2) {
1893 y_addr = fb->m.mem[0].addr;
1894 c_addr = fb->m.mem[1].addr;
1895 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
1896 fb->m.mem[1].bytes_used = fb->m.mem[1].size;
1897 }
1898
1899 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1900 "[%d] %s(), y_addr: %x, size: %u\n",
1901 ctx->id, __func__, y_addr, fb->m.mem[0].size);
1902 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1903 "[%d] %s(), c_addr: %x, size: %u\n",
1904 ctx->id, __func__, c_addr, fb->m.mem[1].size);
1905
1906 bs->y_addr = y_addr;
1907 bs->u_addr = c_addr;
1908 bs->v_addr = c_addr;
1909
1910 y_canvas_cfg = &bs->canvas_config[0];
1911 c_canvas_cfg = &bs->canvas_config[1];
1912
1913 y_canvas_cfg->phy_addr = y_addr;
1914 y_canvas_cfg->width = hw->mb_width << 4;
1915 y_canvas_cfg->height = hw->mb_height << 4;
1916 y_canvas_cfg->block_mode = hw->canvas_mode;
1917 //fb->m.mem[0].bytes_used = y_canvas_cfg->width * y_canvas_cfg->height;
1918 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1919 "[%d] %s(), y_w: %d, y_h: %d\n", ctx->id, __func__,
1920 y_canvas_cfg->width,y_canvas_cfg->height);
1921
1922 c_canvas_cfg->phy_addr = c_addr;
1923 c_canvas_cfg->width = hw->mb_width << 4;
1924 c_canvas_cfg->height = hw->mb_height << 3;
1925 c_canvas_cfg->block_mode = hw->canvas_mode;
1926 //fb->m.mem[1].bytes_used = c_canvas_cfg->width * c_canvas_cfg->height;
1927 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1928 "[%d] %s(), c_w: %d, c_h: %d\n", ctx->id, __func__,
1929 c_canvas_cfg->width, c_canvas_cfg->height);
1930
1931 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1932 "[%d] %s(), alloc buf for bufspec%d\n", ctx->id, __func__, idx);
1933
1934 return ret;
1935}
1936
1937static void config_decode_canvas(struct vdec_h264_hw_s *hw, int i)
1938{
1939 int blkmode = hw->canvas_mode;
1940 int endian = 0;
1941
1942 if (blkmode == CANVAS_BLKMODE_LINEAR) {
1943 if ((h264_debug_flag & IGNORE_PARAM_FROM_CONFIG) == 0)
1944 endian = 7;
1945 else
1946 endian = 0;
1947 }
1948
1949 if (hw->is_used_v4l)
1950 endian = 7;
1951
1952 canvas_config_ex(hw->buffer_spec[i].
1953 y_canvas_index,
1954 hw->buffer_spec[i].y_addr,
1955 hw->mb_width << 4,
1956 hw->mb_height << 4,
1957 CANVAS_ADDR_NOWRAP,
1958 blkmode,
1959 endian);
1960
1961 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1962 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1963 (1 << 11) | /* canvas_blk32_wr */
1964 (blkmode << 10) | /* canvas_blk32*/
1965 (1 << 8) | /* canvas_index_wr*/
1966 (hw->buffer_spec[i].y_canvas_index << 0) /* canvas index*/
1967 );
1968 }
1969
1970 canvas_config_ex(hw->buffer_spec[i].
1971 u_canvas_index,
1972 hw->buffer_spec[i].u_addr,
1973 hw->mb_width << 4,
1974 hw->mb_height << 3,
1975 CANVAS_ADDR_NOWRAP,
1976 blkmode,
1977 endian);
1978
1979 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1980 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1981 (1 << 11) |
1982 (blkmode << 10) |
1983 (1 << 8) |
1984 (hw->buffer_spec[i].u_canvas_index << 0));
1985 }
1986
1987 WRITE_VREG(ANC0_CANVAS_ADDR + hw->buffer_spec[i].canvas_pos,
1988 spec2canvas(&hw->buffer_spec[i]));
1989
1990
1991#ifdef VDEC_DW
1992 if (!IS_VDEC_DW(hw))
1993 return;
1994 else if (IS_VDEC_DW(hw) == 1) {
1995 canvas_config_ex(hw->buffer_spec[i].
1996 vdec_dw_y_canvas_index,
1997 hw->buffer_spec[i].vdec_dw_y_addr,
1998 hw->mb_width << 3,
1999 hw->mb_height << 4,
2000 CANVAS_ADDR_NOWRAP,
2001 blkmode,
2002 endian);
2003 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
2004 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
2005 (1 << 11) |
2006 (blkmode << 10) |
2007 (1 << 8) |
2008 (hw->buffer_spec[i].vdec_dw_y_canvas_index << 0));
2009 }
2010 canvas_config_ex(hw->buffer_spec[i].
2011 vdec_dw_u_canvas_index,
2012 hw->buffer_spec[i].vdec_dw_u_addr,
2013 hw->mb_width << 3,
2014 hw->mb_height << 3,
2015 CANVAS_ADDR_NOWRAP,
2016 blkmode,
2017 endian);
2018 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
2019 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
2020 (1 << 11) |
2021 (blkmode << 10) |
2022 (1 << 8) |
2023 (hw->buffer_spec[i].vdec_dw_u_canvas_index << 0));
2024 }
2025 } else {
2026 canvas_config_ex(hw->buffer_spec[i].
2027 vdec_dw_y_canvas_index,
2028 hw->buffer_spec[i].vdec_dw_y_addr,
2029 hw->mb_width << 3,
2030 hw->mb_height << 3,
2031 CANVAS_ADDR_NOWRAP,
2032 blkmode,
2033 endian);
2034 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
2035 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
2036 (1 << 11) |
2037 (blkmode << 10) |
2038 (1 << 8) |
2039 (hw->buffer_spec[i].vdec_dw_y_canvas_index << 0));
2040 }
2041
2042 canvas_config_ex(hw->buffer_spec[i].
2043 vdec_dw_u_canvas_index,
2044 hw->buffer_spec[i].vdec_dw_u_addr,
2045 hw->mb_width << 3,
2046 hw->mb_height << 2,
2047 CANVAS_ADDR_NOWRAP,
2048 blkmode,
2049 endian);
2050 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
2051 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
2052 (1 << 11) |
2053 (blkmode << 10) |
2054 (1 << 8) |
2055 (hw->buffer_spec[i].vdec_dw_u_canvas_index << 0));
2056 }
2057 }
2058#endif
2059}
2060
2061static void config_decode_canvas_ex(struct vdec_h264_hw_s *hw, int i)
2062{
2063 u32 blkmode = hw->canvas_mode;
2064 int canvas_w;
2065 int canvas_h;
2066
2067 canvas_w = hw->frame_width /
2068 get_double_write_ratio(hw);
2069 canvas_h = hw->frame_height /
2070 get_double_write_ratio(hw);
2071
2072 if (hw->canvas_mode == 0)
2073 canvas_w = ALIGN(canvas_w, 32);
2074 else
2075 canvas_w = ALIGN(canvas_w, 64);
2076 canvas_h = ALIGN(canvas_h, 32);
2077
2078 canvas_config_ex(hw->buffer_spec[i].
2079 y_canvas_index,
2080 hw->buffer_spec[i].dw_y_adr,
2081 canvas_w,
2082 canvas_h,
2083 CANVAS_ADDR_NOWRAP,
2084 blkmode,
2085 7);
2086
2087 canvas_config_ex(hw->buffer_spec[i].
2088 u_canvas_index,
2089 hw->buffer_spec[i].dw_u_v_adr,
2090 canvas_w,
2091 canvas_h,
2092 CANVAS_ADDR_NOWRAP,
2093 blkmode,
2094 7);
2095}
2096
2097static int v4l_get_free_buf_idx(struct vdec_s *vdec)
2098{
2099 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2100 struct aml_vcodec_ctx * v4l = hw->v4l2_ctx;
2101 struct v4l_buff_pool *pool = &v4l->cap_pool;
2102 struct buffer_spec_s *pic = NULL;
2103 int i, idx = INVALID_IDX;
2104 ulong flags;
2105
2106 spin_lock_irqsave(&hw->bufspec_lock, flags);
2107 for (i = 0; i < pool->in; ++i) {
2108 u32 state = (pool->seq[i] >> 16);
2109 u32 index = (pool->seq[i] & 0xffff);
2110
2111 switch (state) {
2112 case V4L_CAP_BUFF_IN_DEC:
2113 pic = &hw->buffer_spec[i];
2114 if ((pic->vf_ref == 0) &&
2115 (pic->used == 0) &&
2116 pic->cma_alloc_addr) {
2117 idx = i;
2118 }
2119 break;
2120 case V4L_CAP_BUFF_IN_M2M:
2121 pic = &hw->buffer_spec[index];
2122 if (!alloc_one_buf_spec_from_queue(hw, index)) {
2123 config_decode_canvas(hw, index);
2124 idx = index;
2125 }
2126 break;
2127 default:
2128 pr_err("v4l buffer state err %d.\n", state);
2129 break;
2130 }
2131
2132 if (idx != INVALID_IDX) {
2133 pic->used = 1;
2134 break;
2135 }
2136 }
2137 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2138
2139 if (idx < 0) {
2140 dpb_print(DECODE_ID(hw), 0, "%s fail\n", __func__);
2141 vmh264_dump_state(vdec);
2142 }
2143
2144 return idx;
2145}
2146
2147int get_free_buf_idx(struct vdec_s *vdec)
2148{
2149 int i;
2150 unsigned long addr, flags;
2151 int index = -1;
2152 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2153 int buf_total = BUFSPEC_POOL_SIZE;
2154
2155 if (hw->is_used_v4l)
2156 return v4l_get_free_buf_idx(vdec);
2157
2158 spin_lock_irqsave(&hw->bufspec_lock, flags);
2159 /*hw->start_search_pos = 0;*/
2160 for (i = hw->start_search_pos; i < buf_total; i++) {
2161 if (hw->mmu_enable)
2162 addr = hw->buffer_spec[i].alloc_header_addr;
2163 else
2164 addr = hw->buffer_spec[i].cma_alloc_addr;
2165
2166 if (hw->buffer_spec[i].vf_ref == 0 &&
2167 hw->buffer_spec[i].used == 0 && addr) {
2168 hw->buffer_spec[i].used = 1;
2169 hw->start_search_pos = i+1;
2170 index = i;
2171 break;
2172 }
2173 }
2174 if (index < 0) {
2175 for (i = 0; i < hw->start_search_pos; i++) {
2176 if (hw->mmu_enable)
2177 addr = hw->buffer_spec[i].alloc_header_addr;
2178 else
2179 addr = hw->buffer_spec[i].cma_alloc_addr;
2180
2181 if (hw->buffer_spec[i].vf_ref == 0 &&
2182 hw->buffer_spec[i].used == 0 && addr) {
2183 hw->buffer_spec[i].used = 1;
2184 hw->start_search_pos = i+1;
2185 index = i;
2186 break;
2187 }
2188 }
2189 }
2190 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2191 if (hw->start_search_pos >= buf_total)
2192 hw->start_search_pos = 0;
2193 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
2194 "%s, buf_spec_num %d\n", __func__, index);
2195
2196 if (index < 0) {
2197 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2198 "%s fail\n", __func__);
2199 vmh264_dump_state(vdec);
2200 }
2201
2202 if (dpb_is_debug(DECODE_ID(hw),
2203 PRINT_FLAG_DUMP_BUFSPEC))
2204 dump_bufspec(hw, __func__);
2205 return index;
2206}
2207
2208int release_buf_spec_num(struct vdec_s *vdec, int buf_spec_num)
2209{
2210 /*u32 cur_buf_idx;*/
2211 unsigned long flags;
2212 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2213 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
2214 "%s buf_spec_num %d used %d\n",
2215 __func__, buf_spec_num,
2216 buf_spec_num > 0 ? hw->buffer_spec[buf_spec_num].used : 0);
2217 if (buf_spec_num >= 0 &&
2218 buf_spec_num < BUFSPEC_POOL_SIZE
2219 ) {
2220 spin_lock_irqsave(&hw->bufspec_lock, flags);
2221 hw->buffer_spec[buf_spec_num].used = 0;
2222 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2223 if (hw->mmu_enable) {
2224 /*WRITE_VREG(CURR_CANVAS_CTRL, buf_spec_num<<24);
2225 cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL);
2226 cur_buf_idx = cur_buf_idx&0xff;*/
2227 decoder_mmu_box_free_idx(hw->mmu_box, buf_spec_num);
2228 }
2229 release_aux_data(hw, buf_spec_num);
2230 }
2231 if (dpb_is_debug(DECODE_ID(hw),
2232 PRINT_FLAG_DUMP_BUFSPEC))
2233 dump_bufspec(hw, __func__);
2234 return 0;
2235}
2236
2237static void config_buf_specs(struct vdec_s *vdec)
2238{
2239 int i, j;
2240 unsigned long flags;
2241 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2242 int mode = IS_VDEC_DW(hw) ? 2 : 1;
2243
2244 spin_lock_irqsave(&hw->bufspec_lock, flags);
2245 for (i = 0, j = 0;
2246 j < hw->dpb.mDPB.size
2247 && i < BUFSPEC_POOL_SIZE;
2248 i++) {
2249 int canvas;
2250 if (hw->buffer_spec[i].used != -1)
2251 continue;
2252 if (vdec->parallel_dec == 1) {
2253 if (hw->buffer_spec[i].y_canvas_index == -1)
2254 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2255 if (hw->buffer_spec[i].u_canvas_index == -1) {
2256 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2257 hw->buffer_spec[i].v_canvas_index = hw->buffer_spec[i].u_canvas_index;
2258 }
2259#ifdef VDEC_DW
2260 if (IS_VDEC_DW(hw)) {
2261 if (hw->buffer_spec[i].vdec_dw_y_canvas_index == -1)
2262 hw->buffer_spec[i].vdec_dw_y_canvas_index =
2263 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2264 if (hw->buffer_spec[i].vdec_dw_u_canvas_index == -1) {
2265 hw->buffer_spec[i].vdec_dw_u_canvas_index =
2266 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2267 hw->buffer_spec[i].vdec_dw_v_canvas_index =
2268 hw->buffer_spec[i].vdec_dw_u_canvas_index;
2269 }
2270 }
2271#endif
2272 } else {
2273 canvas = vdec->get_canvas(j * mode, 2);
2274 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
2275 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
2276 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
2277 dpb_print(DECODE_ID(hw),
2278 PRINT_FLAG_DPB_DETAIL,
2279 "config canvas (%d) %x for bufspec %d\r\n",
2280 j, canvas, i);
2281#ifdef VDEC_DW
2282 if (IS_VDEC_DW(hw)) {
2283 canvas = vdec->get_canvas(j * mode + 1, 2);
2284 hw->buffer_spec[i].vdec_dw_y_canvas_index = canvas_y(canvas);
2285 hw->buffer_spec[i].vdec_dw_u_canvas_index = canvas_u(canvas);
2286 hw->buffer_spec[i].vdec_dw_v_canvas_index = canvas_v(canvas);
2287 dpb_print(DECODE_ID(hw),
2288 PRINT_FLAG_DPB_DETAIL,
2289 "vdec_dw: config canvas (%d) %x for bufspec %d\r\n",
2290 j, canvas, i);
2291 }
2292#endif
2293 }
2294
2295 hw->buffer_spec[i].used = 0;
2296 hw->buffer_spec[i].canvas_pos = j;
2297
2298
2299 j++;
2300 }
2301 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2302}
2303
2304static void config_buf_specs_ex(struct vdec_s *vdec)
2305{
2306 int i, j;
2307 unsigned long flags;
2308 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2309 int mode = IS_VDEC_DW(hw) ? 2 : 1;
2310
2311 spin_lock_irqsave(&hw->bufspec_lock, flags);
2312 for (i = 0, j = 0;
2313 j < hw->dpb.mDPB.size
2314 && i < BUFSPEC_POOL_SIZE;
2315 i++) {
2316 int canvas = 0;
2317 if (hw->buffer_spec[i].used != -1)
2318 continue;
2319 if (vdec->parallel_dec == 1) {
2320 if (hw->buffer_spec[i].y_canvas_index == -1)
2321 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2322 if (hw->buffer_spec[i].u_canvas_index == -1) {
2323 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2324 hw->buffer_spec[i].v_canvas_index = hw->buffer_spec[i].u_canvas_index;
2325 }
2326#ifdef VDEC_DW
2327 if (IS_VDEC_DW(hw)) {
2328 if (hw->buffer_spec[i].vdec_dw_y_canvas_index == -1)
2329 hw->buffer_spec[i].vdec_dw_y_canvas_index =
2330 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2331 if (hw->buffer_spec[i].vdec_dw_u_canvas_index == -1) {
2332 hw->buffer_spec[i].vdec_dw_u_canvas_index =
2333 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2334 hw->buffer_spec[i].vdec_dw_v_canvas_index =
2335 hw->buffer_spec[i].vdec_dw_u_canvas_index;
2336 }
2337 }
2338#endif
2339 } else {
2340 canvas = vdec->get_canvas(j* mode, 2);
2341 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
2342 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
2343 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
2344
2345 dpb_print(DECODE_ID(hw),
2346 PRINT_FLAG_DPB_DETAIL,
2347 "config canvas (%d) %x for bufspec %d\r\n",
2348 j, canvas, i);
2349#ifdef VDEC_DW
2350 if (IS_VDEC_DW(hw)) {
2351 canvas = vdec->get_canvas(j*mode + 1, 2);
2352 hw->buffer_spec[i].vdec_dw_y_canvas_index = canvas_y(canvas);
2353 hw->buffer_spec[i].vdec_dw_u_canvas_index = canvas_u(canvas);
2354 hw->buffer_spec[i].vdec_dw_v_canvas_index = canvas_v(canvas);
2355 dpb_print(DECODE_ID(hw),
2356 PRINT_FLAG_DPB_DETAIL,
2357 "vdec_dw: config canvas (%d) %x for bufspec %d\r\n",
2358 j, canvas, i);
2359 }
2360#endif
2361 }
2362
2363 hw->buffer_spec[i].used = 0;
2364 hw->buffer_spec[i].alloc_header_addr = 0;
2365 hw->buffer_spec[i].canvas_pos = j;
2366
2367 j++;
2368 }
2369 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2370}
2371
2372
2373static void dealloc_buf_specs(struct vdec_h264_hw_s *hw,
2374 unsigned char release_all)
2375{
2376 int i;
2377 unsigned long flags;
2378 unsigned char dealloc_flag = 0;
2379 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2380 if (hw->buffer_spec[i].used == 4 ||
2381 release_all) {
2382 dealloc_flag = 1;
2383 dpb_print(DECODE_ID(hw),
2384 PRINT_FLAG_DPB_DETAIL,
2385 "%s buf_spec_num %d\n",
2386 __func__, i
2387 );
2388 spin_lock_irqsave
2389 (&hw->bufspec_lock, flags);
2390 hw->buffer_spec[i].used = -1;
2391 spin_unlock_irqrestore
2392 (&hw->bufspec_lock, flags);
2393 release_aux_data(hw, i);
2394
2395 if (!hw->mmu_enable) {
2396 if (hw->buffer_spec[i].cma_alloc_addr) {
2397 if (!hw->is_used_v4l) {
2398 decoder_bmmu_box_free_idx(
2399 hw->bmmu_box,
2400 i);
2401 }
2402 spin_lock_irqsave
2403 (&hw->bufspec_lock, flags);
2404 hw->buffer_spec[i].cma_alloc_addr = 0;
2405 hw->buffer_spec[i].buf_adr = 0;
2406 spin_unlock_irqrestore
2407 (&hw->bufspec_lock, flags);
2408 }
2409 } else {
2410 if (hw->buffer_spec[i].alloc_header_addr) {
2411 decoder_mmu_box_free_idx(
2412 hw->mmu_box,
2413 i);
2414 spin_lock_irqsave
2415 (&hw->bufspec_lock, flags);
2416 hw->buffer_spec[i].
2417 alloc_header_addr = 0;
2418 hw->buffer_spec[i].buf_adr = 0;
2419 spin_unlock_irqrestore
2420 (&hw->bufspec_lock, flags);
2421 }
2422 }
2423 }
2424 }
2425 if (dealloc_flag &&
2426 dpb_is_debug(DECODE_ID(hw),
2427 PRINT_FLAG_DUMP_BUFSPEC))
2428 dump_bufspec(hw, __func__);
2429 return;
2430}
2431
2432unsigned char have_free_buf_spec(struct vdec_s *vdec)
2433{
2434 int i;
2435 unsigned long addr;
2436 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2437 struct aml_vcodec_ctx * v4l = hw->v4l2_ctx;
2438 int canvas_pos_min = BUFSPEC_POOL_SIZE;
2439 int index = -1;
2440 int ret = 0;
2441 int allocated_count = 0;
2442
2443 if (hw->is_used_v4l) {
2444 for (i = 0; i < hw->dpb.mDPB.size; i++) {
2445 if (hw->buffer_spec[i].used == 0 &&
2446 hw->buffer_spec[i].vf_ref == 0 &&
2447 hw->buffer_spec[i].cma_alloc_addr) {
2448 return 1;
2449 }
2450 }
2451
2452 if (v4l2_m2m_num_dst_bufs_ready(v4l->m2m_ctx)
2453 >= run_ready_min_buf_num)
2454 return 1;
2455
2456 return 0;
2457 }
2458
2459 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2460 if (hw->mmu_enable)
2461 addr = hw->buffer_spec[i].alloc_header_addr;
2462 else
2463 addr = hw->buffer_spec[i].cma_alloc_addr;
2464 if (hw->buffer_spec[i].used == 0 &&
2465 hw->buffer_spec[i].vf_ref == 0) {
2466
2467 if (addr)
2468 return 1;
2469 if (hw->buffer_spec[i].canvas_pos < canvas_pos_min) {
2470 canvas_pos_min = hw->buffer_spec[i].canvas_pos;
2471 index = i;
2472 }
2473 }
2474 if (addr)
2475 allocated_count++;
2476 }
2477 if (index >= 0) {
2478 mutex_lock(&vmh264_mutex);
2479 dealloc_buf_specs(hw, 0);
2480 if (max_alloc_buf_count == 0 ||
2481 allocated_count < max_alloc_buf_count) {
2482 if (alloc_one_buf_spec(hw, index) >= 0)
2483 ret = 1;
2484 }
2485 mutex_unlock(&vmh264_mutex);
2486 }
2487
2488 return ret;
2489}
2490
2491static int get_buf_spec_by_canvas_pos(struct vdec_h264_hw_s *hw,
2492 int canvas_pos)
2493{
2494 int i;
2495 int j = 0;
2496 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2497 if (hw->buffer_spec[i].canvas_pos >= 0) {
2498 if (j == canvas_pos)
2499 return i;
2500 j++;
2501 }
2502 }
2503 return -1;
2504}
2505static void update_vf_memhandle(struct vdec_h264_hw_s *hw,
2506 struct vframe_s *vf, int index)
2507{
2508 if (index < 0) {
2509 vf->mem_handle = NULL;
2510 vf->mem_head_handle = NULL;
2511 } else if (vf->type & VIDTYPE_SCATTER) {
2512 vf->mem_handle =
2513 decoder_mmu_box_get_mem_handle(
2514 hw->mmu_box, index);
2515 vf->mem_head_handle =
2516 decoder_bmmu_box_get_mem_handle(
2517 hw->bmmu_box, HEADER_BUFFER_IDX(index));
2518 } else {
2519 vf->mem_handle =
2520 decoder_bmmu_box_get_mem_handle(
2521 hw->bmmu_box, VF_BUFFER_IDX(index));
2522 /* vf->mem_head_handle =
2523 decoder_bmmu_box_get_mem_handle(
2524 hw->bmmu_box, HEADER_BUFFER_IDX(index));*/
2525 }
2526 return;
2527}
2528static int check_force_interlace(struct vdec_h264_hw_s *hw,
2529 struct FrameStore *frame)
2530{
2531 int bForceInterlace = 0;
2532 /* no di in secure mode, disable force di */
2533 if (vdec_secure(hw_to_vdec(hw)))
2534 return 0;
2535 if (frame->frame) {
2536 if (frame->frame->coded_frame
2537 && !frame->frame->frame_mbs_only_flag) {
2538 if (frame->frame->structure == FRAME)
2539 return 1;
2540 }
2541 }
2542
2543 if ((dec_control & DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE)
2544 && hw->bitstream_restriction_flag
2545 && (hw->frame_width == 1920)
2546 && (hw->frame_height >= 1080)
2547 && (hw->frame_dur == 3203 || hw->frame_dur == 3840)) {
2548 bForceInterlace = 1;
2549 } else if ((dec_control & DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE)
2550 && (hw->frame_width == 720)
2551 && (hw->frame_height == 576)
2552 && (hw->frame_dur == 3840)) {
2553 bForceInterlace = 1;
2554 }
2555
2556 return bForceInterlace;
2557}
2558
2559static void fill_frame_info(struct vdec_h264_hw_s *hw, struct FrameStore *frame)
2560{
2561 struct vframe_qos_s *vframe_qos = &hw->vframe_qos;
2562
2563 if (frame->slice_type == I_SLICE)
2564 vframe_qos->type = 1;
2565 else if (frame->slice_type == P_SLICE)
2566 vframe_qos->type = 2;
2567 else if (frame->slice_type == B_SLICE)
2568 vframe_qos->type = 3;
2569
2570 if (input_frame_based(hw_to_vdec(hw)))
2571 vframe_qos->size = frame->frame_size2;
2572 else
2573 vframe_qos->size = frame->frame_size;
2574 vframe_qos->pts = frame->pts64;
2575
2576 vframe_qos->max_mv = frame->max_mv;
2577 vframe_qos->avg_mv = frame->avg_mv;
2578 vframe_qos->min_mv = frame->min_mv;
2579/*
2580 pr_info("mv: max:%d, avg:%d, min:%d\n",
2581 vframe_qos->max_mv,
2582 vframe_qos->avg_mv,
2583 vframe_qos->min_mv);
2584*/
2585
2586 vframe_qos->max_qp = frame->max_qp;
2587 vframe_qos->avg_qp = frame->avg_qp;
2588 vframe_qos->min_qp = frame->min_qp;
2589/*
2590 pr_info("qp: max:%d, avg:%d, min:%d\n",
2591 vframe_qos->max_qp,
2592 vframe_qos->avg_qp,
2593 vframe_qos->min_qp);
2594*/
2595
2596 vframe_qos->max_skip = frame->max_skip;
2597 vframe_qos->avg_skip = frame->avg_skip;
2598 vframe_qos->min_skip = frame->min_skip;
2599/*
2600 pr_info("skip: max:%d, avg:%d, min:%d\n",
2601 vframe_qos->max_skip,
2602 vframe_qos->avg_skip,
2603 vframe_qos->min_skip);
2604*/
2605 vframe_qos->num++;
2606}
2607
2608static int is_iframe(struct FrameStore *frame) {
2609
2610 if (frame->frame && frame->frame->slice_type == I_SLICE) {
2611 return 1;
2612 }
2613 return 0;
2614}
2615
2616
2617
2618int prepare_display_buf(struct vdec_s *vdec, struct FrameStore *frame)
2619{
2620 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2621 struct vframe_s *vf = NULL;
2622 int buffer_index = frame->buf_spec_num;
2623 struct aml_vcodec_ctx * v4l2_ctx = hw->v4l2_ctx;
2624 ulong nv_order = VIDTYPE_VIU_NV21;
2625 int vf_count = 1;
2626 int i;
2627 int bForceInterlace = 0;
2628
2629 if (buffer_index < 0 || buffer_index >= BUFSPEC_POOL_SIZE) {
2630 dpb_print(DECODE_ID(hw), 0,
2631 "%s, buffer_index 0x%x is beyond range\n",
2632 __func__, buffer_index);
2633 return -1;
2634 }
2635
2636 /* swap uv */
2637 if (hw->is_used_v4l) {
2638 if ((v4l2_ctx->cap_pix_fmt == V4L2_PIX_FMT_NV12) ||
2639 (v4l2_ctx->cap_pix_fmt == V4L2_PIX_FMT_NV12M))
2640 nv_order = VIDTYPE_VIU_NV12;
2641 }
2642
2643 if (force_disp_bufspec_num & 0x100) {
2644 /*recycle directly*/
2645 if (hw->buffer_spec[frame->buf_spec_num].used != 3 &&
2646 hw->buffer_spec[frame->buf_spec_num].used != 5)
2647 set_frame_output_flag(&hw->dpb, frame->index);
2648
2649 /*make pre_output not set*/
2650 return -1;
2651 }
2652 if (error_proc_policy & 0x1000) {
2653 int error_skip_i_count = (error_skip_count >> 12) & 0xf;
2654 int error_skip_frame_count = error_skip_count & 0xfff;
2655 if (((hw->no_error_count < error_skip_frame_count)
2656 && (error_skip_i_count == 0 ||
2657 hw->no_error_i_count < error_skip_i_count))
2658 && (!(frame->data_flag & I_FLAG)))
2659 frame->data_flag |= ERROR_FLAG;
2660 }
2661 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
2662 "%s, buffer_index 0x%x frame_error %x poc %d hw error %x error_proc_policy %x\n",
2663 __func__, buffer_index, frame->data_flag & ERROR_FLAG,
2664 frame->poc, hw->data_flag & ERROR_FLAG,
2665 error_proc_policy);
2666 if (frame->frame == NULL &&
2667 ((frame->is_used == 1 && frame->top_field)
2668 || (frame->is_used == 2 && frame->bottom_field))) {
2669 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
2670 "%s Error frame_num %d used %d\n",
2671 __func__, frame->frame_num, frame->is_used);
2672 frame->data_flag |= ERROR_FLAG;
2673 }
2674 if (vdec_stream_based(vdec) && !(frame->data_flag & NODISP_FLAG)) {
2675 if ((pts_lookup_offset_us64(PTS_TYPE_VIDEO,
2676 frame->offset_delimiter, &frame->pts, &frame->frame_size,
2677 0, &frame->pts64) == 0)) {
2678 hw->last_pts64 = frame->pts64;
2679 hw->last_pts = frame->pts;
2680 } else {
2681 frame->pts64 = hw->last_pts64 +DUR2PTS(hw->frame_dur) ;
2682 frame->pts = hw->last_pts + DUR2PTS(hw->frame_dur);
2683 }
2684 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
2685 "%s error= 0x%x poc = %d offset= 0x%x pts= 0x%x last_pts =0x%x pts64 = %lld last_pts64= %lld duration = %d\n",
2686 __func__, (frame->data_flag & ERROR_FLAG), frame->poc,
2687 frame->offset_delimiter, frame->pts,hw->last_pts,
2688 frame->pts64, hw->last_pts64, hw->frame_dur);
2689 hw->last_pts64 = frame->pts64;
2690 hw->last_pts = frame->pts;
2691 }
2692
2693 /* SWPL-18973 96000/15=6400, less than 15fps check */
2694 if ((!hw->duration_from_pts_done) && (hw->frame_dur > 6400ULL)) {
2695 if ((check_force_interlace(hw, frame)) &&
2696 (frame->slice_type == I_SLICE) &&
2697 (hw->pts_outside)) {
2698 if ((!hw->h264_pts_count) || (!hw->h264pts1)) {
2699 hw->h264pts1 = frame->pts;
2700 hw->h264_pts_count = 0;
2701 } else if (frame->pts > hw->h264pts1) {
2702 u32 calc_dur =
2703 PTS2DUR(frame->pts - hw->h264pts1);
2704 calc_dur = ((calc_dur/hw->h264_pts_count) << 1);
2705 if (hw->frame_dur < (calc_dur + 200) &&
2706 hw->frame_dur > (calc_dur - 200)) {
2707 hw->frame_dur >>= 1;
2708 vdec_schedule_work(&hw->notify_work);
2709 dpb_print(DECODE_ID(hw), 0,
2710 "correct frame_dur %d, calc_dur %d, count %d\n",
2711 hw->frame_dur, (calc_dur >> 1), hw->h264_pts_count);
2712 hw->duration_from_pts_done = 1;
2713 hw->h264_pts_count = 0;
2714 }
2715 }
2716 }
2717 hw->h264_pts_count++;
2718 }
2719
2720 if (frame->data_flag & ERROR_FLAG) {
2721 vdec_count_info(&hw->gvs, 1, 0);
2722 if (!hw->send_error_frame_flag)
2723 hw->gvs.drop_frame_count++;
2724 }
2725
2726 if ((frame->data_flag & NODISP_FLAG) ||
2727 (frame->data_flag & NULL_FLAG) ||
2728 ((!hw->send_error_frame_flag) &&
2729 (frame->data_flag & ERROR_FLAG)) ||
2730 ((hw->i_only & 0x1) &&
2731 (!(frame->data_flag & I_FLAG)))
2732 ) {
2733 set_frame_output_flag(&hw->dpb, frame->index);
2734 return 0; /*do not return -1,
2735 otherwise flush_dpb() will not flush all dbp frames*/
2736 }
2737
2738 display_frame_count[DECODE_ID(hw)]++;
2739
2740 if (dpb_is_debug(DECODE_ID(hw),
2741 PRINT_FLAG_DPB_DETAIL)) {
2742 dpb_print(DECODE_ID(hw), 0,
2743 "%s, fs[%d] poc %d, buf_spec_num %d\n",
2744 __func__, frame->index, frame->poc,
2745 frame->buf_spec_num);
2746 print_pic_info(DECODE_ID(hw), "predis_frm",
2747 frame->frame, -1);
2748 print_pic_info(DECODE_ID(hw), "predis_top",
2749 frame->top_field, -1);
2750 print_pic_info(DECODE_ID(hw), "predis_bot",
2751 frame->bottom_field, -1);
2752 }
2753
2754 if (!is_interlace(frame))
2755 vf_count = 1;
2756 else
2757 vf_count = 2;
2758 bForceInterlace = check_force_interlace(hw, frame);
2759 if (bForceInterlace)
2760 vf_count = 2;
2761 if (hw->is_used_v4l)
2762 vf_count = 1;
2763 hw->buffer_spec[buffer_index].vf_ref = 0;
2764 fill_frame_info(hw, frame);
2765 for (i = 0; i < vf_count; i++) {
2766 if (kfifo_get(&hw->newframe_q, &vf) == 0 ||
2767 vf == NULL) {
2768 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2769 "%s fatal error, no available buffer slot.\n",
2770 __func__);
2771 return -1;
2772 }
2773 vf->duration_pulldown = 0;
2774 if (!(is_iframe(frame)) && hw->unstable_pts) {
2775 vf->pts = 0;
2776 vf->pts_us64 = 0;
2777 vf->timestamp = 0;
2778 vf->index = VF_INDEX(frame->index, buffer_index);
2779 } else {
2780 vf->pts = frame->pts;
2781 vf->pts_us64 = frame->pts64;
2782 vf->timestamp = frame->timestamp;
2783 vf->index = VF_INDEX(frame->index, buffer_index);
2784 }
2785
2786 if (hw->is_used_v4l) {
2787 vf->v4l_mem_handle
2788 = hw->buffer_spec[buffer_index].cma_alloc_addr;
2789 }
2790
2791 if (hw->mmu_enable) {
2792 if (hw->double_write_mode & 0x10) {
2793 /* double write only */
2794 vf->compBodyAddr = 0;
2795 vf->compHeadAddr = 0;
2796 } else {
2797 /*head adr*/
2798 vf->compHeadAddr =
2799 hw->buffer_spec[buffer_index].alloc_header_addr;
2800 /*body adr*/
2801 vf->compBodyAddr = 0;
2802 vf->canvas0Addr = vf->canvas1Addr = 0;
2803 }
2804
2805 vf->type = VIDTYPE_SCATTER;
2806
2807 if (hw->double_write_mode) {
2808 vf->type |= VIDTYPE_PROGRESSIVE
2809 | VIDTYPE_VIU_FIELD;
2810 vf->type |= nv_order;
2811 if (hw->double_write_mode == 3)
2812 vf->type |= VIDTYPE_COMPRESS;
2813
2814 vf->canvas0Addr = vf->canvas1Addr = -1;
2815 vf->plane_num = 2;
2816 vf->canvas0_config[0] =
2817 hw->buffer_spec[buffer_index].
2818 canvas_config[0];
2819 vf->canvas0_config[1] =
2820 hw->buffer_spec[buffer_index].
2821 canvas_config[1];
2822
2823 vf->canvas1_config[0] =
2824 hw->buffer_spec[buffer_index].
2825 canvas_config[0];
2826 vf->canvas1_config[1] =
2827 hw->buffer_spec[buffer_index].
2828 canvas_config[1];
2829
2830 } else {
2831 vf->type |=
2832 VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
2833 vf->canvas0Addr = vf->canvas1Addr = 0;
2834 }
2835
2836 vf->bitdepth =
2837 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
2838
2839 vf->compWidth = hw->frame_width;
2840 vf->compHeight = hw->frame_height;
2841 } else {
2842 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD |
2843 nv_order;
2844
2845 vf->canvas0Addr = vf->canvas1Addr =
2846 spec2canvas(&hw->buffer_spec[buffer_index]);
2847#ifdef VDEC_DW
2848 if (IS_VDEC_DW(hw))
2849 vf->canvas0Addr = vf->canvas1Addr =
2850 vdec_dw_spec2canvas(&hw->buffer_spec[buffer_index]);
2851#endif
2852
2853 }
2854 set_frame_info(hw, vf, buffer_index);
2855
2856 if (hw->mmu_enable && hw->double_write_mode) {
2857 vf->width = hw->frame_width /
2858 get_double_write_ratio(hw);
2859 vf->height = hw->frame_height /
2860 get_double_write_ratio(hw);
2861 }
2862
2863 vf->flag = 0;
2864 if (frame->data_flag & I_FLAG)
2865 vf->flag |= VFRAME_FLAG_SYNCFRAME;
2866 if (frame->data_flag & ERROR_FLAG)
2867 vf->flag |= VFRAME_FLAG_ERROR_RECOVERY;
2868 update_vf_memhandle(hw, vf, buffer_index);
2869 hw->buffer_spec[buffer_index].used = 2;
2870 hw->buffer_spec[buffer_index].vf_ref++;
2871
2872 if (bForceInterlace || is_interlace(frame)) {
2873 vf->type =
2874 VIDTYPE_INTERLACE_FIRST |
2875 nv_order;
2876
2877 if (bForceInterlace) {
2878 if (frame->frame != NULL && frame->frame->pic_struct == PIC_TOP_BOT) {
2879 vf->type |= (i == 0 ?
2880 VIDTYPE_INTERLACE_TOP :
2881 VIDTYPE_INTERLACE_BOTTOM);
2882 } else if (frame->frame != NULL && frame->frame->pic_struct == PIC_BOT_TOP) {
2883 vf->type |= (i == 0 ?
2884 VIDTYPE_INTERLACE_BOTTOM :
2885 VIDTYPE_INTERLACE_TOP);
2886 } else {
2887 vf->type |= (i == 0 ?
2888 VIDTYPE_INTERLACE_TOP :
2889 VIDTYPE_INTERLACE_BOTTOM);
2890 }
2891
2892 if (i == 1) {
2893 vf->pts = 0;
2894 vf->pts_us64 = 0;
2895 }
2896 } else if (frame->top_field->poc <=
2897 frame->bottom_field->poc) /*top first*/
2898 vf->type |= (i == 0 ?
2899 VIDTYPE_INTERLACE_TOP :
2900 VIDTYPE_INTERLACE_BOTTOM);
2901 else
2902 vf->type |= (i == 0 ?
2903 VIDTYPE_INTERLACE_BOTTOM :
2904 VIDTYPE_INTERLACE_TOP);
2905 vf->duration = vf->duration/2;
2906 }
2907
2908 if (i == 0) {
2909 struct vdec_s *pvdec;
2910 struct vdec_info vs;
2911
2912 pvdec = hw_to_vdec(hw);
2913 memset(&vs, 0, sizeof(struct vdec_info));
2914 pvdec->dec_status(pvdec, &vs);
2915 decoder_do_frame_check(pvdec, vf);
2916 vdec_fill_vdec_frame(pvdec, &hw->vframe_qos, &vs, vf, frame->hw_decode_time);
2917 }
2918
2919 /*vf->ratio_control |= (0x3FF << DISP_RATIO_ASPECT_RATIO_BIT);*/
2920 vf->sar_width = hw->width_aspect_ratio;
2921 vf->sar_height = hw->height_aspect_ratio;
2922
2923 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
2924 ATRACE_COUNTER(MODULE_NAME, vf->pts);
2925 hw->vf_pre_count++;
2926 vdec->vdec_fps_detec(vdec->id);
2927 if (without_display_mode == 0) {
2928 vf_notify_receiver(vdec->vf_provider_name,
2929 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
2930 } else
2931 vh264_vf_put(vh264_vf_get(vdec), vdec);
2932 }
2933 if (dpb_is_debug(DECODE_ID(hw),
2934 PRINT_FLAG_DUMP_BUFSPEC))
2935 dump_bufspec(hw, __func__);
2936
2937 return 0;
2938}
2939
2940int notify_v4l_eos(struct vdec_s *vdec)
2941{
2942 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2943 struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
2944 struct vframe_s *vf = &hw->vframe_dummy;
2945 struct vdec_v4l2_buffer *fb = NULL;
2946 int index = INVALID_IDX;
2947 ulong expires;
2948
2949 if (hw->is_used_v4l && hw->eos) {
2950 expires = jiffies + msecs_to_jiffies(2000);
2951 while (INVALID_IDX == (index = v4l_get_free_buf_idx(vdec))) {
2952 if (time_after(jiffies, expires) ||
2953 v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx))
2954 break;
2955 }
2956
2957 if (index == INVALID_IDX) {
2958 if (vdec_v4l_get_buffer(hw->v4l2_ctx, &fb) < 0) {
2959 pr_err("[%d] EOS get free buff fail.\n", ctx->id);
2960 return -1;
2961 }
2962 }
2963
2964 vf->type |= VIDTYPE_V4L_EOS;
2965 vf->timestamp = ULONG_MAX;
2966 vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L;
2967 vf->v4l_mem_handle = (index == INVALID_IDX) ? (ulong)fb :
2968 hw->buffer_spec[index].cma_alloc_addr;
2969
2970 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
2971
2972 ATRACE_COUNTER(MODULE_NAME, vf->pts);
2973 vf_notify_receiver(vdec->vf_provider_name,
2974 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
2975
2976 pr_info("[%d] H264 EOS notify.\n", ctx->id);
2977 }
2978
2979 return 0;
2980}
2981
2982/******************
2983 * Hardware config
2984 */
2985char *slice_type_name[] = {
2986 "P_SLICE ",
2987 "B_SLICE ",
2988 "I_SLICE ",
2989 "SP_SLICE",
2990 "SI_SLICE",
2991};
2992
2993char *picture_structure_name[] = {
2994 "FRAME",
2995 "TOP_FIELD",
2996 "BOTTOM_FIELD"
2997};
2998
2999void print_pic_info(int decindex, const char *info,
3000 struct StorablePicture *pic,
3001 int slice_type)
3002{
3003 if (pic)
3004 dpb_print(decindex, PRINT_FLAG_DEC_DETAIL,
3005 "%s: %s (original %s), %s, mb_aff_frame_flag %d poc %d, pic_num %d, buf_spec_num %d data_flag 0x%x\n",
3006 info,
3007 picture_structure_name[pic->structure],
3008 pic->coded_frame ? "Frame" : "Field",
3009 (slice_type < 0 ||
3010 slice_type >= (sizeof(slice_type_name) / sizeof(slice_type_name[0]))) ? "" : slice_type_name[slice_type],
3011 pic->mb_aff_frame_flag,
3012 pic->poc,
3013 pic->pic_num,
3014 pic->buf_spec_num,
3015 pic->data_flag);
3016}
3017
3018static void reset_process_time(struct vdec_h264_hw_s *hw)
3019{
3020 if (hw->start_process_time) {
3021 unsigned process_time =
3022 1000 * (jiffies - hw->start_process_time) / HZ;
3023 hw->start_process_time = 0;
3024 if (process_time > max_process_time[DECODE_ID(hw)])
3025 max_process_time[DECODE_ID(hw)] = process_time;
3026 }
3027}
3028
3029static void start_process_time(struct vdec_h264_hw_s *hw)
3030{
3031 hw->decode_timeout_count = 10;
3032 hw->start_process_time = jiffies;
3033}
3034
3035static void config_aux_buf(struct vdec_h264_hw_s *hw)
3036{
3037 WRITE_VREG(H264_AUX_ADR, hw->aux_phy_addr);
3038 WRITE_VREG(H264_AUX_DATA_SIZE,
3039 ((hw->prefix_aux_size >> 4) << 16) |
3040 (hw->suffix_aux_size >> 4)
3041 );
3042}
3043
3044/*
3045* dv_meta_flag: 1, dolby meta only; 2, not include dolby meta
3046*/
3047static void set_aux_data(struct vdec_h264_hw_s *hw,
3048 struct StorablePicture *pic, unsigned char suffix_flag,
3049 unsigned char dv_meta_flag, struct vdec_h264_hw_s *hw_b)
3050{
3051 int i;
3052 unsigned short *aux_adr;
3053 unsigned size_reg_val =
3054 READ_VREG(H264_AUX_DATA_SIZE);
3055 unsigned aux_count = 0;
3056 int aux_size = 0;
3057 struct vdec_h264_hw_s *hw_buf = hw_b ? hw_b : hw;
3058 if (pic == NULL || pic->buf_spec_num < 0 || pic->buf_spec_num >= BUFSPEC_POOL_SIZE
3059 || (!is_buf_spec_in_use(hw, pic->buf_spec_num)))
3060 return;
3061
3062 if (suffix_flag) {
3063 aux_adr = (unsigned short *)
3064 (hw_buf->aux_addr +
3065 hw_buf->prefix_aux_size);
3066 aux_count =
3067 ((size_reg_val & 0xffff) << 4)
3068 >> 1;
3069 aux_size =
3070 hw_buf->suffix_aux_size;
3071 } else {
3072 aux_adr =
3073 (unsigned short *)hw_buf->aux_addr;
3074 aux_count =
3075 ((size_reg_val >> 16) << 4)
3076 >> 1;
3077 aux_size =
3078 hw_buf->prefix_aux_size;
3079 }
3080 if (dpb_is_debug(DECODE_ID(hw),
3081 PRINT_FLAG_DPB_DETAIL)) {
3082 dpb_print(DECODE_ID(hw), 0,
3083 "%s:old size %d count %d,suf %d dv_flag %d\r\n",
3084 __func__, AUX_DATA_SIZE(pic),
3085 aux_count, suffix_flag, dv_meta_flag);
3086 }
3087 if (aux_size > 0 && aux_count > 0) {
3088 int heads_size = 0;
3089 int new_size;
3090 char *new_buf;
3091 for (i = 0; i < aux_count; i++) {
3092 unsigned char tag = aux_adr[i] >> 8;
3093 if (tag != 0 && tag != 0xff) {
3094 if (dv_meta_flag == 0)
3095 heads_size += 8;
3096 else if (dv_meta_flag == 1 && tag == 0x1)
3097 heads_size += 8;
3098 else if (dv_meta_flag == 2 && tag != 0x1)
3099 heads_size += 8;
3100 }
3101 }
3102 new_size = AUX_DATA_SIZE(pic) + aux_count + heads_size;
3103 new_buf = krealloc(AUX_DATA_BUF(pic),
3104 new_size,
3105 GFP_KERNEL);
3106 if (new_buf) {
3107 unsigned char valid_tag = 0;
3108 unsigned char *h =
3109 new_buf +
3110 AUX_DATA_SIZE(pic);
3111 unsigned char *p = h + 8;
3112 int len = 0;
3113 int padding_len = 0;
3114 AUX_DATA_BUF(pic) = new_buf;
3115 for (i = 0; i < aux_count; i += 4) {
3116 int ii;
3117 unsigned char tag = aux_adr[i + 3] >> 8;
3118 if (tag != 0 && tag != 0xff) {
3119 if (dv_meta_flag == 0)
3120 valid_tag = 1;
3121 else if (dv_meta_flag == 1
3122 && tag == 0x1)
3123 valid_tag = 1;
3124 else if (dv_meta_flag == 2
3125 && tag != 0x1)
3126 valid_tag = 1;
3127 else
3128 valid_tag = 0;
3129 if (valid_tag && len > 0) {
3130 AUX_DATA_SIZE(pic) +=
3131 (len + 8);
3132 h[0] =
3133 (len >> 24) & 0xff;
3134 h[1] =
3135 (len >> 16) & 0xff;
3136 h[2] =
3137 (len >> 8) & 0xff;
3138 h[3] =
3139 (len >> 0) & 0xff;
3140 h[6] =
3141 (padding_len >> 8)
3142 & 0xff;
3143 h[7] =
3144 (padding_len) & 0xff;
3145 h += (len + 8);
3146 p += 8;
3147 len = 0;
3148 padding_len = 0;
3149 }
3150 if (valid_tag) {
3151 h[4] = tag;
3152 h[5] = 0;
3153 h[6] = 0;
3154 h[7] = 0;
3155 }
3156 }
3157 if (valid_tag) {
3158 for (ii = 0; ii < 4; ii++) {
3159 unsigned short aa =
3160 aux_adr[i + 3
3161 - ii];
3162 *p = aa & 0xff;
3163 p++;
3164 len++;
3165 /*if ((aa >> 8) == 0xff)
3166 padding_len++;*/
3167 }
3168 }
3169 }
3170 if (len > 0) {
3171 AUX_DATA_SIZE(pic) += (len + 8);
3172 h[0] = (len >> 24) & 0xff;
3173 h[1] = (len >> 16) & 0xff;
3174 h[2] = (len >> 8) & 0xff;
3175 h[3] = (len >> 0) & 0xff;
3176 h[6] = (padding_len >> 8) & 0xff;
3177 h[7] = (padding_len) & 0xff;
3178 }
3179 if (dpb_is_debug(DECODE_ID(hw),
3180 PRINT_FLAG_DPB_DETAIL)) {
3181 dpb_print(DECODE_ID(hw), 0,
3182 "aux: (size %d) suffix_flag %d\n",
3183 AUX_DATA_SIZE(pic), suffix_flag);
3184 for (i = 0; i < AUX_DATA_SIZE(pic); i++) {
3185 dpb_print_cont(DECODE_ID(hw), 0,
3186 "%02x ", AUX_DATA_BUF(pic)[i]);
3187 if (((i + 1) & 0xf) == 0)
3188 dpb_print_cont(
3189 DECODE_ID(hw),
3190 0, "\n");
3191 }
3192 dpb_print_cont(DECODE_ID(hw),
3193 0, "\n");
3194 }
3195
3196 }
3197 }
3198
3199}
3200
3201static void release_aux_data(struct vdec_h264_hw_s *hw,
3202 int buf_spec_num)
3203{
3204 kfree(hw->buffer_spec[buf_spec_num].aux_data_buf);
3205 hw->buffer_spec[buf_spec_num].aux_data_buf = NULL;
3206 hw->buffer_spec[buf_spec_num].aux_data_size = 0;
3207}
3208
3209static void dump_aux_buf(struct vdec_h264_hw_s *hw)
3210{
3211 int i;
3212 unsigned short *aux_adr =
3213 (unsigned short *)
3214 hw->aux_addr;
3215 unsigned aux_size =
3216 (READ_VREG(H264_AUX_DATA_SIZE)
3217 >> 16) << 4;
3218
3219 if (hw->prefix_aux_size > 0) {
3220 dpb_print(DECODE_ID(hw),
3221 0,
3222 "prefix aux: (size %d)\n",
3223 aux_size);
3224 for (i = 0; i <
3225 (aux_size >> 1); i++) {
3226 dpb_print_cont(DECODE_ID(hw),
3227 0,
3228 "%04x ",
3229 *(aux_adr + i));
3230 if (((i + 1) & 0xf)
3231 == 0)
3232 dpb_print_cont(
3233 DECODE_ID(hw),
3234 0, "\n");
3235 }
3236 }
3237 if (hw->suffix_aux_size > 0) {
3238 aux_adr = (unsigned short *)
3239 (hw->aux_addr +
3240 hw->prefix_aux_size);
3241 aux_size =
3242 (READ_VREG(H264_AUX_DATA_SIZE) & 0xffff)
3243 << 4;
3244 dpb_print(DECODE_ID(hw),
3245 0,
3246 "suffix aux: (size %d)\n",
3247 aux_size);
3248 for (i = 0; i <
3249 (aux_size >> 1); i++) {
3250 dpb_print_cont(DECODE_ID(hw),
3251 0,
3252 "%04x ", *(aux_adr + i));
3253 if (((i + 1) & 0xf) == 0)
3254 dpb_print_cont(DECODE_ID(hw),
3255 0, "\n");
3256 }
3257 }
3258}
3259
3260static void config_decode_mode(struct vdec_h264_hw_s *hw)
3261{
3262#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3263 struct vdec_s *vdec = hw_to_vdec(hw);
3264#endif
3265 if (input_frame_based(hw_to_vdec(hw)))
3266 WRITE_VREG(H264_DECODE_MODE,
3267 DECODE_MODE_MULTI_FRAMEBASE);
3268#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3269 else if (vdec->slave)
3270 WRITE_VREG(H264_DECODE_MODE,
3271 (hw->got_valid_nal << 8) |
3272 DECODE_MODE_MULTI_DVBAL);
3273 else if (vdec->master)
3274 WRITE_VREG(H264_DECODE_MODE,
3275 (hw->got_valid_nal << 8) |
3276 DECODE_MODE_MULTI_DVENL);
3277#endif
3278 else
3279 WRITE_VREG(H264_DECODE_MODE,
3280 DECODE_MODE_MULTI_STREAMBASE);
3281 WRITE_VREG(H264_DECODE_SEQINFO,
3282 hw->seq_info2);
3283 WRITE_VREG(HEAD_PADING_REG, 0);
3284
3285 if (hw->init_flag == 0)
3286 WRITE_VREG(INIT_FLAG_REG, 0);
3287 else
3288 WRITE_VREG(INIT_FLAG_REG, 1);
3289}
3290int config_decode_buf(struct vdec_h264_hw_s *hw, struct StorablePicture *pic)
3291{
3292 /* static int count = 0; */
3293 int ret = 0;
3294 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3295 struct Slice *pSlice = &(p_H264_Dpb->mSlice);
3296 unsigned int colocate_adr_offset;
3297 unsigned int val;
3298 struct StorablePicture *last_pic = hw->last_dec_picture;
3299
3300#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
3301 int colocate_buf_index;
3302#endif
3303#define H264_BUFFER_INFO_INDEX PMV3_X /* 0xc24 */
3304#define H264_BUFFER_INFO_DATA PMV2_X /* 0xc22 */
3305#define H264_CURRENT_POC_IDX_RESET LAST_SLICE_MV_ADDR /* 0xc30 */
3306#define H264_CURRENT_POC LAST_MVY /* 0xc32 shared with conceal MV */
3307
3308#define H264_CO_MB_WR_ADDR VLD_C38 /* 0xc38 */
3309/* bit 31:30 -- L1[0] picture coding structure,
3310 * 00 - top field, 01 - bottom field,
3311 * 10 - frame, 11 - mbaff frame
3312 * bit 29 - L1[0] top/bot for B field pciture , 0 - top, 1 - bot
3313 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3314 * -- only used for B Picture Direct mode [2:0] will set to 3'b000
3315 */
3316#define H264_CO_MB_RD_ADDR VLD_C39 /* 0xc39 */
3317
3318/* bit 15 -- flush co_mb_data to DDR -- W-Only
3319 * bit 14 -- h264_co_mb_mem_wr_addr write Enable -- W-Only
3320 * bit 13 -- h264_co_mb_info_wr_ptr write Enable -- W-Only
3321 * bit 9 -- soft_reset -- W-Only
3322 * bit 8 -- upgent
3323 * bit 7:2 -- h264_co_mb_mem_wr_addr
3324 * bit 1:0 -- h264_co_mb_info_wr_ptr
3325 */
3326#define H264_CO_MB_RW_CTL VLD_C3D /* 0xc3d */
3327#define DCAC_DDR_BYTE64_CTL 0x0e1d
3328 unsigned long canvas_adr;
3329 unsigned int ref_reg_val;
3330 unsigned int one_ref_cfg = 0;
3331 int h264_buffer_info_data_write_count;
3332 int i, j;
3333 unsigned int colocate_wr_adr;
3334 unsigned int colocate_rd_adr;
3335 unsigned char use_direct_8x8;
3336 int canvas_pos;
3337 canvas_pos = hw->buffer_spec[pic->buf_spec_num].canvas_pos;
3338 WRITE_VREG(H264_CURRENT_POC_IDX_RESET, 0);
3339 WRITE_VREG(H264_CURRENT_POC, pic->frame_poc);
3340 WRITE_VREG(H264_CURRENT_POC, pic->top_poc);
3341 WRITE_VREG(H264_CURRENT_POC, pic->bottom_poc);
3342
3343 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3344 "%s: pic_num is %d, poc is %d (%d, %d, %d), buf_spec_num %d canvas_pos %d\n",
3345 __func__, pic->pic_num, pic->poc, pic->frame_poc,
3346 pic->top_poc, pic->bottom_poc, pic->buf_spec_num,
3347 canvas_pos);
3348 print_pic_info(DECODE_ID(hw), "cur", pic, pSlice->slice_type);
3349
3350#ifdef VDEC_DW
3351 if (IS_VDEC_DW(hw) && pic->mb_aff_frame_flag)
3352 WRITE_VREG(MDEC_DOUBLEW_CFG0,
3353 ( READ_VREG(MDEC_DOUBLEW_CFG0) & (~(1 << 30))));
3354#endif
3355 WRITE_VREG(CURR_CANVAS_CTRL, canvas_pos << 24);
3356 canvas_adr = READ_VREG(CURR_CANVAS_CTRL) & 0xffffff;
3357
3358 if (!hw->mmu_enable) {
3359 WRITE_VREG(REC_CANVAS_ADDR, canvas_adr);
3360 WRITE_VREG(DBKR_CANVAS_ADDR, canvas_adr);
3361 WRITE_VREG(DBKW_CANVAS_ADDR, canvas_adr);
3362#ifdef VDEC_DW
3363 WRITE_VREG(MDEC_DOUBLEW_CFG1,
3364 (hw->buffer_spec[canvas_pos].vdec_dw_y_canvas_index
3365 | (hw->buffer_spec[canvas_pos].vdec_dw_u_canvas_index << 8)));
3366#endif
3367 } else
3368 hevc_sao_set_pic_buffer(hw, pic);
3369
3370 if (pic->mb_aff_frame_flag)
3371 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf4c0;
3372 else if (pic->structure == TOP_FIELD)
3373 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf400;
3374 else if (pic->structure == BOTTOM_FIELD)
3375 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf440;
3376 else
3377 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf480;
3378
3379 if (pic->bottom_poc < pic->top_poc)
3380 hw->buffer_spec[pic->buf_spec_num].info0 |= 0x100;
3381
3382 hw->buffer_spec[pic->buf_spec_num].info1 = pic->top_poc;
3383 hw->buffer_spec[pic->buf_spec_num].info2 = pic->bottom_poc;
3384 WRITE_VREG(H264_BUFFER_INFO_INDEX, 16);
3385
3386 for (j = 0; j < hw->dpb.mDPB.size; j++) {
3387 int long_term_flag;
3388 i = get_buf_spec_by_canvas_pos(hw, j);
3389 if (i < 0)
3390 break;
3391 long_term_flag =
3392 get_long_term_flag_by_buf_spec_num(p_H264_Dpb, i);
3393 if (long_term_flag > 0) {
3394 if (long_term_flag & 0x1)
3395 hw->buffer_spec[i].info0 |= (1 << 4);
3396 else
3397 hw->buffer_spec[i].info0 &= ~(1 << 4);
3398
3399 if (long_term_flag & 0x2)
3400 hw->buffer_spec[i].info0 |= (1 << 5);
3401 else
3402 hw->buffer_spec[i].info0 &= ~(1 << 5);
3403 }
3404
3405 if (i == pic->buf_spec_num)
3406 WRITE_VREG(H264_BUFFER_INFO_DATA,
3407 hw->buffer_spec[i].info0 | 0xf);
3408 else
3409 WRITE_VREG(H264_BUFFER_INFO_DATA,
3410 hw->buffer_spec[i].info0);
3411 WRITE_VREG(H264_BUFFER_INFO_DATA, hw->buffer_spec[i].info1);
3412 WRITE_VREG(H264_BUFFER_INFO_DATA, hw->buffer_spec[i].info2);
3413 }
3414
3415 /* config reference buffer */
3416 if (hw->mmu_enable) {
3417 hevc_mcr_config_mc_ref(hw);
3418 hevc_mcr_config_mcrcc(hw);
3419 }
3420
3421 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3422 "list0 size %d\n", pSlice->listXsize[0]);
3423 WRITE_VREG(H264_BUFFER_INFO_INDEX, 0);
3424 ref_reg_val = 0;
3425 j = 0;
3426 h264_buffer_info_data_write_count = 0;
3427
3428 //disable this read cache when frame width <= 64 (4MBs)
3429 //IQIDCT_CONTROL, bit[16] dcac_dma_read_cache_disable
3430 if (hw->frame_width <= 64) {
3431 SET_VREG_MASK(IQIDCT_CONTROL,(1 << 16));
3432 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A))
3433 // Disable DDR_BYTE64_CACHE
3434 WRITE_VREG(DCAC_DDR_BYTE64_CTL,
3435 (READ_VREG(DCAC_DDR_BYTE64_CTL) & (~0xf)) | 0xa);
3436 }
3437 else
3438 CLEAR_VREG_MASK(IQIDCT_CONTROL,(1 << 16));
3439
3440 if (last_pic)
3441 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
3442 "last_pic->data_flag %x slice_type %x last_pic->slice_type %x\n",
3443 last_pic->data_flag, pSlice->slice_type, last_pic->slice_type);
3444 if (!hw->i_only && !(error_proc_policy & 0x2000) &&
3445 last_pic && (last_pic->data_flag & ERROR_FLAG)
3446 && (!(last_pic->slice_type == B_SLICE))
3447 && (!(pSlice->slice_type == I_SLICE))) {
3448 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
3449 "no i/idr error mark\n");
3450 hw->data_flag |= ERROR_FLAG;
3451 pic->data_flag |= ERROR_FLAG;
3452 }
3453
3454 for (i = 0; i < (unsigned int)(pSlice->listXsize[0]); i++) {
3455 /*ref list 0 */
3456 struct StorablePicture *ref = pSlice->listX[0][i];
3457 unsigned int cfg;
3458 /* bit[6:5] - frame/field info,
3459 * 01 - top, 10 - bottom, 11 - frame
3460 */
3461 #ifdef ERROR_CHECK
3462 if (ref == NULL) {
3463 hw->data_flag |= ERROR_FLAG;
3464 pic->data_flag |= ERROR_FLAG;
3465 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref list0 NULL\n");
3466 return -1;
3467 }
3468 if ((ref->data_flag & ERROR_FLAG) && ref_frame_mark_flag[DECODE_ID(hw)]) {
3469 hw->data_flag |= ERROR_FLAG;
3470 pic->data_flag |= ERROR_FLAG;
3471 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error mark1 \n");
3472 }
3473
3474 if (error_proc_policy & 0x80000) {
3475 if (ref_b_frame_error_max_count &&
3476 ref->slice_type == B_SLICE) {
3477 if (ref->data_flag & ERROR_FLAG)
3478 hw->b_frame_error_count++;
3479 else
3480 hw->b_frame_error_count = 0;
3481 if (hw->b_frame_error_count > ref_b_frame_error_max_count) {
3482 hw->b_frame_error_count = 0;
3483 dpb_print(DECODE_ID(hw), 0,
3484 "error %d B frame, reset dpb buffer\n",
3485 ref_b_frame_error_max_count);
3486 return -1;
3487 }
3488 }
3489 }
3490
3491 if (ref->data_flag & NULL_FLAG)
3492 hw->data_flag |= NULL_FLAG;
3493#endif
3494 canvas_pos = hw->buffer_spec[ref->buf_spec_num].canvas_pos;
3495
3496 if (ref->structure == TOP_FIELD)
3497 cfg = 0x1;
3498 else if (ref->structure == BOTTOM_FIELD)
3499 cfg = 0x2;
3500 else /* FRAME */
3501 cfg = 0x3;
3502
3503 one_ref_cfg = (canvas_pos & 0x1f) | (cfg << 5);
3504 ref_reg_val <<= 8;
3505 ref_reg_val |= one_ref_cfg;
3506 j++;
3507
3508 if (j == 4) {
3509 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3510 "H264_BUFFER_INFO_DATA: %x\n", ref_reg_val);
3511 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3512 h264_buffer_info_data_write_count++;
3513 j = 0;
3514 }
3515 print_pic_info(DECODE_ID(hw), "list0",
3516 pSlice->listX[0][i], -1);
3517 }
3518 if (j != 0) {
3519 while (j != 4) {
3520 ref_reg_val <<= 8;
3521 ref_reg_val |= one_ref_cfg;
3522 j++;
3523 }
3524 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3525 "H264_BUFFER_INFO_DATA: %x\n",
3526 ref_reg_val);
3527 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3528 h264_buffer_info_data_write_count++;
3529 }
3530 ref_reg_val = (one_ref_cfg << 24) | (one_ref_cfg<<16) |
3531 (one_ref_cfg << 8) | one_ref_cfg;
3532 for (i = h264_buffer_info_data_write_count; i < 8; i++)
3533 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3534
3535 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3536 "list1 size %d\n", pSlice->listXsize[1]);
3537 WRITE_VREG(H264_BUFFER_INFO_INDEX, 8);
3538 ref_reg_val = 0;
3539 j = 0;
3540
3541 for (i = 0; i < (unsigned int)(pSlice->listXsize[1]); i++) {
3542 /* ref list 0 */
3543 struct StorablePicture *ref = pSlice->listX[1][i];
3544 unsigned int cfg;
3545 /* bit[6:5] - frame/field info,
3546 * 01 - top, 10 - bottom, 11 - frame
3547 */
3548
3549 #ifdef ERROR_CHECK
3550 if (ref == NULL) {
3551 hw->data_flag |= ERROR_FLAG;
3552 pic->data_flag |= ERROR_FLAG;
3553 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error list1 NULL\n");
3554 return -2;
3555 }
3556 if ((ref->data_flag & ERROR_FLAG) && (ref_frame_mark_flag[DECODE_ID(hw)])) {
3557 pic->data_flag |= ERROR_FLAG;
3558 hw->data_flag |= ERROR_FLAG;
3559 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error mark2\n");
3560 }
3561 if (ref->data_flag & NULL_FLAG)
3562 hw->data_flag |= NULL_FLAG;
3563#endif
3564 canvas_pos = hw->buffer_spec[ref->buf_spec_num].canvas_pos;
3565 if (ref->structure == TOP_FIELD)
3566 cfg = 0x1;
3567 else if (ref->structure == BOTTOM_FIELD)
3568 cfg = 0x2;
3569 else /* FRAME */
3570 cfg = 0x3;
3571 one_ref_cfg = (canvas_pos & 0x1f) | (cfg << 5);
3572 ref_reg_val <<= 8;
3573 ref_reg_val |= one_ref_cfg;
3574 j++;
3575
3576 if (j == 4) {
3577 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3578 "H264_BUFFER_INFO_DATA: %x\n",
3579 ref_reg_val);
3580 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3581 j = 0;
3582 }
3583 print_pic_info(DECODE_ID(hw), "list1",
3584 pSlice->listX[1][i], -1);
3585 }
3586 if (j != 0) {
3587 while (j != 4) {
3588 ref_reg_val <<= 8;
3589 ref_reg_val |= one_ref_cfg;
3590 j++;
3591 }
3592 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3593 "H264_BUFFER_INFO_DATA: %x\n", ref_reg_val);
3594 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3595 }
3596
3597 /* configure co-locate buffer */
3598 while ((READ_VREG(H264_CO_MB_RW_CTL) >> 11) & 0x1)
3599 ;
3600 if ((pSlice->mode_8x8_flags & 0x4) &&
3601 (pSlice->mode_8x8_flags & 0x2))
3602 use_direct_8x8 = 1;
3603 else
3604 use_direct_8x8 = 0;
3605
3606#ifndef ONE_COLOCATE_BUF_PER_DECODE_BUF
3607 colocate_adr_offset =
3608 ((pic->structure == FRAME && pic->mb_aff_frame_flag == 0)
3609 ? 1 : 2) * 96;
3610 if (use_direct_8x8)
3611 colocate_adr_offset >>= 2;
3612
3613 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3614 "colocate buf size of each mb 0x%x first_mb_in_slice 0x%x colocate_adr_offset 0x%x\r\n",
3615 colocate_adr_offset, pSlice->first_mb_in_slice,
3616 colocate_adr_offset * pSlice->first_mb_in_slice);
3617
3618 colocate_adr_offset *= pSlice->first_mb_in_slice;
3619
3620 if ((pic->colocated_buf_index >= 0) &&
3621 (pic->colocated_buf_index < p_H264_Dpb->colocated_buf_count)) {
3622 colocate_wr_adr = p_H264_Dpb->colocated_mv_addr_start +
3623 ((p_H264_Dpb->colocated_buf_size *
3624 pic->colocated_buf_index)
3625 >> (use_direct_8x8 ? 2 : 0));
3626 if ((colocate_wr_adr + p_H264_Dpb->colocated_buf_size) >
3627 p_H264_Dpb->colocated_mv_addr_end) {
3628 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3629 "Error, colocate buf is not enough, index is %d\n",
3630 pic->colocated_buf_index);
3631 ret = -3;
3632 }
3633 val = colocate_wr_adr + colocate_adr_offset;
3634 WRITE_VREG(H264_CO_MB_WR_ADDR, val);
3635 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3636 "WRITE_VREG(H264_CO_MB_WR_ADDR) = %x, first_mb_in_slice %x pic_structure %x colocate_adr_offset %x mode_8x8_flags %x colocated_buf_size %x\n",
3637 val, pSlice->first_mb_in_slice, pic->structure,
3638 colocate_adr_offset, pSlice->mode_8x8_flags,
3639 p_H264_Dpb->colocated_buf_size);
3640 } else {
3641 WRITE_VREG(H264_CO_MB_WR_ADDR, 0xffffffff);
3642 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3643 "WRITE_VREG(H264_CO_MB_WR_ADDR) = 0xffffffff\n");
3644 }
3645#else
3646 colocate_buf_index = hw->buffer_spec[pic->buf_spec_num].canvas_pos;
3647 colocate_adr_offset =
3648 ((pic->structure == FRAME && pic->mb_aff_frame_flag == 0) ? 1 : 2) * 96;
3649 if (use_direct_8x8)
3650 colocate_adr_offset >>= 2;
3651
3652 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3653 "colocate buf size of each mb 0x%x first_mb_in_slice 0x%x colocate_adr_offset 0x%x\r\n",
3654 colocate_adr_offset, pSlice->first_mb_in_slice,
3655 colocate_adr_offset * pSlice->first_mb_in_slice);
3656
3657 colocate_adr_offset *= pSlice->first_mb_in_slice;
3658
3659 colocate_wr_adr = p_H264_Dpb->colocated_mv_addr_start +
3660 ((p_H264_Dpb->colocated_buf_size * colocate_buf_index) >>
3661 (use_direct_8x8 ? 2 : 0));
3662
3663 if ((colocate_wr_adr + p_H264_Dpb->colocated_buf_size) >
3664 p_H264_Dpb->colocated_mv_addr_end) {
3665 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3666 "Error, colocate buf is not enough, col buf index is %d\n",
3667 colocate_buf_index);
3668 ret = -4;
3669 }
3670 val = colocate_wr_adr + colocate_adr_offset;
3671 WRITE_VREG(H264_CO_MB_WR_ADDR, val);
3672 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3673 "WRITE_VREG(H264_CO_MB_WR_ADDR) = %x, first_mb_in_slice %x pic_structure %x colocate_adr_offset %x mode_8x8_flags %x colocated_buf_size %x\n",
3674 val, pSlice->first_mb_in_slice, pic->structure,
3675 colocate_adr_offset, pSlice->mode_8x8_flags,
3676 p_H264_Dpb->colocated_buf_size);
3677#endif
3678 if (pSlice->listXsize[1] > 0) {
3679 struct StorablePicture *colocate_pic = pSlice->listX[1][0];
3680 /* H264_CO_MB_RD_ADDR[bit 31:30],
3681 * original picture structure of L1[0],
3682 * 00 - top field, 01 - bottom field,
3683 * 10 - frame, 11 - mbaff frame
3684 */
3685 int l10_structure;
3686 int cur_colocate_ref_type;
3687 /* H264_CO_MB_RD_ADDR[bit 29], top/bot for B field pciture,
3688 * 0 - top, 1 - bot
3689 */
3690 unsigned int val;
3691#ifdef ERROR_CHECK
3692 if (colocate_pic == NULL) {
3693 hw->data_flag |= ERROR_FLAG;
3694 pic->data_flag |= ERROR_FLAG;
3695 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " colocate error pic NULL\n");
3696 return -5;
3697 }
3698 if (colocate_pic->data_flag & ERROR_FLAG) {
3699 pic->data_flag |= ERROR_FLAG;
3700 hw->data_flag |= ERROR_FLAG;
3701 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " colocare ref error mark\n");
3702 }
3703 if (colocate_pic->data_flag & NULL_FLAG)
3704 hw->data_flag |= NULL_FLAG;
3705#endif
3706
3707 if (colocate_pic->mb_aff_frame_flag)
3708 l10_structure = 3;
3709 else {
3710 if (colocate_pic->coded_frame)
3711 l10_structure = 2;
3712 else
3713 l10_structure = (colocate_pic->structure ==
3714 BOTTOM_FIELD) ? 1 : 0;
3715 }
3716#if 0
3717 /*case0016, p16,
3718 *cur_colocate_ref_type should be configured base on current pic
3719 */
3720 if (pic->structure == FRAME &&
3721 pic->mb_aff_frame_flag)
3722 cur_colocate_ref_type = 0;
3723 else if (pic->structure == BOTTOM_FIELD)
3724 cur_colocate_ref_type = 1;
3725 else
3726 cur_colocate_ref_type = 0;
3727#else
3728 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3729 " CUR TMP DEBUG : mb_aff_frame_flag : %d, structure : %d coded_frame %d\n",
3730 pic->mb_aff_frame_flag,
3731 pic->structure,
3732 pic->coded_frame);
3733 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3734 " COL TMP DEBUG : mb_aff_frame_flag : %d, structure : %d coded_frame %d\n",
3735 colocate_pic->mb_aff_frame_flag,
3736 colocate_pic->structure,
3737 colocate_pic->coded_frame);
3738 if (pic->structure == FRAME || pic->mb_aff_frame_flag) {
3739 cur_colocate_ref_type =
3740 (abs(pic->poc - colocate_pic->top_poc)
3741 < abs(pic->poc -
3742 colocate_pic->bottom_poc)) ? 0 : 1;
3743 } else
3744 cur_colocate_ref_type =
3745 (colocate_pic->structure
3746 == BOTTOM_FIELD) ? 1 : 0;
3747#endif
3748
3749#ifndef ONE_COLOCATE_BUF_PER_DECODE_BUF
3750 if ((colocate_pic->colocated_buf_index >= 0) &&
3751 (colocate_pic->colocated_buf_index <
3752 p_H264_Dpb->colocated_buf_count)) {
3753 colocate_rd_adr = p_H264_Dpb->colocated_mv_addr_start +
3754 ((p_H264_Dpb->colocated_buf_size *
3755 colocate_pic->colocated_buf_index)
3756 >> (use_direct_8x8 ? 2 : 0));
3757 if ((colocate_rd_adr + p_H264_Dpb->colocated_buf_size) >
3758 p_H264_Dpb->colocated_mv_addr_end) {
3759 dpb_print(DECODE_ID(hw),
3760 PRINT_FLAG_ERROR,
3761 "Error, colocate buf is not enough, index is %d\n",
3762 colocate_pic->colocated_buf_index);
3763 ret = -6;
3764 }
3765 /* bit 31:30 -- L1[0] picture coding structure,
3766 * 00 - top field, 01 - bottom field,
3767 * 10 - frame, 11 - mbaff frame
3768 * bit 29 - L1[0] top/bot for B field pciture,
3769 * 0 - top, 1 - bot
3770 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3771 * -- only used for B Picture Direct mode
3772 * [2:0] will set to 3'b000
3773 */
3774 /* #define H264_CO_MB_RD_ADDR VLD_C39 0xc39 */
3775 val = ((colocate_rd_adr+colocate_adr_offset) >> 3) |
3776 (l10_structure << 30) |
3777 (cur_colocate_ref_type << 29);
3778 WRITE_VREG(H264_CO_MB_RD_ADDR, val);
3779 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3780 "co idx %d, WRITE_VREG(H264_CO_MB_RD_ADDR) = %x, addr %x L1(0) pic_structure %d mbaff %d\n",
3781 colocate_pic->colocated_buf_index,
3782 val, colocate_rd_adr + colocate_adr_offset,
3783 colocate_pic->structure,
3784 colocate_pic->mb_aff_frame_flag);
3785 } else {
3786 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3787 "Error, reference pic has no colocated buf\n");
3788 ret = -7;
3789 }
3790#else
3791 colocate_buf_index =
3792 hw->buffer_spec[colocate_pic->buf_spec_num].canvas_pos;
3793 colocate_rd_adr = p_H264_Dpb->colocated_mv_addr_start +
3794 ((p_H264_Dpb->colocated_buf_size *
3795 colocate_buf_index)
3796 >> (use_direct_8x8 ? 2 : 0));
3797 if ((colocate_rd_adr + p_H264_Dpb->colocated_buf_size) >
3798 p_H264_Dpb->colocated_mv_addr_end) {
3799 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3800 "Error, colocate buf is not enough, col buf index is %d\n",
3801 colocate_buf_index);
3802 ret = -8;
3803 }
3804 /* bit 31:30 -- L1[0] picture coding structure,
3805 * 00 - top field, 01 - bottom field,
3806 * 10 - frame, 11 - mbaff frame
3807 * bit 29 - L1[0] top/bot for B field pciture,
3808 * 0 - top, 1 - bot
3809 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3810 * -- only used for B Picture Direct mode
3811 * [2:0] will set to 3'b000
3812 */
3813 /* #define H264_CO_MB_RD_ADDR VLD_C39 0xc39 */
3814 val = ((colocate_rd_adr+colocate_adr_offset)>>3) |
3815 (l10_structure << 30) | (cur_colocate_ref_type << 29);
3816 WRITE_VREG(H264_CO_MB_RD_ADDR, val);
3817 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3818 "WRITE_VREG(H264_CO_MB_RD_ADDR) = %x, L1(0) pic_structure %d mbaff %d\n",
3819 val, colocate_pic->structure,
3820 colocate_pic->mb_aff_frame_flag);
3821#endif
3822 }
3823 return ret;
3824}
3825
3826static int vh264_vf_states(struct vframe_states *states, void *op_arg)
3827{
3828 unsigned long flags;
3829 struct vdec_s *vdec = op_arg;
3830 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3831
3832 spin_lock_irqsave(&hw->lock, flags);
3833
3834 states->vf_pool_size = VF_POOL_SIZE;
3835 states->buf_free_num = kfifo_len(&hw->newframe_q);
3836 states->buf_avail_num = kfifo_len(&hw->display_q);
3837
3838 spin_unlock_irqrestore(&hw->lock, flags);
3839
3840 return 0;
3841}
3842
3843static struct vframe_s *vh264_vf_peek(void *op_arg)
3844{
3845 struct vframe_s *vf[2] = {0, 0};
3846 struct vdec_s *vdec = op_arg;
3847 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3848
3849 if (!hw)
3850 return NULL;
3851
3852 if (force_disp_bufspec_num & 0x100) {
3853 if (force_disp_bufspec_num & 0x200)
3854 return NULL;
3855 return &hw->vframe_dummy;
3856 }
3857
3858 if (kfifo_out_peek(&hw->display_q, (void *)&vf, 2)) {
3859 if (vf[1]) {
3860 vf[0]->next_vf_pts_valid = true;
3861 vf[0]->next_vf_pts = vf[1]->pts;
3862 } else
3863 vf[0]->next_vf_pts_valid = false;
3864 return vf[0];
3865 }
3866
3867 return NULL;
3868}
3869
3870static struct vframe_s *vh264_vf_get(void *op_arg)
3871{
3872 struct vframe_s *vf;
3873 struct vdec_s *vdec = op_arg;
3874 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3875 struct aml_vcodec_ctx * v4l2_ctx = hw->v4l2_ctx;
3876 ulong nv_order = VIDTYPE_VIU_NV21;
3877
3878 if (!hw)
3879 return NULL;
3880
3881 /* swap uv */
3882 if (hw->is_used_v4l) {
3883 if ((v4l2_ctx->cap_pix_fmt == V4L2_PIX_FMT_NV12) ||
3884 (v4l2_ctx->cap_pix_fmt == V4L2_PIX_FMT_NV12M))
3885 nv_order = VIDTYPE_VIU_NV12;
3886 }
3887
3888 if (force_disp_bufspec_num & 0x100) {
3889 int buffer_index = force_disp_bufspec_num & 0xff;
3890 if (force_disp_bufspec_num & 0x200)
3891 return NULL;
3892
3893 vf = &hw->vframe_dummy;
3894 vf->duration_pulldown = 0;
3895 vf->pts = 0;
3896 vf->pts_us64 = 0;
3897 set_frame_info(hw, vf, buffer_index);
3898 vf->flag = 0;
3899 if (hw->mmu_enable) {
3900 if (hw->double_write_mode & 0x10) {
3901 /* double write only */
3902 vf->compBodyAddr = 0;
3903 vf->compHeadAddr = 0;
3904 } else {
3905 /*head adr*/
3906 vf->compHeadAddr =
3907 hw->buffer_spec[buffer_index].alloc_header_addr;
3908 /*body adr*/
3909 vf->compBodyAddr = 0;
3910 vf->canvas0Addr = vf->canvas1Addr = 0;
3911 }
3912
3913 vf->type = VIDTYPE_SCATTER;
3914
3915 if (hw->double_write_mode) {
3916 vf->type |= VIDTYPE_PROGRESSIVE
3917 | VIDTYPE_VIU_FIELD;
3918 vf->type |= nv_order;
3919 if (hw->double_write_mode == 3)
3920 vf->type |= VIDTYPE_COMPRESS;
3921
3922 vf->canvas0Addr = vf->canvas1Addr = -1;
3923 vf->plane_num = 2;
3924 vf->canvas0_config[0] =
3925 hw->buffer_spec[buffer_index].
3926 canvas_config[0];
3927 vf->canvas0_config[1] =
3928 hw->buffer_spec[buffer_index].
3929 canvas_config[1];
3930
3931 vf->canvas1_config[0] =
3932 hw->buffer_spec[buffer_index].
3933 canvas_config[0];
3934 vf->canvas1_config[1] =
3935 hw->buffer_spec[buffer_index].
3936 canvas_config[1];
3937 } else {
3938 vf->type |=
3939 VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
3940 vf->canvas0Addr = vf->canvas1Addr = 0;
3941 }
3942 vf->bitdepth =
3943 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
3944
3945 vf->compWidth = hw->frame_width;
3946 vf->compHeight = hw->frame_height;
3947
3948 if (hw->double_write_mode) {
3949 vf->width = hw->frame_width /
3950 get_double_write_ratio(hw);
3951 vf->height = hw->frame_height /
3952 get_double_write_ratio(hw);
3953 }
3954 } else {
3955 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD |
3956 nv_order;
3957 vf->canvas0Addr = vf->canvas1Addr =
3958 spec2canvas(&hw->buffer_spec[buffer_index]);
3959 }
3960
3961 /*vf->mem_handle = decoder_bmmu_box_get_mem_handle(
3962 hw->bmmu_box, buffer_index);*/
3963 update_vf_memhandle(hw, vf, buffer_index);
3964 force_disp_bufspec_num |= 0x200;
3965 return vf;
3966 }
3967
3968 if (kfifo_get(&hw->display_q, &vf)) {
3969 int time = jiffies;
3970 unsigned int frame_interval =
3971 1000*(time - hw->last_frame_time)/HZ;
3972 struct vframe_s *next_vf;
3973 if (dpb_is_debug(DECODE_ID(hw),
3974 PRINT_FLAG_VDEC_DETAIL)) {
3975 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3976 int frame_index = FRAME_INDEX(vf->index);
3977 if (frame_index < 0 ||
3978 frame_index >= DPB_SIZE_MAX) {
3979 dpb_print(DECODE_ID(hw), 0,
3980 "%s vf index 0x%x error\r\n",
3981 __func__, vf->index);
3982 } else {
3983 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
3984 "%s buf_spec_num %d vf %p poc %d dur %d pts %d interval %dms\n",
3985 __func__, BUFSPEC_INDEX(vf->index), vf,
3986 p_H264_Dpb->mFrameStore[frame_index].poc,
3987 vf->duration, vf->pts, frame_interval);
3988 }
3989 }
3990 if (hw->last_frame_time > 0) {
3991 if (frame_interval >
3992 max_get_frame_interval[DECODE_ID(hw)])
3993 max_get_frame_interval[DECODE_ID(hw)]
3994 = frame_interval;
3995 }
3996 hw->last_frame_time = time;
3997 vf->index_disp = hw->vf_get_count;
3998 hw->vf_get_count++;
3999 if (kfifo_peek(&hw->display_q, &next_vf)) {
4000 vf->next_vf_pts_valid = true;
4001 vf->next_vf_pts = next_vf->pts;
4002 } else
4003 vf->next_vf_pts_valid = false;
4004 return vf;
4005 }
4006
4007 return NULL;
4008}
4009
4010static bool vf_valid_check(struct vframe_s *vf, struct vdec_h264_hw_s *hw) {
4011 int i,j;
4012 if (hw->is_used_v4l)
4013 return true;
4014 for (i = 0; i < VF_POOL_SIZE; i++) {
4015 for (j = 0; j < VF_POOL_NUM; j ++) {
4016 if (vf == &(hw->vfpool[j][i]))
4017 return true;
4018 }
4019 }
4020 dpb_print(DECODE_ID(hw), 0, " invalid vf been put, vf = %p\n", vf);
4021 for (i = 0; i < VF_POOL_SIZE; i++) {
4022 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
4023 "dump vf [%d]= %p\n", i, &(hw->vfpool[hw->cur_pool][i]));
4024 }
4025 return false;
4026}
4027
4028static void vh264_vf_put(struct vframe_s *vf, void *op_arg)
4029{
4030 struct vdec_s *vdec = op_arg;
4031 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
4032 unsigned long flags;
4033 int buf_spec_num;
4034 int frame_index;
4035
4036 if (vf == (&hw->vframe_dummy))
4037 return;
4038 if (vf->index == -1) {
4039 dpb_print(DECODE_ID(hw), 0,
4040 "Warning: %s vf %p invalid index\r\n",
4041 __func__, vf);
4042 return;
4043 }
4044 frame_index = FRAME_INDEX(vf->index);
4045 buf_spec_num = BUFSPEC_INDEX(vf->index);
4046 if (frame_index < 0 ||
4047 frame_index >= DPB_SIZE_MAX ||
4048 buf_spec_num < 0 ||
4049 buf_spec_num >= BUFSPEC_POOL_SIZE) {
4050 dpb_print(DECODE_ID(hw), 0,
4051 "%s vf index 0x%x error\r\n",
4052 __func__, vf->index);
4053 return;
4054 }
4055 /*get_buf_spec_idx_by_canvas_config(hw,
4056 &vf->canvas0_config[0]);*/
4057 spin_lock_irqsave(&hw->bufspec_lock, flags);
4058 if (hw->buffer_spec[buf_spec_num].used == 2) {
4059 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4060 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
4061 "%s %p to fs[%d], poc %d buf_spec_num %d used %d vf_ref %d\n",
4062 __func__, vf, frame_index,
4063 p_H264_Dpb->mFrameStore[frame_index].poc,
4064 buf_spec_num,
4065 hw->buffer_spec[buf_spec_num].used,
4066 hw->buffer_spec[buf_spec_num].vf_ref);
4067 hw->buffer_spec[buf_spec_num].vf_ref--;
4068 if (hw->buffer_spec[buf_spec_num].vf_ref <= 0)
4069 set_frame_output_flag(&hw->dpb, frame_index);
4070 } else {
4071 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
4072 "%s %p isolated vf, buf_spec_num %d used %d vf_ref %d\n",
4073 __func__, vf, buf_spec_num,
4074 hw->buffer_spec[buf_spec_num].used,
4075 hw->buffer_spec[buf_spec_num].vf_ref);
4076 hw->buffer_spec[buf_spec_num].vf_ref--;
4077 if (hw->buffer_spec[buf_spec_num].vf_ref <= 0) {
4078 if (hw->buffer_spec[buf_spec_num].used == 3)
4079 hw->buffer_spec[buf_spec_num].used = 4;
4080 else if (hw->buffer_spec[buf_spec_num].used == 5)
4081 hw->buffer_spec[buf_spec_num].used = 0;
4082 }
4083 if (dpb_is_debug(DECODE_ID(hw),
4084 PRINT_FLAG_DUMP_BUFSPEC))
4085 dump_bufspec(hw, __func__);
4086
4087 }
4088 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
4089
4090 hw->vf_put_count++;
4091 if (vf && (vf_valid_check(vf, hw) == true))
4092 kfifo_put(&hw->newframe_q, (const struct vframe_s *)vf);
4093
4094#define ASSIST_MBOX1_IRQ_REG VDEC_ASSIST_MBOX1_IRQ_REG
4095 if (hw->buffer_empty_flag)
4096 WRITE_VREG(ASSIST_MBOX1_IRQ_REG, 0x1);
4097}
4098
4099static int vh264_event_cb(int type, void *data, void *op_arg)
4100{
4101 unsigned long flags;
4102 struct vdec_s *vdec = op_arg;
4103 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
4104
4105 if (type & VFRAME_EVENT_RECEIVER_GET_AUX_DATA) {
4106 struct provider_aux_req_s *req =
4107 (struct provider_aux_req_s *)data;
4108 int buf_spec_num;
4109
4110 if (!req->vf) {
4111 req->aux_size = hw->vf_put_count;
4112 return 0;
4113 }
4114 buf_spec_num = BUFSPEC_INDEX(req->vf->index);
4115 spin_lock_irqsave(&hw->lock, flags);
4116 req->aux_buf = NULL;
4117 req->aux_size = 0;
4118 if (buf_spec_num >= 0 &&
4119 buf_spec_num < BUFSPEC_POOL_SIZE &&
4120 is_buf_spec_in_disp_q(hw, buf_spec_num)
4121 ) {
4122 req->aux_buf =
4123 hw->buffer_spec[buf_spec_num].aux_data_buf;
4124 req->aux_size =
4125 hw->buffer_spec[buf_spec_num].aux_data_size;
4126#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
4127 req->dv_enhance_exist =
4128 hw->buffer_spec[buf_spec_num].dv_enhance_exist;
4129#else
4130 req->dv_enhance_exist = 0;
4131#endif
4132 }
4133 spin_unlock_irqrestore(&hw->lock, flags);
4134
4135 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
4136 "%s(type 0x%x vf buf_spec_num 0x%x)=>size 0x%x\n",
4137 __func__, type, buf_spec_num, req->aux_size);
4138 }
4139
4140 return 0;
4141}
4142
4143static void set_frame_info(struct vdec_h264_hw_s *hw, struct vframe_s *vf,
4144 u32 index)
4145{
4146 struct canvas_config_s *p_canvas_config;
4147 int force_rate = input_frame_based(hw_to_vdec(hw)) ?
4148 force_rate_framebase : force_rate_streambase;
4149 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
4150 "%s (%d,%d) dur %d, vf %p, index %d\n", __func__,
4151 hw->frame_width, hw->frame_height, hw->frame_dur, vf, index);
4152
4153 /* signal_type */
4154 if (hw->video_signal_from_vui & VIDEO_SIGNAL_TYPE_AVAILABLE_MASK) {
4155 vf->signal_type = hw->video_signal_from_vui;
4156 if (hw->is_used_v4l) {
4157 struct aml_vdec_hdr_infos hdr;
4158 struct aml_vcodec_ctx *ctx =
4159 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
4160
4161 memset(&hdr, 0, sizeof(hdr));
4162 hdr.signal_type = hw->video_signal_from_vui;
4163 vdec_v4l_set_hdr_infos(ctx, &hdr);
4164 }
4165 } else
4166 vf->signal_type = 0;
4167
4168 vf->width = hw->frame_width;
4169 vf->height = hw->frame_height;
4170 if (force_rate) {
4171 if (force_rate == -1)
4172 vf->duration = 0;
4173 else
4174 vf->duration = 96000/force_rate;
4175 } else
4176 vf->duration = hw->frame_dur;
4177 vf->ratio_control =
4178 (min(hw->h264_ar, (u32) DISP_RATIO_ASPECT_RATIO_MAX)) <<
4179 DISP_RATIO_ASPECT_RATIO_BIT;
4180 vf->orientation = hw->vh264_rotation;
4181
4182 if (hw->mmu_enable)
4183 return;
4184
4185 vf->canvas0Addr = vf->canvas1Addr = -1;
4186#ifdef NV21
4187 vf->plane_num = 2;
4188#else
4189 vf->plane_num = 3;
4190#endif
4191
4192 if (IS_VDEC_DW(hw)) {
4193 vf->width = (hw->frame_width /2);
4194 if (IS_VDEC_DW(hw) == 2)
4195 vf->height = (hw->frame_height /2);
4196 p_canvas_config = &hw->buffer_spec[index].vdec_dw_canvas_config[0];
4197 } else
4198 p_canvas_config = &hw->buffer_spec[index].canvas_config[0];
4199
4200 vf->canvas0_config[0] = p_canvas_config[0];
4201 vf->canvas0_config[1] = p_canvas_config[1];
4202#ifndef NV21
4203 vf->canvas0_config[2] = p_canvas_config[2];
4204#endif
4205 vf->canvas1_config[0] = p_canvas_config[0];
4206 vf->canvas1_config[1] = p_canvas_config[1];
4207#ifndef NV21
4208 vf->canvas1_config[2] = p_canvas_config[2];
4209#endif
4210}
4211
4212static void get_picture_qos_info(struct StorablePicture *picture)
4213{
4214 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
4215 unsigned char a[3];
4216 unsigned char i, j, t;
4217 unsigned long data;
4218
4219 get_random_bytes(&data, sizeof(unsigned long));
4220 if (picture->slice_type == I_SLICE)
4221 data = 0;
4222 a[0] = data & 0xff;
4223 a[1] = (data >> 8) & 0xff;
4224 a[2] = (data >> 16) & 0xff;
4225
4226 for (i = 0; i < 3; i++)
4227 for (j = i+1; j < 3; j++) {
4228 if (a[j] < a[i]) {
4229 t = a[j];
4230 a[j] = a[i];
4231 a[i] = t;
4232 } else if (a[j] == a[i]) {
4233 a[i]++;
4234 t = a[j];
4235 a[j] = a[i];
4236 a[i] = t;
4237 }
4238 }
4239 picture->max_mv = a[2];
4240 picture->avg_mv = a[1];
4241 picture->min_mv = a[0];
4242 /*
4243 pr_info("mv data %x a[0]= %x a[1]= %x a[2]= %x\n",
4244 data, a[0], a[1], a[2]);
4245 */
4246
4247 get_random_bytes(&data, sizeof(unsigned long));
4248 a[0] = data & 0x1f;
4249 a[1] = (data >> 8) & 0x3f;
4250 a[2] = (data >> 16) & 0x7f;
4251
4252 for (i = 0; i < 3; i++)
4253 for (j = i+1; j < 3; j++) {
4254 if (a[j] < a[i]) {
4255 t = a[j];
4256 a[j] = a[i];
4257 a[i] = t;
4258 } else if (a[j] == a[i]) {
4259 a[i]++;
4260 t = a[j];
4261 a[j] = a[i];
4262 a[i] = t;
4263 }
4264 }
4265 picture->max_qp = a[2];
4266 picture->avg_qp = a[1];
4267 picture->min_qp = a[0];
4268 /*
4269 pr_info("qp data %x a[0]= %x a[1]= %x a[2]= %x\n",
4270 data, a[0], a[1], a[2]);
4271 */
4272
4273 get_random_bytes(&data, sizeof(unsigned long));
4274 a[0] = data & 0x1f;
4275 a[1] = (data >> 8) & 0x3f;
4276 a[2] = (data >> 16) & 0x7f;
4277
4278 for (i = 0; i < 3; i++)
4279 for (j = i+1; j < 3; j++) {
4280 if (a[j] < a[i]) {
4281 t = a[j];
4282 a[j] = a[i];
4283 a[i] = t;
4284 } else if (a[j] == a[i]) {
4285 a[i]++;
4286 t = a[j];
4287 a[j] = a[i];
4288 a[i] = t;
4289 }
4290 }
4291 picture->max_skip = a[2];
4292 picture->avg_skip = a[1];
4293 picture->min_skip = a[0];
4294
4295
4296 /*
4297 pr_info("skip data %x a[0]= %x a[1]= %x a[2]= %x\n",
4298 data,a[0], a[1], a[2]);
4299 */
4300 } else {
4301 uint32_t blk88_y_count;
4302 uint32_t blk88_c_count;
4303 uint32_t blk22_mv_count;
4304 uint32_t rdata32;
4305 int32_t mv_hi;
4306 int32_t mv_lo;
4307 uint32_t rdata32_l;
4308 uint32_t mvx_L0_hi;
4309 uint32_t mvy_L0_hi;
4310 uint32_t mvx_L1_hi;
4311 uint32_t mvy_L1_hi;
4312 int64_t value;
4313 uint64_t temp_value;
4314/*
4315#define DEBUG_QOS
4316*/
4317#ifdef DEBUG_QOS
4318 int pic_number = picture->poc;
4319#endif
4320
4321 picture->max_mv = 0;
4322 picture->avg_mv = 0;
4323 picture->min_mv = 0;
4324
4325 picture->max_skip = 0;
4326 picture->avg_skip = 0;
4327 picture->min_skip = 0;
4328
4329 picture->max_qp = 0;
4330 picture->avg_qp = 0;
4331 picture->min_qp = 0;
4332
4333
4334
4335
4336
4337 /* set rd_idx to 0 */
4338 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, 0);
4339 blk88_y_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4340 if (blk88_y_count == 0) {
4341#ifdef DEBUG_QOS
4342 pr_info(" [Picture %d Quality] NO Data yet.\n",
4343 pic_number);
4344#endif
4345 /* reset all counts */
4346 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4347 return;
4348 }
4349 /* qp_y_sum */
4350 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4351#ifdef DEBUG_QOS
4352 pr_info(" [Picture %d Quality] Y QP AVG : %d (%d/%d)\n",
4353 pic_number, rdata32/blk88_y_count,
4354 rdata32, blk88_y_count);
4355#endif
4356 picture->avg_qp = rdata32/blk88_y_count;
4357 /* intra_y_count */
4358 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4359#ifdef DEBUG_QOS
4360 pr_info(" [Picture %d Quality] Y intra rate : %d%c (%d)\n",
4361 pic_number, rdata32*100/blk88_y_count,
4362 '%', rdata32);
4363#endif
4364 /* skipped_y_count */
4365 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4366#ifdef DEBUG_QOS
4367 pr_info(" [Picture %d Quality] Y skipped rate : %d%c (%d)\n",
4368 pic_number, rdata32*100/blk88_y_count,
4369 '%', rdata32);
4370#endif
4371 picture->avg_skip = rdata32*100/blk88_y_count;
4372 /* coeff_non_zero_y_count */
4373 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4374#ifdef DEBUG_QOS
4375 pr_info(" [Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n",
4376 pic_number, (100 - rdata32*100/(blk88_y_count*1)),
4377 '%', rdata32);
4378#endif
4379 /* blk66_c_count */
4380 blk88_c_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4381 if (blk88_c_count == 0) {
4382#ifdef DEBUG_QOS
4383 pr_info(" [Picture %d Quality] NO Data yet.\n",
4384 pic_number);
4385#endif
4386 /* reset all counts */
4387 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4388 return;
4389 }
4390 /* qp_c_sum */
4391 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4392#ifdef DEBUG_QOS
4393 pr_info(" [Picture %d Quality] C QP AVG : %d (%d/%d)\n",
4394 pic_number, rdata32/blk88_c_count,
4395 rdata32, blk88_c_count);
4396#endif
4397 /* intra_c_count */
4398 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4399#ifdef DEBUG_QOS
4400 pr_info(" [Picture %d Quality] C intra rate : %d%c (%d)\n",
4401 pic_number, rdata32*100/blk88_c_count,
4402 '%', rdata32);
4403#endif
4404 /* skipped_cu_c_count */
4405 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4406#ifdef DEBUG_QOS
4407 pr_info(" [Picture %d Quality] C skipped rate : %d%c (%d)\n",
4408 pic_number, rdata32*100/blk88_c_count,
4409 '%', rdata32);
4410#endif
4411 /* coeff_non_zero_c_count */
4412 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4413#ifdef DEBUG_QOS
4414 pr_info(" [Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n",
4415 pic_number, (100 - rdata32*100/(blk88_c_count*1)),
4416 '%', rdata32);
4417#endif
4418
4419 /* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0],
4420 1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */
4421 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4422#ifdef DEBUG_QOS
4423 pr_info(" [Picture %d Quality] Y QP min : %d\n",
4424 pic_number, (rdata32>>0)&0xff);
4425#endif
4426 picture->min_qp = (rdata32>>0)&0xff;
4427
4428#ifdef DEBUG_QOS
4429 pr_info(" [Picture %d Quality] Y QP max : %d\n",
4430 pic_number, (rdata32>>8)&0xff);
4431#endif
4432 picture->max_qp = (rdata32>>8)&0xff;
4433
4434#ifdef DEBUG_QOS
4435 pr_info(" [Picture %d Quality] C QP min : %d\n",
4436 pic_number, (rdata32>>16)&0xff);
4437 pr_info(" [Picture %d Quality] C QP max : %d\n",
4438 pic_number, (rdata32>>24)&0xff);
4439#endif
4440
4441 /* blk22_mv_count */
4442 blk22_mv_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4443 if (blk22_mv_count == 0) {
4444#ifdef DEBUG_QOS
4445 pr_info(" [Picture %d Quality] NO MV Data yet.\n",
4446 pic_number);
4447#endif
4448 /* reset all counts */
4449 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4450 return;
4451 }
4452 /* mvy_L1_count[39:32], mvx_L1_count[39:32],
4453 mvy_L0_count[39:32], mvx_L0_count[39:32] */
4454 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4455 /* should all be 0x00 or 0xff */
4456#ifdef DEBUG_QOS
4457 pr_info(" [Picture %d Quality] MV AVG High Bits: 0x%X\n",
4458 pic_number, rdata32);
4459#endif
4460 mvx_L0_hi = ((rdata32>>0)&0xff);
4461 mvy_L0_hi = ((rdata32>>8)&0xff);
4462 mvx_L1_hi = ((rdata32>>16)&0xff);
4463 mvy_L1_hi = ((rdata32>>24)&0xff);
4464
4465 /* mvx_L0_count[31:0] */
4466 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4467 temp_value = mvx_L0_hi;
4468 temp_value = (temp_value << 32) | rdata32_l;
4469
4470 if (mvx_L0_hi & 0x80)
4471 value = 0xFFFFFFF000000000 | temp_value;
4472 else
4473 value = temp_value;
4474 value = div_s64(value, blk22_mv_count);
4475#ifdef DEBUG_QOS
4476 pr_info(" [Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n",
4477 pic_number, (int)(value),
4478 value, blk22_mv_count);
4479#endif
4480 picture->avg_mv = value;
4481
4482 /* mvy_L0_count[31:0] */
4483 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4484 temp_value = mvy_L0_hi;
4485 temp_value = (temp_value << 32) | rdata32_l;
4486
4487 if (mvy_L0_hi & 0x80)
4488 value = 0xFFFFFFF000000000 | temp_value;
4489 else
4490 value = temp_value;
4491#ifdef DEBUG_QOS
4492 pr_info(" [Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n",
4493 pic_number, rdata32_l/blk22_mv_count,
4494 value, blk22_mv_count);
4495#endif
4496
4497 /* mvx_L1_count[31:0] */
4498 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4499 temp_value = mvx_L1_hi;
4500 temp_value = (temp_value << 32) | rdata32_l;
4501 if (mvx_L1_hi & 0x80)
4502 value = 0xFFFFFFF000000000 | temp_value;
4503 else
4504 value = temp_value;
4505#ifdef DEBUG_QOS
4506 pr_info(" [Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n",
4507 pic_number, rdata32_l/blk22_mv_count,
4508 value, blk22_mv_count);
4509#endif
4510
4511 /* mvy_L1_count[31:0] */
4512 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4513 temp_value = mvy_L1_hi;
4514 temp_value = (temp_value << 32) | rdata32_l;
4515 if (mvy_L1_hi & 0x80)
4516 value = 0xFFFFFFF000000000 | temp_value;
4517 else
4518 value = temp_value;
4519#ifdef DEBUG_QOS
4520 pr_info(" [Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n",
4521 pic_number, rdata32_l/blk22_mv_count,
4522 value, blk22_mv_count);
4523#endif
4524
4525 /* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */
4526 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4527 mv_hi = (rdata32>>16)&0xffff;
4528 if (mv_hi & 0x8000)
4529 mv_hi = 0x8000 - mv_hi;
4530#ifdef DEBUG_QOS
4531 pr_info(" [Picture %d Quality] MVX_L0 MAX : %d\n",
4532 pic_number, mv_hi);
4533#endif
4534 picture->max_mv = mv_hi;
4535
4536 mv_lo = (rdata32>>0)&0xffff;
4537 if (mv_lo & 0x8000)
4538 mv_lo = 0x8000 - mv_lo;
4539#ifdef DEBUG_QOS
4540 pr_info(" [Picture %d Quality] MVX_L0 MIN : %d\n",
4541 pic_number, mv_lo);
4542#endif
4543 picture->min_mv = mv_lo;
4544
4545#ifdef DEBUG_QOS
4546 /* {mvy_L0_max, mvy_L0_min} */
4547 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4548 mv_hi = (rdata32>>16)&0xffff;
4549 if (mv_hi & 0x8000)
4550 mv_hi = 0x8000 - mv_hi;
4551 pr_info(" [Picture %d Quality] MVY_L0 MAX : %d\n",
4552 pic_number, mv_hi);
4553
4554
4555 mv_lo = (rdata32>>0)&0xffff;
4556 if (mv_lo & 0x8000)
4557 mv_lo = 0x8000 - mv_lo;
4558
4559 pr_info(" [Picture %d Quality] MVY_L0 MIN : %d\n",
4560 pic_number, mv_lo);
4561
4562
4563 /* {mvx_L1_max, mvx_L1_min} */
4564 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4565 mv_hi = (rdata32>>16)&0xffff;
4566 if (mv_hi & 0x8000)
4567 mv_hi = 0x8000 - mv_hi;
4568
4569 pr_info(" [Picture %d Quality] MVX_L1 MAX : %d\n",
4570 pic_number, mv_hi);
4571
4572
4573 mv_lo = (rdata32>>0)&0xffff;
4574 if (mv_lo & 0x8000)
4575 mv_lo = 0x8000 - mv_lo;
4576
4577 pr_info(" [Picture %d Quality] MVX_L1 MIN : %d\n",
4578 pic_number, mv_lo);
4579
4580
4581 /* {mvy_L1_max, mvy_L1_min} */
4582 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4583 mv_hi = (rdata32>>16)&0xffff;
4584 if (mv_hi & 0x8000)
4585 mv_hi = 0x8000 - mv_hi;
4586
4587 pr_info(" [Picture %d Quality] MVY_L1 MAX : %d\n",
4588 pic_number, mv_hi);
4589
4590 mv_lo = (rdata32>>0)&0xffff;
4591 if (mv_lo & 0x8000)
4592 mv_lo = 0x8000 - mv_lo;
4593
4594 pr_info(" [Picture %d Quality] MVY_L1 MIN : %d\n",
4595 pic_number, mv_lo);
4596#endif
4597
4598 rdata32 = READ_VREG(VDEC_PIC_QUALITY_CTRL);
4599#ifdef DEBUG_QOS
4600 pr_info(" [Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n",
4601 pic_number, rdata32);
4602#endif
4603 /* reset all counts */
4604 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4605 }
4606}
4607
4608static int get_max_dec_frame_buf_size(int level_idc,
4609 int max_reference_frame_num, int mb_width,
4610 int mb_height)
4611{
4612 int pic_size = mb_width * mb_height * 384;
4613
4614 int size = 0;
4615
4616 switch (level_idc) {
4617 case 9:
4618 size = 152064;
4619 break;
4620 case 10:
4621 size = 152064;
4622 break;
4623 case 11:
4624 size = 345600;
4625 break;
4626 case 12:
4627 size = 912384;
4628 break;
4629 case 13:
4630 size = 912384;
4631 break;
4632 case 20:
4633 size = 912384;
4634 break;
4635 case 21:
4636 size = 1824768;
4637 break;
4638 case 22:
4639 size = 3110400;
4640 break;
4641 case 30:
4642 size = 3110400;
4643 break;
4644 case 31:
4645 size = 6912000;
4646 break;
4647 case 32:
4648 size = 7864320;
4649 break;
4650 case 40:
4651 size = 12582912;
4652 break;
4653 case 41:
4654 size = 12582912;
4655 break;
4656 case 42:
4657 size = 13369344;
4658 break;
4659 case 50:
4660 size = 42393600;
4661 break;
4662 case 51:
4663 case 52:
4664 default:
4665 size = 70778880;
4666 break;
4667 }
4668
4669 size /= pic_size;
4670 size = size + 1; /* need one more buffer */
4671
4672 if (max_reference_frame_num > size)
4673 size = max_reference_frame_num;
4674 size = imin(size, 16);
4675
4676 return size;
4677}
4678
4679static void vh264_config_canvs_for_mmu(struct vdec_h264_hw_s *hw)
4680{
4681 int i, j;
4682
4683 if (hw->double_write_mode) {
4684 mutex_lock(&vmh264_mutex);
4685 if (hw->decode_pic_count == 0) {
4686 for (j = 0; j < hw->dpb.mDPB.size; j++) {
4687 i = get_buf_spec_by_canvas_pos(hw, j);
4688 if (i >= 0)
4689 config_decode_canvas_ex(hw, i);
4690 }
4691 }
4692 mutex_unlock(&vmh264_mutex);
4693 }
4694}
4695
4696static int vh264_set_params(struct vdec_h264_hw_s *hw,
4697 u32 param1, u32 param2, u32 param3, u32 param4)
4698{
4699 int i, j;
4700 int mb_width, mb_total;
4701 int max_reference_size, level_idc;
4702 int mb_height = 0;
4703 unsigned long flags;
4704 /*int mb_mv_byte;*/
4705 struct vdec_s *vdec = hw_to_vdec(hw);
4706 u32 seq_info2;
4707 int ret = 0;
4708 int active_buffer_spec_num;
4709 unsigned int buf_size;
4710 unsigned int frame_mbs_only_flag;
4711 unsigned int chroma_format_idc, chroma444;
4712 unsigned int crop_infor, crop_bottom, crop_right;
4713 unsigned int used_reorder_dpb_size_margin
4714 = hw->reorder_dpb_size_margin;
4715 u8 *colocate_vaddr = NULL;
4716
4717#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
4718 if (vdec->master || vdec->slave)
4719 used_reorder_dpb_size_margin =
4720 reorder_dpb_size_margin_dv;
4721#endif
4722 seq_info2 = param1;
4723 hw->seq_info = param2;
4724
4725 mb_width = seq_info2 & 0xff;
4726 mb_total = (seq_info2 >> 8) & 0xffff;
4727 if (!mb_width && mb_total) /*for 4k2k*/
4728 mb_width = 256;
4729 if (mb_width)
4730 mb_height = mb_total/mb_width;
4731 if (mb_width <= 0 || mb_height <= 0 ||
4732 is_oversize(mb_width << 4, mb_height << 4)) {
4733 dpb_print(DECODE_ID(hw), 0,
4734 "!!!wrong seq_info2 0x%x mb_width/mb_height (0x%x/0x%x) %x\r\n",
4735 seq_info2,
4736 mb_width,
4737 mb_height);
4738 return -1;
4739 }
4740
4741 if (seq_info2 != 0 &&
4742 hw->seq_info2 != (seq_info2 & (~0x80000000)) &&
4743 hw->seq_info2 != 0
4744 ) /*picture size changed*/
4745 h264_reconfig(hw);
4746
4747 if (hw->config_bufmgr_done == 0) {
4748 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4749 u32 reg_val;
4750 hw->cfg_param1 = param1;
4751 hw->cfg_param2 = param2;
4752 hw->cfg_param3 = param3;
4753 hw->cfg_param4 = param4;
4754
4755 hw->seq_info2 = seq_info2 & (~0x80000000);
4756 dpb_print(DECODE_ID(hw), 0,
4757 "AV_SCRATCH_1 = %x, AV_SCRATCH_2 %x\r\n",
4758 seq_info2, hw->seq_info);
4759
4760 dpb_init_global(&hw->dpb,
4761 DECODE_ID(hw), 0, 0);
4762
4763 p_H264_Dpb->fast_output_enable = fast_output_enable;
4764 /*mb_mv_byte = (seq_info2 & 0x80000000) ? 24 : 96;*/
4765
4766#if 1
4767 /*crop*/
4768 /* AV_SCRATCH_2
4769 bit 15: frame_mbs_only_flag
4770 bit 13-14: chroma_format_idc */
4771 frame_mbs_only_flag = (hw->seq_info >> 15) & 0x01;
4772 chroma_format_idc = (hw->seq_info >> 13) & 0x03;
4773 chroma444 = (chroma_format_idc == 3) ? 1 : 0;
4774
4775 /* @AV_SCRATCH_6.31-16 = (left << 8 | right ) << 1
4776 @AV_SCRATCH_6.15-0 = (top << 8 | bottom ) <<
4777 (2 - frame_mbs_only_flag) */
4778 crop_infor = param3;
4779 crop_bottom = (crop_infor & 0xff) >> (2 - frame_mbs_only_flag);
4780 crop_right = ((crop_infor >> 16) & 0xff)
4781 >> (2 - frame_mbs_only_flag);
4782
4783 p_H264_Dpb->mSPS.frame_mbs_only_flag = frame_mbs_only_flag;
4784 hw->frame_width = mb_width << 4;
4785 hw->frame_height = mb_height << 4;
4786 if (frame_mbs_only_flag) {
4787 hw->frame_height =
4788 hw->frame_height - (2 >> chroma444) *
4789 min(crop_bottom,
4790 (unsigned int)((8 << chroma444) - 1));
4791 hw->frame_width =
4792 hw->frame_width -
4793 (2 >> chroma444) * min(crop_right,
4794 (unsigned
4795 int)((8 << chroma444) - 1));
4796 } else {
4797 hw->frame_height =
4798 hw->frame_height - (4 >> chroma444) *
4799 min(crop_bottom,
4800 (unsigned int)((8 << chroma444)
4801 - 1));
4802 hw->frame_width =
4803 hw->frame_width -
4804 (4 >> chroma444) * min(crop_right,
4805 (unsigned int)((8 << chroma444) - 1));
4806 }
4807 dpb_print(DECODE_ID(hw), 0,
4808 "frame_mbs_only_flag %d, crop_bottom %d, frame_height %d,\n",
4809 frame_mbs_only_flag, crop_bottom, hw->frame_height);
4810 dpb_print(DECODE_ID(hw), 0,
4811 "mb_height %d,crop_right %d, frame_width %d, mb_width %d\n",
4812 mb_height, crop_right,
4813 hw->frame_width, mb_width);
4814
4815 if (hw->frame_height == 1088)
4816 hw->frame_height = 1080;
4817#endif
4818 if (!hw->mmu_enable) {
4819 mb_width = (mb_width+3) & 0xfffffffc;
4820 mb_height = (mb_height+3) & 0xfffffffc;
4821 }
4822 mb_total = mb_width * mb_height;
4823 hw->mb_width = mb_width;
4824 hw->mb_height = mb_height;
4825 hw->mb_total = mb_total;
4826 if (hw->mmu_enable)
4827 hevc_mcr_sao_global_hw_init(hw,
4828 (hw->mb_width << 4), (hw->mb_height << 4));
4829
4830 reg_val = param4;
4831 level_idc = reg_val & 0xff;
4832 max_reference_size = (reg_val >> 8) & 0xff;
4833 hw->dpb.origin_max_reference = max_reference_size;
4834 dpb_print(DECODE_ID(hw), 0,
4835 "mb height/widht/total: %x/%x/%x level_idc %x max_ref_num %x\n",
4836 mb_height, mb_width, mb_total,
4837 level_idc, max_reference_size);
4838
4839
4840 p_H264_Dpb->colocated_buf_size = mb_total * 96;
4841 hw->dpb.reorder_pic_num =
4842 get_max_dec_frame_buf_size(level_idc,
4843 max_reference_size, mb_width, mb_height);
4844
4845 dpb_print(DECODE_ID(hw), 0,
4846 "restriction_flag=%d, max_dec_frame_buffering=%d, reorder_pic_num=%d\n",
4847 hw->bitstream_restriction_flag,
4848 hw->max_dec_frame_buffering,
4849 hw->dpb.reorder_pic_num);
4850
4851 if ((hw->bitstream_restriction_flag) &&
4852 (hw->max_dec_frame_buffering <
4853 hw->dpb.reorder_pic_num)) {
4854 hw->dpb.reorder_pic_num = hw->max_dec_frame_buffering;
4855 dpb_print(DECODE_ID(hw), 0,
4856 "set reorder_pic_num to %d\n",
4857 hw->dpb.reorder_pic_num);
4858 }
4859
4860 active_buffer_spec_num =
4861 hw->dpb.reorder_pic_num
4862 + used_reorder_dpb_size_margin;
4863 hw->max_reference_size =
4864 max_reference_size + reference_buf_margin;
4865
4866 if (active_buffer_spec_num > MAX_VF_BUF_NUM) {
4867 active_buffer_spec_num = MAX_VF_BUF_NUM;
4868 hw->dpb.reorder_pic_num = active_buffer_spec_num
4869 - used_reorder_dpb_size_margin;
4870 }
4871 hw->dpb.mDPB.size = active_buffer_spec_num;
4872 if (hw->max_reference_size > MAX_VF_BUF_NUM)
4873 hw->max_reference_size = MAX_VF_BUF_NUM;
4874 hw->dpb.max_reference_size = hw->max_reference_size;
4875
4876 if (hw->no_poc_reorder_flag)
4877 hw->dpb.reorder_pic_num = 1;
4878 dpb_print(DECODE_ID(hw), 0,
4879 "%s active_buf_spec_num %d reorder_pic_num %d collocate_buf_num %d\r\n",
4880 __func__, active_buffer_spec_num,
4881 hw->dpb.reorder_pic_num,
4882 hw->max_reference_size);
4883
4884 buf_size = (hw->mb_total << 8) + (hw->mb_total << 7);
4885
4886 mutex_lock(&vmh264_mutex);
4887 if (!hw->mmu_enable) {
4888 config_buf_specs(vdec);
4889 i = get_buf_spec_by_canvas_pos(hw, 0);
4890
4891 if (hw->is_used_v4l) {
4892 if (i != -1) {
4893 pr_info("v4l: delay alloc the buffer.\n");
4894 }
4895 } else {
4896 if ((i != -1) && alloc_one_buf_spec(hw, i) >= 0)
4897 config_decode_canvas(hw, i);
4898 else
4899 ret = -1;
4900 }
4901 } else {
4902 if (hw->double_write_mode) {
4903 config_buf_specs_ex(vdec);
4904 } else {
4905 spin_lock_irqsave(&hw->bufspec_lock, flags);
4906 for (i = 0, j = 0;
4907 j < active_buffer_spec_num
4908 && i < BUFSPEC_POOL_SIZE;
4909 i++) {
4910 if (hw->buffer_spec[i].used != -1)
4911 continue;
4912 hw->buffer_spec[i].used = 0;
4913 hw->buffer_spec[i].
4914 alloc_header_addr = 0;
4915 hw->buffer_spec[i].canvas_pos = j;
4916 j++;
4917 }
4918 spin_unlock_irqrestore(&hw->bufspec_lock,
4919 flags);
4920 }
4921 hevc_mcr_config_canv2axitbl(hw, 0);
4922 }
4923 mutex_unlock(&vmh264_mutex);
4924 if (dpb_is_debug(DECODE_ID(hw),
4925 PRINT_FLAG_DUMP_BUFSPEC))
4926 dump_bufspec(hw, __func__);
4927
4928#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
4929 buf_size = PAGE_ALIGN(
4930 p_H264_Dpb->colocated_buf_size *
4931 active_buffer_spec_num);
4932#else
4933 buf_size = PAGE_ALIGN(
4934 p_H264_Dpb->colocated_buf_size *
4935 hw->max_reference_size);
4936#endif
4937
4938 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_REF_IDX,
4939 buf_size, DRIVER_NAME,
4940 &hw->collocate_cma_alloc_addr) < 0)
4941 return -1;
4942 if (!vdec_secure(vdec)) {
4943 /* clear for some mosaic problem after reset bufmgr */
4944 colocate_vaddr = codec_mm_vmap(hw->collocate_cma_alloc_addr, buf_size);
4945 if (colocate_vaddr != NULL) {
4946 memset(colocate_vaddr, 0, buf_size);
4947 codec_mm_dma_flush(colocate_vaddr, buf_size, DMA_TO_DEVICE);
4948 codec_mm_unmap_phyaddr(colocate_vaddr);
4949 }
4950 }
4951
4952 hw->dpb.colocated_mv_addr_start =
4953 hw->collocate_cma_alloc_addr;
4954#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
4955 hw->dpb.colocated_mv_addr_end =
4956 hw->dpb.colocated_mv_addr_start +
4957 (p_H264_Dpb->colocated_buf_size *
4958 active_buffer_spec_num);
4959#else
4960 hw->dpb.colocated_mv_addr_end =
4961 hw->dpb.colocated_mv_addr_start +
4962 (p_H264_Dpb->colocated_buf_size *
4963 hw->max_reference_size);
4964#endif
4965 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4966 "callocate cma, %lx, %x\n",
4967 hw->collocate_cma_alloc_addr,
4968 hw->dpb.colocated_mv_addr_start);
4969
4970 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4971 "colocated_mv_addr_start %x colocated_mv_addr_end %x\n",
4972 hw->dpb.colocated_mv_addr_start,
4973 hw->dpb.colocated_mv_addr_end);
4974 if (!hw->mmu_enable) {
4975 mutex_lock(&vmh264_mutex);
4976 if (ret >= 0 && hw->decode_pic_count == 0) {
4977 int buf_cnt;
4978 /* h264_reconfig: alloc later*/
4979 buf_cnt = hw->dpb.mDPB.size;
4980
4981 for (j = 1; j < buf_cnt; j++) {
4982 i = get_buf_spec_by_canvas_pos(hw, j);
4983
4984 if (hw->is_used_v4l) {
4985 pr_info("v4l: delay alloc the buffer.\n");
4986 break;
4987 } else if (alloc_one_buf_spec(hw, i) < 0)
4988 break;
4989
4990 config_decode_canvas(hw, i);
4991 }
4992 }
4993 mutex_unlock(&vmh264_mutex);
4994 } else {
4995 vh264_config_canvs_for_mmu(hw);
4996 }
4997
4998 hw->config_bufmgr_done = 1;
4999
5000 /*end of config_bufmgr_done */
5001 }
5002
5003 return ret;
5004}
5005
5006static void vui_config(struct vdec_h264_hw_s *hw)
5007{
5008 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5009 int aspect_ratio_info_present_flag, aspect_ratio_idc;
5010 /*time*/
5011 hw->num_units_in_tick = p_H264_Dpb->num_units_in_tick;
5012 hw->time_scale = p_H264_Dpb->time_scale;
5013 hw->timing_info_present_flag = p_H264_Dpb->vui_status & 0x2;
5014
5015 hw->bitstream_restriction_flag =
5016 p_H264_Dpb->bitstream_restriction_flag;
5017 hw->num_reorder_frames =
5018 p_H264_Dpb->num_reorder_frames;
5019 hw->max_dec_frame_buffering =
5020 p_H264_Dpb->max_dec_frame_buffering;
5021
5022 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5023 "vui_config: pdb %d, %d, %d\n",
5024 p_H264_Dpb->bitstream_restriction_flag,
5025 p_H264_Dpb->num_reorder_frames,
5026 p_H264_Dpb->max_dec_frame_buffering);
5027
5028 hw->fixed_frame_rate_flag = 0;
5029 if (hw->timing_info_present_flag) {
5030 hw->fixed_frame_rate_flag =
5031 p_H264_Dpb->fixed_frame_rate_flag;
5032
5033 if (((hw->num_units_in_tick * 120) >= hw->time_scale &&
5034 ((!hw->sync_outside) ||
5035 (!hw->frame_dur)))
5036 && hw->num_units_in_tick && hw->time_scale) {
5037 if (hw->use_idr_framerate ||
5038 hw->fixed_frame_rate_flag ||
5039 !hw->frame_dur ||
5040 !hw->duration_from_pts_done
5041 /*|| vh264_running*/) {
5042 u32 frame_dur_es =
5043 div_u64(96000ULL * 2 * hw->num_units_in_tick,
5044 hw->time_scale);
5045 if (hw->frame_dur != frame_dur_es) {
5046 hw->h264_first_valid_pts_ready = false;
5047 hw->h264pts1 = 0;
5048 hw->h264pts2 = 0;
5049 hw->h264_pts_count = 0;
5050 hw->duration_from_pts_done = 0;
5051 fixed_frame_rate_mode =
5052 FIX_FRAME_RATE_OFF;
5053 hw->pts_duration = 0;
5054 hw->frame_dur = frame_dur_es;
5055 vdec_schedule_work(&hw->notify_work);
5056 dpb_print(DECODE_ID(hw),
5057 PRINT_FLAG_DEC_DETAIL,
5058 "frame_dur %d from timing_info\n",
5059 hw->frame_dur);
5060 }
5061
5062 /*hack to avoid use ES frame duration when
5063 *it's half of the rate from system info
5064 * sometimes the encoder is given a wrong
5065 * frame rate but the system side information
5066 * is more reliable
5067 *if ((frame_dur * 2) != frame_dur_es) {
5068 * frame_dur = frame_dur_es;
5069 *}
5070 */
5071 }
5072 }
5073 } else {
5074 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
5075 "H.264: timing_info not present\n");
5076 }
5077
5078 /*aspect ratio*/
5079 aspect_ratio_info_present_flag =
5080 p_H264_Dpb->vui_status & 0x1;
5081 aspect_ratio_idc = p_H264_Dpb->aspect_ratio_idc;
5082
5083 if (aspect_ratio_info_present_flag) {
5084 if (aspect_ratio_idc == EXTEND_SAR) {
5085 hw->h264_ar = 0x3ff;
5086 hw->height_aspect_ratio =
5087 p_H264_Dpb->aspect_ratio_sar_height;
5088 hw->width_aspect_ratio =
5089 p_H264_Dpb->aspect_ratio_sar_width;
5090 } else {
5091 /* pr_info("v264dec: aspect_ratio_idc = %d\n",
5092 aspect_ratio_idc); */
5093
5094 switch (aspect_ratio_idc) {
5095 case 1:
5096 hw->h264_ar = 0x3ff;
5097 hw->height_aspect_ratio = 1;
5098 hw->width_aspect_ratio = 1;
5099 break;
5100 case 2:
5101 hw->h264_ar = 0x3ff;
5102 hw->height_aspect_ratio = 11;
5103 hw->width_aspect_ratio = 12;
5104 break;
5105 case 3:
5106 hw->h264_ar = 0x3ff;
5107 hw->height_aspect_ratio = 11;
5108 hw->width_aspect_ratio = 10;
5109 break;
5110 case 4:
5111 hw->h264_ar = 0x3ff;
5112 hw->height_aspect_ratio = 11;
5113 hw->width_aspect_ratio = 16;
5114 break;
5115 case 5:
5116 hw->h264_ar = 0x3ff;
5117 hw->height_aspect_ratio = 33;
5118 hw->width_aspect_ratio = 40;
5119 break;
5120 case 6:
5121 hw->h264_ar = 0x3ff;
5122 hw->height_aspect_ratio = 11;
5123 hw->width_aspect_ratio = 24;
5124 break;
5125 case 7:
5126 hw->h264_ar = 0x3ff;
5127 hw->height_aspect_ratio = 11;
5128 hw->width_aspect_ratio = 20;
5129 break;
5130 case 8:
5131 hw->h264_ar = 0x3ff;
5132 hw->height_aspect_ratio = 11;
5133 hw->width_aspect_ratio = 32;
5134 break;
5135 case 9:
5136 hw->h264_ar = 0x3ff;
5137 hw->height_aspect_ratio = 33;
5138 hw->width_aspect_ratio = 80;
5139 break;
5140 case 10:
5141 hw->h264_ar = 0x3ff;
5142 hw->height_aspect_ratio = 11;
5143 hw->width_aspect_ratio = 18;
5144 break;
5145 case 11:
5146 hw->h264_ar = 0x3ff;
5147 hw->height_aspect_ratio = 11;
5148 hw->width_aspect_ratio = 15;
5149 break;
5150 case 12:
5151 hw->h264_ar = 0x3ff;
5152 hw->height_aspect_ratio = 33;
5153 hw->width_aspect_ratio = 64;
5154 break;
5155 case 13:
5156 hw->h264_ar = 0x3ff;
5157 hw->height_aspect_ratio = 99;
5158 hw->width_aspect_ratio = 160;
5159 break;
5160 case 14:
5161 hw->h264_ar = 0x3ff;
5162 hw->height_aspect_ratio = 3;
5163 hw->width_aspect_ratio = 4;
5164 break;
5165 case 15:
5166 hw->h264_ar = 0x3ff;
5167 hw->height_aspect_ratio = 2;
5168 hw->width_aspect_ratio = 3;
5169 break;
5170 case 16:
5171 hw->h264_ar = 0x3ff;
5172 hw->height_aspect_ratio = 1;
5173 hw->width_aspect_ratio = 2;
5174 break;
5175 default:
5176 if (hw->vh264_ratio >> 16) {
5177 hw->h264_ar = (hw->frame_height *
5178 (hw->vh264_ratio & 0xffff) *
5179 0x100 +
5180 ((hw->vh264_ratio >> 16) *
5181 hw->frame_width / 2)) /
5182 ((hw->vh264_ratio >> 16) *
5183 hw->frame_width);
5184 hw->height_aspect_ratio = 1;
5185 hw->width_aspect_ratio = 1;
5186 } else {
5187 hw->h264_ar = 0x3ff;
5188 hw->height_aspect_ratio = 1;
5189 hw->width_aspect_ratio = 1;
5190 }
5191 break;
5192 }
5193 }
5194 } else {
5195 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
5196 "v264dec: aspect_ratio not available from source\n");
5197 if (hw->vh264_ratio >> 16) {
5198 /* high 16 bit is width, low 16 bit is height */
5199 hw->h264_ar =
5200 ((hw->vh264_ratio & 0xffff) *
5201 hw->frame_height * 0x100 +
5202 (hw->vh264_ratio >> 16) *
5203 hw->frame_width / 2) /
5204 ((hw->vh264_ratio >> 16) *
5205 hw->frame_width);
5206 hw->height_aspect_ratio = 1;
5207 hw->width_aspect_ratio = 1;
5208 } else {
5209 hw->h264_ar = 0x3ff;
5210 hw->height_aspect_ratio = 1;
5211 hw->width_aspect_ratio = 1;
5212 }
5213 }
5214
5215 if (hw->pts_unstable && (hw->fixed_frame_rate_flag == 0)) {
5216 if (((hw->frame_dur == RATE_2397_FPS)
5217 && (dec_control
5218 & DEC_CONTROL_FLAG_FORCE_RATE_2397_FPS_FIX_FRAME_RATE))
5219 || ((RATE_2997_FPS ==
5220 hw->frame_dur) &&
5221 (dec_control &
5222 DEC_CONTROL_FLAG_FORCE_RATE_2997_FPS_FIX_FRAME_RATE))) {
5223 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
5224 "force fix frame rate\n");
5225 hw->fixed_frame_rate_flag = 0x40;
5226 }
5227 }
5228
5229 /*video_signal_from_vui: to do .. */
5230}
5231
5232static void bufmgr_recover(struct vdec_h264_hw_s *hw)
5233{
5234 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5235
5236 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 2);
5237 if (error_proc_policy & 0x20) {
5238 if (!hw->is_used_v4l)
5239 hw->reset_bufmgr_flag = 1;
5240 }
5241}
5242
5243void bufmgr_force_recover(struct h264_dpb_stru *p_H264_Dpb)
5244{
5245 struct vdec_h264_hw_s *hw =
5246 container_of(p_H264_Dpb, struct vdec_h264_hw_s, dpb);
5247
5248 dpb_print(DECODE_ID(hw), 0, "call %s\n", __func__);
5249
5250 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 2);
5251 hw->reset_bufmgr_flag = 1;
5252}
5253
5254#ifdef CONSTRAIN_MAX_BUF_NUM
5255static int get_vf_ref_only_buf_count(struct vdec_h264_hw_s *hw)
5256{
5257 int i;
5258 int count = 0;
5259 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
5260 if (is_buf_spec_in_disp_q(hw, i) &&
5261 hw->buffer_spec[i].vf_ref > 0)
5262 count++;
5263 }
5264 return count;
5265}
5266
5267static int get_used_buf_count(struct vdec_h264_hw_s *hw)
5268{
5269 int i;
5270 int count = 0;
5271 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
5272 if (is_buf_spec_in_use(hw, i))
5273 count++;
5274 }
5275 return count;
5276}
5277#endif
5278
5279
5280static bool is_buffer_available(struct vdec_s *vdec)
5281{
5282 bool buffer_available = 1;
5283 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
5284 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5285 struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB;
5286 if ((kfifo_len(&hw->newframe_q) <= 0) ||
5287 ((hw->config_bufmgr_done) && (!have_free_buf_spec(vdec))) ||
5288 ((p_H264_Dpb->mDPB.init_done) &&
5289 (p_H264_Dpb->mDPB.used_size >= (p_H264_Dpb->mDPB.size -1)) &&
5290 (is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB) == 0))) {
5291 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
5292 "%s, empty, newq(%d), free_spec(%d), initdon(%d), used_size(%d/%d), unused_fr_dpb(%d)\n",
5293 __func__,
5294 kfifo_len(&hw->newframe_q),
5295 have_free_buf_spec(vdec),
5296 p_H264_Dpb->mDPB.init_done,
5297 p_H264_Dpb->mDPB.used_size, p_H264_Dpb->mDPB.size,
5298 is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB)
5299 );
5300 buffer_available = 0;
5301 if (dpb_is_debug(DECODE_ID(hw),
5302 DEBUG_DISABLE_RUNREADY_RMBUF))
5303 return buffer_available;
5304
5305 if ((error_proc_policy & 0x4) &&
5306 (error_proc_policy & 0x8)) {
5307 if ((kfifo_len(&hw->display_q) <= 0) &&
5308 (p_H264_Dpb->mDPB.used_size ==
5309 p_H264_Dpb->mDPB.size) &&
5310 (p_Dpb->ref_frames_in_buffer >
5311 (imax(
5312 1, p_Dpb->num_ref_frames)
5313 - p_Dpb->ltref_frames_in_buffer +
5314 force_sliding_margin)))
5315 bufmgr_recover(hw);
5316 else
5317 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5318 } else if ((error_proc_policy & 0x4) &&
5319 (kfifo_len(&hw->display_q) <= 0) &&
5320 ((p_H264_Dpb->mDPB.used_size ==
5321 p_H264_Dpb->mDPB.size) ||
5322 (!have_free_buf_spec(vdec)))) {
5323 enum receviver_start_e state = RECEIVER_INACTIVE;
5324 if ((error_proc_policy & 0x10) &&
5325 vf_get_receiver(vdec->vf_provider_name)) {
5326 state =
5327 vf_notify_receiver(vdec->vf_provider_name,
5328 VFRAME_EVENT_PROVIDER_QUREY_STATE,
5329 NULL);
5330 if ((state == RECEIVER_STATE_NULL)
5331 || (state == RECEIVER_STATE_NONE))
5332 state = RECEIVER_INACTIVE;
5333 }
5334 if (state == RECEIVER_INACTIVE)
5335 bufmgr_recover(hw);
5336 else
5337 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5338 } else if ((error_proc_policy & 0x8) &&
5339 (p_Dpb->ref_frames_in_buffer >
5340 (imax(
5341 1, p_Dpb->num_ref_frames)
5342 - p_Dpb->ltref_frames_in_buffer +
5343 force_sliding_margin)))
5344 bufmgr_recover(hw);
5345 else
5346 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5347
5348 if (hw->reset_bufmgr_flag == 1)
5349 buffer_available = 1;
5350 else if (hw->is_used_v4l)
5351 buffer_available = have_free_buf_spec(vdec);
5352 }
5353
5354 return buffer_available;
5355}
5356
5357#define AUX_TAG_SEI 0x2
5358
5359#define SEI_BUFFERING_PERIOD 0
5360#define SEI_PicTiming 1
5361#define SEI_USER_DATA 4
5362#define SEI_RECOVERY_POINT 6
5363
5364/*
5365 *************************************************************************
5366 * Function:Reads bits from the bitstream buffer
5367 * Input:
5368 byte buffer[]
5369 containing sei message data bits
5370 int totbitoffset
5371 bit offset from start of partition
5372 int bytecount
5373 total bytes in bitstream
5374 int numbits
5375 number of bits to read
5376 * Output:
5377 int *info
5378 * Return:
5379 -1: failed
5380 > 0: the count of bit read
5381 * Attention:
5382 *************************************************************************
5383 */
5384
5385static int get_bits(unsigned char buffer[],
5386 int totbitoffset,
5387 int *info,
5388 int bytecount,
5389 int numbits)
5390{
5391 register int inf;
5392 long byteoffset;
5393 int bitoffset;
5394
5395 int bitcounter = numbits;
5396
5397 byteoffset = totbitoffset / 8;
5398 bitoffset = 7 - (totbitoffset % 8);
5399
5400 inf = 0;
5401 while (numbits) {
5402 inf <<= 1;
5403 inf |= (buffer[byteoffset] & (0x01 << bitoffset)) >> bitoffset;
5404 numbits--;
5405 bitoffset--;
5406 if (bitoffset < 0) {
5407 byteoffset++;
5408 bitoffset += 8;
5409 if (byteoffset > bytecount)
5410 return -1;
5411 }
5412 }
5413
5414 *info = inf;
5415
5416
5417 return bitcounter;
5418}
5419
5420static int parse_one_sei_record(struct vdec_h264_hw_s *hw,
5421 u8 *sei_data_buf,
5422 u8 *sei_data_buf_end)
5423{
5424 int payload_type;
5425 int payload_size;
5426 u8 *p_sei;
5427 int temp = 0;
5428 int bit_offset;
5429 int read_size;
5430 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5431
5432 p_sei = sei_data_buf;
5433 read_size = 0;
5434 payload_type = 0;
5435 do {
5436 if (p_sei >= sei_data_buf_end)
5437 return read_size;
5438
5439 payload_type += *p_sei;
5440 read_size++;
5441 } while (*p_sei++ == 255);
5442
5443
5444 payload_size = 0;
5445 do {
5446 if (p_sei >= sei_data_buf_end)
5447 return read_size;
5448
5449 payload_size += *p_sei;
5450 read_size++;
5451 } while (*p_sei++ == 255);
5452
5453
5454 if (p_sei + payload_size > sei_data_buf_end) {
5455 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5456 "%s: payload_type = %d, payload_size = %d is over\n",
5457 __func__, payload_type, payload_size);
5458 return read_size;
5459 }
5460 bit_offset = 0;
5461
5462 if (payload_size <= 0) {
5463 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5464 "%s warning: this is a null sei message for payload_type = %d\n",
5465 __func__, payload_type);
5466 return read_size;
5467 }
5468 switch (payload_type) {
5469 case SEI_BUFFERING_PERIOD:
5470 break;
5471 case SEI_PicTiming:
5472 if (p_H264_Dpb->vui_status & 0xc) {
5473 int cpb_removal_delay;
5474 int dpb_output_delay;
5475 u32 delay_len;
5476
5477 delay_len = p_H264_Dpb->dpb_param.l.data[DELAY_LENGTH];
5478 cpb_removal_delay
5479 = (delay_len & 0x1F) + 1;
5480 dpb_output_delay
5481 = ((delay_len >> 5) & 0x1F) + 1;
5482
5483 get_bits(p_sei, bit_offset,
5484 &temp, payload_size,
5485 dpb_output_delay+cpb_removal_delay);
5486 bit_offset += dpb_output_delay+cpb_removal_delay;
5487 }
5488 if (p_H264_Dpb->vui_status & 0x10) {
5489 get_bits(p_sei, bit_offset, &temp, payload_size, 4);
5490 bit_offset += 4;
5491 p_H264_Dpb->dpb_param.l.data[PICTURE_STRUCT] = temp;
5492 }
5493 break;
5494 case SEI_USER_DATA:
5495 if (enable_itu_t35) {
5496 int i;
5497 int j;
5498 int data_len;
5499 u8 *user_data_buf;
5500
5501 user_data_buf
5502 = hw->sei_itu_data_buf + hw->sei_itu_data_len;
5503 /* user data length should be align with 8 bytes,
5504 if not, then padding with zero*/
5505 for (i = 0; i < payload_size; i += 8) {
5506 if (hw->sei_itu_data_len + i >= SEI_ITU_DATA_SIZE)
5507 break; // Avoid out-of-bound writing
5508 for (j = 0; j < 8; j++) {
5509 int index;
5510
5511 index = i+7-j;
5512 if (index >= payload_size)
5513 user_data_buf[i+j] = 0;
5514 else
5515 user_data_buf[i+j]
5516 = p_sei[i+7-j];
5517 }
5518 }
5519
5520 data_len = payload_size;
5521 if (payload_size % 8)
5522 data_len = ((payload_size + 8) >> 3) << 3;
5523
5524 hw->sei_itu_data_len += data_len;
5525 if (hw->sei_itu_data_len >= SEI_ITU_DATA_SIZE)
5526 hw->sei_itu_data_len = SEI_ITU_DATA_SIZE;
5527 /*
5528 dpb_print(DECODE_ID(hw), 0,
5529 "%s: user data, and len = %d:\n",
5530 __func__, hw->sei_itu_data_len);
5531 */
5532 }
5533 break;
5534 case SEI_RECOVERY_POINT:
5535 p_H264_Dpb->dpb_param.l.data[RECOVERY_POINT] = 1;
5536 break;
5537 }
5538
5539 return read_size + payload_size;
5540}
5541
5542static void parse_sei_data(struct vdec_h264_hw_s *hw,
5543 u8 *sei_data_buf,
5544 int len)
5545{
5546 char *p_sei;
5547 char *p_sei_end;
5548 int parsed_size;
5549 int read_size;
5550
5551
5552 p_sei = sei_data_buf;
5553 p_sei_end = p_sei + len;
5554 parsed_size = 0;
5555 while (parsed_size < len) {
5556 read_size = parse_one_sei_record(hw, p_sei, p_sei_end);
5557 p_sei += read_size;
5558 parsed_size += read_size;
5559 if (*p_sei == 0x80) {
5560 p_sei++;
5561 parsed_size++;
5562 }
5563 }
5564}
5565
5566static void check_decoded_pic_error(struct vdec_h264_hw_s *hw)
5567{
5568 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5569 struct StorablePicture *p = p_H264_Dpb->mVideo.dec_picture;
5570 unsigned mby_mbx = READ_VREG(MBY_MBX);
5571 unsigned mb_total = (hw->seq_info2 >> 8) & 0xffff;
5572 unsigned decode_mb_count =
5573 ((mby_mbx & 0xff) * hw->mb_width +
5574 (((mby_mbx >> 8) & 0xff) + 1));
5575 if (mby_mbx == 0)
5576 return;
5577 if (get_cur_slice_picture_struct(p_H264_Dpb) != FRAME)
5578 mb_total /= 2;
5579
5580 if ((error_proc_policy & 0x200) &&
5581 READ_VREG(ERROR_STATUS_REG) != 0) {
5582 p->data_flag |= ERROR_FLAG;
5583 }
5584
5585 if (error_proc_policy & 0x100) {
5586 if (decode_mb_count < mb_total) {
5587 p->data_flag |= ERROR_FLAG;
5588 if ((error_proc_policy & 0x20000) &&
5589 decode_mb_count >= mb_total * (100 - mb_count_threshold) / 100) {
5590 p->data_flag &= ~ERROR_FLAG;
5591 }
5592 }
5593 }
5594
5595 if (p->data_flag & ERROR_FLAG) {
5596 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
5597 "%s: decode error, seq_info2 0x%x, mby_mbx 0x%x, mb_total %d decoded mb_count %d ERROR_STATUS_REG 0x%x\n",
5598 __func__,
5599 hw->seq_info2,
5600 mby_mbx,
5601 mb_total,
5602 decode_mb_count,
5603 READ_VREG(ERROR_STATUS_REG)
5604 );
5605
5606 }
5607}
5608
5609static int vh264_pic_done_proc(struct vdec_s *vdec)
5610{
5611 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
5612 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5613 int ret;
5614
5615 if (vdec->mvfrm)
5616 vdec->mvfrm->hw_decode_time =
5617 local_clock() - vdec->mvfrm->hw_decode_start;
5618
5619 if (input_frame_based(vdec) &&
5620 (!(hw->i_only & 0x2)) &&
5621 frmbase_cont_bitlevel != 0 &&
5622 READ_VREG(VIFF_BIT_CNT) >
5623 frmbase_cont_bitlevel) {
5624 /*handle the case: multi pictures in one packet*/
5625 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5626 "%s H264_PIC_DATA_DONE decode slice count %d, continue (bitcnt 0x%x)\n",
5627 __func__,
5628 hw->decode_pic_count,
5629 READ_VREG(VIFF_BIT_CNT));
5630 hw->frmbase_cont_flag = 1;
5631 } else
5632 hw->frmbase_cont_flag = 0;
5633
5634 if (p_H264_Dpb->mVideo.dec_picture) {
5635 get_picture_qos_info(p_H264_Dpb->mVideo.dec_picture);
5636#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5637 DEL_EXIST(hw,
5638 p_H264_Dpb->mVideo.dec_picture) = 0;
5639 if (vdec->master) {
5640 struct vdec_h264_hw_s *hw_ba =
5641 (struct vdec_h264_hw_s *)
5642 vdec->master->private;
5643 if (hw_ba->last_dec_picture)
5644 DEL_EXIST(hw_ba,
5645 hw_ba->last_dec_picture)
5646 = 1;
5647 }
5648#endif
5649 mutex_lock(&hw->chunks_mutex);
5650 if (hw->chunk) {
5651 p_H264_Dpb->mVideo.dec_picture->pts =
5652 hw->chunk->pts;
5653 p_H264_Dpb->mVideo.dec_picture->pts64 =
5654 hw->chunk->pts64;
5655 p_H264_Dpb->mVideo.dec_picture->timestamp =
5656 hw->chunk->timestamp;
5657#ifdef MH264_USERDATA_ENABLE
5658 vmh264_udc_fill_vpts(hw,
5659 p_H264_Dpb->mSlice.slice_type,
5660 hw->chunk->pts, 1);
5661#endif
5662
5663#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5664 } else if (vdec->master) {
5665 /*dv enhance layer,
5666 do not checkout pts*/
5667 struct StorablePicture *pic =
5668 p_H264_Dpb->mVideo.dec_picture;
5669 pic->pts = 0;
5670 pic->pts64 = 0;
5671#endif
5672 } else {
5673 struct StorablePicture *pic =
5674 p_H264_Dpb->mVideo.dec_picture;
5675 u32 offset = pic->offset_delimiter;
5676 if (pts_pickout_offset_us64(PTS_TYPE_VIDEO,
5677 offset, &pic->pts, 0, &pic->pts64)) {
5678 pic->pts = 0;
5679 pic->pts64 = 0;
5680#ifdef MH264_USERDATA_ENABLE
5681 vmh264_udc_fill_vpts(hw,
5682 p_H264_Dpb->mSlice.slice_type,
5683 pic->pts, 0);
5684#endif
5685 } else {
5686#ifdef MH264_USERDATA_ENABLE
5687 vmh264_udc_fill_vpts(hw,
5688 p_H264_Dpb->mSlice.slice_type,
5689 pic->pts, 1);
5690#endif
5691 }
5692
5693 }
5694 mutex_unlock(&hw->chunks_mutex);
5695
5696 check_decoded_pic_error(hw);
5697#ifdef ERROR_HANDLE_TEST
5698 if ((hw->data_flag & ERROR_FLAG)
5699 && (error_proc_policy & 0x80)) {
5700 release_cur_decoding_buf(hw);
5701 h264_clear_dpb(hw);
5702 hw->dec_flag = 0;
5703 hw->data_flag = 0;
5704 hw->skip_frame_count = 0;
5705 hw->has_i_frame = 0;
5706 hw->no_error_count = 0xfff;
5707 hw->no_error_i_count = 0xf;
5708 } else
5709#endif
5710 ret = store_picture_in_dpb(p_H264_Dpb,
5711 p_H264_Dpb->mVideo.dec_picture,
5712 hw->data_flag | hw->dec_flag |
5713 p_H264_Dpb->mVideo.dec_picture->data_flag);
5714
5715
5716
5717 if (ret == -1) {
5718 release_cur_decoding_buf(hw);
5719 bufmgr_force_recover(p_H264_Dpb);
5720 } else {
5721 if (hw->data_flag & ERROR_FLAG) {
5722 hw->no_error_count = 0;
5723 hw->no_error_i_count = 0;
5724 } else {
5725 hw->no_error_count++;
5726 if (hw->data_flag & I_FLAG)
5727 hw->no_error_i_count++;
5728 }
5729 if (hw->mmu_enable)
5730 hevc_set_unused_4k_buff_idx(hw,
5731 p_H264_Dpb->mVideo.
5732 dec_picture->buf_spec_num);
5733 bufmgr_post(p_H264_Dpb);
5734 hw->last_dec_picture =
5735 p_H264_Dpb->mVideo.dec_picture;
5736 p_H264_Dpb->mVideo.dec_picture = NULL;
5737 /* dump_dpb(&p_H264_Dpb->mDPB); */
5738 hw->has_i_frame = 1;
5739 if (hw->mmu_enable)
5740 hevc_set_frame_done(hw);
5741 hw->decode_pic_count++;
5742 p_H264_Dpb->decode_pic_count = hw->decode_pic_count;
5743 if (hw->skip_frame_count > 0) {
5744 /*skip n frame after first I */
5745 hw->skip_frame_count--;
5746 if (hw->skip_frame_count == 0)
5747 hw->dec_flag &= (~NODISP_FLAG);
5748 } else if (hw->skip_frame_count < -1) {
5749 /*skip n frame after first I until second I */
5750 hw->skip_frame_count++;
5751 if (hw->skip_frame_count == -1)
5752 hw->dec_flag &= (~NODISP_FLAG);
5753 }
5754 }
5755 }
5756 return 0;
5757}
5758
5759
5760static irqreturn_t vh264_isr_thread_fn(struct vdec_s *vdec, int irq)
5761{
5762 int i;
5763 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
5764 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5765 unsigned int dec_dpb_status = p_H264_Dpb->dec_dpb_status;
5766 u32 debug_tag;
5767
5768 if (dec_dpb_status == H264_CONFIG_REQUEST) {
5769#if 1
5770 unsigned short *p = (unsigned short *)hw->lmem_addr;
5771 for (i = 0; i < (RPM_END-RPM_BEGIN); i += 4) {
5772 int ii;
5773 for (ii = 0; ii < 4; ii++) {
5774 p_H264_Dpb->dpb_param.l.data[i+ii] =
5775 p[i+3-ii];
5776 if (dpb_is_debug(DECODE_ID(hw),
5777 RRINT_FLAG_RPM)) {
5778 if (((i + ii) & 0xf) == 0)
5779 dpb_print(DECODE_ID(hw),
5780 0, "%04x:",
5781 i);
5782 dpb_print_cont(DECODE_ID(hw),
5783 0, "%04x ",
5784 p[i+3-ii]);
5785 if (((i + ii + 1) & 0xf) == 0)
5786 dpb_print_cont(
5787 DECODE_ID(hw),
5788 0, "\r\n");
5789 }
5790 }
5791 }
5792
5793 p_H264_Dpb->bitstream_restriction_flag =
5794 (p_H264_Dpb->dpb_param.l.data[SPS_FLAGS2] >> 3) & 0x1;
5795 p_H264_Dpb->num_reorder_frames =
5796 p_H264_Dpb->dpb_param.l.data[NUM_REORDER_FRAMES];
5797 p_H264_Dpb->max_dec_frame_buffering =
5798 p_H264_Dpb->dpb_param.l.data[MAX_BUFFER_FRAME];
5799
5800 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5801 "H264_CONFIG_REQUEST: pdb %d, %d, %d\n",
5802 p_H264_Dpb->bitstream_restriction_flag,
5803 p_H264_Dpb->num_reorder_frames,
5804 p_H264_Dpb->max_dec_frame_buffering);
5805 hw->bitstream_restriction_flag =
5806 p_H264_Dpb->bitstream_restriction_flag;
5807 hw->num_reorder_frames =
5808 p_H264_Dpb->num_reorder_frames;
5809 hw->max_dec_frame_buffering =
5810 p_H264_Dpb->max_dec_frame_buffering;
5811#endif
5812
5813 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_CONFIG_DONE);
5814 reset_process_time(hw);
5815 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
5816 hw->dec_result = DEC_RESULT_CONFIG_PARAM;
5817#ifdef DETECT_WRONG_MULTI_SLICE
5818 /*restart check count and set 'unknown'*/
5819 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
5820 "%s MULTI_SLICE_DETECT (check_count %d slice_count %d cur_slice_count %d flag %d), H264_CONFIG_REQUEST => restart check\n",
5821 __func__,
5822 hw->multi_slice_pic_check_count,
5823 hw->picture_slice_count,
5824 hw->cur_picture_slice_count,
5825 hw->multi_slice_pic_flag);
5826
5827 hw->multi_slice_pic_check_count = 0;
5828 hw->multi_slice_pic_flag = 0;
5829 hw->picture_slice_count = 0;
5830#endif
5831 vdec_schedule_work(&hw->work);
5832 } else if (dec_dpb_status == H264_SLICE_HEAD_DONE) {
5833 u16 data_hight;
5834 u16 data_low;
5835 u32 video_signal;
5836
5837 int slice_header_process_status = 0;
5838 int I_flag;
5839 int frame_num_gap = 0;
5840 /*unsigned char is_idr;*/
5841 unsigned short *p = (unsigned short *)hw->lmem_addr;
5842 reset_process_time(hw);
5843
5844#ifdef DETECT_WRONG_MULTI_SLICE
5845 hw->cur_picture_slice_count++;
5846 if (hw->multi_slice_pic_flag == 1 &&
5847 hw->cur_picture_slice_count == 1 &&
5848 (error_proc_policy & 0x10000)) {
5849 hw->first_pre_frame_num = p_H264_Dpb->mVideo.pre_frame_num;
5850 }
5851 if (hw->multi_slice_pic_flag == 1 &&
5852 hw->cur_picture_slice_count > 1 &&
5853 (error_proc_policy & 0x10000)) {
5854 dpb_print(DECODE_ID(hw), 0,
5855 "%s MULTI_SLICE_DETECT (check_count %d slice_count %d cur_slice_count %d flag %d), WRONG_MULTI_SLICE detected, insert picture\n",
5856 __func__,
5857 hw->multi_slice_pic_check_count,
5858 hw->picture_slice_count,
5859 hw->cur_picture_slice_count,
5860 hw->multi_slice_pic_flag);
5861 if (hw->cur_picture_slice_count > hw->last_picture_slice_count)
5862 vh264_pic_done_proc(vdec);
5863 else {
5864 if (p_H264_Dpb->mVideo.dec_picture) {
5865 if (p_H264_Dpb->mVideo.dec_picture->colocated_buf_index >= 0) {
5866 release_colocate_buf(p_H264_Dpb,
5867 p_H264_Dpb->mVideo.dec_picture->colocated_buf_index);
5868 p_H264_Dpb->mVideo.dec_picture->colocated_buf_index = -1;
5869 }
5870 }
5871 release_cur_decoding_buf(hw);
5872 }
5873 }
5874#endif
5875
5876 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
5877 hw->reg_vcop_ctrl_reg = READ_VREG(VCOP_CTRL_REG);
5878 hw->reg_rv_ai_mb_count = READ_VREG(RV_AI_MB_COUNT);
5879 hw->vld_dec_control = READ_VREG(VLD_DECODE_CONTROL);
5880 if (input_frame_based(vdec) &&
5881 frmbase_cont_bitlevel2 != 0 &&
5882 READ_VREG(VIFF_BIT_CNT) <
5883 frmbase_cont_bitlevel2 &&
5884 hw->get_data_count >= 0x70000000) {
5885 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5886 "%s H264_SLICE_HEAD_DONE with small bitcnt %d, goto empty_proc\n",
5887 __func__,
5888 READ_VREG(VIFF_BIT_CNT));
5889
5890 goto empty_proc;
5891 }
5892
5893#if 0
5894 if (p_H264_Dpb->mVideo.dec_picture == NULL) {
5895 if (!is_buffer_available(vdec)) {
5896 hw->buffer_empty_flag = 1;
5897 dpb_print(DECODE_ID(hw),
5898 PRINT_FLAG_UCODE_EVT,
5899 "%s, buffer_empty, newframe_q(%d), have_free_buf_spec(%d), init_done(%d), used_size(%d/%d), is_there_unused_frame_from_dpb(%d)\n",
5900 __func__,
5901 kfifo_len(&hw->newframe_q),
5902 have_free_buf_spec(vdec),
5903 p_H264_Dpb->mDPB.init_done,
5904 p_H264_Dpb->mDPB.used_size,
5905 p_H264_Dpb->mDPB.size,
5906 is_there_unused_frame_from_dpb(
5907 &p_H264_Dpb->mDPB));
5908 return IRQ_HANDLED;
5909 }
5910 }
5911
5912 hw->buffer_empty_flag = 0;
5913#endif
5914#ifdef SEND_PARAM_WITH_REG
5915 for (i = 0; i < (RPM_END-RPM_BEGIN); i++) {
5916 unsigned int data32;
5917
5918 do {
5919 data32 = READ_VREG(RPM_CMD_REG);
5920 /* printk("%x\n", data32); */
5921 } while ((data32&0x10000) == 0);
5922 p_H264_Dpb->dpb_param.l.data[i] = data32 & 0xffff;
5923 WRITE_VREG(RPM_CMD_REG, 0);
5924 /* printk("%x:%x\n", i,data32); */
5925 }
5926#else
5927 for (i = 0; i < (RPM_END-RPM_BEGIN); i += 4) {
5928 int ii;
5929
5930 for (ii = 0; ii < 4; ii++) {
5931 p_H264_Dpb->dpb_param.l.data[i+ii] =
5932 p[i+3-ii];
5933 if (dpb_is_debug(DECODE_ID(hw),
5934 RRINT_FLAG_RPM)) {
5935 if (((i + ii) & 0xf) == 0)
5936 dpb_print(DECODE_ID(hw),
5937 0, "%04x:",
5938 i);
5939 dpb_print_cont(DECODE_ID(hw),
5940 0, "%04x ",
5941 p[i+3-ii]);
5942 if (((i + ii + 1) & 0xf) == 0)
5943 dpb_print_cont(
5944 DECODE_ID(hw),
5945 0, "\r\n");
5946 }
5947 }
5948 }
5949#endif
5950 data_low = p_H264_Dpb->dpb_param.l.data[VIDEO_SIGNAL_LOW];
5951 data_hight = p_H264_Dpb->dpb_param.l.data[VIDEO_SIGNAL_HIGHT];
5952
5953 video_signal = (data_hight << 16) | data_low;
5954 hw->video_signal_from_vui =
5955 ((video_signal & 0xffff) << 8) |
5956 ((video_signal & 0xff0000) >> 16) |
5957 ((video_signal & 0x3f000000));
5958
5959
5960 /*dpb_print(DECODE_ID(hw),
5961 0,
5962 "video_signal_from_vui:0x%x, "
5963 "data_low:0x%x, data_hight:0x%x\n",
5964 hw->video_signal_from_vui,
5965 data_low,
5966 data_hight);*/
5967
5968 parse_sei_data(hw, hw->sei_data_buf, hw->sei_data_len);
5969
5970 if (hw->config_bufmgr_done == 0) {
5971 hw->dec_result = DEC_RESULT_DONE;
5972 vdec_schedule_work(&hw->work);
5973 dpb_print(DECODE_ID(hw),
5974 PRINT_FLAG_UCODE_EVT,
5975 "config_bufmgr not done, discard frame\n");
5976 return IRQ_HANDLED;
5977 } else if ((hw->first_i_policy & 0x3) != 0) {
5978 unsigned char is_i_slice =
5979 (p_H264_Dpb->dpb_param.l.data[SLICE_TYPE]
5980 == I_Slice)
5981 ? 1 : 0;
5982 unsigned char is_idr =
5983 ((p_H264_Dpb->dpb_param.dpb.NAL_info_mmco & 0x1f)
5984 == 5);
5985 if ((hw->first_i_policy & 0x3) == 0x3)
5986 is_i_slice = is_idr;
5987 if (!is_i_slice) {
5988 if (hw->has_i_frame == 0) {
5989 amvdec_stop();
5990 vdec->mc_loaded = 0;
5991 hw->dec_result = DEC_RESULT_DONE;
5992 vdec_schedule_work(&hw->work);
5993 dpb_print(DECODE_ID(hw),
5994 PRINT_FLAG_UCODE_EVT,
5995 "has_i_frame is 0, discard none I(DR) frame\n");
5996 return IRQ_HANDLED;
5997 }
5998 } else {
5999 if (hw->skip_frame_count < 0 || is_idr) {
6000 /* second I */
6001 hw->dec_flag &= (~NODISP_FLAG);
6002 hw->skip_frame_count = 0;
6003 }
6004 if (hw->has_i_frame == 0 &&
6005 (!is_idr)) {
6006 int skip_count =
6007 (hw->first_i_policy >> 8) & 0xff;
6008 /* first I (not IDR) */
6009 if ((hw->first_i_policy & 0x3) == 2)
6010 hw->skip_frame_count =
6011 -1 - skip_count;
6012 else
6013 hw->skip_frame_count =
6014 skip_count;
6015 if (hw->skip_frame_count != 0)
6016 hw->dec_flag |= NODISP_FLAG;
6017 }
6018 }
6019 }
6020 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
6021 "current dpb index %d, poc %d, top/bot poc (%d,%d)\n",
6022 p_H264_Dpb->dpb_param.dpb.current_dpb_index,
6023 val(p_H264_Dpb->dpb_param.dpb.frame_pic_order_cnt),
6024 val(p_H264_Dpb->dpb_param.dpb.top_field_pic_order_cnt),
6025 val(p_H264_Dpb->dpb_param.dpb.top_field_pic_order_cnt));
6026 I_flag = (p_H264_Dpb->dpb_param.l.data[SLICE_TYPE] == I_Slice)
6027 ? I_FLAG : 0;
6028
6029 if ((hw->i_only & 0x2) && (I_flag & I_FLAG))
6030 flush_dpb(p_H264_Dpb);
6031
6032 if ((hw->i_only & 0x2) && (!(I_flag & I_FLAG)) &&
6033 (p_H264_Dpb->mSlice.structure == FRAME)) {
6034 hw->data_flag = NULL_FLAG;
6035 goto pic_done_proc;
6036 }
6037
6038 slice_header_process_status =
6039 h264_slice_header_process(p_H264_Dpb, &frame_num_gap);
6040 if (hw->mmu_enable)
6041 hevc_sao_set_slice_type(hw,
6042 slice_header_process_status,
6043 hw->dpb.mSlice.idr_flag);
6044 vui_config(hw);
6045
6046 if (p_H264_Dpb->mVideo.dec_picture) {
6047 int cfg_ret = 0;
6048 bool field_pic_flag = false;
6049
6050 if (slice_header_process_status == 1) {
6051 if (!p_H264_Dpb->mSPS.frame_mbs_only_flag) {
6052 field_pic_flag =
6053 (p_H264_Dpb->mSlice.structure == TOP_FIELD ||
6054 p_H264_Dpb->mSlice.structure == BOTTOM_FIELD) ?
6055 true : false;
6056 }
6057
6058 if (!field_pic_flag && (((p_H264_Dpb->mSPS.profile_idc == BASELINE) &&
6059 (p_H264_Dpb->reorder_pic_num < 2)) ||
6060 (((unsigned long)(hw->vh264_amstream_dec_info
6061 .param)) & 0x8))) {
6062 p_H264_Dpb->fast_output_enable =
6063 H264_OUTPUT_MODE_FAST;
6064 }
6065 else
6066 p_H264_Dpb->fast_output_enable
6067 = fast_output_enable;
6068 hw->data_flag = I_flag;
6069 if ((p_H264_Dpb->
6070 dpb_param.dpb.NAL_info_mmco & 0x1f)
6071 == 5)
6072 hw->data_flag |= IDR_FLAG;
6073 dpb_print(DECODE_ID(hw),
6074 PRINT_FLAG_VDEC_STATUS,
6075 "==================> frame count %d to skip %d\n",
6076 hw->decode_pic_count+1,
6077 hw->skip_frame_count);
6078 } else if (error_proc_policy & 0x100){
6079 struct StorablePicture *p =
6080 p_H264_Dpb->mVideo.dec_picture;
6081 unsigned mby_mbx = READ_VREG(MBY_MBX);
6082 unsigned decode_mb_count =
6083 ((mby_mbx & 0xff) * hw->mb_width +
6084 (((mby_mbx >> 8) & 0xff) + 1));
6085 if (decode_mb_count <
6086 ((p_H264_Dpb->dpb_param.l.data[FIRST_MB_IN_SLICE]) *
6087 (1 + p->mb_aff_frame_flag))) {
6088 dpb_print(DECODE_ID(hw),
6089 PRINT_FLAG_VDEC_STATUS,
6090 "Error detect! first_mb 0x%x mby_mbx 0x%x decode_mb 0x%x\n",
6091 p_H264_Dpb->dpb_param.l.
6092 data[FIRST_MB_IN_SLICE],
6093 READ_VREG(MBY_MBX),
6094 decode_mb_count);
6095 p->data_flag |= ERROR_FLAG;
6096 }/* else if (!p_H264_Dpb->dpb_param.l.data[FIRST_MB_IN_SLICE] && decode_mb_count) {
6097 p->data_flag |= ERROR_FLAG;
6098 goto pic_done_proc;
6099 }*/
6100 }
6101
6102 if (!I_flag && frame_num_gap) {
6103 hw->data_flag |= ERROR_FLAG;
6104 p_H264_Dpb->mVideo.dec_picture->data_flag |= ERROR_FLAG;
6105 dpb_print(DECODE_ID(hw), 0, "frame number gap error\n");
6106 }
6107
6108 if (error_proc_policy & 0x400) {
6109 int ret = dpb_check_ref_list_error(p_H264_Dpb);
6110 if (ret != 0) {
6111 hw->reflist_error_count ++;
6112 dpb_print(DECODE_ID(hw), 0,
6113 "reference list error %d frame count %d to skip %d reflist_error_count %d\n",
6114 ret,
6115 hw->decode_pic_count+1,
6116 hw->skip_frame_count,
6117 hw->reflist_error_count);
6118
6119 p_H264_Dpb->mVideo.dec_picture->data_flag = NODISP_FLAG;
6120 if (((error_proc_policy & 0x80)
6121 && ((hw->dec_flag &
6122 NODISP_FLAG) == 0)) ||(hw->reflist_error_count > 50)) {
6123 hw->reset_bufmgr_flag = 1;
6124 hw->reflist_error_count =0;
6125 amvdec_stop();
6126 vdec->mc_loaded = 0;
6127 hw->dec_result = DEC_RESULT_DONE;
6128 vdec_schedule_work(&hw->work);
6129 return IRQ_HANDLED;
6130 }
6131 } else
6132 hw->reflist_error_count = 0;
6133 }
6134 if ((error_proc_policy & 0x800) && (!(hw->i_only & 0x2))
6135 && p_H264_Dpb->dpb_error_flag != 0) {
6136 dpb_print(DECODE_ID(hw), 0,
6137 "dpb error %d\n",
6138 p_H264_Dpb->dpb_error_flag);
6139 hw->data_flag |= ERROR_FLAG;
6140 p_H264_Dpb->mVideo.dec_picture->data_flag |= ERROR_FLAG;
6141 if ((error_proc_policy & 0x80) &&
6142 ((hw->dec_flag & NODISP_FLAG) == 0)) {
6143 hw->reset_bufmgr_flag = 1;
6144 amvdec_stop();
6145 vdec->mc_loaded = 0;
6146 hw->dec_result = DEC_RESULT_DONE;
6147 vdec_schedule_work(&hw->work);
6148 return IRQ_HANDLED;
6149 }
6150 }
6151
6152 cfg_ret = config_decode_buf(hw,
6153 p_H264_Dpb->mVideo.dec_picture);
6154 if (cfg_ret < 0) {
6155 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
6156 "config_decode_buf fail (%d)\n",
6157 cfg_ret);
6158 if (error_proc_policy & 0x2) {
6159 release_cur_decoding_buf(hw);
6160 /*hw->data_flag |= ERROR_FLAG;*/
6161 hw->reset_bufmgr_flag = 1;
6162 hw->dec_result = DEC_RESULT_DONE;
6163 vdec_schedule_work(&hw->work);
6164 return IRQ_HANDLED;
6165 } else
6166 hw->data_flag |= ERROR_FLAG;
6167 p_H264_Dpb->mVideo.dec_picture->data_flag |= ERROR_FLAG;
6168 }
6169 }
6170
6171 if (slice_header_process_status == 1)
6172 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_NEWPIC);
6173 else
6174 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_SLICE);
6175 hw->last_mby_mbx = 0;
6176 hw->last_vld_level = 0;
6177 start_process_time(hw);
6178 } else if (dec_dpb_status == H264_PIC_DATA_DONE
6179 ||((dec_dpb_status == H264_DATA_REQUEST) && input_frame_based(vdec))) {
6180#ifdef DETECT_WRONG_MULTI_SLICE
6181 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
6182 "%s MULTI_SLICE_DETECT (check_count %d slice_count %d cur_slice_count %d flag %d), H264_PIC_DATA_DONE\n",
6183 __func__,
6184 hw->multi_slice_pic_check_count,
6185 hw->picture_slice_count,
6186 hw->cur_picture_slice_count,
6187 hw->multi_slice_pic_flag);
6188
6189 if (hw->multi_slice_pic_check_count < check_slice_num) {
6190 hw->multi_slice_pic_check_count++;
6191 if (hw->cur_picture_slice_count !=
6192 hw->picture_slice_count) {
6193 /*restart check count and set 'unknown'*/
6194 hw->multi_slice_pic_check_count = 0;
6195 hw->multi_slice_pic_flag = 0;
6196 }
6197 hw->picture_slice_count =
6198 hw->cur_picture_slice_count;
6199 } else if (hw->multi_slice_pic_check_count >= check_slice_num) {
6200 if (hw->picture_slice_count > 1)
6201 hw->multi_slice_pic_flag = 2;
6202 else
6203 hw->multi_slice_pic_flag = 1;
6204 }
6205#endif
6206
6207pic_done_proc:
6208 reset_process_time(hw);
6209 vh264_pic_done_proc(vdec);
6210
6211 if (hw->frmbase_cont_flag) {
6212 /*do not DEC_RESULT_GET_DATA*/
6213 hw->get_data_count = 0x7fffffff;
6214 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
6215 decode_frame_count[DECODE_ID(hw)]++;
6216 start_process_time(hw);
6217 return IRQ_HANDLED;
6218 }
6219 amvdec_stop();
6220 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6221 "%s %s decode slice count %d\n",
6222 __func__,
6223 (dec_dpb_status == H264_PIC_DATA_DONE) ?
6224 "H264_PIC_DATA_DONE" :
6225 (dec_dpb_status == H264_FIND_NEXT_PIC_NAL) ?
6226 "H264_FIND_NEXT_PIC_NAL" : "H264_FIND_NEXT_DVEL_NAL",
6227 hw->decode_pic_count);
6228 /* WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD); */
6229 hw->dec_result = DEC_RESULT_DONE;
6230#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
6231 if (vdec->slave &&
6232 dec_dpb_status == H264_FIND_NEXT_DVEL_NAL) {
6233 struct vdec_h264_hw_s *hw_el =
6234 (struct vdec_h264_hw_s *)(vdec->slave->private);
6235 hw_el->got_valid_nal = 0;
6236 hw->switch_dvlayer_flag = 1;
6237 } else if (vdec->master &&
6238 dec_dpb_status == H264_FIND_NEXT_PIC_NAL) {
6239 struct vdec_h264_hw_s *hw_bl =
6240 (struct vdec_h264_hw_s *)(vdec->master->private);
6241 hw_bl->got_valid_nal = 0;
6242 hw->switch_dvlayer_flag = 1;
6243 } else {
6244 hw->switch_dvlayer_flag = 0;
6245 hw->got_valid_nal = 1;
6246 }
6247#endif
6248
6249 hw->dec_result = DEC_RESULT_DONE;
6250 vdec_schedule_work(&hw->work);
6251
6252#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
6253 } else if (
6254 (dec_dpb_status == H264_FIND_NEXT_PIC_NAL) ||
6255 (dec_dpb_status == H264_FIND_NEXT_DVEL_NAL)) {
6256 goto pic_done_proc;
6257#endif
6258 } else if (dec_dpb_status == H264_AUX_DATA_READY) {
6259 reset_process_time(hw);
6260 if (READ_VREG(H264_AUX_DATA_SIZE) != 0) {
6261 if (dpb_is_debug(DECODE_ID(hw),
6262 PRINT_FLAG_DPB_DETAIL))
6263 dump_aux_buf(hw);
6264#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
6265 if (vdec->dolby_meta_with_el || vdec->slave) {
6266 if (hw->last_dec_picture)
6267 set_aux_data(hw, hw->last_dec_picture,
6268 0, 0, NULL);
6269 } else {
6270 if (vdec->master) {
6271 struct vdec_h264_hw_s *hw_bl =
6272 (struct vdec_h264_hw_s *)
6273 (vdec->master->private);
6274 if (hw_bl->last_dec_picture != NULL) {
6275 set_aux_data(hw_bl,
6276 hw_bl->last_dec_picture,
6277 0, 1, hw);
6278 }
6279 set_aux_data(hw,
6280 hw->last_dec_picture,
6281 0, 2, NULL);
6282 }
6283 }
6284#else
6285 if (hw->last_dec_picture)
6286 set_aux_data(hw,
6287 hw->last_dec_picture, 0, 0, NULL);
6288#endif
6289 }
6290#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
6291 hw->switch_dvlayer_flag = 0;
6292 hw->got_valid_nal = 1;
6293#endif
6294 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6295 "%s H264_AUX_DATA_READY\n", __func__);
6296 hw->dec_result = DEC_RESULT_DONE;
6297 vdec_schedule_work(&hw->work);
6298 } else if (/*(dec_dpb_status == H264_DATA_REQUEST) ||*/
6299 (dec_dpb_status == H264_SEARCH_BUFEMPTY) ||
6300 (dec_dpb_status == H264_DECODE_BUFEMPTY) ||
6301 (dec_dpb_status == H264_DECODE_TIMEOUT)) {
6302empty_proc:
6303 reset_process_time(hw);
6304 if ((error_proc_policy & 0x40000) &&
6305 dec_dpb_status == H264_DECODE_TIMEOUT)
6306 goto pic_done_proc;
6307 if (!hw->frmbase_cont_flag)
6308 release_cur_decoding_buf(hw);
6309
6310 if (input_frame_based(vdec) ||
6311 (READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0x200)) {
6312 if (h264_debug_flag &
6313 DISABLE_ERROR_HANDLE) {
6314 dpb_print(DECODE_ID(hw),
6315 PRINT_FLAG_ERROR,
6316 "%s decoding error, level 0x%x\n",
6317 __func__,
6318 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
6319 goto send_again;
6320 }
6321 amvdec_stop();
6322 vdec->mc_loaded = 0;
6323 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6324 "%s %s\n", __func__,
6325 (dec_dpb_status == H264_SEARCH_BUFEMPTY) ?
6326 "H264_SEARCH_BUFEMPTY" :
6327 (dec_dpb_status == H264_DECODE_BUFEMPTY) ?
6328 "H264_DECODE_BUFEMPTY" :
6329 (dec_dpb_status == H264_DECODE_TIMEOUT) ?
6330 "H264_DECODE_TIMEOUT" :
6331 "OTHER");
6332 hw->dec_result = DEC_RESULT_DONE;
6333
6334 if (dec_dpb_status == H264_SEARCH_BUFEMPTY)
6335 hw->search_dataempty_num++;
6336 else if (dec_dpb_status == H264_DECODE_TIMEOUT) {
6337 hw->decode_timeout_num++;
6338 if (error_proc_policy & 0x4000) {
6339 hw->data_flag |= ERROR_FLAG;
6340 if ((p_H264_Dpb->last_dpb_status == H264_DECODE_TIMEOUT) ||
6341 (p_H264_Dpb->last_dpb_status == H264_PIC_DATA_DONE) ||
6342 ((p_H264_Dpb->last_dpb_status == H264_SLICE_HEAD_DONE) &&
6343 (p_H264_Dpb->mSlice.slice_type != B_SLICE))) {
6344 dpb_print(DECODE_ID(hw),
6345 PRINT_FLAG_ERROR, "%s last dpb status 0x%x need bugmgr reset \n",
6346 p_H264_Dpb->last_dpb_status, __func__);
6347 hw->reset_bufmgr_flag = 1;
6348 }
6349 }
6350 } else if (dec_dpb_status == H264_DECODE_BUFEMPTY)
6351 hw->decode_dataempty_num++;
6352 if (!hw->frmbase_cont_flag)
6353 hw->data_flag |= ERROR_FLAG;
6354
6355 vdec_schedule_work(&hw->work);
6356 } else {
6357 /* WRITE_VREG(DPB_STATUS_REG, H264_ACTION_INIT); */
6358#ifdef DETECT_WRONG_MULTI_SLICE
6359 if (hw->multi_slice_pic_flag == 1 &&
6360 hw->cur_picture_slice_count > 1 &&
6361 (error_proc_policy & 0x10000)) {
6362 p_H264_Dpb->mVideo.pre_frame_num = hw->first_pre_frame_num;
6363 }
6364 hw->last_picture_slice_count = hw->cur_picture_slice_count;
6365#endif
6366 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6367 "%s DEC_RESULT_AGAIN\n", __func__);
6368send_again:
6369 hw->dec_result = DEC_RESULT_AGAIN;
6370 vdec_schedule_work(&hw->work);
6371 }
6372 } else if (dec_dpb_status == H264_DATA_REQUEST) {
6373 reset_process_time(hw);
6374 if (input_frame_based(vdec)) {
6375 dpb_print(DECODE_ID(hw),
6376 PRINT_FLAG_VDEC_STATUS,
6377 "%s H264_DATA_REQUEST (%d)\n",
6378 __func__, hw->get_data_count);
6379 hw->dec_result = DEC_RESULT_GET_DATA;
6380 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
6381 hw->get_data_start_time = jiffies;
6382 hw->get_data_count++;
6383 if (hw->get_data_count >= frame_max_data_packet)
6384 goto empty_proc;
6385 vdec_schedule_work(&hw->work);
6386 } else
6387 goto empty_proc;
6388 } else if (dec_dpb_status == H264_DECODE_OVER_SIZE) {
6389 dpb_print(DECODE_ID(hw), 0,
6390 "vmh264 decode oversize !!\n");
6391 release_cur_decoding_buf(hw);
6392 hw->data_flag |= ERROR_FLAG;
6393 hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
6394 reset_process_time(hw);
6395 hw->dec_result = DEC_RESULT_DONE;
6396 vdec_schedule_work(&hw->work);
6397 return IRQ_HANDLED;
6398 } else if (dec_dpb_status == H264_SEI_DATA_READY) {
6399 int aux_data_len;
6400 aux_data_len =
6401 (READ_VREG(H264_AUX_DATA_SIZE) >> 16) << 4;
6402
6403 if (aux_data_len > SEI_DATA_SIZE) {
6404 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
6405 "sei data size more than 4K: %d, discarded it\n",
6406 hw->sei_itu_data_len);
6407 hw->sei_itu_data_len = 0;
6408 }
6409
6410 if (aux_data_len != 0) {
6411 u8 *trans_data_buf;
6412 u8 *sei_data_buf;
6413 u8 swap_byte;
6414
6415#if 0
6416 dump_aux_buf(hw);
6417#endif
6418 trans_data_buf = (u8 *)hw->aux_addr;
6419
6420 if (trans_data_buf[7] == AUX_TAG_SEI) {
6421 int left_len;
6422
6423 sei_data_buf = (u8 *)hw->sei_data_buf
6424 + hw->sei_data_len;
6425 left_len = SEI_DATA_SIZE - hw->sei_data_len;
6426 if (aux_data_len/2 <= left_len) {
6427 for (i = 0; i < aux_data_len/2; i++)
6428 sei_data_buf[i]
6429 = trans_data_buf[i*2];
6430
6431 aux_data_len = aux_data_len / 2;
6432 for (i = 0; i < aux_data_len; i = i+4) {
6433 swap_byte = sei_data_buf[i];
6434 sei_data_buf[i]
6435 = sei_data_buf[i+3];
6436 sei_data_buf[i+3] = swap_byte;
6437
6438 swap_byte = sei_data_buf[i+1];
6439 sei_data_buf[i+1]
6440 = sei_data_buf[i+2];
6441 sei_data_buf[i+2] = swap_byte;
6442 }
6443
6444 for (i = aux_data_len-1; i >= 0; i--)
6445 if (sei_data_buf[i] != 0)
6446 break;
6447
6448 hw->sei_data_len += i+1;
6449 } else
6450 dpb_print(DECODE_ID(hw),
6451 PRINT_FLAG_ERROR,
6452 "sei data size %d and more than left space: %d, discarded it\n",
6453 hw->sei_itu_data_len,
6454 left_len);
6455 }
6456 }
6457 WRITE_VREG(DPB_STATUS_REG, H264_SEI_DATA_DONE);
6458
6459 return IRQ_HANDLED;
6460 }
6461
6462
6463 /* ucode debug */
6464 debug_tag = READ_VREG(DEBUG_REG1);
6465 if (debug_tag & 0x10000) {
6466 unsigned short *p = (unsigned short *)hw->lmem_addr;
6467
6468 dpb_print(DECODE_ID(hw), 0,
6469 "LMEM<tag %x>:\n", debug_tag);
6470 for (i = 0; i < 0x400; i += 4) {
6471 int ii;
6472 if ((i & 0xf) == 0)
6473 dpb_print_cont(DECODE_ID(hw), 0,
6474 "%03x: ", i);
6475 for (ii = 0; ii < 4; ii++)
6476 dpb_print_cont(DECODE_ID(hw), 0,
6477 "%04x ", p[i+3-ii]);
6478 if (((i+ii) & 0xf) == 0)
6479 dpb_print_cont(DECODE_ID(hw), 0,
6480 "\n");
6481 }
6482 if (((udebug_pause_pos & 0xffff)
6483 == (debug_tag & 0xffff)) &&
6484 (udebug_pause_decode_idx == 0 ||
6485 udebug_pause_decode_idx ==
6486 hw->decode_pic_count) &&
6487 (udebug_pause_val == 0 ||
6488 udebug_pause_val == READ_VREG(DEBUG_REG2))) {
6489 udebug_pause_pos &= 0xffff;
6490 hw->ucode_pause_pos = udebug_pause_pos;
6491 }
6492 else if (debug_tag & 0x20000)
6493 hw->ucode_pause_pos = 0xffffffff;
6494 if (hw->ucode_pause_pos)
6495 reset_process_time(hw);
6496 else
6497 WRITE_VREG(DEBUG_REG1, 0);
6498 } else if (debug_tag != 0) {
6499 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
6500 "dbg%x: %x\n", debug_tag,
6501 READ_VREG(DEBUG_REG2));
6502 if (((udebug_pause_pos & 0xffff)
6503 == (debug_tag & 0xffff)) &&
6504 (udebug_pause_decode_idx == 0 ||
6505 udebug_pause_decode_idx ==
6506 hw->decode_pic_count) &&
6507 (udebug_pause_val == 0 ||
6508 udebug_pause_val == READ_VREG(DEBUG_REG2))) {
6509 udebug_pause_pos &= 0xffff;
6510 hw->ucode_pause_pos = udebug_pause_pos;
6511 }
6512 if (hw->ucode_pause_pos)
6513 reset_process_time(hw);
6514 else
6515 WRITE_VREG(DEBUG_REG1, 0);
6516 }
6517 /**/
6518 return IRQ_HANDLED;
6519}
6520
6521static irqreturn_t vh264_isr(struct vdec_s *vdec, int irq)
6522{
6523 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
6524 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6525
6526
6527 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
6528
6529 if (!hw)
6530 return IRQ_HANDLED;
6531
6532 if (hw->eos)
6533 return IRQ_HANDLED;
6534
6535 p_H264_Dpb->vdec = vdec;
6536 p_H264_Dpb->dec_dpb_status = READ_VREG(DPB_STATUS_REG);
6537
6538 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
6539 "%s DPB_STATUS_REG: 0x%x, run(%d) last_state (%x) ERROR_STATUS_REG 0x%x, sb (0x%x 0x%x 0x%x) bitcnt 0x%x mby_mbx 0x%x\n",
6540 __func__,
6541 p_H264_Dpb->dec_dpb_status,
6542 run_count[DECODE_ID(hw)],
6543 hw->dec_result,
6544 READ_VREG(ERROR_STATUS_REG),
6545 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
6546 READ_VREG(VLD_MEM_VIFIFO_WP),
6547 READ_VREG(VLD_MEM_VIFIFO_RP),
6548 READ_VREG(VIFF_BIT_CNT),
6549 READ_VREG(MBY_MBX));
6550
6551 if (p_H264_Dpb->dec_dpb_status == H264_WRRSP_REQUEST) {
6552 if (hw->mmu_enable)
6553 hevc_sao_wait_done(hw);
6554 WRITE_VREG(DPB_STATUS_REG, H264_WRRSP_DONE);
6555 return IRQ_HANDLED;
6556 }
6557 return IRQ_WAKE_THREAD;
6558
6559}
6560
6561static void timeout_process(struct vdec_h264_hw_s *hw)
6562{
6563 struct vdec_s *vdec = hw_to_vdec(hw);
6564 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6565
6566 /*
6567 * In this very timeout point,the vh264_work arrives,
6568 * let it to handle the scenario.
6569 */
6570 if (work_pending(&hw->work))
6571 return;
6572
6573 hw->timeout_num++;
6574 amvdec_stop();
6575 vdec->mc_loaded = 0;
6576 if (hw->mmu_enable) {
6577 hevc_set_frame_done(hw);
6578 hevc_sao_wait_done(hw);
6579 }
6580 if (!hw->i_only && (error_proc_policy & 0x2))
6581 flush_dpb(p_H264_Dpb);
6582 dpb_print(DECODE_ID(hw),
6583 PRINT_FLAG_ERROR, "%s decoder timeout\n", __func__);
6584 release_cur_decoding_buf(hw);
6585 hw->dec_result = DEC_RESULT_DONE;
6586 hw->data_flag |= ERROR_FLAG;
6587
6588 if (work_pending(&hw->work))
6589 return;
6590 vdec_schedule_work(&hw->timeout_work);
6591}
6592
6593static void dump_bufspec(struct vdec_h264_hw_s *hw,
6594 const char *caller)
6595{
6596 int i;
6597 dpb_print(DECODE_ID(hw), 0,
6598 "%s in %s:\n", __func__, caller);
6599 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
6600 if (hw->buffer_spec[i].used == -1)
6601 continue;
6602 dpb_print(DECODE_ID(hw), 0,
6603 "bufspec (%d): used %d adr 0x%x canvas(%d) vf_ref(%d) ",
6604 i, hw->buffer_spec[i].used,
6605 hw->buffer_spec[i].buf_adr,
6606 hw->buffer_spec[i].canvas_pos,
6607 hw->buffer_spec[i].vf_ref
6608 );
6609#ifdef CONFIG_AM_VDEC_DV
6610 dpb_print_cont(DECODE_ID(hw), 0,
6611 "dv_el_exist %d",
6612 hw->buffer_spec[i].dv_enhance_exist
6613 );
6614#endif
6615 dpb_print_cont(DECODE_ID(hw), 0, "\n");
6616 }
6617
6618}
6619
6620static void vmh264_dump_state(struct vdec_s *vdec)
6621{
6622 struct vdec_h264_hw_s *hw =
6623 (struct vdec_h264_hw_s *)(vdec->private);
6624 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6625 dpb_print(DECODE_ID(hw), 0,
6626 "====== %s\n", __func__);
6627 dpb_print(DECODE_ID(hw), 0,
6628 "width/height (%d/%d), reorder_pic_num %d dpb size(bufspec count) %d max_reference_size(collocate count) %d i_only %d send_err %d\n",
6629 hw->frame_width,
6630 hw->frame_height,
6631 hw->dpb.reorder_pic_num,
6632 hw->dpb.mDPB.size,
6633 hw->max_reference_size,
6634 hw->i_only,
6635 hw->send_error_frame_flag
6636 );
6637
6638 dpb_print(DECODE_ID(hw), 0,
6639 "is_framebase(%d), eos %d, state 0x%x, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d bufmgr_reset_cnt %d error_frame_count = %d, drop_frame_count = %d\n",
6640 input_frame_based(vdec),
6641 hw->eos,
6642 hw->stat,
6643 hw->dec_result,
6644 decode_frame_count[DECODE_ID(hw)],
6645 display_frame_count[DECODE_ID(hw)],
6646 run_count[DECODE_ID(hw)],
6647 not_run_ready[DECODE_ID(hw)],
6648 input_empty[DECODE_ID(hw)],
6649 hw->reset_bufmgr_count,
6650 hw->gvs.error_frame_count,
6651 hw->gvs.drop_frame_count
6652 );
6653
6654#ifdef DETECT_WRONG_MULTI_SLICE
6655 dpb_print(DECODE_ID(hw), 0,
6656 "MULTI_SLICE_DETECT (check_count %d slice_count %d cur_slice_count %d flag %d)\n",
6657 hw->multi_slice_pic_check_count,
6658 hw->picture_slice_count,
6659 hw->cur_picture_slice_count,
6660 hw->multi_slice_pic_flag);
6661#endif
6662
6663
6664 if (vf_get_receiver(vdec->vf_provider_name)) {
6665 enum receviver_start_e state =
6666 vf_notify_receiver(vdec->vf_provider_name,
6667 VFRAME_EVENT_PROVIDER_QUREY_STATE,
6668 NULL);
6669 dpb_print(DECODE_ID(hw), 0,
6670 "\nreceiver(%s) state %d\n",
6671 vdec->vf_provider_name,
6672 state);
6673 }
6674
6675 dpb_print(DECODE_ID(hw), 0,
6676 "%s, newq(%d/%d), dispq(%d/%d) vf prepare/get/put (%d/%d/%d), free_spec(%d), initdon(%d), used_size(%d/%d), unused_fr_dpb(%d) fast_output_enable %x \n",
6677 __func__,
6678 kfifo_len(&hw->newframe_q),
6679 VF_POOL_SIZE,
6680 kfifo_len(&hw->display_q),
6681 VF_POOL_SIZE,
6682 hw->vf_pre_count,
6683 hw->vf_get_count,
6684 hw->vf_put_count,
6685 have_free_buf_spec(vdec),
6686 p_H264_Dpb->mDPB.init_done,
6687 p_H264_Dpb->mDPB.used_size, p_H264_Dpb->mDPB.size,
6688 is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB),
6689 p_H264_Dpb->fast_output_enable
6690 );
6691
6692 dump_dpb(&p_H264_Dpb->mDPB, 1);
6693 dump_pic(p_H264_Dpb);
6694 dump_bufspec(hw, __func__);
6695
6696 dpb_print(DECODE_ID(hw), 0,
6697 "DPB_STATUS_REG=0x%x\n",
6698 READ_VREG(DPB_STATUS_REG));
6699 dpb_print(DECODE_ID(hw), 0,
6700 "MPC_E=0x%x\n",
6701 READ_VREG(MPC_E));
6702 dpb_print(DECODE_ID(hw), 0,
6703 "H264_DECODE_MODE=0x%x\n",
6704 READ_VREG(H264_DECODE_MODE));
6705 dpb_print(DECODE_ID(hw), 0,
6706 "MBY_MBX=0x%x\n",
6707 READ_VREG(MBY_MBX));
6708 dpb_print(DECODE_ID(hw), 0,
6709 "H264_DECODE_SIZE=0x%x\n",
6710 READ_VREG(H264_DECODE_SIZE));
6711 dpb_print(DECODE_ID(hw), 0,
6712 "VIFF_BIT_CNT=0x%x\n",
6713 READ_VREG(VIFF_BIT_CNT));
6714 dpb_print(DECODE_ID(hw), 0,
6715 "VLD_MEM_VIFIFO_LEVEL=0x%x\n",
6716 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
6717 dpb_print(DECODE_ID(hw), 0,
6718 "VLD_MEM_VIFIFO_WP=0x%x\n",
6719 READ_VREG(VLD_MEM_VIFIFO_WP));
6720 dpb_print(DECODE_ID(hw), 0,
6721 "VLD_MEM_VIFIFO_RP=0x%x\n",
6722 READ_VREG(VLD_MEM_VIFIFO_RP));
6723 dpb_print(DECODE_ID(hw), 0,
6724 "PARSER_VIDEO_RP=0x%x\n",
6725 READ_PARSER_REG(PARSER_VIDEO_RP));
6726 dpb_print(DECODE_ID(hw), 0,
6727 "PARSER_VIDEO_WP=0x%x\n",
6728 READ_PARSER_REG(PARSER_VIDEO_WP));
6729
6730 if (input_frame_based(vdec) &&
6731 dpb_is_debug(DECODE_ID(hw),
6732 PRINT_FRAMEBASE_DATA)
6733 ) {
6734 int jj;
6735 if (hw->chunk && hw->chunk->block &&
6736 hw->chunk->size > 0) {
6737 u8 *data = NULL;
6738
6739 if (!hw->chunk->block->is_mapped)
6740 data = codec_mm_vmap(hw->chunk->block->start +
6741 hw->chunk->offset, hw->chunk->size);
6742 else
6743 data = ((u8 *)hw->chunk->block->start_virt)
6744 + hw->chunk->offset;
6745
6746 dpb_print(DECODE_ID(hw), 0,
6747 "frame data size 0x%x\n",
6748 hw->chunk->size);
6749 for (jj = 0; jj < hw->chunk->size; jj++) {
6750 if ((jj & 0xf) == 0)
6751 dpb_print(DECODE_ID(hw),
6752 PRINT_FRAMEBASE_DATA,
6753 "%06x:", jj);
6754 dpb_print_cont(DECODE_ID(hw),
6755 PRINT_FRAMEBASE_DATA,
6756 "%02x ", data[jj]);
6757 if (((jj + 1) & 0xf) == 0)
6758 dpb_print_cont(DECODE_ID(hw),
6759 PRINT_FRAMEBASE_DATA,
6760 "\n");
6761 }
6762
6763 if (!hw->chunk->block->is_mapped)
6764 codec_mm_unmap_phyaddr(data);
6765 }
6766 }
6767}
6768
6769
6770static void check_timer_func(unsigned long arg)
6771{
6772 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)arg;
6773 struct vdec_s *vdec = hw_to_vdec(hw);
6774 int error_skip_frame_count = error_skip_count & 0xfff;
6775 unsigned int timeout_val = decode_timeout_val;
6776 if (timeout_val != 0 &&
6777 hw->no_error_count < error_skip_frame_count)
6778 timeout_val = errordata_timeout_val;
6779 if ((h264_debug_cmd & 0x100) != 0 &&
6780 DECODE_ID(hw) == (h264_debug_cmd & 0xff)) {
6781 hw->dec_result = DEC_RESULT_DONE;
6782 vdec_schedule_work(&hw->work);
6783 pr_info("vdec %d is forced to be disconnected\n",
6784 h264_debug_cmd & 0xff);
6785 h264_debug_cmd = 0;
6786 return;
6787 }
6788 if ((h264_debug_cmd & 0x200) != 0 &&
6789 DECODE_ID(hw) == (h264_debug_cmd & 0xff)) {
6790 pr_debug("vdec %d is forced to reset bufmgr\n",
6791 h264_debug_cmd & 0xff);
6792 hw->reset_bufmgr_flag = 1;
6793 h264_debug_cmd = 0;
6794 return;
6795 }
6796
6797 if (vdec->next_status == VDEC_STATUS_DISCONNECTED &&
6798 !hw->is_used_v4l) {
6799 hw->dec_result = DEC_RESULT_FORCE_EXIT;
6800 vdec_schedule_work(&hw->work);
6801 pr_debug("vdec requested to be disconnected\n");
6802 return;
6803 }
6804
6805 if (radr != 0) {
6806 if (rval != 0) {
6807 WRITE_VREG(radr, rval);
6808 pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
6809 } else
6810 pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
6811 rval = 0;
6812 radr = 0;
6813 }
6814
6815 if (((h264_debug_flag & DISABLE_ERROR_HANDLE) == 0) &&
6816 (timeout_val > 0) &&
6817 (hw->start_process_time > 0) &&
6818 ((1000 * (jiffies - hw->start_process_time) / HZ)
6819 > timeout_val)
6820 ) {
6821 u32 dpb_status = READ_VREG(DPB_STATUS_REG);
6822 u32 mby_mbx = READ_VREG(MBY_MBX);
6823 if ((dpb_status == H264_ACTION_DECODE_NEWPIC) ||
6824 (dpb_status == H264_ACTION_DECODE_SLICE)) {
6825 if (hw->last_mby_mbx == mby_mbx) {
6826 if (hw->decode_timeout_count > 0)
6827 hw->decode_timeout_count--;
6828 if (hw->decode_timeout_count == 0)
6829 {
6830 reset_process_time(hw);
6831 timeout_process(hw);
6832 }
6833 } else
6834 start_process_time(hw);
6835 } else if (is_in_parsing_state(dpb_status)) {
6836 if (hw->last_vld_level ==
6837 READ_VREG(VLD_MEM_VIFIFO_LEVEL)) {
6838 if (hw->decode_timeout_count > 0)
6839 hw->decode_timeout_count--;
6840 if (hw->decode_timeout_count == 0)
6841 {
6842 reset_process_time(hw);
6843 timeout_process(hw);
6844 }
6845 }
6846 }
6847 hw->last_vld_level =
6848 READ_VREG(VLD_MEM_VIFIFO_LEVEL);
6849 hw->last_mby_mbx = mby_mbx;
6850 }
6851
6852 if ((hw->ucode_pause_pos != 0) &&
6853 (hw->ucode_pause_pos != 0xffffffff) &&
6854 udebug_pause_pos != hw->ucode_pause_pos) {
6855 hw->ucode_pause_pos = 0;
6856 WRITE_VREG(DEBUG_REG1, 0);
6857 }
6858
6859 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
6860}
6861
6862static int dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
6863{
6864 u32 ar, ar_tmp;
6865 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
6866
6867 if (!hw)
6868 return -1;
6869
6870 vstatus->frame_width = hw->frame_width;
6871 vstatus->frame_height = hw->frame_height;
6872 if (hw->frame_dur != 0) {
6873 vstatus->frame_dur = hw->frame_dur;
6874 vstatus->frame_rate = 96000 / hw->frame_dur;
6875 }
6876 else
6877 vstatus->frame_rate = -1;
6878 vstatus->error_count = hw->gvs.error_frame_count;
6879 vstatus->status = hw->stat;
6880 if (hw->h264_ar == 0x3ff)
6881 ar_tmp = (0x100 *
6882 hw->frame_height * hw->height_aspect_ratio) /
6883 (hw->frame_width * hw->width_aspect_ratio);
6884 else
6885 ar_tmp = hw->h264_ar;
6886 ar = min_t(u32,
6887 ar_tmp,
6888 DISP_RATIO_ASPECT_RATIO_MAX);
6889 vstatus->ratio_control =
6890 ar << DISP_RATIO_ASPECT_RATIO_BIT;
6891
6892 vstatus->error_frame_count = hw->gvs.error_frame_count;
6893 vstatus->drop_frame_count = hw->gvs.drop_frame_count;
6894 vstatus->frame_count = decode_frame_count[DECODE_ID(hw)];
6895 snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
6896 "%s-%02d", DRIVER_NAME, hw->id);
6897
6898 return 0;
6899}
6900
6901static int vh264_hw_ctx_restore(struct vdec_h264_hw_s *hw)
6902{
6903 int i, j;
6904 struct aml_vcodec_ctx * v4l2_ctx = hw->v4l2_ctx;
6905
6906 /* if (hw->init_flag == 0) { */
6907 if (h264_debug_flag & 0x40000000) {
6908 /* if (1) */
6909 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6910 "%s, reset register\n", __func__);
6911
6912 while (READ_VREG(DCAC_DMA_CTRL) & 0x8000)
6913 ;
6914 while (READ_VREG(LMEM_DMA_CTRL) & 0x8000)
6915 ; /* reg address is 0x350 */
6916
6917#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
6918 WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4));
6919 WRITE_VREG(DOS_SW_RESET0, 0);
6920
6921 READ_VREG(DOS_SW_RESET0);
6922 READ_VREG(DOS_SW_RESET0);
6923 READ_VREG(DOS_SW_RESET0);
6924
6925 WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4));
6926 WRITE_VREG(DOS_SW_RESET0, 0);
6927
6928 WRITE_VREG(DOS_SW_RESET0, (1<<9) | (1<<8));
6929 WRITE_VREG(DOS_SW_RESET0, 0);
6930
6931 READ_VREG(DOS_SW_RESET0);
6932 READ_VREG(DOS_SW_RESET0);
6933 READ_VREG(DOS_SW_RESET0);
6934
6935#else
6936 WRITE_RESET_REG(RESET0_REGISTER,
6937 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
6938 READ_RESET_REG(RESET0_REGISTER);
6939 WRITE_RESET_REG(RESET0_REGISTER,
6940 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
6941
6942 WRITE_RESET_REG(RESET2_REGISTER, RESET_PIC_DC | RESET_DBLK);
6943#endif
6944 WRITE_VREG(POWER_CTL_VLD,
6945 READ_VREG(POWER_CTL_VLD) | (0 << 10) |
6946 (1 << 9) | (1 << 6));
6947 } else {
6948 /* WRITE_VREG(POWER_CTL_VLD,
6949 * READ_VREG(POWER_CTL_VLD) | (0 << 10) | (1 << 9) );
6950 */
6951 WRITE_VREG(POWER_CTL_VLD,
6952 READ_VREG(POWER_CTL_VLD) |
6953 (0 << 10) | (1 << 9) | (1 << 6));
6954 }
6955 /* disable PSCALE for hardware sharing */
6956 WRITE_VREG(PSCALE_CTRL, 0);
6957
6958 /* clear mailbox interrupt */
6959 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
6960
6961 /* enable mailbox interrupt */
6962 WRITE_VREG(ASSIST_MBOX1_MASK, 1);
6963
6964#ifdef NV21
6965 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1<<17);
6966#endif
6967
6968 /* cbcr_merge_swap_en */
6969 if (hw->is_used_v4l
6970 && (v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21
6971 || v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
6972 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 16);
6973 else
6974 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 16);
6975
6976 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 0xbf << 24);
6977 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 0xbf << 24);
6978
6979 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 31);
6980 if (hw->mmu_enable) {
6981 SET_VREG_MASK(MDEC_PIC_DC_MUX_CTRL, 1<<31);
6982 /* sw reset to extif hardware */
6983 SET_VREG_MASK(MDEC_EXTIF_CFG1, 1<<30);
6984 CLEAR_VREG_MASK(MDEC_EXTIF_CFG1, 1<<30);
6985 } else {
6986 CLEAR_VREG_MASK(MDEC_PIC_DC_MUX_CTRL, 1 << 31);
6987 WRITE_VREG(MDEC_EXTIF_CFG1, 0);
6988 }
6989
6990
6991#if 1 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
6992 /* pr_info("vh264 meson8 prot init\n"); */
6993 WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa);
6994#endif
6995
6996#ifdef VDEC_DW
6997 if (IS_VDEC_DW(hw)) {
6998 u32 data = ((1 << 30) |(1 << 0) |(1 << 8));
6999
7000 if (IS_VDEC_DW(hw) == 2)
7001 data |= (1 << 9);
7002 WRITE_VREG(MDEC_DOUBLEW_CFG0, data); /* Double Write Enable*/
7003 }
7004#endif
7005 if (hw->dpb.mDPB.size > 0) {
7006 WRITE_VREG(AV_SCRATCH_7, (hw->max_reference_size << 24) |
7007 (hw->dpb.mDPB.size << 16) |
7008 (hw->dpb.mDPB.size << 8));
7009
7010 for (j = 0; j < hw->dpb.mDPB.size; j++) {
7011 i = get_buf_spec_by_canvas_pos(hw, j);
7012 if (i < 0)
7013 break;
7014
7015 if (!hw->mmu_enable &&
7016 hw->buffer_spec[i].cma_alloc_addr)
7017 config_decode_canvas(hw, i);
7018 if (hw->mmu_enable && hw->double_write_mode)
7019 config_decode_canvas_ex(hw, i);
7020 }
7021 } else {
7022 WRITE_VREG(AV_SCRATCH_0, 0);
7023 WRITE_VREG(AV_SCRATCH_9, 0);
7024 }
7025
7026 if (hw->init_flag == 0)
7027 WRITE_VREG(DPB_STATUS_REG, 0);
7028 else
7029 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_START);
7030
7031 WRITE_VREG(FRAME_COUNTER_REG, hw->decode_pic_count);
7032 WRITE_VREG(AV_SCRATCH_8, hw->buf_offset);
7033 if (!tee_enabled())
7034 WRITE_VREG(AV_SCRATCH_G, hw->mc_dma_handle);
7035
7036 /* hw->error_recovery_mode = (error_recovery_mode != 0) ?
7037 * error_recovery_mode : error_recovery_mode_in;
7038 */
7039 /* WRITE_VREG(AV_SCRATCH_F,
7040 * (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) );
7041 */
7042 WRITE_VREG(AV_SCRATCH_F, (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) |
7043 ((error_recovery_mode_in & 0x1) << 4));
7044 /*if (hw->ucode_type == UCODE_IP_ONLY_PARAM)
7045 SET_VREG_MASK(AV_SCRATCH_F, 1 << 6);
7046 else*/
7047 CLEAR_VREG_MASK(AV_SCRATCH_F, 1 << 6);
7048
7049 WRITE_VREG(LMEM_DUMP_ADR, (u32)hw->lmem_phy_addr);
7050#if 1 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
7051 WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa);
7052#endif
7053
7054 WRITE_VREG(DEBUG_REG1, 0);
7055 WRITE_VREG(DEBUG_REG2, 0);
7056
7057 if (hw->reg_iqidct_control)
7058 WRITE_VREG(IQIDCT_CONTROL, hw->reg_iqidct_control);
7059 if (hw->reg_vcop_ctrl_reg)
7060 WRITE_VREG(VCOP_CTRL_REG, hw->reg_vcop_ctrl_reg);
7061 if (hw->vld_dec_control)
7062 WRITE_VREG(VLD_DECODE_CONTROL, hw->vld_dec_control);
7063 return 0;
7064}
7065
7066static int vmh264_set_trickmode(struct vdec_s *vdec, unsigned long trickmode)
7067{
7068 struct vdec_h264_hw_s *hw =
7069 (struct vdec_h264_hw_s *)vdec->private;
7070 if (i_only_flag & 0x100)
7071 return 0;
7072 if (trickmode == TRICKMODE_I)
7073 hw->i_only = 0x3;
7074 else if (trickmode == TRICKMODE_NONE)
7075 hw->i_only = 0x0;
7076 return 0;
7077}
7078
7079static unsigned char amvdec_enable_flag;
7080static void vh264_local_init(struct vdec_h264_hw_s *hw, bool is_reset)
7081{
7082 int i;
7083 hw->init_flag = 0;
7084 hw->first_sc_checked= 0;
7085 hw->eos = 0;
7086 hw->valve_count = 0;
7087 hw->config_bufmgr_done = 0;
7088 hw->start_process_time = 0;
7089 hw->has_i_frame = 0;
7090 hw->no_error_count = 0xfff;
7091 hw->no_error_i_count = 0xf;
7092
7093 hw->dec_flag = 0;
7094 hw->data_flag = 0;
7095 hw->skip_frame_count = 0;
7096 hw->reg_iqidct_control = 0;
7097 hw->reg_vcop_ctrl_reg = 0;
7098 hw->reg_rv_ai_mb_count = 0;
7099 hw->vld_dec_control = 0;
7100 hw->decode_timeout_count = 0;
7101 hw->no_mem_count = 0;
7102 hw->vh264_ratio = hw->vh264_amstream_dec_info.ratio;
7103 /* vh264_ratio = 0x100; */
7104
7105 hw->vh264_rotation = (((unsigned long)
7106 hw->vh264_amstream_dec_info.param) >> 16) & 0xffff;
7107
7108 hw->frame_prog = 0;
7109 hw->frame_width = hw->vh264_amstream_dec_info.width;
7110 hw->frame_height = hw->vh264_amstream_dec_info.height;
7111 hw->frame_dur = hw->vh264_amstream_dec_info.rate;
7112 hw->pts_outside = ((unsigned long)
7113 hw->vh264_amstream_dec_info.param) & 0x01;
7114 hw->sync_outside = ((unsigned long)
7115 hw->vh264_amstream_dec_info.param & 0x02) >> 1;
7116 hw->use_idr_framerate = ((unsigned long)
7117 hw->vh264_amstream_dec_info.param & 0x04) >> 2;
7118 hw->max_refer_buf = !(((unsigned long)
7119 hw->vh264_amstream_dec_info.param & 0x10) >> 4);
7120 if (hw->frame_dur < 96000/960) {
7121 /*more than 960fps,it should not be a correct value,
7122 *give default 30fps
7123 */
7124 hw->frame_dur = 96000/30;
7125 }
7126
7127 hw->unstable_pts = (((unsigned long) hw->vh264_amstream_dec_info.param & 0x40) >> 6);
7128
7129 hw->first_i_policy = first_i_policy;
7130
7131 pr_info("H264 sysinfo: %dx%d duration=%d, pts_outside=%d\n",
7132 hw->frame_width, hw->frame_height, hw->frame_dur, hw->pts_outside);
7133 pr_debug("sync_outside=%d, use_idr_framerate=%d, is_used_v4l: %d\n",
7134 hw->sync_outside, hw->use_idr_framerate, hw->is_used_v4l);
7135
7136 if (i_only_flag & 0x100)
7137 hw->i_only = i_only_flag & 0xff;
7138 if (hw->i_only)
7139 hw->dpb.first_insert_frame = FirstInsertFrm_SKIPDONE;
7140
7141 if ((unsigned long) hw->vh264_amstream_dec_info.param
7142 & 0x08)
7143 hw->no_poc_reorder_flag = 1;
7144
7145 error_recovery_mode_in = 1; /*ucode control?*/
7146 if (error_proc_policy & 0x80000000)
7147 hw->send_error_frame_flag = error_proc_policy & 0x1;
7148 else if ((unsigned long) hw->vh264_amstream_dec_info.param & 0x20)
7149 hw->send_error_frame_flag = 0; /*Don't display mark err frames*/
7150
7151 if (!is_reset) {
7152 INIT_KFIFO(hw->display_q);
7153 INIT_KFIFO(hw->newframe_q);
7154
7155 for (i = 0; i < VF_POOL_SIZE; i++) {
7156 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
7157 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
7158 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
7159 kfifo_put(&hw->newframe_q, vf);
7160 }
7161 }
7162
7163 hw->duration_from_pts_done = 0;
7164
7165 hw->p_last_vf = NULL;
7166 hw->vh264_stream_switching_state = SWITCHING_STATE_OFF;
7167 hw->hevc_cur_buf_idx = 0xffff;
7168
7169 init_waitqueue_head(&hw->wait_q);
7170
7171 return;
7172}
7173
7174static s32 vh264_init(struct vdec_h264_hw_s *hw)
7175{
7176 int size = -1;
7177 int fw_size = 0x1000 * 16;
7178 int fw_mmu_size = 0x1000 * 16;
7179 struct firmware_s *fw = NULL, *fw_mmu = NULL;
7180
7181 /* int trickmode_fffb = 0; */
7182
7183 /* pr_info("\nvh264_init\n"); */
7184 /* init_timer(&hw->recycle_timer); */
7185
7186 /* timer init */
7187 init_timer(&hw->check_timer);
7188
7189 hw->check_timer.data = (unsigned long)hw;
7190 hw->check_timer.function = check_timer_func;
7191 hw->check_timer.expires = jiffies + CHECK_INTERVAL;
7192
7193 /* add_timer(&hw->check_timer); */
7194 hw->stat |= STAT_TIMER_ARM;
7195 hw->stat |= STAT_ISR_REG;
7196
7197 mutex_init(&hw->chunks_mutex);
7198 vh264_local_init(hw, false);
7199 INIT_WORK(&hw->work, vh264_work);
7200 INIT_WORK(&hw->notify_work, vh264_notify_work);
7201 INIT_WORK(&hw->timeout_work, vh264_timeout_work);
7202#ifdef MH264_USERDATA_ENABLE
7203 INIT_WORK(&hw->user_data_ready_work, user_data_ready_notify_work);
7204#endif
7205
7206 if (!amvdec_enable_flag) {
7207 amvdec_enable_flag = true;
7208 amvdec_enable();
7209 if (hw->mmu_enable)
7210 amhevc_enable();
7211 }
7212 if (hw->mmu_enable) {
7213
7214 hw->frame_mmu_map_addr =
7215 dma_alloc_coherent(amports_get_dma_device(),
7216 FRAME_MMU_MAP_SIZE,
7217 &hw->frame_mmu_map_phy_addr, GFP_KERNEL);
7218 if (hw->frame_mmu_map_addr == NULL) {
7219 pr_err("%s: failed to alloc count_buffer\n", __func__);
7220 return -ENOMEM;
7221 }
7222 }
7223
7224 fw = vmalloc(sizeof(struct firmware_s) + fw_size);
7225 if (IS_ERR_OR_NULL(fw))
7226 return -ENOMEM;
7227
7228 size = get_firmware_data(VIDEO_DEC_H264_MULTI, fw->data);
7229 if (size < 0) {
7230 pr_err("get firmware fail.\n");
7231 vfree(fw);
7232 return -1;
7233 }
7234
7235 fw->len = size;
7236 hw->fw = fw;
7237
7238 if (hw->mmu_enable) {
7239 fw_mmu = vmalloc(sizeof(struct firmware_s) + fw_mmu_size);
7240 if (IS_ERR_OR_NULL(fw_mmu))
7241 return -ENOMEM;
7242
7243 size = get_firmware_data(VIDEO_DEC_H264_MULTI_MMU, fw_mmu->data);
7244 if (size < 0) {
7245 pr_err("get mmu fw fail.\n");
7246 vfree(fw_mmu);
7247 return -1;
7248 }
7249
7250 fw_mmu->len = size;
7251 hw->fw_mmu = fw_mmu;
7252 }
7253
7254 if (!tee_enabled()) {
7255 /* -- ucode loading (amrisc and swap code) */
7256 hw->mc_cpu_addr =
7257 dma_alloc_coherent(amports_get_dma_device(), MC_TOTAL_SIZE,
7258 &hw->mc_dma_handle, GFP_KERNEL);
7259 if (!hw->mc_cpu_addr) {
7260 amvdec_enable_flag = false;
7261 amvdec_disable();
7262 if (hw->mmu_enable)
7263 amhevc_disable();
7264 pr_info("vh264_init: Can not allocate mc memory.\n");
7265 return -ENOMEM;
7266 }
7267
7268 /*pr_info("264 ucode swap area: phyaddr %p, cpu vaddr %p\n",
7269 (void *)hw->mc_dma_handle, hw->mc_cpu_addr);
7270 */
7271
7272 /*ret = amvdec_loadmc_ex(VFORMAT_H264, NULL, buf);*/
7273
7274 /*header*/
7275 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_HEADER,
7276 fw->data + 0x4000, MC_SWAP_SIZE);
7277 /*data*/
7278 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_DATA,
7279 fw->data + 0x2000, MC_SWAP_SIZE);
7280 /*mmco*/
7281 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MMCO,
7282 fw->data + 0x6000, MC_SWAP_SIZE);
7283 /*list*/
7284 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_LIST,
7285 fw->data + 0x3000, MC_SWAP_SIZE);
7286 /*slice*/
7287 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_SLICE,
7288 fw->data + 0x5000, MC_SWAP_SIZE);
7289 /*main*/
7290 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN,
7291 fw->data, 0x2000);
7292 /*data*/
7293 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN + 0x2000,
7294 fw->data + 0x2000, 0x1000);
7295 /*slice*/
7296 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN + 0x3000,
7297 fw->data + 0x5000, 0x1000);
7298 }
7299
7300#if 1 /* #ifdef BUFFER_MGR_IN_C */
7301 hw->lmem_addr = (dma_addr_t)dma_alloc_coherent(amports_get_dma_device(),
7302 PAGE_SIZE, (dma_addr_t *)&hw->lmem_phy_addr, GFP_KERNEL);
7303
7304 if (hw->lmem_addr == 0) {
7305 pr_err("%s: failed to alloc lmem buffer\n", __func__);
7306 return -1;
7307 }
7308 pr_debug("%s, phy_addr=%lx vaddr=%p\n",
7309 __func__, hw->lmem_phy_addr, (void *)hw->lmem_addr);
7310
7311 if (prefix_aux_buf_size > 0 ||
7312 suffix_aux_buf_size > 0) {
7313 u32 aux_buf_size;
7314 hw->prefix_aux_size = AUX_BUF_ALIGN(prefix_aux_buf_size);
7315 hw->suffix_aux_size = AUX_BUF_ALIGN(suffix_aux_buf_size);
7316 aux_buf_size = hw->prefix_aux_size + hw->suffix_aux_size;
7317 hw->aux_addr = dma_alloc_coherent(amports_get_dma_device(),
7318 aux_buf_size, &hw->aux_phy_addr,
7319 GFP_KERNEL);
7320 if (hw->aux_addr == NULL) {
7321 pr_err("%s: failed to alloc rpm buffer\n", __func__);
7322 return -1;
7323 }
7324
7325 hw->sei_data_buf = kmalloc(SEI_DATA_SIZE, GFP_KERNEL);
7326 if (hw->sei_data_buf == NULL) {
7327 pr_err("%s: failed to alloc sei itu data buffer\n",
7328 __func__);
7329 return -1;
7330 }
7331 hw->sei_itu_data_buf = kmalloc(SEI_ITU_DATA_SIZE, GFP_KERNEL);
7332 if (hw->sei_itu_data_buf == NULL) {
7333 pr_err("%s: failed to alloc sei itu data buffer\n",
7334 __func__);
7335 dma_free_coherent(amports_get_dma_device(),
7336 hw->prefix_aux_size + hw->suffix_aux_size, hw->aux_addr,
7337 hw->aux_phy_addr);
7338 hw->aux_addr = NULL;
7339 kfree(hw->sei_data_buf);
7340 hw->sei_data_buf = NULL;
7341
7342 return -1;
7343 }
7344
7345 if (NULL == hw->sei_user_data_buffer) {
7346 hw->sei_user_data_buffer = kmalloc(USER_DATA_SIZE,
7347 GFP_KERNEL);
7348 if (!hw->sei_user_data_buffer) {
7349 pr_info("%s: Can not allocate sei_data_buffer\n",
7350 __func__);
7351 dma_free_coherent(amports_get_dma_device(),
7352 hw->prefix_aux_size + hw->suffix_aux_size, hw->aux_addr,
7353 hw->aux_phy_addr);
7354 hw->aux_addr = NULL;
7355 kfree(hw->sei_data_buf);
7356 hw->sei_data_buf = NULL;
7357 kfree(hw->sei_itu_data_buf);
7358 hw->sei_itu_data_buf = NULL;
7359
7360 return -1;
7361 }
7362 hw->sei_user_data_wp = 0;
7363 }
7364 }
7365/* BUFFER_MGR_IN_C */
7366#endif
7367 hw->stat |= STAT_MC_LOAD;
7368
7369 /* add memory barrier */
7370 wmb();
7371
7372 return 0;
7373}
7374
7375static int vh264_stop(struct vdec_h264_hw_s *hw)
7376{
7377 if (hw->stat & STAT_VDEC_RUN) {
7378 amvdec_stop();
7379 hw->stat &= ~STAT_VDEC_RUN;
7380 }
7381#ifdef VDEC_DW
7382 WRITE_VREG(MDEC_DOUBLEW_CFG0, 0);
7383#endif
7384#ifdef MH264_USERDATA_ENABLE
7385 cancel_work_sync(&hw->user_data_ready_work);
7386#endif
7387 cancel_work_sync(&hw->notify_work);
7388 cancel_work_sync(&hw->timeout_work);
7389 cancel_work_sync(&hw->work);
7390
7391
7392 if (hw->stat & STAT_MC_LOAD) {
7393 if (hw->mc_cpu_addr != NULL) {
7394 dma_free_coherent(amports_get_dma_device(),
7395 MC_TOTAL_SIZE, hw->mc_cpu_addr,
7396 hw->mc_dma_handle);
7397 hw->mc_cpu_addr = NULL;
7398 }
7399 if (hw->frame_mmu_map_addr != NULL) {
7400 dma_free_coherent(amports_get_dma_device(),
7401 FRAME_MMU_MAP_SIZE, hw->frame_mmu_map_addr,
7402 hw->frame_mmu_map_phy_addr);
7403 hw->frame_mmu_map_addr = NULL;
7404 }
7405
7406 }
7407 if (hw->stat & STAT_ISR_REG) {
7408 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
7409 hw->stat &= ~STAT_ISR_REG;
7410 }
7411 if (hw->lmem_addr) {
7412 dma_free_coherent(amports_get_dma_device(),
7413 PAGE_SIZE, (void *)hw->lmem_addr,
7414 hw->lmem_phy_addr);
7415 hw->lmem_addr = 0;
7416 }
7417
7418 if (hw->aux_addr) {
7419 dma_free_coherent(amports_get_dma_device(),
7420 hw->prefix_aux_size + hw->suffix_aux_size, hw->aux_addr,
7421 hw->aux_phy_addr);
7422 hw->aux_addr = NULL;
7423 }
7424 if (hw->sei_data_buf != NULL) {
7425 kfree(hw->sei_data_buf);
7426 hw->sei_data_buf = NULL;
7427 }
7428 if (hw->sei_itu_data_buf != NULL) {
7429 kfree(hw->sei_itu_data_buf);
7430 hw->sei_itu_data_buf = NULL;
7431 }
7432 if (hw->sei_user_data_buffer != NULL) {
7433 kfree(hw->sei_user_data_buffer);
7434 hw->sei_user_data_buffer = NULL;
7435 }
7436 /* amvdec_disable(); */
7437
7438 vfree(hw->fw);
7439 hw->fw = NULL;
7440
7441 if (hw->mmu_enable) {
7442 vfree(hw->fw_mmu);
7443 hw->fw_mmu = NULL;
7444 }
7445
7446 dpb_print(DECODE_ID(hw), 0,
7447 "%s\n",
7448 __func__);
7449 return 0;
7450}
7451
7452static void wait_vmh264_search_done(struct vdec_h264_hw_s *hw)
7453{
7454 u32 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
7455 int count = 0;
7456 do {
7457 usleep_range(100, 500);
7458 if (vld_rp == READ_VREG(VLD_MEM_VIFIFO_RP))
7459 break;
7460 if (count > 2000) {
7461 dpb_print(DECODE_ID(hw),
7462 PRINT_FLAG_ERROR, "%s timeout count %d vld_rp 0x%x VLD_MEM_VIFIFO_RP 0x%x\n",
7463 __func__, count, vld_rp, READ_VREG(VLD_MEM_VIFIFO_RP));
7464 break;
7465 } else
7466 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
7467 count++;
7468 } while (1);
7469}
7470
7471static void vh264_notify_work(struct work_struct *work)
7472{
7473 struct vdec_h264_hw_s *hw = container_of(work,
7474 struct vdec_h264_hw_s, notify_work);
7475 struct vdec_s *vdec = hw_to_vdec(hw);
7476 if (vdec->fr_hint_state == VDEC_NEED_HINT) {
7477 vf_notify_receiver(vdec->vf_provider_name,
7478 VFRAME_EVENT_PROVIDER_FR_HINT,
7479 (void *)((unsigned long)hw->frame_dur));
7480 vdec->fr_hint_state = VDEC_HINTED;
7481 }
7482
7483 return;
7484}
7485
7486#ifdef MH264_USERDATA_ENABLE
7487static void vmh264_reset_udr_mgr(struct vdec_h264_hw_s *hw)
7488{
7489 hw->wait_for_udr_send = 0;
7490 hw->sei_itu_data_len = 0;
7491 memset(&hw->ud_record, 0, sizeof(hw->ud_record));
7492}
7493
7494static void vmh264_crate_userdata_manager(
7495 struct vdec_h264_hw_s *hw,
7496 u8 *userdata_buf,
7497 int buf_len)
7498{
7499 if (hw) {
7500
7501
7502 mutex_init(&hw->userdata_mutex);
7503
7504 memset(&hw->userdata_info, 0,
7505 sizeof(struct mh264_userdata_info_t));
7506 hw->userdata_info.data_buf = userdata_buf;
7507 hw->userdata_info.buf_len = buf_len;
7508 hw->userdata_info.data_buf_end = userdata_buf + buf_len;
7509
7510 vmh264_reset_udr_mgr(hw);
7511
7512 }
7513}
7514
7515static void vmh264_destroy_userdata_manager(struct vdec_h264_hw_s *hw)
7516{
7517 if (hw)
7518 memset(&hw->userdata_info,
7519 0,
7520 sizeof(struct mh264_userdata_info_t));
7521}
7522
7523/*
7524#define DUMP_USERDATA_RECORD
7525*/
7526#ifdef DUMP_USERDATA_RECORD
7527
7528#define MAX_USER_DATA_SIZE 3145728
7529static void *user_data_buf;
7530static unsigned char *pbuf_start;
7531static int total_len;
7532static int bskip;
7533static int n_userdata_id;
7534
7535static void print_data(unsigned char *pdata,
7536 int len,
7537 unsigned int poc_number,
7538 unsigned int flag,
7539 unsigned int duration,
7540 unsigned int vpts,
7541 unsigned int vpts_valid,
7542 int rec_id)
7543{
7544 int nLeft;
7545
7546 nLeft = len;
7547#if 0
7548 pr_info("%d len:%d, flag:%d, dur:%d, vpts:0x%x, valid:%d, poc:%d\n",
7549 rec_id, len, flag,
7550 duration, vpts, vpts_valid, poc_number);
7551#endif
7552 pr_info("%d len = %d, flag = %d, vpts = 0x%x\n",
7553 rec_id, len, flag, vpts);
7554
7555 if (len == 96) {
7556 int i;
7557 nLeft = 72;
7558 while (nLeft >= 16) {
7559 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
7560 pdata[0], pdata[1], pdata[2], pdata[3],
7561 pdata[4], pdata[5], pdata[6], pdata[7],
7562 pdata[8], pdata[9], pdata[10], pdata[11],
7563 pdata[12], pdata[13], pdata[14], pdata[15]);
7564 nLeft -= 16;
7565 pdata += 16;
7566 }
7567
7568
7569 while (nLeft > 0) {
7570 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
7571 pdata[0], pdata[1], pdata[2], pdata[3],
7572 pdata[4], pdata[5], pdata[6], pdata[7]);
7573 nLeft -= 8;
7574 pdata += 8;
7575 }
7576
7577 i = 0;
7578 nLeft = 96-72;
7579 while (i < nLeft) {
7580 if (pdata[0] != 0) {
7581 pr_info("some data error\n");
7582 break;
7583 }
7584 pdata++;
7585 i++;
7586 }
7587 } else {
7588 while (nLeft >= 16) {
7589 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
7590 pdata[0], pdata[1], pdata[2], pdata[3],
7591 pdata[4], pdata[5], pdata[6], pdata[7],
7592 pdata[8], pdata[9], pdata[10], pdata[11],
7593 pdata[12], pdata[13], pdata[14], pdata[15]);
7594 nLeft -= 16;
7595 pdata += 16;
7596 }
7597
7598
7599 while (nLeft > 0) {
7600 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
7601 pdata[0], pdata[1], pdata[2], pdata[3],
7602 pdata[4], pdata[5], pdata[6], pdata[7]);
7603 nLeft -= 8;
7604 pdata += 8;
7605 }
7606
7607 }
7608}
7609
7610static void push_to_buf(struct vdec_h264_hw_s *hw,
7611 u8 *pdata,
7612 int len,
7613 struct userdata_meta_info_t *pmeta);
7614
7615static void dump_userdata_record(struct vdec_h264_hw_s *hw,
7616 struct mh264_userdata_record_t *record)
7617{
7618 if (record && hw) {
7619 u8 *pdata;
7620
7621 pdata = hw->userdata_info.data_buf + record->rec_start;
7622/*
7623 print_data(pdata,
7624 record->rec_len,
7625 record->meta_info.flags,
7626 record->meta_info.duration,
7627 record->meta_info.vpts,
7628 record->meta_info.vpts_valid,
7629 n_record_id);
7630*/
7631 push_to_buf(hw, pdata, record->rec_len, &record->meta_info);
7632 n_userdata_id++;
7633 }
7634}
7635
7636
7637static void push_to_buf(struct vdec_h264_hw_s *hw,
7638 u8 *pdata, int len,
7639 struct userdata_meta_info_t *pmeta)
7640{
7641 u32 *pLen;
7642 int info_cnt;
7643 u8 *pbuf_end;
7644
7645 if (!user_data_buf)
7646 return;
7647
7648 if (bskip) {
7649 pr_info("over size, skip\n");
7650 return;
7651 }
7652 info_cnt = 0;
7653 pLen = (u32 *)pbuf_start;
7654
7655 *pLen = len;
7656 pbuf_start += sizeof(u32);
7657 info_cnt++;
7658 pLen++;
7659
7660 *pLen = pmeta->poc_number;
7661 pbuf_start += sizeof(u32);
7662 info_cnt++;
7663 pLen++;
7664
7665 *pLen = pmeta->duration;
7666 pbuf_start += sizeof(u32);
7667 info_cnt++;
7668 pLen++;
7669
7670 *pLen = pmeta->flags;
7671 pbuf_start += sizeof(u32);
7672 info_cnt++;
7673 pLen++;
7674
7675 *pLen = pmeta->vpts;
7676 pbuf_start += sizeof(u32);
7677 info_cnt++;
7678 pLen++;
7679
7680 *pLen = pmeta->vpts_valid;
7681 pbuf_start += sizeof(u32);
7682 info_cnt++;
7683 pLen++;
7684
7685
7686 *pLen = n_userdata_id;
7687 pbuf_start += sizeof(u32);
7688 info_cnt++;
7689 pLen++;
7690
7691
7692
7693 pbuf_end = (u8 *)hw->sei_user_data_buffer + USER_DATA_SIZE;
7694 if (pdata + len > pbuf_end) {
7695 int first_section_len;
7696
7697 first_section_len = pbuf_end - pdata;
7698 memcpy(pbuf_start, pdata, first_section_len);
7699 pdata = (u8 *)hw->sei_user_data_buffer;
7700 pbuf_start += first_section_len;
7701 memcpy(pbuf_start, pdata, len - first_section_len);
7702 pbuf_start += len - first_section_len;
7703 } else {
7704 memcpy(pbuf_start, pdata, len);
7705 pbuf_start += len;
7706 }
7707
7708 total_len += len + info_cnt * sizeof(u32);
7709 if (total_len >= MAX_USER_DATA_SIZE-4096)
7710 bskip = 1;
7711}
7712
7713static void show_user_data_buf(void)
7714{
7715 u8 *pbuf;
7716 int len;
7717 unsigned int flag;
7718 unsigned int duration;
7719 unsigned int vpts;
7720 unsigned int vpts_valid;
7721 unsigned int poc_number;
7722 int rec_id;
7723
7724 pr_info("show user data buf\n");
7725 pbuf = user_data_buf;
7726
7727 while (pbuf < pbuf_start) {
7728 u32 *pLen;
7729
7730 pLen = (u32 *)pbuf;
7731
7732 len = *pLen;
7733 pLen++;
7734 pbuf += sizeof(u32);
7735
7736 poc_number = *pLen;
7737 pLen++;
7738 pbuf += sizeof(u32);
7739
7740 duration = *pLen;
7741 pLen++;
7742 pbuf += sizeof(u32);
7743
7744 flag = *pLen;
7745 pLen++;
7746 pbuf += sizeof(u32);
7747
7748 vpts = *pLen;
7749 pLen++;
7750 pbuf += sizeof(u32);
7751
7752 vpts_valid = *pLen;
7753 pLen++;
7754 pbuf += sizeof(u32);
7755
7756 rec_id = *pLen;
7757 pLen++;
7758 pbuf += sizeof(u32);
7759
7760 print_data(pbuf, len, poc_number, flag,
7761 duration, vpts,
7762 vpts_valid, rec_id);
7763 pbuf += len;
7764 msleep(30);
7765 }
7766}
7767
7768static int vmh264_init_userdata_dump(void)
7769{
7770 user_data_buf = kmalloc(MAX_USER_DATA_SIZE, GFP_KERNEL);
7771 if (user_data_buf)
7772 return 1;
7773 else
7774 return 0;
7775}
7776
7777static void vmh264_dump_userdata(void)
7778{
7779 if (user_data_buf) {
7780 show_user_data_buf();
7781 kfree(user_data_buf);
7782 user_data_buf = NULL;
7783 }
7784}
7785
7786static void vmh264_reset_user_data_buf(void)
7787{
7788 total_len = 0;
7789 pbuf_start = user_data_buf;
7790 bskip = 0;
7791 n_userdata_id = 0;
7792}
7793#endif
7794
7795
7796static void vmh264_udc_fill_vpts(struct vdec_h264_hw_s *hw,
7797 int frame_type,
7798 u32 vpts,
7799 u32 vpts_valid)
7800{
7801 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
7802
7803 unsigned char *pdata;
7804 u8 *pmax_sei_data_buffer;
7805 u8 *sei_data_buf;
7806 int i;
7807 int wp;
7808 int data_length;
7809 struct mh264_userdata_record_t *p_userdata_rec;
7810
7811
7812#ifdef MH264_USERDATA_ENABLE
7813 struct userdata_meta_info_t meta_info;
7814 memset(&meta_info, 0, sizeof(meta_info));
7815#endif
7816
7817 if (hw->sei_itu_data_len <= 0)
7818 return;
7819
7820 pdata = (u8 *)hw->sei_user_data_buffer + hw->sei_user_data_wp;
7821 pmax_sei_data_buffer = (u8 *)hw->sei_user_data_buffer + USER_DATA_SIZE;
7822 sei_data_buf = (u8 *)hw->sei_itu_data_buf;
7823 for (i = 0; i < hw->sei_itu_data_len; i++) {
7824 *pdata++ = sei_data_buf[i];
7825 if (pdata >= pmax_sei_data_buffer)
7826 pdata = (u8 *)hw->sei_user_data_buffer;
7827 }
7828
7829 hw->sei_user_data_wp = (hw->sei_user_data_wp
7830 + hw->sei_itu_data_len) % USER_DATA_SIZE;
7831 hw->sei_itu_data_len = 0;
7832
7833#ifdef MH264_USERDATA_ENABLE
7834 meta_info.duration = hw->frame_dur;
7835 meta_info.flags |= (VFORMAT_H264 << 3);
7836
7837 meta_info.vpts = vpts;
7838 meta_info.vpts_valid = vpts_valid;
7839 meta_info.poc_number =
7840 p_H264_Dpb->mVideo.dec_picture->poc;
7841
7842
7843 wp = hw->sei_user_data_wp;
7844
7845 if (hw->sei_user_data_wp > hw->userdata_info.last_wp)
7846 data_length = wp - hw->userdata_info.last_wp;
7847 else
7848 data_length = wp + hw->userdata_info.buf_len
7849 - hw->userdata_info.last_wp;
7850
7851 if (data_length & 0x7)
7852 data_length = (((data_length + 8) >> 3) << 3);
7853
7854 p_userdata_rec = &hw->ud_record;
7855 p_userdata_rec->meta_info = meta_info;
7856 p_userdata_rec->rec_start = hw->userdata_info.last_wp;
7857 p_userdata_rec->rec_len = data_length;
7858 hw->userdata_info.last_wp = wp;
7859
7860 p_userdata_rec->meta_info.flags |=
7861 p_H264_Dpb->mVideo.dec_picture->pic_struct << 12;
7862
7863 hw->wait_for_udr_send = 1;
7864 vdec_schedule_work(&hw->user_data_ready_work);
7865#endif
7866}
7867
7868
7869static void user_data_ready_notify_work(struct work_struct *work)
7870{
7871 struct vdec_h264_hw_s *hw = container_of(work,
7872 struct vdec_h264_hw_s, user_data_ready_work);
7873
7874
7875 mutex_lock(&hw->userdata_mutex);
7876
7877 hw->userdata_info.records[hw->userdata_info.write_index]
7878 = hw->ud_record;
7879 hw->userdata_info.write_index++;
7880 if (hw->userdata_info.write_index >= USERDATA_FIFO_NUM)
7881 hw->userdata_info.write_index = 0;
7882
7883 mutex_unlock(&hw->userdata_mutex);
7884
7885#ifdef DUMP_USERDATA_RECORD
7886 dump_userdata_record(hw, &hw->ud_record);
7887#endif
7888 vdec_wakeup_userdata_poll(hw_to_vdec(hw));
7889
7890 hw->wait_for_udr_send = 0;
7891}
7892
7893static int vmh264_user_data_read(struct vdec_s *vdec,
7894 struct userdata_param_t *puserdata_para)
7895{
7896 struct vdec_h264_hw_s *hw = NULL;
7897 int rec_ri, rec_wi;
7898 int rec_len;
7899 u8 *rec_data_start;
7900 u8 *pdest_buf;
7901 struct mh264_userdata_record_t *p_userdata_rec;
7902 u32 data_size;
7903 u32 res;
7904 int copy_ok = 1;
7905
7906 hw = (struct vdec_h264_hw_s *)vdec->private;
7907
7908 pdest_buf = puserdata_para->pbuf_addr;
7909
7910 mutex_lock(&hw->userdata_mutex);
7911
7912/*
7913 pr_info("ri = %d, wi = %d\n",
7914 lg_p_mpeg12_userdata_info->read_index,
7915 lg_p_mpeg12_userdata_info->write_index);
7916*/
7917 rec_ri = hw->userdata_info.read_index;
7918 rec_wi = hw->userdata_info.write_index;
7919
7920 if (rec_ri == rec_wi) {
7921 mutex_unlock(&hw->userdata_mutex);
7922 return 0;
7923 }
7924
7925 p_userdata_rec = hw->userdata_info.records + rec_ri;
7926
7927 rec_len = p_userdata_rec->rec_len;
7928 rec_data_start = p_userdata_rec->rec_start + hw->userdata_info.data_buf;
7929/*
7930 pr_info("rec_len:%d, rec_start:%d, buf_len:%d\n",
7931 p_userdata_rec->rec_len,
7932 p_userdata_rec->rec_start,
7933 puserdata_para->buf_len);
7934*/
7935 if (rec_len <= puserdata_para->buf_len) {
7936 /* dvb user data buffer is enought to
7937 copy the whole recored. */
7938 data_size = rec_len;
7939 if (rec_data_start + data_size
7940 > hw->userdata_info.data_buf_end) {
7941 int first_section_len;
7942
7943 first_section_len = hw->userdata_info.buf_len -
7944 p_userdata_rec->rec_start;
7945 res = (u32)copy_to_user((void *)pdest_buf,
7946 (void *)rec_data_start,
7947 first_section_len);
7948 if (res) {
7949 pr_info("p1 read not end res=%d, request=%d\n",
7950 res, first_section_len);
7951 copy_ok = 0;
7952
7953 p_userdata_rec->rec_len -=
7954 first_section_len - res;
7955 p_userdata_rec->rec_start +=
7956 first_section_len - res;
7957 puserdata_para->data_size =
7958 first_section_len - res;
7959 } else {
7960 res = (u32)copy_to_user(
7961 (void *)(pdest_buf+first_section_len),
7962 (void *)hw->userdata_info.data_buf,
7963 data_size - first_section_len);
7964 if (res) {
7965 pr_info("p2 read not end res=%d, request=%d\n",
7966 res, data_size);
7967 copy_ok = 0;
7968 }
7969 p_userdata_rec->rec_len -=
7970 data_size - res;
7971 p_userdata_rec->rec_start =
7972 data_size - first_section_len - res;
7973 puserdata_para->data_size =
7974 data_size - res;
7975 }
7976 } else {
7977 res = (u32)copy_to_user((void *)pdest_buf,
7978 (void *)rec_data_start,
7979 data_size);
7980 if (res) {
7981 pr_info("p3 read not end res=%d, request=%d\n",
7982 res, data_size);
7983 copy_ok = 0;
7984 }
7985 p_userdata_rec->rec_len -= data_size - res;
7986 p_userdata_rec->rec_start += data_size - res;
7987 puserdata_para->data_size = data_size - res;
7988 }
7989
7990 if (copy_ok) {
7991 hw->userdata_info.read_index++;
7992 if (hw->userdata_info.read_index >= USERDATA_FIFO_NUM)
7993 hw->userdata_info.read_index = 0;
7994 }
7995 } else {
7996 /* dvb user data buffer is not enought
7997 to copy the whole recored. */
7998 data_size = puserdata_para->buf_len;
7999 if (rec_data_start + data_size
8000 > hw->userdata_info.data_buf_end) {
8001 int first_section_len;
8002
8003 first_section_len = hw->userdata_info.buf_len -
8004 p_userdata_rec->rec_start;
8005 res = (u32)copy_to_user((void *)pdest_buf,
8006 (void *)rec_data_start,
8007 first_section_len);
8008 if (res) {
8009 pr_info("p4 read not end res=%d, request=%d\n",
8010 res, first_section_len);
8011 copy_ok = 0;
8012 p_userdata_rec->rec_len -=
8013 first_section_len - res;
8014 p_userdata_rec->rec_start +=
8015 first_section_len - res;
8016 puserdata_para->data_size =
8017 first_section_len - res;
8018 } else {
8019 /* first secton copy is ok*/
8020 res = (u32)copy_to_user(
8021 (void *)(pdest_buf+first_section_len),
8022 (void *)hw->userdata_info.data_buf,
8023 data_size - first_section_len);
8024 if (res) {
8025 pr_info("p5 read not end res=%d, request=%d\n",
8026 res,
8027 data_size - first_section_len);
8028 copy_ok = 0;
8029 }
8030
8031 p_userdata_rec->rec_len -=
8032 data_size - res;
8033 p_userdata_rec->rec_start =
8034 data_size - first_section_len - res;
8035 puserdata_para->data_size =
8036 data_size - res;
8037 }
8038 } else {
8039 res = (u32)copy_to_user((void *)pdest_buf,
8040 (void *)rec_data_start,
8041 data_size);
8042 if (res) {
8043 pr_info("p6 read not end res=%d, request=%d\n",
8044 res, data_size);
8045 copy_ok = 0;
8046 }
8047
8048 p_userdata_rec->rec_len -= data_size - res;
8049 p_userdata_rec->rec_start += data_size - res;
8050 puserdata_para->data_size = data_size - res;
8051 }
8052
8053 if (copy_ok) {
8054 hw->userdata_info.read_index++;
8055 if (hw->userdata_info.read_index >= USERDATA_FIFO_NUM)
8056 hw->userdata_info.read_index = 0;
8057 }
8058
8059 }
8060 puserdata_para->meta_info = p_userdata_rec->meta_info;
8061
8062 if (hw->userdata_info.read_index <= hw->userdata_info.write_index)
8063 puserdata_para->meta_info.records_in_que =
8064 hw->userdata_info.write_index -
8065 hw->userdata_info.read_index;
8066 else
8067 puserdata_para->meta_info.records_in_que =
8068 hw->userdata_info.write_index +
8069 USERDATA_FIFO_NUM -
8070 hw->userdata_info.read_index;
8071
8072 puserdata_para->version = (0<<24|0<<16|0<<8|1);
8073
8074 mutex_unlock(&hw->userdata_mutex);
8075
8076 return 1;
8077}
8078
8079static void vmh264_reset_userdata_fifo(struct vdec_s *vdec, int bInit)
8080{
8081 struct vdec_h264_hw_s *hw = NULL;
8082
8083 hw = (struct vdec_h264_hw_s *)vdec->private;
8084
8085 if (hw) {
8086 mutex_lock(&hw->userdata_mutex);
8087 pr_info("vmh264_reset_userdata_fifo: bInit: %d, ri: %d, wi: %d\n",
8088 bInit,
8089 hw->userdata_info.read_index,
8090 hw->userdata_info.write_index);
8091 hw->userdata_info.read_index = 0;
8092 hw->userdata_info.write_index = 0;
8093
8094 if (bInit)
8095 hw->userdata_info.last_wp = 0;
8096 mutex_unlock(&hw->userdata_mutex);
8097 }
8098}
8099
8100static void vmh264_wakeup_userdata_poll(struct vdec_s *vdec)
8101{
8102 amstream_wakeup_userdata_poll(vdec);
8103}
8104
8105#endif
8106
8107static int vmh264_get_ps_info(struct vdec_h264_hw_s *hw, u32 param1, u32 param4, struct aml_vdec_ps_infos *ps)
8108{
8109 struct vdec_s *vdec = hw_to_vdec(hw);
8110 int mb_width, mb_total;
8111 int mb_height = 0;
8112 int active_buffer_spec_num;
8113 int max_reference_size ,level_idc;
8114 unsigned int used_reorder_dpb_size_margin
8115 = hw->reorder_dpb_size_margin;
8116 int reorder_pic_num;
8117
8118 level_idc = param4 & 0xff;
8119 max_reference_size = (param4 >> 8) & 0xff;
8120
8121#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8122 if (vdec->master || vdec->slave)
8123 used_reorder_dpb_size_margin =
8124 reorder_dpb_size_margin_dv;
8125#endif
8126 mb_width = param1 & 0xff;
8127 mb_total = (param1 >> 8) & 0xffff;
8128 if (!mb_width && mb_total) /*for 4k2k*/
8129 mb_width = 256;
8130 if (mb_width)
8131 mb_height = mb_total/mb_width;
8132 if (mb_width <= 0 || mb_height <= 0 ||
8133 is_oversize(mb_width << 4, mb_height << 4)) {
8134 dpb_print(DECODE_ID(hw), 0,
8135 "!!!wrong param1 0x%x mb_width/mb_height (0x%x/0x%x) %x\r\n",
8136 param1,
8137 mb_width,
8138 mb_height);
8139 return -1;
8140 }
8141
8142 reorder_pic_num =
8143 get_max_dec_frame_buf_size(level_idc,
8144 max_reference_size, mb_width, mb_height);
8145
8146 if ((hw->bitstream_restriction_flag) &&
8147 (hw->max_dec_frame_buffering <
8148 reorder_pic_num)) {
8149 reorder_pic_num = hw->max_dec_frame_buffering;
8150 dpb_print(DECODE_ID(hw), 0,
8151 "set reorder_pic_num to %d\n",
8152 reorder_pic_num);
8153 }
8154
8155 active_buffer_spec_num =
8156 reorder_pic_num
8157 + used_reorder_dpb_size_margin;
8158
8159 if (active_buffer_spec_num > MAX_VF_BUF_NUM) {
8160 active_buffer_spec_num = MAX_VF_BUF_NUM;
8161 reorder_pic_num = active_buffer_spec_num
8162 - used_reorder_dpb_size_margin;
8163 }
8164
8165 if (hw->no_poc_reorder_flag)
8166 reorder_pic_num = 1;
8167
8168 ps->profile = level_idc;
8169 ps->ref_frames = max_reference_size;
8170 ps->mb_width = mb_width;
8171 ps->mb_height = mb_height;
8172 ps->visible_width = mb_width << 4;
8173 ps->visible_height = mb_height << 4;
8174 ps->coded_width = ALIGN(mb_width << 4, 64);
8175 ps->coded_height = ALIGN(mb_height << 4, 64);
8176 ps->reorder_frames = reorder_pic_num;
8177 ps->dpb_size = active_buffer_spec_num;
8178
8179 return 0;
8180}
8181
8182static int v4l_res_change(struct vdec_h264_hw_s *hw, u32 param1, u32 param4)
8183{
8184 struct aml_vcodec_ctx *ctx =
8185 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8186 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8187 int ret = 0;
8188
8189 if (ctx->param_sets_from_ucode &&
8190 hw->res_ch_flag == 0) {
8191 if (param1 != 0 &&
8192 hw->seq_info2 != (param1 & (~0x80000000)) &&
8193 hw->seq_info2 != 0) /*picture size changed*/ {
8194 struct aml_vdec_ps_infos ps;
8195 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL, "h264 res_change\n");
8196 if (vmh264_get_ps_info(hw, param1, param4, &ps) < 0) {
8197 dpb_print(DECODE_ID(hw), 0, "set parameters error\n");
8198 }
8199 hw->v4l_params_parsed = false;
8200 vdec_v4l_set_ps_infos(ctx, &ps);
8201 vdec_v4l_res_ch_event(ctx);
8202 hw->res_ch_flag = 1;
8203 amvdec_stop();
8204 if (hw->mmu_enable)
8205 amhevc_stop();
8206 hw->eos = 1;
8207 flush_dpb(p_H264_Dpb);
8208 //del_timer_sync(&hw->check_timer);
8209 if (hw->is_used_v4l)
8210 notify_v4l_eos(hw_to_vdec(hw));
8211 ret = 1;
8212 }
8213 }
8214
8215 return ret;
8216
8217}
8218
8219static void vh264_work_implement(struct vdec_h264_hw_s *hw,
8220 struct vdec_s *vdec, int from)
8221{
8222 /* finished decoding one frame or error,
8223 * notify vdec core to switch context
8224 */
8225 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
8226 "%s dec_result %d %x %x %x\n",
8227 __func__,
8228 hw->dec_result,
8229 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8230 READ_VREG(VLD_MEM_VIFIFO_WP),
8231 READ_VREG(VLD_MEM_VIFIFO_RP));
8232 if (!hw->mmu_enable) {
8233 mutex_lock(&vmh264_mutex);
8234 dealloc_buf_specs(hw, 0);
8235 mutex_unlock(&vmh264_mutex);
8236 }
8237 hw->dpb.last_dpb_status = hw->dpb.dec_dpb_status;
8238 if (hw->dec_result == DEC_RESULT_CONFIG_PARAM) {
8239 u32 param1 = READ_VREG(AV_SCRATCH_1);
8240 u32 param2 = READ_VREG(AV_SCRATCH_2);
8241 u32 param3 = READ_VREG(AV_SCRATCH_6);
8242 u32 param4 = READ_VREG(AV_SCRATCH_B);
8243 struct aml_vcodec_ctx *ctx =
8244 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8245
8246 if (hw->is_used_v4l &&
8247 ctx->param_sets_from_ucode) {
8248 if (!v4l_res_change(hw, param1, param4)) {
8249 if (!hw->v4l_params_parsed) {
8250 struct aml_vdec_ps_infos ps;
8251 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL, "h264 parsered csd data\n");
8252 if (vmh264_get_ps_info(hw, param1, param4, &ps) < 0) {
8253 dpb_print(DECODE_ID(hw), 0, "set parameters error\n");
8254 }
8255 hw->v4l_params_parsed = true;
8256 vdec_v4l_set_ps_infos(ctx, &ps);
8257 amvdec_stop();
8258 if (hw->mmu_enable)
8259 amhevc_stop();
8260 }
8261 else {
8262 if (vh264_set_params(hw, param1,
8263 param2, param3, param4) < 0)
8264 dpb_print(DECODE_ID(hw), 0, "set parameters error\n");
8265
8266 WRITE_VREG(AV_SCRATCH_0, (hw->max_reference_size<<24) |
8267 (hw->dpb.mDPB.size<<16) |
8268 (hw->dpb.mDPB.size<<8));
8269 hw->res_ch_flag = 0;
8270 start_process_time(hw);
8271 return;
8272 }
8273 }
8274 } else {
8275 if (vh264_set_params(hw, param1,
8276 param2, param3, param4) < 0)
8277 dpb_print(DECODE_ID(hw), 0, "set parameters error\n");
8278
8279 WRITE_VREG(AV_SCRATCH_0, (hw->max_reference_size<<24) |
8280 (hw->dpb.mDPB.size<<16) |
8281 (hw->dpb.mDPB.size<<8));
8282 start_process_time(hw);
8283 return;
8284 }
8285 } else
8286 if (((hw->dec_result == DEC_RESULT_GET_DATA) ||
8287 (hw->dec_result == DEC_RESULT_GET_DATA_RETRY))
8288 && (hw_to_vdec(hw)->next_status !=
8289 VDEC_STATUS_DISCONNECTED)) {
8290 if (!vdec_has_more_input(vdec)) {
8291 hw->dec_result = DEC_RESULT_EOS;
8292 vdec_schedule_work(&hw->work);
8293 return;
8294 }
8295
8296 if (hw->dec_result == DEC_RESULT_GET_DATA) {
8297 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8298 "%s DEC_RESULT_GET_DATA %x %x %x\n",
8299 __func__,
8300 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8301 READ_VREG(VLD_MEM_VIFIFO_WP),
8302 READ_VREG(VLD_MEM_VIFIFO_RP));
8303 mutex_lock(&hw->chunks_mutex);
8304 vdec_vframe_dirty(vdec, hw->chunk);
8305 hw->chunk = NULL;
8306 mutex_unlock(&hw->chunks_mutex);
8307 vdec_clean_input(vdec);
8308 }
8309 if ((hw->dec_result == DEC_RESULT_GET_DATA_RETRY) &&
8310 ((1000 * (jiffies - hw->get_data_start_time) / HZ)
8311 > get_data_timeout_val)) {
8312 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8313 "%s DEC_RESULT_GET_DATA_RETRY timeout\n",
8314 __func__);
8315 goto result_done;
8316 }
8317 if (is_buffer_available(vdec)) {
8318 int r;
8319 int decode_size;
8320 r = vdec_prepare_input(vdec, &hw->chunk);
8321 if (r < 0 && (hw_to_vdec(hw)->next_status !=
8322 VDEC_STATUS_DISCONNECTED)) {
8323 hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
8324
8325 dpb_print(DECODE_ID(hw),
8326 PRINT_FLAG_VDEC_DETAIL,
8327 "vdec_prepare_input: Insufficient data\n");
8328 vdec_schedule_work(&hw->work);
8329 return;
8330 }
8331 hw->dec_result = DEC_RESULT_NONE;
8332 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8333 "%s: chunk size 0x%x\n",
8334 __func__, hw->chunk->size);
8335
8336 if (dpb_is_debug(DECODE_ID(hw),
8337 PRINT_FRAMEBASE_DATA)) {
8338 int jj;
8339 u8 *data = NULL;
8340
8341 if (!hw->chunk->block->is_mapped)
8342 data = codec_mm_vmap(
8343 hw->chunk->block->start +
8344 hw->chunk->offset, r);
8345 else
8346 data = ((u8 *)
8347 hw->chunk->block->start_virt)
8348 + hw->chunk->offset;
8349
8350 for (jj = 0; jj < r; jj++) {
8351 if ((jj & 0xf) == 0)
8352 dpb_print(DECODE_ID(hw),
8353 PRINT_FRAMEBASE_DATA,
8354 "%06x:", jj);
8355 dpb_print_cont(DECODE_ID(hw),
8356 PRINT_FRAMEBASE_DATA,
8357 "%02x ", data[jj]);
8358 if (((jj + 1) & 0xf) == 0)
8359 dpb_print_cont(DECODE_ID(hw),
8360 PRINT_FRAMEBASE_DATA,
8361 "\n");
8362 }
8363
8364 if (!hw->chunk->block->is_mapped)
8365 codec_mm_unmap_phyaddr(data);
8366 }
8367 WRITE_VREG(POWER_CTL_VLD,
8368 READ_VREG(POWER_CTL_VLD) |
8369 (0 << 10) | (1 << 9) | (1 << 6));
8370 WRITE_VREG(H264_DECODE_INFO, (1<<13));
8371 decode_size = hw->chunk->size +
8372 (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
8373 WRITE_VREG(H264_DECODE_SIZE, decode_size);
8374 WRITE_VREG(VIFF_BIT_CNT, decode_size * 8);
8375 vdec_enable_input(vdec);
8376
8377 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
8378 start_process_time(hw);
8379 } else{
8380 if (hw_to_vdec(hw)->next_status
8381 != VDEC_STATUS_DISCONNECTED) {
8382 hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
8383 vdec_schedule_work(&hw->work);
8384 }
8385 }
8386 return;
8387 } else if (hw->dec_result == DEC_RESULT_DONE) {
8388 /* if (!hw->ctx_valid)
8389 hw->ctx_valid = 1; */
8390result_done:
8391 {
8392 if (error_proc_policy & 0x8000) {
8393 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8394 int i;
8395 struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB;
8396
8397 for (i = 0; i < p_Dpb->used_size; i++) {
8398 if (p_Dpb->fs[i]->dpb_frame_count + 500 < p_H264_Dpb->dpb_frame_count) {
8399 dpb_print(DECODE_ID(hw),
8400 0,
8401 "unmark reference dpb_frame_count diffrence large in dpb\n");
8402 unmark_for_reference(p_Dpb, p_Dpb->fs[i]);
8403 }
8404 }
8405 }
8406 }
8407 if (hw->mmu_enable
8408 && hw->frame_busy && hw->frame_done) {
8409 long used_4k_num;
8410 hevc_sao_wait_done(hw);
8411 if (hw->hevc_cur_buf_idx != 0xffff) {
8412 used_4k_num =
8413 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
8414 if (used_4k_num >= 0)
8415 dpb_print(DECODE_ID(hw),
8416 PRINT_FLAG_MMU_DETAIL,
8417 "release unused buf , used_4k_num %ld index %d\n",
8418 used_4k_num, hw->hevc_cur_buf_idx);
8419 hevc_mmu_dma_check(hw_to_vdec(hw));
8420 decoder_mmu_box_free_idx_tail(
8421 hw->mmu_box,
8422 hw->hevc_cur_buf_idx,
8423 used_4k_num);
8424 hw->hevc_cur_buf_idx = 0xffff;
8425 }
8426 }
8427 decode_frame_count[DECODE_ID(hw)]++;
8428 amvdec_stop();
8429 if (!vdec_is_support_4k()) {
8430 if (clk_adj_frame_count < VDEC_CLOCK_ADJUST_FRAME) {
8431 clk_adj_frame_count++;
8432 if (clk_adj_frame_count == VDEC_CLOCK_ADJUST_FRAME)
8433 vdec_source_changed(VFORMAT_H264, 3840, 2160, 60);
8434 }
8435 }
8436 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8437 "%s dec_result %d %x %x %x\n",
8438 __func__,
8439 hw->dec_result,
8440 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8441 READ_VREG(VLD_MEM_VIFIFO_WP),
8442 READ_VREG(VLD_MEM_VIFIFO_RP));
8443 mutex_lock(&hw->chunks_mutex);
8444 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
8445 hw->chunk = NULL;
8446 mutex_unlock(&hw->chunks_mutex);
8447 } else if (hw->dec_result == DEC_RESULT_AGAIN) {
8448 /*
8449 stream base: stream buf empty or timeout
8450 frame base: vdec_prepare_input fail
8451 */
8452 if (!vdec_has_more_input(vdec) && (hw_to_vdec(hw)->next_status !=
8453 VDEC_STATUS_DISCONNECTED)) {
8454 hw->dec_result = DEC_RESULT_EOS;
8455 vdec_schedule_work(&hw->work);
8456 return;
8457 }
8458 hw->next_again_flag = 1;
8459 } else if (hw->dec_result == DEC_RESULT_EOS) {
8460 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8461 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8462 "%s: end of stream\n",
8463 __func__);
8464 amvdec_stop();
8465 if (hw->mmu_enable)
8466 amhevc_stop();
8467 hw->eos = 1;
8468 flush_dpb(p_H264_Dpb);
8469 if (hw->is_used_v4l)
8470 notify_v4l_eos(hw_to_vdec(hw));
8471 mutex_lock(&hw->chunks_mutex);
8472 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
8473 hw->chunk = NULL;
8474 mutex_unlock(&hw->chunks_mutex);
8475 vdec_clean_input(vdec);
8476 } else if (hw->dec_result == DEC_RESULT_FORCE_EXIT) {
8477 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8478 "%s: force exit\n",
8479 __func__);
8480 amvdec_stop();
8481 if (hw->mmu_enable)
8482 amhevc_stop();
8483 if (hw->stat & STAT_ISR_REG) {
8484 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
8485 hw->stat &= ~STAT_ISR_REG;
8486 }
8487 }
8488 WRITE_VREG(ASSIST_MBOX1_MASK, 0);
8489 del_timer_sync(&hw->check_timer);
8490 hw->stat &= ~STAT_TIMER_ARM;
8491#ifdef DETECT_WRONG_MULTI_SLICE
8492 if (hw->dec_result != DEC_RESULT_AGAIN)
8493 hw->last_picture_slice_count = 0;
8494#endif
8495 wait_vmh264_search_done(hw);
8496 /* mark itself has all HW resource released and input released */
8497
8498#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8499 if (hw->switch_dvlayer_flag) {
8500 if (vdec->slave)
8501 vdec_set_next_sched(vdec, vdec->slave);
8502 else if (vdec->master)
8503 vdec_set_next_sched(vdec, vdec->master);
8504 } else if (vdec->slave || vdec->master)
8505 vdec_set_next_sched(vdec, vdec);
8506#endif
8507
8508 if (from == 1) {
8509 /* This is a timeout work */
8510 if (work_pending(&hw->work)) {
8511 /*
8512 * The vh264_work arrives at the last second,
8513 * give it a chance to handle the scenario.
8514 */
8515 return;
8516 }
8517 }
8518
8519 /* mark itself has all HW resource released and input released */
8520 if (vdec->parallel_dec == 1) {
8521 if (hw->mmu_enable == 0)
8522 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1);
8523 else
8524 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
8525 } else
8526 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
8527
8528 wake_up_interruptible(&hw->wait_q);
8529
8530 if (hw->is_used_v4l) {
8531 struct aml_vcodec_ctx *ctx =
8532 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8533
8534 if (ctx->param_sets_from_ucode &&
8535 !hw->v4l_params_parsed)
8536 vdec_v4l_write_frame_sync(ctx);
8537 }
8538
8539 if (hw->vdec_cb)
8540 hw->vdec_cb(hw_to_vdec(hw), hw->vdec_cb_arg);
8541}
8542
8543
8544static void vh264_work(struct work_struct *work)
8545{
8546 struct vdec_h264_hw_s *hw = container_of(work,
8547 struct vdec_h264_hw_s, work);
8548 struct vdec_s *vdec = hw_to_vdec(hw);
8549
8550 vh264_work_implement(hw, vdec, 0);
8551}
8552
8553
8554static void vh264_timeout_work(struct work_struct *work)
8555{
8556 struct vdec_h264_hw_s *hw = container_of(work,
8557 struct vdec_h264_hw_s, timeout_work);
8558 struct vdec_s *vdec = hw_to_vdec(hw);
8559
8560 if (work_pending(&hw->work))
8561 return;
8562
8563 vh264_work_implement(hw, vdec, 1);
8564}
8565
8566static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask)
8567{
8568 bool ret = 0;
8569 struct vdec_h264_hw_s *hw =
8570 (struct vdec_h264_hw_s *)vdec->private;
8571 int tvp = vdec_secure(hw_to_vdec(hw)) ?
8572 CODEC_MM_FLAGS_TVP : 0;
8573
8574 if (!hw->first_sc_checked && hw->mmu_enable) {
8575 int size = decoder_mmu_box_sc_check(hw->mmu_box, tvp);
8576 hw->first_sc_checked =1;
8577 dpb_print(DECODE_ID(hw), 0,
8578 "vmh264 cached=%d need_size=%d speed= %d ms\n",
8579 size, (hw->need_cache_size >> PAGE_SHIFT),
8580 (int)(get_jiffies_64() - hw->sc_start_time) * 1000/HZ);
8581 }
8582
8583 if (vdec_stream_based(vdec) && (hw->init_flag == 0)
8584 && pre_decode_buf_level != 0) {
8585 u32 rp, wp, level;
8586
8587 rp = READ_PARSER_REG(PARSER_VIDEO_RP);
8588 wp = READ_PARSER_REG(PARSER_VIDEO_WP);
8589 if (wp < rp)
8590 level = vdec->input.size + wp - rp;
8591 else
8592 level = wp - rp;
8593
8594 if (level < pre_decode_buf_level)
8595 return 0;
8596 }
8597
8598#ifndef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8599 if (vdec->master)
8600 return 0;
8601#endif
8602 if (hw->eos)
8603 return 0;
8604
8605 if (hw->stat & DECODER_FATAL_ERROR_NO_MEM)
8606 return 0;
8607
8608 if (disp_vframe_valve_level &&
8609 kfifo_len(&hw->display_q) >=
8610 disp_vframe_valve_level) {
8611 hw->valve_count--;
8612 if (hw->valve_count <= 0)
8613 hw->valve_count = 2;
8614 else
8615 return 0;
8616 }
8617 if (hw->next_again_flag &&
8618 (!vdec_frame_based(vdec))) {
8619 u32 parser_wr_ptr =
8620 READ_PARSER_REG(PARSER_VIDEO_WP);
8621 if (parser_wr_ptr >= hw->pre_parser_wr_ptr &&
8622 (parser_wr_ptr - hw->pre_parser_wr_ptr) <
8623 again_threshold) {
8624 int r = vdec_sync_input(vdec);
8625 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
8626 "%s buf lelvel:%x\n", __func__, r);
8627 return 0;
8628 }
8629 }
8630
8631 if (h264_debug_flag & 0x20000000) {
8632 /* pr_info("%s, a\n", __func__); */
8633 ret = 1;
8634 } else
8635 ret = is_buffer_available(vdec);
8636
8637#ifdef CONSTRAIN_MAX_BUF_NUM
8638 if (hw->dpb.mDPB.size > 0) { /*make sure initilized*/
8639 if (run_ready_max_vf_only_num > 0 &&
8640 get_vf_ref_only_buf_count(hw) >=
8641 run_ready_max_vf_only_num
8642 )
8643 ret = 0;
8644 if (run_ready_display_q_num > 0 &&
8645 kfifo_len(&hw->display_q) >=
8646 run_ready_display_q_num)
8647 ret = 0;
8648 /*avoid more buffers consumed when
8649 switching resolution*/
8650 if (run_ready_max_buf_num == 0xff &&
8651 get_used_buf_count(hw) >
8652 hw->dpb.mDPB.size)
8653 ret = 0;
8654 else if (run_ready_max_buf_num &&
8655 get_used_buf_count(hw) >=
8656 run_ready_max_buf_num)
8657 ret = 0;
8658 }
8659#endif
8660 if (hw->is_used_v4l) {
8661 struct aml_vcodec_ctx *ctx =
8662 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8663
8664 if (ctx->param_sets_from_ucode) {
8665 if (hw->v4l_params_parsed) {
8666 if (!ctx->v4l_codec_dpb_ready &&
8667 v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx) <
8668 run_ready_min_buf_num)
8669 ret = 0;
8670 } else {
8671 if ((hw->res_ch_flag == 1) &&
8672 ((ctx->state <= AML_STATE_INIT) ||
8673 (ctx->state >= AML_STATE_FLUSHING)))
8674 ret = 0;
8675 }
8676 } else if (!ctx->v4l_codec_dpb_ready) {
8677 if (v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx) <
8678 run_ready_min_buf_num)
8679 ret = 0;
8680 }
8681
8682 }
8683
8684 if (ret)
8685 not_run_ready[DECODE_ID(hw)] = 0;
8686 else
8687 not_run_ready[DECODE_ID(hw)]++;
8688 if (vdec->parallel_dec == 1) {
8689 if (hw->mmu_enable == 0)
8690 return ret ? (CORE_MASK_VDEC_1) : 0;
8691 else
8692 return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
8693 } else
8694 return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
8695}
8696
8697static unsigned char get_data_check_sum
8698 (struct vdec_h264_hw_s *hw, int size)
8699{
8700 int jj;
8701 int sum = 0;
8702 u8 *data = NULL;
8703
8704 if (!hw->chunk->block->is_mapped)
8705 data = codec_mm_vmap(hw->chunk->block->start +
8706 hw->chunk->offset, size);
8707 else
8708 data = ((u8 *)hw->chunk->block->start_virt)
8709 + hw->chunk->offset;
8710
8711 for (jj = 0; jj < size; jj++)
8712 sum += data[jj];
8713
8714 if (!hw->chunk->block->is_mapped)
8715 codec_mm_unmap_phyaddr(data);
8716 return sum;
8717}
8718
8719static void run(struct vdec_s *vdec, unsigned long mask,
8720 void (*callback)(struct vdec_s *, void *), void *arg)
8721{
8722 struct vdec_h264_hw_s *hw =
8723 (struct vdec_h264_hw_s *)vdec->private;
8724 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8725 int size, ret = -1;
8726
8727 run_count[DECODE_ID(hw)]++;
8728 vdec_reset_core(vdec);
8729 if (hw->mmu_enable)
8730 hevc_reset_core(vdec);
8731 hw->vdec_cb_arg = arg;
8732 hw->vdec_cb = callback;
8733
8734#ifdef DETECT_WRONG_MULTI_SLICE
8735 hw->cur_picture_slice_count = 0;
8736#endif
8737
8738 if (kfifo_len(&hw->display_q) > VF_POOL_SIZE) {
8739 hw->reset_bufmgr_flag = 1;
8740 dpb_print(DECODE_ID(hw), 0,
8741 "kfifo len:%d invaild, need bufmgr reset\n",
8742 kfifo_len(&hw->display_q));
8743 }
8744
8745 hw->pre_parser_wr_ptr =
8746 READ_PARSER_REG(PARSER_VIDEO_WP);
8747 hw->next_again_flag = 0;
8748
8749 if (hw->reset_bufmgr_flag ||
8750 ((error_proc_policy & 0x40) &&
8751 p_H264_Dpb->buf_alloc_fail)) {
8752 h264_reset_bufmgr(vdec);
8753 hw->reset_bufmgr_flag = 0;
8754 }
8755
8756 if (h264_debug_cmd & 0xf000) {
8757 if (((h264_debug_cmd >> 12) & 0xf)
8758 == (DECODE_ID(hw) + 1)) {
8759 h264_reconfig(hw);
8760 h264_debug_cmd &= (~0xf000);
8761 }
8762 }
8763 /* hw->chunk = vdec_prepare_input(vdec); */
8764#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8765 if (vdec->slave || vdec->master)
8766 vdec_set_flag(vdec, VDEC_FLAG_SELF_INPUT_CONTEXT);
8767#endif
8768 size = vdec_prepare_input(vdec, &hw->chunk);
8769 if ((size < 0) ||
8770 (input_frame_based(vdec) && hw->chunk == NULL)) {
8771 input_empty[DECODE_ID(hw)]++;
8772 hw->dec_result = DEC_RESULT_AGAIN;
8773
8774 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
8775 "vdec_prepare_input: Insufficient data\n");
8776
8777 vdec_schedule_work(&hw->work);
8778 return;
8779 }
8780 input_empty[DECODE_ID(hw)] = 0;
8781
8782 hw->dec_result = DEC_RESULT_NONE;
8783 hw->get_data_count = 0;
8784#if 0
8785 pr_info("VLD_MEM_VIFIFO_LEVEL = 0x%x, rp = 0x%x, wp = 0x%x\n",
8786 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8787 READ_VREG(VLD_MEM_VIFIFO_RP),
8788 READ_VREG(VLD_MEM_VIFIFO_WP));
8789#endif
8790
8791 if (input_frame_based(vdec) && !vdec_secure(vdec)) {
8792 u8 *data = NULL;
8793
8794 if (!hw->chunk->block->is_mapped)
8795 data = codec_mm_vmap(hw->chunk->block->start +
8796 hw->chunk->offset, size);
8797 else
8798 data = ((u8 *)hw->chunk->block->start_virt)
8799 + hw->chunk->offset;
8800
8801 if (dpb_is_debug(DECODE_ID(hw),
8802 PRINT_FLAG_VDEC_STATUS)
8803 ) {
8804 dpb_print(DECODE_ID(hw), 0,
8805 "%s: size 0x%x sum 0x%x %02x %02x %02x %02x %02x %02x .. %02x %02x %02x %02x\n",
8806 __func__, size, get_data_check_sum(hw, size),
8807 data[0], data[1], data[2], data[3],
8808 data[4], data[5], data[size - 4],
8809 data[size - 3], data[size - 2],
8810 data[size - 1]);
8811 }
8812 if (dpb_is_debug(DECODE_ID(hw),
8813 PRINT_FRAMEBASE_DATA)
8814 ) {
8815 int jj;
8816
8817 for (jj = 0; jj < size; jj++) {
8818 if ((jj & 0xf) == 0)
8819 dpb_print(DECODE_ID(hw),
8820 PRINT_FRAMEBASE_DATA,
8821 "%06x:", jj);
8822 dpb_print_cont(DECODE_ID(hw),
8823 PRINT_FRAMEBASE_DATA,
8824 "%02x ", data[jj]);
8825 if (((jj + 1) & 0xf) == 0)
8826 dpb_print_cont(DECODE_ID(hw),
8827 PRINT_FRAMEBASE_DATA,
8828 "\n");
8829 }
8830 }
8831
8832 if (!hw->chunk->block->is_mapped)
8833 codec_mm_unmap_phyaddr(data);
8834 } else
8835 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8836 "%s: %x %x %x %x %x size 0x%x\n",
8837 __func__,
8838 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8839 READ_VREG(VLD_MEM_VIFIFO_WP),
8840 READ_VREG(VLD_MEM_VIFIFO_RP),
8841 READ_PARSER_REG(PARSER_VIDEO_RP),
8842 READ_PARSER_REG(PARSER_VIDEO_WP),
8843 size);
8844
8845 start_process_time(hw);
8846 if (vdec->mc_loaded) {
8847 /*firmware have load before,
8848 and not changes to another.
8849 ignore reload.
8850 */
8851 WRITE_VREG(AV_SCRATCH_G, hw->reg_g_status);
8852 } else {
8853
8854 ret = amvdec_vdec_loadmc_ex(VFORMAT_H264, "mh264", vdec, hw->fw->data);
8855 if (ret < 0) {
8856 amvdec_enable_flag = false;
8857 amvdec_disable();
8858
8859 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
8860 "MH264 the %s fw loading failed, err: %x\n",
8861 tee_enabled() ? "TEE" : "local", ret);
8862 hw->dec_result = DEC_RESULT_FORCE_EXIT;
8863 vdec_schedule_work(&hw->work);
8864 return;
8865 }
8866 vdec->mc_type = VFORMAT_H264;
8867 hw->reg_g_status = READ_VREG(AV_SCRATCH_G);
8868 if (hw->mmu_enable) {
8869 ret = amhevc_loadmc_ex(VFORMAT_H264, "mh264_mmu",
8870 hw->fw_mmu->data);
8871 if (ret < 0) {
8872 amvdec_enable_flag = false;
8873 amhevc_disable();
8874
8875 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
8876 "MH264_MMU the %s fw loading failed, err: %x\n",
8877 tee_enabled() ? "TEE" : "local", ret);
8878 hw->dec_result = DEC_RESULT_FORCE_EXIT;
8879 vdec_schedule_work(&hw->work);
8880 return;
8881 }
8882 vdec->mc_type = ((1 << 16) | VFORMAT_H264);
8883 }
8884 vdec->mc_loaded = 0;
8885 }
8886 vmh264_reset_udr_mgr(hw);
8887
8888 if (vh264_hw_ctx_restore(hw) < 0) {
8889 vdec_schedule_work(&hw->work);
8890 return;
8891 }
8892 if (input_frame_based(vdec)) {
8893 int decode_size = 0;
8894
8895 decode_size = hw->chunk->size +
8896 (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
8897 WRITE_VREG(H264_DECODE_INFO, (1<<13));
8898 WRITE_VREG(H264_DECODE_SIZE, decode_size);
8899 WRITE_VREG(VIFF_BIT_CNT, decode_size * 8);
8900 if (vdec->mvfrm)
8901 vdec->mvfrm->frame_size = hw->chunk->size;
8902 } else {
8903 if (size <= 0)
8904 size = 0x7fffffff; /*error happen*/
8905 WRITE_VREG(H264_DECODE_INFO, (1<<13));
8906 WRITE_VREG(H264_DECODE_SIZE, size);
8907 WRITE_VREG(VIFF_BIT_CNT, size * 8);
8908 }
8909 config_aux_buf(hw);
8910 config_decode_mode(hw);
8911 vdec_enable_input(vdec);
8912 WRITE_VREG(NAL_SEARCH_CTL, 0);
8913 hw->sei_data_len = 0;
8914 if (enable_itu_t35)
8915 WRITE_VREG(NAL_SEARCH_CTL, READ_VREG(NAL_SEARCH_CTL) | 0x1);
8916 if (!hw->init_flag) {
8917 if (hw->mmu_enable)
8918 WRITE_VREG(NAL_SEARCH_CTL,
8919 READ_VREG(NAL_SEARCH_CTL) | 0x2);
8920 else
8921 WRITE_VREG(NAL_SEARCH_CTL,
8922 READ_VREG(NAL_SEARCH_CTL) & (~0x2));
8923 }
8924 if (udebug_flag)
8925 WRITE_VREG(AV_SCRATCH_K, udebug_flag);
8926 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
8927
8928 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
8929
8930 if (hw->mmu_enable)
8931 SET_VREG_MASK(VDEC_ASSIST_MMC_CTRL1, 1 << 3);
8932 else
8933 CLEAR_VREG_MASK(VDEC_ASSIST_MMC_CTRL1, 1 << 3);
8934 }
8935 if (vdec->mvfrm)
8936 vdec->mvfrm->hw_decode_start = local_clock();
8937 amvdec_start();
8938 if (hw->mmu_enable /*&& !hw->frame_busy && !hw->frame_done*/) {
8939 WRITE_VREG(HEVC_ASSIST_SCRATCH_0, 0x0);
8940 amhevc_start();
8941 if (hw->config_bufmgr_done) {
8942 hevc_mcr_sao_global_hw_init(hw,
8943 (hw->mb_width << 4), (hw->mb_height << 4));
8944 hevc_mcr_config_canv2axitbl(hw, 1);
8945 }
8946 }
8947
8948 /* if (hw->init_flag) { */
8949 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
8950 /* } */
8951
8952 hw->init_flag = 1;
8953}
8954
8955static void clear_refer_bufs(struct vdec_h264_hw_s *hw)
8956{
8957 int i;
8958
8959 mutex_lock(&vmh264_mutex);
8960 dealloc_buf_specs(hw, 1);
8961 mutex_unlock(&vmh264_mutex);
8962
8963 INIT_KFIFO(hw->display_q);
8964 INIT_KFIFO(hw->newframe_q);
8965
8966 for (i = 0; i < VF_POOL_SIZE; i++) {
8967 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
8968 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8969 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
8970 kfifo_put(&hw->newframe_q, vf);
8971 }
8972}
8973
8974static void reset(struct vdec_s *vdec)
8975{
8976 struct vdec_h264_hw_s *hw =
8977 (struct vdec_h264_hw_s *)vdec->private;
8978
8979 pr_info("vmh264 reset\n");
8980
8981 cancel_work_sync(&hw->work);
8982 cancel_work_sync(&hw->notify_work);
8983 if (hw->stat & STAT_VDEC_RUN) {
8984 amvdec_stop();
8985 if (hw->mmu_enable)
8986 amhevc_stop();
8987 hw->stat &= ~STAT_VDEC_RUN;
8988 }
8989
8990 if (hw->stat & STAT_TIMER_ARM) {
8991 del_timer_sync(&hw->check_timer);
8992 hw->stat &= ~STAT_TIMER_ARM;
8993 }
8994 hw->eos = 0;
8995 hw->decode_pic_count = 0;
8996 hw->dec_result = DEC_RESULT_NONE;
8997
8998 clear_refer_bufs(hw);
8999 reset_process_time(hw);
9000 h264_reset_bufmgr(vdec);
9001
9002 dpb_print(DECODE_ID(hw), 0, "%s\n", __func__);
9003}
9004
9005static void h264_reconfig(struct vdec_h264_hw_s *hw)
9006{
9007 int i;
9008 unsigned long flags;
9009 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
9010 struct vdec_s *vdec = hw_to_vdec(hw);
9011 dpb_print(DECODE_ID(hw), 0,
9012 "%s\n", __func__);
9013 /* after calling flush_dpb() and bufmgr_h264_remove_unused_frame(),
9014 all buffers are in display queue (used == 2),
9015 or free (used == 0)
9016 */
9017 if (dpb_is_debug(DECODE_ID(hw),
9018 PRINT_FLAG_DUMP_BUFSPEC))
9019 dump_bufspec(hw, "pre h264_reconfig");
9020
9021 flush_dpb(p_H264_Dpb);
9022 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 0);
9023
9024 if (hw->collocate_cma_alloc_addr) {
9025 decoder_bmmu_box_free_idx(
9026 hw->bmmu_box,
9027 BMMU_REF_IDX);
9028 hw->collocate_cma_alloc_addr = 0;
9029 hw->dpb.colocated_mv_addr_start = 0;
9030 hw->dpb.colocated_mv_addr_end = 0;
9031 }
9032 spin_lock_irqsave(&hw->bufspec_lock, flags);
9033 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
9034 if (vdec->parallel_dec == 1) {
9035 vdec->free_canvas_ex(hw->buffer_spec[i].y_canvas_index, vdec->id);
9036 vdec->free_canvas_ex(hw->buffer_spec[i].u_canvas_index, vdec->id);
9037 vdec->free_canvas_ex(hw->buffer_spec[i].v_canvas_index, vdec->id);
9038 hw->buffer_spec[i].y_canvas_index = -1;
9039 hw->buffer_spec[i].u_canvas_index = -1;
9040 hw->buffer_spec[i].v_canvas_index = -1;
9041#ifdef VDEC_DW
9042 if (IS_VDEC_DW(hw)) {
9043 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_y_canvas_index, vdec->id);
9044 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_u_canvas_index, vdec->id);
9045 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_v_canvas_index, vdec->id);
9046 hw->buffer_spec[i].vdec_dw_y_canvas_index = -1;
9047 hw->buffer_spec[i].vdec_dw_u_canvas_index = -1;
9048 hw->buffer_spec[i].vdec_dw_v_canvas_index = -1;
9049#endif
9050 }
9051 }
9052 /*make sure buffers not put back to bufmgr when
9053 vf_put is called*/
9054 if (hw->buffer_spec[i].used == 2)
9055 hw->buffer_spec[i].used = 3;
9056
9057 /* ready to release "free buffers"
9058 */
9059 if (hw->buffer_spec[i].used == 0)
9060 hw->buffer_spec[i].used = 4;
9061
9062 hw->buffer_spec[i].canvas_pos = -1;
9063 }
9064 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
9065 hw->has_i_frame = 0;
9066 hw->config_bufmgr_done = 0;
9067
9068 if (hw->is_used_v4l) {
9069 mutex_lock(&vmh264_mutex);
9070 dealloc_buf_specs(hw, 1);
9071 mutex_unlock(&vmh264_mutex);
9072 }
9073
9074 if (dpb_is_debug(DECODE_ID(hw),
9075 PRINT_FLAG_DUMP_BUFSPEC))
9076 dump_bufspec(hw, "after h264_reconfig");
9077}
9078
9079#ifdef ERROR_HANDLE_TEST
9080static void h264_clear_dpb(struct vdec_h264_hw_s *hw)
9081{
9082 int i;
9083 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
9084 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
9085 "%s\n", __func__);
9086 remove_dpb_pictures(p_H264_Dpb);
9087 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
9088 /*make sure buffers not put back to bufmgr when
9089 vf_put is called*/
9090 if (hw->buffer_spec[i].used == 2)
9091 hw->buffer_spec[i].used = 5;
9092 }
9093
9094}
9095#endif
9096
9097static void h264_reset_bufmgr(struct vdec_s *vdec)
9098{
9099 ulong timeout;
9100 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
9101 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
9102#if 0
9103 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
9104 int actual_dpb_size, max_reference_size;
9105 int reorder_pic_num;
9106 unsigned int colocated_buf_size;
9107 unsigned int colocated_mv_addr_start;
9108 unsigned int colocated_mv_addr_end;
9109 dpb_print(DECODE_ID(hw), 0,
9110 "%s\n", __func__);
9111
9112 for (i = 0; i < VF_POOL_SIZE; i++)
9113 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
9114
9115 actual_dpb_size = p_H264_Dpb->mDPB.size;
9116 max_reference_size = p_H264_Dpb->max_reference_size;
9117 reorder_pic_num = p_H264_Dpb->reorder_pic_num;
9118
9119 colocated_buf_size = p_H264_Dpb->colocated_buf_size;
9120 colocated_mv_addr_start = p_H264_Dpb->colocated_mv_addr_start;
9121 colocated_mv_addr_end = p_H264_Dpb->colocated_mv_addr_end;
9122
9123 hw->cur_pool++;
9124 if (hw->cur_pool >= VF_POOL_NUM)
9125 hw->cur_pool = 0;
9126
9127 INIT_KFIFO(hw->display_q);
9128 INIT_KFIFO(hw->newframe_q);
9129
9130 for (i = 0; i < VF_POOL_SIZE; i++) {
9131 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
9132 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
9133 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
9134 kfifo_put(&hw->newframe_q, vf);
9135 }
9136
9137 for (i = 0; i < BUFSPEC_POOL_SIZE; i++)
9138 hw->buffer_spec[i].used = 0;
9139
9140 dpb_init_global(&hw->dpb,
9141 DECODE_ID(hw), 0, 0);
9142 p_H264_Dpb->mDPB.size = actual_dpb_size;
9143 p_H264_Dpb->max_reference_size = max_reference_size;
9144 p_H264_Dpb->reorder_pic_num = reorder_pic_num;
9145
9146 p_H264_Dpb->colocated_buf_size = colocated_buf_size;
9147 p_H264_Dpb->colocated_mv_addr_start = colocated_mv_addr_start;
9148 p_H264_Dpb->colocated_mv_addr_end = colocated_mv_addr_end;
9149
9150 p_H264_Dpb->fast_output_enable = fast_output_enable;
9151 hw->has_i_frame = 0;
9152#else
9153 dpb_print(DECODE_ID(hw), 0,
9154 "%s frame count %d to skip %d\n\n",
9155 __func__, hw->decode_pic_count+1,
9156 hw->skip_frame_count);
9157
9158 flush_dpb(&hw->dpb);
9159
9160 timeout = jiffies + HZ;
9161 while (kfifo_len(&hw->display_q) > 0) {
9162 if (time_after(jiffies, timeout))
9163 break;
9164 schedule();
9165 }
9166
9167 buf_spec_init(hw);
9168
9169 vh264_local_init(hw, true);
9170 /*hw->decode_pic_count = 0;
9171 hw->seq_info2 = 0;*/
9172
9173 if (vh264_set_params(hw,
9174 hw->cfg_param1,
9175 hw->cfg_param2,
9176 hw->cfg_param3,
9177 hw->cfg_param4) < 0)
9178 hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
9179
9180 /*drop 3 frames after reset bufmgr if bit0 is set 1 */
9181 if (first_i_policy & 0x01)
9182 hw->first_i_policy = (3 << 8) | first_i_policy;
9183
9184 p_H264_Dpb->first_insert_frame = FirstInsertFrm_RESET;
9185
9186 hw->init_flag = 1;
9187
9188 hw->reset_bufmgr_count++;
9189#endif
9190}
9191
9192int ammvdec_h264_mmu_init(struct vdec_h264_hw_s *hw)
9193{
9194 int ret = -1;
9195 int tvp_flag = vdec_secure(hw_to_vdec(hw)) ?
9196 CODEC_MM_FLAGS_TVP : 0;
9197 int buf_size = 64;
9198
9199 pr_debug("ammvdec_h264_mmu_init tvp = 0x%x mmu_enable %d\n",
9200 tvp_flag, hw->mmu_enable);
9201 hw->need_cache_size = buf_size * SZ_1M;
9202 hw->sc_start_time = get_jiffies_64();
9203 if (hw->mmu_enable && !hw->mmu_box) {
9204 hw->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME,
9205 hw->id,
9206 MMU_MAX_BUFFERS,
9207 hw->need_cache_size,
9208 tvp_flag);
9209 if (!hw->mmu_box) {
9210 pr_err("h264 4k alloc mmu box failed!!\n");
9211 return -1;
9212 }
9213 ret = 0;
9214 }
9215 if (!hw->bmmu_box) {
9216 hw->bmmu_box = decoder_bmmu_box_alloc_box(
9217 DRIVER_NAME,
9218 hw->id,
9219 BMMU_MAX_BUFFERS,
9220 4 + PAGE_SHIFT,
9221 CODEC_MM_FLAGS_CMA_CLEAR |
9222 CODEC_MM_FLAGS_FOR_VDECODER |
9223 tvp_flag);
9224 if (hw->bmmu_box)
9225 ret = 0;
9226 }
9227 return ret;
9228}
9229int ammvdec_h264_mmu_release(struct vdec_h264_hw_s *hw)
9230{
9231 if (hw->mmu_box) {
9232 decoder_mmu_box_free(hw->mmu_box);
9233 hw->mmu_box = NULL;
9234 }
9235 if (hw->bmmu_box) {
9236 decoder_bmmu_box_free(hw->bmmu_box);
9237 hw->bmmu_box = NULL;
9238 }
9239 return 0;
9240}
9241
9242static int ammvdec_h264_probe(struct platform_device *pdev)
9243{
9244 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
9245 struct vdec_h264_hw_s *hw = NULL;
9246 char *tmpbuf;
9247 int config_val;
9248
9249 if (pdata == NULL) {
9250 pr_info("\nammvdec_h264 memory resource undefined.\n");
9251 return -EFAULT;
9252 }
9253
9254 hw = (struct vdec_h264_hw_s *)h264_alloc_hw_stru(&pdev->dev,
9255 sizeof(struct vdec_h264_hw_s), GFP_KERNEL);
9256 if (hw == NULL) {
9257 pr_info("\nammvdec_h264 device data allocation failed\n");
9258 return -ENOMEM;
9259 }
9260 hw->id = pdev->id;
9261 hw->platform_dev = pdev;
9262
9263 /* the ctx from v4l2 driver. */
9264 hw->v4l2_ctx = pdata->private;
9265
9266 platform_set_drvdata(pdev, pdata);
9267
9268 hw->mmu_enable = 0;
9269 hw->first_head_check_flag = 0;
9270
9271 if (pdata->sys_info)
9272 hw->vh264_amstream_dec_info = *pdata->sys_info;
9273
9274 if (force_enable_mmu && pdata->sys_info &&
9275 (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TXLX) &&
9276 (get_cpu_major_id() != AM_MESON_CPU_MAJOR_ID_GXLX) &&
9277 (pdata->sys_info->height * pdata->sys_info->width
9278 > 1920 * 1088))
9279 hw->mmu_enable = 1;
9280
9281 if (hw->mmu_enable &&
9282 (pdata->frame_base_video_path == FRAME_BASE_PATH_IONVIDEO)) {
9283 hw->mmu_enable = 0;
9284 pr_info("ionvideo needs disable mmu, path= %d \n",
9285 pdata->frame_base_video_path);
9286 }
9287
9288 if (ammvdec_h264_mmu_init(hw)) {
9289 h264_free_hw_stru(&pdev->dev, (void *)hw);
9290 pr_info("\nammvdec_h264 mmu alloc failed!\n");
9291 return -ENOMEM;
9292 }
9293
9294 if (pdata->config_len) {
9295 /*use ptr config for doubel_write_mode, etc*/
9296 if (get_config_int(pdata->config,
9297 "mh264_double_write_mode", &config_val) == 0)
9298 hw->double_write_mode = config_val;
9299 else
9300 hw->double_write_mode = double_write_mode;
9301
9302 if (get_config_int(pdata->config,
9303 "parm_v4l_codec_enable",
9304 &config_val) == 0)
9305 hw->is_used_v4l = config_val;
9306
9307 if (get_config_int(pdata->config,
9308 "parm_v4l_buffer_margin",
9309 &config_val) == 0)
9310 hw->reorder_dpb_size_margin = config_val;
9311
9312 if (get_config_int(pdata->config,
9313 "parm_v4l_canvas_mem_mode",
9314 &config_val) == 0)
9315 hw->canvas_mode = config_val;
9316 } else
9317 hw->double_write_mode = double_write_mode;
9318
9319 if (!hw->is_used_v4l) {
9320 hw->reorder_dpb_size_margin = reorder_dpb_size_margin;
9321 hw->canvas_mode = mem_map_mode;
9322
9323 if ((h264_debug_flag & IGNORE_PARAM_FROM_CONFIG) == 0)
9324 hw->canvas_mode = pdata->canvas_mode;
9325 }
9326
9327 if (hw->mmu_enable)
9328 hw->double_write_mode &= 0xffff;
9329
9330 if (pdata->parallel_dec == 1) {
9331 int i;
9332 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
9333 hw->buffer_spec[i].y_canvas_index = -1;
9334 hw->buffer_spec[i].u_canvas_index = -1;
9335 hw->buffer_spec[i].v_canvas_index = -1;
9336#ifdef VDEC_DW
9337 if (IS_VDEC_DW(hw)) {
9338 hw->buffer_spec[i].vdec_dw_y_canvas_index = -1;
9339 hw->buffer_spec[i].vdec_dw_u_canvas_index = -1;
9340 hw->buffer_spec[i].vdec_dw_v_canvas_index = -1;
9341 }
9342#endif
9343 }
9344 }
9345
9346 dpb_print(DECODE_ID(hw), 0,
9347 "%s mmu_enable %d double_write_mode 0x%x\n",
9348 __func__, hw->mmu_enable, hw->double_write_mode);
9349
9350 pdata->private = hw;
9351 pdata->dec_status = dec_status;
9352 pdata->set_trickmode = vmh264_set_trickmode;
9353 pdata->run_ready = run_ready;
9354 pdata->run = run;
9355 pdata->reset = reset;
9356 pdata->irq_handler = vh264_isr;
9357 pdata->threaded_irq_handler = vh264_isr_thread_fn;
9358 pdata->dump_state = vmh264_dump_state;
9359
9360#ifdef MH264_USERDATA_ENABLE
9361 pdata->wakeup_userdata_poll = vmh264_wakeup_userdata_poll;
9362 pdata->user_data_read = vmh264_user_data_read;
9363 pdata->reset_userdata_fifo = vmh264_reset_userdata_fifo;
9364#else
9365 pdata->wakeup_userdata_poll = NULL;
9366 pdata->user_data_read = NULL;
9367 pdata->reset_userdata_fifo = NULL;
9368#endif
9369 if (pdata->use_vfm_path) {
9370 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
9371 VFM_DEC_PROVIDER_NAME);
9372 hw->frameinfo_enable = 1;
9373 }
9374#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9375 else if (vdec_dual(pdata)) {
9376 if (dv_toggle_prov_name) /*debug purpose*/
9377 snprintf(pdata->vf_provider_name,
9378 VDEC_PROVIDER_NAME_SIZE,
9379 (pdata->master) ? VFM_DEC_DVBL_PROVIDER_NAME :
9380 VFM_DEC_DVEL_PROVIDER_NAME);
9381 else
9382 snprintf(pdata->vf_provider_name,
9383 VDEC_PROVIDER_NAME_SIZE,
9384 (pdata->master) ? VFM_DEC_DVEL_PROVIDER_NAME :
9385 VFM_DEC_DVBL_PROVIDER_NAME);
9386 }
9387#endif
9388 else
9389 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
9390 PROVIDER_NAME ".%02x", pdev->id & 0xff);
9391
9392 vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
9393 &vf_provider_ops, pdata);
9394
9395 platform_set_drvdata(pdev, pdata);
9396
9397 buf_spec_init(hw);
9398
9399 hw->platform_dev = pdev;
9400
9401#ifdef DUMP_USERDATA_RECORD
9402 vmh264_init_userdata_dump();
9403 vmh264_reset_user_data_buf();
9404#endif
9405 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_DPB_IDX,
9406 V_BUF_ADDR_OFFSET, DRIVER_NAME, &hw->cma_alloc_addr) < 0) {
9407 h264_free_hw_stru(&pdev->dev, (void *)hw);
9408 pdata->dec_status = NULL;
9409 return -ENOMEM;
9410 }
9411
9412 hw->buf_offset = hw->cma_alloc_addr - DEF_BUF_START_ADDR +
9413 DCAC_READ_MARGIN;
9414 if (hw->mmu_enable) {
9415 u32 extif_size = EXTIF_BUF_SIZE;
9416 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A)
9417 extif_size <<= 1;
9418 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_EXTIF_IDX,
9419 extif_size, DRIVER_NAME, &hw->extif_addr) < 0) {
9420 h264_free_hw_stru(&pdev->dev, (void *)hw);
9421 pdata->dec_status = NULL;
9422 return -ENOMEM;
9423 }
9424 }
9425 if (!vdec_secure(pdata)) {
9426#if 1
9427 /*init internal buf*/
9428 tmpbuf = (char *)codec_mm_phys_to_virt(hw->cma_alloc_addr);
9429 if (tmpbuf) {
9430 memset(tmpbuf, 0, V_BUF_ADDR_OFFSET);
9431 codec_mm_dma_flush(tmpbuf,
9432 V_BUF_ADDR_OFFSET,
9433 DMA_TO_DEVICE);
9434 } else {
9435 tmpbuf = codec_mm_vmap(hw->cma_alloc_addr,
9436 V_BUF_ADDR_OFFSET);
9437 if (tmpbuf) {
9438 memset(tmpbuf, 0, V_BUF_ADDR_OFFSET);
9439 codec_mm_dma_flush(tmpbuf,
9440 V_BUF_ADDR_OFFSET,
9441 DMA_TO_DEVICE);
9442 codec_mm_unmap_phyaddr(tmpbuf);
9443 }
9444 }
9445#else
9446 /*init sps/pps internal buf 64k*/
9447 tmpbuf = (char *)codec_mm_phys_to_virt(hw->cma_alloc_addr
9448 + (mem_sps_base - DEF_BUF_START_ADDR));
9449 memset(tmpbuf, 0, 0x10000);
9450 dma_sync_single_for_device(amports_get_dma_device(),
9451 hw->cma_alloc_addr +
9452 (mem_sps_base - DEF_BUF_START_ADDR),
9453 0x10000, DMA_TO_DEVICE);
9454#endif
9455 }
9456 /**/
9457
9458#if 0
9459 if (NULL == hw->sei_data_buffer) {
9460 hw->sei_data_buffer =
9461 dma_alloc_coherent(amports_get_dma_device(),
9462 USER_DATA_SIZE,
9463 &hw->sei_data_buffer_phys, GFP_KERNEL);
9464 if (!hw->sei_data_buffer) {
9465 pr_info("%s: Can not allocate sei_data_buffer\n",
9466 __func__);
9467 ammvdec_h264_mmu_release(hw);
9468 h264_free_hw_stru(&pdev->dev, (void *)hw);
9469 return -ENOMEM;
9470 }
9471 /* pr_info("buffer 0x%x, phys 0x%x, remap 0x%x\n",
9472 sei_data_buffer, sei_data_buffer_phys,
9473 (u32)sei_data_buffer_remap); */
9474 }
9475#endif
9476 dpb_print(DECODE_ID(hw), 0, "ammvdec_h264 mem-addr=%lx,buff_offset=%x,buf_start=%lx\n",
9477 pdata->mem_start, hw->buf_offset, hw->cma_alloc_addr);
9478
9479 if (vdec_is_support_4k() ||
9480 (clk_adj_frame_count > (VDEC_CLOCK_ADJUST_FRAME - 1)))
9481 vdec_source_changed(VFORMAT_H264, 3840, 2160, 60);
9482 else if (pdata->sys_info->height * pdata->sys_info->width <= 1280 * 720)
9483 {
9484 vdec_source_changed(VFORMAT_H264, 1280, 720, 29);
9485 }else
9486 {
9487 vdec_source_changed(VFORMAT_H264, 1920, 1080, 29);
9488 }
9489
9490 if (vh264_init(hw) < 0) {
9491 pr_info("\nammvdec_h264 init failed.\n");
9492 ammvdec_h264_mmu_release(hw);
9493 h264_free_hw_stru(&pdev->dev, (void *)hw);
9494 pdata->dec_status = NULL;
9495 return -ENODEV;
9496 }
9497#ifdef MH264_USERDATA_ENABLE
9498 vmh264_crate_userdata_manager(hw,
9499 hw->sei_user_data_buffer,
9500 USER_DATA_SIZE);
9501#endif
9502
9503 vdec_set_prepare_level(pdata, start_decode_buf_level);
9504 if (pdata->parallel_dec == 1) {
9505 if (hw->mmu_enable == 0)
9506 vdec_core_request(pdata, CORE_MASK_VDEC_1);
9507 else {
9508 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9509 | CORE_MASK_COMBINE);
9510 }
9511 } else
9512 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9513 | CORE_MASK_COMBINE);
9514
9515 atomic_set(&hw->vh264_active, 1);
9516 vdec_set_vframe_comm(pdata, DRIVER_NAME);
9517 display_frame_count[DECODE_ID(hw)] = 0;
9518 decode_frame_count[DECODE_ID(hw)] = 0;
9519
9520 return 0;
9521}
9522
9523static int ammvdec_h264_remove(struct platform_device *pdev)
9524{
9525 struct vdec_h264_hw_s *hw =
9526 (struct vdec_h264_hw_s *)
9527 (((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
9528 int i;
9529
9530 struct vdec_s *vdec = hw_to_vdec(hw);
9531
9532 if (vdec->next_status == VDEC_STATUS_DISCONNECTED
9533 && (vdec->status == VDEC_STATUS_ACTIVE)) {
9534 dpb_print(DECODE_ID(hw), 0,
9535 "%s force exit %d\n", __func__, __LINE__);
9536 hw->dec_result = DEC_RESULT_FORCE_EXIT;
9537 vdec_schedule_work(&hw->work);
9538 wait_event_interruptible_timeout(hw->wait_q,
9539 (vdec->status == VDEC_STATUS_CONNECTED),
9540 msecs_to_jiffies(1000)); /* wait for work done */
9541 }
9542
9543 for (i = 0; i < BUFSPEC_POOL_SIZE; i++)
9544 release_aux_data(hw, i);
9545
9546 atomic_set(&hw->vh264_active, 0);
9547
9548 if (hw->stat & STAT_TIMER_ARM) {
9549 del_timer_sync(&hw->check_timer);
9550 hw->stat &= ~STAT_TIMER_ARM;
9551 }
9552
9553 vh264_stop(hw);
9554#ifdef MH264_USERDATA_ENABLE
9555#ifdef DUMP_USERDATA_RECORD
9556 vmh264_dump_userdata();
9557#endif
9558 vmh264_destroy_userdata_manager(hw);
9559#endif
9560 /* vdec_source_changed(VFORMAT_H264, 0, 0, 0); */
9561
9562 atomic_set(&hw->vh264_active, 0);
9563 if (vdec->parallel_dec == 1) {
9564 if (hw->mmu_enable == 0)
9565 vdec_core_release(vdec, CORE_MASK_VDEC_1);
9566 else
9567 vdec_core_release(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC |
9568 CORE_MASK_COMBINE);
9569 } else
9570 vdec_core_release(hw_to_vdec(hw), CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
9571
9572 vdec_set_status(hw_to_vdec(hw), VDEC_STATUS_DISCONNECTED);
9573 if (vdec->parallel_dec == 1) {
9574 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
9575 vdec->free_canvas_ex(hw->buffer_spec[i].y_canvas_index, vdec->id);
9576 vdec->free_canvas_ex(hw->buffer_spec[i].u_canvas_index, vdec->id);
9577 vdec->free_canvas_ex(hw->buffer_spec[i].v_canvas_index, vdec->id);
9578 if (IS_VDEC_DW(hw)) {
9579 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_y_canvas_index, vdec->id);
9580 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_u_canvas_index, vdec->id);
9581 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_v_canvas_index, vdec->id);
9582 }
9583 }
9584 }
9585
9586 ammvdec_h264_mmu_release(hw);
9587 h264_free_hw_stru(&pdev->dev, (void *)hw);
9588 clk_adj_frame_count = 0;
9589
9590 return 0;
9591}
9592
9593/****************************************/
9594#ifdef CONFIG_PM
9595static int mh264_suspend(struct device *dev)
9596{
9597 amvdec_suspend(to_platform_device(dev), dev->power.power_state);
9598 return 0;
9599}
9600
9601static int mh264_resume(struct device *dev)
9602{
9603 amvdec_resume(to_platform_device(dev));
9604 return 0;
9605}
9606
9607static const struct dev_pm_ops mh264_pm_ops = {
9608 SET_SYSTEM_SLEEP_PM_OPS(mh264_suspend, mh264_resume)
9609};
9610#endif
9611
9612static struct platform_driver ammvdec_h264_driver = {
9613 .probe = ammvdec_h264_probe,
9614 .remove = ammvdec_h264_remove,
9615 .driver = {
9616 .name = DRIVER_NAME,
9617#ifdef CONFIG_PM
9618 .pm = &mh264_pm_ops,
9619#endif
9620 }
9621};
9622
9623static struct codec_profile_t ammvdec_h264_profile = {
9624 .name = "mh264",
9625 .profile = ""
9626};
9627
9628static struct mconfig hm264_configs[] = {
9629 MC_PU32("h264_debug_flag", &h264_debug_flag),
9630 MC_PI32("start_decode_buf_level", &start_decode_buf_level),
9631 MC_PU32("fixed_frame_rate_mode", &fixed_frame_rate_mode),
9632 MC_PU32("decode_timeout_val", &decode_timeout_val),
9633 MC_PU32("reorder_dpb_size_margin", &reorder_dpb_size_margin),
9634 MC_PU32("reference_buf_margin", &reference_buf_margin),
9635 MC_PU32("radr", &radr),
9636 MC_PU32("rval", &rval),
9637 MC_PU32("h264_debug_mask", &h264_debug_mask),
9638 MC_PU32("h264_debug_cmd", &h264_debug_cmd),
9639 MC_PI32("force_rate_streambase", &force_rate_streambase),
9640 MC_PI32("dec_control", &dec_control),
9641 MC_PI32("force_rate_framebase", &force_rate_framebase),
9642 MC_PI32("force_disp_bufspec_num", &force_disp_bufspec_num),
9643 MC_PU32("prefix_aux_buf_size", &prefix_aux_buf_size),
9644 MC_PU32("suffix_aux_buf_size", &suffix_aux_buf_size),
9645#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9646 MC_PU32("reorder_dpb_size_margin_dv", &reorder_dpb_size_margin_dv),
9647 MC_PU32("dv_toggle_prov_name", &dv_toggle_prov_name),
9648 MC_PU32("dolby_meta_with_el", &dolby_meta_with_el),
9649#endif
9650 MC_PU32("i_only_flag", &i_only_flag),
9651 MC_PU32("force_rate_streambase", &force_rate_streambase),
9652};
9653static struct mconfig_node hm264_node;
9654
9655
9656static int __init ammvdec_h264_driver_init_module(void)
9657{
9658 pr_info("ammvdec_h264 module init\n");
9659 if (platform_driver_register(&ammvdec_h264_driver)) {
9660 pr_info("failed to register ammvdec_h264 driver\n");
9661 return -ENODEV;
9662 }
9663
9664 if (vdec_is_support_4k()) {
9665 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TXLX) {
9666 ammvdec_h264_profile.profile =
9667 "4k, dwrite, compressed";
9668 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXTVBB) {
9669 ammvdec_h264_profile.profile = "4k";
9670 }
9671 }
9672
9673 vcodec_profile_register(&ammvdec_h264_profile);
9674 INIT_REG_NODE_CONFIGS("media.decoder", &hm264_node,
9675 "mh264", hm264_configs, CONFIG_FOR_RW);
9676 return 0;
9677}
9678
9679static void __exit ammvdec_h264_driver_remove_module(void)
9680{
9681 pr_info("ammvdec_h264 module remove.\n");
9682
9683 platform_driver_unregister(&ammvdec_h264_driver);
9684}
9685
9686/****************************************/
9687module_param(h264_debug_flag, uint, 0664);
9688MODULE_PARM_DESC(h264_debug_flag, "\n ammvdec_h264 h264_debug_flag\n");
9689
9690module_param(start_decode_buf_level, int, 0664);
9691MODULE_PARM_DESC(start_decode_buf_level,
9692 "\n ammvdec_h264 start_decode_buf_level\n");
9693
9694module_param(pre_decode_buf_level, int, 0664);
9695MODULE_PARM_DESC(pre_decode_buf_level, "\n ammvdec_h264 pre_decode_buf_level\n");
9696
9697module_param(fixed_frame_rate_mode, uint, 0664);
9698MODULE_PARM_DESC(fixed_frame_rate_mode, "\namvdec_h264 fixed_frame_rate_mode\n");
9699
9700module_param(decode_timeout_val, uint, 0664);
9701MODULE_PARM_DESC(decode_timeout_val, "\n amvdec_h264 decode_timeout_val\n");
9702
9703module_param(errordata_timeout_val, uint, 0664);
9704MODULE_PARM_DESC(errordata_timeout_val, "\n amvdec_h264 errordata_timeout_val\n");
9705
9706module_param(get_data_timeout_val, uint, 0664);
9707MODULE_PARM_DESC(get_data_timeout_val, "\n amvdec_h264 get_data_timeout_val\n");
9708
9709module_param(frame_max_data_packet, uint, 0664);
9710MODULE_PARM_DESC(frame_max_data_packet, "\n amvdec_h264 frame_max_data_packet\n");
9711
9712module_param(reorder_dpb_size_margin, uint, 0664);
9713MODULE_PARM_DESC(reorder_dpb_size_margin, "\n ammvdec_h264 reorder_dpb_size_margin\n");
9714
9715#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9716module_param(reorder_dpb_size_margin_dv, uint, 0664);
9717MODULE_PARM_DESC(reorder_dpb_size_margin_dv,
9718 "\n ammvdec_h264 reorder_dpb_size_margin_dv\n");
9719#endif
9720
9721module_param(reference_buf_margin, uint, 0664);
9722MODULE_PARM_DESC(reference_buf_margin, "\n ammvdec_h264 reference_buf_margin\n");
9723
9724#ifdef CONSTRAIN_MAX_BUF_NUM
9725module_param(run_ready_max_vf_only_num, uint, 0664);
9726MODULE_PARM_DESC(run_ready_max_vf_only_num, "\n run_ready_max_vf_only_num\n");
9727
9728module_param(run_ready_display_q_num, uint, 0664);
9729MODULE_PARM_DESC(run_ready_display_q_num, "\n run_ready_display_q_num\n");
9730
9731module_param(run_ready_max_buf_num, uint, 0664);
9732MODULE_PARM_DESC(run_ready_max_buf_num, "\n run_ready_max_buf_num\n");
9733#endif
9734
9735module_param(radr, uint, 0664);
9736MODULE_PARM_DESC(radr, "\nradr\n");
9737
9738module_param(rval, uint, 0664);
9739MODULE_PARM_DESC(rval, "\nrval\n");
9740
9741module_param(h264_debug_mask, uint, 0664);
9742MODULE_PARM_DESC(h264_debug_mask, "\n amvdec_h264 h264_debug_mask\n");
9743
9744module_param(h264_debug_cmd, uint, 0664);
9745MODULE_PARM_DESC(h264_debug_cmd, "\n amvdec_h264 h264_debug_cmd\n");
9746
9747module_param(force_rate_streambase, int, 0664);
9748MODULE_PARM_DESC(force_rate_streambase, "\n amvdec_h264 force_rate_streambase\n");
9749
9750module_param(dec_control, int, 0664);
9751MODULE_PARM_DESC(dec_control, "\n amvdec_h264 dec_control\n");
9752
9753module_param(force_rate_framebase, int, 0664);
9754MODULE_PARM_DESC(force_rate_framebase, "\n amvdec_h264 force_rate_framebase\n");
9755
9756module_param(force_disp_bufspec_num, int, 0664);
9757MODULE_PARM_DESC(force_disp_bufspec_num, "\n amvdec_h264 force_disp_bufspec_num\n");
9758
9759module_param(V_BUF_ADDR_OFFSET, int, 0664);
9760MODULE_PARM_DESC(V_BUF_ADDR_OFFSET, "\n amvdec_h264 V_BUF_ADDR_OFFSET\n");
9761
9762module_param(prefix_aux_buf_size, uint, 0664);
9763MODULE_PARM_DESC(prefix_aux_buf_size, "\n prefix_aux_buf_size\n");
9764
9765module_param(suffix_aux_buf_size, uint, 0664);
9766MODULE_PARM_DESC(suffix_aux_buf_size, "\n suffix_aux_buf_size\n");
9767
9768#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9769module_param(dv_toggle_prov_name, uint, 0664);
9770MODULE_PARM_DESC(dv_toggle_prov_name, "\n dv_toggle_prov_name\n");
9771
9772module_param(dolby_meta_with_el, uint, 0664);
9773MODULE_PARM_DESC(dolby_meta_with_el, "\n dolby_meta_with_el\n");
9774
9775#endif
9776
9777module_param(fast_output_enable, uint, 0664);
9778MODULE_PARM_DESC(fast_output_enable, "\n amvdec_h264 fast_output_enable\n");
9779
9780module_param(error_proc_policy, uint, 0664);
9781MODULE_PARM_DESC(error_proc_policy, "\n amvdec_h264 error_proc_policy\n");
9782
9783module_param(error_skip_count, uint, 0664);
9784MODULE_PARM_DESC(error_skip_count, "\n amvdec_h264 error_skip_count\n");
9785
9786module_param(force_sliding_margin, uint, 0664);
9787MODULE_PARM_DESC(force_sliding_margin, "\n amvdec_h264 force_sliding_margin\n");
9788
9789module_param(i_only_flag, uint, 0664);
9790MODULE_PARM_DESC(i_only_flag, "\n amvdec_h264 i_only_flag\n");
9791
9792module_param(first_i_policy, uint, 0664);
9793MODULE_PARM_DESC(first_i_policy, "\n amvdec_h264 first_i_policy\n");
9794
9795module_param(frmbase_cont_bitlevel, uint, 0664);
9796MODULE_PARM_DESC(frmbase_cont_bitlevel,
9797 "\n amvdec_h264 frmbase_cont_bitlevel\n");
9798
9799module_param(frmbase_cont_bitlevel2, uint, 0664);
9800MODULE_PARM_DESC(frmbase_cont_bitlevel2,
9801 "\n amvdec_h264 frmbase_cont_bitlevel\n");
9802
9803module_param(udebug_flag, uint, 0664);
9804MODULE_PARM_DESC(udebug_flag, "\n amvdec_mh264 udebug_flag\n");
9805
9806module_param(udebug_pause_pos, uint, 0664);
9807MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n");
9808
9809module_param(udebug_pause_val, uint, 0664);
9810MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n");
9811
9812module_param(udebug_pause_decode_idx, uint, 0664);
9813MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n");
9814
9815module_param(max_alloc_buf_count, uint, 0664);
9816MODULE_PARM_DESC(max_alloc_buf_count, "\n amvdec_h264 max_alloc_buf_count\n");
9817
9818module_param(enable_itu_t35, uint, 0664);
9819MODULE_PARM_DESC(enable_itu_t35, "\n amvdec_h264 enable_itu_t35\n");
9820
9821module_param(endian, uint, 0664);
9822MODULE_PARM_DESC(endian, "\nrval\n");
9823
9824module_param(mmu_enable, uint, 0664);
9825MODULE_PARM_DESC(mmu_enable, "\n mmu_enable\n");
9826
9827module_param(force_enable_mmu, uint, 0664);
9828MODULE_PARM_DESC(force_enable_mmu, "\n force_enable_mmu\n");
9829
9830module_param(again_threshold, uint, 0664);
9831MODULE_PARM_DESC(again_threshold, "\n again_threshold\n");
9832
9833module_param(stream_mode_start_num, uint, 0664);
9834MODULE_PARM_DESC(stream_mode_start_num, "\n stream_mode_start_num\n");
9835
9836/*
9837module_param(trigger_task, uint, 0664);
9838MODULE_PARM_DESC(trigger_task, "\n amvdec_h264 trigger_task\n");
9839*/
9840module_param_array(decode_frame_count, uint, &max_decode_instance_num, 0664);
9841
9842module_param_array(display_frame_count, uint, &max_decode_instance_num, 0664);
9843
9844module_param_array(max_process_time, uint, &max_decode_instance_num, 0664);
9845
9846module_param_array(run_count, uint,
9847 &max_decode_instance_num, 0664);
9848
9849module_param_array(not_run_ready, uint,
9850 &max_decode_instance_num, 0664);
9851
9852module_param_array(input_empty, uint,
9853 &max_decode_instance_num, 0664);
9854
9855module_param_array(max_get_frame_interval, uint,
9856 &max_decode_instance_num, 0664);
9857
9858module_param_array(step, uint, &max_decode_instance_num, 0664);
9859
9860module_param_array(ref_frame_mark_flag, uint, &max_decode_instance_num, 0664);
9861
9862module_param(disp_vframe_valve_level, uint, 0664);
9863MODULE_PARM_DESC(disp_vframe_valve_level, "\n disp_vframe_valve_level\n");
9864
9865module_param(double_write_mode, uint, 0664);
9866MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n");
9867
9868module_param(mem_map_mode, uint, 0664);
9869MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n");
9870
9871module_param(without_display_mode, uint, 0664);
9872MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n");
9873
9874module_param(check_slice_num, uint, 0664);
9875MODULE_PARM_DESC(check_slice_num, "\n check_slice_num\n");
9876
9877module_param(mb_count_threshold, uint, 0664);
9878MODULE_PARM_DESC(mb_count_threshold, "\n mb_count_threshold\n");
9879
9880module_init(ammvdec_h264_driver_init_module);
9881module_exit(ammvdec_h264_driver_remove_module);
9882
9883MODULE_DESCRIPTION("AMLOGIC H264 Video Decoder Driver");
9884MODULE_LICENSE("GPL");
9885
generated by cgit at 2024-05-19 18:48:42 (GMT)