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path: root/drivers/frame_provider/decoder/h264_multi/vmh264.c (plain)
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1/*
2 * drivers/amlogic/amports/vh264.c
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17#define DEBUG
18#include <linux/kernel.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/interrupt.h>
22#include <linux/timer.h>
23#include <linux/kfifo.h>
24#include <linux/platform_device.h>
25#include <linux/random.h>
26
27#include <linux/amlogic/media/utils/amstream.h>
28#include <linux/amlogic/media/frame_sync/ptsserv.h>
29#include <linux/amlogic/media/canvas/canvas.h>
30#include <linux/amlogic/media/vfm/vframe.h>
31#include <linux/amlogic/media/vfm/vframe_provider.h>
32#include <linux/amlogic/media/vfm/vframe_receiver.h>
33#include <linux/amlogic/media/utils/vformat.h>
34#include <linux/amlogic/media/frame_sync/tsync.h>
35#include <linux/workqueue.h>
36#include <linux/dma-mapping.h>
37#include <linux/atomic.h>
38#include <linux/module.h>
39#include <linux/slab.h>
40#include <linux/dma-mapping.h>
41#include <linux/dma-contiguous.h>
42#include "../../../stream_input/amports/amports_priv.h"
43#include <linux/amlogic/media/codec_mm/codec_mm.h>
44
45#include "../utils/vdec_input.h"
46#include <linux/amlogic/tee.h>
47
48#include <linux/amlogic/media/utils/vdec_reg.h>
49#include "../utils/vdec.h"
50#include "../utils/amvdec.h"
51#include "../h264/vh264.h"
52#include "../../../stream_input/parser/streambuf.h"
53#include <linux/delay.h>
54#include <linux/amlogic/media/codec_mm/configs.h>
55#include "../utils/decoder_mmu_box.h"
56#include "../utils/decoder_bmmu_box.h"
57#include "../utils/firmware.h"
58#include <linux/amlogic/tee.h>
59#include <linux/uaccess.h>
60#include "../utils/config_parser.h"
61#include "../../../common/chips/decoder_cpu_ver_info.h"
62#include "../utils/vdec_v4l2_buffer_ops.h"
63#include <linux/crc32.h>
64#include <media/v4l2-mem2mem.h>
65
66#undef pr_info
67#define pr_info printk
68#define VDEC_DW
69#define DEBUG_UCODE
70#define MEM_NAME "codec_m264"
71#define MULTI_INSTANCE_FRAMEWORK
72/* #define ONE_COLOCATE_BUF_PER_DECODE_BUF */
73#include "h264_dpb.h"
74/* #define SEND_PARAM_WITH_REG */
75
76#define DRIVER_NAME "ammvdec_h264"
77#define MODULE_NAME "ammvdec_h264"
78#define DRIVER_HEADER_NAME "ammvdec_h264_header"
79
80#define CHECK_INTERVAL (HZ/100)
81
82#define SEI_DATA_SIZE (8*1024)
83#define SEI_ITU_DATA_SIZE (4*1024)
84
85#define RATE_MEASURE_NUM 8
86#define RATE_CORRECTION_THRESHOLD 5
87#define RATE_2397_FPS 4004 /* 23.97 */
88#define RATE_25_FPS 3840 /* 25 */
89#define RATE_2997_FPS 3203 /* 29.97 */
90#define DUR2PTS(x) ((x)*90/96)
91#define PTS2DUR(x) ((x)*96/90)
92#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96)
93#define FIX_FRAME_RATE_CHECK_IFRAME_NUM 2
94
95#define FIX_FRAME_RATE_OFF 0
96#define FIX_FRAME_RATE_ON 1
97#define FIX_FRAME_RATE_SMOOTH_CHECKING 2
98
99#define DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE 0x0001
100#define DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE 0x0002
101#define DEC_CONTROL_FLAG_FORCE_RATE_2397_FPS_FIX_FRAME_RATE 0x0010
102#define DEC_CONTROL_FLAG_FORCE_RATE_2997_FPS_FIX_FRAME_RATE 0x0020
103
104#define DECODE_ID(hw) (hw_to_vdec(hw)->id)
105
106#define RATE_MEASURE_NUM 8
107#define RATE_CORRECTION_THRESHOLD 5
108#define RATE_24_FPS 4004 /* 23.97 */
109#define RATE_25_FPS 3840 /* 25 */
110#define DUR2PTS(x) ((x)*90/96)
111#define PTS2DUR(x) ((x)*96/90)
112#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96)
113#define FIX_FRAME_RATE_CHECK_IDRFRAME_NUM 2
114
115#define H264_DEV_NUM 9
116
117#define CONSTRAIN_MAX_BUF_NUM
118
119#define H264_MMU
120#define VIDEO_SIGNAL_TYPE_AVAILABLE_MASK 0x20000000
121#define INVALID_IDX -1 /* Invalid buffer index.*/
122
123static int mmu_enable;
124/*mmu do not support mbaff*/
125static int force_enable_mmu = 0;
126unsigned int h264_debug_flag; /* 0xa0000000; */
127unsigned int h264_debug_mask = 0xff;
128 /*
129 *h264_debug_cmd:
130 * 0x1xx, force decoder id of xx to be disconnected
131 */
132unsigned int h264_debug_cmd;
133
134static unsigned int dec_control =
135 DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE |
136 DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE;
137
138static unsigned int force_rate_streambase;
139static unsigned int force_rate_framebase;
140static unsigned int force_disp_bufspec_num;
141static unsigned int fixed_frame_rate_mode;
142static unsigned int error_recovery_mode_in;
143static int start_decode_buf_level = 0x4000;
144static int pre_decode_buf_level = 0x1000;
145static int stream_mode_start_num = 4;
146
147#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
148/*to make reorder size difference of bl and el not too big*/
149static unsigned int reorder_dpb_size_margin_dv = 16;
150#endif
151static unsigned int reorder_dpb_size_margin = 6;
152static unsigned int reference_buf_margin = 4;
153
154#ifdef CONSTRAIN_MAX_BUF_NUM
155static u32 run_ready_max_vf_only_num;
156static u32 run_ready_display_q_num;
157 /*0: not check
158 0xff: mDPB.size
159 */
160static u32 run_ready_max_buf_num = 0xff;
161#endif
162
163static u32 run_ready_min_buf_num = 2;
164
165#define VDEC_ASSIST_CANVAS_BLK32 0x5
166
167
168static unsigned int max_alloc_buf_count;
169static unsigned int decode_timeout_val = 100;
170static unsigned int errordata_timeout_val = 50;
171static unsigned int get_data_timeout_val = 2000;
172#if 1
173/* H264_DATA_REQUEST does not work, disable it,
174decode has error for data in none continuous address
175*/
176static unsigned int frame_max_data_packet;
177#else
178static unsigned int frame_max_data_packet = 8;
179#endif
180static unsigned int radr;
181static unsigned int rval;
182static u32 endian = 0xff0;
183
184/*
185 udebug_flag:
186 bit 0, enable ucode print
187 bit 1, enable ucode detail print
188 bit 3, disable ucode watchdog
189 bit [31:16] not 0, pos to dump lmem
190 bit 2, pop bits to lmem
191 bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
192*/
193static u32 udebug_flag;
194/*
195 when udebug_flag[1:0] is not 0
196 udebug_pause_pos not 0,
197 pause position
198*/
199static u32 udebug_pause_pos;
200/*
201 when udebug_flag[1:0] is not 0
202 and udebug_pause_pos is not 0,
203 pause only when DEBUG_REG2 is equal to this val
204*/
205static u32 udebug_pause_val;
206
207static u32 udebug_pause_decode_idx;
208
209static unsigned int disp_vframe_valve_level;
210
211static unsigned int max_decode_instance_num = H264_DEV_NUM;
212static unsigned int decode_frame_count[H264_DEV_NUM];
213static unsigned int display_frame_count[H264_DEV_NUM];
214static unsigned int max_process_time[H264_DEV_NUM];
215static unsigned int max_get_frame_interval[H264_DEV_NUM];
216static unsigned int run_count[H264_DEV_NUM];
217static unsigned int input_empty[H264_DEV_NUM];
218static unsigned int not_run_ready[H264_DEV_NUM];
219static unsigned int ref_frame_mark_flag[H264_DEV_NUM] =
220{1, 1, 1, 1, 1, 1, 1, 1, 1};
221
222#define VDEC_CLOCK_ADJUST_FRAME 30
223static unsigned int clk_adj_frame_count;
224
225/*
226 *bit[3:0]: 0, run ; 1, pause; 3, step
227 *bit[4]: 1, schedule run
228 */
229static unsigned int step[H264_DEV_NUM];
230
231#define AUX_BUF_ALIGN(adr) ((adr + 0xf) & (~0xf))
232static u32 prefix_aux_buf_size = (16 * 1024);
233static u32 suffix_aux_buf_size;
234
235#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
236static u32 dv_toggle_prov_name;
237
238static u32 dolby_meta_with_el;
239#endif
240
241/*
242 bit[8]
243 0: use sys_info[bit 3]
244 not 0:use i_only_flag[7:0]
245 bit[7:0]:
246 bit 0, 1: only display I picture;
247 bit 1, 1: only decode I picture;
248*/
249static unsigned int i_only_flag;
250
251/*
252 error_proc_policy:
253 bit[0] send_error_frame_flag;
254 (valid when bit[31] is 1, otherwise use sysinfo)
255 bit[1] do not decode if config_decode_buf() fail
256 bit[2] force release buf if in deadlock
257 bit[3] force sliding window ref_frames_in_buffer > num_ref_frames
258 bit[4] check inactive of receiver
259 bit[5] reset buffmgr if in deadlock
260 bit[6] reset buffmgr if bufspec, collocate buf, pic alloc fail
261 bit[7] reset buffmgr if dpb error
262
263 bit[8] check total mbx/mby of decoded frame
264 bit[9] check ERROR_STATUS_REG
265 bit[10] check reference list
266 bit[11] mark error if dpb error
267 bit[12] i_only when error happen
268 bit[13] 0: mark error according to last pic, 1: ignore mark error
269 bit[14] 0: result done when timeout from ucode. 1: reset bufmgr when timeout.
270*/
271static unsigned int error_proc_policy = 0x4fb6; /*0x1f14*/
272
273
274/*
275 error_skip_count:
276 bit[11:0] error skip frame count
277 bit[15:12] error skip i picture count
278*/
279static unsigned int error_skip_count = (0x2 << 12) | 0x40;
280
281static unsigned int force_sliding_margin;
282/*
283 bit[1:0]:
284 0, start playing from any frame
285 1, start playing from I frame
286 bit[15:8]: the count of skip frames after first I
287 2, start playing from second I frame (decode from the first I)
288 bit[15:8]: the max count of skip frames after first I
289 3, start playing from IDR
290*/
291static unsigned int first_i_policy = 1;
292
293/*
294 fast_output_enable:
295 bit [0], output frame if there is IDR in list
296 bit [1], output frame if the current poc is 1 big than the previous poc
297 bit [2], if even poc only, output frame ifthe cuurent poc
298 is 2 big than the previous poc
299 bit [3], ip only
300*/
301static unsigned int fast_output_enable = H264_OUTPUT_MODE_NORMAL;
302
303static unsigned int enable_itu_t35 = 1;
304
305static unsigned int frmbase_cont_bitlevel = 0x40;
306
307static unsigned int frmbase_cont_bitlevel2 = 0x1;
308
309
310#define MH264_USERDATA_ENABLE
311
312/* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */
313/* hevc->double_write_mode:
314 0, no double write
315 1, 1:1 ratio
316 2, (1/4):(1/4) ratio
317 3, (1/4):(1/4) ratio, with both compressed frame included
318 4, (1/2):(1/2) ratio
319 0x10, double write only
320 0x10000: vdec dw horizotal 1/2
321 0x20000: vdec dw horizotal/vertical 1/2
322*/
323static u32 double_write_mode;
324static u32 without_display_mode;
325#define IS_VDEC_DW(hw) (hw->double_write_mode >> 16 & 0xf)
326
327static void vmh264_dump_state(struct vdec_s *vdec);
328
329#define is_in_parsing_state(status) \
330 ((status == H264_ACTION_SEARCH_HEAD) || \
331 ((status & 0xf0) == 0x80))
332
333#define is_interlace(frame) \
334 (frame->frame &&\
335 frame->top_field &&\
336 frame->bottom_field &&\
337 (!frame->frame->coded_frame))
338static inline bool close_to(int a, int b, int m)
339{
340 return (abs(a - b) < m) ? true : false;
341}
342
343#if 0
344#define h264_alloc_hw_stru(dev, size, opt) devm_kzalloc(dev, size, opt)
345#define h264_free_hw_stru(dev, hw) devm_kfree(dev, hw)
346#else
347#define h264_alloc_hw_stru(dev, size, opt) vzalloc(size)
348#define h264_free_hw_stru(dev, hw) vfree(hw)
349#endif
350
351/* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
352#define NV21
353/* #endif */
354
355/* 12M for L41 */
356#define MAX_DPB_BUFF_SIZE (12*1024*1024)
357#define DEFAULT_MEM_SIZE (32*1024*1024)
358#define AVIL_DPB_BUFF_SIZE 0x01ec2000
359
360#define DEF_BUF_START_ADDR 0x01000000
361#define mem_sps_base 0x011c3c00
362#define mem_pps_base 0x011cbc00
363/*#define V_BUF_ADDR_OFFSET (0x13e000)*/
364u32 V_BUF_ADDR_OFFSET = 0x200000;
365#define DCAC_READ_MARGIN (64 * 1024)
366
367
368#define EXTEND_SAR 0xff
369#define BUFSPEC_POOL_SIZE 64
370#define VF_POOL_SIZE 64
371#define VF_POOL_NUM 2
372#define MAX_VF_BUF_NUM 27
373#define BMMU_MAX_BUFFERS (BUFSPEC_POOL_SIZE + 3)
374#define BMMU_REF_IDX (BUFSPEC_POOL_SIZE)
375#define BMMU_DPB_IDX (BUFSPEC_POOL_SIZE + 1)
376#define BMMU_EXTIF_IDX (BUFSPEC_POOL_SIZE + 2)
377#define EXTIF_BUF_SIZE (0x10000 * 2)
378
379#define HEADER_BUFFER_IDX(n) (n)
380#define VF_BUFFER_IDX(n) (n)
381
382
383#define PUT_INTERVAL (HZ/100)
384#define NO_DISP_WD_COUNT (3 * HZ / PUT_INTERVAL)
385
386#define MMU_MAX_BUFFERS BUFSPEC_POOL_SIZE
387#define SWITCHING_STATE_OFF 0
388#define SWITCHING_STATE_ON_CMD3 1
389#define SWITCHING_STATE_ON_CMD1 2
390
391
392
393#define INCPTR(p) ptr_atomic_wrap_inc(&p)
394
395#define SLICE_TYPE_I 2
396#define SLICE_TYPE_P 5
397#define SLICE_TYPE_B 6
398
399struct buffer_spec_s {
400 /*
401 used:
402 -1, none allocated
403 0, allocated, free
404 1, used by dpb
405 2, in disp queue;
406 3, in disp queue, isolated,
407 do not use for dpb when vf_put;
408 4, to release
409 5, in disp queue, isolated (but not to release)
410 do not use for dpb when vf_put;
411 */
412 unsigned int used;
413 unsigned int info0;
414 unsigned int info1;
415 unsigned int info2;
416 unsigned int y_addr;
417 unsigned int u_addr;
418 unsigned int v_addr;
419
420 int y_canvas_index;
421 int u_canvas_index;
422 int v_canvas_index;
423
424#ifdef VDEC_DW
425 unsigned int vdec_dw_y_addr;
426 unsigned int vdec_dw_u_addr;
427 unsigned int vdec_dw_v_addr;
428
429 int vdec_dw_y_canvas_index;
430 int vdec_dw_u_canvas_index;
431 int vdec_dw_v_canvas_index;
432#ifdef NV21
433 struct canvas_config_s vdec_dw_canvas_config[2];
434#else
435 struct canvas_config_s vdec_dw_canvas_config[3];
436#endif
437#endif
438
439#ifdef NV21
440 struct canvas_config_s canvas_config[2];
441#else
442 struct canvas_config_s canvas_config[3];
443#endif
444 unsigned long cma_alloc_addr;
445 unsigned int buf_adr;
446#ifdef H264_MMU
447 unsigned long alloc_header_addr;
448#endif
449 char *aux_data_buf;
450 int aux_data_size;
451#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
452 unsigned char dv_enhance_exist;
453#endif
454 int canvas_pos;
455 int vf_ref;
456 /*unsigned int comp_body_size;*/
457 unsigned int dw_y_adr;
458 unsigned int dw_u_v_adr;
459};
460
461#define AUX_DATA_SIZE(pic) (hw->buffer_spec[pic->buf_spec_num].aux_data_size)
462#define AUX_DATA_BUF(pic) (hw->buffer_spec[pic->buf_spec_num].aux_data_buf)
463#define DEL_EXIST(h, p) (h->buffer_spec[p->buf_spec_num].dv_enhance_exist)
464
465
466#define vdec_dw_spec2canvas(x) \
467 (((x)->vdec_dw_v_canvas_index << 16) | \
468 ((x)->vdec_dw_u_canvas_index << 8) | \
469 ((x)->vdec_dw_y_canvas_index << 0))
470
471
472#define spec2canvas(x) \
473 (((x)->v_canvas_index << 16) | \
474 ((x)->u_canvas_index << 8) | \
475 ((x)->y_canvas_index << 0))
476
477#define FRAME_INDEX(vf_index) (vf_index & 0xff)
478#define BUFSPEC_INDEX(vf_index) ((vf_index >> 8) & 0xff)
479#define VF_INDEX(frm_idx, bufspec_idx) (frm_idx | (bufspec_idx << 8))
480
481static struct vframe_s *vh264_vf_peek(void *);
482static struct vframe_s *vh264_vf_get(void *);
483static void vh264_vf_put(struct vframe_s *, void *);
484static int vh264_vf_states(struct vframe_states *states, void *);
485static int vh264_event_cb(int type, void *data, void *private_data);
486static void vh264_work(struct work_struct *work);
487static void vh264_timeout_work(struct work_struct *work);
488static void vh264_notify_work(struct work_struct *work);
489#ifdef MH264_USERDATA_ENABLE
490static void user_data_ready_notify_work(struct work_struct *work);
491static void vmh264_wakeup_userdata_poll(struct vdec_s *vdec);
492#endif
493
494static const char vh264_dec_id[] = "vh264-dev";
495
496#define PROVIDER_NAME "vdec.h264"
497
498static const struct vframe_operations_s vf_provider_ops = {
499 .peek = vh264_vf_peek,
500 .get = vh264_vf_get,
501 .put = vh264_vf_put,
502 .event_cb = vh264_event_cb,
503 .vf_states = vh264_vf_states,
504};
505
506#define DEC_RESULT_NONE 0
507#define DEC_RESULT_DONE 1
508#define DEC_RESULT_AGAIN 2
509#define DEC_RESULT_CONFIG_PARAM 3
510#define DEC_RESULT_GET_DATA 4
511#define DEC_RESULT_GET_DATA_RETRY 5
512#define DEC_RESULT_ERROR 6
513#define DEC_RESULT_EOS 7
514#define DEC_RESULT_FORCE_EXIT 8
515
516/*
517 *static const char *dec_result_str[] = {
518 * "DEC_RESULT_NONE ",
519 * "DEC_RESULT_DONE ",
520 * "DEC_RESULT_AGAIN ",
521 * "DEC_RESULT_CONFIG_PARAM",
522 * "DEC_RESULT_GET_DATA ",
523 * "DEC_RESULT_GET_DA_RETRY",
524 * "DEC_RESULT_ERROR ",
525 *};
526 */
527
528#define UCODE_IP_ONLY 2
529#define UCODE_IP_ONLY_PARAM 1
530
531#define MC_OFFSET_HEADER 0x0000
532#define MC_OFFSET_DATA 0x1000
533#define MC_OFFSET_MMCO 0x2000
534#define MC_OFFSET_LIST 0x3000
535#define MC_OFFSET_SLICE 0x4000
536#define MC_OFFSET_MAIN 0x5000
537
538#define MC_TOTAL_SIZE ((20+16)*SZ_1K)
539#define MC_SWAP_SIZE (4*SZ_1K)
540#define MODE_ERROR 0
541#define MODE_FULL 1
542
543#define DFS_HIGH_THEASHOLD 3
544
545#define INIT_FLAG_REG AV_SCRATCH_2
546#define HEAD_PADING_REG AV_SCRATCH_3
547#define UCODE_WATCHDOG_REG AV_SCRATCH_7
548#define LMEM_DUMP_ADR AV_SCRATCH_L
549#define DEBUG_REG1 AV_SCRATCH_M
550#define DEBUG_REG2 AV_SCRATCH_N
551#define FRAME_COUNTER_REG AV_SCRATCH_I
552#define RPM_CMD_REG AV_SCRATCH_A
553#define H264_DECODE_SIZE AV_SCRATCH_E
554#define H264_DECODE_MODE AV_SCRATCH_4
555#define H264_DECODE_SEQINFO AV_SCRATCH_5
556#define H264_AUX_ADR AV_SCRATCH_C
557#define H264_AUX_DATA_SIZE AV_SCRATCH_H
558
559#define H264_DECODE_INFO M4_CONTROL_REG /* 0xc29 */
560#define DPB_STATUS_REG AV_SCRATCH_J
561#define ERROR_STATUS_REG AV_SCRATCH_9
562 /*
563 NAL_SEARCH_CTL: bit 0, enable itu_t35
564 NAL_SEARCH_CTL: bit 1, enable mmu
565 */
566#define NAL_SEARCH_CTL AV_SCRATCH_9
567#define MBY_MBX MB_MOTION_MODE /*0xc07*/
568
569#define DECODE_MODE_SINGLE 0x0
570#define DECODE_MODE_MULTI_FRAMEBASE 0x1
571#define DECODE_MODE_MULTI_STREAMBASE 0x2
572#define DECODE_MODE_MULTI_DVBAL 0x3
573#define DECODE_MODE_MULTI_DVENL 0x4
574static DEFINE_MUTEX(vmh264_mutex);
575
576
577
578#ifdef MH264_USERDATA_ENABLE
579
580struct mh264_userdata_record_t {
581 struct userdata_meta_info_t meta_info;
582 u32 rec_start;
583 u32 rec_len;
584};
585
586struct mh264_ud_record_wait_node_t {
587 struct list_head list;
588 struct mh264_userdata_record_t ud_record;
589};
590#define USERDATA_FIFO_NUM 256
591#define MAX_FREE_USERDATA_NODES 5
592
593struct mh264_userdata_info_t {
594 struct mh264_userdata_record_t records[USERDATA_FIFO_NUM];
595 u8 *data_buf;
596 u8 *data_buf_end;
597 u32 buf_len;
598 u32 read_index;
599 u32 write_index;
600 u32 last_wp;
601};
602
603
604#endif
605
606struct vdec_h264_hw_s {
607 spinlock_t lock;
608 spinlock_t bufspec_lock;
609 int id;
610 struct platform_device *platform_dev;
611 unsigned long cma_alloc_addr;
612 /* struct page *collocate_cma_alloc_pages; */
613 unsigned long collocate_cma_alloc_addr;
614
615 u32 prefix_aux_size;
616 u32 suffix_aux_size;
617 void *aux_addr;
618 dma_addr_t aux_phy_addr;
619
620 /* buffer for store all sei data */
621 void *sei_data_buf;
622 u32 sei_data_len;
623
624 /* buffer for storing one itu35 recored */
625 void *sei_itu_data_buf;
626 u32 sei_itu_data_len;
627
628 /* recycle buffer for user data storing all itu35 records */
629 void *sei_user_data_buffer;
630 u32 sei_user_data_wp;
631#ifdef MH264_USERDATA_ENABLE
632 struct work_struct user_data_ready_work;
633#endif
634 struct StorablePicture *last_dec_picture;
635
636 ulong lmem_addr;
637 dma_addr_t lmem_addr_remap;
638
639 void *bmmu_box;
640#ifdef H264_MMU
641 void *mmu_box;
642 void *frame_mmu_map_addr;
643 dma_addr_t frame_mmu_map_phy_addr;
644 u32 hevc_cur_buf_idx;
645 u32 losless_comp_body_size;
646 u32 losless_comp_body_size_sao;
647 u32 losless_comp_header_size;
648 u32 mc_buffer_size_u_v;
649 u32 mc_buffer_size_u_v_h;
650 u32 is_idr_frame;
651 u32 is_new_pic;
652 u32 frame_done;
653 u32 frame_busy;
654 unsigned long extif_addr;
655 int double_write_mode;
656 int mmu_enable;
657#endif
658
659 DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
660 DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
661
662 int cur_pool;
663 struct vframe_s vfpool[VF_POOL_NUM][VF_POOL_SIZE];
664 struct buffer_spec_s buffer_spec[BUFSPEC_POOL_SIZE];
665 struct vframe_s switching_fense_vf;
666 struct h264_dpb_stru dpb;
667 u8 init_flag;
668 u8 first_sc_checked;
669 u8 has_i_frame;
670 u8 config_bufmgr_done;
671 u32 max_reference_size;
672 u32 decode_pic_count;
673 u32 reflist_error_count;
674 int start_search_pos;
675 u32 reg_iqidct_control;
676 u32 reg_vcop_ctrl_reg;
677 u32 reg_rv_ai_mb_count;
678 u32 vld_dec_control;
679 struct vframe_s vframe_dummy;
680
681 unsigned char buffer_empty_flag;
682
683 u32 frame_width;
684 u32 frame_height;
685 u32 frame_dur;
686 u32 frame_prog;
687 u32 frame_packing_type;
688
689 struct vframe_chunk_s *chunk;
690
691 u32 stat;
692 unsigned long buf_start;
693 u32 buf_offset;
694 u32 buf_size;
695 /* u32 ucode_map_start; */
696 u32 pts_outside;
697 u32 sync_outside;
698 u32 vh264_ratio;
699 u32 vh264_rotation;
700 u32 use_idr_framerate;
701
702 u32 seq_info;
703 u32 seq_info2;
704 u32 video_signal_from_vui; /*to do .. */
705 u32 timing_info_present_flag;
706 u32 fixed_frame_rate_flag;
707 u32 bitstream_restriction_flag;
708 u32 num_reorder_frames;
709 u32 max_dec_frame_buffering;
710 u32 iframe_count;
711 u32 aspect_ratio_info;
712 u32 num_units_in_tick;
713 u32 time_scale;
714 u32 h264_ar;
715 bool h264_first_valid_pts_ready;
716 u32 h264pts1;
717 u32 h264pts2;
718 u32 pts_duration;
719 u32 h264_pts_count;
720 u32 duration_from_pts_done;
721 u32 pts_unstable;
722 u32 unstable_pts;
723 u32 last_checkout_pts;
724 u32 max_refer_buf;
725
726 s32 vh264_stream_switching_state;
727 struct vframe_s *p_last_vf;
728 u32 last_pts;
729 u32 last_pts_remainder;
730 u32 last_duration;
731 u32 last_mb_width, last_mb_height;
732 bool check_pts_discontinue;
733 bool pts_discontinue;
734 u32 wait_buffer_counter;
735 u32 first_offset;
736 u32 first_pts;
737 u64 first_pts64;
738 bool first_pts_cached;
739 u64 last_pts64;
740#if 0
741 void *sei_data_buffer;
742 dma_addr_t sei_data_buffer_phys;
743#endif
744
745 uint error_recovery_mode;
746 uint mb_total;
747 uint mb_width;
748 uint mb_height;
749
750 uint i_only;
751 int skip_frame_count;
752 bool no_poc_reorder_flag;
753 bool send_error_frame_flag;
754 dma_addr_t mc_dma_handle;
755 void *mc_cpu_addr;
756 int vh264_reset;
757
758 atomic_t vh264_active;
759
760 struct dec_sysinfo vh264_amstream_dec_info;
761
762 int dec_result;
763 struct work_struct work;
764 struct work_struct notify_work;
765 struct work_struct timeout_work;
766 void (*vdec_cb)(struct vdec_s *, void *);
767 void *vdec_cb_arg;
768
769 struct timer_list check_timer;
770
771 /**/
772 unsigned int last_frame_time;
773 u32 vf_pre_count;
774 u32 vf_get_count;
775 u32 vf_put_count;
776
777 /* timeout handle */
778 unsigned long int start_process_time;
779 unsigned int last_mby_mbx;
780 unsigned int last_vld_level;
781 unsigned int decode_timeout_count;
782 unsigned int timeout_num;
783 unsigned int search_dataempty_num;
784 unsigned int decode_timeout_num;
785 unsigned int decode_dataempty_num;
786 unsigned int buffer_empty_recover_num;
787
788 unsigned get_data_count;
789 unsigned get_data_start_time;
790 /**/
791
792 /*log*/
793 unsigned int packet_write_success_count;
794 unsigned int packet_write_EAGAIN_count;
795 unsigned int packet_write_ENOMEM_count;
796 unsigned int packet_write_EFAULT_count;
797 unsigned int total_read_size_pre;
798 unsigned int total_read_size;
799 unsigned int frame_count_pre;
800#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
801 u8 switch_dvlayer_flag;
802 u8 got_valid_nal;
803#endif
804 u8 eos;
805 u8 data_flag;
806 u32 no_error_count;
807 u32 no_error_i_count;
808 /*
809 NODISP_FLAG
810 */
811 u8 dec_flag;
812
813 u32 ucode_pause_pos;
814
815 u8 reset_bufmgr_flag;
816 u32 reset_bufmgr_count;
817 u32 cfg_param1;
818 u32 cfg_param2;
819 u32 cfg_param3;
820 u32 cfg_param4;
821 int valve_count;
822 u8 next_again_flag;
823 u32 pre_parser_wr_ptr;
824 struct firmware_s *fw;
825 struct firmware_s *fw_mmu;
826#ifdef MH264_USERDATA_ENABLE
827 /*user data*/
828 struct mutex userdata_mutex;
829 struct mh264_userdata_info_t userdata_info;
830 struct mh264_userdata_record_t ud_record;
831 int wait_for_udr_send;
832#endif
833 u32 no_mem_count;
834 u32 canvas_mode;
835 bool is_used_v4l;
836 void *v4l2_ctx;
837 bool v4l_params_parsed;
838 wait_queue_head_t wait_q;
839 u32 reg_g_status;
840 struct mutex chunks_mutex;
841 int need_cache_size;
842 u64 sc_start_time;
843 u8 frmbase_cont_flag;
844 struct vframe_qos_s vframe_qos;
845 int frameinfo_enable;
846 bool first_head_check_flag;
847 unsigned int height_aspect_ratio;
848 unsigned int width_aspect_ratio;
849 bool new_iframe_flag;
850 bool ref_err_flush_dpb_flag;
851 unsigned int first_i_policy;
852 u32 reorder_dpb_size_margin;
853};
854
855static u32 again_threshold;
856
857static void timeout_process(struct vdec_h264_hw_s *hw);
858static void dump_bufspec(struct vdec_h264_hw_s *hw,
859 const char *caller);
860static void h264_reconfig(struct vdec_h264_hw_s *hw);
861static void h264_reset_bufmgr(struct vdec_s *vdec);
862static void vh264_local_init(struct vdec_h264_hw_s *hw, bool is_reset);
863static int vh264_hw_ctx_restore(struct vdec_h264_hw_s *hw);
864static int vh264_stop(struct vdec_h264_hw_s *hw);
865static s32 vh264_init(struct vdec_h264_hw_s *hw);
866static void set_frame_info(struct vdec_h264_hw_s *hw, struct vframe_s *vf,
867 u32 index);
868static void release_aux_data(struct vdec_h264_hw_s *hw,
869 int buf_spec_num);
870#ifdef ERROR_HANDLE_TEST
871static void h264_clear_dpb(struct vdec_h264_hw_s *hw);
872#endif
873
874#define H265_PUT_SAO_4K_SET 0x03
875#define H265_ABORT_SAO_4K_SET 0x04
876#define H265_ABORT_SAO_4K_SET_DONE 0x05
877
878#define SYS_COMMAND HEVC_ASSIST_SCRATCH_0
879#define H265_CHECK_AXI_INFO_BASE HEVC_ASSIST_SCRATCH_8
880#define H265_SAO_4K_SET_BASE HEVC_ASSIST_SCRATCH_9
881#define H265_SAO_4K_SET_COUNT HEVC_ASSIST_SCRATCH_A
882#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464
883
884
885#define HEVC_CM_HEADER_START_ADDR 0x3628
886#define HEVC_CM_BODY_START_ADDR 0x3626
887#define HEVC_CM_BODY_LENGTH 0x3627
888#define HEVC_CM_HEADER_LENGTH 0x3629
889#define HEVC_CM_HEADER_OFFSET 0x362b
890#define HEVC_SAO_CTRL9 0x362d
891#define HEVCD_MPP_DECOMP_CTL3 0x34c4
892#define HEVCD_MPP_VDEC_MCR_CTL 0x34c8
893#define HEVC_DBLK_CFGB 0x350b
894#define HEVC_ASSIST_MMU_MAP_ADDR 0x3009
895
896#define H265_DW_NO_SCALE
897#define H265_MEM_MAP_MODE 0 /*0:linear 1:32x32 2:64x32*/
898#define H265_LOSLESS_COMPRESS_MODE
899#define MAX_FRAME_4K_NUM 0x1200
900#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)
901
902/* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */
903static u32 mem_map_mode = H265_MEM_MAP_MODE;
904
905#define MAX_SIZE_8K (8192 * 4608)
906#define MAX_SIZE_4K (4096 * 2304)
907
908static int is_oversize(int w, int h)
909{
910 int max = (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)?
911 MAX_SIZE_8K : MAX_SIZE_4K;
912
913 if (w < 0 || h < 0)
914 return true;
915
916 if (h != 0 && (w > max / h))
917 return true;
918
919 return false;
920}
921
922static void vmh264_udc_fill_vpts(struct vdec_h264_hw_s *hw,
923 int frame_type,
924 u32 vpts,
925 u32 vpts_valid);
926static int compute_losless_comp_body_size(int width,
927 int height, int bit_depth_10);
928static int compute_losless_comp_header_size(int width, int height);
929
930static int hevc_alloc_mmu(struct vdec_h264_hw_s *hw, int pic_idx,
931 int pic_width, int pic_height, u16 bit_depth,
932 unsigned int *mmu_index_adr) {
933 int cur_buf_idx;
934 int bit_depth_10 = (bit_depth != 0x00);
935 int picture_size;
936 u32 cur_mmu_4k_number;
937
938 WRITE_VREG(CURR_CANVAS_CTRL, pic_idx<<24);
939 cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL)&0xff;
940 picture_size = compute_losless_comp_body_size(pic_width,
941 pic_height, bit_depth_10);
942 cur_mmu_4k_number = ((picture_size+(1<<12)-1) >> 12);
943 dpb_print(DECODE_ID(hw),
944 PRINT_FLAG_MMU_DETAIL,
945 "alloc_mmu new_fb_idx %d picture_size %d cur_mmu_4k_number %d\n",
946 cur_buf_idx, picture_size, cur_mmu_4k_number);
947
948 if (cur_mmu_4k_number > MAX_FRAME_4K_NUM) {
949 pr_err("hevc_alloc_mmu cur_mmu_4k_number %d unsupport\n",
950 cur_mmu_4k_number);
951 return -1;
952 }
953
954 return decoder_mmu_box_alloc_idx(
955 hw->mmu_box,
956 cur_buf_idx,
957 cur_mmu_4k_number,
958 mmu_index_adr);
959}
960
961static int compute_losless_comp_body_size(int width,
962 int height, int bit_depth_10)
963{
964 int width_x64;
965 int height_x32;
966 int bsize;
967
968 width_x64 = width + 63;
969 width_x64 >>= 6;
970
971 height_x32 = height + 31;
972 height_x32 >>= 5;
973
974#ifdef H264_MMU
975 bsize = (bit_depth_10 ? 4096 : 3264) * width_x64*height_x32;
976#else
977 bsize = (bit_depth_10 ? 4096 : 3072) * width_x64*height_x32;
978#endif
979 return bsize;
980}
981
982static int compute_losless_comp_header_size(int width, int height)
983{
984 int width_x64;
985 int width_x128;
986 int height_x64;
987 int hsize;
988
989 width_x64 = width + 63;
990 width_x64 >>= 6;
991
992 width_x128 = width + 127;
993 width_x128 >>= 7;
994
995 height_x64 = height + 63;
996 height_x64 >>= 6;
997
998#ifdef H264_MMU
999 hsize = 128*width_x64*height_x64;
1000#else
1001 hsize = 32*width_x128*height_x64;
1002#endif
1003 return hsize;
1004}
1005
1006static int get_double_write_ratio(struct vdec_h264_hw_s *hw)
1007{
1008 int ratio = 1;
1009 int dw_mode = hw->double_write_mode;
1010 if ((dw_mode == 2) ||
1011 (dw_mode == 3))
1012 ratio = 4;
1013 else if (dw_mode == 4)
1014 ratio = 2;
1015 return ratio;
1016}
1017
1018
1019static int get_dw_size(struct vdec_h264_hw_s *hw, u32 *pdw_buffer_size_u_v_h)
1020{
1021 int pic_width, pic_height;
1022 int lcu_size = 16;
1023 int dw_buf_size;
1024 u32 dw_buffer_size_u_v;
1025 u32 dw_buffer_size_u_v_h;
1026 int dw_mode = hw->double_write_mode;
1027
1028 pic_width = hw->frame_width;
1029 pic_height = hw->frame_height;
1030
1031 if (dw_mode) {
1032 int pic_width_dw = pic_width /
1033 get_double_write_ratio(hw);
1034 int pic_height_dw = pic_height /
1035 get_double_write_ratio(hw);
1036
1037 int pic_width_lcu_dw = (pic_width_dw % lcu_size) ?
1038 pic_width_dw / lcu_size + 1 :
1039 pic_width_dw / lcu_size;
1040 int pic_height_lcu_dw = (pic_height_dw % lcu_size) ?
1041 pic_height_dw / lcu_size + 1 :
1042 pic_height_dw / lcu_size;
1043 int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw;
1044
1045
1046 dw_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2;
1047 dw_buffer_size_u_v_h = (dw_buffer_size_u_v + 0xffff) >> 16;
1048 /*64k alignment*/
1049 dw_buf_size = ((dw_buffer_size_u_v_h << 16) * 3);
1050 *pdw_buffer_size_u_v_h = dw_buffer_size_u_v_h;
1051 } else {
1052 *pdw_buffer_size_u_v_h = 0;
1053 dw_buf_size = 0;
1054 }
1055
1056 return dw_buf_size;
1057}
1058
1059
1060static void hevc_mcr_config_canv2axitbl(struct vdec_h264_hw_s *hw, int restore)
1061{
1062 int i, size;
1063 u32 canvas_addr;
1064 unsigned long maddr;
1065 int num_buff = hw->dpb.mDPB.size;
1066 int dw_size = 0;
1067 u32 dw_buffer_size_u_v_h;
1068 u32 blkmode = hw->canvas_mode;
1069 int dw_mode = hw->double_write_mode;
1070
1071 canvas_addr = ANC0_CANVAS_ADDR;
1072 for (i = 0; i < num_buff; i++)
1073 WRITE_VREG((canvas_addr + i), i | (i << 8) | (i << 16));
1074
1075 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x1 << 1) | (0x1 << 2));
1076 size = hw->losless_comp_body_size + hw->losless_comp_header_size;
1077
1078
1079 dw_size = get_dw_size(hw, &dw_buffer_size_u_v_h);
1080 size += dw_size;
1081 if (size > 0)
1082 size += 0x10000;
1083
1084 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1085 "dw_buffer_size_u_v_h = %d, dw_size = 0x%x, size = 0x%x\n",
1086 dw_buffer_size_u_v_h, dw_size, size);
1087
1088 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1089 "body_size = %d, header_size = %d, body_size_sao = %d\n",
1090 hw->losless_comp_body_size,
1091 hw->losless_comp_header_size,
1092 hw->losless_comp_body_size_sao);
1093
1094 for (i = 0; i < num_buff; i++) {
1095 if (!restore) {
1096 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box,
1097 HEADER_BUFFER_IDX(i), size,
1098 DRIVER_HEADER_NAME, &maddr) < 0) {
1099 dpb_print(DECODE_ID(hw), 0,
1100 "%s malloc compress header failed %d\n",
1101 DRIVER_HEADER_NAME, i);
1102 return;
1103 }
1104 } else
1105 maddr = hw->buffer_spec[i].alloc_header_addr;
1106 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, maddr >> 5);
1107 hw->buffer_spec[i].alloc_header_addr = maddr;
1108 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1109 "%s : canvas: %d axiaddr:%x size 0x%x\n",
1110 __func__, i, (u32)maddr, size);
1111
1112 if (dw_mode) {
1113 u32 addr;
1114 int canvas_w;
1115 int canvas_h;
1116
1117 canvas_w = hw->frame_width /
1118 get_double_write_ratio(hw);
1119 canvas_h = hw->frame_height /
1120 get_double_write_ratio(hw);
1121
1122 if (hw->canvas_mode == 0)
1123 canvas_w = ALIGN(canvas_w, 32);
1124 else
1125 canvas_w = ALIGN(canvas_w, 64);
1126 canvas_h = ALIGN(canvas_h, 32);
1127
1128 hw->buffer_spec[i].dw_y_adr =
1129 maddr + hw->losless_comp_header_size;
1130
1131 hw->buffer_spec[i].dw_y_adr =
1132 ((hw->buffer_spec[i].dw_y_adr + 0xffff) >> 16)
1133 << 16;
1134 hw->buffer_spec[i].dw_u_v_adr =
1135 hw->buffer_spec[i].dw_y_adr
1136 + (dw_buffer_size_u_v_h << 16) * 2;
1137
1138
1139 hw->buffer_spec[i].buf_adr
1140 = hw->buffer_spec[i].dw_y_adr;
1141 addr = hw->buffer_spec[i].buf_adr;
1142
1143
1144 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1145 "dw_y_adr = 0x%x, dw_u_v_adr = 0x%x, y_addr = 0x%x, u_addr = 0x%x, v_addr = 0x%x, width = %d, height = %d\n",
1146 hw->buffer_spec[i].dw_y_adr,
1147 hw->buffer_spec[i].dw_u_v_adr,
1148 hw->buffer_spec[i].y_addr,
1149 hw->buffer_spec[i].u_addr,
1150 hw->buffer_spec[i].v_addr,
1151 canvas_w,
1152 canvas_h);
1153
1154 hw->buffer_spec[i].canvas_config[0].phy_addr =
1155 hw->buffer_spec[i].dw_y_adr;
1156 hw->buffer_spec[i].canvas_config[0].width = canvas_w;
1157 hw->buffer_spec[i].canvas_config[0].height = canvas_h;
1158 hw->buffer_spec[i].canvas_config[0].block_mode =
1159 blkmode;
1160 hw->buffer_spec[i].canvas_config[0].endian = 7;
1161
1162 hw->buffer_spec[i].canvas_config[1].phy_addr =
1163 hw->buffer_spec[i].dw_u_v_adr;
1164 hw->buffer_spec[i].canvas_config[1].width = canvas_w;
1165 hw->buffer_spec[i].canvas_config[1].height = canvas_h;
1166 hw->buffer_spec[i].canvas_config[1].block_mode =
1167 blkmode;
1168 hw->buffer_spec[i].canvas_config[1].endian = 7;
1169 }
1170 }
1171 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
1172
1173 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (0 << 8) | (0<<1) | 1);
1174 for (i = 0; i < 32; i++)
1175 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
1176 return;
1177}
1178static void hevc_mcr_config_mc_ref(struct vdec_h264_hw_s *hw)
1179{
1180 u32 i;
1181 u32 ref_canv;
1182 struct Slice *pSlice = &(hw->dpb.mSlice);
1183 /*REFLIST[0]*/
1184 for (i = 0; i < (unsigned int)(pSlice->listXsize[0]); i++) {
1185 struct StorablePicture *ref = pSlice->listX[0][i];
1186 if (ref == NULL)
1187 return;
1188 WRITE_VREG(CURR_CANVAS_CTRL, ref->buf_spec_num<<24);
1189 ref_canv = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1190 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1191 (ref->buf_spec_num & 0x3f) << 8);
1192 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ref_canv);
1193 }
1194 /*REFLIST[1]*/
1195 for (i = 0; i < (unsigned int)(pSlice->listXsize[1]); i++) {
1196 struct StorablePicture *ref = pSlice->listX[1][i];
1197 if (ref == NULL)
1198 return;
1199 WRITE_VREG(CURR_CANVAS_CTRL, ref->buf_spec_num<<24);
1200 ref_canv = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1201 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1202 (ref->buf_spec_num & 0x3f) << 8);
1203 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ref_canv);
1204 }
1205 return;
1206}
1207
1208static void hevc_mcr_config_mcrcc(struct vdec_h264_hw_s *hw)
1209{
1210 u32 rdata32;
1211 u32 rdata32_2;
1212 u32 slice_type;
1213 struct StorablePicture *ref;
1214 struct Slice *pSlice;
1215 slice_type = hw->dpb.mSlice.slice_type;
1216 pSlice = &(hw->dpb.mSlice);
1217 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2);
1218 if (slice_type == I_SLICE) {
1219 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
1220 return;
1221 }
1222 if (slice_type == B_SLICE) {
1223 ref = pSlice->listX[0][0];
1224 if (ref == NULL)
1225 return;
1226 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1227 ((ref->buf_spec_num & 0x3f) << 8));
1228 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1229 rdata32 = rdata32 & 0xffff;
1230 rdata32 = rdata32 | (rdata32 << 16);
1231 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
1232
1233 ref = pSlice->listX[1][0];
1234 if (ref == NULL)
1235 return;
1236 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1237 ((ref->buf_spec_num & 0x3f) << 8));
1238 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1239 rdata32_2 = rdata32_2 & 0xffff;
1240 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
1241 if (rdata32 == rdata32_2) {
1242 ref = pSlice->listX[1][1];
1243 if (ref == NULL)
1244 return;
1245 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1246 ((ref->buf_spec_num & 0x3f) << 8));
1247 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1248 rdata32_2 = rdata32_2 & 0xffff;
1249 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
1250 }
1251 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32_2);
1252 } else { /*P-PIC*/
1253 ref = pSlice->listX[0][0];
1254 if (ref == NULL)
1255 return;
1256 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1257 ((ref->buf_spec_num & 0x3f) << 8));
1258 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1259 rdata32 = rdata32 & 0xffff;
1260 rdata32 = rdata32 | (rdata32 << 16);
1261 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
1262
1263 ref = pSlice->listX[0][1];
1264 if (ref == NULL)
1265 return;
1266 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1267 ((ref->buf_spec_num & 0x3f) << 8));
1268 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1269 rdata32 = rdata32 & 0xffff;
1270 rdata32 = rdata32 | (rdata32 << 16);
1271 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
1272 }
1273 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0);
1274 return;
1275}
1276
1277
1278static void hevc_mcr_sao_global_hw_init(struct vdec_h264_hw_s *hw,
1279 u32 width, u32 height) {
1280 u32 data32;
1281 u32 lcu_x_num, lcu_y_num;
1282 u32 lcu_total;
1283 u32 mc_buffer_size_u_v;
1284 u32 mc_buffer_size_u_v_h;
1285 int dw_mode = hw->double_write_mode;
1286
1287 lcu_x_num = (width + 15) >> 4;
1288 lcu_y_num = (height + 15) >> 4;
1289 lcu_total = lcu_x_num * lcu_y_num;
1290
1291 hw->mc_buffer_size_u_v = mc_buffer_size_u_v = lcu_total*16*16/2;
1292 hw->mc_buffer_size_u_v_h =
1293 mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff)>>16;
1294
1295 hw->losless_comp_body_size = 0;
1296
1297 hw->losless_comp_body_size_sao =
1298 compute_losless_comp_body_size(width, height, 0);
1299 hw->losless_comp_header_size =
1300 compute_losless_comp_header_size(width, height);
1301
1302 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1); /*sw reset ipp10b_top*/
1303 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x0); /*sw reset ipp10b_top*/
1304
1305 /* setup lcu_size = 16*/
1306 WRITE_VREG(HEVCD_IPP_TOP_LCUCONFIG, 16); /*set lcu size = 16*/
1307 /*pic_width/pic_height*/
1308 WRITE_VREG(HEVCD_IPP_TOP_FRMCONFIG,
1309 (height & 0xffff) << 16 | (width & 0xffff));
1310 /* bitdepth_luma = 8*/
1311 /* bitdepth_chroma = 8*/
1312 WRITE_VREG(HEVCD_IPP_BITDEPTH_CONFIG, 0x0);/*set bit-depth 8 */
1313
1314#ifdef H265_LOSLESS_COMPRESS_MODE
1315 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
1316 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0x0);
1317#else
1318 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
1319#endif
1320 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
1321 data32 &= (~0x30);
1322 data32 |= (hw->canvas_mode << 4);
1323 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
1324
1325 WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,
1326 (0x80 << 20) | (0x80 << 10) | (0xff));
1327
1328 WRITE_VREG(HEVCD_MPP_VDEC_MCR_CTL, 0x1 | (0x1 << 4));
1329
1330 /*comfig vdec:h264:mdec to use hevc mcr/mcrcc/decomp*/
1331 WRITE_VREG(MDEC_PIC_DC_MUX_CTRL,
1332 READ_VREG(MDEC_PIC_DC_MUX_CTRL) | 0x1 << 31);
1333 /* ipp_enable*/
1334 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1 << 1);
1335
1336 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
1337 WRITE_VREG(HEVC_DBLK_CFG1, 0x2); // set ctusize==16
1338 WRITE_VREG(HEVC_DBLK_CFG2, ((height & 0xffff)<<16) | (width & 0xffff));
1339 if (dw_mode)
1340 WRITE_VREG(HEVC_DBLK_CFGB, 0x40405703);
1341 else
1342 WRITE_VREG(HEVC_DBLK_CFGB, 0x40405503);
1343 }
1344
1345 data32 = READ_VREG(HEVC_SAO_CTRL0);
1346 data32 &= (~0xf);
1347 data32 |= 0x4;
1348 WRITE_VREG(HEVC_SAO_CTRL0, data32);
1349 WRITE_VREG(HEVC_SAO_PIC_SIZE, (height & 0xffff) << 16 |
1350 (width & 0xffff));
1351 data32 = ((lcu_x_num-1) | (lcu_y_num-1) << 16);
1352
1353 WRITE_VREG(HEVC_SAO_PIC_SIZE_LCU, data32);
1354 data32 = (lcu_x_num | lcu_y_num << 16);
1355 WRITE_VREG(HEVC_SAO_TILE_SIZE_LCU, data32);
1356 data32 = (mc_buffer_size_u_v_h << 16) << 1;
1357 WRITE_VREG(HEVC_SAO_Y_LENGTH, data32);
1358 data32 = (mc_buffer_size_u_v_h << 16);
1359 WRITE_VREG(HEVC_SAO_C_LENGTH, data32);
1360
1361 data32 = READ_VREG(HEVC_SAO_CTRL1);
1362 data32 &= (~0x3000);
1363 data32 &= (~0xff0);
1364 data32 |= endian; /* Big-Endian per 64-bit */
1365
1366 if (hw->mmu_enable && dw_mode)
1367 data32 |= ((hw->canvas_mode << 12));
1368 else
1369 data32 |= ((hw->canvas_mode << 12)|2);
1370
1371 WRITE_VREG(HEVC_SAO_CTRL1, data32);
1372
1373#ifdef H265_DW_NO_SCALE
1374 WRITE_VREG(HEVC_SAO_CTRL5, READ_VREG(HEVC_SAO_CTRL5) & ~(0xff << 16));
1375 if (hw->mmu_enable && dw_mode) {
1376 data32 = READ_VREG(HEVC_SAO_CTRL5);
1377 data32 &= (~(0xff << 16));
1378 if (dw_mode == 2 ||
1379 dw_mode == 3)
1380 data32 |= (0xff<<16);
1381 else if (dw_mode == 4)
1382 data32 |= (0x33<<16);
1383 WRITE_VREG(HEVC_SAO_CTRL5, data32);
1384 }
1385
1386
1387#endif
1388
1389
1390#ifdef H265_LOSLESS_COMPRESS_MODE
1391 data32 = READ_VREG(HEVC_SAO_CTRL5);
1392 data32 |= (1<<9); /*8-bit smem-mode*/
1393 WRITE_VREG(HEVC_SAO_CTRL5, data32);
1394
1395 WRITE_VREG(HEVC_CM_BODY_LENGTH, hw->losless_comp_body_size_sao);
1396 WRITE_VREG(HEVC_CM_HEADER_OFFSET, hw->losless_comp_body_size);
1397 WRITE_VREG(HEVC_CM_HEADER_LENGTH, hw->losless_comp_header_size);
1398#endif
1399
1400#ifdef H265_LOSLESS_COMPRESS_MODE
1401 WRITE_VREG(HEVC_SAO_CTRL9, READ_VREG(HEVC_SAO_CTRL9) | (0x1 << 1));
1402 WRITE_VREG(HEVC_SAO_CTRL5, READ_VREG(HEVC_SAO_CTRL5) | (0x1 << 10));
1403#endif
1404
1405 WRITE_VREG(HEVC_SAO_CTRL9, READ_VREG(HEVC_SAO_CTRL9) | 0x1 << 7);
1406
1407 memset(hw->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE);
1408
1409 WRITE_VREG(MDEC_EXTIF_CFG0, hw->extif_addr);
1410 WRITE_VREG(MDEC_EXTIF_CFG1, 0x80000000);
1411 return;
1412}
1413
1414static void hevc_sao_set_slice_type(struct vdec_h264_hw_s *hw,
1415 u32 is_new_pic, u32 is_idr)
1416{
1417 hw->is_new_pic = is_new_pic;
1418 hw->is_idr_frame = is_idr;
1419 return;
1420}
1421
1422static void hevc_sao_set_pic_buffer(struct vdec_h264_hw_s *hw,
1423 struct StorablePicture *pic) {
1424 u32 mc_y_adr;
1425 u32 mc_u_v_adr;
1426 u32 dw_y_adr;
1427 u32 dw_u_v_adr;
1428 u32 canvas_addr;
1429 int ret;
1430 int dw_mode = hw->double_write_mode;
1431 if (hw->is_new_pic != 1)
1432 return;
1433
1434 if (hw->is_idr_frame) {
1435 /* William TBD */
1436 memset(hw->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE);
1437 }
1438
1439 WRITE_VREG(CURR_CANVAS_CTRL, pic->buf_spec_num << 24);
1440 canvas_addr = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1441 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x0 << 1) |
1442 (0x0 << 2) | ((canvas_addr & 0xff) << 8));
1443 mc_y_adr = READ_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA) << 5;
1444 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x0 << 1) |
1445 (0x0 << 2) | (((canvas_addr >> 8) & 0xff) << 8));
1446 mc_u_v_adr = READ_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA) << 5;
1447 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
1448
1449
1450 if (dw_mode) {
1451 dw_y_adr = hw->buffer_spec[pic->buf_spec_num].dw_y_adr;
1452 dw_u_v_adr = hw->buffer_spec[pic->buf_spec_num].dw_u_v_adr;
1453 } else {
1454 dw_y_adr = 0;
1455 dw_u_v_adr = 0;
1456 }
1457#ifdef H265_LOSLESS_COMPRESS_MODE
1458 if (dw_mode)
1459 WRITE_VREG(HEVC_SAO_Y_START_ADDR, dw_y_adr);
1460 WRITE_VREG(HEVC_CM_BODY_START_ADDR, mc_y_adr);
1461#ifdef H264_MMU
1462 WRITE_VREG(HEVC_CM_HEADER_START_ADDR, mc_y_adr);
1463#else
1464 WRITE_VREG(HEVC_CM_HEADER_START_ADDR,
1465 (mc_y_adr + hw->losless_comp_body_size));
1466#endif
1467#else
1468 WRITE_VREG(HEVC_SAO_Y_START_ADDR, mc_y_adr);
1469#endif
1470
1471#ifndef H265_LOSLESS_COMPRESS_MODE
1472 WRITE_VREG(HEVC_SAO_C_START_ADDR, mc_u_v_adr);
1473#else
1474 if (dw_mode)
1475 WRITE_VREG(HEVC_SAO_C_START_ADDR, dw_u_v_adr);
1476#endif
1477
1478#ifndef LOSLESS_COMPRESS_MODE
1479 if (dw_mode) {
1480 WRITE_VREG(HEVC_SAO_Y_WPTR, mc_y_adr);
1481 WRITE_VREG(HEVC_SAO_C_WPTR, mc_u_v_adr);
1482 }
1483#else
1484 WRITE_VREG(HEVC_SAO_Y_WPTR, dw_y_adr);
1485 WRITE_VREG(HEVC_SAO_C_WPTR, dw_u_v_adr);
1486#endif
1487
1488 ret = hevc_alloc_mmu(hw, pic->buf_spec_num,
1489 (hw->mb_width << 4), (hw->mb_height << 4), 0x0,
1490 hw->frame_mmu_map_addr);
1491 if (ret != 0) {
1492 dpb_print(DECODE_ID(hw),
1493 PRINT_FLAG_MMU_DETAIL, "can't alloc need mmu1,idx %d ret =%d\n",
1494 pic->buf_spec_num,
1495 ret);
1496 return;
1497 }
1498
1499 /*Reset SAO + Enable SAO slice_start*/
1500 if (hw->mmu_enable && get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A)
1501 WRITE_VREG(HEVC_DBLK_CFG0, 0x1); // reset buffer32x4 in lpf for every picture
1502 WRITE_VREG(HEVC_SAO_INT_STATUS,
1503 READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 28);
1504 WRITE_VREG(HEVC_SAO_INT_STATUS,
1505 READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 31);
1506 /*pr_info("hevc_sao_set_pic_buffer:mc_y_adr: %x\n", mc_y_adr);*/
1507 /*Send coommand to hevc-code to supply 4k buffers to sao*/
1508
1509 if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
1510 WRITE_VREG(H265_SAO_4K_SET_BASE, (u32)hw->frame_mmu_map_phy_addr);
1511 WRITE_VREG(H265_SAO_4K_SET_COUNT, MAX_FRAME_4K_NUM);
1512 } else
1513 WRITE_VREG(HEVC_ASSIST_MMU_MAP_ADDR, (u32)hw->frame_mmu_map_phy_addr);
1514 WRITE_VREG(SYS_COMMAND, H265_PUT_SAO_4K_SET);
1515 hw->frame_busy = 1;
1516 return;
1517}
1518
1519
1520static void hevc_set_unused_4k_buff_idx(struct vdec_h264_hw_s *hw,
1521 u32 buf_spec_num) {
1522 WRITE_VREG(CURR_CANVAS_CTRL, buf_spec_num<<24);
1523 hw->hevc_cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL)&0xff;
1524 dpb_print(DECODE_ID(hw),
1525 PRINT_FLAG_MMU_DETAIL, " %s cur_buf_idx %d buf_spec_num %d\n",
1526 __func__, hw->hevc_cur_buf_idx, buf_spec_num);
1527 return;
1528}
1529
1530
1531static void hevc_set_frame_done(struct vdec_h264_hw_s *hw)
1532{
1533 ulong timeout = jiffies + HZ;
1534 dpb_print(DECODE_ID(hw),
1535 PRINT_FLAG_MMU_DETAIL, "hevc_frame_done...set\n");
1536 while ((READ_VREG(HEVC_SAO_INT_STATUS) & 0x1) == 0) {
1537 if (time_after(jiffies, timeout)) {
1538 dpb_print(DECODE_ID(hw),
1539 PRINT_FLAG_MMU_DETAIL, " %s..timeout!\n", __func__);
1540 break;
1541 }
1542 }
1543 timeout = jiffies + HZ;
1544 while (READ_VREG(HEVC_CM_CORE_STATUS) & 0x1) {
1545 if (time_after(jiffies, timeout)) {
1546 dpb_print(DECODE_ID(hw),
1547 PRINT_FLAG_MMU_DETAIL, " %s cm_core..timeout!\n", __func__);
1548 break;
1549 }
1550 }
1551 WRITE_VREG(HEVC_SAO_INT_STATUS, 0x1);
1552 hw->frame_done = 1;
1553 return;
1554}
1555
1556static void release_cur_decoding_buf(struct vdec_h264_hw_s *hw)
1557{
1558 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
1559 if (p_H264_Dpb->mVideo.dec_picture) {
1560 release_picture(p_H264_Dpb,
1561 p_H264_Dpb->mVideo.dec_picture);
1562 p_H264_Dpb->mVideo.dec_picture->data_flag &= ~ERROR_FLAG;
1563 p_H264_Dpb->mVideo.dec_picture = NULL;
1564 if (hw->mmu_enable)
1565 hevc_set_frame_done(hw);
1566 }
1567}
1568
1569static void hevc_sao_wait_done(struct vdec_h264_hw_s *hw)
1570{
1571 ulong timeout = jiffies + HZ;
1572 dpb_print(DECODE_ID(hw),
1573 PRINT_FLAG_MMU_DETAIL, "hevc_sao_wait_done...start\n");
1574 while ((READ_VREG(HEVC_SAO_INT_STATUS) >> 31)) {
1575 if (time_after(jiffies, timeout)) {
1576 dpb_print(DECODE_ID(hw),
1577 PRINT_FLAG_MMU_DETAIL,
1578 "hevc_sao_wait_done...wait timeout!\n");
1579 break;
1580 }
1581 }
1582 timeout = jiffies + HZ;
1583 if ((hw->frame_busy == 1) && (hw->frame_done == 1) ) {
1584 if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
1585 WRITE_VREG(SYS_COMMAND, H265_ABORT_SAO_4K_SET);
1586 while ((READ_VREG(SYS_COMMAND) & 0xff) !=
1587 H265_ABORT_SAO_4K_SET_DONE) {
1588 if (time_after(jiffies, timeout)) {
1589 dpb_print(DECODE_ID(hw),
1590 PRINT_FLAG_MMU_DETAIL,
1591 "wait h265_abort_sao_4k_set_done timeout!\n");
1592 break;
1593 }
1594 }
1595 }
1596 amhevc_stop();
1597 hw->frame_busy = 0;
1598 hw->frame_done = 0;
1599 dpb_print(DECODE_ID(hw),
1600 PRINT_FLAG_MMU_DETAIL,
1601 "sao wait done ,hevc stop!\n");
1602 }
1603 return;
1604}
1605static void buf_spec_init(struct vdec_h264_hw_s *hw)
1606{
1607 int i;
1608 unsigned long flags;
1609 spin_lock_irqsave(&hw->bufspec_lock, flags);
1610
1611 for (i = 0; i < VF_POOL_SIZE; i++) {
1612 struct vframe_s *vf = &hw->vfpool[hw->cur_pool][i];
1613 u32 ref_idx = BUFSPEC_INDEX(vf->index);
1614 if ((vf->index != -1) &&
1615 (hw->buffer_spec[ref_idx].vf_ref == 0) &&
1616 (hw->buffer_spec[ref_idx].used != -1)) {
1617 vf->index = -1;
1618 }
1619 }
1620
1621 hw->cur_pool++;
1622 if (hw->cur_pool >= VF_POOL_NUM)
1623 hw->cur_pool = 0;
1624
1625 for (i = 0; i < VF_POOL_SIZE; i++) {
1626 struct vframe_s *vf = &hw->vfpool[hw->cur_pool][i];
1627 u32 ref_idx = BUFSPEC_INDEX(vf->index);
1628 if ((vf->index != -1) &&
1629 (hw->buffer_spec[ref_idx].vf_ref == 0) &&
1630 (hw->buffer_spec[ref_idx].used != -1)) {
1631 vf->index = -1;
1632 }
1633 }
1634
1635 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
1636 hw->buffer_spec[i].used = -1;
1637 hw->buffer_spec[i].canvas_pos = -1;
1638 }
1639
1640 if (dpb_is_debug(DECODE_ID(hw),
1641 PRINT_FLAG_DUMP_BUFSPEC))
1642 dump_bufspec(hw, __func__);
1643 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
1644}
1645
1646/*is active in buf management */
1647static unsigned char is_buf_spec_in_use(struct vdec_h264_hw_s *hw,
1648 int buf_spec_num)
1649{
1650 unsigned char ret = 0;
1651 if (hw->buffer_spec[buf_spec_num].used == 1 ||
1652 hw->buffer_spec[buf_spec_num].used == 2 ||
1653 hw->buffer_spec[buf_spec_num].used == 3 ||
1654 hw->buffer_spec[buf_spec_num].used == 5)
1655 ret = 1;
1656 return ret;
1657}
1658
1659static unsigned char is_buf_spec_in_disp_q(struct vdec_h264_hw_s *hw,
1660 int buf_spec_num)
1661{
1662 unsigned char ret = 0;
1663 if (hw->buffer_spec[buf_spec_num].used == 2 ||
1664 hw->buffer_spec[buf_spec_num].used == 3 ||
1665 hw->buffer_spec[buf_spec_num].used == 5)
1666 ret = 1;
1667 return ret;
1668}
1669
1670static int alloc_one_buf_spec(struct vdec_h264_hw_s *hw, int i)
1671{
1672 struct vdec_s *vdec = hw_to_vdec(hw);
1673 if (hw->mmu_enable) {
1674 if (hw->buffer_spec[i].alloc_header_addr)
1675 return 0;
1676 else
1677 return -1;
1678 } else {
1679
1680 int buf_size = (hw->mb_total << 8) + (hw->mb_total << 7);
1681 int addr;
1682#ifdef VDEC_DW
1683 int orig_buf_size;
1684 orig_buf_size = buf_size;
1685 if (IS_VDEC_DW(hw) == 1)
1686 buf_size += (hw->mb_total << 7) + (hw->mb_total << 6);
1687 else if (IS_VDEC_DW(hw) == 2)
1688 buf_size += (hw->mb_total << 6) + (hw->mb_total << 5);
1689#endif
1690 if (hw->buffer_spec[i].cma_alloc_addr)
1691 return 0;
1692
1693 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, i,
1694 PAGE_ALIGN(buf_size), DRIVER_NAME,
1695 &hw->buffer_spec[i].cma_alloc_addr) < 0) {
1696 hw->buffer_spec[i].cma_alloc_addr = 0;
1697 if (hw->no_mem_count++ > 3) {
1698 hw->stat |= DECODER_FATAL_ERROR_NO_MEM;
1699 hw->reset_bufmgr_flag = 1;
1700 }
1701 dpb_print(DECODE_ID(hw), 0,
1702 "%s, fail to alloc buf for bufspec%d, try later\n",
1703 __func__, i
1704 );
1705 return -1;
1706 } else {
1707 hw->no_mem_count = 0;
1708 hw->stat &= ~DECODER_FATAL_ERROR_NO_MEM;
1709 }
1710 if (!vdec_secure(vdec)) {
1711 /*init internal buf*/
1712 char *tmpbuf = (char *)codec_mm_phys_to_virt(hw->buffer_spec[i].cma_alloc_addr);
1713 if (tmpbuf) {
1714 memset(tmpbuf, 0, PAGE_ALIGN(buf_size));
1715 codec_mm_dma_flush(tmpbuf,
1716 PAGE_ALIGN(buf_size),
1717 DMA_TO_DEVICE);
1718 } else {
1719 tmpbuf = codec_mm_vmap(hw->buffer_spec[i].cma_alloc_addr, PAGE_ALIGN(buf_size));
1720 if (tmpbuf) {
1721 memset(tmpbuf, 0, PAGE_ALIGN(buf_size));
1722 codec_mm_dma_flush(tmpbuf,
1723 PAGE_ALIGN(buf_size),
1724 DMA_TO_DEVICE);
1725 codec_mm_unmap_phyaddr(tmpbuf);
1726 }
1727 }
1728 }
1729 hw->buffer_spec[i].buf_adr =
1730 hw->buffer_spec[i].cma_alloc_addr;
1731 addr = hw->buffer_spec[i].buf_adr;
1732
1733
1734 hw->buffer_spec[i].y_addr = addr;
1735 addr += hw->mb_total << 8;
1736 hw->buffer_spec[i].u_addr = addr;
1737 hw->buffer_spec[i].v_addr = addr;
1738 addr += hw->mb_total << 7;
1739
1740 hw->buffer_spec[i].canvas_config[0].phy_addr =
1741 hw->buffer_spec[i].y_addr;
1742 hw->buffer_spec[i].canvas_config[0].width =
1743 hw->mb_width << 4;
1744 hw->buffer_spec[i].canvas_config[0].height =
1745 hw->mb_height << 4;
1746 hw->buffer_spec[i].canvas_config[0].block_mode =
1747 hw->canvas_mode;
1748
1749 hw->buffer_spec[i].canvas_config[1].phy_addr =
1750 hw->buffer_spec[i].u_addr;
1751 hw->buffer_spec[i].canvas_config[1].width =
1752 hw->mb_width << 4;
1753 hw->buffer_spec[i].canvas_config[1].height =
1754 hw->mb_height << 3;
1755 hw->buffer_spec[i].canvas_config[1].block_mode =
1756 hw->canvas_mode;
1757 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
1758 "%s, alloc buf for bufspec%d\n",
1759 __func__, i
1760 );
1761#ifdef VDEC_DW
1762
1763 if (!IS_VDEC_DW(hw))
1764 return 0;
1765 else if (IS_VDEC_DW(hw) == 1) {
1766 addr = hw->buffer_spec[i].cma_alloc_addr + orig_buf_size;
1767 hw->buffer_spec[i].vdec_dw_y_addr = addr;
1768 addr += hw->mb_total << 7;
1769 hw->buffer_spec[i].vdec_dw_u_addr = addr;
1770 hw->buffer_spec[i].vdec_dw_v_addr = addr;
1771 addr += hw->mb_total << 6;
1772
1773 hw->buffer_spec[i].vdec_dw_canvas_config[0].phy_addr =
1774 hw->buffer_spec[i].vdec_dw_y_addr;
1775 hw->buffer_spec[i].vdec_dw_canvas_config[0].width =
1776 hw->mb_width << 3;
1777 hw->buffer_spec[i].vdec_dw_canvas_config[0].height =
1778 hw->mb_height << 4;
1779 hw->buffer_spec[i].vdec_dw_canvas_config[0].block_mode =
1780 CANVAS_BLKMODE_32X32;
1781
1782 hw->buffer_spec[i].vdec_dw_canvas_config[1].phy_addr =
1783 hw->buffer_spec[i].vdec_dw_u_addr;
1784 hw->buffer_spec[i].vdec_dw_canvas_config[1].width =
1785 hw->mb_width << 3;
1786 hw->buffer_spec[i].vdec_dw_canvas_config[1].height =
1787 hw->mb_height << 3;
1788 hw->buffer_spec[i].vdec_dw_canvas_config[1].block_mode =
1789 CANVAS_BLKMODE_32X32;
1790 }else {
1791 addr = hw->buffer_spec[i].cma_alloc_addr + orig_buf_size;
1792 hw->buffer_spec[i].vdec_dw_y_addr = addr;
1793 addr += hw->mb_total << 6;
1794 hw->buffer_spec[i].vdec_dw_u_addr = addr;
1795 hw->buffer_spec[i].vdec_dw_v_addr = addr;
1796 addr += hw->mb_total << 5;
1797
1798 hw->buffer_spec[i].vdec_dw_canvas_config[0].phy_addr =
1799 hw->buffer_spec[i].vdec_dw_y_addr;
1800 hw->buffer_spec[i].vdec_dw_canvas_config[0].width =
1801 hw->mb_width << 3;
1802 hw->buffer_spec[i].vdec_dw_canvas_config[0].height =
1803 hw->mb_height << 3;
1804 hw->buffer_spec[i].vdec_dw_canvas_config[0].block_mode =
1805 CANVAS_BLKMODE_32X32;
1806
1807 hw->buffer_spec[i].vdec_dw_canvas_config[1].phy_addr =
1808 hw->buffer_spec[i].vdec_dw_u_addr;
1809 hw->buffer_spec[i].vdec_dw_canvas_config[1].width =
1810 hw->mb_width << 3;
1811 hw->buffer_spec[i].vdec_dw_canvas_config[1].height =
1812 hw->mb_height << 2;
1813 hw->buffer_spec[i].vdec_dw_canvas_config[1].block_mode =
1814 CANVAS_BLKMODE_32X32;
1815 }
1816 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
1817 "%s, vdec_dw: alloc buf for bufspec%d\n",
1818 __func__, i
1819 );
1820#endif
1821 }
1822 return 0;
1823}
1824
1825static int alloc_one_buf_spec_from_queue(struct vdec_h264_hw_s *hw, int idx)
1826{
1827 int ret = 0;
1828 struct aml_vcodec_ctx *ctx = NULL;
1829 struct buffer_spec_s *bs = &hw->buffer_spec[idx];
1830 struct canvas_config_s *y_canvas_cfg = NULL;
1831 struct canvas_config_s *c_canvas_cfg = NULL;
1832 struct vdec_v4l2_buffer *fb = NULL;
1833 unsigned int y_addr = 0, c_addr = 0;
1834
1835 if (IS_ERR_OR_NULL(hw->v4l2_ctx)) {
1836 pr_err("the v4l context has err.\n");
1837 return -1;
1838 }
1839
1840 if (bs->cma_alloc_addr)
1841 return 0;
1842
1843 ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
1844 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1845 "[%d] %s(), try alloc from v4l queue buf size: %d\n",
1846 ctx->id, __func__,
1847 (hw->mb_total << 8) + (hw->mb_total << 7));
1848
1849 ret = vdec_v4l_get_buffer(hw->v4l2_ctx, &fb);
1850 if (ret < 0) {
1851 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1852 "[%d] get fb fail.\n", ctx->id);
1853 return ret;
1854 }
1855
1856 bs->cma_alloc_addr = (unsigned long)fb;
1857 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1858 "[%d] %s(), cma alloc addr: 0x%x\n",
1859 ctx->id, __func__, bs->cma_alloc_addr);
1860
1861 if (fb->num_planes == 1) {
1862 y_addr = fb->m.mem[0].addr;
1863 c_addr = fb->m.mem[0].addr + fb->m.mem[0].offset;
1864 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
1865 } else if (fb->num_planes == 2) {
1866 y_addr = fb->m.mem[0].addr;
1867 c_addr = fb->m.mem[1].addr;
1868 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
1869 fb->m.mem[1].bytes_used = fb->m.mem[1].size;
1870 }
1871
1872 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1873 "[%d] %s(), y_addr: %x, size: %u\n",
1874 ctx->id, __func__, y_addr, fb->m.mem[0].size);
1875 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1876 "[%d] %s(), c_addr: %x, size: %u\n",
1877 ctx->id, __func__, c_addr, fb->m.mem[1].size);
1878
1879 bs->y_addr = y_addr;
1880 bs->u_addr = c_addr;
1881 bs->v_addr = c_addr;
1882
1883 y_canvas_cfg = &bs->canvas_config[0];
1884 c_canvas_cfg = &bs->canvas_config[1];
1885
1886 y_canvas_cfg->phy_addr = y_addr;
1887 y_canvas_cfg->width = hw->mb_width << 4;
1888 y_canvas_cfg->height = hw->mb_height << 4;
1889 y_canvas_cfg->block_mode = hw->canvas_mode;
1890 //fb->m.mem[0].bytes_used = y_canvas_cfg->width * y_canvas_cfg->height;
1891 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1892 "[%d] %s(), y_w: %d, y_h: %d\n", ctx->id, __func__,
1893 y_canvas_cfg->width,y_canvas_cfg->height);
1894
1895 c_canvas_cfg->phy_addr = c_addr;
1896 c_canvas_cfg->width = hw->mb_width << 4;
1897 c_canvas_cfg->height = hw->mb_height << 3;
1898 c_canvas_cfg->block_mode = hw->canvas_mode;
1899 //fb->m.mem[1].bytes_used = c_canvas_cfg->width * c_canvas_cfg->height;
1900 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1901 "[%d] %s(), c_w: %d, c_h: %d\n", ctx->id, __func__,
1902 c_canvas_cfg->width, c_canvas_cfg->height);
1903
1904 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1905 "[%d] %s(), alloc buf for bufspec%d\n", ctx->id, __func__, idx);
1906
1907 return ret;
1908}
1909
1910static void config_decode_canvas(struct vdec_h264_hw_s *hw, int i)
1911{
1912 int blkmode = hw->canvas_mode;
1913 int endian = 0;
1914
1915 if (blkmode == CANVAS_BLKMODE_LINEAR) {
1916 if ((h264_debug_flag & IGNORE_PARAM_FROM_CONFIG) == 0)
1917 endian = 7;
1918 else
1919 endian = 0;
1920 }
1921
1922 if (hw->is_used_v4l)
1923 endian = 7;
1924
1925 canvas_config_ex(hw->buffer_spec[i].
1926 y_canvas_index,
1927 hw->buffer_spec[i].y_addr,
1928 hw->mb_width << 4,
1929 hw->mb_height << 4,
1930 CANVAS_ADDR_NOWRAP,
1931 blkmode,
1932 endian);
1933
1934 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1935 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1936 (1 << 11) | /* canvas_blk32_wr */
1937 (blkmode << 10) | /* canvas_blk32*/
1938 (1 << 8) | /* canvas_index_wr*/
1939 (hw->buffer_spec[i].y_canvas_index << 0) /* canvas index*/
1940 );
1941 }
1942
1943 canvas_config_ex(hw->buffer_spec[i].
1944 u_canvas_index,
1945 hw->buffer_spec[i].u_addr,
1946 hw->mb_width << 4,
1947 hw->mb_height << 3,
1948 CANVAS_ADDR_NOWRAP,
1949 blkmode,
1950 endian);
1951
1952 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1953 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1954 (1 << 11) |
1955 (blkmode << 10) |
1956 (1 << 8) |
1957 (hw->buffer_spec[i].u_canvas_index << 0));
1958 }
1959
1960 WRITE_VREG(ANC0_CANVAS_ADDR + hw->buffer_spec[i].canvas_pos,
1961 spec2canvas(&hw->buffer_spec[i]));
1962
1963
1964#ifdef VDEC_DW
1965 if (!IS_VDEC_DW(hw))
1966 return;
1967 else if (IS_VDEC_DW(hw) == 1) {
1968 canvas_config_ex(hw->buffer_spec[i].
1969 vdec_dw_y_canvas_index,
1970 hw->buffer_spec[i].vdec_dw_y_addr,
1971 hw->mb_width << 3,
1972 hw->mb_height << 4,
1973 CANVAS_ADDR_NOWRAP,
1974 blkmode,
1975 endian);
1976 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1977 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1978 (1 << 11) |
1979 (blkmode << 10) |
1980 (1 << 8) |
1981 (hw->buffer_spec[i].vdec_dw_y_canvas_index << 0));
1982 }
1983 canvas_config_ex(hw->buffer_spec[i].
1984 vdec_dw_u_canvas_index,
1985 hw->buffer_spec[i].vdec_dw_u_addr,
1986 hw->mb_width << 3,
1987 hw->mb_height << 3,
1988 CANVAS_ADDR_NOWRAP,
1989 blkmode,
1990 endian);
1991 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1992 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1993 (1 << 11) |
1994 (blkmode << 10) |
1995 (1 << 8) |
1996 (hw->buffer_spec[i].vdec_dw_u_canvas_index << 0));
1997 }
1998 } else {
1999 canvas_config_ex(hw->buffer_spec[i].
2000 vdec_dw_y_canvas_index,
2001 hw->buffer_spec[i].vdec_dw_y_addr,
2002 hw->mb_width << 3,
2003 hw->mb_height << 3,
2004 CANVAS_ADDR_NOWRAP,
2005 blkmode,
2006 endian);
2007 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
2008 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
2009 (1 << 11) |
2010 (blkmode << 10) |
2011 (1 << 8) |
2012 (hw->buffer_spec[i].vdec_dw_y_canvas_index << 0));
2013 }
2014
2015 canvas_config_ex(hw->buffer_spec[i].
2016 vdec_dw_u_canvas_index,
2017 hw->buffer_spec[i].vdec_dw_u_addr,
2018 hw->mb_width << 3,
2019 hw->mb_height << 2,
2020 CANVAS_ADDR_NOWRAP,
2021 blkmode,
2022 endian);
2023 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
2024 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
2025 (1 << 11) |
2026 (blkmode << 10) |
2027 (1 << 8) |
2028 (hw->buffer_spec[i].vdec_dw_u_canvas_index << 0));
2029 }
2030 }
2031#endif
2032}
2033
2034static void config_decode_canvas_ex(struct vdec_h264_hw_s *hw, int i)
2035{
2036 u32 blkmode = hw->canvas_mode;
2037 int canvas_w;
2038 int canvas_h;
2039
2040 canvas_w = hw->frame_width /
2041 get_double_write_ratio(hw);
2042 canvas_h = hw->frame_height /
2043 get_double_write_ratio(hw);
2044
2045 if (hw->canvas_mode == 0)
2046 canvas_w = ALIGN(canvas_w, 32);
2047 else
2048 canvas_w = ALIGN(canvas_w, 64);
2049 canvas_h = ALIGN(canvas_h, 32);
2050
2051 canvas_config_ex(hw->buffer_spec[i].
2052 y_canvas_index,
2053 hw->buffer_spec[i].dw_y_adr,
2054 canvas_w,
2055 canvas_h,
2056 CANVAS_ADDR_NOWRAP,
2057 blkmode,
2058 7);
2059
2060 canvas_config_ex(hw->buffer_spec[i].
2061 u_canvas_index,
2062 hw->buffer_spec[i].dw_u_v_adr,
2063 canvas_w,
2064 canvas_h,
2065 CANVAS_ADDR_NOWRAP,
2066 blkmode,
2067 7);
2068}
2069
2070static int v4l_get_free_buf_idx(struct vdec_s *vdec)
2071{
2072 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2073 struct aml_vcodec_ctx * v4l = hw->v4l2_ctx;
2074 struct v4l_buff_pool *pool = &v4l->cap_pool;
2075 struct buffer_spec_s *pic = NULL;
2076 int i, idx = INVALID_IDX;
2077 ulong flags;
2078
2079 spin_lock_irqsave(&hw->bufspec_lock, flags);
2080 for (i = 0; i < pool->in; ++i) {
2081 u32 state = (pool->seq[i] >> 16);
2082 u32 index = (pool->seq[i] & 0xffff);
2083
2084 switch (state) {
2085 case V4L_CAP_BUFF_IN_DEC:
2086 pic = &hw->buffer_spec[i];
2087 if ((pic->vf_ref == 0) &&
2088 (pic->used == 0) &&
2089 pic->cma_alloc_addr) {
2090 idx = i;
2091 }
2092 break;
2093 case V4L_CAP_BUFF_IN_M2M:
2094 pic = &hw->buffer_spec[index];
2095 if (!alloc_one_buf_spec_from_queue(hw, index)) {
2096 config_decode_canvas(hw, index);
2097 idx = index;
2098 }
2099 break;
2100 default:
2101 pr_err("v4l buffer state err %d.\n", state);
2102 break;
2103 }
2104
2105 if (idx != INVALID_IDX) {
2106 pic->used = 1;
2107 break;
2108 }
2109 }
2110 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2111
2112 if (idx < 0) {
2113 dpb_print(DECODE_ID(hw), 0, "%s fail\n", __func__);
2114 vmh264_dump_state(vdec);
2115 }
2116
2117 return idx;
2118}
2119
2120int get_free_buf_idx(struct vdec_s *vdec)
2121{
2122 int i;
2123 unsigned long addr, flags;
2124 int index = -1;
2125 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2126 int buf_total = BUFSPEC_POOL_SIZE;
2127
2128 if (hw->is_used_v4l)
2129 return v4l_get_free_buf_idx(vdec);
2130
2131 spin_lock_irqsave(&hw->bufspec_lock, flags);
2132 /*hw->start_search_pos = 0;*/
2133 for (i = hw->start_search_pos; i < buf_total; i++) {
2134 if (hw->mmu_enable)
2135 addr = hw->buffer_spec[i].alloc_header_addr;
2136 else
2137 addr = hw->buffer_spec[i].cma_alloc_addr;
2138
2139 if (hw->buffer_spec[i].vf_ref == 0 &&
2140 hw->buffer_spec[i].used == 0 && addr) {
2141 hw->buffer_spec[i].used = 1;
2142 hw->start_search_pos = i+1;
2143 index = i;
2144 break;
2145 }
2146 }
2147 if (index < 0) {
2148 for (i = 0; i < hw->start_search_pos; i++) {
2149 if (hw->mmu_enable)
2150 addr = hw->buffer_spec[i].alloc_header_addr;
2151 else
2152 addr = hw->buffer_spec[i].cma_alloc_addr;
2153
2154 if (hw->buffer_spec[i].vf_ref == 0 &&
2155 hw->buffer_spec[i].used == 0 && addr) {
2156 hw->buffer_spec[i].used = 1;
2157 hw->start_search_pos = i+1;
2158 index = i;
2159 break;
2160 }
2161 }
2162 }
2163 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2164 if (hw->start_search_pos >= buf_total)
2165 hw->start_search_pos = 0;
2166 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
2167 "%s, buf_spec_num %d\n", __func__, index);
2168
2169 if (index < 0) {
2170 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2171 "%s fail\n", __func__);
2172 vmh264_dump_state(vdec);
2173 }
2174
2175 if (dpb_is_debug(DECODE_ID(hw),
2176 PRINT_FLAG_DUMP_BUFSPEC))
2177 dump_bufspec(hw, __func__);
2178 return index;
2179}
2180
2181int release_buf_spec_num(struct vdec_s *vdec, int buf_spec_num)
2182{
2183 /*u32 cur_buf_idx;*/
2184 unsigned long flags;
2185 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2186 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
2187 "%s buf_spec_num %d used %d\n",
2188 __func__, buf_spec_num,
2189 buf_spec_num > 0 ? hw->buffer_spec[buf_spec_num].used : 0);
2190 if (buf_spec_num >= 0 &&
2191 buf_spec_num < BUFSPEC_POOL_SIZE
2192 ) {
2193 spin_lock_irqsave(&hw->bufspec_lock, flags);
2194 hw->buffer_spec[buf_spec_num].used = 0;
2195 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2196 if (hw->mmu_enable) {
2197 /*WRITE_VREG(CURR_CANVAS_CTRL, buf_spec_num<<24);
2198 cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL);
2199 cur_buf_idx = cur_buf_idx&0xff;*/
2200 decoder_mmu_box_free_idx(hw->mmu_box, buf_spec_num);
2201 }
2202 release_aux_data(hw, buf_spec_num);
2203 }
2204 if (dpb_is_debug(DECODE_ID(hw),
2205 PRINT_FLAG_DUMP_BUFSPEC))
2206 dump_bufspec(hw, __func__);
2207 return 0;
2208}
2209
2210static void config_buf_specs(struct vdec_s *vdec)
2211{
2212 int i, j;
2213 unsigned long flags;
2214 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2215 int mode = IS_VDEC_DW(hw) ? 2 : 1;
2216
2217 spin_lock_irqsave(&hw->bufspec_lock, flags);
2218 for (i = 0, j = 0;
2219 j < hw->dpb.mDPB.size
2220 && i < BUFSPEC_POOL_SIZE;
2221 i++) {
2222 int canvas;
2223 if (hw->buffer_spec[i].used != -1)
2224 continue;
2225 if (vdec->parallel_dec == 1) {
2226 if (hw->buffer_spec[i].y_canvas_index == -1)
2227 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2228 if (hw->buffer_spec[i].u_canvas_index == -1) {
2229 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2230 hw->buffer_spec[i].v_canvas_index = hw->buffer_spec[i].u_canvas_index;
2231 }
2232#ifdef VDEC_DW
2233 if (IS_VDEC_DW(hw)) {
2234 if (hw->buffer_spec[i].vdec_dw_y_canvas_index == -1)
2235 hw->buffer_spec[i].vdec_dw_y_canvas_index =
2236 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2237 if (hw->buffer_spec[i].vdec_dw_u_canvas_index == -1) {
2238 hw->buffer_spec[i].vdec_dw_u_canvas_index =
2239 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2240 hw->buffer_spec[i].vdec_dw_v_canvas_index =
2241 hw->buffer_spec[i].vdec_dw_u_canvas_index;
2242 }
2243 }
2244#endif
2245 } else {
2246 canvas = vdec->get_canvas(j * mode, 2);
2247 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
2248 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
2249 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
2250 dpb_print(DECODE_ID(hw),
2251 PRINT_FLAG_DPB_DETAIL,
2252 "config canvas (%d) %x for bufspec %d\r\n",
2253 j, canvas, i);
2254#ifdef VDEC_DW
2255 if (IS_VDEC_DW(hw)) {
2256 canvas = vdec->get_canvas(j * mode + 1, 2);
2257 hw->buffer_spec[i].vdec_dw_y_canvas_index = canvas_y(canvas);
2258 hw->buffer_spec[i].vdec_dw_u_canvas_index = canvas_u(canvas);
2259 hw->buffer_spec[i].vdec_dw_v_canvas_index = canvas_v(canvas);
2260 dpb_print(DECODE_ID(hw),
2261 PRINT_FLAG_DPB_DETAIL,
2262 "vdec_dw: config canvas (%d) %x for bufspec %d\r\n",
2263 j, canvas, i);
2264 }
2265#endif
2266 }
2267
2268 hw->buffer_spec[i].used = 0;
2269 hw->buffer_spec[i].canvas_pos = j;
2270
2271
2272 j++;
2273 }
2274 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2275}
2276
2277static void config_buf_specs_ex(struct vdec_s *vdec)
2278{
2279 int i, j;
2280 unsigned long flags;
2281 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2282 int mode = IS_VDEC_DW(hw) ? 2 : 1;
2283
2284 spin_lock_irqsave(&hw->bufspec_lock, flags);
2285 for (i = 0, j = 0;
2286 j < hw->dpb.mDPB.size
2287 && i < BUFSPEC_POOL_SIZE;
2288 i++) {
2289 int canvas = 0;
2290 if (hw->buffer_spec[i].used != -1)
2291 continue;
2292 if (vdec->parallel_dec == 1) {
2293 if (hw->buffer_spec[i].y_canvas_index == -1)
2294 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2295 if (hw->buffer_spec[i].u_canvas_index == -1) {
2296 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2297 hw->buffer_spec[i].v_canvas_index = hw->buffer_spec[i].u_canvas_index;
2298 }
2299#ifdef VDEC_DW
2300 if (IS_VDEC_DW(hw)) {
2301 if (hw->buffer_spec[i].vdec_dw_y_canvas_index == -1)
2302 hw->buffer_spec[i].vdec_dw_y_canvas_index =
2303 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2304 if (hw->buffer_spec[i].vdec_dw_u_canvas_index == -1) {
2305 hw->buffer_spec[i].vdec_dw_u_canvas_index =
2306 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2307 hw->buffer_spec[i].vdec_dw_v_canvas_index =
2308 hw->buffer_spec[i].vdec_dw_u_canvas_index;
2309 }
2310 }
2311#endif
2312 } else {
2313 canvas = vdec->get_canvas(j* mode, 2);
2314 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
2315 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
2316 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
2317
2318 dpb_print(DECODE_ID(hw),
2319 PRINT_FLAG_DPB_DETAIL,
2320 "config canvas (%d) %x for bufspec %d\r\n",
2321 j, canvas, i);
2322#ifdef VDEC_DW
2323 if (IS_VDEC_DW(hw)) {
2324 canvas = vdec->get_canvas(j*mode + 1, 2);
2325 hw->buffer_spec[i].vdec_dw_y_canvas_index = canvas_y(canvas);
2326 hw->buffer_spec[i].vdec_dw_u_canvas_index = canvas_u(canvas);
2327 hw->buffer_spec[i].vdec_dw_v_canvas_index = canvas_v(canvas);
2328 dpb_print(DECODE_ID(hw),
2329 PRINT_FLAG_DPB_DETAIL,
2330 "vdec_dw: config canvas (%d) %x for bufspec %d\r\n",
2331 j, canvas, i);
2332 }
2333#endif
2334 }
2335
2336 hw->buffer_spec[i].used = 0;
2337 hw->buffer_spec[i].alloc_header_addr = 0;
2338 hw->buffer_spec[i].canvas_pos = j;
2339
2340 j++;
2341 }
2342 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2343}
2344
2345
2346static void dealloc_buf_specs(struct vdec_h264_hw_s *hw,
2347 unsigned char release_all)
2348{
2349 int i;
2350 unsigned long flags;
2351 unsigned char dealloc_flag = 0;
2352 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2353 if (hw->buffer_spec[i].used == 4 ||
2354 release_all) {
2355 dealloc_flag = 1;
2356 dpb_print(DECODE_ID(hw),
2357 PRINT_FLAG_DPB_DETAIL,
2358 "%s buf_spec_num %d\n",
2359 __func__, i
2360 );
2361 spin_lock_irqsave
2362 (&hw->bufspec_lock, flags);
2363 hw->buffer_spec[i].used = -1;
2364 spin_unlock_irqrestore
2365 (&hw->bufspec_lock, flags);
2366 release_aux_data(hw, i);
2367
2368 if (!hw->mmu_enable) {
2369 if (hw->buffer_spec[i].cma_alloc_addr) {
2370 if (!hw->is_used_v4l) {
2371 decoder_bmmu_box_free_idx(
2372 hw->bmmu_box,
2373 i);
2374 }
2375 spin_lock_irqsave
2376 (&hw->bufspec_lock, flags);
2377 hw->buffer_spec[i].cma_alloc_addr = 0;
2378 hw->buffer_spec[i].buf_adr = 0;
2379 spin_unlock_irqrestore
2380 (&hw->bufspec_lock, flags);
2381 }
2382 } else {
2383 if (hw->buffer_spec[i].alloc_header_addr) {
2384 decoder_mmu_box_free_idx(
2385 hw->mmu_box,
2386 i);
2387 spin_lock_irqsave
2388 (&hw->bufspec_lock, flags);
2389 hw->buffer_spec[i].
2390 alloc_header_addr = 0;
2391 hw->buffer_spec[i].buf_adr = 0;
2392 spin_unlock_irqrestore
2393 (&hw->bufspec_lock, flags);
2394 }
2395 }
2396 }
2397 }
2398 if (dealloc_flag &&
2399 dpb_is_debug(DECODE_ID(hw),
2400 PRINT_FLAG_DUMP_BUFSPEC))
2401 dump_bufspec(hw, __func__);
2402 return;
2403}
2404
2405unsigned char have_free_buf_spec(struct vdec_s *vdec)
2406{
2407 int i;
2408 unsigned long addr;
2409 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2410 struct aml_vcodec_ctx * v4l = hw->v4l2_ctx;
2411 int canvas_pos_min = BUFSPEC_POOL_SIZE;
2412 int index = -1;
2413 int ret = 0;
2414 int allocated_count = 0;
2415
2416 if (hw->is_used_v4l) {
2417 for (i = 0; i < hw->dpb.mDPB.size; i++) {
2418 if (hw->buffer_spec[i].used == 0 &&
2419 hw->buffer_spec[i].vf_ref == 0 &&
2420 hw->buffer_spec[i].cma_alloc_addr) {
2421 return 1;
2422 }
2423 }
2424
2425 if (v4l2_m2m_num_dst_bufs_ready(v4l->m2m_ctx)
2426 >= run_ready_min_buf_num)
2427 return 1;
2428
2429 return 0;
2430 }
2431
2432 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2433 if (hw->mmu_enable)
2434 addr = hw->buffer_spec[i].alloc_header_addr;
2435 else
2436 addr = hw->buffer_spec[i].cma_alloc_addr;
2437 if (hw->buffer_spec[i].used == 0 &&
2438 hw->buffer_spec[i].vf_ref == 0) {
2439
2440 if (addr)
2441 return 1;
2442 if (hw->buffer_spec[i].canvas_pos < canvas_pos_min) {
2443 canvas_pos_min = hw->buffer_spec[i].canvas_pos;
2444 index = i;
2445 }
2446 }
2447 if (addr)
2448 allocated_count++;
2449 }
2450 if (index >= 0) {
2451 mutex_lock(&vmh264_mutex);
2452 dealloc_buf_specs(hw, 0);
2453 if (max_alloc_buf_count == 0 ||
2454 allocated_count < max_alloc_buf_count) {
2455 if (alloc_one_buf_spec(hw, index) >= 0)
2456 ret = 1;
2457 }
2458 mutex_unlock(&vmh264_mutex);
2459 }
2460
2461 return ret;
2462}
2463
2464static int get_buf_spec_by_canvas_pos(struct vdec_h264_hw_s *hw,
2465 int canvas_pos)
2466{
2467 int i;
2468 int j = 0;
2469 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2470 if (hw->buffer_spec[i].canvas_pos >= 0) {
2471 if (j == canvas_pos)
2472 return i;
2473 j++;
2474 }
2475 }
2476 return -1;
2477}
2478static void update_vf_memhandle(struct vdec_h264_hw_s *hw,
2479 struct vframe_s *vf, int index)
2480{
2481 if (index < 0) {
2482 vf->mem_handle = NULL;
2483 vf->mem_head_handle = NULL;
2484 } else if (vf->type & VIDTYPE_SCATTER) {
2485 vf->mem_handle =
2486 decoder_mmu_box_get_mem_handle(
2487 hw->mmu_box, index);
2488 vf->mem_head_handle =
2489 decoder_bmmu_box_get_mem_handle(
2490 hw->bmmu_box, HEADER_BUFFER_IDX(index));
2491 } else {
2492 vf->mem_handle =
2493 decoder_bmmu_box_get_mem_handle(
2494 hw->bmmu_box, VF_BUFFER_IDX(index));
2495 /* vf->mem_head_handle =
2496 decoder_bmmu_box_get_mem_handle(
2497 hw->bmmu_box, HEADER_BUFFER_IDX(index));*/
2498 }
2499 return;
2500}
2501static int check_force_interlace(struct vdec_h264_hw_s *hw,
2502 struct FrameStore *frame)
2503{
2504 int bForceInterlace = 0;
2505 /* no di in secure mode, disable force di */
2506 if (vdec_secure(hw_to_vdec(hw)))
2507 return 0;
2508 if (frame->frame) {
2509 if (frame->frame->coded_frame
2510 && !frame->frame->frame_mbs_only_flag) {
2511 if (frame->frame->structure == FRAME)
2512 return 1;
2513 }
2514 }
2515
2516 if ((dec_control & DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE)
2517 && hw->bitstream_restriction_flag
2518 && (hw->frame_width == 1920)
2519 && (hw->frame_height >= 1080)
2520 && (hw->frame_dur == 3203 || hw->frame_dur == 3840)) {
2521 bForceInterlace = 1;
2522 } else if ((dec_control & DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE)
2523 && (hw->frame_width == 720)
2524 && (hw->frame_height == 576)
2525 && (hw->frame_dur == 3840)) {
2526 bForceInterlace = 1;
2527 }
2528
2529 return bForceInterlace;
2530}
2531
2532static void fill_frame_info(struct vdec_h264_hw_s *hw, struct FrameStore *frame)
2533{
2534 struct vframe_qos_s *vframe_qos = &hw->vframe_qos;
2535 if (frame->slice_type == I_SLICE)
2536 vframe_qos->type = 1;
2537 else if (frame->slice_type == P_SLICE)
2538 vframe_qos->type = 2;
2539 else if (frame->slice_type == B_SLICE)
2540 vframe_qos->type = 3;
2541
2542 vframe_qos->size = frame->frame_size;
2543 vframe_qos->pts = frame->pts64;
2544
2545 vframe_qos->max_mv = frame->max_mv;
2546 vframe_qos->avg_mv = frame->avg_mv;
2547 vframe_qos->min_mv = frame->min_mv;
2548/*
2549 pr_info("mv: max:%d, avg:%d, min:%d\n",
2550 vframe_qos->max_mv,
2551 vframe_qos->avg_mv,
2552 vframe_qos->min_mv);
2553*/
2554
2555 vframe_qos->max_qp = frame->max_qp;
2556 vframe_qos->avg_qp = frame->avg_qp;
2557 vframe_qos->min_qp = frame->min_qp;
2558/*
2559 pr_info("qp: max:%d, avg:%d, min:%d\n",
2560 vframe_qos->max_qp,
2561 vframe_qos->avg_qp,
2562 vframe_qos->min_qp);
2563*/
2564
2565 vframe_qos->max_skip = frame->max_skip;
2566 vframe_qos->avg_skip = frame->avg_skip;
2567 vframe_qos->min_skip = frame->min_skip;
2568/*
2569 pr_info("skip: max:%d, avg:%d, min:%d\n",
2570 vframe_qos->max_skip,
2571 vframe_qos->avg_skip,
2572 vframe_qos->min_skip);
2573*/
2574 vframe_qos->num++;
2575 if (hw->frameinfo_enable)
2576 vdec_fill_frame_info(vframe_qos, 1);
2577}
2578
2579static int is_iframe(struct FrameStore *frame) {
2580
2581 if (frame->frame && frame->frame->slice_type == I_SLICE) {
2582 return 1;
2583 }
2584 return 0;
2585}
2586
2587
2588
2589int prepare_display_buf(struct vdec_s *vdec, struct FrameStore *frame)
2590{
2591 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2592 struct vframe_s *vf = NULL;
2593 int buffer_index = frame->buf_spec_num;
2594 int vf_count = 1;
2595 int i;
2596 int bForceInterlace = 0;
2597
2598 if (buffer_index < 0 || buffer_index >= BUFSPEC_POOL_SIZE) {
2599 dpb_print(DECODE_ID(hw), 0,
2600 "%s, buffer_index 0x%x is beyond range\n",
2601 __func__, buffer_index);
2602 return -1;
2603 }
2604 if (force_disp_bufspec_num & 0x100) {
2605 /*recycle directly*/
2606 if (hw->buffer_spec[frame->buf_spec_num].used != 3 &&
2607 hw->buffer_spec[frame->buf_spec_num].used != 5)
2608 set_frame_output_flag(&hw->dpb, frame->index);
2609
2610 /*make pre_output not set*/
2611 return -1;
2612 }
2613 if (error_proc_policy & 0x1000) {
2614 int error_skip_i_count = (error_skip_count >> 12) & 0xf;
2615 int error_skip_frame_count = error_skip_count & 0xfff;
2616 if (((hw->no_error_count < error_skip_frame_count)
2617 && (error_skip_i_count == 0 ||
2618 hw->no_error_i_count < error_skip_i_count))
2619 && (!(frame->data_flag & I_FLAG)))
2620 frame->data_flag |= ERROR_FLAG;
2621 }
2622 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
2623 "%s, buffer_index 0x%x frame_error %x poc %d hw error %x error_proc_policy %x\n",
2624 __func__, buffer_index, frame->data_flag & ERROR_FLAG,
2625 frame->poc, hw->data_flag & ERROR_FLAG,
2626 error_proc_policy);
2627 if (frame->frame == NULL &&
2628 ((frame->is_used == 1 && frame->top_field)
2629 || (frame->is_used == 2 && frame->bottom_field))) {
2630 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
2631 "%s Error frame_num %d used %d\n",
2632 __func__, frame->frame_num, frame->is_used);
2633 frame->data_flag |= ERROR_FLAG;
2634 }
2635 if (vdec_stream_based(vdec) && !(frame->data_flag & NODISP_FLAG)) {
2636 if ((pts_lookup_offset_us64(PTS_TYPE_VIDEO,
2637 frame->offset_delimiter, &frame->pts, &frame->frame_size,
2638 0, &frame->pts64) == 0)) {
2639 hw->last_pts64 = frame->pts64;
2640 hw->last_pts = frame->pts;
2641 } else {
2642 frame->pts64 = hw->last_pts64 +DUR2PTS(hw->frame_dur) ;
2643 frame->pts = hw->last_pts + DUR2PTS(hw->frame_dur);
2644 }
2645 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
2646 "%s error= 0x%x poc = %d offset= 0x%x pts= 0x%x last_pts =0x%x pts64 = %lld last_pts64= %lld duration = %d\n",
2647 __func__, (frame->data_flag & ERROR_FLAG), frame->poc,
2648 frame->offset_delimiter, frame->pts,hw->last_pts,
2649 frame->pts64, hw->last_pts64, hw->frame_dur);
2650 hw->last_pts64 = frame->pts64;
2651 hw->last_pts = frame->pts;
2652 }
2653 if ((frame->data_flag & NODISP_FLAG) ||
2654 (frame->data_flag & NULL_FLAG) ||
2655 ((!hw->send_error_frame_flag) &&
2656 (frame->data_flag & ERROR_FLAG)) ||
2657 ((hw->i_only & 0x1) &&
2658 (!(frame->data_flag & I_FLAG)))
2659 ) {
2660 set_frame_output_flag(&hw->dpb, frame->index);
2661 return 0; /*do not return -1,
2662 otherwise flush_dpb() will not flush all dbp frames*/
2663 }
2664
2665 display_frame_count[DECODE_ID(hw)]++;
2666
2667 if (dpb_is_debug(DECODE_ID(hw),
2668 PRINT_FLAG_DPB_DETAIL)) {
2669 dpb_print(DECODE_ID(hw), 0,
2670 "%s, fs[%d] poc %d, buf_spec_num %d\n",
2671 __func__, frame->index, frame->poc,
2672 frame->buf_spec_num);
2673 print_pic_info(DECODE_ID(hw), "predis_frm",
2674 frame->frame, -1);
2675 print_pic_info(DECODE_ID(hw), "predis_top",
2676 frame->top_field, -1);
2677 print_pic_info(DECODE_ID(hw), "predis_bot",
2678 frame->bottom_field, -1);
2679 }
2680
2681 if (!is_interlace(frame))
2682 vf_count = 1;
2683 else
2684 vf_count = 2;
2685 bForceInterlace = check_force_interlace(hw, frame);
2686 if (bForceInterlace)
2687 vf_count = 2;
2688 hw->buffer_spec[buffer_index].vf_ref = 0;
2689 fill_frame_info(hw, frame);
2690 for (i = 0; i < vf_count; i++) {
2691 if (kfifo_get(&hw->newframe_q, &vf) == 0 ||
2692 vf == NULL) {
2693 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2694 "%s fatal error, no available buffer slot.\n",
2695 __func__);
2696 return -1;
2697 }
2698 vf->duration_pulldown = 0;
2699 if (!(is_iframe(frame)) && hw->unstable_pts) {
2700 vf->pts = 0;
2701 vf->pts_us64 = 0;
2702 vf->timestamp = 0;
2703 vf->index = VF_INDEX(frame->index, buffer_index);
2704 } else {
2705 vf->pts = frame->pts;
2706 vf->pts_us64 = frame->pts64;
2707 vf->timestamp = frame->timestamp;
2708 vf->index = VF_INDEX(frame->index, buffer_index);
2709 }
2710
2711 if (hw->is_used_v4l) {
2712 vf->v4l_mem_handle
2713 = hw->buffer_spec[buffer_index].cma_alloc_addr;
2714 }
2715
2716 if (hw->mmu_enable) {
2717 if (hw->double_write_mode & 0x10) {
2718 /* double write only */
2719 vf->compBodyAddr = 0;
2720 vf->compHeadAddr = 0;
2721 } else {
2722 /*head adr*/
2723 vf->compHeadAddr =
2724 hw->buffer_spec[buffer_index].alloc_header_addr;
2725 /*body adr*/
2726 vf->compBodyAddr = 0;
2727 vf->canvas0Addr = vf->canvas1Addr = 0;
2728 }
2729
2730 vf->type = VIDTYPE_SCATTER;
2731
2732 if (hw->double_write_mode) {
2733 vf->type |= VIDTYPE_PROGRESSIVE
2734 | VIDTYPE_VIU_FIELD;
2735 vf->type |= VIDTYPE_VIU_NV21;
2736 if (hw->double_write_mode == 3)
2737 vf->type |= VIDTYPE_COMPRESS;
2738
2739 vf->canvas0Addr = vf->canvas1Addr = -1;
2740 vf->plane_num = 2;
2741 vf->canvas0_config[0] =
2742 hw->buffer_spec[buffer_index].
2743 canvas_config[0];
2744 vf->canvas0_config[1] =
2745 hw->buffer_spec[buffer_index].
2746 canvas_config[1];
2747
2748 vf->canvas1_config[0] =
2749 hw->buffer_spec[buffer_index].
2750 canvas_config[0];
2751 vf->canvas1_config[1] =
2752 hw->buffer_spec[buffer_index].
2753 canvas_config[1];
2754
2755 } else {
2756 vf->type |=
2757 VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
2758 vf->canvas0Addr = vf->canvas1Addr = 0;
2759 }
2760
2761 vf->bitdepth =
2762 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
2763
2764 vf->compWidth = hw->frame_width;
2765 vf->compHeight = hw->frame_height;
2766 } else {
2767 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD |
2768 VIDTYPE_VIU_NV21;
2769
2770 vf->canvas0Addr = vf->canvas1Addr =
2771 spec2canvas(&hw->buffer_spec[buffer_index]);
2772#ifdef VDEC_DW
2773 if (IS_VDEC_DW(hw))
2774 vf->canvas0Addr = vf->canvas1Addr =
2775 vdec_dw_spec2canvas(&hw->buffer_spec[buffer_index]);
2776#endif
2777
2778 }
2779 set_frame_info(hw, vf, buffer_index);
2780
2781 if (hw->mmu_enable && hw->double_write_mode) {
2782 vf->width = hw->frame_width /
2783 get_double_write_ratio(hw);
2784 vf->height = hw->frame_height /
2785 get_double_write_ratio(hw);
2786 }
2787
2788 vf->flag = 0;
2789 if (frame->data_flag & I_FLAG)
2790 vf->flag |= VFRAME_FLAG_SYNCFRAME;
2791 if (frame->data_flag & ERROR_FLAG)
2792 vf->flag |= VFRAME_FLAG_ERROR_RECOVERY;
2793 update_vf_memhandle(hw, vf, buffer_index);
2794 hw->buffer_spec[buffer_index].used = 2;
2795 hw->buffer_spec[buffer_index].vf_ref++;
2796
2797 if (bForceInterlace || is_interlace(frame)) {
2798 vf->type =
2799 VIDTYPE_INTERLACE_FIRST |
2800 VIDTYPE_VIU_NV21;
2801
2802 if (bForceInterlace) {
2803 vf->type |= (i == 0 ?
2804 VIDTYPE_INTERLACE_TOP :
2805 VIDTYPE_INTERLACE_BOTTOM);
2806 if (i == 1) {
2807 vf->pts = 0;
2808 vf->pts_us64 = 0;
2809 }
2810 } else if (frame->top_field->poc <=
2811 frame->bottom_field->poc) /*top first*/
2812 vf->type |= (i == 0 ?
2813 VIDTYPE_INTERLACE_TOP :
2814 VIDTYPE_INTERLACE_BOTTOM);
2815 else
2816 vf->type |= (i == 0 ?
2817 VIDTYPE_INTERLACE_BOTTOM :
2818 VIDTYPE_INTERLACE_TOP);
2819 vf->duration = vf->duration/2;
2820 }
2821
2822 if (i == 0)
2823 decoder_do_frame_check(hw_to_vdec(hw), vf);
2824
2825 /*vf->ratio_control |= (0x3FF << DISP_RATIO_ASPECT_RATIO_BIT);*/
2826 vf->sar_width = hw->width_aspect_ratio;
2827 vf->sar_height = hw->height_aspect_ratio;
2828
2829 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
2830 ATRACE_COUNTER(MODULE_NAME, vf->pts);
2831 hw->vf_pre_count++;
2832 vdec->vdec_fps_detec(vdec->id);
2833 if (without_display_mode == 0) {
2834 vf_notify_receiver(vdec->vf_provider_name,
2835 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
2836 } else
2837 vh264_vf_put(vh264_vf_get(vdec), vdec);
2838 }
2839 if (dpb_is_debug(DECODE_ID(hw),
2840 PRINT_FLAG_DUMP_BUFSPEC))
2841 dump_bufspec(hw, __func__);
2842
2843 return 0;
2844}
2845
2846int notify_v4l_eos(struct vdec_s *vdec)
2847{
2848 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2849 struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
2850 struct vframe_s *vf = &hw->vframe_dummy;
2851 struct vdec_v4l2_buffer *fb = NULL;
2852 int index = INVALID_IDX;
2853 ulong expires;
2854
2855 if (hw->is_used_v4l && hw->eos) {
2856 expires = jiffies + msecs_to_jiffies(2000);
2857 while (INVALID_IDX == (index = v4l_get_free_buf_idx(vdec))) {
2858 if (time_after(jiffies, expires) ||
2859 v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx))
2860 break;
2861 }
2862
2863 if (index == INVALID_IDX) {
2864 if (vdec_v4l_get_buffer(hw->v4l2_ctx, &fb) < 0) {
2865 pr_err("[%d] EOS get free buff fail.\n", ctx->id);
2866 return -1;
2867 }
2868 }
2869
2870 vf->type |= VIDTYPE_V4L_EOS;
2871 vf->timestamp = ULONG_MAX;
2872 vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L;
2873 vf->v4l_mem_handle = (index == INVALID_IDX) ? (ulong)fb :
2874 hw->buffer_spec[index].cma_alloc_addr;
2875
2876 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
2877
2878 ATRACE_COUNTER(MODULE_NAME, vf->pts);
2879 vf_notify_receiver(vdec->vf_provider_name,
2880 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
2881
2882 pr_info("[%d] H264 EOS notify.\n", ctx->id);
2883 }
2884
2885 return 0;
2886}
2887
2888/******************
2889 * Hardware config
2890 */
2891char *slice_type_name[] = {
2892 "P_SLICE ",
2893 "B_SLICE ",
2894 "I_SLICE ",
2895 "SP_SLICE",
2896 "SI_SLICE",
2897};
2898
2899char *picture_structure_name[] = {
2900 "FRAME",
2901 "TOP_FIELD",
2902 "BOTTOM_FIELD"
2903};
2904
2905void print_pic_info(int decindex, const char *info,
2906 struct StorablePicture *pic,
2907 int slice_type)
2908{
2909 if (pic)
2910 dpb_print(decindex, PRINT_FLAG_DEC_DETAIL,
2911 "%s: %s (original %s), %s, mb_aff_frame_flag %d poc %d, pic_num %d, buf_spec_num %d data_flag 0x%x\n",
2912 info,
2913 picture_structure_name[pic->structure],
2914 pic->coded_frame ? "Frame" : "Field",
2915 (slice_type < 0 ||
2916 slice_type >= (sizeof(slice_type_name) / sizeof(slice_type_name[0]))) ? "" : slice_type_name[slice_type],
2917 pic->mb_aff_frame_flag,
2918 pic->poc,
2919 pic->pic_num,
2920 pic->buf_spec_num,
2921 pic->data_flag);
2922}
2923
2924static void reset_process_time(struct vdec_h264_hw_s *hw)
2925{
2926 if (hw->start_process_time) {
2927 unsigned process_time =
2928 1000 * (jiffies - hw->start_process_time) / HZ;
2929 hw->start_process_time = 0;
2930 if (process_time > max_process_time[DECODE_ID(hw)])
2931 max_process_time[DECODE_ID(hw)] = process_time;
2932 }
2933}
2934
2935static void start_process_time(struct vdec_h264_hw_s *hw)
2936{
2937 hw->decode_timeout_count = 10;
2938 hw->start_process_time = jiffies;
2939}
2940
2941static void config_aux_buf(struct vdec_h264_hw_s *hw)
2942{
2943 WRITE_VREG(H264_AUX_ADR, hw->aux_phy_addr);
2944 WRITE_VREG(H264_AUX_DATA_SIZE,
2945 ((hw->prefix_aux_size >> 4) << 16) |
2946 (hw->suffix_aux_size >> 4)
2947 );
2948}
2949
2950/*
2951* dv_meta_flag: 1, dolby meta only; 2, not include dolby meta
2952*/
2953static void set_aux_data(struct vdec_h264_hw_s *hw,
2954 struct StorablePicture *pic, unsigned char suffix_flag,
2955 unsigned char dv_meta_flag, struct vdec_h264_hw_s *hw_b)
2956{
2957 int i;
2958 unsigned short *aux_adr;
2959 unsigned size_reg_val =
2960 READ_VREG(H264_AUX_DATA_SIZE);
2961 unsigned aux_count = 0;
2962 int aux_size = 0;
2963 struct vdec_h264_hw_s *hw_buf = hw_b ? hw_b : hw;
2964 if (pic == NULL || pic->buf_spec_num < 0 || pic->buf_spec_num >= BUFSPEC_POOL_SIZE
2965 || (!is_buf_spec_in_use(hw, pic->buf_spec_num)))
2966 return;
2967
2968 if (suffix_flag) {
2969 aux_adr = (unsigned short *)
2970 (hw_buf->aux_addr +
2971 hw_buf->prefix_aux_size);
2972 aux_count =
2973 ((size_reg_val & 0xffff) << 4)
2974 >> 1;
2975 aux_size =
2976 hw_buf->suffix_aux_size;
2977 } else {
2978 aux_adr =
2979 (unsigned short *)hw_buf->aux_addr;
2980 aux_count =
2981 ((size_reg_val >> 16) << 4)
2982 >> 1;
2983 aux_size =
2984 hw_buf->prefix_aux_size;
2985 }
2986 if (dpb_is_debug(DECODE_ID(hw),
2987 PRINT_FLAG_DPB_DETAIL)) {
2988 dpb_print(DECODE_ID(hw), 0,
2989 "%s:old size %d count %d,suf %d dv_flag %d\r\n",
2990 __func__, AUX_DATA_SIZE(pic),
2991 aux_count, suffix_flag, dv_meta_flag);
2992 }
2993 if (aux_size > 0 && aux_count > 0) {
2994 int heads_size = 0;
2995 int new_size;
2996 char *new_buf;
2997 for (i = 0; i < aux_count; i++) {
2998 unsigned char tag = aux_adr[i] >> 8;
2999 if (tag != 0 && tag != 0xff) {
3000 if (dv_meta_flag == 0)
3001 heads_size += 8;
3002 else if (dv_meta_flag == 1 && tag == 0x1)
3003 heads_size += 8;
3004 else if (dv_meta_flag == 2 && tag != 0x1)
3005 heads_size += 8;
3006 }
3007 }
3008 new_size = AUX_DATA_SIZE(pic) + aux_count + heads_size;
3009 new_buf = krealloc(AUX_DATA_BUF(pic),
3010 new_size,
3011 GFP_KERNEL);
3012 if (new_buf) {
3013 unsigned char valid_tag = 0;
3014 unsigned char *h =
3015 new_buf +
3016 AUX_DATA_SIZE(pic);
3017 unsigned char *p = h + 8;
3018 int len = 0;
3019 int padding_len = 0;
3020 AUX_DATA_BUF(pic) = new_buf;
3021 for (i = 0; i < aux_count; i += 4) {
3022 int ii;
3023 unsigned char tag = aux_adr[i + 3] >> 8;
3024 if (tag != 0 && tag != 0xff) {
3025 if (dv_meta_flag == 0)
3026 valid_tag = 1;
3027 else if (dv_meta_flag == 1
3028 && tag == 0x1)
3029 valid_tag = 1;
3030 else if (dv_meta_flag == 2
3031 && tag != 0x1)
3032 valid_tag = 1;
3033 else
3034 valid_tag = 0;
3035 if (valid_tag && len > 0) {
3036 AUX_DATA_SIZE(pic) +=
3037 (len + 8);
3038 h[0] =
3039 (len >> 24) & 0xff;
3040 h[1] =
3041 (len >> 16) & 0xff;
3042 h[2] =
3043 (len >> 8) & 0xff;
3044 h[3] =
3045 (len >> 0) & 0xff;
3046 h[6] =
3047 (padding_len >> 8)
3048 & 0xff;
3049 h[7] =
3050 (padding_len) & 0xff;
3051 h += (len + 8);
3052 p += 8;
3053 len = 0;
3054 padding_len = 0;
3055 }
3056 if (valid_tag) {
3057 h[4] = tag;
3058 h[5] = 0;
3059 h[6] = 0;
3060 h[7] = 0;
3061 }
3062 }
3063 if (valid_tag) {
3064 for (ii = 0; ii < 4; ii++) {
3065 unsigned short aa =
3066 aux_adr[i + 3
3067 - ii];
3068 *p = aa & 0xff;
3069 p++;
3070 len++;
3071 /*if ((aa >> 8) == 0xff)
3072 padding_len++;*/
3073 }
3074 }
3075 }
3076 if (len > 0) {
3077 AUX_DATA_SIZE(pic) += (len + 8);
3078 h[0] = (len >> 24) & 0xff;
3079 h[1] = (len >> 16) & 0xff;
3080 h[2] = (len >> 8) & 0xff;
3081 h[3] = (len >> 0) & 0xff;
3082 h[6] = (padding_len >> 8) & 0xff;
3083 h[7] = (padding_len) & 0xff;
3084 }
3085 if (dpb_is_debug(DECODE_ID(hw),
3086 PRINT_FLAG_DPB_DETAIL)) {
3087 dpb_print(DECODE_ID(hw), 0,
3088 "aux: (size %d) suffix_flag %d\n",
3089 AUX_DATA_SIZE(pic), suffix_flag);
3090 for (i = 0; i < AUX_DATA_SIZE(pic); i++) {
3091 dpb_print_cont(DECODE_ID(hw), 0,
3092 "%02x ", AUX_DATA_BUF(pic)[i]);
3093 if (((i + 1) & 0xf) == 0)
3094 dpb_print_cont(
3095 DECODE_ID(hw),
3096 0, "\n");
3097 }
3098 dpb_print_cont(DECODE_ID(hw),
3099 0, "\n");
3100 }
3101
3102 }
3103 }
3104
3105}
3106
3107static void release_aux_data(struct vdec_h264_hw_s *hw,
3108 int buf_spec_num)
3109{
3110 kfree(hw->buffer_spec[buf_spec_num].aux_data_buf);
3111 hw->buffer_spec[buf_spec_num].aux_data_buf = NULL;
3112 hw->buffer_spec[buf_spec_num].aux_data_size = 0;
3113}
3114
3115static void dump_aux_buf(struct vdec_h264_hw_s *hw)
3116{
3117 int i;
3118 unsigned short *aux_adr =
3119 (unsigned short *)
3120 hw->aux_addr;
3121 unsigned aux_size =
3122 (READ_VREG(H264_AUX_DATA_SIZE)
3123 >> 16) << 4;
3124
3125 if (hw->prefix_aux_size > 0) {
3126 dpb_print(DECODE_ID(hw),
3127 0,
3128 "prefix aux: (size %d)\n",
3129 aux_size);
3130 for (i = 0; i <
3131 (aux_size >> 1); i++) {
3132 dpb_print_cont(DECODE_ID(hw),
3133 0,
3134 "%04x ",
3135 *(aux_adr + i));
3136 if (((i + 1) & 0xf)
3137 == 0)
3138 dpb_print_cont(
3139 DECODE_ID(hw),
3140 0, "\n");
3141 }
3142 }
3143 if (hw->suffix_aux_size > 0) {
3144 aux_adr = (unsigned short *)
3145 (hw->aux_addr +
3146 hw->prefix_aux_size);
3147 aux_size =
3148 (READ_VREG(H264_AUX_DATA_SIZE) & 0xffff)
3149 << 4;
3150 dpb_print(DECODE_ID(hw),
3151 0,
3152 "suffix aux: (size %d)\n",
3153 aux_size);
3154 for (i = 0; i <
3155 (aux_size >> 1); i++) {
3156 dpb_print_cont(DECODE_ID(hw),
3157 0,
3158 "%04x ", *(aux_adr + i));
3159 if (((i + 1) & 0xf) == 0)
3160 dpb_print_cont(DECODE_ID(hw),
3161 0, "\n");
3162 }
3163 }
3164}
3165
3166static void config_decode_mode(struct vdec_h264_hw_s *hw)
3167{
3168#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3169 struct vdec_s *vdec = hw_to_vdec(hw);
3170#endif
3171 if (input_frame_based(hw_to_vdec(hw)))
3172 WRITE_VREG(H264_DECODE_MODE,
3173 DECODE_MODE_MULTI_FRAMEBASE);
3174#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3175 else if (vdec->slave)
3176 WRITE_VREG(H264_DECODE_MODE,
3177 (hw->got_valid_nal << 8) |
3178 DECODE_MODE_MULTI_DVBAL);
3179 else if (vdec->master)
3180 WRITE_VREG(H264_DECODE_MODE,
3181 (hw->got_valid_nal << 8) |
3182 DECODE_MODE_MULTI_DVENL);
3183#endif
3184 else
3185 WRITE_VREG(H264_DECODE_MODE,
3186 DECODE_MODE_MULTI_STREAMBASE);
3187 WRITE_VREG(H264_DECODE_SEQINFO,
3188 hw->seq_info2);
3189 WRITE_VREG(HEAD_PADING_REG, 0);
3190
3191 if (hw->init_flag == 0)
3192 WRITE_VREG(INIT_FLAG_REG, 0);
3193 else
3194 WRITE_VREG(INIT_FLAG_REG, 1);
3195}
3196int config_decode_buf(struct vdec_h264_hw_s *hw, struct StorablePicture *pic)
3197{
3198 /* static int count = 0; */
3199 int ret = 0;
3200 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3201 struct Slice *pSlice = &(p_H264_Dpb->mSlice);
3202 unsigned int colocate_adr_offset;
3203 unsigned int val;
3204 struct StorablePicture *last_pic = hw->last_dec_picture;
3205
3206#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
3207 int colocate_buf_index;
3208#endif
3209#define H264_BUFFER_INFO_INDEX PMV3_X /* 0xc24 */
3210#define H264_BUFFER_INFO_DATA PMV2_X /* 0xc22 */
3211#define H264_CURRENT_POC_IDX_RESET LAST_SLICE_MV_ADDR /* 0xc30 */
3212#define H264_CURRENT_POC LAST_MVY /* 0xc32 shared with conceal MV */
3213
3214#define H264_CO_MB_WR_ADDR VLD_C38 /* 0xc38 */
3215/* bit 31:30 -- L1[0] picture coding structure,
3216 * 00 - top field, 01 - bottom field,
3217 * 10 - frame, 11 - mbaff frame
3218 * bit 29 - L1[0] top/bot for B field pciture , 0 - top, 1 - bot
3219 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3220 * -- only used for B Picture Direct mode [2:0] will set to 3'b000
3221 */
3222#define H264_CO_MB_RD_ADDR VLD_C39 /* 0xc39 */
3223
3224/* bit 15 -- flush co_mb_data to DDR -- W-Only
3225 * bit 14 -- h264_co_mb_mem_wr_addr write Enable -- W-Only
3226 * bit 13 -- h264_co_mb_info_wr_ptr write Enable -- W-Only
3227 * bit 9 -- soft_reset -- W-Only
3228 * bit 8 -- upgent
3229 * bit 7:2 -- h264_co_mb_mem_wr_addr
3230 * bit 1:0 -- h264_co_mb_info_wr_ptr
3231 */
3232#define H264_CO_MB_RW_CTL VLD_C3D /* 0xc3d */
3233#define DCAC_DDR_BYTE64_CTL 0x0e1d
3234 unsigned long canvas_adr;
3235 unsigned int ref_reg_val;
3236 unsigned int one_ref_cfg = 0;
3237 int h264_buffer_info_data_write_count;
3238 int i, j;
3239 unsigned int colocate_wr_adr;
3240 unsigned int colocate_rd_adr;
3241 unsigned char use_direct_8x8;
3242 int canvas_pos;
3243 canvas_pos = hw->buffer_spec[pic->buf_spec_num].canvas_pos;
3244 WRITE_VREG(H264_CURRENT_POC_IDX_RESET, 0);
3245 WRITE_VREG(H264_CURRENT_POC, pic->frame_poc);
3246 WRITE_VREG(H264_CURRENT_POC, pic->top_poc);
3247 WRITE_VREG(H264_CURRENT_POC, pic->bottom_poc);
3248
3249 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3250 "%s: pic_num is %d, poc is %d (%d, %d, %d), buf_spec_num %d canvas_pos %d\n",
3251 __func__, pic->pic_num, pic->poc, pic->frame_poc,
3252 pic->top_poc, pic->bottom_poc, pic->buf_spec_num,
3253 canvas_pos);
3254 print_pic_info(DECODE_ID(hw), "cur", pic, pSlice->slice_type);
3255
3256#ifdef VDEC_DW
3257 if (IS_VDEC_DW(hw) && pic->mb_aff_frame_flag)
3258 WRITE_VREG(MDEC_DOUBLEW_CFG0,
3259 ( READ_VREG(MDEC_DOUBLEW_CFG0) & (~(1 << 30))));
3260#endif
3261 WRITE_VREG(CURR_CANVAS_CTRL, canvas_pos << 24);
3262 canvas_adr = READ_VREG(CURR_CANVAS_CTRL) & 0xffffff;
3263
3264 if (!hw->mmu_enable) {
3265 WRITE_VREG(REC_CANVAS_ADDR, canvas_adr);
3266 WRITE_VREG(DBKR_CANVAS_ADDR, canvas_adr);
3267 WRITE_VREG(DBKW_CANVAS_ADDR, canvas_adr);
3268#ifdef VDEC_DW
3269 WRITE_VREG(MDEC_DOUBLEW_CFG1,
3270 (hw->buffer_spec[canvas_pos].vdec_dw_y_canvas_index
3271 | (hw->buffer_spec[canvas_pos].vdec_dw_u_canvas_index << 8)));
3272#endif
3273 } else
3274 hevc_sao_set_pic_buffer(hw, pic);
3275
3276 if (pic->mb_aff_frame_flag)
3277 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf4c0;
3278 else if (pic->structure == TOP_FIELD)
3279 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf400;
3280 else if (pic->structure == BOTTOM_FIELD)
3281 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf440;
3282 else
3283 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf480;
3284
3285 if (pic->bottom_poc < pic->top_poc)
3286 hw->buffer_spec[pic->buf_spec_num].info0 |= 0x100;
3287
3288 hw->buffer_spec[pic->buf_spec_num].info1 = pic->top_poc;
3289 hw->buffer_spec[pic->buf_spec_num].info2 = pic->bottom_poc;
3290 WRITE_VREG(H264_BUFFER_INFO_INDEX, 16);
3291
3292 for (j = 0; j < hw->dpb.mDPB.size; j++) {
3293 int long_term_flag;
3294 i = get_buf_spec_by_canvas_pos(hw, j);
3295 if (i < 0)
3296 break;
3297 long_term_flag =
3298 get_long_term_flag_by_buf_spec_num(p_H264_Dpb, i);
3299 if (long_term_flag > 0) {
3300 if (long_term_flag & 0x1)
3301 hw->buffer_spec[i].info0 |= (1 << 4);
3302 else
3303 hw->buffer_spec[i].info0 &= ~(1 << 4);
3304
3305 if (long_term_flag & 0x2)
3306 hw->buffer_spec[i].info0 |= (1 << 5);
3307 else
3308 hw->buffer_spec[i].info0 &= ~(1 << 5);
3309 }
3310
3311 if (i == pic->buf_spec_num)
3312 WRITE_VREG(H264_BUFFER_INFO_DATA,
3313 hw->buffer_spec[i].info0 | 0xf);
3314 else
3315 WRITE_VREG(H264_BUFFER_INFO_DATA,
3316 hw->buffer_spec[i].info0);
3317 WRITE_VREG(H264_BUFFER_INFO_DATA, hw->buffer_spec[i].info1);
3318 WRITE_VREG(H264_BUFFER_INFO_DATA, hw->buffer_spec[i].info2);
3319 }
3320
3321 /* config reference buffer */
3322 if (hw->mmu_enable) {
3323 hevc_mcr_config_mc_ref(hw);
3324 hevc_mcr_config_mcrcc(hw);
3325 }
3326
3327 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3328 "list0 size %d\n", pSlice->listXsize[0]);
3329 WRITE_VREG(H264_BUFFER_INFO_INDEX, 0);
3330 ref_reg_val = 0;
3331 j = 0;
3332 h264_buffer_info_data_write_count = 0;
3333
3334 //disable this read cache when frame width <= 64 (4MBs)
3335 //IQIDCT_CONTROL, bit[16] dcac_dma_read_cache_disable
3336 if (hw->frame_width <= 64) {
3337 SET_VREG_MASK(IQIDCT_CONTROL,(1 << 16));
3338 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A))
3339 // Disable DDR_BYTE64_CACHE
3340 WRITE_VREG(DCAC_DDR_BYTE64_CTL,
3341 (READ_VREG(DCAC_DDR_BYTE64_CTL) & (~0xf)) | 0xa);
3342 }
3343 else
3344 CLEAR_VREG_MASK(IQIDCT_CONTROL,(1 << 16));
3345
3346 if (last_pic)
3347 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
3348 "last_pic->data_flag %x slice_type %x last_pic->slice_type %x\n",
3349 last_pic->data_flag, pSlice->slice_type, last_pic->slice_type);
3350 if (!hw->i_only && !(error_proc_policy & 0x2000) &&
3351 last_pic && (last_pic->data_flag & ERROR_FLAG)
3352 && (!(last_pic->slice_type == B_SLICE))
3353 && (!(pSlice->slice_type == I_SLICE))) {
3354 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
3355 "no i/idr error mark\n");
3356 hw->data_flag |= ERROR_FLAG;
3357 pic->data_flag |= ERROR_FLAG;
3358 }
3359
3360 for (i = 0; i < (unsigned int)(pSlice->listXsize[0]); i++) {
3361 /*ref list 0 */
3362 struct StorablePicture *ref = pSlice->listX[0][i];
3363 unsigned int cfg;
3364 /* bit[6:5] - frame/field info,
3365 * 01 - top, 10 - bottom, 11 - frame
3366 */
3367 #ifdef ERROR_CHECK
3368 if (ref == NULL) {
3369 hw->data_flag |= ERROR_FLAG;
3370 pic->data_flag |= ERROR_FLAG;
3371 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref list0 NULL\n");
3372 return -1;
3373 }
3374 if ((ref->data_flag & ERROR_FLAG) && ref_frame_mark_flag[DECODE_ID(hw)]) {
3375 hw->data_flag |= ERROR_FLAG;
3376 pic->data_flag |= ERROR_FLAG;
3377 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error mark1 \n");
3378 }
3379 if (ref->data_flag & NULL_FLAG)
3380 hw->data_flag |= NULL_FLAG;
3381#endif
3382 canvas_pos = hw->buffer_spec[ref->buf_spec_num].canvas_pos;
3383
3384 if (ref->structure == TOP_FIELD)
3385 cfg = 0x1;
3386 else if (ref->structure == BOTTOM_FIELD)
3387 cfg = 0x2;
3388 else /* FRAME */
3389 cfg = 0x3;
3390
3391 one_ref_cfg = (canvas_pos & 0x1f) | (cfg << 5);
3392 ref_reg_val <<= 8;
3393 ref_reg_val |= one_ref_cfg;
3394 j++;
3395
3396 if (j == 4) {
3397 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3398 "H264_BUFFER_INFO_DATA: %x\n", ref_reg_val);
3399 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3400 h264_buffer_info_data_write_count++;
3401 j = 0;
3402 }
3403 print_pic_info(DECODE_ID(hw), "list0",
3404 pSlice->listX[0][i], -1);
3405 }
3406 if (j != 0) {
3407 while (j != 4) {
3408 ref_reg_val <<= 8;
3409 ref_reg_val |= one_ref_cfg;
3410 j++;
3411 }
3412 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3413 "H264_BUFFER_INFO_DATA: %x\n",
3414 ref_reg_val);
3415 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3416 h264_buffer_info_data_write_count++;
3417 }
3418 ref_reg_val = (one_ref_cfg << 24) | (one_ref_cfg<<16) |
3419 (one_ref_cfg << 8) | one_ref_cfg;
3420 for (i = h264_buffer_info_data_write_count; i < 8; i++)
3421 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3422
3423 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3424 "list1 size %d\n", pSlice->listXsize[1]);
3425 WRITE_VREG(H264_BUFFER_INFO_INDEX, 8);
3426 ref_reg_val = 0;
3427 j = 0;
3428
3429 for (i = 0; i < (unsigned int)(pSlice->listXsize[1]); i++) {
3430 /* ref list 0 */
3431 struct StorablePicture *ref = pSlice->listX[1][i];
3432 unsigned int cfg;
3433 /* bit[6:5] - frame/field info,
3434 * 01 - top, 10 - bottom, 11 - frame
3435 */
3436
3437 #ifdef ERROR_CHECK
3438 if (ref == NULL) {
3439 hw->data_flag |= ERROR_FLAG;
3440 pic->data_flag |= ERROR_FLAG;
3441 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error list1 NULL\n");
3442 return -2;
3443 }
3444 if ((ref->data_flag & ERROR_FLAG) && (ref_frame_mark_flag[DECODE_ID(hw)])) {
3445 pic->data_flag |= ERROR_FLAG;
3446 hw->data_flag |= ERROR_FLAG;
3447 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error mark2\n");
3448 }
3449 if (ref->data_flag & NULL_FLAG)
3450 hw->data_flag |= NULL_FLAG;
3451#endif
3452 canvas_pos = hw->buffer_spec[ref->buf_spec_num].canvas_pos;
3453 if (ref->structure == TOP_FIELD)
3454 cfg = 0x1;
3455 else if (ref->structure == BOTTOM_FIELD)
3456 cfg = 0x2;
3457 else /* FRAME */
3458 cfg = 0x3;
3459 one_ref_cfg = (canvas_pos & 0x1f) | (cfg << 5);
3460 ref_reg_val <<= 8;
3461 ref_reg_val |= one_ref_cfg;
3462 j++;
3463
3464 if (j == 4) {
3465 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3466 "H264_BUFFER_INFO_DATA: %x\n",
3467 ref_reg_val);
3468 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3469 j = 0;
3470 }
3471 print_pic_info(DECODE_ID(hw), "list1",
3472 pSlice->listX[1][i], -1);
3473 }
3474 if (j != 0) {
3475 while (j != 4) {
3476 ref_reg_val <<= 8;
3477 ref_reg_val |= one_ref_cfg;
3478 j++;
3479 }
3480 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3481 "H264_BUFFER_INFO_DATA: %x\n", ref_reg_val);
3482 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3483 }
3484
3485 /* configure co-locate buffer */
3486 while ((READ_VREG(H264_CO_MB_RW_CTL) >> 11) & 0x1)
3487 ;
3488 if ((pSlice->mode_8x8_flags & 0x4) &&
3489 (pSlice->mode_8x8_flags & 0x2))
3490 use_direct_8x8 = 1;
3491 else
3492 use_direct_8x8 = 0;
3493
3494#ifndef ONE_COLOCATE_BUF_PER_DECODE_BUF
3495 colocate_adr_offset =
3496 ((pic->structure == FRAME && pic->mb_aff_frame_flag == 0)
3497 ? 1 : 2) * 96;
3498 if (use_direct_8x8)
3499 colocate_adr_offset >>= 2;
3500
3501 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3502 "colocate buf size of each mb 0x%x first_mb_in_slice 0x%x colocate_adr_offset 0x%x\r\n",
3503 colocate_adr_offset, pSlice->first_mb_in_slice,
3504 colocate_adr_offset * pSlice->first_mb_in_slice);
3505
3506 colocate_adr_offset *= pSlice->first_mb_in_slice;
3507
3508 if ((pic->colocated_buf_index >= 0) &&
3509 (pic->colocated_buf_index < p_H264_Dpb->colocated_buf_count)) {
3510 colocate_wr_adr = p_H264_Dpb->colocated_mv_addr_start +
3511 ((p_H264_Dpb->colocated_buf_size *
3512 pic->colocated_buf_index)
3513 >> (use_direct_8x8 ? 2 : 0));
3514 if ((colocate_wr_adr + p_H264_Dpb->colocated_buf_size) >
3515 p_H264_Dpb->colocated_mv_addr_end) {
3516 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3517 "Error, colocate buf is not enough, index is %d\n",
3518 pic->colocated_buf_index);
3519 ret = -3;
3520 }
3521 val = colocate_wr_adr + colocate_adr_offset;
3522 WRITE_VREG(H264_CO_MB_WR_ADDR, val);
3523 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3524 "WRITE_VREG(H264_CO_MB_WR_ADDR) = %x, first_mb_in_slice %x pic_structure %x colocate_adr_offset %x mode_8x8_flags %x colocated_buf_size %x\n",
3525 val, pSlice->first_mb_in_slice, pic->structure,
3526 colocate_adr_offset, pSlice->mode_8x8_flags,
3527 p_H264_Dpb->colocated_buf_size);
3528 } else {
3529 WRITE_VREG(H264_CO_MB_WR_ADDR, 0xffffffff);
3530 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3531 "WRITE_VREG(H264_CO_MB_WR_ADDR) = 0xffffffff\n");
3532 }
3533#else
3534 colocate_buf_index = hw->buffer_spec[pic->buf_spec_num].canvas_pos;
3535 colocate_adr_offset =
3536 ((pic->structure == FRAME && pic->mb_aff_frame_flag == 0) ? 1 : 2) * 96;
3537 if (use_direct_8x8)
3538 colocate_adr_offset >>= 2;
3539
3540 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3541 "colocate buf size of each mb 0x%x first_mb_in_slice 0x%x colocate_adr_offset 0x%x\r\n",
3542 colocate_adr_offset, pSlice->first_mb_in_slice,
3543 colocate_adr_offset * pSlice->first_mb_in_slice);
3544
3545 colocate_adr_offset *= pSlice->first_mb_in_slice;
3546
3547 colocate_wr_adr = p_H264_Dpb->colocated_mv_addr_start +
3548 ((p_H264_Dpb->colocated_buf_size * colocate_buf_index) >>
3549 (use_direct_8x8 ? 2 : 0));
3550
3551 if ((colocate_wr_adr + p_H264_Dpb->colocated_buf_size) >
3552 p_H264_Dpb->colocated_mv_addr_end) {
3553 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3554 "Error, colocate buf is not enough, col buf index is %d\n",
3555 colocate_buf_index);
3556 ret = -4;
3557 }
3558 val = colocate_wr_adr + colocate_adr_offset;
3559 WRITE_VREG(H264_CO_MB_WR_ADDR, val);
3560 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3561 "WRITE_VREG(H264_CO_MB_WR_ADDR) = %x, first_mb_in_slice %x pic_structure %x colocate_adr_offset %x mode_8x8_flags %x colocated_buf_size %x\n",
3562 val, pSlice->first_mb_in_slice, pic->structure,
3563 colocate_adr_offset, pSlice->mode_8x8_flags,
3564 p_H264_Dpb->colocated_buf_size);
3565#endif
3566 if (pSlice->listXsize[1] > 0) {
3567 struct StorablePicture *colocate_pic = pSlice->listX[1][0];
3568 /* H264_CO_MB_RD_ADDR[bit 31:30],
3569 * original picture structure of L1[0],
3570 * 00 - top field, 01 - bottom field,
3571 * 10 - frame, 11 - mbaff frame
3572 */
3573 int l10_structure;
3574 int cur_colocate_ref_type;
3575 /* H264_CO_MB_RD_ADDR[bit 29], top/bot for B field pciture,
3576 * 0 - top, 1 - bot
3577 */
3578 unsigned int val;
3579#ifdef ERROR_CHECK
3580 if (colocate_pic == NULL) {
3581 hw->data_flag |= ERROR_FLAG;
3582 pic->data_flag |= ERROR_FLAG;
3583 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " colocate error pic NULL\n");
3584 return -5;
3585 }
3586 if (colocate_pic->data_flag & ERROR_FLAG) {
3587 pic->data_flag |= ERROR_FLAG;
3588 hw->data_flag |= ERROR_FLAG;
3589 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " colocare ref error mark\n");
3590 }
3591 if (colocate_pic->data_flag & NULL_FLAG)
3592 hw->data_flag |= NULL_FLAG;
3593#endif
3594
3595 if (colocate_pic->mb_aff_frame_flag)
3596 l10_structure = 3;
3597 else {
3598 if (colocate_pic->coded_frame)
3599 l10_structure = 2;
3600 else
3601 l10_structure = (colocate_pic->structure ==
3602 BOTTOM_FIELD) ? 1 : 0;
3603 }
3604#if 0
3605 /*case0016, p16,
3606 *cur_colocate_ref_type should be configured base on current pic
3607 */
3608 if (pic->structure == FRAME &&
3609 pic->mb_aff_frame_flag)
3610 cur_colocate_ref_type = 0;
3611 else if (pic->structure == BOTTOM_FIELD)
3612 cur_colocate_ref_type = 1;
3613 else
3614 cur_colocate_ref_type = 0;
3615#else
3616 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3617 " CUR TMP DEBUG : mb_aff_frame_flag : %d, structure : %d coded_frame %d\n",
3618 pic->mb_aff_frame_flag,
3619 pic->structure,
3620 pic->coded_frame);
3621 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3622 " COL TMP DEBUG : mb_aff_frame_flag : %d, structure : %d coded_frame %d\n",
3623 colocate_pic->mb_aff_frame_flag,
3624 colocate_pic->structure,
3625 colocate_pic->coded_frame);
3626 if (pic->structure == FRAME || pic->mb_aff_frame_flag) {
3627 cur_colocate_ref_type =
3628 (abs(pic->poc - colocate_pic->top_poc)
3629 < abs(pic->poc -
3630 colocate_pic->bottom_poc)) ? 0 : 1;
3631 } else
3632 cur_colocate_ref_type =
3633 (colocate_pic->structure
3634 == BOTTOM_FIELD) ? 1 : 0;
3635#endif
3636
3637#ifndef ONE_COLOCATE_BUF_PER_DECODE_BUF
3638 if ((colocate_pic->colocated_buf_index >= 0) &&
3639 (colocate_pic->colocated_buf_index <
3640 p_H264_Dpb->colocated_buf_count)) {
3641 colocate_rd_adr = p_H264_Dpb->colocated_mv_addr_start +
3642 ((p_H264_Dpb->colocated_buf_size *
3643 colocate_pic->colocated_buf_index)
3644 >> (use_direct_8x8 ? 2 : 0));
3645 if ((colocate_rd_adr + p_H264_Dpb->colocated_buf_size) >
3646 p_H264_Dpb->colocated_mv_addr_end) {
3647 dpb_print(DECODE_ID(hw),
3648 PRINT_FLAG_ERROR,
3649 "Error, colocate buf is not enough, index is %d\n",
3650 colocate_pic->colocated_buf_index);
3651 ret = -6;
3652 }
3653 /* bit 31:30 -- L1[0] picture coding structure,
3654 * 00 - top field, 01 - bottom field,
3655 * 10 - frame, 11 - mbaff frame
3656 * bit 29 - L1[0] top/bot for B field pciture,
3657 * 0 - top, 1 - bot
3658 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3659 * -- only used for B Picture Direct mode
3660 * [2:0] will set to 3'b000
3661 */
3662 /* #define H264_CO_MB_RD_ADDR VLD_C39 0xc39 */
3663 val = ((colocate_rd_adr+colocate_adr_offset) >> 3) |
3664 (l10_structure << 30) |
3665 (cur_colocate_ref_type << 29);
3666 WRITE_VREG(H264_CO_MB_RD_ADDR, val);
3667 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3668 "co idx %d, WRITE_VREG(H264_CO_MB_RD_ADDR) = %x, addr %x L1(0) pic_structure %d mbaff %d\n",
3669 colocate_pic->colocated_buf_index,
3670 val, colocate_rd_adr + colocate_adr_offset,
3671 colocate_pic->structure,
3672 colocate_pic->mb_aff_frame_flag);
3673 } else {
3674 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3675 "Error, reference pic has no colocated buf\n");
3676 ret = -7;
3677 }
3678#else
3679 colocate_buf_index =
3680 hw->buffer_spec[colocate_pic->buf_spec_num].canvas_pos;
3681 colocate_rd_adr = p_H264_Dpb->colocated_mv_addr_start +
3682 ((p_H264_Dpb->colocated_buf_size *
3683 colocate_buf_index)
3684 >> (use_direct_8x8 ? 2 : 0));
3685 if ((colocate_rd_adr + p_H264_Dpb->colocated_buf_size) >
3686 p_H264_Dpb->colocated_mv_addr_end) {
3687 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3688 "Error, colocate buf is not enough, col buf index is %d\n",
3689 colocate_buf_index);
3690 ret = -8;
3691 }
3692 /* bit 31:30 -- L1[0] picture coding structure,
3693 * 00 - top field, 01 - bottom field,
3694 * 10 - frame, 11 - mbaff frame
3695 * bit 29 - L1[0] top/bot for B field pciture,
3696 * 0 - top, 1 - bot
3697 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3698 * -- only used for B Picture Direct mode
3699 * [2:0] will set to 3'b000
3700 */
3701 /* #define H264_CO_MB_RD_ADDR VLD_C39 0xc39 */
3702 val = ((colocate_rd_adr+colocate_adr_offset)>>3) |
3703 (l10_structure << 30) | (cur_colocate_ref_type << 29);
3704 WRITE_VREG(H264_CO_MB_RD_ADDR, val);
3705 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3706 "WRITE_VREG(H264_CO_MB_RD_ADDR) = %x, L1(0) pic_structure %d mbaff %d\n",
3707 val, colocate_pic->structure,
3708 colocate_pic->mb_aff_frame_flag);
3709#endif
3710 }
3711 return ret;
3712}
3713
3714static int vh264_vf_states(struct vframe_states *states, void *op_arg)
3715{
3716 unsigned long flags;
3717 struct vdec_s *vdec = op_arg;
3718 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3719
3720 spin_lock_irqsave(&hw->lock, flags);
3721
3722 states->vf_pool_size = VF_POOL_SIZE;
3723 states->buf_free_num = kfifo_len(&hw->newframe_q);
3724 states->buf_avail_num = kfifo_len(&hw->display_q);
3725
3726 spin_unlock_irqrestore(&hw->lock, flags);
3727
3728 return 0;
3729}
3730
3731static struct vframe_s *vh264_vf_peek(void *op_arg)
3732{
3733 struct vframe_s *vf[2] = {0, 0};
3734 struct vdec_s *vdec = op_arg;
3735 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3736
3737 if (!hw)
3738 return NULL;
3739
3740 if (force_disp_bufspec_num & 0x100) {
3741 if (force_disp_bufspec_num & 0x200)
3742 return NULL;
3743 return &hw->vframe_dummy;
3744 }
3745
3746 if (kfifo_out_peek(&hw->display_q, (void *)&vf, 2)) {
3747 if (vf[1]) {
3748 vf[0]->next_vf_pts_valid = true;
3749 vf[0]->next_vf_pts = vf[1]->pts;
3750 } else
3751 vf[0]->next_vf_pts_valid = false;
3752 return vf[0];
3753 }
3754
3755 return NULL;
3756}
3757
3758static struct vframe_s *vh264_vf_get(void *op_arg)
3759{
3760 struct vframe_s *vf;
3761 struct vdec_s *vdec = op_arg;
3762 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3763
3764 if (!hw)
3765 return NULL;
3766
3767 if (force_disp_bufspec_num & 0x100) {
3768 int buffer_index = force_disp_bufspec_num & 0xff;
3769 if (force_disp_bufspec_num & 0x200)
3770 return NULL;
3771
3772 vf = &hw->vframe_dummy;
3773 vf->duration_pulldown = 0;
3774 vf->pts = 0;
3775 vf->pts_us64 = 0;
3776 set_frame_info(hw, vf, buffer_index);
3777 vf->flag = 0;
3778 if (hw->mmu_enable) {
3779 if (hw->double_write_mode & 0x10) {
3780 /* double write only */
3781 vf->compBodyAddr = 0;
3782 vf->compHeadAddr = 0;
3783 } else {
3784 /*head adr*/
3785 vf->compHeadAddr =
3786 hw->buffer_spec[buffer_index].alloc_header_addr;
3787 /*body adr*/
3788 vf->compBodyAddr = 0;
3789 vf->canvas0Addr = vf->canvas1Addr = 0;
3790 }
3791
3792 vf->type = VIDTYPE_SCATTER;
3793
3794 if (hw->double_write_mode) {
3795 vf->type |= VIDTYPE_PROGRESSIVE
3796 | VIDTYPE_VIU_FIELD;
3797 vf->type |= VIDTYPE_VIU_NV21;
3798 if (hw->double_write_mode == 3)
3799 vf->type |= VIDTYPE_COMPRESS;
3800
3801 vf->canvas0Addr = vf->canvas1Addr = -1;
3802 vf->plane_num = 2;
3803 vf->canvas0_config[0] =
3804 hw->buffer_spec[buffer_index].
3805 canvas_config[0];
3806 vf->canvas0_config[1] =
3807 hw->buffer_spec[buffer_index].
3808 canvas_config[1];
3809
3810 vf->canvas1_config[0] =
3811 hw->buffer_spec[buffer_index].
3812 canvas_config[0];
3813 vf->canvas1_config[1] =
3814 hw->buffer_spec[buffer_index].
3815 canvas_config[1];
3816 } else {
3817 vf->type |=
3818 VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
3819 vf->canvas0Addr = vf->canvas1Addr = 0;
3820 }
3821 vf->bitdepth =
3822 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
3823
3824 vf->compWidth = hw->frame_width;
3825 vf->compHeight = hw->frame_height;
3826
3827 if (hw->double_write_mode) {
3828 vf->width = hw->frame_width /
3829 get_double_write_ratio(hw);
3830 vf->height = hw->frame_height /
3831 get_double_write_ratio(hw);
3832 }
3833 } else {
3834 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD |
3835 VIDTYPE_VIU_NV21;
3836 vf->canvas0Addr = vf->canvas1Addr =
3837 spec2canvas(&hw->buffer_spec[buffer_index]);
3838 }
3839
3840 /*vf->mem_handle = decoder_bmmu_box_get_mem_handle(
3841 hw->bmmu_box, buffer_index);*/
3842 update_vf_memhandle(hw, vf, buffer_index);
3843 force_disp_bufspec_num |= 0x200;
3844 return vf;
3845 }
3846
3847 if (kfifo_get(&hw->display_q, &vf)) {
3848 int time = jiffies;
3849 unsigned int frame_interval =
3850 1000*(time - hw->last_frame_time)/HZ;
3851 struct vframe_s *next_vf;
3852 if (dpb_is_debug(DECODE_ID(hw),
3853 PRINT_FLAG_VDEC_DETAIL)) {
3854 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3855 int frame_index = FRAME_INDEX(vf->index);
3856 if (frame_index < 0 ||
3857 frame_index >= DPB_SIZE_MAX) {
3858 dpb_print(DECODE_ID(hw), 0,
3859 "%s vf index 0x%x error\r\n",
3860 __func__, vf->index);
3861 } else {
3862 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
3863 "%s buf_spec_num %d vf %p poc %d dur %d pts %d interval %dms\n",
3864 __func__, BUFSPEC_INDEX(vf->index), vf,
3865 p_H264_Dpb->mFrameStore[frame_index].poc,
3866 vf->duration, vf->pts, frame_interval);
3867 }
3868 }
3869 if (hw->last_frame_time > 0) {
3870 if (frame_interval >
3871 max_get_frame_interval[DECODE_ID(hw)])
3872 max_get_frame_interval[DECODE_ID(hw)]
3873 = frame_interval;
3874 }
3875 hw->last_frame_time = time;
3876 vf->index_disp = hw->vf_get_count;
3877 hw->vf_get_count++;
3878 if (kfifo_peek(&hw->display_q, &next_vf)) {
3879 vf->next_vf_pts_valid = true;
3880 vf->next_vf_pts = next_vf->pts;
3881 } else
3882 vf->next_vf_pts_valid = false;
3883 return vf;
3884 }
3885
3886 return NULL;
3887}
3888
3889static void vh264_vf_put(struct vframe_s *vf, void *op_arg)
3890{
3891 struct vdec_s *vdec = op_arg;
3892 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3893 unsigned long flags;
3894 int buf_spec_num;
3895 int frame_index;
3896
3897 if (vf == (&hw->vframe_dummy))
3898 return;
3899 if (vf->index == -1) {
3900 dpb_print(DECODE_ID(hw), 0,
3901 "Warning: %s vf %p invalid index\r\n",
3902 __func__, vf);
3903 return;
3904 }
3905 frame_index = FRAME_INDEX(vf->index);
3906 buf_spec_num = BUFSPEC_INDEX(vf->index);
3907 if (frame_index < 0 ||
3908 frame_index >= DPB_SIZE_MAX ||
3909 buf_spec_num < 0 ||
3910 buf_spec_num >= BUFSPEC_POOL_SIZE) {
3911 dpb_print(DECODE_ID(hw), 0,
3912 "%s vf index 0x%x error\r\n",
3913 __func__, vf->index);
3914 return;
3915 }
3916 /*get_buf_spec_idx_by_canvas_config(hw,
3917 &vf->canvas0_config[0]);*/
3918 spin_lock_irqsave(&hw->bufspec_lock, flags);
3919 if (hw->buffer_spec[buf_spec_num].used == 2) {
3920 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3921 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3922 "%s %p to fs[%d], poc %d buf_spec_num %d used %d vf_ref %d\n",
3923 __func__, vf, frame_index,
3924 p_H264_Dpb->mFrameStore[frame_index].poc,
3925 buf_spec_num,
3926 hw->buffer_spec[buf_spec_num].used,
3927 hw->buffer_spec[buf_spec_num].vf_ref);
3928 hw->buffer_spec[buf_spec_num].vf_ref--;
3929 if (hw->buffer_spec[buf_spec_num].vf_ref <= 0)
3930 set_frame_output_flag(&hw->dpb, frame_index);
3931 } else {
3932 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3933 "%s %p isolated vf, buf_spec_num %d used %d vf_ref %d\n",
3934 __func__, vf, buf_spec_num,
3935 hw->buffer_spec[buf_spec_num].used,
3936 hw->buffer_spec[buf_spec_num].vf_ref);
3937 hw->buffer_spec[buf_spec_num].vf_ref--;
3938 if (hw->buffer_spec[buf_spec_num].vf_ref <= 0) {
3939 if (hw->buffer_spec[buf_spec_num].used == 3)
3940 hw->buffer_spec[buf_spec_num].used = 4;
3941 else if (hw->buffer_spec[buf_spec_num].used == 5)
3942 hw->buffer_spec[buf_spec_num].used = 0;
3943 }
3944 if (dpb_is_debug(DECODE_ID(hw),
3945 PRINT_FLAG_DUMP_BUFSPEC))
3946 dump_bufspec(hw, __func__);
3947
3948 }
3949 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
3950
3951 hw->vf_put_count++;
3952 kfifo_put(&hw->newframe_q, (const struct vframe_s *)vf);
3953
3954#define ASSIST_MBOX1_IRQ_REG VDEC_ASSIST_MBOX1_IRQ_REG
3955 if (hw->buffer_empty_flag)
3956 WRITE_VREG(ASSIST_MBOX1_IRQ_REG, 0x1);
3957}
3958
3959static int vh264_event_cb(int type, void *data, void *op_arg)
3960{
3961 unsigned long flags;
3962 struct vdec_s *vdec = op_arg;
3963 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3964
3965 if (type & VFRAME_EVENT_RECEIVER_GET_AUX_DATA) {
3966 struct provider_aux_req_s *req =
3967 (struct provider_aux_req_s *)data;
3968 int buf_spec_num;
3969
3970 if (!req->vf) {
3971 req->aux_size = hw->vf_put_count;
3972 return 0;
3973 }
3974 buf_spec_num = BUFSPEC_INDEX(req->vf->index);
3975 spin_lock_irqsave(&hw->lock, flags);
3976 req->aux_buf = NULL;
3977 req->aux_size = 0;
3978 if (buf_spec_num >= 0 &&
3979 buf_spec_num < BUFSPEC_POOL_SIZE &&
3980 is_buf_spec_in_disp_q(hw, buf_spec_num)
3981 ) {
3982 req->aux_buf =
3983 hw->buffer_spec[buf_spec_num].aux_data_buf;
3984 req->aux_size =
3985 hw->buffer_spec[buf_spec_num].aux_data_size;
3986#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3987 req->dv_enhance_exist =
3988 hw->buffer_spec[buf_spec_num].dv_enhance_exist;
3989#else
3990 req->dv_enhance_exist = 0;
3991#endif
3992 }
3993 spin_unlock_irqrestore(&hw->lock, flags);
3994
3995 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3996 "%s(type 0x%x vf buf_spec_num 0x%x)=>size 0x%x\n",
3997 __func__, type, buf_spec_num, req->aux_size);
3998 }
3999
4000 return 0;
4001}
4002
4003static void set_frame_info(struct vdec_h264_hw_s *hw, struct vframe_s *vf,
4004 u32 index)
4005{
4006 struct canvas_config_s *p_canvas_config;
4007 int force_rate = input_frame_based(hw_to_vdec(hw)) ?
4008 force_rate_framebase : force_rate_streambase;
4009 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
4010 "%s (%d,%d) dur %d, vf %p, index %d\n", __func__,
4011 hw->frame_width, hw->frame_height, hw->frame_dur, vf, index);
4012
4013 /* signal_type */
4014 if (hw->video_signal_from_vui & VIDEO_SIGNAL_TYPE_AVAILABLE_MASK) {
4015 vf->signal_type = hw->video_signal_from_vui;
4016 if (hw->is_used_v4l) {
4017 struct aml_vdec_hdr_infos hdr;
4018 struct aml_vcodec_ctx *ctx =
4019 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
4020
4021 memset(&hdr, 0, sizeof(hdr));
4022 hdr.signal_type = hw->video_signal_from_vui;
4023 vdec_v4l_set_hdr_infos(ctx, &hdr);
4024 }
4025 } else
4026 vf->signal_type = 0;
4027
4028 vf->width = hw->frame_width;
4029 vf->height = hw->frame_height;
4030 if (force_rate) {
4031 if (force_rate == -1)
4032 vf->duration = 0;
4033 else
4034 vf->duration = 96000/force_rate;
4035 } else
4036 vf->duration = hw->frame_dur;
4037 vf->ratio_control =
4038 (min(hw->h264_ar, (u32) DISP_RATIO_ASPECT_RATIO_MAX)) <<
4039 DISP_RATIO_ASPECT_RATIO_BIT;
4040 vf->orientation = hw->vh264_rotation;
4041
4042 if (hw->mmu_enable)
4043 return;
4044
4045 vf->canvas0Addr = vf->canvas1Addr = -1;
4046#ifdef NV21
4047 vf->plane_num = 2;
4048#else
4049 vf->plane_num = 3;
4050#endif
4051
4052 if (IS_VDEC_DW(hw)) {
4053 vf->width = (hw->frame_width /2);
4054 if (IS_VDEC_DW(hw) == 2)
4055 vf->height = (hw->frame_height /2);
4056 p_canvas_config = &hw->buffer_spec[index].vdec_dw_canvas_config[0];
4057 } else
4058 p_canvas_config = &hw->buffer_spec[index].canvas_config[0];
4059
4060 vf->canvas0_config[0] = p_canvas_config[0];
4061 vf->canvas0_config[1] = p_canvas_config[1];
4062#ifndef NV21
4063 vf->canvas0_config[2] = p_canvas_config[2];
4064#endif
4065 vf->canvas1_config[0] = p_canvas_config[0];
4066 vf->canvas1_config[1] = p_canvas_config[1];
4067#ifndef NV21
4068 vf->canvas1_config[2] = p_canvas_config[2];
4069#endif
4070}
4071
4072static void get_picture_qos_info(struct StorablePicture *picture)
4073{
4074 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
4075 unsigned char a[3];
4076 unsigned char i, j, t;
4077 unsigned long data;
4078
4079 get_random_bytes(&data, sizeof(unsigned long));
4080 if (picture->slice_type == I_SLICE)
4081 data = 0;
4082 a[0] = data & 0xff;
4083 a[1] = (data >> 8) & 0xff;
4084 a[2] = (data >> 16) & 0xff;
4085
4086 for (i = 0; i < 3; i++)
4087 for (j = i+1; j < 3; j++) {
4088 if (a[j] < a[i]) {
4089 t = a[j];
4090 a[j] = a[i];
4091 a[i] = t;
4092 } else if (a[j] == a[i]) {
4093 a[i]++;
4094 t = a[j];
4095 a[j] = a[i];
4096 a[i] = t;
4097 }
4098 }
4099 picture->max_mv = a[2];
4100 picture->avg_mv = a[1];
4101 picture->min_mv = a[0];
4102 /*
4103 pr_info("mv data %x a[0]= %x a[1]= %x a[2]= %x\n",
4104 data, a[0], a[1], a[2]);
4105 */
4106
4107 get_random_bytes(&data, sizeof(unsigned long));
4108 a[0] = data & 0x1f;
4109 a[1] = (data >> 8) & 0x3f;
4110 a[2] = (data >> 16) & 0x7f;
4111
4112 for (i = 0; i < 3; i++)
4113 for (j = i+1; j < 3; j++) {
4114 if (a[j] < a[i]) {
4115 t = a[j];
4116 a[j] = a[i];
4117 a[i] = t;
4118 } else if (a[j] == a[i]) {
4119 a[i]++;
4120 t = a[j];
4121 a[j] = a[i];
4122 a[i] = t;
4123 }
4124 }
4125 picture->max_qp = a[2];
4126 picture->avg_qp = a[1];
4127 picture->min_qp = a[0];
4128 /*
4129 pr_info("qp data %x a[0]= %x a[1]= %x a[2]= %x\n",
4130 data, a[0], a[1], a[2]);
4131 */
4132
4133 get_random_bytes(&data, sizeof(unsigned long));
4134 a[0] = data & 0x1f;
4135 a[1] = (data >> 8) & 0x3f;
4136 a[2] = (data >> 16) & 0x7f;
4137
4138 for (i = 0; i < 3; i++)
4139 for (j = i+1; j < 3; j++) {
4140 if (a[j] < a[i]) {
4141 t = a[j];
4142 a[j] = a[i];
4143 a[i] = t;
4144 } else if (a[j] == a[i]) {
4145 a[i]++;
4146 t = a[j];
4147 a[j] = a[i];
4148 a[i] = t;
4149 }
4150 }
4151 picture->max_skip = a[2];
4152 picture->avg_skip = a[1];
4153 picture->min_skip = a[0];
4154
4155
4156 /*
4157 pr_info("skip data %x a[0]= %x a[1]= %x a[2]= %x\n",
4158 data,a[0], a[1], a[2]);
4159 */
4160 } else {
4161 uint32_t blk88_y_count;
4162 uint32_t blk88_c_count;
4163 uint32_t blk22_mv_count;
4164 uint32_t rdata32;
4165 int32_t mv_hi;
4166 int32_t mv_lo;
4167 uint32_t rdata32_l;
4168 uint32_t mvx_L0_hi;
4169 uint32_t mvy_L0_hi;
4170 uint32_t mvx_L1_hi;
4171 uint32_t mvy_L1_hi;
4172 int64_t value;
4173 uint64_t temp_value;
4174/*
4175#define DEBUG_QOS
4176*/
4177#ifdef DEBUG_QOS
4178 int pic_number = picture->poc;
4179#endif
4180
4181 picture->max_mv = 0;
4182 picture->avg_mv = 0;
4183 picture->min_mv = 0;
4184
4185 picture->max_skip = 0;
4186 picture->avg_skip = 0;
4187 picture->min_skip = 0;
4188
4189 picture->max_qp = 0;
4190 picture->avg_qp = 0;
4191 picture->min_qp = 0;
4192
4193
4194
4195
4196
4197 /* set rd_idx to 0 */
4198 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, 0);
4199 blk88_y_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4200 if (blk88_y_count == 0) {
4201#ifdef DEBUG_QOS
4202 pr_info(" [Picture %d Quality] NO Data yet.\n",
4203 pic_number);
4204#endif
4205 /* reset all counts */
4206 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4207 return;
4208 }
4209 /* qp_y_sum */
4210 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4211#ifdef DEBUG_QOS
4212 pr_info(" [Picture %d Quality] Y QP AVG : %d (%d/%d)\n",
4213 pic_number, rdata32/blk88_y_count,
4214 rdata32, blk88_y_count);
4215#endif
4216 picture->avg_qp = rdata32/blk88_y_count;
4217 /* intra_y_count */
4218 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4219#ifdef DEBUG_QOS
4220 pr_info(" [Picture %d Quality] Y intra rate : %d%c (%d)\n",
4221 pic_number, rdata32*100/blk88_y_count,
4222 '%', rdata32);
4223#endif
4224 /* skipped_y_count */
4225 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4226#ifdef DEBUG_QOS
4227 pr_info(" [Picture %d Quality] Y skipped rate : %d%c (%d)\n",
4228 pic_number, rdata32*100/blk88_y_count,
4229 '%', rdata32);
4230#endif
4231 picture->avg_skip = rdata32*100/blk88_y_count;
4232 /* coeff_non_zero_y_count */
4233 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4234#ifdef DEBUG_QOS
4235 pr_info(" [Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n",
4236 pic_number, (100 - rdata32*100/(blk88_y_count*1)),
4237 '%', rdata32);
4238#endif
4239 /* blk66_c_count */
4240 blk88_c_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4241 if (blk88_c_count == 0) {
4242#ifdef DEBUG_QOS
4243 pr_info(" [Picture %d Quality] NO Data yet.\n",
4244 pic_number);
4245#endif
4246 /* reset all counts */
4247 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4248 return;
4249 }
4250 /* qp_c_sum */
4251 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4252#ifdef DEBUG_QOS
4253 pr_info(" [Picture %d Quality] C QP AVG : %d (%d/%d)\n",
4254 pic_number, rdata32/blk88_c_count,
4255 rdata32, blk88_c_count);
4256#endif
4257 /* intra_c_count */
4258 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4259#ifdef DEBUG_QOS
4260 pr_info(" [Picture %d Quality] C intra rate : %d%c (%d)\n",
4261 pic_number, rdata32*100/blk88_c_count,
4262 '%', rdata32);
4263#endif
4264 /* skipped_cu_c_count */
4265 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4266#ifdef DEBUG_QOS
4267 pr_info(" [Picture %d Quality] C skipped rate : %d%c (%d)\n",
4268 pic_number, rdata32*100/blk88_c_count,
4269 '%', rdata32);
4270#endif
4271 /* coeff_non_zero_c_count */
4272 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4273#ifdef DEBUG_QOS
4274 pr_info(" [Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n",
4275 pic_number, (100 - rdata32*100/(blk88_c_count*1)),
4276 '%', rdata32);
4277#endif
4278
4279 /* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0],
4280 1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */
4281 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4282#ifdef DEBUG_QOS
4283 pr_info(" [Picture %d Quality] Y QP min : %d\n",
4284 pic_number, (rdata32>>0)&0xff);
4285#endif
4286 picture->min_qp = (rdata32>>0)&0xff;
4287
4288#ifdef DEBUG_QOS
4289 pr_info(" [Picture %d Quality] Y QP max : %d\n",
4290 pic_number, (rdata32>>8)&0xff);
4291#endif
4292 picture->max_qp = (rdata32>>8)&0xff;
4293
4294#ifdef DEBUG_QOS
4295 pr_info(" [Picture %d Quality] C QP min : %d\n",
4296 pic_number, (rdata32>>16)&0xff);
4297 pr_info(" [Picture %d Quality] C QP max : %d\n",
4298 pic_number, (rdata32>>24)&0xff);
4299#endif
4300
4301 /* blk22_mv_count */
4302 blk22_mv_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4303 if (blk22_mv_count == 0) {
4304#ifdef DEBUG_QOS
4305 pr_info(" [Picture %d Quality] NO MV Data yet.\n",
4306 pic_number);
4307#endif
4308 /* reset all counts */
4309 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4310 return;
4311 }
4312 /* mvy_L1_count[39:32], mvx_L1_count[39:32],
4313 mvy_L0_count[39:32], mvx_L0_count[39:32] */
4314 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4315 /* should all be 0x00 or 0xff */
4316#ifdef DEBUG_QOS
4317 pr_info(" [Picture %d Quality] MV AVG High Bits: 0x%X\n",
4318 pic_number, rdata32);
4319#endif
4320 mvx_L0_hi = ((rdata32>>0)&0xff);
4321 mvy_L0_hi = ((rdata32>>8)&0xff);
4322 mvx_L1_hi = ((rdata32>>16)&0xff);
4323 mvy_L1_hi = ((rdata32>>24)&0xff);
4324
4325 /* mvx_L0_count[31:0] */
4326 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4327 temp_value = mvx_L0_hi;
4328 temp_value = (temp_value << 32) | rdata32_l;
4329
4330 if (mvx_L0_hi & 0x80)
4331 value = 0xFFFFFFF000000000 | temp_value;
4332 else
4333 value = temp_value;
4334 value = div_s64(value, blk22_mv_count);
4335#ifdef DEBUG_QOS
4336 pr_info(" [Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n",
4337 pic_number, (int)(value),
4338 value, blk22_mv_count);
4339#endif
4340 picture->avg_mv = value;
4341
4342 /* mvy_L0_count[31:0] */
4343 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4344 temp_value = mvy_L0_hi;
4345 temp_value = (temp_value << 32) | rdata32_l;
4346
4347 if (mvy_L0_hi & 0x80)
4348 value = 0xFFFFFFF000000000 | temp_value;
4349 else
4350 value = temp_value;
4351#ifdef DEBUG_QOS
4352 pr_info(" [Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n",
4353 pic_number, rdata32_l/blk22_mv_count,
4354 value, blk22_mv_count);
4355#endif
4356
4357 /* mvx_L1_count[31:0] */
4358 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4359 temp_value = mvx_L1_hi;
4360 temp_value = (temp_value << 32) | rdata32_l;
4361 if (mvx_L1_hi & 0x80)
4362 value = 0xFFFFFFF000000000 | temp_value;
4363 else
4364 value = temp_value;
4365#ifdef DEBUG_QOS
4366 pr_info(" [Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n",
4367 pic_number, rdata32_l/blk22_mv_count,
4368 value, blk22_mv_count);
4369#endif
4370
4371 /* mvy_L1_count[31:0] */
4372 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4373 temp_value = mvy_L1_hi;
4374 temp_value = (temp_value << 32) | rdata32_l;
4375 if (mvy_L1_hi & 0x80)
4376 value = 0xFFFFFFF000000000 | temp_value;
4377 else
4378 value = temp_value;
4379#ifdef DEBUG_QOS
4380 pr_info(" [Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n",
4381 pic_number, rdata32_l/blk22_mv_count,
4382 value, blk22_mv_count);
4383#endif
4384
4385 /* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */
4386 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4387 mv_hi = (rdata32>>16)&0xffff;
4388 if (mv_hi & 0x8000)
4389 mv_hi = 0x8000 - mv_hi;
4390#ifdef DEBUG_QOS
4391 pr_info(" [Picture %d Quality] MVX_L0 MAX : %d\n",
4392 pic_number, mv_hi);
4393#endif
4394 picture->max_mv = mv_hi;
4395
4396 mv_lo = (rdata32>>0)&0xffff;
4397 if (mv_lo & 0x8000)
4398 mv_lo = 0x8000 - mv_lo;
4399#ifdef DEBUG_QOS
4400 pr_info(" [Picture %d Quality] MVX_L0 MIN : %d\n",
4401 pic_number, mv_lo);
4402#endif
4403 picture->min_mv = mv_lo;
4404
4405 /* {mvy_L0_max, mvy_L0_min} */
4406 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4407 mv_hi = (rdata32>>16)&0xffff;
4408 if (mv_hi & 0x8000)
4409 mv_hi = 0x8000 - mv_hi;
4410#ifdef DEBUG_QOS
4411 pr_info(" [Picture %d Quality] MVY_L0 MAX : %d\n",
4412 pic_number, mv_hi);
4413#endif
4414
4415 mv_lo = (rdata32>>0)&0xffff;
4416 if (mv_lo & 0x8000)
4417 mv_lo = 0x8000 - mv_lo;
4418#ifdef DEBUG_QOS
4419 pr_info(" [Picture %d Quality] MVY_L0 MIN : %d\n",
4420 pic_number, mv_lo);
4421#endif
4422
4423 /* {mvx_L1_max, mvx_L1_min} */
4424 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4425 mv_hi = (rdata32>>16)&0xffff;
4426 if (mv_hi & 0x8000)
4427 mv_hi = 0x8000 - mv_hi;
4428#ifdef DEBUG_QOS
4429 pr_info(" [Picture %d Quality] MVX_L1 MAX : %d\n",
4430 pic_number, mv_hi);
4431#endif
4432
4433 mv_lo = (rdata32>>0)&0xffff;
4434 if (mv_lo & 0x8000)
4435 mv_lo = 0x8000 - mv_lo;
4436#ifdef DEBUG_QOS
4437 pr_info(" [Picture %d Quality] MVX_L1 MIN : %d\n",
4438 pic_number, mv_lo);
4439#endif
4440
4441 /* {mvy_L1_max, mvy_L1_min} */
4442 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4443 mv_hi = (rdata32>>16)&0xffff;
4444 if (mv_hi & 0x8000)
4445 mv_hi = 0x8000 - mv_hi;
4446#ifdef DEBUG_QOS
4447 pr_info(" [Picture %d Quality] MVY_L1 MAX : %d\n",
4448 pic_number, mv_hi);
4449#endif
4450 mv_lo = (rdata32>>0)&0xffff;
4451 if (mv_lo & 0x8000)
4452 mv_lo = 0x8000 - mv_lo;
4453#ifdef DEBUG_QOS
4454 pr_info(" [Picture %d Quality] MVY_L1 MIN : %d\n",
4455 pic_number, mv_lo);
4456#endif
4457
4458 rdata32 = READ_VREG(VDEC_PIC_QUALITY_CTRL);
4459#ifdef DEBUG_QOS
4460 pr_info(" [Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n",
4461 pic_number, rdata32);
4462#endif
4463 /* reset all counts */
4464 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4465 }
4466}
4467
4468static int get_max_dec_frame_buf_size(int level_idc,
4469 int max_reference_frame_num, int mb_width,
4470 int mb_height)
4471{
4472 int pic_size = mb_width * mb_height * 384;
4473
4474 int size = 0;
4475
4476 switch (level_idc) {
4477 case 9:
4478 size = 152064;
4479 break;
4480 case 10:
4481 size = 152064;
4482 break;
4483 case 11:
4484 size = 345600;
4485 break;
4486 case 12:
4487 size = 912384;
4488 break;
4489 case 13:
4490 size = 912384;
4491 break;
4492 case 20:
4493 size = 912384;
4494 break;
4495 case 21:
4496 size = 1824768;
4497 break;
4498 case 22:
4499 size = 3110400;
4500 break;
4501 case 30:
4502 size = 3110400;
4503 break;
4504 case 31:
4505 size = 6912000;
4506 break;
4507 case 32:
4508 size = 7864320;
4509 break;
4510 case 40:
4511 size = 12582912;
4512 break;
4513 case 41:
4514 size = 12582912;
4515 break;
4516 case 42:
4517 size = 13369344;
4518 break;
4519 case 50:
4520 size = 42393600;
4521 break;
4522 case 51:
4523 case 52:
4524 default:
4525 size = 70778880;
4526 break;
4527 }
4528
4529 size /= pic_size;
4530 size = size + 1; /* need one more buffer */
4531
4532 if (max_reference_frame_num > size)
4533 size = max_reference_frame_num;
4534 size = imin(size, 16);
4535
4536 return size;
4537}
4538
4539static void vh264_config_canvs_for_mmu(struct vdec_h264_hw_s *hw)
4540{
4541 int i, j;
4542
4543 if (hw->double_write_mode) {
4544 mutex_lock(&vmh264_mutex);
4545 if (hw->decode_pic_count == 0) {
4546 for (j = 0; j < hw->dpb.mDPB.size; j++) {
4547 i = get_buf_spec_by_canvas_pos(hw, j);
4548 if (i >= 0)
4549 config_decode_canvas_ex(hw, i);
4550 }
4551 }
4552 mutex_unlock(&vmh264_mutex);
4553 }
4554}
4555
4556static int vh264_set_params(struct vdec_h264_hw_s *hw,
4557 u32 param1, u32 param2, u32 param3, u32 param4)
4558{
4559 int i, j;
4560 int mb_width, mb_total;
4561 int max_reference_size, level_idc;
4562 int mb_height = 0;
4563 unsigned long flags;
4564 /*int mb_mv_byte;*/
4565 struct vdec_s *vdec = hw_to_vdec(hw);
4566 u32 seq_info2;
4567 int ret = 0;
4568 int active_buffer_spec_num;
4569 unsigned int buf_size;
4570 unsigned int frame_mbs_only_flag;
4571 unsigned int chroma_format_idc, chroma444;
4572 unsigned int crop_infor, crop_bottom, crop_right;
4573 unsigned int used_reorder_dpb_size_margin
4574 = hw->reorder_dpb_size_margin;
4575 u8 *colocate_vaddr = NULL;
4576
4577#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
4578 if (vdec->master || vdec->slave)
4579 used_reorder_dpb_size_margin =
4580 reorder_dpb_size_margin_dv;
4581#endif
4582 seq_info2 = param1;
4583 hw->seq_info = param2;
4584
4585 mb_width = seq_info2 & 0xff;
4586 mb_total = (seq_info2 >> 8) & 0xffff;
4587 if (!mb_width && mb_total) /*for 4k2k*/
4588 mb_width = 256;
4589 if (mb_width)
4590 mb_height = mb_total/mb_width;
4591 if (mb_width <= 0 || mb_height <= 0 ||
4592 is_oversize(mb_width << 4, mb_height << 4)) {
4593 dpb_print(DECODE_ID(hw), 0,
4594 "!!!wrong seq_info2 0x%x mb_width/mb_height (0x%x/0x%x) %x\r\n",
4595 seq_info2,
4596 mb_width,
4597 mb_height);
4598 return -1;
4599 }
4600
4601 if (seq_info2 != 0 &&
4602 hw->seq_info2 != (seq_info2 & (~0x80000000)) &&
4603 hw->seq_info2 != 0
4604 ) /*picture size changed*/
4605 h264_reconfig(hw);
4606
4607 if (hw->config_bufmgr_done == 0) {
4608 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4609 u32 reg_val;
4610 hw->cfg_param1 = param1;
4611 hw->cfg_param2 = param2;
4612 hw->cfg_param3 = param3;
4613 hw->cfg_param4 = param4;
4614
4615 hw->seq_info2 = seq_info2 & (~0x80000000);
4616 dpb_print(DECODE_ID(hw), 0,
4617 "AV_SCRATCH_1 = %x, AV_SCRATCH_2 %x\r\n",
4618 seq_info2, hw->seq_info);
4619
4620 dpb_init_global(&hw->dpb,
4621 DECODE_ID(hw), 0, 0);
4622
4623 p_H264_Dpb->fast_output_enable = fast_output_enable;
4624 /*mb_mv_byte = (seq_info2 & 0x80000000) ? 24 : 96;*/
4625
4626#if 1
4627 /*crop*/
4628 /* AV_SCRATCH_2
4629 bit 15: frame_mbs_only_flag
4630 bit 13-14: chroma_format_idc */
4631 frame_mbs_only_flag = (hw->seq_info >> 15) & 0x01;
4632 chroma_format_idc = (hw->seq_info >> 13) & 0x03;
4633 chroma444 = (chroma_format_idc == 3) ? 1 : 0;
4634
4635 /* @AV_SCRATCH_6.31-16 = (left << 8 | right ) << 1
4636 @AV_SCRATCH_6.15-0 = (top << 8 | bottom ) <<
4637 (2 - frame_mbs_only_flag) */
4638 crop_infor = param3;
4639 crop_bottom = (crop_infor & 0xff) >> (2 - frame_mbs_only_flag);
4640 crop_right = ((crop_infor >> 16) & 0xff)
4641 >> (2 - frame_mbs_only_flag);
4642
4643 p_H264_Dpb->mSPS.frame_mbs_only_flag = frame_mbs_only_flag;
4644 hw->frame_width = mb_width << 4;
4645 hw->frame_height = mb_height << 4;
4646 if (frame_mbs_only_flag) {
4647 hw->frame_height =
4648 hw->frame_height - (2 >> chroma444) *
4649 min(crop_bottom,
4650 (unsigned int)((8 << chroma444) - 1));
4651 hw->frame_width =
4652 hw->frame_width -
4653 (2 >> chroma444) * min(crop_right,
4654 (unsigned
4655 int)((8 << chroma444) - 1));
4656 } else {
4657 hw->frame_height =
4658 hw->frame_height - (4 >> chroma444) *
4659 min(crop_bottom,
4660 (unsigned int)((8 << chroma444)
4661 - 1));
4662 hw->frame_width =
4663 hw->frame_width -
4664 (4 >> chroma444) * min(crop_right,
4665 (unsigned int)((8 << chroma444) - 1));
4666 }
4667 dpb_print(DECODE_ID(hw), 0,
4668 "frame_mbs_only_flag %d, crop_bottom %d, frame_height %d,\n",
4669 frame_mbs_only_flag, crop_bottom, hw->frame_height);
4670 dpb_print(DECODE_ID(hw), 0,
4671 "mb_height %d,crop_right %d, frame_width %d, mb_width %d\n",
4672 mb_height, crop_right,
4673 hw->frame_width, mb_width);
4674
4675 if (hw->frame_height == 1088)
4676 hw->frame_height = 1080;
4677#endif
4678 if (!hw->mmu_enable) {
4679 mb_width = (mb_width+3) & 0xfffffffc;
4680 mb_height = (mb_height+3) & 0xfffffffc;
4681 }
4682 mb_total = mb_width * mb_height;
4683 hw->mb_width = mb_width;
4684 hw->mb_height = mb_height;
4685 hw->mb_total = mb_total;
4686 if (hw->mmu_enable)
4687 hevc_mcr_sao_global_hw_init(hw,
4688 (hw->mb_width << 4), (hw->mb_height << 4));
4689
4690 reg_val = param4;
4691 level_idc = reg_val & 0xff;
4692 max_reference_size = (reg_val >> 8) & 0xff;
4693 hw->dpb.origin_max_reference = max_reference_size;
4694 dpb_print(DECODE_ID(hw), 0,
4695 "mb height/widht/total: %x/%x/%x level_idc %x max_ref_num %x\n",
4696 mb_height, mb_width, mb_total,
4697 level_idc, max_reference_size);
4698
4699
4700 p_H264_Dpb->colocated_buf_size = mb_total * 96;
4701 hw->dpb.reorder_pic_num =
4702 get_max_dec_frame_buf_size(level_idc,
4703 max_reference_size, mb_width, mb_height);
4704
4705 dpb_print(DECODE_ID(hw), 0,
4706 "restriction_flag=%d, max_dec_frame_buffering=%d, reorder_pic_num=%d\n",
4707 hw->bitstream_restriction_flag,
4708 hw->max_dec_frame_buffering,
4709 hw->dpb.reorder_pic_num);
4710
4711 if ((hw->bitstream_restriction_flag) &&
4712 (hw->max_dec_frame_buffering <
4713 hw->dpb.reorder_pic_num)) {
4714 hw->dpb.reorder_pic_num = hw->max_dec_frame_buffering;
4715 dpb_print(DECODE_ID(hw), 0,
4716 "set reorder_pic_num to %d\n",
4717 hw->dpb.reorder_pic_num);
4718 }
4719
4720 active_buffer_spec_num =
4721 hw->dpb.reorder_pic_num
4722 + used_reorder_dpb_size_margin;
4723 hw->max_reference_size =
4724 max_reference_size + reference_buf_margin;
4725
4726 if (active_buffer_spec_num > MAX_VF_BUF_NUM) {
4727 active_buffer_spec_num = MAX_VF_BUF_NUM;
4728 hw->dpb.reorder_pic_num = active_buffer_spec_num
4729 - used_reorder_dpb_size_margin;
4730 }
4731 hw->dpb.mDPB.size = active_buffer_spec_num;
4732 if (hw->max_reference_size > MAX_VF_BUF_NUM)
4733 hw->max_reference_size = MAX_VF_BUF_NUM;
4734 hw->dpb.max_reference_size = hw->max_reference_size;
4735
4736 if (hw->no_poc_reorder_flag)
4737 hw->dpb.reorder_pic_num = 1;
4738 dpb_print(DECODE_ID(hw), 0,
4739 "%s active_buf_spec_num %d reorder_pic_num %d collocate_buf_num %d\r\n",
4740 __func__, active_buffer_spec_num,
4741 hw->dpb.reorder_pic_num,
4742 hw->max_reference_size);
4743
4744 buf_size = (hw->mb_total << 8) + (hw->mb_total << 7);
4745
4746 mutex_lock(&vmh264_mutex);
4747 if (!hw->mmu_enable) {
4748 config_buf_specs(vdec);
4749 i = get_buf_spec_by_canvas_pos(hw, 0);
4750
4751 if (hw->is_used_v4l) {
4752 if (i != -1) {
4753 pr_info("v4l: delay alloc the buffer.\n");
4754 }
4755 } else {
4756 if ((i != -1) && alloc_one_buf_spec(hw, i) >= 0)
4757 config_decode_canvas(hw, i);
4758 else
4759 ret = -1;
4760 }
4761 } else {
4762 if (hw->double_write_mode) {
4763 config_buf_specs_ex(vdec);
4764 } else {
4765 spin_lock_irqsave(&hw->bufspec_lock, flags);
4766 for (i = 0, j = 0;
4767 j < active_buffer_spec_num
4768 && i < BUFSPEC_POOL_SIZE;
4769 i++) {
4770 if (hw->buffer_spec[i].used != -1)
4771 continue;
4772 hw->buffer_spec[i].used = 0;
4773 hw->buffer_spec[i].
4774 alloc_header_addr = 0;
4775 hw->buffer_spec[i].canvas_pos = j;
4776 j++;
4777 }
4778 spin_unlock_irqrestore(&hw->bufspec_lock,
4779 flags);
4780 }
4781 hevc_mcr_config_canv2axitbl(hw, 0);
4782 }
4783 mutex_unlock(&vmh264_mutex);
4784 if (dpb_is_debug(DECODE_ID(hw),
4785 PRINT_FLAG_DUMP_BUFSPEC))
4786 dump_bufspec(hw, __func__);
4787
4788#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
4789 buf_size = PAGE_ALIGN(
4790 p_H264_Dpb->colocated_buf_size *
4791 active_buffer_spec_num);
4792#else
4793 buf_size = PAGE_ALIGN(
4794 p_H264_Dpb->colocated_buf_size *
4795 hw->max_reference_size);
4796#endif
4797
4798 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_REF_IDX,
4799 buf_size, DRIVER_NAME,
4800 &hw->collocate_cma_alloc_addr) < 0)
4801 return -1;
4802 if (!vdec_secure(vdec)) {
4803 /* clear for some mosaic problem after reset bufmgr */
4804 colocate_vaddr = codec_mm_vmap(hw->collocate_cma_alloc_addr, buf_size);
4805 if (colocate_vaddr != NULL) {
4806 memset(colocate_vaddr, 0, buf_size);
4807 codec_mm_dma_flush(colocate_vaddr, buf_size, DMA_TO_DEVICE);
4808 codec_mm_unmap_phyaddr(colocate_vaddr);
4809 }
4810 }
4811
4812 hw->dpb.colocated_mv_addr_start =
4813 hw->collocate_cma_alloc_addr;
4814#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
4815 hw->dpb.colocated_mv_addr_end =
4816 hw->dpb.colocated_mv_addr_start +
4817 (p_H264_Dpb->colocated_buf_size *
4818 active_buffer_spec_num);
4819#else
4820 hw->dpb.colocated_mv_addr_end =
4821 hw->dpb.colocated_mv_addr_start +
4822 (p_H264_Dpb->colocated_buf_size *
4823 hw->max_reference_size);
4824#endif
4825 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4826 "callocate cma, %lx, %x\n",
4827 hw->collocate_cma_alloc_addr,
4828 hw->dpb.colocated_mv_addr_start);
4829
4830 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4831 "colocated_mv_addr_start %x colocated_mv_addr_end %x\n",
4832 hw->dpb.colocated_mv_addr_start,
4833 hw->dpb.colocated_mv_addr_end);
4834 if (!hw->mmu_enable) {
4835 mutex_lock(&vmh264_mutex);
4836 if (ret >= 0 && hw->decode_pic_count == 0) {
4837 int buf_cnt;
4838 /* h264_reconfig: alloc later*/
4839 buf_cnt = hw->dpb.mDPB.size;
4840
4841 for (j = 1; j < buf_cnt; j++) {
4842 i = get_buf_spec_by_canvas_pos(hw, j);
4843
4844 if (hw->is_used_v4l) {
4845 pr_info("v4l: delay alloc the buffer.\n");
4846 break;
4847 } else if (alloc_one_buf_spec(hw, i) < 0)
4848 break;
4849
4850 config_decode_canvas(hw, i);
4851 }
4852 }
4853 mutex_unlock(&vmh264_mutex);
4854 } else {
4855 vh264_config_canvs_for_mmu(hw);
4856 }
4857
4858 hw->config_bufmgr_done = 1;
4859
4860 /*end of config_bufmgr_done */
4861 }
4862
4863 return ret;
4864}
4865
4866static void vui_config(struct vdec_h264_hw_s *hw)
4867{
4868 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4869 int aspect_ratio_info_present_flag, aspect_ratio_idc;
4870 /*time*/
4871 hw->num_units_in_tick = p_H264_Dpb->num_units_in_tick;
4872 hw->time_scale = p_H264_Dpb->time_scale;
4873 hw->timing_info_present_flag = p_H264_Dpb->vui_status & 0x2;
4874
4875 hw->bitstream_restriction_flag =
4876 p_H264_Dpb->bitstream_restriction_flag;
4877 hw->num_reorder_frames =
4878 p_H264_Dpb->num_reorder_frames;
4879 hw->max_dec_frame_buffering =
4880 p_H264_Dpb->max_dec_frame_buffering;
4881
4882 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
4883 "vui_config: pdb %d, %d, %d\n",
4884 p_H264_Dpb->bitstream_restriction_flag,
4885 p_H264_Dpb->num_reorder_frames,
4886 p_H264_Dpb->max_dec_frame_buffering);
4887
4888 hw->fixed_frame_rate_flag = 0;
4889 if (hw->timing_info_present_flag) {
4890 hw->fixed_frame_rate_flag =
4891 p_H264_Dpb->fixed_frame_rate_flag;
4892
4893 if (((hw->num_units_in_tick * 120) >= hw->time_scale &&
4894 ((!hw->sync_outside) ||
4895 (!hw->frame_dur)))
4896 && hw->num_units_in_tick && hw->time_scale) {
4897 if (hw->use_idr_framerate ||
4898 hw->fixed_frame_rate_flag ||
4899 !hw->frame_dur ||
4900 !hw->duration_from_pts_done
4901 /*|| vh264_running*/) {
4902 u32 frame_dur_es =
4903 div_u64(96000ULL * 2 * hw->num_units_in_tick,
4904 hw->time_scale);
4905 if (hw->frame_dur != frame_dur_es) {
4906 hw->h264_first_valid_pts_ready = false;
4907 hw->h264pts1 = 0;
4908 hw->h264pts2 = 0;
4909 hw->h264_pts_count = 0;
4910 hw->duration_from_pts_done = 0;
4911 fixed_frame_rate_mode =
4912 FIX_FRAME_RATE_OFF;
4913 hw->pts_duration = 0;
4914 hw->frame_dur = frame_dur_es;
4915 vdec_schedule_work(&hw->notify_work);
4916 dpb_print(DECODE_ID(hw),
4917 PRINT_FLAG_DEC_DETAIL,
4918 "frame_dur %d from timing_info\n",
4919 hw->frame_dur);
4920 }
4921
4922 /*hack to avoid use ES frame duration when
4923 *it's half of the rate from system info
4924 * sometimes the encoder is given a wrong
4925 * frame rate but the system side information
4926 * is more reliable
4927 *if ((frame_dur * 2) != frame_dur_es) {
4928 * frame_dur = frame_dur_es;
4929 *}
4930 */
4931 }
4932 }
4933 } else {
4934 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4935 "H.264: timing_info not present\n");
4936 }
4937
4938 /*aspect ratio*/
4939 aspect_ratio_info_present_flag =
4940 p_H264_Dpb->vui_status & 0x1;
4941 aspect_ratio_idc = p_H264_Dpb->aspect_ratio_idc;
4942
4943 if (aspect_ratio_info_present_flag) {
4944 if (aspect_ratio_idc == EXTEND_SAR) {
4945 hw->h264_ar = 0x3ff;
4946 hw->height_aspect_ratio =
4947 p_H264_Dpb->aspect_ratio_sar_height;
4948 hw->width_aspect_ratio =
4949 p_H264_Dpb->aspect_ratio_sar_width;
4950 } else {
4951 /* pr_info("v264dec: aspect_ratio_idc = %d\n",
4952 aspect_ratio_idc); */
4953
4954 switch (aspect_ratio_idc) {
4955 case 1:
4956 hw->h264_ar = 0x3ff;
4957 hw->height_aspect_ratio = 1;
4958 hw->width_aspect_ratio = 1;
4959 break;
4960 case 2:
4961 hw->h264_ar = 0x3ff;
4962 hw->height_aspect_ratio = 11;
4963 hw->width_aspect_ratio = 12;
4964 break;
4965 case 3:
4966 hw->h264_ar = 0x3ff;
4967 hw->height_aspect_ratio = 11;
4968 hw->width_aspect_ratio = 10;
4969 break;
4970 case 4:
4971 hw->h264_ar = 0x3ff;
4972 hw->height_aspect_ratio = 11;
4973 hw->width_aspect_ratio = 16;
4974 break;
4975 case 5:
4976 hw->h264_ar = 0x3ff;
4977 hw->height_aspect_ratio = 33;
4978 hw->width_aspect_ratio = 40;
4979 break;
4980 case 6:
4981 hw->h264_ar = 0x3ff;
4982 hw->height_aspect_ratio = 11;
4983 hw->width_aspect_ratio = 24;
4984 break;
4985 case 7:
4986 hw->h264_ar = 0x3ff;
4987 hw->height_aspect_ratio = 11;
4988 hw->width_aspect_ratio = 20;
4989 break;
4990 case 8:
4991 hw->h264_ar = 0x3ff;
4992 hw->height_aspect_ratio = 11;
4993 hw->width_aspect_ratio = 32;
4994 break;
4995 case 9:
4996 hw->h264_ar = 0x3ff;
4997 hw->height_aspect_ratio = 33;
4998 hw->width_aspect_ratio = 80;
4999 break;
5000 case 10:
5001 hw->h264_ar = 0x3ff;
5002 hw->height_aspect_ratio = 11;
5003 hw->width_aspect_ratio = 18;
5004 break;
5005 case 11:
5006 hw->h264_ar = 0x3ff;
5007 hw->height_aspect_ratio = 11;
5008 hw->width_aspect_ratio = 15;
5009 break;
5010 case 12:
5011 hw->h264_ar = 0x3ff;
5012 hw->height_aspect_ratio = 33;
5013 hw->width_aspect_ratio = 64;
5014 break;
5015 case 13:
5016 hw->h264_ar = 0x3ff;
5017 hw->height_aspect_ratio = 99;
5018 hw->width_aspect_ratio = 160;
5019 break;
5020 case 14:
5021 hw->h264_ar = 0x3ff;
5022 hw->height_aspect_ratio = 3;
5023 hw->width_aspect_ratio = 4;
5024 break;
5025 case 15:
5026 hw->h264_ar = 0x3ff;
5027 hw->height_aspect_ratio = 2;
5028 hw->width_aspect_ratio = 3;
5029 break;
5030 case 16:
5031 hw->h264_ar = 0x3ff;
5032 hw->height_aspect_ratio = 1;
5033 hw->width_aspect_ratio = 2;
5034 break;
5035 default:
5036 if (hw->vh264_ratio >> 16) {
5037 hw->h264_ar = (hw->frame_height *
5038 (hw->vh264_ratio & 0xffff) *
5039 0x100 +
5040 ((hw->vh264_ratio >> 16) *
5041 hw->frame_width / 2)) /
5042 ((hw->vh264_ratio >> 16) *
5043 hw->frame_width);
5044 hw->height_aspect_ratio = 1;
5045 hw->width_aspect_ratio = 1;
5046 } else {
5047 hw->h264_ar = 0x3ff;
5048 hw->height_aspect_ratio = 1;
5049 hw->width_aspect_ratio = 1;
5050 }
5051 break;
5052 }
5053 }
5054 } else {
5055 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
5056 "v264dec: aspect_ratio not available from source\n");
5057 if (hw->vh264_ratio >> 16) {
5058 /* high 16 bit is width, low 16 bit is height */
5059 hw->h264_ar =
5060 ((hw->vh264_ratio & 0xffff) *
5061 hw->frame_height * 0x100 +
5062 (hw->vh264_ratio >> 16) *
5063 hw->frame_width / 2) /
5064 ((hw->vh264_ratio >> 16) *
5065 hw->frame_width);
5066 hw->height_aspect_ratio = 1;
5067 hw->width_aspect_ratio = 1;
5068 } else {
5069 hw->h264_ar = 0x3ff;
5070 hw->height_aspect_ratio = 1;
5071 hw->width_aspect_ratio = 1;
5072 }
5073 }
5074
5075 if (hw->pts_unstable && (hw->fixed_frame_rate_flag == 0)) {
5076 if (((hw->frame_dur == RATE_2397_FPS)
5077 && (dec_control
5078 & DEC_CONTROL_FLAG_FORCE_RATE_2397_FPS_FIX_FRAME_RATE))
5079 || ((RATE_2997_FPS ==
5080 hw->frame_dur) &&
5081 (dec_control &
5082 DEC_CONTROL_FLAG_FORCE_RATE_2997_FPS_FIX_FRAME_RATE))) {
5083 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
5084 "force fix frame rate\n");
5085 hw->fixed_frame_rate_flag = 0x40;
5086 }
5087 }
5088
5089 /*video_signal_from_vui: to do .. */
5090}
5091
5092static void bufmgr_recover(struct vdec_h264_hw_s *hw)
5093{
5094 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5095
5096 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 2);
5097 if (error_proc_policy & 0x20) {
5098 if (!hw->is_used_v4l)
5099 hw->reset_bufmgr_flag = 1;
5100 }
5101}
5102
5103void bufmgr_force_recover(struct h264_dpb_stru *p_H264_Dpb)
5104{
5105 struct vdec_h264_hw_s *hw =
5106 container_of(p_H264_Dpb, struct vdec_h264_hw_s, dpb);
5107
5108 dpb_print(DECODE_ID(hw), 0, "call %s\n", __func__);
5109
5110 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 2);
5111 hw->reset_bufmgr_flag = 1;
5112}
5113
5114#ifdef CONSTRAIN_MAX_BUF_NUM
5115static int get_vf_ref_only_buf_count(struct vdec_h264_hw_s *hw)
5116{
5117 int i;
5118 int count = 0;
5119 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
5120 if (is_buf_spec_in_disp_q(hw, i) &&
5121 hw->buffer_spec[i].vf_ref > 0)
5122 count++;
5123 }
5124 return count;
5125}
5126
5127static int get_used_buf_count(struct vdec_h264_hw_s *hw)
5128{
5129 int i;
5130 int count = 0;
5131 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
5132 if (is_buf_spec_in_use(hw, i))
5133 count++;
5134 }
5135 return count;
5136}
5137#endif
5138
5139
5140static bool is_buffer_available(struct vdec_s *vdec)
5141{
5142 bool buffer_available = 1;
5143 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
5144 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5145 struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB;
5146 if ((kfifo_len(&hw->newframe_q) <= 0) ||
5147 ((hw->config_bufmgr_done) && (!have_free_buf_spec(vdec))) ||
5148 ((p_H264_Dpb->mDPB.init_done) &&
5149 (p_H264_Dpb->mDPB.used_size >= (p_H264_Dpb->mDPB.size -1)) &&
5150 (is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB) == 0))) {
5151 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
5152 "%s, empty, newq(%d), free_spec(%d), initdon(%d), used_size(%d/%d), unused_fr_dpb(%d)\n",
5153 __func__,
5154 kfifo_len(&hw->newframe_q),
5155 have_free_buf_spec(vdec),
5156 p_H264_Dpb->mDPB.init_done,
5157 p_H264_Dpb->mDPB.used_size, p_H264_Dpb->mDPB.size,
5158 is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB)
5159 );
5160 buffer_available = 0;
5161 if (dpb_is_debug(DECODE_ID(hw),
5162 DEBUG_DISABLE_RUNREADY_RMBUF))
5163 return buffer_available;
5164
5165 if ((error_proc_policy & 0x4) &&
5166 (error_proc_policy & 0x8)) {
5167 if ((kfifo_len(&hw->display_q) <= 0) &&
5168 (p_H264_Dpb->mDPB.used_size ==
5169 p_H264_Dpb->mDPB.size) &&
5170 (p_Dpb->ref_frames_in_buffer >
5171 (imax(
5172 1, p_Dpb->num_ref_frames)
5173 - p_Dpb->ltref_frames_in_buffer +
5174 force_sliding_margin)))
5175 bufmgr_recover(hw);
5176 else
5177 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5178 } else if ((error_proc_policy & 0x4) &&
5179 (kfifo_len(&hw->display_q) <= 0) &&
5180 ((p_H264_Dpb->mDPB.used_size ==
5181 p_H264_Dpb->mDPB.size) ||
5182 (!have_free_buf_spec(vdec)))) {
5183 enum receviver_start_e state = RECEIVER_INACTIVE;
5184 if ((error_proc_policy & 0x10) &&
5185 vf_get_receiver(vdec->vf_provider_name)) {
5186 state =
5187 vf_notify_receiver(vdec->vf_provider_name,
5188 VFRAME_EVENT_PROVIDER_QUREY_STATE,
5189 NULL);
5190 if ((state == RECEIVER_STATE_NULL)
5191 || (state == RECEIVER_STATE_NONE))
5192 state = RECEIVER_INACTIVE;
5193 }
5194 if (state == RECEIVER_INACTIVE)
5195 bufmgr_recover(hw);
5196 else
5197 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5198 } else if ((error_proc_policy & 0x8) &&
5199 (p_Dpb->ref_frames_in_buffer >
5200 (imax(
5201 1, p_Dpb->num_ref_frames)
5202 - p_Dpb->ltref_frames_in_buffer +
5203 force_sliding_margin)))
5204 bufmgr_recover(hw);
5205 else
5206 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5207
5208 if (hw->reset_bufmgr_flag == 1)
5209 buffer_available = 1;
5210 else if (hw->is_used_v4l)
5211 buffer_available = have_free_buf_spec(vdec);
5212 }
5213
5214 return buffer_available;
5215}
5216
5217#define AUX_TAG_SEI 0x2
5218
5219#define SEI_BUFFERING_PERIOD 0
5220#define SEI_PicTiming 1
5221#define SEI_USER_DATA 4
5222#define SEI_RECOVERY_POINT 6
5223
5224/*
5225 *************************************************************************
5226 * Function:Reads bits from the bitstream buffer
5227 * Input:
5228 byte buffer[]
5229 containing sei message data bits
5230 int totbitoffset
5231 bit offset from start of partition
5232 int bytecount
5233 total bytes in bitstream
5234 int numbits
5235 number of bits to read
5236 * Output:
5237 int *info
5238 * Return:
5239 -1: failed
5240 > 0: the count of bit read
5241 * Attention:
5242 *************************************************************************
5243 */
5244
5245static int get_bits(unsigned char buffer[],
5246 int totbitoffset,
5247 int *info,
5248 int bytecount,
5249 int numbits)
5250{
5251 register int inf;
5252 long byteoffset;
5253 int bitoffset;
5254
5255 int bitcounter = numbits;
5256
5257 byteoffset = totbitoffset / 8;
5258 bitoffset = 7 - (totbitoffset % 8);
5259
5260 inf = 0;
5261 while (numbits) {
5262 inf <<= 1;
5263 inf |= (buffer[byteoffset] & (0x01 << bitoffset)) >> bitoffset;
5264 numbits--;
5265 bitoffset--;
5266 if (bitoffset < 0) {
5267 byteoffset++;
5268 bitoffset += 8;
5269 if (byteoffset > bytecount)
5270 return -1;
5271 }
5272 }
5273
5274 *info = inf;
5275
5276
5277 return bitcounter;
5278}
5279
5280static int parse_one_sei_record(struct vdec_h264_hw_s *hw,
5281 u8 *sei_data_buf,
5282 u8 *sei_data_buf_end)
5283{
5284 int payload_type;
5285 int payload_size;
5286 u8 *p_sei;
5287 int temp = 0;
5288 int bit_offset;
5289 int read_size;
5290 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5291
5292 p_sei = sei_data_buf;
5293 read_size = 0;
5294 payload_type = 0;
5295 do {
5296 if (p_sei >= sei_data_buf_end)
5297 return read_size;
5298
5299 payload_type += *p_sei;
5300 read_size++;
5301 } while (*p_sei++ == 255);
5302
5303
5304 payload_size = 0;
5305 do {
5306 if (p_sei >= sei_data_buf_end)
5307 return read_size;
5308
5309 payload_size += *p_sei;
5310 read_size++;
5311 } while (*p_sei++ == 255);
5312
5313
5314 if (p_sei + payload_size > sei_data_buf_end) {
5315 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5316 "%s: payload_type = %d, payload_size = %d is over\n",
5317 __func__, payload_type, payload_size);
5318 return read_size;
5319 }
5320 bit_offset = 0;
5321
5322 if (payload_size <= 0) {
5323 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5324 "%s warning: this is a null sei message for payload_type = %d\n",
5325 __func__, payload_type);
5326 return read_size;
5327 }
5328 switch (payload_type) {
5329 case SEI_BUFFERING_PERIOD:
5330 break;
5331 case SEI_PicTiming:
5332 if (p_H264_Dpb->vui_status & 0xc) {
5333 int cpb_removal_delay;
5334 int dpb_output_delay;
5335 u32 delay_len;
5336
5337 delay_len = p_H264_Dpb->dpb_param.l.data[DELAY_LENGTH];
5338 cpb_removal_delay
5339 = (delay_len & 0x1F) + 1;
5340 dpb_output_delay
5341 = ((delay_len >> 5) & 0x1F) + 1;
5342
5343 get_bits(p_sei, bit_offset,
5344 &temp, payload_size,
5345 dpb_output_delay+cpb_removal_delay);
5346 bit_offset += dpb_output_delay+cpb_removal_delay;
5347 }
5348 if (p_H264_Dpb->vui_status & 0x10) {
5349 get_bits(p_sei, bit_offset, &temp, payload_size, 4);
5350 bit_offset += 4;
5351 p_H264_Dpb->dpb_param.l.data[PICTURE_STRUCT] = temp;
5352 }
5353 break;
5354 case SEI_USER_DATA:
5355 if (enable_itu_t35) {
5356 int i;
5357 int j;
5358 int data_len;
5359 u8 *user_data_buf;
5360
5361 user_data_buf
5362 = hw->sei_itu_data_buf + hw->sei_itu_data_len;
5363 /* user data length should be align with 8 bytes,
5364 if not, then padding with zero*/
5365 for (i = 0; i < payload_size; i += 8) {
5366 for (j = 0; j < 8; j++) {
5367 int index;
5368
5369 index = i+7-j;
5370 if (index >= payload_size)
5371 user_data_buf[i+j] = 0;
5372 else
5373 user_data_buf[i+j]
5374 = p_sei[i+7-j];
5375 }
5376 }
5377
5378 data_len = payload_size;
5379 if (payload_size % 8)
5380 data_len = ((payload_size + 8) >> 3) << 3;
5381
5382 hw->sei_itu_data_len += data_len;
5383 /*
5384 dpb_print(DECODE_ID(hw), 0,
5385 "%s: user data, and len = %d:\n",
5386 __func__, hw->sei_itu_data_len);
5387 */
5388 }
5389 break;
5390 case SEI_RECOVERY_POINT:
5391 p_H264_Dpb->dpb_param.l.data[RECOVERY_POINT] = 1;
5392 break;
5393 }
5394
5395 return read_size + payload_size;
5396}
5397
5398static void parse_sei_data(struct vdec_h264_hw_s *hw,
5399 u8 *sei_data_buf,
5400 int len)
5401{
5402 char *p_sei;
5403 char *p_sei_end;
5404 int parsed_size;
5405 int read_size;
5406
5407
5408 p_sei = sei_data_buf;
5409 p_sei_end = p_sei + len;
5410 parsed_size = 0;
5411 while (parsed_size < len) {
5412 read_size = parse_one_sei_record(hw, p_sei, p_sei_end);
5413 p_sei += read_size;
5414 parsed_size += read_size;
5415 if (*p_sei == 0x80) {
5416 p_sei++;
5417 parsed_size++;
5418 }
5419 }
5420}
5421
5422static void check_decoded_pic_error(struct vdec_h264_hw_s *hw)
5423{
5424 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5425 struct StorablePicture *p = p_H264_Dpb->mVideo.dec_picture;
5426 unsigned mby_mbx = READ_VREG(MBY_MBX);
5427 unsigned mb_total = (hw->seq_info2 >> 8) & 0xffff;
5428 unsigned decode_mb_count =
5429 ((mby_mbx & 0xff) * hw->mb_width +
5430 (((mby_mbx >> 8) & 0xff) + 1));
5431 if (mby_mbx == 0)
5432 return;
5433 if (get_cur_slice_picture_struct(p_H264_Dpb) != FRAME)
5434 mb_total /= 2;
5435 if (error_proc_policy & 0x100) {
5436 if (decode_mb_count < mb_total)
5437 p->data_flag |= ERROR_FLAG;
5438 }
5439
5440 if ((error_proc_policy & 0x200) &&
5441 READ_VREG(ERROR_STATUS_REG) != 0) {
5442 p->data_flag |= ERROR_FLAG;
5443 }
5444
5445 if (p->data_flag & ERROR_FLAG) {
5446 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
5447 "%s: decode error, seq_info2 0x%x, mby_mbx 0x%x, mb_total %d decoded mb_count %d ERROR_STATUS_REG 0x%x\n",
5448 __func__,
5449 hw->seq_info2,
5450 mby_mbx,
5451 mb_total,
5452 decode_mb_count,
5453 READ_VREG(ERROR_STATUS_REG)
5454 );
5455
5456 }
5457}
5458
5459static irqreturn_t vh264_isr_thread_fn(struct vdec_s *vdec, int irq)
5460{
5461 int i;
5462 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
5463 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5464 unsigned int dec_dpb_status = p_H264_Dpb->dec_dpb_status;
5465 u32 debug_tag;
5466 int ret;
5467
5468 if (dec_dpb_status == H264_CONFIG_REQUEST) {
5469#if 1
5470 unsigned short *p = (unsigned short *)hw->lmem_addr;
5471 dma_sync_single_for_cpu(
5472 amports_get_dma_device(),
5473 hw->lmem_addr_remap,
5474 PAGE_SIZE,
5475 DMA_FROM_DEVICE);
5476 for (i = 0; i < (RPM_END-RPM_BEGIN); i += 4) {
5477 int ii;
5478 for (ii = 0; ii < 4; ii++) {
5479 p_H264_Dpb->dpb_param.l.data[i+ii] =
5480 p[i+3-ii];
5481 if (dpb_is_debug(DECODE_ID(hw),
5482 RRINT_FLAG_RPM)) {
5483 if (((i + ii) & 0xf) == 0)
5484 dpb_print(DECODE_ID(hw),
5485 0, "%04x:",
5486 i);
5487 dpb_print_cont(DECODE_ID(hw),
5488 0, "%04x ",
5489 p[i+3-ii]);
5490 if (((i + ii + 1) & 0xf) == 0)
5491 dpb_print_cont(
5492 DECODE_ID(hw),
5493 0, "\r\n");
5494 }
5495 }
5496 }
5497
5498 p_H264_Dpb->bitstream_restriction_flag =
5499 (p_H264_Dpb->dpb_param.l.data[SPS_FLAGS2] >> 3) & 0x1;
5500 p_H264_Dpb->num_reorder_frames =
5501 p_H264_Dpb->dpb_param.l.data[NUM_REORDER_FRAMES];
5502 p_H264_Dpb->max_dec_frame_buffering =
5503 p_H264_Dpb->dpb_param.l.data[MAX_BUFFER_FRAME];
5504
5505 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5506 "H264_CONFIG_REQUEST: pdb %d, %d, %d\n",
5507 p_H264_Dpb->bitstream_restriction_flag,
5508 p_H264_Dpb->num_reorder_frames,
5509 p_H264_Dpb->max_dec_frame_buffering);
5510 hw->bitstream_restriction_flag =
5511 p_H264_Dpb->bitstream_restriction_flag;
5512 hw->num_reorder_frames =
5513 p_H264_Dpb->num_reorder_frames;
5514 hw->max_dec_frame_buffering =
5515 p_H264_Dpb->max_dec_frame_buffering;
5516#endif
5517
5518 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_CONFIG_DONE);
5519 reset_process_time(hw);
5520 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
5521 hw->dec_result = DEC_RESULT_CONFIG_PARAM;
5522 vdec_schedule_work(&hw->work);
5523 } else if (dec_dpb_status == H264_SLICE_HEAD_DONE) {
5524 u16 data_hight;
5525 u16 data_low;
5526 u32 video_signal;
5527
5528 int slice_header_process_status = 0;
5529 int I_flag;
5530 /*unsigned char is_idr;*/
5531 unsigned short *p = (unsigned short *)hw->lmem_addr;
5532 reset_process_time(hw);
5533
5534 if (hw->is_used_v4l) {
5535 struct aml_vcodec_ctx *ctx =
5536 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
5537
5538 if (ctx->param_sets_from_ucode && !ctx->v4l_codec_ready) {
5539 //amvdec_stop();
5540 hw->dec_result = DEC_RESULT_DONE;
5541 vdec_schedule_work(&hw->work);
5542 return IRQ_HANDLED;
5543 }
5544 }
5545
5546 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
5547 hw->reg_vcop_ctrl_reg = READ_VREG(VCOP_CTRL_REG);
5548 hw->reg_rv_ai_mb_count = READ_VREG(RV_AI_MB_COUNT);
5549 hw->vld_dec_control = READ_VREG(VLD_DECODE_CONTROL);
5550 if (input_frame_based(vdec) &&
5551 frmbase_cont_bitlevel2 != 0 &&
5552 READ_VREG(VIFF_BIT_CNT) <
5553 frmbase_cont_bitlevel2 &&
5554 hw->get_data_count >= 0x70000000) {
5555 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5556 "%s H264_SLICE_HEAD_DONE with small bitcnt %d, goto empty_proc\n",
5557 __func__,
5558 READ_VREG(VIFF_BIT_CNT));
5559
5560 goto empty_proc;
5561 }
5562
5563 dma_sync_single_for_cpu(
5564 amports_get_dma_device(),
5565 hw->lmem_addr_remap,
5566 PAGE_SIZE,
5567 DMA_FROM_DEVICE);
5568#if 0
5569 if (p_H264_Dpb->mVideo.dec_picture == NULL) {
5570 if (!is_buffer_available(vdec)) {
5571 hw->buffer_empty_flag = 1;
5572 dpb_print(DECODE_ID(hw),
5573 PRINT_FLAG_UCODE_EVT,
5574 "%s, buffer_empty, newframe_q(%d), have_free_buf_spec(%d), init_done(%d), used_size(%d/%d), is_there_unused_frame_from_dpb(%d)\n",
5575 __func__,
5576 kfifo_len(&hw->newframe_q),
5577 have_free_buf_spec(vdec),
5578 p_H264_Dpb->mDPB.init_done,
5579 p_H264_Dpb->mDPB.used_size,
5580 p_H264_Dpb->mDPB.size,
5581 is_there_unused_frame_from_dpb(
5582 &p_H264_Dpb->mDPB));
5583 return IRQ_HANDLED;
5584 }
5585 }
5586
5587 hw->buffer_empty_flag = 0;
5588#endif
5589#ifdef SEND_PARAM_WITH_REG
5590 for (i = 0; i < (RPM_END-RPM_BEGIN); i++) {
5591 unsigned int data32;
5592
5593 do {
5594 data32 = READ_VREG(RPM_CMD_REG);
5595 /* printk("%x\n", data32); */
5596 } while ((data32&0x10000) == 0);
5597 p_H264_Dpb->dpb_param.l.data[i] = data32 & 0xffff;
5598 WRITE_VREG(RPM_CMD_REG, 0);
5599 /* printk("%x:%x\n", i,data32); */
5600 }
5601#else
5602 for (i = 0; i < (RPM_END-RPM_BEGIN); i += 4) {
5603 int ii;
5604
5605 for (ii = 0; ii < 4; ii++) {
5606 p_H264_Dpb->dpb_param.l.data[i+ii] =
5607 p[i+3-ii];
5608 if (dpb_is_debug(DECODE_ID(hw),
5609 RRINT_FLAG_RPM)) {
5610 if (((i + ii) & 0xf) == 0)
5611 dpb_print(DECODE_ID(hw),
5612 0, "%04x:",
5613 i);
5614 dpb_print_cont(DECODE_ID(hw),
5615 0, "%04x ",
5616 p[i+3-ii]);
5617 if (((i + ii + 1) & 0xf) == 0)
5618 dpb_print_cont(
5619 DECODE_ID(hw),
5620 0, "\r\n");
5621 }
5622 }
5623 }
5624#endif
5625 data_low = p_H264_Dpb->dpb_param.l.data[VIDEO_SIGNAL_LOW];
5626 data_hight = p_H264_Dpb->dpb_param.l.data[VIDEO_SIGNAL_HIGHT];
5627
5628 video_signal = (data_hight << 16) | data_low;
5629 hw->video_signal_from_vui =
5630 ((video_signal & 0xffff) << 8) |
5631 ((video_signal & 0xff0000) >> 16) |
5632 ((video_signal & 0x3f000000));
5633
5634
5635 /*dpb_print(DECODE_ID(hw),
5636 0,
5637 "video_signal_from_vui:0x%x, "
5638 "data_low:0x%x, data_hight:0x%x\n",
5639 hw->video_signal_from_vui,
5640 data_low,
5641 data_hight);*/
5642
5643 parse_sei_data(hw, hw->sei_data_buf, hw->sei_data_len);
5644
5645 if (hw->config_bufmgr_done == 0) {
5646 hw->dec_result = DEC_RESULT_DONE;
5647 vdec_schedule_work(&hw->work);
5648 dpb_print(DECODE_ID(hw),
5649 PRINT_FLAG_UCODE_EVT,
5650 "config_bufmgr not done, discard frame\n");
5651 return IRQ_HANDLED;
5652 } else if ((hw->first_i_policy & 0x3) != 0) {
5653 unsigned char is_i_slice =
5654 (p_H264_Dpb->dpb_param.l.data[SLICE_TYPE]
5655 == I_Slice)
5656 ? 1 : 0;
5657 unsigned char is_idr =
5658 ((p_H264_Dpb->dpb_param.dpb.NAL_info_mmco & 0x1f)
5659 == 5);
5660 if ((hw->first_i_policy & 0x3) == 0x3)
5661 is_i_slice = is_idr;
5662 if (!is_i_slice) {
5663 if (hw->has_i_frame == 0) {
5664 amvdec_stop();
5665 vdec->mc_loaded = 0;
5666 hw->dec_result = DEC_RESULT_DONE;
5667 vdec_schedule_work(&hw->work);
5668 dpb_print(DECODE_ID(hw),
5669 PRINT_FLAG_UCODE_EVT,
5670 "has_i_frame is 0, discard none I(DR) frame\n");
5671 return IRQ_HANDLED;
5672 }
5673 } else {
5674 if (hw->skip_frame_count < 0 || is_idr) {
5675 /* second I */
5676 hw->dec_flag &= (~NODISP_FLAG);
5677 hw->skip_frame_count = 0;
5678 }
5679 if (hw->has_i_frame == 0 &&
5680 (!is_idr)) {
5681 int skip_count =
5682 (hw->first_i_policy >> 8) & 0xff;
5683 /* first I (not IDR) */
5684 if ((hw->first_i_policy & 0x3) == 2)
5685 hw->skip_frame_count =
5686 -1 - skip_count;
5687 else
5688 hw->skip_frame_count =
5689 skip_count;
5690 if (hw->skip_frame_count != 0)
5691 hw->dec_flag |= NODISP_FLAG;
5692 }
5693 }
5694 }
5695 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
5696 "current dpb index %d, poc %d, top/bot poc (%d,%d)\n",
5697 p_H264_Dpb->dpb_param.dpb.current_dpb_index,
5698 val(p_H264_Dpb->dpb_param.dpb.frame_pic_order_cnt),
5699 val(p_H264_Dpb->dpb_param.dpb.top_field_pic_order_cnt),
5700 val(p_H264_Dpb->dpb_param.dpb.top_field_pic_order_cnt));
5701 I_flag = (p_H264_Dpb->dpb_param.l.data[SLICE_TYPE] == I_Slice)
5702 ? I_FLAG : 0;
5703
5704 if ((hw->i_only & 0x2) && (I_flag & I_FLAG))
5705 flush_dpb(p_H264_Dpb);
5706
5707 if ((hw->i_only & 0x2) && (!(I_flag & I_FLAG)) &&
5708 (p_H264_Dpb->mSlice.structure == FRAME)) {
5709 hw->data_flag = NULL_FLAG;
5710 goto pic_done_proc;
5711 }
5712
5713 slice_header_process_status =
5714 h264_slice_header_process(p_H264_Dpb);
5715 if (hw->mmu_enable)
5716 hevc_sao_set_slice_type(hw,
5717 slice_header_process_status,
5718 hw->dpb.mSlice.idr_flag);
5719 vui_config(hw);
5720
5721 if (p_H264_Dpb->mVideo.dec_picture) {
5722 int cfg_ret = 0;
5723 bool field_pic_flag = false;
5724
5725 if (slice_header_process_status == 1) {
5726 if (!p_H264_Dpb->mSPS.frame_mbs_only_flag) {
5727 field_pic_flag =
5728 (p_H264_Dpb->mSlice.structure == TOP_FIELD ||
5729 p_H264_Dpb->mSlice.structure == BOTTOM_FIELD) ?
5730 true : false;
5731 }
5732
5733 if (!field_pic_flag && (((p_H264_Dpb->mSPS.profile_idc == BASELINE) &&
5734 (p_H264_Dpb->reorder_pic_num < 2)) ||
5735 (((unsigned long)(hw->vh264_amstream_dec_info
5736 .param)) & 0x8))) {
5737 p_H264_Dpb->fast_output_enable =
5738 H264_OUTPUT_MODE_FAST;
5739 }
5740 else
5741 p_H264_Dpb->fast_output_enable
5742 = fast_output_enable;
5743 hw->data_flag = I_flag;
5744 if ((p_H264_Dpb->
5745 dpb_param.dpb.NAL_info_mmco & 0x1f)
5746 == 5)
5747 hw->data_flag |= IDR_FLAG;
5748 dpb_print(DECODE_ID(hw),
5749 PRINT_FLAG_VDEC_STATUS,
5750 "==================> frame count %d to skip %d\n",
5751 hw->decode_pic_count+1,
5752 hw->skip_frame_count);
5753 } else if (error_proc_policy & 0x100){
5754 struct StorablePicture *p =
5755 p_H264_Dpb->mVideo.dec_picture;
5756 unsigned mby_mbx = READ_VREG(MBY_MBX);
5757 unsigned decode_mb_count =
5758 ((mby_mbx & 0xff) * hw->mb_width +
5759 (((mby_mbx >> 8) & 0xff) + 1));
5760 if (decode_mb_count <
5761 ((p_H264_Dpb->dpb_param.l.data[FIRST_MB_IN_SLICE]) *
5762 (1 + p->mb_aff_frame_flag))) {
5763 dpb_print(DECODE_ID(hw),
5764 PRINT_FLAG_VDEC_STATUS,
5765 "Error detect! first_mb 0x%x mby_mbx 0x%x decode_mb 0x%x\n",
5766 p_H264_Dpb->dpb_param.l.
5767 data[FIRST_MB_IN_SLICE],
5768 READ_VREG(MBY_MBX),
5769 decode_mb_count);
5770 p->data_flag |= ERROR_FLAG;
5771 } else if (!p_H264_Dpb->dpb_param.l.data[FIRST_MB_IN_SLICE] && decode_mb_count) {
5772 p->data_flag |= ERROR_FLAG;
5773 goto pic_done_proc;
5774 }
5775 }
5776
5777 if (p_H264_Dpb->mVideo.dec_picture->slice_type == I_SLICE) {
5778 hw->new_iframe_flag = 1;
5779 }
5780 if (hw->new_iframe_flag) {
5781 if (p_H264_Dpb->mVideo.dec_picture->slice_type == P_SLICE) {
5782 hw->new_iframe_flag = 0;
5783 hw->ref_err_flush_dpb_flag = 1;
5784 }else if (p_H264_Dpb->mVideo.dec_picture->slice_type == B_SLICE) {
5785 hw->new_iframe_flag = 0;
5786 hw->ref_err_flush_dpb_flag = 0;
5787 }
5788 }
5789
5790 if (error_proc_policy & 0x400) {
5791 int ret = dpb_check_ref_list_error(p_H264_Dpb);
5792 if (ret != 0) {
5793 hw->reflist_error_count ++;
5794 dpb_print(DECODE_ID(hw), 0,
5795 "reference list error %d frame count %d to skip %d reflist_error_count %d\n",
5796 ret,
5797 hw->decode_pic_count+1,
5798 hw->skip_frame_count,
5799 hw->reflist_error_count);
5800
5801 if (hw->ref_err_flush_dpb_flag) {
5802 flush_dpb(p_H264_Dpb);
5803 p_H264_Dpb->colocated_buf_map = 0;
5804 if (p_H264_Dpb->mVideo.dec_picture->colocated_buf_index >= 0) {
5805 p_H264_Dpb->colocated_buf_map |= 1 <<
5806 p_H264_Dpb->mVideo.dec_picture->colocated_buf_index;
5807 }
5808 }
5809
5810 p_H264_Dpb->mVideo.dec_picture->data_flag = NODISP_FLAG;
5811 if (((error_proc_policy & 0x80)
5812 && ((hw->dec_flag &
5813 NODISP_FLAG) == 0)) ||(hw->reflist_error_count > 50)) {
5814 hw->reset_bufmgr_flag = 1;
5815 hw->reflist_error_count =0;
5816 amvdec_stop();
5817 vdec->mc_loaded = 0;
5818 hw->dec_result = DEC_RESULT_DONE;
5819 vdec_schedule_work(&hw->work);
5820 return IRQ_HANDLED;
5821 }
5822 } else
5823 hw->reflist_error_count = 0;
5824 }
5825 if ((error_proc_policy & 0x800) && (!(hw->i_only & 0x2))
5826 && p_H264_Dpb->dpb_error_flag != 0) {
5827 dpb_print(DECODE_ID(hw), 0,
5828 "dpb error %d\n",
5829 p_H264_Dpb->dpb_error_flag);
5830 hw->data_flag |= ERROR_FLAG;
5831 p_H264_Dpb->mVideo.dec_picture->data_flag |= ERROR_FLAG;
5832 if ((error_proc_policy & 0x80) &&
5833 ((hw->dec_flag & NODISP_FLAG) == 0)) {
5834 hw->reset_bufmgr_flag = 1;
5835 amvdec_stop();
5836 vdec->mc_loaded = 0;
5837 hw->dec_result = DEC_RESULT_DONE;
5838 vdec_schedule_work(&hw->work);
5839 return IRQ_HANDLED;
5840 }
5841 }
5842
5843 cfg_ret = config_decode_buf(hw,
5844 p_H264_Dpb->mVideo.dec_picture);
5845 if (cfg_ret < 0) {
5846 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
5847 "config_decode_buf fail (%d)\n",
5848 cfg_ret);
5849 if (error_proc_policy & 0x2) {
5850 release_cur_decoding_buf(hw);
5851 /*hw->data_flag |= ERROR_FLAG;*/
5852 hw->reset_bufmgr_flag = 1;
5853 hw->dec_result = DEC_RESULT_DONE;
5854 vdec_schedule_work(&hw->work);
5855 return IRQ_HANDLED;
5856 } else
5857 hw->data_flag |= ERROR_FLAG;
5858 p_H264_Dpb->mVideo.dec_picture->data_flag |= ERROR_FLAG;
5859 }
5860 }
5861
5862 if (slice_header_process_status == 1)
5863 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_NEWPIC);
5864 else
5865 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_SLICE);
5866 hw->last_mby_mbx = 0;
5867 hw->last_vld_level = 0;
5868 start_process_time(hw);
5869 } else if (dec_dpb_status == H264_PIC_DATA_DONE
5870 ||((dec_dpb_status == H264_DATA_REQUEST) && input_frame_based(vdec))) {
5871pic_done_proc:
5872 reset_process_time(hw);
5873
5874 if (input_frame_based(vdec) &&
5875 (!(hw->i_only & 0x2)) &&
5876 frmbase_cont_bitlevel != 0 &&
5877 READ_VREG(VIFF_BIT_CNT) >
5878 frmbase_cont_bitlevel) {
5879 /*handle the case: multi pictures in one packet*/
5880 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5881 "%s H264_PIC_DATA_DONE decode slice count %d, continue (bitcnt 0x%x)\n",
5882 __func__,
5883 hw->decode_pic_count,
5884 READ_VREG(VIFF_BIT_CNT));
5885 hw->frmbase_cont_flag = 1;
5886 } else
5887 hw->frmbase_cont_flag = 0;
5888
5889 if (p_H264_Dpb->mVideo.dec_picture) {
5890 get_picture_qos_info(p_H264_Dpb->mVideo.dec_picture);
5891#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5892 DEL_EXIST(hw,
5893 p_H264_Dpb->mVideo.dec_picture) = 0;
5894 if (vdec->master) {
5895 struct vdec_h264_hw_s *hw_ba =
5896 (struct vdec_h264_hw_s *)
5897 vdec->master->private;
5898 if (hw_ba->last_dec_picture)
5899 DEL_EXIST(hw_ba,
5900 hw_ba->last_dec_picture)
5901 = 1;
5902 }
5903#endif
5904 mutex_lock(&hw->chunks_mutex);
5905 if (hw->chunk) {
5906 p_H264_Dpb->mVideo.dec_picture->pts =
5907 hw->chunk->pts;
5908 p_H264_Dpb->mVideo.dec_picture->pts64 =
5909 hw->chunk->pts64;
5910 p_H264_Dpb->mVideo.dec_picture->timestamp =
5911 hw->chunk->timestamp;
5912#ifdef MH264_USERDATA_ENABLE
5913 vmh264_udc_fill_vpts(hw,
5914 p_H264_Dpb->mSlice.slice_type,
5915 hw->chunk->pts, 1);
5916#endif
5917
5918#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5919 } else if (vdec->master) {
5920 /*dv enhance layer,
5921 do not checkout pts*/
5922 struct StorablePicture *pic =
5923 p_H264_Dpb->mVideo.dec_picture;
5924 pic->pts = 0;
5925 pic->pts64 = 0;
5926#endif
5927 } else {
5928 struct StorablePicture *pic =
5929 p_H264_Dpb->mVideo.dec_picture;
5930 u32 offset = pic->offset_delimiter;
5931 if (pts_pickout_offset_us64(PTS_TYPE_VIDEO,
5932 offset, &pic->pts, 0, &pic->pts64)) {
5933 pic->pts = 0;
5934 pic->pts64 = 0;
5935#ifdef MH264_USERDATA_ENABLE
5936 vmh264_udc_fill_vpts(hw,
5937 p_H264_Dpb->mSlice.slice_type,
5938 pic->pts, 0);
5939#endif
5940 } else {
5941#ifdef MH264_USERDATA_ENABLE
5942 vmh264_udc_fill_vpts(hw,
5943 p_H264_Dpb->mSlice.slice_type,
5944 pic->pts, 1);
5945#endif
5946 }
5947
5948 }
5949 mutex_unlock(&hw->chunks_mutex);
5950
5951 check_decoded_pic_error(hw);
5952#ifdef ERROR_HANDLE_TEST
5953 if ((hw->data_flag & ERROR_FLAG)
5954 && (error_proc_policy & 0x80)) {
5955 release_cur_decoding_buf(hw);
5956 h264_clear_dpb(hw);
5957 hw->dec_flag = 0;
5958 hw->data_flag = 0;
5959 hw->skip_frame_count = 0;
5960 hw->has_i_frame = 0;
5961 hw->no_error_count = 0xfff;
5962 hw->no_error_i_count = 0xf;
5963 } else
5964#endif
5965 ret = store_picture_in_dpb(p_H264_Dpb,
5966 p_H264_Dpb->mVideo.dec_picture,
5967 hw->data_flag | hw->dec_flag |
5968 p_H264_Dpb->mVideo.dec_picture->data_flag);
5969
5970
5971
5972 if (ret == -1) {
5973 release_cur_decoding_buf(hw);
5974 bufmgr_force_recover(p_H264_Dpb);
5975 } else {
5976 if (hw->data_flag & ERROR_FLAG) {
5977 hw->no_error_count = 0;
5978 hw->no_error_i_count = 0;
5979 } else {
5980 hw->no_error_count++;
5981 if (hw->data_flag & I_FLAG)
5982 hw->no_error_i_count++;
5983 }
5984 if (hw->mmu_enable)
5985 hevc_set_unused_4k_buff_idx(hw,
5986 p_H264_Dpb->mVideo.
5987 dec_picture->buf_spec_num);
5988 bufmgr_post(p_H264_Dpb);
5989 hw->last_dec_picture =
5990 p_H264_Dpb->mVideo.dec_picture;
5991 p_H264_Dpb->mVideo.dec_picture = NULL;
5992 /* dump_dpb(&p_H264_Dpb->mDPB); */
5993 hw->has_i_frame = 1;
5994 if (hw->mmu_enable)
5995 hevc_set_frame_done(hw);
5996 hw->decode_pic_count++;
5997 p_H264_Dpb->decode_pic_count = hw->decode_pic_count;
5998 if (hw->skip_frame_count > 0) {
5999 /*skip n frame after first I */
6000 hw->skip_frame_count--;
6001 if (hw->skip_frame_count == 0)
6002 hw->dec_flag &= (~NODISP_FLAG);
6003 } else if (hw->skip_frame_count < -1) {
6004 /*skip n frame after first I until second I */
6005 hw->skip_frame_count++;
6006 if (hw->skip_frame_count == -1)
6007 hw->dec_flag &= (~NODISP_FLAG);
6008 }
6009 }
6010 }
6011 if (hw->frmbase_cont_flag) {
6012 /*do not DEC_RESULT_GET_DATA*/
6013 hw->get_data_count = 0x7fffffff;
6014 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
6015 decode_frame_count[DECODE_ID(hw)]++;
6016 start_process_time(hw);
6017 return IRQ_HANDLED;
6018 }
6019 amvdec_stop();
6020 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6021 "%s %s decode slice count %d\n",
6022 __func__,
6023 (dec_dpb_status == H264_PIC_DATA_DONE) ?
6024 "H264_PIC_DATA_DONE" :
6025 (dec_dpb_status == H264_FIND_NEXT_PIC_NAL) ?
6026 "H264_FIND_NEXT_PIC_NAL" : "H264_FIND_NEXT_DVEL_NAL",
6027 hw->decode_pic_count);
6028 /* WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD); */
6029 hw->dec_result = DEC_RESULT_DONE;
6030#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
6031 if (vdec->slave &&
6032 dec_dpb_status == H264_FIND_NEXT_DVEL_NAL) {
6033 struct vdec_h264_hw_s *hw_el =
6034 (struct vdec_h264_hw_s *)(vdec->slave->private);
6035 hw_el->got_valid_nal = 0;
6036 hw->switch_dvlayer_flag = 1;
6037 } else if (vdec->master &&
6038 dec_dpb_status == H264_FIND_NEXT_PIC_NAL) {
6039 struct vdec_h264_hw_s *hw_bl =
6040 (struct vdec_h264_hw_s *)(vdec->master->private);
6041 hw_bl->got_valid_nal = 0;
6042 hw->switch_dvlayer_flag = 1;
6043 } else {
6044 hw->switch_dvlayer_flag = 0;
6045 hw->got_valid_nal = 1;
6046 }
6047#endif
6048
6049 hw->dec_result = DEC_RESULT_DONE;
6050 vdec_schedule_work(&hw->work);
6051
6052#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
6053 } else if (
6054 (dec_dpb_status == H264_FIND_NEXT_PIC_NAL) ||
6055 (dec_dpb_status == H264_FIND_NEXT_DVEL_NAL)) {
6056 goto pic_done_proc;
6057#endif
6058 } else if (dec_dpb_status == H264_AUX_DATA_READY) {
6059 reset_process_time(hw);
6060 if (READ_VREG(H264_AUX_DATA_SIZE) != 0) {
6061 dma_sync_single_for_cpu(
6062 amports_get_dma_device(),
6063 hw->aux_phy_addr,
6064 hw->prefix_aux_size + hw->suffix_aux_size,
6065 DMA_FROM_DEVICE);
6066 if (dpb_is_debug(DECODE_ID(hw),
6067 PRINT_FLAG_DPB_DETAIL))
6068 dump_aux_buf(hw);
6069#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
6070 if (vdec->dolby_meta_with_el || vdec->slave) {
6071 if (hw->last_dec_picture)
6072 set_aux_data(hw, hw->last_dec_picture,
6073 0, 0, NULL);
6074 } else {
6075 if (vdec->master) {
6076 struct vdec_h264_hw_s *hw_bl =
6077 (struct vdec_h264_hw_s *)
6078 (vdec->master->private);
6079 if (hw_bl->last_dec_picture != NULL) {
6080 set_aux_data(hw_bl,
6081 hw_bl->last_dec_picture,
6082 0, 1, hw);
6083 }
6084 set_aux_data(hw,
6085 hw->last_dec_picture,
6086 0, 2, NULL);
6087 }
6088 }
6089#else
6090 if (hw->last_dec_picture)
6091 set_aux_data(hw,
6092 hw->last_dec_picture, 0, 0, NULL);
6093#endif
6094 }
6095#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
6096 hw->switch_dvlayer_flag = 0;
6097 hw->got_valid_nal = 1;
6098#endif
6099 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6100 "%s H264_AUX_DATA_READY\n", __func__);
6101 hw->dec_result = DEC_RESULT_DONE;
6102 vdec_schedule_work(&hw->work);
6103 } else if (/*(dec_dpb_status == H264_DATA_REQUEST) ||*/
6104 (dec_dpb_status == H264_SEARCH_BUFEMPTY) ||
6105 (dec_dpb_status == H264_DECODE_BUFEMPTY) ||
6106 (dec_dpb_status == H264_DECODE_TIMEOUT)) {
6107empty_proc:
6108 reset_process_time(hw);
6109 if (!hw->frmbase_cont_flag)
6110 release_cur_decoding_buf(hw);
6111
6112 if (input_frame_based(vdec) ||
6113 (READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0x200)) {
6114 if (h264_debug_flag &
6115 DISABLE_ERROR_HANDLE) {
6116 dpb_print(DECODE_ID(hw),
6117 PRINT_FLAG_ERROR,
6118 "%s decoding error, level 0x%x\n",
6119 __func__,
6120 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
6121 goto send_again;
6122 }
6123 amvdec_stop();
6124 vdec->mc_loaded = 0;
6125 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6126 "%s %s\n", __func__,
6127 (dec_dpb_status == H264_SEARCH_BUFEMPTY) ?
6128 "H264_SEARCH_BUFEMPTY" :
6129 (dec_dpb_status == H264_DECODE_BUFEMPTY) ?
6130 "H264_DECODE_BUFEMPTY" :
6131 (dec_dpb_status == H264_DECODE_TIMEOUT) ?
6132 "H264_DECODE_TIMEOUT" :
6133 "OTHER");
6134 hw->dec_result = DEC_RESULT_DONE;
6135
6136 if (dec_dpb_status == H264_SEARCH_BUFEMPTY)
6137 hw->search_dataempty_num++;
6138 else if (dec_dpb_status == H264_DECODE_TIMEOUT) {
6139 hw->decode_timeout_num++;
6140 if (error_proc_policy & 0x4000) {
6141 hw->data_flag |= ERROR_FLAG;
6142 if ((p_H264_Dpb->last_dpb_status == H264_DECODE_TIMEOUT) ||
6143 (p_H264_Dpb->last_dpb_status == H264_PIC_DATA_DONE) ||
6144 ((p_H264_Dpb->last_dpb_status == H264_SLICE_HEAD_DONE) &&
6145 (p_H264_Dpb->mSlice.slice_type != B_SLICE))) {
6146 dpb_print(DECODE_ID(hw),
6147 PRINT_FLAG_ERROR, "%s last dpb status 0x%x need bugmgr reset \n",
6148 p_H264_Dpb->last_dpb_status, __func__);
6149 hw->reset_bufmgr_flag = 1;
6150 }
6151 }
6152 } else if (dec_dpb_status == H264_DECODE_BUFEMPTY)
6153 hw->decode_dataempty_num++;
6154 if (!hw->frmbase_cont_flag)
6155 hw->data_flag |= ERROR_FLAG;
6156
6157 vdec_schedule_work(&hw->work);
6158 } else {
6159 /* WRITE_VREG(DPB_STATUS_REG, H264_ACTION_INIT); */
6160 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6161 "%s DEC_RESULT_AGAIN\n", __func__);
6162send_again:
6163 hw->dec_result = DEC_RESULT_AGAIN;
6164 vdec_schedule_work(&hw->work);
6165 }
6166 } else if (dec_dpb_status == H264_DATA_REQUEST) {
6167 reset_process_time(hw);
6168 if (input_frame_based(vdec)) {
6169 dpb_print(DECODE_ID(hw),
6170 PRINT_FLAG_VDEC_STATUS,
6171 "%s H264_DATA_REQUEST (%d)\n",
6172 __func__, hw->get_data_count);
6173 hw->dec_result = DEC_RESULT_GET_DATA;
6174 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
6175 hw->get_data_start_time = jiffies;
6176 hw->get_data_count++;
6177 if (hw->get_data_count >= frame_max_data_packet)
6178 goto empty_proc;
6179 vdec_schedule_work(&hw->work);
6180 } else
6181 goto empty_proc;
6182 } else if (dec_dpb_status == H264_DECODE_OVER_SIZE) {
6183 dpb_print(DECODE_ID(hw), 0,
6184 "vmh264 decode oversize !!\n");
6185 release_cur_decoding_buf(hw);
6186 hw->data_flag |= ERROR_FLAG;
6187 hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
6188 reset_process_time(hw);
6189 hw->dec_result = DEC_RESULT_DONE;
6190 vdec_schedule_work(&hw->work);
6191 return IRQ_HANDLED;
6192 } else if (dec_dpb_status == H264_SEI_DATA_READY) {
6193 int aux_data_len;
6194 aux_data_len =
6195 (READ_VREG(H264_AUX_DATA_SIZE) >> 16) << 4;
6196
6197 if (aux_data_len > SEI_DATA_SIZE) {
6198 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
6199 "sei data size more than 4K: %d, discarded it\n",
6200 hw->sei_itu_data_len);
6201 hw->sei_itu_data_len = 0;
6202 }
6203
6204 if (aux_data_len != 0) {
6205 u8 *trans_data_buf;
6206 u8 *sei_data_buf;
6207 u8 swap_byte;
6208
6209 dma_sync_single_for_cpu(
6210 amports_get_dma_device(),
6211 hw->aux_phy_addr,
6212 hw->prefix_aux_size + hw->suffix_aux_size,
6213 DMA_FROM_DEVICE);
6214#if 0
6215 dump_aux_buf(hw);
6216#endif
6217 trans_data_buf = (u8 *)hw->aux_addr;
6218
6219 if (trans_data_buf[7] == AUX_TAG_SEI) {
6220 int left_len;
6221
6222 sei_data_buf = (u8 *)hw->sei_data_buf
6223 + hw->sei_data_len;
6224 left_len = SEI_DATA_SIZE - hw->sei_data_len;
6225 if (aux_data_len/2 <= left_len) {
6226 for (i = 0; i < aux_data_len/2; i++)
6227 sei_data_buf[i]
6228 = trans_data_buf[i*2];
6229
6230 aux_data_len = aux_data_len / 2;
6231 for (i = 0; i < aux_data_len; i = i+4) {
6232 swap_byte = sei_data_buf[i];
6233 sei_data_buf[i]
6234 = sei_data_buf[i+3];
6235 sei_data_buf[i+3] = swap_byte;
6236
6237 swap_byte = sei_data_buf[i+1];
6238 sei_data_buf[i+1]
6239 = sei_data_buf[i+2];
6240 sei_data_buf[i+2] = swap_byte;
6241 }
6242
6243 for (i = aux_data_len-1; i >= 0; i--)
6244 if (sei_data_buf[i] != 0)
6245 break;
6246
6247 hw->sei_data_len += i+1;
6248 } else
6249 dpb_print(DECODE_ID(hw),
6250 PRINT_FLAG_ERROR,
6251 "sei data size %d and more than left space: %d, discarded it\n",
6252 hw->sei_itu_data_len,
6253 left_len);
6254 }
6255 }
6256 WRITE_VREG(DPB_STATUS_REG, H264_SEI_DATA_DONE);
6257
6258 return IRQ_HANDLED;
6259 }
6260
6261
6262 /* ucode debug */
6263 debug_tag = READ_VREG(DEBUG_REG1);
6264 if (debug_tag & 0x10000) {
6265 unsigned short *p = (unsigned short *)hw->lmem_addr;
6266
6267 dma_sync_single_for_cpu(
6268 amports_get_dma_device(),
6269 hw->lmem_addr_remap,
6270 PAGE_SIZE,
6271 DMA_FROM_DEVICE);
6272
6273 dpb_print(DECODE_ID(hw), 0,
6274 "LMEM<tag %x>:\n", debug_tag);
6275 for (i = 0; i < 0x400; i += 4) {
6276 int ii;
6277 if ((i & 0xf) == 0)
6278 dpb_print_cont(DECODE_ID(hw), 0,
6279 "%03x: ", i);
6280 for (ii = 0; ii < 4; ii++)
6281 dpb_print_cont(DECODE_ID(hw), 0,
6282 "%04x ", p[i+3-ii]);
6283 if (((i+ii) & 0xf) == 0)
6284 dpb_print_cont(DECODE_ID(hw), 0,
6285 "\n");
6286 }
6287 if (((udebug_pause_pos & 0xffff)
6288 == (debug_tag & 0xffff)) &&
6289 (udebug_pause_decode_idx == 0 ||
6290 udebug_pause_decode_idx ==
6291 hw->decode_pic_count) &&
6292 (udebug_pause_val == 0 ||
6293 udebug_pause_val == READ_VREG(DEBUG_REG2))) {
6294 udebug_pause_pos &= 0xffff;
6295 hw->ucode_pause_pos = udebug_pause_pos;
6296 }
6297 else if (debug_tag & 0x20000)
6298 hw->ucode_pause_pos = 0xffffffff;
6299 if (hw->ucode_pause_pos)
6300 reset_process_time(hw);
6301 else
6302 WRITE_VREG(DEBUG_REG1, 0);
6303 } else if (debug_tag != 0) {
6304 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
6305 "dbg%x: %x\n", debug_tag,
6306 READ_VREG(DEBUG_REG2));
6307 if (((udebug_pause_pos & 0xffff)
6308 == (debug_tag & 0xffff)) &&
6309 (udebug_pause_decode_idx == 0 ||
6310 udebug_pause_decode_idx ==
6311 hw->decode_pic_count) &&
6312 (udebug_pause_val == 0 ||
6313 udebug_pause_val == READ_VREG(DEBUG_REG2))) {
6314 udebug_pause_pos &= 0xffff;
6315 hw->ucode_pause_pos = udebug_pause_pos;
6316 }
6317 if (hw->ucode_pause_pos)
6318 reset_process_time(hw);
6319 else
6320 WRITE_VREG(DEBUG_REG1, 0);
6321 }
6322 /**/
6323 return IRQ_HANDLED;
6324}
6325
6326static irqreturn_t vh264_isr(struct vdec_s *vdec, int irq)
6327{
6328 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
6329 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6330
6331
6332 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
6333
6334 if (!hw)
6335 return IRQ_HANDLED;
6336
6337 if (hw->eos)
6338 return IRQ_HANDLED;
6339
6340 p_H264_Dpb->vdec = vdec;
6341 p_H264_Dpb->dec_dpb_status = READ_VREG(DPB_STATUS_REG);
6342
6343 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
6344 "%s DPB_STATUS_REG: 0x%x, ERROR_STATUS_REG 0x%x, sb (0x%x 0x%x 0x%x) bitcnt 0x%x mby_mbx 0x%x\n",
6345 __func__,
6346 p_H264_Dpb->dec_dpb_status,
6347 READ_VREG(ERROR_STATUS_REG),
6348 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
6349 READ_VREG(VLD_MEM_VIFIFO_WP),
6350 READ_VREG(VLD_MEM_VIFIFO_RP),
6351 READ_VREG(VIFF_BIT_CNT),
6352 READ_VREG(MBY_MBX));
6353
6354 if (p_H264_Dpb->dec_dpb_status == H264_WRRSP_REQUEST) {
6355 if (hw->mmu_enable)
6356 hevc_sao_wait_done(hw);
6357 WRITE_VREG(DPB_STATUS_REG, H264_WRRSP_DONE);
6358 return IRQ_HANDLED;
6359 }
6360 return IRQ_WAKE_THREAD;
6361
6362}
6363
6364static void timeout_process(struct vdec_h264_hw_s *hw)
6365{
6366 struct vdec_s *vdec = hw_to_vdec(hw);
6367 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6368
6369 /*
6370 * In this very timeout point,the vh264_work arrives,
6371 * let it to handle the scenario.
6372 */
6373 if (work_pending(&hw->work))
6374 return;
6375
6376 hw->timeout_num++;
6377 amvdec_stop();
6378 vdec->mc_loaded = 0;
6379 if (hw->mmu_enable) {
6380 hevc_set_frame_done(hw);
6381 hevc_sao_wait_done(hw);
6382 }
6383 if (!hw->i_only && (error_proc_policy & 0x2))
6384 flush_dpb(p_H264_Dpb);
6385 dpb_print(DECODE_ID(hw),
6386 PRINT_FLAG_ERROR, "%s decoder timeout\n", __func__);
6387 release_cur_decoding_buf(hw);
6388 hw->dec_result = DEC_RESULT_DONE;
6389 hw->data_flag |= ERROR_FLAG;
6390
6391 if (work_pending(&hw->work))
6392 return;
6393 vdec_schedule_work(&hw->timeout_work);
6394}
6395
6396static void dump_bufspec(struct vdec_h264_hw_s *hw,
6397 const char *caller)
6398{
6399 int i;
6400 dpb_print(DECODE_ID(hw), 0,
6401 "%s in %s:\n", __func__, caller);
6402 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
6403 if (hw->buffer_spec[i].used == -1)
6404 continue;
6405 dpb_print(DECODE_ID(hw), 0,
6406 "bufspec (%d): used %d adr 0x%x canvas(%d) vf_ref(%d) ",
6407 i, hw->buffer_spec[i].used,
6408 hw->buffer_spec[i].buf_adr,
6409 hw->buffer_spec[i].canvas_pos,
6410 hw->buffer_spec[i].vf_ref
6411 );
6412#ifdef CONFIG_AM_VDEC_DV
6413 dpb_print_cont(DECODE_ID(hw), 0,
6414 "dv_el_exist %d",
6415 hw->buffer_spec[i].dv_enhance_exist
6416 );
6417#endif
6418 dpb_print_cont(DECODE_ID(hw), 0, "\n");
6419 }
6420
6421}
6422
6423static void vmh264_dump_state(struct vdec_s *vdec)
6424{
6425 struct vdec_h264_hw_s *hw =
6426 (struct vdec_h264_hw_s *)(vdec->private);
6427 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6428 dpb_print(DECODE_ID(hw), 0,
6429 "====== %s\n", __func__);
6430 dpb_print(DECODE_ID(hw), 0,
6431 "width/height (%d/%d), reorder_pic_num %d dpb size(bufspec count) %d max_reference_size(collocate count) %d i_only %d send_err %d\n",
6432 hw->frame_width,
6433 hw->frame_height,
6434 hw->dpb.reorder_pic_num,
6435 hw->dpb.mDPB.size,
6436 hw->max_reference_size,
6437 hw->i_only,
6438 hw->send_error_frame_flag
6439 );
6440
6441 dpb_print(DECODE_ID(hw), 0,
6442 "is_framebase(%d), eos %d, state 0x%x, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d bufmgr_reset_cnt %d\n",
6443 input_frame_based(vdec),
6444 hw->eos,
6445 hw->stat,
6446 hw->dec_result,
6447 decode_frame_count[DECODE_ID(hw)],
6448 display_frame_count[DECODE_ID(hw)],
6449 run_count[DECODE_ID(hw)],
6450 not_run_ready[DECODE_ID(hw)],
6451 input_empty[DECODE_ID(hw)],
6452 hw->reset_bufmgr_count
6453 );
6454
6455 if (vf_get_receiver(vdec->vf_provider_name)) {
6456 enum receviver_start_e state =
6457 vf_notify_receiver(vdec->vf_provider_name,
6458 VFRAME_EVENT_PROVIDER_QUREY_STATE,
6459 NULL);
6460 dpb_print(DECODE_ID(hw), 0,
6461 "\nreceiver(%s) state %d\n",
6462 vdec->vf_provider_name,
6463 state);
6464 }
6465
6466 dpb_print(DECODE_ID(hw), 0,
6467 "%s, newq(%d/%d), dispq(%d/%d) vf prepare/get/put (%d/%d/%d), free_spec(%d), initdon(%d), used_size(%d/%d), unused_fr_dpb(%d) fast_output_enable %x \n",
6468 __func__,
6469 kfifo_len(&hw->newframe_q),
6470 VF_POOL_SIZE,
6471 kfifo_len(&hw->display_q),
6472 VF_POOL_SIZE,
6473 hw->vf_pre_count,
6474 hw->vf_get_count,
6475 hw->vf_put_count,
6476 have_free_buf_spec(vdec),
6477 p_H264_Dpb->mDPB.init_done,
6478 p_H264_Dpb->mDPB.used_size, p_H264_Dpb->mDPB.size,
6479 is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB),
6480 p_H264_Dpb->fast_output_enable
6481 );
6482
6483 dump_dpb(&p_H264_Dpb->mDPB, 1);
6484 dump_pic(p_H264_Dpb);
6485 dump_bufspec(hw, __func__);
6486
6487 dpb_print(DECODE_ID(hw), 0,
6488 "DPB_STATUS_REG=0x%x\n",
6489 READ_VREG(DPB_STATUS_REG));
6490 dpb_print(DECODE_ID(hw), 0,
6491 "MPC_E=0x%x\n",
6492 READ_VREG(MPC_E));
6493 dpb_print(DECODE_ID(hw), 0,
6494 "H264_DECODE_MODE=0x%x\n",
6495 READ_VREG(H264_DECODE_MODE));
6496 dpb_print(DECODE_ID(hw), 0,
6497 "MBY_MBX=0x%x\n",
6498 READ_VREG(MBY_MBX));
6499 dpb_print(DECODE_ID(hw), 0,
6500 "H264_DECODE_SIZE=0x%x\n",
6501 READ_VREG(H264_DECODE_SIZE));
6502 dpb_print(DECODE_ID(hw), 0,
6503 "VIFF_BIT_CNT=0x%x\n",
6504 READ_VREG(VIFF_BIT_CNT));
6505 dpb_print(DECODE_ID(hw), 0,
6506 "VLD_MEM_VIFIFO_LEVEL=0x%x\n",
6507 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
6508 dpb_print(DECODE_ID(hw), 0,
6509 "VLD_MEM_VIFIFO_WP=0x%x\n",
6510 READ_VREG(VLD_MEM_VIFIFO_WP));
6511 dpb_print(DECODE_ID(hw), 0,
6512 "VLD_MEM_VIFIFO_RP=0x%x\n",
6513 READ_VREG(VLD_MEM_VIFIFO_RP));
6514 dpb_print(DECODE_ID(hw), 0,
6515 "PARSER_VIDEO_RP=0x%x\n",
6516 READ_PARSER_REG(PARSER_VIDEO_RP));
6517 dpb_print(DECODE_ID(hw), 0,
6518 "PARSER_VIDEO_WP=0x%x\n",
6519 READ_PARSER_REG(PARSER_VIDEO_WP));
6520
6521 if (input_frame_based(vdec) &&
6522 dpb_is_debug(DECODE_ID(hw),
6523 PRINT_FRAMEBASE_DATA)
6524 ) {
6525 int jj;
6526 if (hw->chunk && hw->chunk->block &&
6527 hw->chunk->size > 0) {
6528 u8 *data = NULL;
6529
6530 if (!hw->chunk->block->is_mapped)
6531 data = codec_mm_vmap(hw->chunk->block->start +
6532 hw->chunk->offset, hw->chunk->size);
6533 else
6534 data = ((u8 *)hw->chunk->block->start_virt)
6535 + hw->chunk->offset;
6536
6537 dpb_print(DECODE_ID(hw), 0,
6538 "frame data size 0x%x\n",
6539 hw->chunk->size);
6540 for (jj = 0; jj < hw->chunk->size; jj++) {
6541 if ((jj & 0xf) == 0)
6542 dpb_print(DECODE_ID(hw),
6543 PRINT_FRAMEBASE_DATA,
6544 "%06x:", jj);
6545 dpb_print_cont(DECODE_ID(hw),
6546 PRINT_FRAMEBASE_DATA,
6547 "%02x ", data[jj]);
6548 if (((jj + 1) & 0xf) == 0)
6549 dpb_print_cont(DECODE_ID(hw),
6550 PRINT_FRAMEBASE_DATA,
6551 "\n");
6552 }
6553
6554 if (!hw->chunk->block->is_mapped)
6555 codec_mm_unmap_phyaddr(data);
6556 }
6557 }
6558}
6559
6560
6561static void check_timer_func(unsigned long arg)
6562{
6563 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)arg;
6564 struct vdec_s *vdec = hw_to_vdec(hw);
6565 int error_skip_frame_count = error_skip_count & 0xfff;
6566 unsigned int timeout_val = decode_timeout_val;
6567 if (timeout_val != 0 &&
6568 hw->no_error_count < error_skip_frame_count)
6569 timeout_val = errordata_timeout_val;
6570 if ((h264_debug_cmd & 0x100) != 0 &&
6571 DECODE_ID(hw) == (h264_debug_cmd & 0xff)) {
6572 hw->dec_result = DEC_RESULT_DONE;
6573 vdec_schedule_work(&hw->work);
6574 pr_info("vdec %d is forced to be disconnected\n",
6575 h264_debug_cmd & 0xff);
6576 h264_debug_cmd = 0;
6577 return;
6578 }
6579 if ((h264_debug_cmd & 0x200) != 0 &&
6580 DECODE_ID(hw) == (h264_debug_cmd & 0xff)) {
6581 pr_debug("vdec %d is forced to reset bufmgr\n",
6582 h264_debug_cmd & 0xff);
6583 hw->reset_bufmgr_flag = 1;
6584 h264_debug_cmd = 0;
6585 return;
6586 }
6587
6588 if (vdec->next_status == VDEC_STATUS_DISCONNECTED) {
6589 hw->dec_result = DEC_RESULT_FORCE_EXIT;
6590 vdec_schedule_work(&hw->work);
6591 pr_debug("vdec requested to be disconnected\n");
6592 return;
6593 }
6594
6595 if (radr != 0) {
6596 if (rval != 0) {
6597 WRITE_VREG(radr, rval);
6598 pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
6599 } else
6600 pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
6601 rval = 0;
6602 radr = 0;
6603 }
6604
6605 if ((input_frame_based(vdec) ||
6606 (READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0xb0)) &&
6607 ((h264_debug_flag & DISABLE_ERROR_HANDLE) == 0) &&
6608 (timeout_val > 0) &&
6609 (hw->start_process_time > 0) &&
6610 ((1000 * (jiffies - hw->start_process_time) / HZ)
6611 > timeout_val)
6612 ) {
6613 u32 dpb_status = READ_VREG(DPB_STATUS_REG);
6614 u32 mby_mbx = READ_VREG(MBY_MBX);
6615 if ((dpb_status == H264_ACTION_DECODE_NEWPIC) ||
6616 (dpb_status == H264_ACTION_DECODE_SLICE)) {
6617 if (hw->last_mby_mbx == mby_mbx) {
6618 if (hw->decode_timeout_count > 0)
6619 hw->decode_timeout_count--;
6620 if (hw->decode_timeout_count == 0)
6621 {
6622 reset_process_time(hw);
6623 timeout_process(hw);
6624 }
6625 } else
6626 start_process_time(hw);
6627 } else if (is_in_parsing_state(dpb_status)) {
6628 if (hw->last_vld_level ==
6629 READ_VREG(VLD_MEM_VIFIFO_LEVEL)) {
6630 if (hw->decode_timeout_count > 0)
6631 hw->decode_timeout_count--;
6632 if (hw->decode_timeout_count == 0)
6633 {
6634 reset_process_time(hw);
6635 timeout_process(hw);
6636 }
6637 }
6638 }
6639 hw->last_vld_level =
6640 READ_VREG(VLD_MEM_VIFIFO_LEVEL);
6641 hw->last_mby_mbx = mby_mbx;
6642 }
6643
6644 if ((hw->ucode_pause_pos != 0) &&
6645 (hw->ucode_pause_pos != 0xffffffff) &&
6646 udebug_pause_pos != hw->ucode_pause_pos) {
6647 hw->ucode_pause_pos = 0;
6648 WRITE_VREG(DEBUG_REG1, 0);
6649 }
6650
6651 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
6652}
6653
6654static int dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
6655{
6656 u32 ar;
6657 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
6658
6659 if (!hw)
6660 return -1;
6661
6662 vstatus->frame_width = hw->frame_width;
6663 vstatus->frame_height = hw->frame_height;
6664 if (hw->frame_dur != 0)
6665 vstatus->frame_rate = 96000 / hw->frame_dur;
6666 else
6667 vstatus->frame_rate = -1;
6668 vstatus->error_count = 0;
6669 vstatus->status = hw->stat;
6670 if (hw->h264_ar == 0x3ff)
6671 hw->h264_ar = (0x100 *
6672 hw->frame_height * hw->height_aspect_ratio) /
6673 (hw->frame_width * hw->width_aspect_ratio);
6674 ar = min_t(u32,
6675 hw->h264_ar,
6676 DISP_RATIO_ASPECT_RATIO_MAX);
6677 vstatus->ratio_control =
6678 ar << DISP_RATIO_ASPECT_RATIO_BIT;
6679
6680 snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
6681 "%s-%02d", DRIVER_NAME, hw->id);
6682
6683 return 0;
6684}
6685
6686static int vh264_hw_ctx_restore(struct vdec_h264_hw_s *hw)
6687{
6688 int i, j;
6689 struct aml_vcodec_ctx * v4l2_ctx = hw->v4l2_ctx;
6690
6691 /* if (hw->init_flag == 0) { */
6692 if (h264_debug_flag & 0x40000000) {
6693 /* if (1) */
6694 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6695 "%s, reset register\n", __func__);
6696
6697 while (READ_VREG(DCAC_DMA_CTRL) & 0x8000)
6698 ;
6699 while (READ_VREG(LMEM_DMA_CTRL) & 0x8000)
6700 ; /* reg address is 0x350 */
6701
6702#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
6703 WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4));
6704 WRITE_VREG(DOS_SW_RESET0, 0);
6705
6706 READ_VREG(DOS_SW_RESET0);
6707 READ_VREG(DOS_SW_RESET0);
6708 READ_VREG(DOS_SW_RESET0);
6709
6710 WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4));
6711 WRITE_VREG(DOS_SW_RESET0, 0);
6712
6713 WRITE_VREG(DOS_SW_RESET0, (1<<9) | (1<<8));
6714 WRITE_VREG(DOS_SW_RESET0, 0);
6715
6716 READ_VREG(DOS_SW_RESET0);
6717 READ_VREG(DOS_SW_RESET0);
6718 READ_VREG(DOS_SW_RESET0);
6719
6720#else
6721 WRITE_RESET_REG(RESET0_REGISTER,
6722 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
6723 READ_RESET_REG(RESET0_REGISTER);
6724 WRITE_RESET_REG(RESET0_REGISTER,
6725 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
6726
6727 WRITE_RESET_REG(RESET2_REGISTER, RESET_PIC_DC | RESET_DBLK);
6728#endif
6729 WRITE_VREG(POWER_CTL_VLD,
6730 READ_VREG(POWER_CTL_VLD) | (0 << 10) |
6731 (1 << 9) | (1 << 6));
6732 } else {
6733 /* WRITE_VREG(POWER_CTL_VLD,
6734 * READ_VREG(POWER_CTL_VLD) | (0 << 10) | (1 << 9) );
6735 */
6736 WRITE_VREG(POWER_CTL_VLD,
6737 READ_VREG(POWER_CTL_VLD) |
6738 (0 << 10) | (1 << 9) | (1 << 6));
6739 }
6740 /* disable PSCALE for hardware sharing */
6741 WRITE_VREG(PSCALE_CTRL, 0);
6742
6743 /* clear mailbox interrupt */
6744 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
6745
6746 /* enable mailbox interrupt */
6747 WRITE_VREG(ASSIST_MBOX1_MASK, 1);
6748
6749#ifdef NV21
6750 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1<<17);
6751#endif
6752
6753 /* cbcr_merge_swap_en */
6754 if (hw->is_used_v4l
6755 && (v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21
6756 || v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
6757 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 16);
6758
6759 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 0xbf << 24);
6760 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 0xbf << 24);
6761
6762 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 31);
6763 if (hw->mmu_enable) {
6764 SET_VREG_MASK(MDEC_PIC_DC_MUX_CTRL, 1<<31);
6765 /* sw reset to extif hardware */
6766 SET_VREG_MASK(MDEC_EXTIF_CFG1, 1<<30);
6767 CLEAR_VREG_MASK(MDEC_EXTIF_CFG1, 1<<30);
6768 } else {
6769 CLEAR_VREG_MASK(MDEC_PIC_DC_MUX_CTRL, 1 << 31);
6770 WRITE_VREG(MDEC_EXTIF_CFG1, 0);
6771 }
6772
6773
6774#if 1 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
6775 /* pr_info("vh264 meson8 prot init\n"); */
6776 WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa);
6777#endif
6778
6779#ifdef VDEC_DW
6780 if (IS_VDEC_DW(hw)) {
6781 u32 data = ((1 << 30) |(1 << 0) |(1 << 8));
6782
6783 if (IS_VDEC_DW(hw) == 2)
6784 data |= (1 << 9);
6785 WRITE_VREG(MDEC_DOUBLEW_CFG0, data); /* Double Write Enable*/
6786 }
6787#endif
6788 if (hw->dpb.mDPB.size > 0) {
6789 WRITE_VREG(AV_SCRATCH_7, (hw->max_reference_size << 24) |
6790 (hw->dpb.mDPB.size << 16) |
6791 (hw->dpb.mDPB.size << 8));
6792
6793 for (j = 0; j < hw->dpb.mDPB.size; j++) {
6794 i = get_buf_spec_by_canvas_pos(hw, j);
6795 if (i < 0)
6796 break;
6797
6798 if (!hw->mmu_enable &&
6799 hw->buffer_spec[i].cma_alloc_addr)
6800 config_decode_canvas(hw, i);
6801 if (hw->mmu_enable && hw->double_write_mode)
6802 config_decode_canvas_ex(hw, i);
6803 }
6804 } else {
6805 WRITE_VREG(AV_SCRATCH_0, 0);
6806 WRITE_VREG(AV_SCRATCH_9, 0);
6807 }
6808
6809 if (hw->init_flag == 0)
6810 WRITE_VREG(DPB_STATUS_REG, 0);
6811 else
6812 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_START);
6813
6814 WRITE_VREG(FRAME_COUNTER_REG, hw->decode_pic_count);
6815 WRITE_VREG(AV_SCRATCH_8, hw->buf_offset);
6816 if (!tee_enabled())
6817 WRITE_VREG(AV_SCRATCH_G, hw->mc_dma_handle);
6818
6819 /* hw->error_recovery_mode = (error_recovery_mode != 0) ?
6820 * error_recovery_mode : error_recovery_mode_in;
6821 */
6822 /* WRITE_VREG(AV_SCRATCH_F,
6823 * (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) );
6824 */
6825 WRITE_VREG(AV_SCRATCH_F, (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) |
6826 ((error_recovery_mode_in & 0x1) << 4));
6827 /*if (hw->ucode_type == UCODE_IP_ONLY_PARAM)
6828 SET_VREG_MASK(AV_SCRATCH_F, 1 << 6);
6829 else*/
6830 CLEAR_VREG_MASK(AV_SCRATCH_F, 1 << 6);
6831
6832 WRITE_VREG(LMEM_DUMP_ADR, (u32)hw->lmem_addr_remap);
6833#if 1 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
6834 WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa);
6835#endif
6836
6837 WRITE_VREG(DEBUG_REG1, 0);
6838 WRITE_VREG(DEBUG_REG2, 0);
6839
6840 if (hw->reg_iqidct_control)
6841 WRITE_VREG(IQIDCT_CONTROL, hw->reg_iqidct_control);
6842 if (hw->reg_vcop_ctrl_reg)
6843 WRITE_VREG(VCOP_CTRL_REG, hw->reg_vcop_ctrl_reg);
6844 if (hw->vld_dec_control)
6845 WRITE_VREG(VLD_DECODE_CONTROL, hw->vld_dec_control);
6846 return 0;
6847}
6848
6849static int vmh264_set_trickmode(struct vdec_s *vdec, unsigned long trickmode)
6850{
6851 struct vdec_h264_hw_s *hw =
6852 (struct vdec_h264_hw_s *)vdec->private;
6853 if (i_only_flag & 0x100)
6854 return 0;
6855 if (trickmode == TRICKMODE_I)
6856 hw->i_only = 0x3;
6857 else if (trickmode == TRICKMODE_NONE)
6858 hw->i_only = 0x0;
6859 return 0;
6860}
6861
6862static unsigned char amvdec_enable_flag;
6863static void vh264_local_init(struct vdec_h264_hw_s *hw, bool is_reset)
6864{
6865 int i;
6866 hw->init_flag = 0;
6867 hw->first_sc_checked= 0;
6868 hw->eos = 0;
6869 hw->valve_count = 0;
6870 hw->config_bufmgr_done = 0;
6871 hw->start_process_time = 0;
6872 hw->has_i_frame = 0;
6873 hw->no_error_count = 0xfff;
6874 hw->no_error_i_count = 0xf;
6875
6876 hw->dec_flag = 0;
6877 hw->data_flag = 0;
6878 hw->skip_frame_count = 0;
6879 hw->reg_iqidct_control = 0;
6880 hw->reg_vcop_ctrl_reg = 0;
6881 hw->reg_rv_ai_mb_count = 0;
6882 hw->vld_dec_control = 0;
6883 hw->decode_timeout_count = 0;
6884 hw->no_mem_count = 0;
6885 hw->vh264_ratio = hw->vh264_amstream_dec_info.ratio;
6886 /* vh264_ratio = 0x100; */
6887
6888 hw->vh264_rotation = (((unsigned long)
6889 hw->vh264_amstream_dec_info.param) >> 16) & 0xffff;
6890
6891 hw->frame_prog = 0;
6892 hw->frame_width = hw->vh264_amstream_dec_info.width;
6893 hw->frame_height = hw->vh264_amstream_dec_info.height;
6894 hw->frame_dur = hw->vh264_amstream_dec_info.rate;
6895 hw->pts_outside = ((unsigned long)
6896 hw->vh264_amstream_dec_info.param) & 0x01;
6897 hw->sync_outside = ((unsigned long)
6898 hw->vh264_amstream_dec_info.param & 0x02) >> 1;
6899 hw->use_idr_framerate = ((unsigned long)
6900 hw->vh264_amstream_dec_info.param & 0x04) >> 2;
6901 hw->max_refer_buf = !(((unsigned long)
6902 hw->vh264_amstream_dec_info.param & 0x10) >> 4);
6903 if (hw->frame_dur < 96000/960) {
6904 /*more than 960fps,it should not be a correct value,
6905 *give default 30fps
6906 */
6907 hw->frame_dur = 96000/30;
6908 }
6909
6910 hw->unstable_pts = (((unsigned long) hw->vh264_amstream_dec_info.param & 0x40) >> 6);
6911
6912 hw->first_i_policy = first_i_policy;
6913
6914 pr_info("H264 sysinfo: %dx%d duration=%d, pts_outside=%d\n",
6915 hw->frame_width, hw->frame_height, hw->frame_dur, hw->pts_outside);
6916 pr_debug("sync_outside=%d, use_idr_framerate=%d, is_used_v4l: %d\n",
6917 hw->sync_outside, hw->use_idr_framerate, hw->is_used_v4l);
6918
6919 if (i_only_flag & 0x100)
6920 hw->i_only = i_only_flag & 0xff;
6921 if (hw->i_only)
6922 hw->dpb.first_insert_frame = FirstInsertFrm_SKIPDONE;
6923
6924 if ((unsigned long) hw->vh264_amstream_dec_info.param
6925 & 0x08)
6926 hw->no_poc_reorder_flag = 1;
6927
6928 error_recovery_mode_in = 1; /*ucode control?*/
6929 if (error_proc_policy & 0x80000000)
6930 hw->send_error_frame_flag = error_proc_policy & 0x1;
6931 else if ((unsigned long) hw->vh264_amstream_dec_info.param & 0x20)
6932 hw->send_error_frame_flag = 0; /*Don't display mark err frames*/
6933
6934 if (!is_reset) {
6935 INIT_KFIFO(hw->display_q);
6936 INIT_KFIFO(hw->newframe_q);
6937
6938 for (i = 0; i < VF_POOL_SIZE; i++) {
6939 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
6940 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
6941 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
6942 kfifo_put(&hw->newframe_q, vf);
6943 }
6944 }
6945
6946 hw->duration_from_pts_done = 0;
6947
6948 hw->p_last_vf = NULL;
6949 hw->vh264_stream_switching_state = SWITCHING_STATE_OFF;
6950 hw->hevc_cur_buf_idx = 0xffff;
6951
6952 init_waitqueue_head(&hw->wait_q);
6953
6954 return;
6955}
6956
6957static s32 vh264_init(struct vdec_h264_hw_s *hw)
6958{
6959 int size = -1;
6960 int fw_size = 0x1000 * 16;
6961 int fw_mmu_size = 0x1000 * 16;
6962 struct firmware_s *fw = NULL, *fw_mmu = NULL;
6963
6964 /* int trickmode_fffb = 0; */
6965
6966 /* pr_info("\nvh264_init\n"); */
6967 /* init_timer(&hw->recycle_timer); */
6968
6969 /* timer init */
6970 init_timer(&hw->check_timer);
6971
6972 hw->check_timer.data = (unsigned long)hw;
6973 hw->check_timer.function = check_timer_func;
6974 hw->check_timer.expires = jiffies + CHECK_INTERVAL;
6975
6976 /* add_timer(&hw->check_timer); */
6977 hw->stat |= STAT_TIMER_ARM;
6978 hw->stat |= STAT_ISR_REG;
6979
6980 mutex_init(&hw->chunks_mutex);
6981 vh264_local_init(hw, false);
6982 INIT_WORK(&hw->work, vh264_work);
6983 INIT_WORK(&hw->notify_work, vh264_notify_work);
6984 INIT_WORK(&hw->timeout_work, vh264_timeout_work);
6985#ifdef MH264_USERDATA_ENABLE
6986 INIT_WORK(&hw->user_data_ready_work, user_data_ready_notify_work);
6987#endif
6988
6989 if (!amvdec_enable_flag) {
6990 amvdec_enable_flag = true;
6991 amvdec_enable();
6992 if (hw->mmu_enable)
6993 amhevc_enable();
6994 }
6995 if (hw->mmu_enable) {
6996
6997 hw->frame_mmu_map_addr =
6998 dma_alloc_coherent(amports_get_dma_device(),
6999 FRAME_MMU_MAP_SIZE,
7000 &hw->frame_mmu_map_phy_addr, GFP_KERNEL);
7001 if (hw->frame_mmu_map_addr == NULL) {
7002 pr_err("%s: failed to alloc count_buffer\n", __func__);
7003 return -ENOMEM;
7004 }
7005 }
7006
7007 fw = vmalloc(sizeof(struct firmware_s) + fw_size);
7008 if (IS_ERR_OR_NULL(fw))
7009 return -ENOMEM;
7010
7011 size = get_firmware_data(VIDEO_DEC_H264_MULTI, fw->data);
7012 if (size < 0) {
7013 pr_err("get firmware fail.\n");
7014 vfree(fw);
7015 return -1;
7016 }
7017
7018 fw->len = size;
7019 hw->fw = fw;
7020
7021 if (hw->mmu_enable) {
7022 fw_mmu = vmalloc(sizeof(struct firmware_s) + fw_mmu_size);
7023 if (IS_ERR_OR_NULL(fw_mmu))
7024 return -ENOMEM;
7025
7026 size = get_firmware_data(VIDEO_DEC_H264_MULTI_MMU, fw_mmu->data);
7027 if (size < 0) {
7028 pr_err("get mmu fw fail.\n");
7029 vfree(fw_mmu);
7030 return -1;
7031 }
7032
7033 fw_mmu->len = size;
7034 hw->fw_mmu = fw_mmu;
7035 }
7036
7037 if (!tee_enabled()) {
7038 /* -- ucode loading (amrisc and swap code) */
7039 hw->mc_cpu_addr =
7040 dma_alloc_coherent(amports_get_dma_device(), MC_TOTAL_SIZE,
7041 &hw->mc_dma_handle, GFP_KERNEL);
7042 if (!hw->mc_cpu_addr) {
7043 amvdec_enable_flag = false;
7044 amvdec_disable();
7045 if (hw->mmu_enable)
7046 amhevc_disable();
7047 pr_info("vh264_init: Can not allocate mc memory.\n");
7048 return -ENOMEM;
7049 }
7050
7051 /*pr_info("264 ucode swap area: phyaddr %p, cpu vaddr %p\n",
7052 (void *)hw->mc_dma_handle, hw->mc_cpu_addr);
7053 */
7054
7055 /*ret = amvdec_loadmc_ex(VFORMAT_H264, NULL, buf);*/
7056
7057 /*header*/
7058 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_HEADER,
7059 fw->data + 0x4000, MC_SWAP_SIZE);
7060 /*data*/
7061 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_DATA,
7062 fw->data + 0x2000, MC_SWAP_SIZE);
7063 /*mmco*/
7064 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MMCO,
7065 fw->data + 0x6000, MC_SWAP_SIZE);
7066 /*list*/
7067 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_LIST,
7068 fw->data + 0x3000, MC_SWAP_SIZE);
7069 /*slice*/
7070 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_SLICE,
7071 fw->data + 0x5000, MC_SWAP_SIZE);
7072 /*main*/
7073 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN,
7074 fw->data, 0x2000);
7075 /*data*/
7076 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN + 0x2000,
7077 fw->data + 0x2000, 0x1000);
7078 /*slice*/
7079 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN + 0x3000,
7080 fw->data + 0x5000, 0x1000);
7081 }
7082
7083#if 1 /* #ifdef BUFFER_MGR_IN_C */
7084 hw->lmem_addr = __get_free_page(GFP_KERNEL);
7085 if (!hw->lmem_addr) {
7086 pr_info("%s: failed to alloc lmem_addr\n", __func__);
7087 return -ENOMEM;
7088 } else {
7089 hw->lmem_addr_remap = dma_map_single(
7090 amports_get_dma_device(),
7091 (void *)hw->lmem_addr,
7092 PAGE_SIZE, DMA_FROM_DEVICE);
7093 if (dma_mapping_error(amports_get_dma_device(),
7094 hw->lmem_addr_remap)) {
7095 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
7096 "%s: failed to map lmem_addr\n", __func__);
7097 free_page(hw->lmem_addr);
7098 hw->lmem_addr = 0;
7099 hw->lmem_addr_remap = 0;
7100 return -ENOMEM;
7101 }
7102
7103 pr_debug("%s, vaddr=%lx phy_addr=%p\n",
7104 __func__, hw->lmem_addr, (void *)hw->lmem_addr_remap);
7105 }
7106
7107 if (prefix_aux_buf_size > 0 ||
7108 suffix_aux_buf_size > 0) {
7109 u32 aux_buf_size;
7110 hw->prefix_aux_size = AUX_BUF_ALIGN(prefix_aux_buf_size);
7111 hw->suffix_aux_size = AUX_BUF_ALIGN(suffix_aux_buf_size);
7112 aux_buf_size = hw->prefix_aux_size + hw->suffix_aux_size;
7113 hw->aux_addr = kmalloc(aux_buf_size, GFP_KERNEL);
7114 if (hw->aux_addr == NULL) {
7115 pr_err("%s: failed to alloc rpm buffer\n", __func__);
7116 return -1;
7117 }
7118
7119 hw->aux_phy_addr = dma_map_single(amports_get_dma_device(),
7120 hw->aux_addr, aux_buf_size, DMA_FROM_DEVICE);
7121 if (dma_mapping_error(amports_get_dma_device(),
7122 hw->aux_phy_addr)) {
7123 pr_err("%s: failed to map rpm buffer\n", __func__);
7124 kfree(hw->aux_addr);
7125 hw->aux_addr = NULL;
7126 return -1;
7127 }
7128 hw->sei_data_buf = kmalloc(SEI_DATA_SIZE, GFP_KERNEL);
7129 if (hw->sei_data_buf == NULL) {
7130 pr_err("%s: failed to alloc sei itu data buffer\n",
7131 __func__);
7132 return -1;
7133 }
7134 hw->sei_itu_data_buf = kmalloc(SEI_ITU_DATA_SIZE, GFP_KERNEL);
7135 if (hw->sei_itu_data_buf == NULL) {
7136 pr_err("%s: failed to alloc sei itu data buffer\n",
7137 __func__);
7138 kfree(hw->aux_addr);
7139 hw->aux_addr = NULL;
7140 kfree(hw->sei_data_buf);
7141 hw->sei_data_buf = NULL;
7142
7143 return -1;
7144 }
7145
7146 if (NULL == hw->sei_user_data_buffer) {
7147 hw->sei_user_data_buffer = kmalloc(USER_DATA_SIZE,
7148 GFP_KERNEL);
7149 if (!hw->sei_user_data_buffer) {
7150 pr_info("%s: Can not allocate sei_data_buffer\n",
7151 __func__);
7152 kfree(hw->aux_addr);
7153 hw->aux_addr = NULL;
7154 kfree(hw->sei_data_buf);
7155 hw->sei_data_buf = NULL;
7156 kfree(hw->sei_itu_data_buf);
7157 hw->sei_itu_data_buf = NULL;
7158
7159 return -1;
7160 }
7161 hw->sei_user_data_wp = 0;
7162 }
7163 }
7164/* BUFFER_MGR_IN_C */
7165#endif
7166 hw->stat |= STAT_MC_LOAD;
7167
7168 /* add memory barrier */
7169 wmb();
7170
7171 return 0;
7172}
7173
7174static int vh264_stop(struct vdec_h264_hw_s *hw)
7175{
7176 if (hw->stat & STAT_VDEC_RUN) {
7177 amvdec_stop();
7178 hw->stat &= ~STAT_VDEC_RUN;
7179 }
7180#ifdef VDEC_DW
7181 WRITE_VREG(MDEC_DOUBLEW_CFG0, 0);
7182#endif
7183#ifdef MH264_USERDATA_ENABLE
7184 cancel_work_sync(&hw->user_data_ready_work);
7185#endif
7186 cancel_work_sync(&hw->notify_work);
7187 cancel_work_sync(&hw->timeout_work);
7188 cancel_work_sync(&hw->work);
7189
7190
7191 if (hw->stat & STAT_MC_LOAD) {
7192 if (hw->mc_cpu_addr != NULL) {
7193 dma_free_coherent(amports_get_dma_device(),
7194 MC_TOTAL_SIZE, hw->mc_cpu_addr,
7195 hw->mc_dma_handle);
7196 hw->mc_cpu_addr = NULL;
7197 }
7198 if (hw->frame_mmu_map_addr != NULL) {
7199 dma_free_coherent(amports_get_dma_device(),
7200 FRAME_MMU_MAP_SIZE, hw->frame_mmu_map_addr,
7201 hw->frame_mmu_map_phy_addr);
7202 hw->frame_mmu_map_addr = NULL;
7203 }
7204
7205 }
7206 if (hw->stat & STAT_ISR_REG) {
7207 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
7208 hw->stat &= ~STAT_ISR_REG;
7209 }
7210 if (hw->lmem_addr_remap) {
7211 dma_unmap_single(amports_get_dma_device(),
7212 hw->lmem_addr_remap,
7213 PAGE_SIZE, DMA_FROM_DEVICE);
7214 hw->lmem_addr_remap = 0;
7215 }
7216 if (hw->lmem_addr) {
7217 free_page(hw->lmem_addr);
7218 hw->lmem_addr = 0;
7219 }
7220 if (hw->aux_addr) {
7221 dma_unmap_single(amports_get_dma_device(),
7222 hw->aux_phy_addr,
7223 hw->prefix_aux_size + hw->suffix_aux_size,
7224 DMA_FROM_DEVICE);
7225 kfree(hw->aux_addr);
7226 hw->aux_addr = NULL;
7227 }
7228 if (hw->sei_data_buf != NULL) {
7229 kfree(hw->sei_data_buf);
7230 hw->sei_data_buf = NULL;
7231 }
7232 if (hw->sei_itu_data_buf != NULL) {
7233 kfree(hw->sei_itu_data_buf);
7234 hw->sei_itu_data_buf = NULL;
7235 }
7236 if (hw->sei_user_data_buffer != NULL) {
7237 kfree(hw->sei_user_data_buffer);
7238 hw->sei_user_data_buffer = NULL;
7239 }
7240 /* amvdec_disable(); */
7241
7242 vfree(hw->fw);
7243 hw->fw = NULL;
7244
7245 if (hw->mmu_enable) {
7246 vfree(hw->fw_mmu);
7247 hw->fw_mmu = NULL;
7248 }
7249
7250 dpb_print(DECODE_ID(hw), 0,
7251 "%s\n",
7252 __func__);
7253 return 0;
7254}
7255
7256static void wait_vmh264_search_done(struct vdec_h264_hw_s *hw)
7257{
7258 u32 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
7259 int count = 0;
7260 do {
7261 usleep_range(100, 500);
7262 if (vld_rp == READ_VREG(VLD_MEM_VIFIFO_RP))
7263 break;
7264 if (count > 2000) {
7265 dpb_print(DECODE_ID(hw),
7266 PRINT_FLAG_ERROR, "%s timeout count %d vld_rp 0x%x VLD_MEM_VIFIFO_RP 0x%x\n",
7267 __func__, count, vld_rp, READ_VREG(VLD_MEM_VIFIFO_RP));
7268 break;
7269 } else
7270 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
7271 count++;
7272 } while (1);
7273}
7274
7275static void vh264_notify_work(struct work_struct *work)
7276{
7277 struct vdec_h264_hw_s *hw = container_of(work,
7278 struct vdec_h264_hw_s, notify_work);
7279 struct vdec_s *vdec = hw_to_vdec(hw);
7280 if (vdec->fr_hint_state == VDEC_NEED_HINT) {
7281 vf_notify_receiver(vdec->vf_provider_name,
7282 VFRAME_EVENT_PROVIDER_FR_HINT,
7283 (void *)((unsigned long)hw->frame_dur));
7284 vdec->fr_hint_state = VDEC_HINTED;
7285 }
7286
7287 return;
7288}
7289
7290#ifdef MH264_USERDATA_ENABLE
7291static void vmh264_reset_udr_mgr(struct vdec_h264_hw_s *hw)
7292{
7293 hw->wait_for_udr_send = 0;
7294 hw->sei_itu_data_len = 0;
7295 memset(&hw->ud_record, 0, sizeof(hw->ud_record));
7296}
7297
7298static void vmh264_crate_userdata_manager(
7299 struct vdec_h264_hw_s *hw,
7300 u8 *userdata_buf,
7301 int buf_len)
7302{
7303 if (hw) {
7304
7305
7306 mutex_init(&hw->userdata_mutex);
7307
7308 memset(&hw->userdata_info, 0,
7309 sizeof(struct mh264_userdata_info_t));
7310 hw->userdata_info.data_buf = userdata_buf;
7311 hw->userdata_info.buf_len = buf_len;
7312 hw->userdata_info.data_buf_end = userdata_buf + buf_len;
7313
7314 vmh264_reset_udr_mgr(hw);
7315
7316 }
7317}
7318
7319static void vmh264_destroy_userdata_manager(struct vdec_h264_hw_s *hw)
7320{
7321 if (hw)
7322 memset(&hw->userdata_info,
7323 0,
7324 sizeof(struct mh264_userdata_info_t));
7325}
7326
7327/*
7328#define DUMP_USERDATA_RECORD
7329*/
7330#ifdef DUMP_USERDATA_RECORD
7331
7332#define MAX_USER_DATA_SIZE 3145728
7333static void *user_data_buf;
7334static unsigned char *pbuf_start;
7335static int total_len;
7336static int bskip;
7337static int n_userdata_id;
7338
7339static void print_data(unsigned char *pdata,
7340 int len,
7341 unsigned int poc_number,
7342 unsigned int flag,
7343 unsigned int duration,
7344 unsigned int vpts,
7345 unsigned int vpts_valid,
7346 int rec_id)
7347{
7348 int nLeft;
7349
7350 nLeft = len;
7351#if 0
7352 pr_info("%d len:%d, flag:%d, dur:%d, vpts:0x%x, valid:%d, poc:%d\n",
7353 rec_id, len, flag,
7354 duration, vpts, vpts_valid, poc_number);
7355#endif
7356 pr_info("%d len = %d, flag = %d, vpts = 0x%x\n",
7357 rec_id, len, flag, vpts);
7358
7359 if (len == 96) {
7360 int i;
7361 nLeft = 72;
7362 while (nLeft >= 16) {
7363 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
7364 pdata[0], pdata[1], pdata[2], pdata[3],
7365 pdata[4], pdata[5], pdata[6], pdata[7],
7366 pdata[8], pdata[9], pdata[10], pdata[11],
7367 pdata[12], pdata[13], pdata[14], pdata[15]);
7368 nLeft -= 16;
7369 pdata += 16;
7370 }
7371
7372
7373 while (nLeft > 0) {
7374 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
7375 pdata[0], pdata[1], pdata[2], pdata[3],
7376 pdata[4], pdata[5], pdata[6], pdata[7]);
7377 nLeft -= 8;
7378 pdata += 8;
7379 }
7380
7381 i = 0;
7382 nLeft = 96-72;
7383 while (i < nLeft) {
7384 if (pdata[0] != 0) {
7385 pr_info("some data error\n");
7386 break;
7387 }
7388 pdata++;
7389 i++;
7390 }
7391 } else {
7392 while (nLeft >= 16) {
7393 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
7394 pdata[0], pdata[1], pdata[2], pdata[3],
7395 pdata[4], pdata[5], pdata[6], pdata[7],
7396 pdata[8], pdata[9], pdata[10], pdata[11],
7397 pdata[12], pdata[13], pdata[14], pdata[15]);
7398 nLeft -= 16;
7399 pdata += 16;
7400 }
7401
7402
7403 while (nLeft > 0) {
7404 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
7405 pdata[0], pdata[1], pdata[2], pdata[3],
7406 pdata[4], pdata[5], pdata[6], pdata[7]);
7407 nLeft -= 8;
7408 pdata += 8;
7409 }
7410
7411 }
7412}
7413
7414static void push_to_buf(struct vdec_h264_hw_s *hw,
7415 u8 *pdata,
7416 int len,
7417 struct userdata_meta_info_t *pmeta);
7418
7419static void dump_userdata_record(struct vdec_h264_hw_s *hw,
7420 struct mh264_userdata_record_t *record)
7421{
7422 if (record && hw) {
7423 u8 *pdata;
7424
7425 pdata = hw->userdata_info.data_buf + record->rec_start;
7426/*
7427 print_data(pdata,
7428 record->rec_len,
7429 record->meta_info.flags,
7430 record->meta_info.duration,
7431 record->meta_info.vpts,
7432 record->meta_info.vpts_valid,
7433 n_record_id);
7434*/
7435 push_to_buf(hw, pdata, record->rec_len, &record->meta_info);
7436 n_userdata_id++;
7437 }
7438}
7439
7440
7441static void push_to_buf(struct vdec_h264_hw_s *hw,
7442 u8 *pdata, int len,
7443 struct userdata_meta_info_t *pmeta)
7444{
7445 u32 *pLen;
7446 int info_cnt;
7447 u8 *pbuf_end;
7448
7449 if (!user_data_buf)
7450 return;
7451
7452 if (bskip) {
7453 pr_info("over size, skip\n");
7454 return;
7455 }
7456 info_cnt = 0;
7457 pLen = (u32 *)pbuf_start;
7458
7459 *pLen = len;
7460 pbuf_start += sizeof(u32);
7461 info_cnt++;
7462 pLen++;
7463
7464 *pLen = pmeta->poc_number;
7465 pbuf_start += sizeof(u32);
7466 info_cnt++;
7467 pLen++;
7468
7469 *pLen = pmeta->duration;
7470 pbuf_start += sizeof(u32);
7471 info_cnt++;
7472 pLen++;
7473
7474 *pLen = pmeta->flags;
7475 pbuf_start += sizeof(u32);
7476 info_cnt++;
7477 pLen++;
7478
7479 *pLen = pmeta->vpts;
7480 pbuf_start += sizeof(u32);
7481 info_cnt++;
7482 pLen++;
7483
7484 *pLen = pmeta->vpts_valid;
7485 pbuf_start += sizeof(u32);
7486 info_cnt++;
7487 pLen++;
7488
7489
7490 *pLen = n_userdata_id;
7491 pbuf_start += sizeof(u32);
7492 info_cnt++;
7493 pLen++;
7494
7495
7496
7497 pbuf_end = (u8 *)hw->sei_user_data_buffer + USER_DATA_SIZE;
7498 if (pdata + len > pbuf_end) {
7499 int first_section_len;
7500
7501 first_section_len = pbuf_end - pdata;
7502 memcpy(pbuf_start, pdata, first_section_len);
7503 pdata = (u8 *)hw->sei_user_data_buffer;
7504 pbuf_start += first_section_len;
7505 memcpy(pbuf_start, pdata, len - first_section_len);
7506 pbuf_start += len - first_section_len;
7507 } else {
7508 memcpy(pbuf_start, pdata, len);
7509 pbuf_start += len;
7510 }
7511
7512 total_len += len + info_cnt * sizeof(u32);
7513 if (total_len >= MAX_USER_DATA_SIZE-4096)
7514 bskip = 1;
7515}
7516
7517static void show_user_data_buf(void)
7518{
7519 u8 *pbuf;
7520 int len;
7521 unsigned int flag;
7522 unsigned int duration;
7523 unsigned int vpts;
7524 unsigned int vpts_valid;
7525 unsigned int poc_number;
7526 int rec_id;
7527
7528 pr_info("show user data buf\n");
7529 pbuf = user_data_buf;
7530
7531 while (pbuf < pbuf_start) {
7532 u32 *pLen;
7533
7534 pLen = (u32 *)pbuf;
7535
7536 len = *pLen;
7537 pLen++;
7538 pbuf += sizeof(u32);
7539
7540 poc_number = *pLen;
7541 pLen++;
7542 pbuf += sizeof(u32);
7543
7544 duration = *pLen;
7545 pLen++;
7546 pbuf += sizeof(u32);
7547
7548 flag = *pLen;
7549 pLen++;
7550 pbuf += sizeof(u32);
7551
7552 vpts = *pLen;
7553 pLen++;
7554 pbuf += sizeof(u32);
7555
7556 vpts_valid = *pLen;
7557 pLen++;
7558 pbuf += sizeof(u32);
7559
7560 rec_id = *pLen;
7561 pLen++;
7562 pbuf += sizeof(u32);
7563
7564 print_data(pbuf, len, poc_number, flag,
7565 duration, vpts,
7566 vpts_valid, rec_id);
7567 pbuf += len;
7568 msleep(30);
7569 }
7570}
7571
7572static int vmh264_init_userdata_dump(void)
7573{
7574 user_data_buf = kmalloc(MAX_USER_DATA_SIZE, GFP_KERNEL);
7575 if (user_data_buf)
7576 return 1;
7577 else
7578 return 0;
7579}
7580
7581static void vmh264_dump_userdata(void)
7582{
7583 if (user_data_buf) {
7584 show_user_data_buf();
7585 kfree(user_data_buf);
7586 user_data_buf = NULL;
7587 }
7588}
7589
7590static void vmh264_reset_user_data_buf(void)
7591{
7592 total_len = 0;
7593 pbuf_start = user_data_buf;
7594 bskip = 0;
7595 n_userdata_id = 0;
7596}
7597#endif
7598
7599
7600static void vmh264_udc_fill_vpts(struct vdec_h264_hw_s *hw,
7601 int frame_type,
7602 u32 vpts,
7603 u32 vpts_valid)
7604{
7605 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
7606
7607 unsigned char *pdata;
7608 u8 *pmax_sei_data_buffer;
7609 u8 *sei_data_buf;
7610 int i;
7611 int wp;
7612 int data_length;
7613 struct mh264_userdata_record_t *p_userdata_rec;
7614
7615
7616#ifdef MH264_USERDATA_ENABLE
7617 struct userdata_meta_info_t meta_info;
7618 memset(&meta_info, 0, sizeof(meta_info));
7619#endif
7620
7621 if (hw->sei_itu_data_len <= 0)
7622 return;
7623
7624 pdata = (u8 *)hw->sei_user_data_buffer + hw->sei_user_data_wp;
7625 pmax_sei_data_buffer = (u8 *)hw->sei_user_data_buffer + USER_DATA_SIZE;
7626 sei_data_buf = (u8 *)hw->sei_itu_data_buf;
7627 for (i = 0; i < hw->sei_itu_data_len; i++) {
7628 *pdata++ = sei_data_buf[i];
7629 if (pdata >= pmax_sei_data_buffer)
7630 pdata = (u8 *)hw->sei_user_data_buffer;
7631 }
7632
7633 hw->sei_user_data_wp = (hw->sei_user_data_wp
7634 + hw->sei_itu_data_len) % USER_DATA_SIZE;
7635 hw->sei_itu_data_len = 0;
7636
7637#ifdef MH264_USERDATA_ENABLE
7638 meta_info.duration = hw->frame_dur;
7639 meta_info.flags |= (VFORMAT_H264 << 3);
7640
7641 meta_info.vpts = vpts;
7642 meta_info.vpts_valid = vpts_valid;
7643 meta_info.poc_number =
7644 p_H264_Dpb->mVideo.dec_picture->poc;
7645
7646
7647 wp = hw->sei_user_data_wp;
7648
7649 if (hw->sei_user_data_wp > hw->userdata_info.last_wp)
7650 data_length = wp - hw->userdata_info.last_wp;
7651 else
7652 data_length = wp + hw->userdata_info.buf_len
7653 - hw->userdata_info.last_wp;
7654
7655 if (data_length & 0x7)
7656 data_length = (((data_length + 8) >> 3) << 3);
7657
7658 p_userdata_rec = &hw->ud_record;
7659 p_userdata_rec->meta_info = meta_info;
7660 p_userdata_rec->rec_start = hw->userdata_info.last_wp;
7661 p_userdata_rec->rec_len = data_length;
7662 hw->userdata_info.last_wp = wp;
7663
7664 p_userdata_rec->meta_info.flags |=
7665 p_H264_Dpb->mVideo.dec_picture->pic_struct << 12;
7666
7667 hw->wait_for_udr_send = 1;
7668 vdec_schedule_work(&hw->user_data_ready_work);
7669#endif
7670}
7671
7672
7673static void user_data_ready_notify_work(struct work_struct *work)
7674{
7675 struct vdec_h264_hw_s *hw = container_of(work,
7676 struct vdec_h264_hw_s, user_data_ready_work);
7677
7678
7679 mutex_lock(&hw->userdata_mutex);
7680
7681 hw->userdata_info.records[hw->userdata_info.write_index]
7682 = hw->ud_record;
7683 hw->userdata_info.write_index++;
7684 if (hw->userdata_info.write_index >= USERDATA_FIFO_NUM)
7685 hw->userdata_info.write_index = 0;
7686
7687 mutex_unlock(&hw->userdata_mutex);
7688
7689#ifdef DUMP_USERDATA_RECORD
7690 dump_userdata_record(hw, &hw->ud_record);
7691#endif
7692 vdec_wakeup_userdata_poll(hw_to_vdec(hw));
7693
7694 hw->wait_for_udr_send = 0;
7695}
7696
7697static int vmh264_user_data_read(struct vdec_s *vdec,
7698 struct userdata_param_t *puserdata_para)
7699{
7700 struct vdec_h264_hw_s *hw = NULL;
7701 int rec_ri, rec_wi;
7702 int rec_len;
7703 u8 *rec_data_start;
7704 u8 *pdest_buf;
7705 struct mh264_userdata_record_t *p_userdata_rec;
7706 u32 data_size;
7707 u32 res;
7708 int copy_ok = 1;
7709
7710 hw = (struct vdec_h264_hw_s *)vdec->private;
7711
7712 pdest_buf = puserdata_para->pbuf_addr;
7713
7714 mutex_lock(&hw->userdata_mutex);
7715
7716/*
7717 pr_info("ri = %d, wi = %d\n",
7718 lg_p_mpeg12_userdata_info->read_index,
7719 lg_p_mpeg12_userdata_info->write_index);
7720*/
7721 rec_ri = hw->userdata_info.read_index;
7722 rec_wi = hw->userdata_info.write_index;
7723
7724 if (rec_ri == rec_wi) {
7725 mutex_unlock(&hw->userdata_mutex);
7726 return 0;
7727 }
7728
7729 p_userdata_rec = hw->userdata_info.records + rec_ri;
7730
7731 rec_len = p_userdata_rec->rec_len;
7732 rec_data_start = p_userdata_rec->rec_start + hw->userdata_info.data_buf;
7733/*
7734 pr_info("rec_len:%d, rec_start:%d, buf_len:%d\n",
7735 p_userdata_rec->rec_len,
7736 p_userdata_rec->rec_start,
7737 puserdata_para->buf_len);
7738*/
7739 if (rec_len <= puserdata_para->buf_len) {
7740 /* dvb user data buffer is enought to
7741 copy the whole recored. */
7742 data_size = rec_len;
7743 if (rec_data_start + data_size
7744 > hw->userdata_info.data_buf_end) {
7745 int first_section_len;
7746
7747 first_section_len = hw->userdata_info.buf_len -
7748 p_userdata_rec->rec_start;
7749 res = (u32)copy_to_user((void *)pdest_buf,
7750 (void *)rec_data_start,
7751 first_section_len);
7752 if (res) {
7753 pr_info("p1 read not end res=%d, request=%d\n",
7754 res, first_section_len);
7755 copy_ok = 0;
7756
7757 p_userdata_rec->rec_len -=
7758 first_section_len - res;
7759 p_userdata_rec->rec_start +=
7760 first_section_len - res;
7761 puserdata_para->data_size =
7762 first_section_len - res;
7763 } else {
7764 res = (u32)copy_to_user(
7765 (void *)(pdest_buf+first_section_len),
7766 (void *)hw->userdata_info.data_buf,
7767 data_size - first_section_len);
7768 if (res) {
7769 pr_info("p2 read not end res=%d, request=%d\n",
7770 res, data_size);
7771 copy_ok = 0;
7772 }
7773 p_userdata_rec->rec_len -=
7774 data_size - res;
7775 p_userdata_rec->rec_start =
7776 data_size - first_section_len - res;
7777 puserdata_para->data_size =
7778 data_size - res;
7779 }
7780 } else {
7781 res = (u32)copy_to_user((void *)pdest_buf,
7782 (void *)rec_data_start,
7783 data_size);
7784 if (res) {
7785 pr_info("p3 read not end res=%d, request=%d\n",
7786 res, data_size);
7787 copy_ok = 0;
7788 }
7789 p_userdata_rec->rec_len -= data_size - res;
7790 p_userdata_rec->rec_start += data_size - res;
7791 puserdata_para->data_size = data_size - res;
7792 }
7793
7794 if (copy_ok) {
7795 hw->userdata_info.read_index++;
7796 if (hw->userdata_info.read_index >= USERDATA_FIFO_NUM)
7797 hw->userdata_info.read_index = 0;
7798 }
7799 } else {
7800 /* dvb user data buffer is not enought
7801 to copy the whole recored. */
7802 data_size = puserdata_para->buf_len;
7803 if (rec_data_start + data_size
7804 > hw->userdata_info.data_buf_end) {
7805 int first_section_len;
7806
7807 first_section_len = hw->userdata_info.buf_len -
7808 p_userdata_rec->rec_start;
7809 res = (u32)copy_to_user((void *)pdest_buf,
7810 (void *)rec_data_start,
7811 first_section_len);
7812 if (res) {
7813 pr_info("p4 read not end res=%d, request=%d\n",
7814 res, first_section_len);
7815 copy_ok = 0;
7816 p_userdata_rec->rec_len -=
7817 first_section_len - res;
7818 p_userdata_rec->rec_start +=
7819 first_section_len - res;
7820 puserdata_para->data_size =
7821 first_section_len - res;
7822 } else {
7823 /* first secton copy is ok*/
7824 res = (u32)copy_to_user(
7825 (void *)(pdest_buf+first_section_len),
7826 (void *)hw->userdata_info.data_buf,
7827 data_size - first_section_len);
7828 if (res) {
7829 pr_info("p5 read not end res=%d, request=%d\n",
7830 res,
7831 data_size - first_section_len);
7832 copy_ok = 0;
7833 }
7834
7835 p_userdata_rec->rec_len -=
7836 data_size - res;
7837 p_userdata_rec->rec_start =
7838 data_size - first_section_len - res;
7839 puserdata_para->data_size =
7840 data_size - res;
7841 }
7842 } else {
7843 res = (u32)copy_to_user((void *)pdest_buf,
7844 (void *)rec_data_start,
7845 data_size);
7846 if (res) {
7847 pr_info("p6 read not end res=%d, request=%d\n",
7848 res, data_size);
7849 copy_ok = 0;
7850 }
7851
7852 p_userdata_rec->rec_len -= data_size - res;
7853 p_userdata_rec->rec_start += data_size - res;
7854 puserdata_para->data_size = data_size - res;
7855 }
7856
7857 if (copy_ok) {
7858 hw->userdata_info.read_index++;
7859 if (hw->userdata_info.read_index >= USERDATA_FIFO_NUM)
7860 hw->userdata_info.read_index = 0;
7861 }
7862
7863 }
7864 puserdata_para->meta_info = p_userdata_rec->meta_info;
7865
7866 if (hw->userdata_info.read_index <= hw->userdata_info.write_index)
7867 puserdata_para->meta_info.records_in_que =
7868 hw->userdata_info.write_index -
7869 hw->userdata_info.read_index;
7870 else
7871 puserdata_para->meta_info.records_in_que =
7872 hw->userdata_info.write_index +
7873 USERDATA_FIFO_NUM -
7874 hw->userdata_info.read_index;
7875
7876 puserdata_para->version = (0<<24|0<<16|0<<8|1);
7877
7878 mutex_unlock(&hw->userdata_mutex);
7879
7880 return 1;
7881}
7882
7883static void vmh264_reset_userdata_fifo(struct vdec_s *vdec, int bInit)
7884{
7885 struct vdec_h264_hw_s *hw = NULL;
7886
7887 hw = (struct vdec_h264_hw_s *)vdec->private;
7888
7889 if (hw) {
7890 mutex_lock(&hw->userdata_mutex);
7891 pr_info("vmh264_reset_userdata_fifo: bInit: %d, ri: %d, wi: %d\n",
7892 bInit,
7893 hw->userdata_info.read_index,
7894 hw->userdata_info.write_index);
7895 hw->userdata_info.read_index = 0;
7896 hw->userdata_info.write_index = 0;
7897
7898 if (bInit)
7899 hw->userdata_info.last_wp = 0;
7900 mutex_unlock(&hw->userdata_mutex);
7901 }
7902}
7903
7904static void vmh264_wakeup_userdata_poll(struct vdec_s *vdec)
7905{
7906 amstream_wakeup_userdata_poll(vdec);
7907}
7908
7909#endif
7910
7911
7912static void vh264_work_implement(struct vdec_h264_hw_s *hw,
7913 struct vdec_s *vdec, int from)
7914{
7915 /* finished decoding one frame or error,
7916 * notify vdec core to switch context
7917 */
7918 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
7919 "%s dec_result %d %x %x %x\n",
7920 __func__,
7921 hw->dec_result,
7922 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7923 READ_VREG(VLD_MEM_VIFIFO_WP),
7924 READ_VREG(VLD_MEM_VIFIFO_RP));
7925 if (!hw->mmu_enable) {
7926 mutex_lock(&vmh264_mutex);
7927 dealloc_buf_specs(hw, 0);
7928 mutex_unlock(&vmh264_mutex);
7929 }
7930 hw->dpb.last_dpb_status = hw->dpb.dec_dpb_status;
7931 if (hw->dec_result == DEC_RESULT_CONFIG_PARAM) {
7932 u32 param1 = READ_VREG(AV_SCRATCH_1);
7933 u32 param2 = READ_VREG(AV_SCRATCH_2);
7934 u32 param3 = READ_VREG(AV_SCRATCH_6);
7935 u32 param4 = READ_VREG(AV_SCRATCH_B);
7936
7937 if (vh264_set_params(hw, param1,
7938 param2, param3, param4) < 0)
7939 dpb_print(DECODE_ID(hw), 0, "set parameters error\n");
7940
7941 WRITE_VREG(AV_SCRATCH_0, (hw->max_reference_size<<24) |
7942 (hw->dpb.mDPB.size<<16) |
7943 (hw->dpb.mDPB.size<<8));
7944
7945 if (hw->is_used_v4l) {
7946 struct aml_vcodec_ctx *ctx =
7947 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
7948
7949 if (ctx->param_sets_from_ucode && !hw->v4l_params_parsed) {
7950 struct aml_vdec_ps_infos ps;
7951
7952 ps.visible_width = hw->frame_width;
7953 ps.visible_height = hw->frame_height;
7954 ps.coded_width = ALIGN(hw->frame_width, 64);
7955 ps.coded_height = ALIGN(hw->frame_height, 64);
7956 ps.dpb_size = hw->dpb.mDPB.size;
7957 hw->v4l_params_parsed = true;
7958 vdec_v4l_set_ps_infos(ctx, &ps);
7959 }
7960 }
7961
7962 start_process_time(hw);
7963 return;
7964 } else
7965 if (((hw->dec_result == DEC_RESULT_GET_DATA) ||
7966 (hw->dec_result == DEC_RESULT_GET_DATA_RETRY))
7967 && (hw_to_vdec(hw)->next_status !=
7968 VDEC_STATUS_DISCONNECTED)) {
7969 if (!vdec_has_more_input(vdec)) {
7970 hw->dec_result = DEC_RESULT_EOS;
7971 vdec_schedule_work(&hw->work);
7972 return;
7973 }
7974
7975 if (hw->dec_result == DEC_RESULT_GET_DATA) {
7976 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7977 "%s DEC_RESULT_GET_DATA %x %x %x\n",
7978 __func__,
7979 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7980 READ_VREG(VLD_MEM_VIFIFO_WP),
7981 READ_VREG(VLD_MEM_VIFIFO_RP));
7982 mutex_lock(&hw->chunks_mutex);
7983 vdec_vframe_dirty(vdec, hw->chunk);
7984 hw->chunk = NULL;
7985 mutex_unlock(&hw->chunks_mutex);
7986 vdec_clean_input(vdec);
7987 }
7988 if ((hw->dec_result == DEC_RESULT_GET_DATA_RETRY) &&
7989 ((1000 * (jiffies - hw->get_data_start_time) / HZ)
7990 > get_data_timeout_val)) {
7991 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7992 "%s DEC_RESULT_GET_DATA_RETRY timeout\n",
7993 __func__);
7994 goto result_done;
7995 }
7996 if (is_buffer_available(vdec)) {
7997 int r;
7998 int decode_size;
7999 r = vdec_prepare_input(vdec, &hw->chunk);
8000 if (r < 0 && (hw_to_vdec(hw)->next_status !=
8001 VDEC_STATUS_DISCONNECTED)) {
8002 hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
8003
8004 dpb_print(DECODE_ID(hw),
8005 PRINT_FLAG_VDEC_DETAIL,
8006 "vdec_prepare_input: Insufficient data\n");
8007 vdec_schedule_work(&hw->work);
8008 return;
8009 }
8010 hw->dec_result = DEC_RESULT_NONE;
8011 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8012 "%s: chunk size 0x%x\n",
8013 __func__, hw->chunk->size);
8014
8015 if (dpb_is_debug(DECODE_ID(hw),
8016 PRINT_FRAMEBASE_DATA)) {
8017 int jj;
8018 u8 *data = NULL;
8019
8020 if (!hw->chunk->block->is_mapped)
8021 data = codec_mm_vmap(
8022 hw->chunk->block->start +
8023 hw->chunk->offset, r);
8024 else
8025 data = ((u8 *)
8026 hw->chunk->block->start_virt)
8027 + hw->chunk->offset;
8028
8029 for (jj = 0; jj < r; jj++) {
8030 if ((jj & 0xf) == 0)
8031 dpb_print(DECODE_ID(hw),
8032 PRINT_FRAMEBASE_DATA,
8033 "%06x:", jj);
8034 dpb_print_cont(DECODE_ID(hw),
8035 PRINT_FRAMEBASE_DATA,
8036 "%02x ", data[jj]);
8037 if (((jj + 1) & 0xf) == 0)
8038 dpb_print_cont(DECODE_ID(hw),
8039 PRINT_FRAMEBASE_DATA,
8040 "\n");
8041 }
8042
8043 if (!hw->chunk->block->is_mapped)
8044 codec_mm_unmap_phyaddr(data);
8045 }
8046 WRITE_VREG(POWER_CTL_VLD,
8047 READ_VREG(POWER_CTL_VLD) |
8048 (0 << 10) | (1 << 9) | (1 << 6));
8049 WRITE_VREG(H264_DECODE_INFO, (1<<13));
8050 decode_size = hw->chunk->size +
8051 (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
8052 WRITE_VREG(H264_DECODE_SIZE, decode_size);
8053 WRITE_VREG(VIFF_BIT_CNT, decode_size * 8);
8054 vdec_enable_input(vdec);
8055
8056 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
8057 start_process_time(hw);
8058 } else{
8059 if (hw_to_vdec(hw)->next_status
8060 != VDEC_STATUS_DISCONNECTED) {
8061 hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
8062 vdec_schedule_work(&hw->work);
8063 }
8064 }
8065 return;
8066 } else if (hw->dec_result == DEC_RESULT_DONE) {
8067 /* if (!hw->ctx_valid)
8068 hw->ctx_valid = 1; */
8069result_done:
8070 if (hw->mmu_enable
8071 && hw->frame_busy && hw->frame_done) {
8072 long used_4k_num;
8073 hevc_sao_wait_done(hw);
8074 if (hw->hevc_cur_buf_idx != 0xffff) {
8075 used_4k_num =
8076 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
8077 if (used_4k_num >= 0)
8078 dpb_print(DECODE_ID(hw),
8079 PRINT_FLAG_MMU_DETAIL,
8080 "release unused buf , used_4k_num %ld index %d\n",
8081 used_4k_num, hw->hevc_cur_buf_idx);
8082 hevc_mmu_dma_check(hw_to_vdec(hw));
8083 decoder_mmu_box_free_idx_tail(
8084 hw->mmu_box,
8085 hw->hevc_cur_buf_idx,
8086 used_4k_num);
8087 hw->hevc_cur_buf_idx = 0xffff;
8088 }
8089 }
8090 decode_frame_count[DECODE_ID(hw)]++;
8091 amvdec_stop();
8092 if (!vdec_is_support_4k()) {
8093 if (clk_adj_frame_count < VDEC_CLOCK_ADJUST_FRAME) {
8094 clk_adj_frame_count++;
8095 if (clk_adj_frame_count == VDEC_CLOCK_ADJUST_FRAME)
8096 vdec_source_changed(VFORMAT_H264, 3840, 2160, 60);
8097 }
8098 }
8099 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8100 "%s dec_result %d %x %x %x\n",
8101 __func__,
8102 hw->dec_result,
8103 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8104 READ_VREG(VLD_MEM_VIFIFO_WP),
8105 READ_VREG(VLD_MEM_VIFIFO_RP));
8106 mutex_lock(&hw->chunks_mutex);
8107 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
8108 hw->chunk = NULL;
8109 mutex_unlock(&hw->chunks_mutex);
8110 } else if (hw->dec_result == DEC_RESULT_AGAIN) {
8111 /*
8112 stream base: stream buf empty or timeout
8113 frame base: vdec_prepare_input fail
8114 */
8115 if (!vdec_has_more_input(vdec) && (hw_to_vdec(hw)->next_status !=
8116 VDEC_STATUS_DISCONNECTED)) {
8117 hw->dec_result = DEC_RESULT_EOS;
8118 vdec_schedule_work(&hw->work);
8119 return;
8120 }
8121 hw->next_again_flag = 1;
8122 } else if (hw->dec_result == DEC_RESULT_EOS) {
8123 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8124 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8125 "%s: end of stream\n",
8126 __func__);
8127 amvdec_stop();
8128 if (hw->mmu_enable)
8129 amhevc_stop();
8130 hw->eos = 1;
8131 flush_dpb(p_H264_Dpb);
8132 if (hw->is_used_v4l)
8133 notify_v4l_eos(hw_to_vdec(hw));
8134 mutex_lock(&hw->chunks_mutex);
8135 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
8136 hw->chunk = NULL;
8137 mutex_unlock(&hw->chunks_mutex);
8138 vdec_clean_input(vdec);
8139 } else if (hw->dec_result == DEC_RESULT_FORCE_EXIT) {
8140 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8141 "%s: force exit\n",
8142 __func__);
8143 amvdec_stop();
8144 if (hw->mmu_enable)
8145 amhevc_stop();
8146 if (hw->stat & STAT_ISR_REG) {
8147 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
8148 hw->stat &= ~STAT_ISR_REG;
8149 }
8150 }
8151 WRITE_VREG(ASSIST_MBOX1_MASK, 0);
8152 del_timer_sync(&hw->check_timer);
8153 hw->stat &= ~STAT_TIMER_ARM;
8154
8155 wait_vmh264_search_done(hw);
8156 /* mark itself has all HW resource released and input released */
8157
8158#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8159 if (hw->switch_dvlayer_flag) {
8160 if (vdec->slave)
8161 vdec_set_next_sched(vdec, vdec->slave);
8162 else if (vdec->master)
8163 vdec_set_next_sched(vdec, vdec->master);
8164 } else if (vdec->slave || vdec->master)
8165 vdec_set_next_sched(vdec, vdec);
8166#endif
8167
8168 if (from == 1) {
8169 /* This is a timeout work */
8170 if (work_pending(&hw->work)) {
8171 /*
8172 * The vh264_work arrives at the last second,
8173 * give it a chance to handle the scenario.
8174 */
8175 return;
8176 }
8177 }
8178
8179 /* mark itself has all HW resource released and input released */
8180 if (vdec->parallel_dec == 1) {
8181 if (hw->mmu_enable == 0)
8182 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1);
8183 else
8184 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
8185 } else
8186 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
8187
8188 wake_up_interruptible(&hw->wait_q);
8189
8190 if (hw->is_used_v4l) {
8191 struct aml_vcodec_ctx *ctx =
8192 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8193
8194 if (ctx->param_sets_from_ucode &&
8195 !hw->v4l_params_parsed)
8196 vdec_v4l_write_frame_sync(ctx);
8197 }
8198
8199 if (hw->vdec_cb)
8200 hw->vdec_cb(hw_to_vdec(hw), hw->vdec_cb_arg);
8201}
8202
8203
8204static void vh264_work(struct work_struct *work)
8205{
8206 struct vdec_h264_hw_s *hw = container_of(work,
8207 struct vdec_h264_hw_s, work);
8208 struct vdec_s *vdec = hw_to_vdec(hw);
8209
8210 vh264_work_implement(hw, vdec, 0);
8211}
8212
8213
8214static void vh264_timeout_work(struct work_struct *work)
8215{
8216 struct vdec_h264_hw_s *hw = container_of(work,
8217 struct vdec_h264_hw_s, timeout_work);
8218 struct vdec_s *vdec = hw_to_vdec(hw);
8219
8220 if (work_pending(&hw->work))
8221 return;
8222
8223 vh264_work_implement(hw, vdec, 1);
8224}
8225
8226static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask)
8227{
8228 bool ret = 0;
8229 struct vdec_h264_hw_s *hw =
8230 (struct vdec_h264_hw_s *)vdec->private;
8231 int tvp = vdec_secure(hw_to_vdec(hw)) ?
8232 CODEC_MM_FLAGS_TVP : 0;
8233
8234 if (!hw->first_sc_checked && hw->mmu_enable) {
8235 int size = decoder_mmu_box_sc_check(hw->mmu_box, tvp);
8236 hw->first_sc_checked =1;
8237 dpb_print(DECODE_ID(hw), 0,
8238 "vmh264 cached=%d need_size=%d speed= %d ms\n",
8239 size, (hw->need_cache_size >> PAGE_SHIFT),
8240 (int)(get_jiffies_64() - hw->sc_start_time) * 1000/HZ);
8241 }
8242
8243 if (vdec_stream_based(vdec) && (hw->init_flag == 0)
8244 && pre_decode_buf_level != 0) {
8245 u32 rp, wp, level;
8246
8247 rp = READ_PARSER_REG(PARSER_VIDEO_RP);
8248 wp = READ_PARSER_REG(PARSER_VIDEO_WP);
8249 if (wp < rp)
8250 level = vdec->input.size + wp - rp;
8251 else
8252 level = wp - rp;
8253
8254 if (level < pre_decode_buf_level)
8255 return 0;
8256 }
8257
8258#ifndef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8259 if (vdec->master)
8260 return 0;
8261#endif
8262 if (hw->eos)
8263 return 0;
8264
8265 if (hw->stat & DECODER_FATAL_ERROR_NO_MEM)
8266 return 0;
8267
8268 if (disp_vframe_valve_level &&
8269 kfifo_len(&hw->display_q) >=
8270 disp_vframe_valve_level) {
8271 hw->valve_count--;
8272 if (hw->valve_count <= 0)
8273 hw->valve_count = 2;
8274 else
8275 return 0;
8276 }
8277 if (hw->next_again_flag &&
8278 (!vdec_frame_based(vdec))) {
8279 u32 parser_wr_ptr =
8280 READ_PARSER_REG(PARSER_VIDEO_WP);
8281 if (parser_wr_ptr >= hw->pre_parser_wr_ptr &&
8282 (parser_wr_ptr - hw->pre_parser_wr_ptr) <
8283 again_threshold) {
8284 int r = vdec_sync_input(vdec);
8285 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
8286 "%s buf lelvel:%x\n", __func__, r);
8287 return 0;
8288 }
8289 }
8290
8291 if (h264_debug_flag & 0x20000000) {
8292 /* pr_info("%s, a\n", __func__); */
8293 ret = 1;
8294 } else
8295 ret = is_buffer_available(vdec);
8296
8297#ifdef CONSTRAIN_MAX_BUF_NUM
8298 if (hw->dpb.mDPB.size > 0) { /*make sure initilized*/
8299 if (run_ready_max_vf_only_num > 0 &&
8300 get_vf_ref_only_buf_count(hw) >=
8301 run_ready_max_vf_only_num
8302 )
8303 ret = 0;
8304 if (run_ready_display_q_num > 0 &&
8305 kfifo_len(&hw->display_q) >=
8306 run_ready_display_q_num)
8307 ret = 0;
8308 /*avoid more buffers consumed when
8309 switching resolution*/
8310 if (run_ready_max_buf_num == 0xff &&
8311 get_used_buf_count(hw) >
8312 hw->dpb.mDPB.size)
8313 ret = 0;
8314 else if (run_ready_max_buf_num &&
8315 get_used_buf_count(hw) >=
8316 run_ready_max_buf_num)
8317 ret = 0;
8318 }
8319#endif
8320 if (hw->is_used_v4l) {
8321 struct aml_vcodec_ctx *ctx =
8322 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8323
8324 if (ctx->param_sets_from_ucode &&
8325 !ctx->v4l_codec_ready &&
8326 hw->v4l_params_parsed) {
8327 ret = 0; /*the params has parsed.*/
8328 } else if (!ctx->v4l_codec_dpb_ready) {
8329 if (v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx) <
8330 run_ready_min_buf_num)
8331 ret = 0;
8332 }
8333 }
8334
8335 if (ret)
8336 not_run_ready[DECODE_ID(hw)] = 0;
8337 else
8338 not_run_ready[DECODE_ID(hw)]++;
8339 if (vdec->parallel_dec == 1) {
8340 if (hw->mmu_enable == 0)
8341 return ret ? (CORE_MASK_VDEC_1) : 0;
8342 else
8343 return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
8344 } else
8345 return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
8346}
8347
8348static unsigned char get_data_check_sum
8349 (struct vdec_h264_hw_s *hw, int size)
8350{
8351 int jj;
8352 int sum = 0;
8353 u8 *data = NULL;
8354
8355 if (!hw->chunk->block->is_mapped)
8356 data = codec_mm_vmap(hw->chunk->block->start +
8357 hw->chunk->offset, size);
8358 else
8359 data = ((u8 *)hw->chunk->block->start_virt)
8360 + hw->chunk->offset;
8361
8362 for (jj = 0; jj < size; jj++)
8363 sum += data[jj];
8364
8365 if (!hw->chunk->block->is_mapped)
8366 codec_mm_unmap_phyaddr(data);
8367 return sum;
8368}
8369
8370static void run(struct vdec_s *vdec, unsigned long mask,
8371 void (*callback)(struct vdec_s *, void *), void *arg)
8372{
8373 struct vdec_h264_hw_s *hw =
8374 (struct vdec_h264_hw_s *)vdec->private;
8375 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8376 int size, ret = -1;
8377
8378 run_count[DECODE_ID(hw)]++;
8379 vdec_reset_core(vdec);
8380 if (hw->mmu_enable)
8381 hevc_reset_core(vdec);
8382 hw->vdec_cb_arg = arg;
8383 hw->vdec_cb = callback;
8384
8385 if (kfifo_len(&hw->display_q) > VF_POOL_SIZE) {
8386 hw->reset_bufmgr_flag = 1;
8387 dpb_print(DECODE_ID(hw), 0,
8388 "kfifo len:%d invaild, need bufmgr reset\n",
8389 kfifo_len(&hw->display_q));
8390 }
8391
8392 hw->pre_parser_wr_ptr =
8393 READ_PARSER_REG(PARSER_VIDEO_WP);
8394 hw->next_again_flag = 0;
8395
8396 if (hw->reset_bufmgr_flag ||
8397 ((error_proc_policy & 0x40) &&
8398 p_H264_Dpb->buf_alloc_fail)) {
8399 h264_reset_bufmgr(vdec);
8400 hw->reset_bufmgr_flag = 0;
8401 }
8402
8403 if (h264_debug_cmd & 0xf000) {
8404 if (((h264_debug_cmd >> 12) & 0xf)
8405 == (DECODE_ID(hw) + 1)) {
8406 h264_reconfig(hw);
8407 h264_debug_cmd &= (~0xf000);
8408 }
8409 }
8410 /* hw->chunk = vdec_prepare_input(vdec); */
8411#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8412 if (vdec->slave || vdec->master)
8413 vdec_set_flag(vdec, VDEC_FLAG_SELF_INPUT_CONTEXT);
8414#endif
8415 size = vdec_prepare_input(vdec, &hw->chunk);
8416 if ((size < 0) ||
8417 (input_frame_based(vdec) && hw->chunk == NULL)) {
8418 input_empty[DECODE_ID(hw)]++;
8419 hw->dec_result = DEC_RESULT_AGAIN;
8420
8421 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
8422 "vdec_prepare_input: Insufficient data\n");
8423
8424 vdec_schedule_work(&hw->work);
8425 return;
8426 }
8427 input_empty[DECODE_ID(hw)] = 0;
8428
8429 hw->dec_result = DEC_RESULT_NONE;
8430 hw->get_data_count = 0;
8431#if 0
8432 pr_info("VLD_MEM_VIFIFO_LEVEL = 0x%x, rp = 0x%x, wp = 0x%x\n",
8433 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8434 READ_VREG(VLD_MEM_VIFIFO_RP),
8435 READ_VREG(VLD_MEM_VIFIFO_WP));
8436#endif
8437
8438 if (input_frame_based(vdec) && !vdec_secure(vdec)) {
8439 u8 *data = NULL;
8440
8441 if (!hw->chunk->block->is_mapped)
8442 data = codec_mm_vmap(hw->chunk->block->start +
8443 hw->chunk->offset, size);
8444 else
8445 data = ((u8 *)hw->chunk->block->start_virt)
8446 + hw->chunk->offset;
8447
8448 if (dpb_is_debug(DECODE_ID(hw),
8449 PRINT_FLAG_VDEC_STATUS)
8450 ) {
8451 dpb_print(DECODE_ID(hw), 0,
8452 "%s: size 0x%x sum 0x%x %02x %02x %02x %02x %02x %02x .. %02x %02x %02x %02x\n",
8453 __func__, size, get_data_check_sum(hw, size),
8454 data[0], data[1], data[2], data[3],
8455 data[4], data[5], data[size - 4],
8456 data[size - 3], data[size - 2],
8457 data[size - 1]);
8458 }
8459 if (dpb_is_debug(DECODE_ID(hw),
8460 PRINT_FRAMEBASE_DATA)
8461 ) {
8462 int jj;
8463
8464 for (jj = 0; jj < size; jj++) {
8465 if ((jj & 0xf) == 0)
8466 dpb_print(DECODE_ID(hw),
8467 PRINT_FRAMEBASE_DATA,
8468 "%06x:", jj);
8469 dpb_print_cont(DECODE_ID(hw),
8470 PRINT_FRAMEBASE_DATA,
8471 "%02x ", data[jj]);
8472 if (((jj + 1) & 0xf) == 0)
8473 dpb_print_cont(DECODE_ID(hw),
8474 PRINT_FRAMEBASE_DATA,
8475 "\n");
8476 }
8477 }
8478
8479 if (!hw->chunk->block->is_mapped)
8480 codec_mm_unmap_phyaddr(data);
8481 } else
8482 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8483 "%s: %x %x %x %x %x size 0x%x\n",
8484 __func__,
8485 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8486 READ_VREG(VLD_MEM_VIFIFO_WP),
8487 READ_VREG(VLD_MEM_VIFIFO_RP),
8488 READ_PARSER_REG(PARSER_VIDEO_RP),
8489 READ_PARSER_REG(PARSER_VIDEO_WP),
8490 size);
8491
8492 start_process_time(hw);
8493 if (vdec->mc_loaded) {
8494 /*firmware have load before,
8495 and not changes to another.
8496 ignore reload.
8497 */
8498 WRITE_VREG(AV_SCRATCH_G, hw->reg_g_status);
8499 } else {
8500
8501 ret = amvdec_vdec_loadmc_ex(VFORMAT_H264, "mh264", vdec, hw->fw->data);
8502 if (ret < 0) {
8503 amvdec_enable_flag = false;
8504 amvdec_disable();
8505
8506 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
8507 "MH264 the %s fw loading failed, err: %x\n",
8508 tee_enabled() ? "TEE" : "local", ret);
8509 hw->dec_result = DEC_RESULT_FORCE_EXIT;
8510 vdec_schedule_work(&hw->work);
8511 return;
8512 }
8513 vdec->mc_type = VFORMAT_H264;
8514 hw->reg_g_status = READ_VREG(AV_SCRATCH_G);
8515 if (hw->mmu_enable) {
8516 ret = amhevc_loadmc_ex(VFORMAT_H264, "mh264_mmu",
8517 hw->fw_mmu->data);
8518 if (ret < 0) {
8519 amvdec_enable_flag = false;
8520 amhevc_disable();
8521
8522 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
8523 "MH264_MMU the %s fw loading failed, err: %x\n",
8524 tee_enabled() ? "TEE" : "local", ret);
8525 hw->dec_result = DEC_RESULT_FORCE_EXIT;
8526 vdec_schedule_work(&hw->work);
8527 return;
8528 }
8529 vdec->mc_type = ((1 << 16) | VFORMAT_H264);
8530 }
8531 vdec->mc_loaded = 1;
8532 }
8533 vmh264_reset_udr_mgr(hw);
8534
8535 if (vh264_hw_ctx_restore(hw) < 0) {
8536 vdec_schedule_work(&hw->work);
8537 return;
8538 }
8539 if (input_frame_based(vdec)) {
8540 int decode_size = 0;
8541
8542 decode_size = hw->chunk->size +
8543 (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
8544 WRITE_VREG(H264_DECODE_INFO, (1<<13));
8545 WRITE_VREG(H264_DECODE_SIZE, decode_size);
8546 WRITE_VREG(VIFF_BIT_CNT, decode_size * 8);
8547 } else {
8548 if (size <= 0)
8549 size = 0x7fffffff; /*error happen*/
8550 WRITE_VREG(H264_DECODE_INFO, (1<<13));
8551 WRITE_VREG(H264_DECODE_SIZE, size);
8552 WRITE_VREG(VIFF_BIT_CNT, size * 8);
8553 }
8554 config_aux_buf(hw);
8555 config_decode_mode(hw);
8556 vdec_enable_input(vdec);
8557 WRITE_VREG(NAL_SEARCH_CTL, 0);
8558 hw->sei_data_len = 0;
8559 if (enable_itu_t35)
8560 WRITE_VREG(NAL_SEARCH_CTL, READ_VREG(NAL_SEARCH_CTL) | 0x1);
8561 if (!hw->init_flag) {
8562 if (hw->mmu_enable)
8563 WRITE_VREG(NAL_SEARCH_CTL,
8564 READ_VREG(NAL_SEARCH_CTL) | 0x2);
8565 else
8566 WRITE_VREG(NAL_SEARCH_CTL,
8567 READ_VREG(NAL_SEARCH_CTL) & (~0x2));
8568 }
8569 if (udebug_flag)
8570 WRITE_VREG(AV_SCRATCH_K, udebug_flag);
8571 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
8572
8573 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
8574
8575 if (hw->mmu_enable)
8576 SET_VREG_MASK(VDEC_ASSIST_MMC_CTRL1, 1 << 3);
8577 else
8578 CLEAR_VREG_MASK(VDEC_ASSIST_MMC_CTRL1, 1 << 3);
8579 }
8580 amvdec_start();
8581 if (hw->mmu_enable /*&& !hw->frame_busy && !hw->frame_done*/) {
8582 WRITE_VREG(HEVC_ASSIST_SCRATCH_0, 0x0);
8583 amhevc_start();
8584 if (hw->config_bufmgr_done) {
8585 hevc_mcr_sao_global_hw_init(hw,
8586 (hw->mb_width << 4), (hw->mb_height << 4));
8587 hevc_mcr_config_canv2axitbl(hw, 1);
8588 }
8589 }
8590
8591 /* if (hw->init_flag) { */
8592 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
8593 /* } */
8594
8595 hw->init_flag = 1;
8596}
8597
8598static void clear_refer_bufs(struct vdec_h264_hw_s *hw)
8599{
8600 int i;
8601
8602 mutex_lock(&vmh264_mutex);
8603 dealloc_buf_specs(hw, 1);
8604 mutex_unlock(&vmh264_mutex);
8605
8606 INIT_KFIFO(hw->display_q);
8607 INIT_KFIFO(hw->newframe_q);
8608
8609 for (i = 0; i < VF_POOL_SIZE; i++) {
8610 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
8611 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8612 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
8613 kfifo_put(&hw->newframe_q, vf);
8614 }
8615}
8616
8617static void reset(struct vdec_s *vdec)
8618{
8619 struct vdec_h264_hw_s *hw =
8620 (struct vdec_h264_hw_s *)vdec->private;
8621
8622 pr_info("vmh264 reset\n");
8623
8624 cancel_work_sync(&hw->work);
8625 cancel_work_sync(&hw->notify_work);
8626 if (hw->stat & STAT_VDEC_RUN) {
8627 amhevc_stop();
8628 hw->stat &= ~STAT_VDEC_RUN;
8629 }
8630
8631 if (hw->stat & STAT_TIMER_ARM) {
8632 del_timer_sync(&hw->check_timer);
8633 hw->stat &= ~STAT_TIMER_ARM;
8634 }
8635 hw->eos = 0;
8636 hw->decode_pic_count = 0;
8637 hw->dec_result = DEC_RESULT_NONE;
8638
8639 clear_refer_bufs(hw);
8640 reset_process_time(hw);
8641 h264_reset_bufmgr(vdec);
8642
8643 dpb_print(DECODE_ID(hw), 0, "%s\n", __func__);
8644}
8645
8646static void h264_reconfig(struct vdec_h264_hw_s *hw)
8647{
8648 int i;
8649 unsigned long flags;
8650 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8651 struct vdec_s *vdec = hw_to_vdec(hw);
8652 dpb_print(DECODE_ID(hw), 0,
8653 "%s\n", __func__);
8654 /* after calling flush_dpb() and bufmgr_h264_remove_unused_frame(),
8655 all buffers are in display queue (used == 2),
8656 or free (used == 0)
8657 */
8658 if (dpb_is_debug(DECODE_ID(hw),
8659 PRINT_FLAG_DUMP_BUFSPEC))
8660 dump_bufspec(hw, "pre h264_reconfig");
8661
8662 flush_dpb(p_H264_Dpb);
8663 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 0);
8664
8665 if (hw->collocate_cma_alloc_addr) {
8666 decoder_bmmu_box_free_idx(
8667 hw->bmmu_box,
8668 BMMU_REF_IDX);
8669 hw->collocate_cma_alloc_addr = 0;
8670 hw->dpb.colocated_mv_addr_start = 0;
8671 hw->dpb.colocated_mv_addr_end = 0;
8672 }
8673 spin_lock_irqsave(&hw->bufspec_lock, flags);
8674 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8675 if (vdec->parallel_dec == 1) {
8676 vdec->free_canvas_ex(hw->buffer_spec[i].y_canvas_index, vdec->id);
8677 vdec->free_canvas_ex(hw->buffer_spec[i].u_canvas_index, vdec->id);
8678 vdec->free_canvas_ex(hw->buffer_spec[i].v_canvas_index, vdec->id);
8679 hw->buffer_spec[i].y_canvas_index = -1;
8680 hw->buffer_spec[i].u_canvas_index = -1;
8681 hw->buffer_spec[i].v_canvas_index = -1;
8682#ifdef VDEC_DW
8683 if (IS_VDEC_DW(hw)) {
8684 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_y_canvas_index, vdec->id);
8685 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_u_canvas_index, vdec->id);
8686 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_v_canvas_index, vdec->id);
8687 hw->buffer_spec[i].vdec_dw_y_canvas_index = -1;
8688 hw->buffer_spec[i].vdec_dw_u_canvas_index = -1;
8689 hw->buffer_spec[i].vdec_dw_v_canvas_index = -1;
8690#endif
8691 }
8692 }
8693 /*make sure buffers not put back to bufmgr when
8694 vf_put is called*/
8695 if (hw->buffer_spec[i].used == 2)
8696 hw->buffer_spec[i].used = 3;
8697
8698 /* ready to release "free buffers"
8699 */
8700 if (hw->buffer_spec[i].used == 0)
8701 hw->buffer_spec[i].used = 4;
8702
8703 hw->buffer_spec[i].canvas_pos = -1;
8704 }
8705 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
8706 hw->has_i_frame = 0;
8707 hw->config_bufmgr_done = 0;
8708
8709 if (hw->is_used_v4l) {
8710 mutex_lock(&vmh264_mutex);
8711 dealloc_buf_specs(hw, 1);
8712 mutex_unlock(&vmh264_mutex);
8713 }
8714
8715 if (dpb_is_debug(DECODE_ID(hw),
8716 PRINT_FLAG_DUMP_BUFSPEC))
8717 dump_bufspec(hw, "after h264_reconfig");
8718}
8719
8720#ifdef ERROR_HANDLE_TEST
8721static void h264_clear_dpb(struct vdec_h264_hw_s *hw)
8722{
8723 int i;
8724 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8725 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8726 "%s\n", __func__);
8727 remove_dpb_pictures(p_H264_Dpb);
8728 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8729 /*make sure buffers not put back to bufmgr when
8730 vf_put is called*/
8731 if (hw->buffer_spec[i].used == 2)
8732 hw->buffer_spec[i].used = 5;
8733 }
8734
8735}
8736#endif
8737
8738static void h264_reset_bufmgr(struct vdec_s *vdec)
8739{
8740 ulong timeout;
8741 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
8742#if 0
8743 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8744 int actual_dpb_size, max_reference_size;
8745 int reorder_pic_num;
8746 unsigned int colocated_buf_size;
8747 unsigned int colocated_mv_addr_start;
8748 unsigned int colocated_mv_addr_end;
8749 dpb_print(DECODE_ID(hw), 0,
8750 "%s\n", __func__);
8751
8752 for (i = 0; i < VF_POOL_SIZE; i++)
8753 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8754
8755 actual_dpb_size = p_H264_Dpb->mDPB.size;
8756 max_reference_size = p_H264_Dpb->max_reference_size;
8757 reorder_pic_num = p_H264_Dpb->reorder_pic_num;
8758
8759 colocated_buf_size = p_H264_Dpb->colocated_buf_size;
8760 colocated_mv_addr_start = p_H264_Dpb->colocated_mv_addr_start;
8761 colocated_mv_addr_end = p_H264_Dpb->colocated_mv_addr_end;
8762
8763 hw->cur_pool++;
8764 if (hw->cur_pool >= VF_POOL_NUM)
8765 hw->cur_pool = 0;
8766
8767 INIT_KFIFO(hw->display_q);
8768 INIT_KFIFO(hw->newframe_q);
8769
8770 for (i = 0; i < VF_POOL_SIZE; i++) {
8771 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
8772 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8773 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
8774 kfifo_put(&hw->newframe_q, vf);
8775 }
8776
8777 for (i = 0; i < BUFSPEC_POOL_SIZE; i++)
8778 hw->buffer_spec[i].used = 0;
8779
8780 dpb_init_global(&hw->dpb,
8781 DECODE_ID(hw), 0, 0);
8782 p_H264_Dpb->mDPB.size = actual_dpb_size;
8783 p_H264_Dpb->max_reference_size = max_reference_size;
8784 p_H264_Dpb->reorder_pic_num = reorder_pic_num;
8785
8786 p_H264_Dpb->colocated_buf_size = colocated_buf_size;
8787 p_H264_Dpb->colocated_mv_addr_start = colocated_mv_addr_start;
8788 p_H264_Dpb->colocated_mv_addr_end = colocated_mv_addr_end;
8789
8790 p_H264_Dpb->fast_output_enable = fast_output_enable;
8791 hw->has_i_frame = 0;
8792#else
8793 dpb_print(DECODE_ID(hw), 0,
8794 "%s frame count %d to skip %d\n\n",
8795 __func__, hw->decode_pic_count+1,
8796 hw->skip_frame_count);
8797
8798 timeout = jiffies + HZ;
8799 while (kfifo_len(&hw->display_q) > 0) {
8800 if (time_after(jiffies, timeout))
8801 break;
8802 schedule();
8803 }
8804
8805 vf_notify_receiver(vdec->vf_provider_name, VFRAME_EVENT_PROVIDER_RESET, NULL);
8806
8807 buf_spec_init(hw);
8808
8809 vh264_local_init(hw, true);
8810 /*hw->decode_pic_count = 0;
8811 hw->seq_info2 = 0;*/
8812
8813 if (vh264_set_params(hw,
8814 hw->cfg_param1,
8815 hw->cfg_param2,
8816 hw->cfg_param3,
8817 hw->cfg_param4) < 0)
8818 hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
8819
8820 /*drop 3 frames after reset bufmgr if bit0 is set 1 */
8821 if (first_i_policy & 0x01)
8822 hw->first_i_policy = (3 << 8) | first_i_policy;
8823
8824 hw->init_flag = 1;
8825 hw->reset_bufmgr_count++;
8826#endif
8827}
8828
8829int ammvdec_h264_mmu_init(struct vdec_h264_hw_s *hw)
8830{
8831 int ret = -1;
8832 int tvp_flag = vdec_secure(hw_to_vdec(hw)) ?
8833 CODEC_MM_FLAGS_TVP : 0;
8834 int buf_size = 64;
8835
8836 pr_debug("ammvdec_h264_mmu_init tvp = 0x%x mmu_enable %d\n",
8837 tvp_flag, hw->mmu_enable);
8838 hw->need_cache_size = buf_size * SZ_1M;
8839 hw->sc_start_time = get_jiffies_64();
8840 if (hw->mmu_enable && !hw->mmu_box) {
8841 hw->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME,
8842 hw->id,
8843 MMU_MAX_BUFFERS,
8844 hw->need_cache_size,
8845 tvp_flag);
8846 if (!hw->mmu_box) {
8847 pr_err("h264 4k alloc mmu box failed!!\n");
8848 return -1;
8849 }
8850 ret = 0;
8851 }
8852 if (!hw->bmmu_box) {
8853 hw->bmmu_box = decoder_bmmu_box_alloc_box(
8854 DRIVER_NAME,
8855 hw->id,
8856 BMMU_MAX_BUFFERS,
8857 4 + PAGE_SHIFT,
8858 CODEC_MM_FLAGS_CMA_CLEAR |
8859 CODEC_MM_FLAGS_FOR_VDECODER |
8860 tvp_flag);
8861 if (hw->bmmu_box)
8862 ret = 0;
8863 }
8864 return ret;
8865}
8866int ammvdec_h264_mmu_release(struct vdec_h264_hw_s *hw)
8867{
8868 if (hw->mmu_box) {
8869 decoder_mmu_box_free(hw->mmu_box);
8870 hw->mmu_box = NULL;
8871 }
8872 if (hw->bmmu_box) {
8873 decoder_bmmu_box_free(hw->bmmu_box);
8874 hw->bmmu_box = NULL;
8875 }
8876 return 0;
8877}
8878
8879static int ammvdec_h264_probe(struct platform_device *pdev)
8880{
8881 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
8882 struct vdec_h264_hw_s *hw = NULL;
8883 char *tmpbuf;
8884 int config_val;
8885
8886 if (pdata == NULL) {
8887 pr_info("\nammvdec_h264 memory resource undefined.\n");
8888 return -EFAULT;
8889 }
8890 pr_info("%s:cts test\n",__func__);
8891
8892 hw = (struct vdec_h264_hw_s *)h264_alloc_hw_stru(&pdev->dev,
8893 sizeof(struct vdec_h264_hw_s), GFP_KERNEL);
8894 if (hw == NULL) {
8895 pr_info("\nammvdec_h264 device data allocation failed\n");
8896 return -ENOMEM;
8897 }
8898 hw->id = pdev->id;
8899 hw->platform_dev = pdev;
8900
8901 /* the ctx from v4l2 driver. */
8902 hw->v4l2_ctx = pdata->private;
8903
8904 platform_set_drvdata(pdev, pdata);
8905
8906 hw->mmu_enable = 0;
8907 hw->first_head_check_flag = 0;
8908 hw->new_iframe_flag = 0;
8909 hw->ref_err_flush_dpb_flag = 0;
8910
8911 if (pdata->sys_info)
8912 hw->vh264_amstream_dec_info = *pdata->sys_info;
8913
8914 if (force_enable_mmu && pdata->sys_info &&
8915 (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TXLX) &&
8916 (get_cpu_major_id() != AM_MESON_CPU_MAJOR_ID_GXLX) &&
8917 (pdata->sys_info->height * pdata->sys_info->width
8918 > 1920 * 1088))
8919 hw->mmu_enable = 1;
8920
8921 if (hw->mmu_enable &&
8922 (pdata->frame_base_video_path == FRAME_BASE_PATH_IONVIDEO)) {
8923 hw->mmu_enable = 0;
8924 pr_info("ionvideo needs disable mmu, path= %d \n",
8925 pdata->frame_base_video_path);
8926 }
8927
8928 if (ammvdec_h264_mmu_init(hw)) {
8929 h264_free_hw_stru(&pdev->dev, (void *)hw);
8930 pr_info("\nammvdec_h264 mmu alloc failed!\n");
8931 return -ENOMEM;
8932 }
8933
8934 if (pdata->config_len) {
8935 /*use ptr config for doubel_write_mode, etc*/
8936 if (get_config_int(pdata->config,
8937 "mh264_double_write_mode", &config_val) == 0)
8938 hw->double_write_mode = config_val;
8939 else
8940 hw->double_write_mode = double_write_mode;
8941
8942 if (get_config_int(pdata->config,
8943 "parm_v4l_codec_enable",
8944 &config_val) == 0)
8945 hw->is_used_v4l = config_val;
8946
8947 if (get_config_int(pdata->config,
8948 "parm_v4l_buffer_margin",
8949 &config_val) == 0)
8950 hw->reorder_dpb_size_margin = config_val;
8951
8952 if (get_config_int(pdata->config,
8953 "parm_v4l_canvas_mem_mode",
8954 &config_val) == 0)
8955 hw->canvas_mode = config_val;
8956 } else
8957 hw->double_write_mode = double_write_mode;
8958
8959 if (!hw->is_used_v4l) {
8960 hw->reorder_dpb_size_margin = reorder_dpb_size_margin;
8961 hw->canvas_mode = mem_map_mode;
8962
8963 if ((h264_debug_flag & IGNORE_PARAM_FROM_CONFIG) == 0)
8964 hw->canvas_mode = pdata->canvas_mode;
8965 }
8966
8967 if (hw->mmu_enable)
8968 hw->double_write_mode &= 0xffff;
8969
8970 if (pdata->parallel_dec == 1) {
8971 int i;
8972 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8973 hw->buffer_spec[i].y_canvas_index = -1;
8974 hw->buffer_spec[i].u_canvas_index = -1;
8975 hw->buffer_spec[i].v_canvas_index = -1;
8976#ifdef VDEC_DW
8977 if (IS_VDEC_DW(hw)) {
8978 hw->buffer_spec[i].vdec_dw_y_canvas_index = -1;
8979 hw->buffer_spec[i].vdec_dw_u_canvas_index = -1;
8980 hw->buffer_spec[i].vdec_dw_v_canvas_index = -1;
8981 }
8982#endif
8983 }
8984 }
8985
8986 dpb_print(DECODE_ID(hw), 0,
8987 "%s mmu_enable %d double_write_mode 0x%x\n",
8988 __func__, hw->mmu_enable, hw->double_write_mode);
8989
8990 pdata->private = hw;
8991 pdata->dec_status = dec_status;
8992 pdata->set_trickmode = vmh264_set_trickmode;
8993 pdata->run_ready = run_ready;
8994 pdata->run = run;
8995 pdata->reset = reset;
8996 pdata->irq_handler = vh264_isr;
8997 pdata->threaded_irq_handler = vh264_isr_thread_fn;
8998 pdata->dump_state = vmh264_dump_state;
8999
9000#ifdef MH264_USERDATA_ENABLE
9001 pdata->wakeup_userdata_poll = vmh264_wakeup_userdata_poll;
9002 pdata->user_data_read = vmh264_user_data_read;
9003 pdata->reset_userdata_fifo = vmh264_reset_userdata_fifo;
9004#else
9005 pdata->wakeup_userdata_poll = NULL;
9006 pdata->user_data_read = NULL;
9007 pdata->reset_userdata_fifo = NULL;
9008#endif
9009 if (pdata->use_vfm_path) {
9010 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
9011 VFM_DEC_PROVIDER_NAME);
9012 hw->frameinfo_enable = 1;
9013 }
9014#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9015 else if (vdec_dual(pdata)) {
9016 if (dv_toggle_prov_name) /*debug purpose*/
9017 snprintf(pdata->vf_provider_name,
9018 VDEC_PROVIDER_NAME_SIZE,
9019 (pdata->master) ? VFM_DEC_DVBL_PROVIDER_NAME :
9020 VFM_DEC_DVEL_PROVIDER_NAME);
9021 else
9022 snprintf(pdata->vf_provider_name,
9023 VDEC_PROVIDER_NAME_SIZE,
9024 (pdata->master) ? VFM_DEC_DVEL_PROVIDER_NAME :
9025 VFM_DEC_DVBL_PROVIDER_NAME);
9026 }
9027#endif
9028 else
9029 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
9030 PROVIDER_NAME ".%02x", pdev->id & 0xff);
9031
9032 vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
9033 &vf_provider_ops, pdata);
9034
9035 platform_set_drvdata(pdev, pdata);
9036
9037 buf_spec_init(hw);
9038
9039 hw->platform_dev = pdev;
9040
9041#ifdef DUMP_USERDATA_RECORD
9042 vmh264_init_userdata_dump();
9043 vmh264_reset_user_data_buf();
9044#endif
9045 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_DPB_IDX,
9046 V_BUF_ADDR_OFFSET, DRIVER_NAME, &hw->cma_alloc_addr) < 0) {
9047 h264_free_hw_stru(&pdev->dev, (void *)hw);
9048 pdata->dec_status = NULL;
9049 return -ENOMEM;
9050 }
9051
9052 hw->buf_offset = hw->cma_alloc_addr - DEF_BUF_START_ADDR +
9053 DCAC_READ_MARGIN;
9054 if (hw->mmu_enable) {
9055 u32 extif_size = EXTIF_BUF_SIZE;
9056 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A)
9057 extif_size <<= 1;
9058 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_EXTIF_IDX,
9059 extif_size, DRIVER_NAME, &hw->extif_addr) < 0) {
9060 h264_free_hw_stru(&pdev->dev, (void *)hw);
9061 pdata->dec_status = NULL;
9062 return -ENOMEM;
9063 }
9064 }
9065 if (!vdec_secure(pdata)) {
9066#if 1
9067 /*init internal buf*/
9068 tmpbuf = (char *)codec_mm_phys_to_virt(hw->cma_alloc_addr);
9069 if (tmpbuf) {
9070 memset(tmpbuf, 0, V_BUF_ADDR_OFFSET);
9071 codec_mm_dma_flush(tmpbuf,
9072 V_BUF_ADDR_OFFSET,
9073 DMA_TO_DEVICE);
9074 } else {
9075 tmpbuf = codec_mm_vmap(hw->cma_alloc_addr,
9076 V_BUF_ADDR_OFFSET);
9077 if (tmpbuf) {
9078 memset(tmpbuf, 0, V_BUF_ADDR_OFFSET);
9079 codec_mm_dma_flush(tmpbuf,
9080 V_BUF_ADDR_OFFSET,
9081 DMA_TO_DEVICE);
9082 codec_mm_unmap_phyaddr(tmpbuf);
9083 }
9084 }
9085#else
9086 /*init sps/pps internal buf 64k*/
9087 tmpbuf = (char *)codec_mm_phys_to_virt(hw->cma_alloc_addr
9088 + (mem_sps_base - DEF_BUF_START_ADDR));
9089 memset(tmpbuf, 0, 0x10000);
9090 dma_sync_single_for_device(amports_get_dma_device(),
9091 hw->cma_alloc_addr +
9092 (mem_sps_base - DEF_BUF_START_ADDR),
9093 0x10000, DMA_TO_DEVICE);
9094#endif
9095 }
9096 /**/
9097
9098#if 0
9099 if (NULL == hw->sei_data_buffer) {
9100 hw->sei_data_buffer =
9101 dma_alloc_coherent(amports_get_dma_device(),
9102 USER_DATA_SIZE,
9103 &hw->sei_data_buffer_phys, GFP_KERNEL);
9104 if (!hw->sei_data_buffer) {
9105 pr_info("%s: Can not allocate sei_data_buffer\n",
9106 __func__);
9107 ammvdec_h264_mmu_release(hw);
9108 h264_free_hw_stru(&pdev->dev, (void *)hw);
9109 return -ENOMEM;
9110 }
9111 /* pr_info("buffer 0x%x, phys 0x%x, remap 0x%x\n",
9112 sei_data_buffer, sei_data_buffer_phys,
9113 (u32)sei_data_buffer_remap); */
9114 }
9115#endif
9116 dpb_print(DECODE_ID(hw), 0, "ammvdec_h264 mem-addr=%lx,buff_offset=%x,buf_start=%lx\n",
9117 pdata->mem_start, hw->buf_offset, hw->cma_alloc_addr);
9118
9119 if (vdec_is_support_4k() ||
9120 (clk_adj_frame_count > (VDEC_CLOCK_ADJUST_FRAME - 1)))
9121 vdec_source_changed(VFORMAT_H264, 3840, 2160, 60);
9122 else if (pdata->sys_info->height * pdata->sys_info->width <= 1280 * 720)
9123 {
9124 vdec_source_changed(VFORMAT_H264, 1280, 720, 29);
9125 }else
9126 {
9127 vdec_source_changed(VFORMAT_H264, 1920, 1080, 29);
9128 }
9129
9130 if (vh264_init(hw) < 0) {
9131 pr_info("\nammvdec_h264 init failed.\n");
9132 ammvdec_h264_mmu_release(hw);
9133 h264_free_hw_stru(&pdev->dev, (void *)hw);
9134 pdata->dec_status = NULL;
9135 return -ENODEV;
9136 }
9137#ifdef MH264_USERDATA_ENABLE
9138 vmh264_crate_userdata_manager(hw,
9139 hw->sei_user_data_buffer,
9140 USER_DATA_SIZE);
9141#endif
9142
9143 vdec_set_prepare_level(pdata, start_decode_buf_level);
9144 if (pdata->parallel_dec == 1) {
9145 if (hw->mmu_enable == 0)
9146 vdec_core_request(pdata, CORE_MASK_VDEC_1);
9147 else {
9148 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9149 | CORE_MASK_COMBINE);
9150 }
9151 } else
9152 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9153 | CORE_MASK_COMBINE);
9154
9155 atomic_set(&hw->vh264_active, 1);
9156
9157 return 0;
9158}
9159
9160static int ammvdec_h264_remove(struct platform_device *pdev)
9161{
9162 struct vdec_h264_hw_s *hw =
9163 (struct vdec_h264_hw_s *)
9164 (((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
9165 int i;
9166
9167 struct vdec_s *vdec = hw_to_vdec(hw);
9168
9169 if (vdec->next_status == VDEC_STATUS_DISCONNECTED
9170 && (vdec->status == VDEC_STATUS_ACTIVE)) {
9171 dpb_print(DECODE_ID(hw), 0,
9172 "%s force exit %d\n", __func__, __LINE__);
9173 hw->dec_result = DEC_RESULT_FORCE_EXIT;
9174 vdec_schedule_work(&hw->work);
9175 wait_event_interruptible_timeout(hw->wait_q,
9176 (vdec->status == VDEC_STATUS_CONNECTED),
9177 msecs_to_jiffies(1000)); /* wait for work done */
9178 }
9179
9180 for (i = 0; i < BUFSPEC_POOL_SIZE; i++)
9181 release_aux_data(hw, i);
9182
9183 atomic_set(&hw->vh264_active, 0);
9184
9185 if (hw->stat & STAT_TIMER_ARM) {
9186 del_timer_sync(&hw->check_timer);
9187 hw->stat &= ~STAT_TIMER_ARM;
9188 }
9189
9190 vh264_stop(hw);
9191#ifdef MH264_USERDATA_ENABLE
9192#ifdef DUMP_USERDATA_RECORD
9193 vmh264_dump_userdata();
9194#endif
9195 vmh264_destroy_userdata_manager(hw);
9196#endif
9197 /* vdec_source_changed(VFORMAT_H264, 0, 0, 0); */
9198
9199 atomic_set(&hw->vh264_active, 0);
9200 if (vdec->parallel_dec == 1) {
9201 if (hw->mmu_enable == 0)
9202 vdec_core_release(vdec, CORE_MASK_VDEC_1);
9203 else
9204 vdec_core_release(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC |
9205 CORE_MASK_COMBINE);
9206 } else
9207 vdec_core_release(hw_to_vdec(hw), CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
9208
9209 vdec_set_status(hw_to_vdec(hw), VDEC_STATUS_DISCONNECTED);
9210 if (vdec->parallel_dec == 1) {
9211 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
9212 vdec->free_canvas_ex(hw->buffer_spec[i].y_canvas_index, vdec->id);
9213 vdec->free_canvas_ex(hw->buffer_spec[i].u_canvas_index, vdec->id);
9214 vdec->free_canvas_ex(hw->buffer_spec[i].v_canvas_index, vdec->id);
9215 if (IS_VDEC_DW(hw)) {
9216 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_y_canvas_index, vdec->id);
9217 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_u_canvas_index, vdec->id);
9218 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_v_canvas_index, vdec->id);
9219 }
9220 }
9221 }
9222
9223 ammvdec_h264_mmu_release(hw);
9224 h264_free_hw_stru(&pdev->dev, (void *)hw);
9225 clk_adj_frame_count = 0;
9226
9227 return 0;
9228}
9229
9230/****************************************/
9231#ifdef CONFIG_PM
9232static int mh264_suspend(struct device *dev)
9233{
9234 amvdec_suspend(to_platform_device(dev), dev->power.power_state);
9235 return 0;
9236}
9237
9238static int mh264_resume(struct device *dev)
9239{
9240 amvdec_resume(to_platform_device(dev));
9241 return 0;
9242}
9243
9244static const struct dev_pm_ops mh264_pm_ops = {
9245 SET_SYSTEM_SLEEP_PM_OPS(mh264_suspend, mh264_resume)
9246};
9247#endif
9248
9249static struct platform_driver ammvdec_h264_driver = {
9250 .probe = ammvdec_h264_probe,
9251 .remove = ammvdec_h264_remove,
9252 .driver = {
9253 .name = DRIVER_NAME,
9254#ifdef CONFIG_PM
9255 .pm = &mh264_pm_ops,
9256#endif
9257 }
9258};
9259
9260static struct codec_profile_t ammvdec_h264_profile = {
9261 .name = "mh264",
9262 .profile = ""
9263};
9264
9265static struct mconfig hm264_configs[] = {
9266 MC_PU32("h264_debug_flag", &h264_debug_flag),
9267 MC_PI32("start_decode_buf_level", &start_decode_buf_level),
9268 MC_PU32("fixed_frame_rate_mode", &fixed_frame_rate_mode),
9269 MC_PU32("decode_timeout_val", &decode_timeout_val),
9270 MC_PU32("reorder_dpb_size_margin", &reorder_dpb_size_margin),
9271 MC_PU32("reference_buf_margin", &reference_buf_margin),
9272 MC_PU32("radr", &radr),
9273 MC_PU32("rval", &rval),
9274 MC_PU32("h264_debug_mask", &h264_debug_mask),
9275 MC_PU32("h264_debug_cmd", &h264_debug_cmd),
9276 MC_PI32("force_rate_streambase", &force_rate_streambase),
9277 MC_PI32("dec_control", &dec_control),
9278 MC_PI32("force_rate_framebase", &force_rate_framebase),
9279 MC_PI32("force_disp_bufspec_num", &force_disp_bufspec_num),
9280 MC_PU32("prefix_aux_buf_size", &prefix_aux_buf_size),
9281 MC_PU32("suffix_aux_buf_size", &suffix_aux_buf_size),
9282#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9283 MC_PU32("reorder_dpb_size_margin_dv", &reorder_dpb_size_margin_dv),
9284 MC_PU32("dv_toggle_prov_name", &dv_toggle_prov_name),
9285 MC_PU32("dolby_meta_with_el", &dolby_meta_with_el),
9286#endif
9287 MC_PU32("i_only_flag", &i_only_flag),
9288 MC_PU32("force_rate_streambase", &force_rate_streambase),
9289};
9290static struct mconfig_node hm264_node;
9291
9292
9293static int __init ammvdec_h264_driver_init_module(void)
9294{
9295 pr_info("ammvdec_h264 module init\n");
9296 if (platform_driver_register(&ammvdec_h264_driver)) {
9297 pr_info("failed to register ammvdec_h264 driver\n");
9298 return -ENODEV;
9299 }
9300
9301 if (vdec_is_support_4k()) {
9302 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TXLX) {
9303 ammvdec_h264_profile.profile =
9304 "4k, dwrite, compressed";
9305 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXTVBB) {
9306 ammvdec_h264_profile.profile = "4k";
9307 }
9308 }
9309
9310 vcodec_profile_register(&ammvdec_h264_profile);
9311 INIT_REG_NODE_CONFIGS("media.decoder", &hm264_node,
9312 "mh264", hm264_configs, CONFIG_FOR_RW);
9313 return 0;
9314}
9315
9316static void __exit ammvdec_h264_driver_remove_module(void)
9317{
9318 pr_info("ammvdec_h264 module remove.\n");
9319
9320 platform_driver_unregister(&ammvdec_h264_driver);
9321}
9322
9323/****************************************/
9324module_param(h264_debug_flag, uint, 0664);
9325MODULE_PARM_DESC(h264_debug_flag, "\n ammvdec_h264 h264_debug_flag\n");
9326
9327module_param(start_decode_buf_level, int, 0664);
9328MODULE_PARM_DESC(start_decode_buf_level,
9329 "\n ammvdec_h264 start_decode_buf_level\n");
9330
9331module_param(pre_decode_buf_level, int, 0664);
9332MODULE_PARM_DESC(pre_decode_buf_level, "\n ammvdec_h264 pre_decode_buf_level\n");
9333
9334module_param(fixed_frame_rate_mode, uint, 0664);
9335MODULE_PARM_DESC(fixed_frame_rate_mode, "\namvdec_h264 fixed_frame_rate_mode\n");
9336
9337module_param(decode_timeout_val, uint, 0664);
9338MODULE_PARM_DESC(decode_timeout_val, "\n amvdec_h264 decode_timeout_val\n");
9339
9340module_param(errordata_timeout_val, uint, 0664);
9341MODULE_PARM_DESC(errordata_timeout_val, "\n amvdec_h264 errordata_timeout_val\n");
9342
9343module_param(get_data_timeout_val, uint, 0664);
9344MODULE_PARM_DESC(get_data_timeout_val, "\n amvdec_h264 get_data_timeout_val\n");
9345
9346module_param(frame_max_data_packet, uint, 0664);
9347MODULE_PARM_DESC(frame_max_data_packet, "\n amvdec_h264 frame_max_data_packet\n");
9348
9349module_param(reorder_dpb_size_margin, uint, 0664);
9350MODULE_PARM_DESC(reorder_dpb_size_margin, "\n ammvdec_h264 reorder_dpb_size_margin\n");
9351
9352#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9353module_param(reorder_dpb_size_margin_dv, uint, 0664);
9354MODULE_PARM_DESC(reorder_dpb_size_margin_dv,
9355 "\n ammvdec_h264 reorder_dpb_size_margin_dv\n");
9356#endif
9357
9358module_param(reference_buf_margin, uint, 0664);
9359MODULE_PARM_DESC(reference_buf_margin, "\n ammvdec_h264 reference_buf_margin\n");
9360
9361#ifdef CONSTRAIN_MAX_BUF_NUM
9362module_param(run_ready_max_vf_only_num, uint, 0664);
9363MODULE_PARM_DESC(run_ready_max_vf_only_num, "\n run_ready_max_vf_only_num\n");
9364
9365module_param(run_ready_display_q_num, uint, 0664);
9366MODULE_PARM_DESC(run_ready_display_q_num, "\n run_ready_display_q_num\n");
9367
9368module_param(run_ready_max_buf_num, uint, 0664);
9369MODULE_PARM_DESC(run_ready_max_buf_num, "\n run_ready_max_buf_num\n");
9370#endif
9371
9372module_param(radr, uint, 0664);
9373MODULE_PARM_DESC(radr, "\nradr\n");
9374
9375module_param(rval, uint, 0664);
9376MODULE_PARM_DESC(rval, "\nrval\n");
9377
9378module_param(h264_debug_mask, uint, 0664);
9379MODULE_PARM_DESC(h264_debug_mask, "\n amvdec_h264 h264_debug_mask\n");
9380
9381module_param(h264_debug_cmd, uint, 0664);
9382MODULE_PARM_DESC(h264_debug_cmd, "\n amvdec_h264 h264_debug_cmd\n");
9383
9384module_param(force_rate_streambase, int, 0664);
9385MODULE_PARM_DESC(force_rate_streambase, "\n amvdec_h264 force_rate_streambase\n");
9386
9387module_param(dec_control, int, 0664);
9388MODULE_PARM_DESC(dec_control, "\n amvdec_h264 dec_control\n");
9389
9390module_param(force_rate_framebase, int, 0664);
9391MODULE_PARM_DESC(force_rate_framebase, "\n amvdec_h264 force_rate_framebase\n");
9392
9393module_param(force_disp_bufspec_num, int, 0664);
9394MODULE_PARM_DESC(force_disp_bufspec_num, "\n amvdec_h264 force_disp_bufspec_num\n");
9395
9396module_param(V_BUF_ADDR_OFFSET, int, 0664);
9397MODULE_PARM_DESC(V_BUF_ADDR_OFFSET, "\n amvdec_h264 V_BUF_ADDR_OFFSET\n");
9398
9399module_param(prefix_aux_buf_size, uint, 0664);
9400MODULE_PARM_DESC(prefix_aux_buf_size, "\n prefix_aux_buf_size\n");
9401
9402module_param(suffix_aux_buf_size, uint, 0664);
9403MODULE_PARM_DESC(suffix_aux_buf_size, "\n suffix_aux_buf_size\n");
9404
9405#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9406module_param(dv_toggle_prov_name, uint, 0664);
9407MODULE_PARM_DESC(dv_toggle_prov_name, "\n dv_toggle_prov_name\n");
9408
9409module_param(dolby_meta_with_el, uint, 0664);
9410MODULE_PARM_DESC(dolby_meta_with_el, "\n dolby_meta_with_el\n");
9411
9412#endif
9413
9414module_param(fast_output_enable, uint, 0664);
9415MODULE_PARM_DESC(fast_output_enable, "\n amvdec_h264 fast_output_enable\n");
9416
9417module_param(error_proc_policy, uint, 0664);
9418MODULE_PARM_DESC(error_proc_policy, "\n amvdec_h264 error_proc_policy\n");
9419
9420module_param(error_skip_count, uint, 0664);
9421MODULE_PARM_DESC(error_skip_count, "\n amvdec_h264 error_skip_count\n");
9422
9423module_param(force_sliding_margin, uint, 0664);
9424MODULE_PARM_DESC(force_sliding_margin, "\n amvdec_h264 force_sliding_margin\n");
9425
9426module_param(i_only_flag, uint, 0664);
9427MODULE_PARM_DESC(i_only_flag, "\n amvdec_h264 i_only_flag\n");
9428
9429module_param(first_i_policy, uint, 0664);
9430MODULE_PARM_DESC(first_i_policy, "\n amvdec_h264 first_i_policy\n");
9431
9432module_param(frmbase_cont_bitlevel, uint, 0664);
9433MODULE_PARM_DESC(frmbase_cont_bitlevel,
9434 "\n amvdec_h264 frmbase_cont_bitlevel\n");
9435
9436module_param(frmbase_cont_bitlevel2, uint, 0664);
9437MODULE_PARM_DESC(frmbase_cont_bitlevel2,
9438 "\n amvdec_h264 frmbase_cont_bitlevel\n");
9439
9440module_param(udebug_flag, uint, 0664);
9441MODULE_PARM_DESC(udebug_flag, "\n amvdec_mh264 udebug_flag\n");
9442
9443module_param(udebug_pause_pos, uint, 0664);
9444MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n");
9445
9446module_param(udebug_pause_val, uint, 0664);
9447MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n");
9448
9449module_param(udebug_pause_decode_idx, uint, 0664);
9450MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n");
9451
9452module_param(max_alloc_buf_count, uint, 0664);
9453MODULE_PARM_DESC(max_alloc_buf_count, "\n amvdec_h264 max_alloc_buf_count\n");
9454
9455module_param(enable_itu_t35, uint, 0664);
9456MODULE_PARM_DESC(enable_itu_t35, "\n amvdec_h264 enable_itu_t35\n");
9457
9458module_param(endian, uint, 0664);
9459MODULE_PARM_DESC(endian, "\nrval\n");
9460
9461module_param(mmu_enable, uint, 0664);
9462MODULE_PARM_DESC(mmu_enable, "\n mmu_enable\n");
9463
9464module_param(force_enable_mmu, uint, 0664);
9465MODULE_PARM_DESC(force_enable_mmu, "\n force_enable_mmu\n");
9466
9467module_param(again_threshold, uint, 0664);
9468MODULE_PARM_DESC(again_threshold, "\n again_threshold\n");
9469
9470module_param(stream_mode_start_num, uint, 0664);
9471MODULE_PARM_DESC(stream_mode_start_num, "\n stream_mode_start_num\n");
9472
9473/*
9474module_param(trigger_task, uint, 0664);
9475MODULE_PARM_DESC(trigger_task, "\n amvdec_h264 trigger_task\n");
9476*/
9477module_param_array(decode_frame_count, uint, &max_decode_instance_num, 0664);
9478
9479module_param_array(display_frame_count, uint, &max_decode_instance_num, 0664);
9480
9481module_param_array(max_process_time, uint, &max_decode_instance_num, 0664);
9482
9483module_param_array(run_count, uint,
9484 &max_decode_instance_num, 0664);
9485
9486module_param_array(not_run_ready, uint,
9487 &max_decode_instance_num, 0664);
9488
9489module_param_array(input_empty, uint,
9490 &max_decode_instance_num, 0664);
9491
9492module_param_array(max_get_frame_interval, uint,
9493 &max_decode_instance_num, 0664);
9494
9495module_param_array(step, uint, &max_decode_instance_num, 0664);
9496
9497module_param_array(ref_frame_mark_flag, uint, &max_decode_instance_num, 0664);
9498
9499module_param(disp_vframe_valve_level, uint, 0664);
9500MODULE_PARM_DESC(disp_vframe_valve_level, "\n disp_vframe_valve_level\n");
9501
9502module_param(double_write_mode, uint, 0664);
9503MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n");
9504
9505module_param(mem_map_mode, uint, 0664);
9506MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n");
9507
9508module_param(without_display_mode, uint, 0664);
9509MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n");
9510
9511
9512module_init(ammvdec_h264_driver_init_module);
9513module_exit(ammvdec_h264_driver_remove_module);
9514
9515MODULE_DESCRIPTION("AMLOGIC H264 Video Decoder Driver");
9516MODULE_LICENSE("GPL");
9517
generated by cgit at 2024-05-19 15:57:29 (GMT)