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path: root/drivers/frame_provider/decoder/mjpeg/vmjpeg_multi.c (plain)
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1/*
2 * drivers/amlogic/amports/vmjpeg.c
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17
18#include <linux/kernel.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/interrupt.h>
22#include <linux/timer.h>
23#include <linux/kfifo.h>
24#include <linux/platform_device.h>
25#include <linux/delay.h>
26#include <linux/amlogic/media/frame_sync/ptsserv.h>
27#include <linux/amlogic/media/utils/amstream.h>
28#include <linux/amlogic/media/canvas/canvas.h>
29#include <linux/amlogic/media/vfm/vframe.h>
30#include <linux/amlogic/media/vfm/vframe_provider.h>
31#include <linux/amlogic/media/vfm/vframe_receiver.h>
32#include <linux/amlogic/tee.h>
33
34#include <linux/amlogic/media/utils/vdec_reg.h>
35#include <linux/amlogic/media/registers/register.h>
36#include "../../../stream_input/amports/amports_priv.h"
37
38#include "../utils/vdec_input.h"
39#include "../utils/vdec.h"
40#include "../utils/amvdec.h"
41#include "../utils/decoder_mmu_box.h"
42#include "../utils/decoder_bmmu_box.h"
43#include <linux/amlogic/media/codec_mm/codec_mm.h>
44#include <linux/amlogic/media/codec_mm/configs.h>
45#include "../utils/firmware.h"
46#include "../utils/vdec_v4l2_buffer_ops.h"
47#include "../utils/config_parser.h"
48
49#define MEM_NAME "codec_mmjpeg"
50
51#define DRIVER_NAME "ammvdec_mjpeg"
52#define MODULE_NAME "ammvdec_mjpeg"
53#define CHECK_INTERVAL (HZ/100)
54
55/* protocol register usage
56 * AV_SCRATCH_4 : decode buffer spec
57 * AV_SCRATCH_5 : decode buffer index
58 */
59
60#define MREG_DECODE_PARAM AV_SCRATCH_2 /* bit 0-3: pico_addr_mode */
61/* bit 15-4: reference height */
62#define MREG_TO_AMRISC AV_SCRATCH_8
63#define MREG_FROM_AMRISC AV_SCRATCH_9
64#define MREG_FRAME_OFFSET AV_SCRATCH_A
65#define DEC_STATUS_REG AV_SCRATCH_F
66#define MREG_PIC_WIDTH AV_SCRATCH_B
67#define MREG_PIC_HEIGHT AV_SCRATCH_C
68#define DECODE_STOP_POS AV_SCRATCH_K
69
70#define PICINFO_BUF_IDX_MASK 0x0007
71#define PICINFO_AVI1 0x0080
72#define PICINFO_INTERLACE 0x0020
73#define PICINFO_INTERLACE_AVI1_BOT 0x0010
74#define PICINFO_INTERLACE_FIRST 0x0010
75
76#define VF_POOL_SIZE 64
77#define DECODE_BUFFER_NUM_MAX 16
78#define DECODE_BUFFER_NUM_DEF 4
79#define MAX_BMMU_BUFFER_NUM DECODE_BUFFER_NUM_MAX
80
81#define DEFAULT_MEM_SIZE (32*SZ_1M)
82static int debug_enable;
83static u32 udebug_flag;
84#define DECODE_ID(hw) (hw_to_vdec(hw)->id)
85
86static unsigned int radr;
87static unsigned int rval;
88#define VMJPEG_DEV_NUM 9
89static unsigned int max_decode_instance_num = VMJPEG_DEV_NUM;
90static unsigned int max_process_time[VMJPEG_DEV_NUM];
91static unsigned int decode_timeout_val = 200;
92static struct vframe_s *vmjpeg_vf_peek(void *);
93static struct vframe_s *vmjpeg_vf_get(void *);
94static void vmjpeg_vf_put(struct vframe_s *, void *);
95static int vmjpeg_vf_states(struct vframe_states *states, void *);
96static int vmjpeg_event_cb(int type, void *data, void *private_data);
97static void vmjpeg_work(struct work_struct *work);
98static int pre_decode_buf_level = 0x800;
99static int start_decode_buf_level = 0x2000;
100static u32 without_display_mode;
101static u32 dynamic_buf_num_margin;
102#undef pr_info
103#define pr_info printk
104unsigned int mmjpeg_debug_mask = 0xff;
105#define PRINT_FLAG_ERROR 0x0
106#define PRINT_FLAG_RUN_FLOW 0X0001
107#define PRINT_FLAG_TIMEINFO 0x0002
108#define PRINT_FLAG_UCODE_DETAIL 0x0004
109#define PRINT_FLAG_VLD_DETAIL 0x0008
110#define PRINT_FLAG_DEC_DETAIL 0x0010
111#define PRINT_FLAG_BUFFER_DETAIL 0x0020
112#define PRINT_FLAG_RESTORE 0x0040
113#define PRINT_FRAME_NUM 0x0080
114#define PRINT_FLAG_FORCE_DONE 0x0100
115#define PRINT_FRAMEBASE_DATA 0x0400
116#define PRINT_FLAG_TIMEOUT_STATUS 0x1000
117#define PRINT_FLAG_V4L_DETAIL 0x8000
118#define IGNORE_PARAM_FROM_CONFIG 0x8000000
119
120int mmjpeg_debug_print(int index, int debug_flag, const char *fmt, ...)
121{
122 if (((debug_enable & debug_flag) &&
123 ((1 << index) & mmjpeg_debug_mask))
124 || (debug_flag == PRINT_FLAG_ERROR)) {
125 unsigned char buf[512];
126 int len = 0;
127 va_list args;
128 va_start(args, fmt);
129 len = sprintf(buf, "%d: ", index);
130 vsnprintf(buf + len, 512-len, fmt, args);
131 pr_info("%s", buf);
132 va_end(args);
133 }
134 return 0;
135}
136
137static const char vmjpeg_dec_id[] = "vmmjpeg-dev";
138
139#define PROVIDER_NAME "vdec.mjpeg"
140static const struct vframe_operations_s vf_provider_ops = {
141 .peek = vmjpeg_vf_peek,
142 .get = vmjpeg_vf_get,
143 .put = vmjpeg_vf_put,
144 .event_cb = vmjpeg_event_cb,
145 .vf_states = vmjpeg_vf_states,
146};
147
148#define DEC_RESULT_NONE 0
149#define DEC_RESULT_DONE 1
150#define DEC_RESULT_AGAIN 2
151#define DEC_RESULT_ERROR 3
152#define DEC_RESULT_FORCE_EXIT 4
153#define DEC_RESULT_EOS 5
154#define DEC_DECODE_TIMEOUT 0x21
155
156
157struct buffer_spec_s {
158 unsigned int y_addr;
159 unsigned int u_addr;
160 unsigned int v_addr;
161
162 int y_canvas_index;
163 int u_canvas_index;
164 int v_canvas_index;
165
166 struct canvas_config_s canvas_config[3];
167 unsigned long cma_alloc_addr;
168 int cma_alloc_count;
169 unsigned int buf_adr;
170 ulong v4l_ref_buf_addr;
171};
172
173#define spec2canvas(x) \
174 (((x)->v_canvas_index << 16) | \
175 ((x)->u_canvas_index << 8) | \
176 ((x)->y_canvas_index << 0))
177
178struct vdec_mjpeg_hw_s {
179 spinlock_t lock;
180 struct mutex vmjpeg_mutex;
181
182 struct platform_device *platform_dev;
183 DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
184 DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
185
186 struct vframe_s vfpool[VF_POOL_SIZE];
187 struct buffer_spec_s buffer_spec[DECODE_BUFFER_NUM_MAX];
188 s32 vfbuf_use[DECODE_BUFFER_NUM_MAX];
189
190 u32 frame_width;
191 u32 frame_height;
192 u32 frame_dur;
193 u32 saved_resolution;
194 u8 init_flag;
195 u32 stat;
196 u32 dec_result;
197 unsigned long buf_start;
198 u32 buf_size;
199 void *mm_blk_handle;
200 struct dec_sysinfo vmjpeg_amstream_dec_info;
201
202 struct vframe_chunk_s *chunk;
203 struct work_struct work;
204 void (*vdec_cb)(struct vdec_s *, void *);
205 void *vdec_cb_arg;
206 struct firmware_s *fw;
207 struct timer_list check_timer;
208 u32 decode_timeout_count;
209 unsigned long int start_process_time;
210 u32 last_vld_level;
211 u8 eos;
212 u32 frame_num;
213 u32 put_num;
214 u32 run_count;
215 u32 not_run_ready;
216 u32 buffer_not_ready;
217 u32 input_empty;
218 u32 peek_num;
219 u32 get_num;
220 bool is_used_v4l;
221 void *v4l2_ctx;
222 bool v4l_params_parsed;
223 int buf_num;
224 int dynamic_buf_num_margin;
225};
226
227static void reset_process_time(struct vdec_mjpeg_hw_s *hw);
228static void set_frame_info(struct vdec_mjpeg_hw_s *hw, struct vframe_s *vf)
229{
230 u32 temp;
231 temp = READ_VREG(MREG_PIC_WIDTH);
232 if (temp > 1920)
233 vf->width = hw->frame_width = 1920;
234 else if (temp > 0)
235 vf->width = hw->frame_width = temp;
236 temp = READ_VREG(MREG_PIC_HEIGHT);
237 if (temp > 1088)
238 vf->height = hw->frame_height = 1088;
239 else if (temp > 0)
240 vf->height = hw->frame_height = temp;
241 vf->duration = hw->frame_dur;
242 vf->ratio_control = 0;
243 vf->duration_pulldown = 0;
244 vf->flag = 0;
245
246 vf->canvas0Addr = vf->canvas1Addr = -1;
247 vf->plane_num = 3;
248
249 vf->canvas0_config[0] = hw->buffer_spec[vf->index].canvas_config[0];
250 vf->canvas0_config[1] = hw->buffer_spec[vf->index].canvas_config[1];
251 vf->canvas0_config[2] = hw->buffer_spec[vf->index].canvas_config[2];
252
253 vf->canvas1_config[0] = hw->buffer_spec[vf->index].canvas_config[0];
254 vf->canvas1_config[1] = hw->buffer_spec[vf->index].canvas_config[1];
255 vf->canvas1_config[2] = hw->buffer_spec[vf->index].canvas_config[2];
256}
257
258static irqreturn_t vmjpeg_isr(struct vdec_s *vdec, int irq)
259{
260 struct vdec_mjpeg_hw_s *hw =
261 (struct vdec_mjpeg_hw_s *)(vdec->private);
262
263 if (!hw)
264 return IRQ_HANDLED;
265
266 if (hw->eos)
267 return IRQ_HANDLED;
268
269 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
270
271 return IRQ_WAKE_THREAD;
272}
273
274static irqreturn_t vmjpeg_isr_thread_fn(struct vdec_s *vdec, int irq)
275{
276 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)(vdec->private);
277 u32 reg;
278 struct vframe_s *vf = NULL;
279 u32 index, offset = 0, pts;
280 u64 pts_us64;
281 u32 frame_size;
282
283 reset_process_time(hw);
284 if (READ_VREG(AV_SCRATCH_D) != 0 &&
285 (debug_enable & PRINT_FLAG_UCODE_DETAIL)) {
286 pr_info("dbg%x: %x\n", READ_VREG(AV_SCRATCH_D),
287 READ_VREG(AV_SCRATCH_E));
288 WRITE_VREG(AV_SCRATCH_D, 0);
289 return IRQ_HANDLED;
290 }
291
292 reg = READ_VREG(MREG_FROM_AMRISC);
293 index = READ_VREG(AV_SCRATCH_5);
294
295 if (index >= hw->buf_num) {
296 pr_err("fatal error, invalid buffer index.");
297 return IRQ_HANDLED;
298 }
299
300 if (kfifo_get(&hw->newframe_q, &vf) == 0) {
301 pr_info(
302 "fatal error, no available buffer slot.");
303 return IRQ_HANDLED;
304 }
305
306 if (hw->is_used_v4l) {
307 struct aml_vcodec_ctx *ctx =
308 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
309
310 if (ctx->param_sets_from_ucode && !hw->v4l_params_parsed) {
311 struct aml_vdec_ps_infos ps;
312
313 ps.visible_width = hw->frame_width;
314 ps.visible_height = hw->frame_height;
315 ps.coded_width = ALIGN(hw->frame_width, 64);
316 ps.coded_height = ALIGN(hw->frame_height, 64);
317 ps.dpb_size = hw->buf_num;
318 hw->v4l_params_parsed = true;
319 vdec_v4l_set_ps_infos(ctx, &ps);
320 }
321 }
322
323 if (hw->is_used_v4l) {
324 vf->v4l_mem_handle
325 = hw->buffer_spec[index].v4l_ref_buf_addr;
326 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
327 "[%d] %s(), v4l mem handle: 0x%lx\n",
328 ((struct aml_vcodec_ctx *)(hw->v4l2_ctx))->id,
329 __func__, vf->v4l_mem_handle);
330 }
331
332 vf->index = index;
333 set_frame_info(hw, vf);
334
335 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD;
336 /* vf->pts = (pts_valid) ? pts : 0; */
337 /* vf->pts_us64 = (pts_valid) ? pts_us64 : 0; */
338
339 if (hw->chunk) {
340 vf->pts = hw->chunk->pts;
341 vf->pts_us64 = hw->chunk->pts64;
342 } else {
343 offset = READ_VREG(MREG_FRAME_OFFSET);
344 if (pts_lookup_offset_us64
345 (PTS_TYPE_VIDEO, offset, &pts,
346 &frame_size, 3000,
347 &pts_us64) == 0) {
348 vf->pts = pts;
349 vf->pts_us64 = pts_us64;
350 } else {
351 vf->pts = 0;
352 vf->pts_us64 = 0;
353 }
354 }
355 vf->orientation = 0;
356 hw->vfbuf_use[index]++;
357
358 vf->mem_handle =
359 decoder_bmmu_box_get_mem_handle(
360 hw->mm_blk_handle, index);
361 decoder_do_frame_check(vdec, vf);
362 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
363 ATRACE_COUNTER(MODULE_NAME, vf->pts);
364 hw->frame_num++;
365 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FRAME_NUM,
366 "%s:frame num:%d,pts=%d,pts64=%lld. dur=%d\n",
367 __func__, hw->frame_num,
368 vf->pts, vf->pts_us64, vf->duration);
369 vdec->vdec_fps_detec(vdec->id);
370 if (without_display_mode == 0) {
371 vf_notify_receiver(vdec->vf_provider_name,
372 VFRAME_EVENT_PROVIDER_VFRAME_READY,
373 NULL);
374 } else
375 vmjpeg_vf_put(vmjpeg_vf_get(vdec), vdec);
376
377 hw->dec_result = DEC_RESULT_DONE;
378
379 vdec_schedule_work(&hw->work);
380
381 return IRQ_HANDLED;
382}
383
384static struct vframe_s *vmjpeg_vf_peek(void *op_arg)
385{
386 struct vframe_s *vf;
387 struct vdec_s *vdec = op_arg;
388 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private;
389
390 if (!hw)
391 return NULL;
392 hw->peek_num++;
393 if (kfifo_peek(&hw->display_q, &vf))
394 return vf;
395
396 return NULL;
397}
398
399static struct vframe_s *vmjpeg_vf_get(void *op_arg)
400{
401 struct vframe_s *vf;
402 struct vdec_s *vdec = op_arg;
403 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private;
404
405 if (!hw)
406 return NULL;
407 hw->get_num++;
408 if (kfifo_get(&hw->display_q, &vf))
409 return vf;
410
411 return NULL;
412}
413
414static void vmjpeg_vf_put(struct vframe_s *vf, void *op_arg)
415{
416 struct vdec_s *vdec = op_arg;
417 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private;
418 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FRAME_NUM,
419 "%s:put_num:%d\n", __func__, hw->put_num);
420 hw->vfbuf_use[vf->index]--;
421 kfifo_put(&hw->newframe_q, (const struct vframe_s *)vf);
422 hw->put_num++;
423}
424
425static int vmjpeg_event_cb(int type, void *data, void *private_data)
426{
427 return 0;
428}
429
430static int vmjpeg_vf_states(struct vframe_states *states, void *op_arg)
431{
432 unsigned long flags;
433 struct vdec_s *vdec = op_arg;
434 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private;
435
436 spin_lock_irqsave(&hw->lock, flags);
437
438 states->vf_pool_size = VF_POOL_SIZE;
439 states->buf_free_num = kfifo_len(&hw->newframe_q);
440 states->buf_avail_num = kfifo_len(&hw->display_q);
441 states->buf_recycle_num = 0;
442
443 spin_unlock_irqrestore(&hw->lock, flags);
444
445 return 0;
446}
447
448static int vmjpeg_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
449{
450 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private;
451
452 if (!hw)
453 return -1;
454
455 vstatus->frame_width = hw->frame_width;
456 vstatus->frame_height = hw->frame_height;
457 if (0 != hw->frame_dur)
458 vstatus->frame_rate = 96000 / hw->frame_dur;
459 else
460 vstatus->frame_rate = 96000;
461 vstatus->error_count = 0;
462 vstatus->status = hw->stat;
463
464 return 0;
465}
466
467/****************************************/
468static void vmjpeg_canvas_init(struct vdec_mjpeg_hw_s *hw)
469{
470 int i, ret;
471 u32 canvas_width, canvas_height;
472 u32 decbuf_size, decbuf_y_size, decbuf_uv_size;
473 unsigned long buf_start, addr;
474 u32 endian;
475 struct vdec_s *vdec = hw_to_vdec(hw);
476
477 endian = (vdec->canvas_mode ==
478 CANVAS_BLKMODE_LINEAR) ? 7 : 0;
479 canvas_width = 1920;
480 canvas_height = 1088;
481 decbuf_y_size = 0x200000;
482 decbuf_uv_size = 0x80000;
483 decbuf_size = 0x300000;
484
485 for (i = 0; i < hw->buf_num; i++) {
486 int canvas;
487
488 if (hw->is_used_v4l) {
489 continue;
490 } else {
491 ret = decoder_bmmu_box_alloc_buf_phy(hw->mm_blk_handle, i,
492 decbuf_size, DRIVER_NAME, &buf_start);
493 if (ret < 0) {
494 pr_err("CMA alloc failed! size 0x%d idx %d\n",
495 decbuf_size, i);
496 return;
497 }
498 }
499
500 hw->buffer_spec[i].buf_adr = buf_start;
501 addr = hw->buffer_spec[i].buf_adr;
502
503 hw->buffer_spec[i].y_addr = addr;
504 addr += decbuf_y_size;
505 hw->buffer_spec[i].u_addr = addr;
506 addr += decbuf_uv_size;
507 hw->buffer_spec[i].v_addr = addr;
508
509 if (vdec->parallel_dec == 1) {
510 if (hw->buffer_spec[i].y_canvas_index == -1)
511 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
512 if (hw->buffer_spec[i].u_canvas_index == -1)
513 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
514 if (hw->buffer_spec[i].v_canvas_index == -1)
515 hw->buffer_spec[i].v_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
516 } else {
517 canvas = vdec->get_canvas(i, 3);
518 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
519 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
520 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
521 }
522
523 canvas_config_ex(hw->buffer_spec[i].y_canvas_index,
524 hw->buffer_spec[i].y_addr,
525 canvas_width,
526 canvas_height,
527 CANVAS_ADDR_NOWRAP,
528 CANVAS_BLKMODE_LINEAR, endian);
529 hw->buffer_spec[i].canvas_config[0].phy_addr =
530 hw->buffer_spec[i].y_addr;
531 hw->buffer_spec[i].canvas_config[0].width =
532 canvas_width;
533 hw->buffer_spec[i].canvas_config[0].height =
534 canvas_height;
535 hw->buffer_spec[i].canvas_config[0].block_mode =
536 CANVAS_BLKMODE_LINEAR;
537 hw->buffer_spec[i].canvas_config[0].endian =
538 endian;
539
540 canvas_config_ex(hw->buffer_spec[i].u_canvas_index,
541 hw->buffer_spec[i].u_addr,
542 canvas_width / 2,
543 canvas_height / 2,
544 CANVAS_ADDR_NOWRAP,
545 CANVAS_BLKMODE_LINEAR, endian);
546 hw->buffer_spec[i].canvas_config[1].phy_addr =
547 hw->buffer_spec[i].u_addr;
548 hw->buffer_spec[i].canvas_config[1].width =
549 canvas_width / 2;
550 hw->buffer_spec[i].canvas_config[1].height =
551 canvas_height / 2;
552 hw->buffer_spec[i].canvas_config[1].block_mode =
553 CANVAS_BLKMODE_LINEAR;
554 hw->buffer_spec[i].canvas_config[1].endian =
555 endian;
556
557 canvas_config_ex(hw->buffer_spec[i].v_canvas_index,
558 hw->buffer_spec[i].v_addr,
559 canvas_width / 2,
560 canvas_height / 2,
561 CANVAS_ADDR_NOWRAP,
562 CANVAS_BLKMODE_LINEAR, endian);
563 hw->buffer_spec[i].canvas_config[2].phy_addr =
564 hw->buffer_spec[i].v_addr;
565 hw->buffer_spec[i].canvas_config[2].width =
566 canvas_width / 2;
567 hw->buffer_spec[i].canvas_config[2].height =
568 canvas_height / 2;
569 hw->buffer_spec[i].canvas_config[2].block_mode =
570 CANVAS_BLKMODE_LINEAR;
571 hw->buffer_spec[i].canvas_config[2].endian =
572 endian;
573 }
574}
575
576static void init_scaler(void)
577{
578 /* 4 point triangle */
579 const unsigned int filt_coef[] = {
580 0x20402000, 0x20402000, 0x1f3f2101, 0x1f3f2101,
581 0x1e3e2202, 0x1e3e2202, 0x1d3d2303, 0x1d3d2303,
582 0x1c3c2404, 0x1c3c2404, 0x1b3b2505, 0x1b3b2505,
583 0x1a3a2606, 0x1a3a2606, 0x19392707, 0x19392707,
584 0x18382808, 0x18382808, 0x17372909, 0x17372909,
585 0x16362a0a, 0x16362a0a, 0x15352b0b, 0x15352b0b,
586 0x14342c0c, 0x14342c0c, 0x13332d0d, 0x13332d0d,
587 0x12322e0e, 0x12322e0e, 0x11312f0f, 0x11312f0f,
588 0x10303010
589 };
590 int i;
591
592 /* pscale enable, PSCALE cbus bmem enable */
593 WRITE_VREG(PSCALE_CTRL, 0xc000);
594
595 /* write filter coefs */
596 WRITE_VREG(PSCALE_BMEM_ADDR, 0);
597 for (i = 0; i < 33; i++) {
598 WRITE_VREG(PSCALE_BMEM_DAT, 0);
599 WRITE_VREG(PSCALE_BMEM_DAT, filt_coef[i]);
600 }
601
602 /* Y horizontal initial info */
603 WRITE_VREG(PSCALE_BMEM_ADDR, 37 * 2);
604 /* [35]: buf repeat pix0,
605 * [34:29] => buf receive num,
606 * [28:16] => buf blk x,
607 * [15:0] => buf phase
608 */
609 WRITE_VREG(PSCALE_BMEM_DAT, 0x0008);
610 WRITE_VREG(PSCALE_BMEM_DAT, 0x60000000);
611
612 /* C horizontal initial info */
613 WRITE_VREG(PSCALE_BMEM_ADDR, 41 * 2);
614 WRITE_VREG(PSCALE_BMEM_DAT, 0x0008);
615 WRITE_VREG(PSCALE_BMEM_DAT, 0x60000000);
616
617 /* Y vertical initial info */
618 WRITE_VREG(PSCALE_BMEM_ADDR, 39 * 2);
619 WRITE_VREG(PSCALE_BMEM_DAT, 0x0008);
620 WRITE_VREG(PSCALE_BMEM_DAT, 0x60000000);
621
622 /* C vertical initial info */
623 WRITE_VREG(PSCALE_BMEM_ADDR, 43 * 2);
624 WRITE_VREG(PSCALE_BMEM_DAT, 0x0008);
625 WRITE_VREG(PSCALE_BMEM_DAT, 0x60000000);
626
627 /* Y horizontal phase step */
628 WRITE_VREG(PSCALE_BMEM_ADDR, 36 * 2 + 1);
629 /* [19:0] => Y horizontal phase step */
630 WRITE_VREG(PSCALE_BMEM_DAT, 0x10000);
631 /* C horizontal phase step */
632 WRITE_VREG(PSCALE_BMEM_ADDR, 40 * 2 + 1);
633 /* [19:0] => C horizontal phase step */
634 WRITE_VREG(PSCALE_BMEM_DAT, 0x10000);
635
636 /* Y vertical phase step */
637 WRITE_VREG(PSCALE_BMEM_ADDR, 38 * 2 + 1);
638 /* [19:0] => Y vertical phase step */
639 WRITE_VREG(PSCALE_BMEM_DAT, 0x10000);
640 /* C vertical phase step */
641 WRITE_VREG(PSCALE_BMEM_ADDR, 42 * 2 + 1);
642 /* [19:0] => C horizontal phase step */
643 WRITE_VREG(PSCALE_BMEM_DAT, 0x10000);
644
645 /* reset pscaler */
646#if 1/*MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6*/
647 WRITE_VREG(DOS_SW_RESET0, (1 << 10));
648 WRITE_VREG(DOS_SW_RESET0, 0);
649#else
650 WRITE_RESET_REG(RESET2_REGISTER, RESET_PSCALE);
651#endif
652 READ_RESET_REG(RESET2_REGISTER);
653 READ_RESET_REG(RESET2_REGISTER);
654 READ_RESET_REG(RESET2_REGISTER);
655
656 WRITE_VREG(PSCALE_RST, 0x7);
657 WRITE_VREG(PSCALE_RST, 0x0);
658}
659
660static void vmjpeg_dump_state(struct vdec_s *vdec)
661{
662 struct vdec_mjpeg_hw_s *hw =
663 (struct vdec_mjpeg_hw_s *)(vdec->private);
664 mmjpeg_debug_print(DECODE_ID(hw), 0,
665 "====== %s\n", __func__);
666 mmjpeg_debug_print(DECODE_ID(hw), 0,
667 "width/height (%d/%d) buf_num %d\n",
668 hw->frame_width,
669 hw->frame_height,
670 hw->buf_num
671 );
672 mmjpeg_debug_print(DECODE_ID(hw), 0,
673 "is_framebase(%d), eos %d, state 0x%x, dec_result 0x%x dec_frm %d put_frm %d run %d not_run_ready %d input_empty %d\n",
674 input_frame_based(vdec),
675 hw->eos,
676 hw->stat,
677 hw->dec_result,
678 hw->frame_num,
679 hw->put_num,
680 hw->run_count,
681 hw->not_run_ready,
682 hw->input_empty
683 );
684 if (vf_get_receiver(vdec->vf_provider_name)) {
685 enum receviver_start_e state =
686 vf_notify_receiver(vdec->vf_provider_name,
687 VFRAME_EVENT_PROVIDER_QUREY_STATE,
688 NULL);
689 mmjpeg_debug_print(DECODE_ID(hw), 0,
690 "\nreceiver(%s) state %d\n",
691 vdec->vf_provider_name,
692 state);
693 }
694 mmjpeg_debug_print(DECODE_ID(hw), 0,
695 "%s, newq(%d/%d), dispq(%d/%d) vf peek/get/put (%d/%d/%d)\n",
696 __func__,
697 kfifo_len(&hw->newframe_q),
698 VF_POOL_SIZE,
699 kfifo_len(&hw->display_q),
700 VF_POOL_SIZE,
701 hw->peek_num,
702 hw->get_num,
703 hw->put_num
704 );
705 mmjpeg_debug_print(DECODE_ID(hw), 0,
706 "VIFF_BIT_CNT=0x%x\n",
707 READ_VREG(VIFF_BIT_CNT));
708 mmjpeg_debug_print(DECODE_ID(hw), 0,
709 "VLD_MEM_VIFIFO_LEVEL=0x%x\n",
710 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
711 mmjpeg_debug_print(DECODE_ID(hw), 0,
712 "VLD_MEM_VIFIFO_WP=0x%x\n",
713 READ_VREG(VLD_MEM_VIFIFO_WP));
714 mmjpeg_debug_print(DECODE_ID(hw), 0,
715 "VLD_MEM_VIFIFO_RP=0x%x\n",
716 READ_VREG(VLD_MEM_VIFIFO_RP));
717 mmjpeg_debug_print(DECODE_ID(hw), 0,
718 "PARSER_VIDEO_RP=0x%x\n",
719 READ_PARSER_REG(PARSER_VIDEO_RP));
720 mmjpeg_debug_print(DECODE_ID(hw), 0,
721 "PARSER_VIDEO_WP=0x%x\n",
722 READ_PARSER_REG(PARSER_VIDEO_WP));
723 if (input_frame_based(vdec) &&
724 debug_enable & PRINT_FRAMEBASE_DATA
725 ) {
726 int jj;
727 if (hw->chunk && hw->chunk->block &&
728 hw->chunk->size > 0) {
729 u8 *data = NULL;
730
731 if (!hw->chunk->block->is_mapped)
732 data = codec_mm_vmap(hw->chunk->block->start +
733 hw->chunk->offset, hw->chunk->size);
734 else
735 data = ((u8 *)hw->chunk->block->start_virt) +
736 hw->chunk->offset;
737
738 mmjpeg_debug_print(DECODE_ID(hw), 0,
739 "frame data size 0x%x\n",
740 hw->chunk->size);
741 for (jj = 0; jj < hw->chunk->size; jj++) {
742 if ((jj & 0xf) == 0)
743 mmjpeg_debug_print(DECODE_ID(hw),
744 PRINT_FRAMEBASE_DATA,
745 "%06x:", jj);
746 mmjpeg_debug_print(DECODE_ID(hw),
747 PRINT_FRAMEBASE_DATA,
748 "%02x ", data[jj]);
749 if (((jj + 1) & 0xf) == 0)
750 mmjpeg_debug_print(DECODE_ID(hw),
751 PRINT_FRAMEBASE_DATA,
752 "\n");
753 }
754
755 if (!hw->chunk->block->is_mapped)
756 codec_mm_unmap_phyaddr(data);
757 }
758 }
759}
760static void reset_process_time(struct vdec_mjpeg_hw_s *hw)
761{
762 if (hw->start_process_time) {
763 unsigned process_time =
764 1000 * (jiffies - hw->start_process_time) / HZ;
765 hw->start_process_time = 0;
766 if (process_time > max_process_time[DECODE_ID(hw)])
767 max_process_time[DECODE_ID(hw)] = process_time;
768 }
769}
770
771static void start_process_time(struct vdec_mjpeg_hw_s *hw)
772{
773 hw->decode_timeout_count = 2;
774 hw->start_process_time = jiffies;
775}
776
777static void timeout_process(struct vdec_mjpeg_hw_s *hw)
778{
779 amvdec_stop();
780 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
781 "%s decoder timeout\n", __func__);
782 hw->dec_result = DEC_RESULT_DONE;
783 reset_process_time(hw);
784 vdec_schedule_work(&hw->work);
785}
786
787static void check_timer_func(unsigned long arg)
788{
789 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)arg;
790 struct vdec_s *vdec = hw_to_vdec(hw);
791 int timeout_val = decode_timeout_val;
792
793 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_VLD_DETAIL,
794 "%s: status:nstatus=%d:%d\n",
795 __func__, vdec->status, vdec->next_status);
796 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_VLD_DETAIL,
797 "%s: %d,buftl=%x:%x:%x:%x\n",
798 __func__, __LINE__,
799 READ_VREG(VLD_MEM_VIFIFO_BUF_CNTL),
800 READ_PARSER_REG(PARSER_VIDEO_WP),
801 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
802 READ_VREG(VLD_MEM_VIFIFO_WP));
803
804 if (radr != 0) {
805 if (rval != 0) {
806 WRITE_VREG(radr, rval);
807 pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
808 } else
809 pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
810 rval = 0;
811 radr = 0;
812 }
813
814 if (((debug_enable & PRINT_FLAG_TIMEOUT_STATUS) == 0) &&
815 (input_frame_based(vdec) ||
816 ((u32)READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0x100)) &&
817 (timeout_val > 0) &&
818 (hw->start_process_time > 0) &&
819 ((1000 * (jiffies - hw->start_process_time) / HZ)
820 > timeout_val)) {
821 if (hw->last_vld_level == READ_VREG(VLD_MEM_VIFIFO_LEVEL)) {
822 if (hw->decode_timeout_count > 0)
823 hw->decode_timeout_count--;
824 if (hw->decode_timeout_count == 0)
825 timeout_process(hw);
826 }
827 hw->last_vld_level = READ_VREG(VLD_MEM_VIFIFO_LEVEL);
828 }
829
830 if (READ_VREG(DEC_STATUS_REG) == DEC_DECODE_TIMEOUT) {
831 pr_info("ucode DEC_DECODE_TIMEOUT\n");
832 if (hw->decode_timeout_count > 0)
833 hw->decode_timeout_count--;
834 if (hw->decode_timeout_count == 0)
835 timeout_process(hw);
836 WRITE_VREG(DEC_STATUS_REG, 0);
837 }
838
839 if (vdec->next_status == VDEC_STATUS_DISCONNECTED) {
840 hw->dec_result = DEC_RESULT_FORCE_EXIT;
841 vdec_schedule_work(&hw->work);
842 pr_info("vdec requested to be disconnected\n");
843 return;
844 }
845 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
846}
847
848static int vmjpeg_v4l_alloc_buff_config_canvas(struct vdec_mjpeg_hw_s *hw, int i)
849{
850 int ret;
851 u32 canvas;
852 ulong decbuf_start = 0, addr;
853 int decbuf_y_size = 0, decbuf_uv_size = 0;
854 u32 canvas_width = 0, canvas_height = 0;
855 struct vdec_s *vdec = hw_to_vdec(hw);
856 struct vdec_v4l2_buffer *fb = NULL;
857
858 if (hw->buffer_spec[i].v4l_ref_buf_addr)
859 return 0;
860
861 ret = vdec_v4l_get_buffer(hw->v4l2_ctx, &fb);
862 if (ret < 0) {
863 mmjpeg_debug_print(DECODE_ID(hw), 0,
864 "[%d] get fb fail.\n",
865 ((struct aml_vcodec_ctx *)
866 (hw->v4l2_ctx))->id);
867 return ret;
868 }
869
870 hw->buffer_spec[i].v4l_ref_buf_addr = (ulong)fb;
871 if (fb->num_planes == 1) {
872 decbuf_start = fb->m.mem[0].addr;
873 decbuf_y_size = fb->m.mem[0].offset;
874 decbuf_uv_size = fb->m.mem[0].size - fb->m.mem[0].offset;
875 canvas_width = ALIGN(hw->frame_width, 16);
876 canvas_height = ALIGN(hw->frame_height, 16);
877 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
878 } else if (fb->num_planes == 2) {
879 decbuf_start = fb->m.mem[0].addr;
880 decbuf_y_size = fb->m.mem[0].size;
881 decbuf_uv_size = fb->m.mem[1].size << 1;
882 canvas_width = ALIGN(hw->frame_width, 16);
883 canvas_height = ALIGN(hw->frame_height, 16);
884 fb->m.mem[0].bytes_used = decbuf_y_size;
885 fb->m.mem[1].bytes_used = decbuf_uv_size >> 1;
886 }
887
888 hw->buffer_spec[i].buf_adr = decbuf_start;
889 addr = hw->buffer_spec[i].buf_adr;
890 hw->buffer_spec[i].y_addr = addr;
891 addr += decbuf_y_size;
892 hw->buffer_spec[i].u_addr = addr;
893 addr += decbuf_uv_size;
894 hw->buffer_spec[i].v_addr = addr;
895
896 mmjpeg_debug_print(DECODE_ID(hw), 0, "[%d] %s(), v4l ref buf addr: 0x%x\n",
897 ((struct aml_vcodec_ctx *)(hw->v4l2_ctx))->id, __func__, fb);
898
899 if (vdec->parallel_dec == 1) {
900 if (hw->buffer_spec[i].y_canvas_index == -1)
901 hw->buffer_spec[i].y_canvas_index =
902 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
903 if (hw->buffer_spec[i].u_canvas_index == -1)
904 hw->buffer_spec[i].u_canvas_index =
905 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
906 if (hw->buffer_spec[i].v_canvas_index == -1)
907 hw->buffer_spec[i].v_canvas_index =
908 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
909 } else {
910 canvas = vdec->get_canvas(i, 3);
911 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
912 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
913 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
914 }
915
916 canvas_config(hw->buffer_spec[i].y_canvas_index,
917 hw->buffer_spec[i].y_addr,
918 canvas_width,
919 canvas_height,
920 CANVAS_ADDR_NOWRAP,
921 CANVAS_BLKMODE_LINEAR);
922 hw->buffer_spec[i].canvas_config[0].phy_addr =
923 hw->buffer_spec[i].y_addr;
924 hw->buffer_spec[i].canvas_config[0].width =
925 canvas_width;
926 hw->buffer_spec[i].canvas_config[0].height =
927 canvas_height;
928 hw->buffer_spec[i].canvas_config[0].block_mode =
929 CANVAS_BLKMODE_LINEAR;
930
931 canvas_config(hw->buffer_spec[i].u_canvas_index,
932 hw->buffer_spec[i].u_addr,
933 canvas_width / 2,
934 canvas_height / 2,
935 CANVAS_ADDR_NOWRAP,
936 CANVAS_BLKMODE_LINEAR);
937 hw->buffer_spec[i].canvas_config[1].phy_addr =
938 hw->buffer_spec[i].u_addr;
939 hw->buffer_spec[i].canvas_config[1].width =
940 canvas_width / 2;
941 hw->buffer_spec[i].canvas_config[1].height =
942 canvas_height / 2;
943 hw->buffer_spec[i].canvas_config[1].block_mode =
944 CANVAS_BLKMODE_LINEAR;
945
946 canvas_config(hw->buffer_spec[i].v_canvas_index,
947 hw->buffer_spec[i].v_addr,
948 canvas_width / 2,
949 canvas_height / 2,
950 CANVAS_ADDR_NOWRAP,
951 CANVAS_BLKMODE_LINEAR);
952 hw->buffer_spec[i].canvas_config[2].phy_addr =
953 hw->buffer_spec[i].v_addr;
954 hw->buffer_spec[i].canvas_config[2].width =
955 canvas_width / 2;
956 hw->buffer_spec[i].canvas_config[2].height =
957 canvas_height / 2;
958 hw->buffer_spec[i].canvas_config[2].block_mode =
959 CANVAS_BLKMODE_LINEAR;
960
961 return 0;
962}
963
964static int vmjpeg_get_buf_num(struct vdec_mjpeg_hw_s *hw)
965{
966 int buf_num = DECODE_BUFFER_NUM_DEF;
967
968 buf_num += hw->dynamic_buf_num_margin;
969
970 if (buf_num > DECODE_BUFFER_NUM_MAX)
971 buf_num = DECODE_BUFFER_NUM_MAX;
972
973 return buf_num;
974}
975
976static bool is_enough_free_buffer(struct vdec_mjpeg_hw_s *hw)
977{
978 int i;
979
980 for (i = 0; i < hw->buf_num; i++) {
981 if (hw->vfbuf_use[i] == 0)
982 break;
983 }
984
985 return i == hw->buf_num ? false : true;
986}
987
988static int find_free_buffer(struct vdec_mjpeg_hw_s *hw)
989{
990 int i;
991
992 for (i = 0; i < hw->buf_num; i++) {
993 if (hw->vfbuf_use[i] == 0)
994 break;
995 }
996
997 if (i == hw->buf_num)
998 return -1;
999
1000 if (hw->is_used_v4l)
1001 if (vmjpeg_v4l_alloc_buff_config_canvas(hw, i))
1002 return -1;
1003
1004 return i;
1005}
1006
1007static int vmjpeg_hw_ctx_restore(struct vdec_mjpeg_hw_s *hw)
1008{
1009 struct buffer_spec_s *buff_spec;
1010 int index, i;
1011
1012 index = find_free_buffer(hw);
1013 if (index < 0)
1014 return -1;
1015
1016 WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6));
1017 WRITE_VREG(DOS_SW_RESET0, 0);
1018
1019 if (!hw->init_flag) {
1020 vmjpeg_canvas_init(hw);
1021 } else {
1022 if (!hw->is_used_v4l) {
1023 for (i = 0; i < hw->buf_num; i++) {
1024 buff_spec = &hw->buffer_spec[i];
1025 canvas_config_config(buff_spec->y_canvas_index,
1026 &buff_spec->canvas_config[0]);
1027 canvas_config_config(buff_spec->u_canvas_index,
1028 &buff_spec->canvas_config[1]);
1029 canvas_config_config(buff_spec->v_canvas_index,
1030 &buff_spec->canvas_config[2]);
1031 }
1032 }
1033 }
1034
1035 /* find next decode buffer index */
1036 WRITE_VREG(AV_SCRATCH_4, spec2canvas(&hw->buffer_spec[index]));
1037 WRITE_VREG(AV_SCRATCH_5, index);
1038
1039 init_scaler();
1040
1041 /* clear buffer IN/OUT registers */
1042 WRITE_VREG(MREG_TO_AMRISC, 0);
1043 WRITE_VREG(MREG_FROM_AMRISC, 0);
1044
1045 WRITE_VREG(MCPU_INTR_MSK, 0xffff);
1046 WRITE_VREG(MREG_DECODE_PARAM, (hw->frame_height << 4) | 0x8000);
1047
1048 /* clear mailbox interrupt */
1049 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
1050 /* enable mailbox interrupt */
1051 WRITE_VREG(ASSIST_MBOX1_MASK, 1);
1052 /* set interrupt mapping for vld */
1053 WRITE_VREG(ASSIST_AMR1_INT8, 8);
1054#if 1/*MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6*/
1055 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 17);
1056#endif
1057 return 0;
1058}
1059
1060static s32 vmjpeg_init(struct vdec_s *vdec)
1061{
1062 int i;
1063 int size = -1, fw_size = 0x1000 * 16;
1064 struct firmware_s *fw = NULL;
1065 struct vdec_mjpeg_hw_s *hw =
1066 (struct vdec_mjpeg_hw_s *)vdec->private;
1067
1068 fw = vmalloc(sizeof(struct firmware_s) + fw_size);
1069 if (IS_ERR_OR_NULL(fw))
1070 return -ENOMEM;
1071
1072 size = get_firmware_data(VIDEO_DEC_MJPEG_MULTI, fw->data);
1073 if (size < 0) {
1074 pr_err("get firmware fail.");
1075 vfree(fw);
1076 return -1;
1077 }
1078
1079 fw->len = size;
1080 hw->fw = fw;
1081
1082 hw->frame_width = hw->vmjpeg_amstream_dec_info.width;
1083 hw->frame_height = hw->vmjpeg_amstream_dec_info.height;
1084 hw->frame_dur = ((hw->vmjpeg_amstream_dec_info.rate) ?
1085 hw->vmjpeg_amstream_dec_info.rate : 3840);
1086 hw->saved_resolution = 0;
1087 hw->eos = 0;
1088 hw->init_flag = 0;
1089 hw->frame_num = 0;
1090 hw->put_num = 0;
1091 hw->run_count = 0;
1092 hw->not_run_ready = 0;
1093 hw->input_empty = 0;
1094 hw->peek_num = 0;
1095 hw->get_num = 0;
1096 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++)
1097 hw->vfbuf_use[i] = 0;
1098
1099 INIT_KFIFO(hw->display_q);
1100 INIT_KFIFO(hw->newframe_q);
1101
1102 for (i = 0; i < VF_POOL_SIZE; i++) {
1103 const struct vframe_s *vf = &hw->vfpool[i];
1104
1105 hw->vfpool[i].index = -1;
1106 kfifo_put(&hw->newframe_q, vf);
1107 }
1108
1109 if (hw->mm_blk_handle) {
1110 decoder_bmmu_box_free(hw->mm_blk_handle);
1111 hw->mm_blk_handle = NULL;
1112 }
1113
1114 hw->mm_blk_handle = decoder_bmmu_box_alloc_box(
1115 DRIVER_NAME,
1116 0,
1117 MAX_BMMU_BUFFER_NUM,
1118 4 + PAGE_SHIFT,
1119 CODEC_MM_FLAGS_CMA_CLEAR |
1120 CODEC_MM_FLAGS_FOR_VDECODER);
1121
1122 init_timer(&hw->check_timer);
1123
1124 hw->check_timer.data = (unsigned long)hw;
1125 hw->check_timer.function = check_timer_func;
1126 hw->check_timer.expires = jiffies + CHECK_INTERVAL;
1127 /*add_timer(&hw->check_timer);*/
1128 hw->stat |= STAT_TIMER_ARM;
1129 hw->stat |= STAT_ISR_REG;
1130
1131 WRITE_VREG(DECODE_STOP_POS, udebug_flag);
1132 INIT_WORK(&hw->work, vmjpeg_work);
1133 pr_info("w:h=%d:%d\n", hw->frame_width, hw->frame_height);
1134 return 0;
1135}
1136
1137static unsigned long run_ready(struct vdec_s *vdec,
1138 unsigned long mask)
1139{
1140 struct vdec_mjpeg_hw_s *hw =
1141 (struct vdec_mjpeg_hw_s *)vdec->private;
1142 hw->not_run_ready++;
1143 if (hw->eos)
1144 return 0;
1145 if (vdec_stream_based(vdec) && (hw->init_flag == 0)
1146 && pre_decode_buf_level != 0) {
1147 u32 rp, wp, level;
1148
1149 rp = READ_PARSER_REG(PARSER_VIDEO_RP);
1150 wp = READ_PARSER_REG(PARSER_VIDEO_WP);
1151 if (wp < rp)
1152 level = vdec->input.size + wp - rp;
1153 else
1154 level = wp - rp;
1155
1156 if (level < pre_decode_buf_level)
1157 return 0;
1158 }
1159
1160 if (!is_enough_free_buffer(hw)) {
1161 hw->buffer_not_ready++;
1162 return 0;
1163 }
1164
1165 hw->not_run_ready = 0;
1166 hw->buffer_not_ready = 0;
1167 if (vdec->parallel_dec == 1)
1168 return CORE_MASK_VDEC_1;
1169 else
1170 return CORE_MASK_VDEC_1 | CORE_MASK_HEVC;
1171}
1172
1173static void run(struct vdec_s *vdec, unsigned long mask,
1174 void (*callback)(struct vdec_s *, void *), void *arg)
1175{
1176 struct vdec_mjpeg_hw_s *hw =
1177 (struct vdec_mjpeg_hw_s *)vdec->private;
1178 int i, ret;
1179
1180 hw->vdec_cb_arg = arg;
1181 hw->vdec_cb = callback;
1182
1183 hw->run_count++;
1184 vdec_reset_core(vdec);
1185 for (i = 0; i < hw->buf_num; i++) {
1186 if (hw->vfbuf_use[i] == 0)
1187 break;
1188 }
1189
1190 if (i == hw->buf_num) {
1191 hw->dec_result = DEC_RESULT_AGAIN;
1192 vdec_schedule_work(&hw->work);
1193 return;
1194 }
1195
1196 ret = vdec_prepare_input(vdec, &hw->chunk);
1197 if (ret <= 0) {
1198 hw->input_empty++;
1199 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_RUN_FLOW,
1200 "%s: %d,r=%d,buftl=%x:%x:%x\n",
1201 __func__, __LINE__, ret,
1202 READ_VREG(VLD_MEM_VIFIFO_BUF_CNTL),
1203 READ_PARSER_REG(PARSER_VIDEO_WP),
1204 READ_VREG(VLD_MEM_VIFIFO_WP));
1205
1206 hw->dec_result = DEC_RESULT_AGAIN;
1207 vdec_schedule_work(&hw->work);
1208 return;
1209 }
1210 hw->input_empty = 0;
1211 hw->dec_result = DEC_RESULT_NONE;
1212 if (vdec->mc_loaded) {
1213 /*firmware have load before,
1214 and not changes to another.
1215 ignore reload.
1216 */
1217 } else {
1218 ret = amvdec_vdec_loadmc_ex(VFORMAT_MJPEG, "mmjpeg", vdec, hw->fw->data);
1219 if (ret < 0) {
1220 pr_err("[%d] MMJPEG: the %s fw loading failed, err: %x\n",
1221 vdec->id, tee_enabled() ? "TEE" : "local", ret);
1222 hw->dec_result = DEC_RESULT_FORCE_EXIT;
1223 vdec_schedule_work(&hw->work);
1224 return;
1225 }
1226 vdec->mc_loaded = 1;
1227 vdec->mc_type = VFORMAT_MJPEG;
1228 }
1229/* if (amvdec_vdec_loadmc_buf_ex(vdec, hw->fw->data, hw->fw->len) < 0) {
1230 pr_err("%s: Error amvdec_loadmc fail\n", __func__);
1231 return;
1232 }*/
1233
1234 if (vmjpeg_hw_ctx_restore(hw) < 0) {
1235 hw->dec_result = DEC_RESULT_ERROR;
1236 mmjpeg_debug_print(DECODE_ID(hw), 0,
1237 "amvdec_mmjpeg: error HW context restore\n");
1238 vdec_schedule_work(&hw->work);
1239 return;
1240 }
1241#if 0
1242 vdec_enable_input(vdec);
1243 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
1244#endif
1245 hw->stat |= STAT_MC_LOAD;
1246 start_process_time(hw);
1247 hw->last_vld_level = 0;
1248 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
1249 amvdec_start();
1250 vdec_enable_input(vdec);
1251 hw->stat |= STAT_VDEC_RUN;
1252 hw->init_flag = 1;
1253
1254 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_RUN_FLOW,
1255 "%s (0x%x 0x%x 0x%x) vldcrl 0x%x bitcnt 0x%x powerctl 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
1256 __func__,
1257 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
1258 READ_VREG(VLD_MEM_VIFIFO_WP),
1259 READ_VREG(VLD_MEM_VIFIFO_RP),
1260 READ_VREG(VLD_DECODE_CONTROL),
1261 READ_VREG(VIFF_BIT_CNT),
1262 READ_VREG(POWER_CTL_VLD),
1263 READ_VREG(VLD_MEM_VIFIFO_START_PTR),
1264 READ_VREG(VLD_MEM_VIFIFO_CURR_PTR),
1265 READ_VREG(VLD_MEM_VIFIFO_CONTROL),
1266 READ_VREG(VLD_MEM_VIFIFO_BUF_CNTL),
1267 READ_VREG(VLD_MEM_VIFIFO_END_PTR));
1268}
1269static void wait_vmjpeg_search_done(struct vdec_mjpeg_hw_s *hw)
1270{
1271 u32 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
1272 int count = 0;
1273
1274 do {
1275 usleep_range(100, 500);
1276 if (vld_rp == READ_VREG(VLD_MEM_VIFIFO_RP))
1277 break;
1278 if (count > 1000) {
1279 mmjpeg_debug_print(DECODE_ID(hw), 0,
1280 "%s, count %d vld_rp 0x%x VLD_MEM_VIFIFO_RP 0x%x\n",
1281 __func__, count, vld_rp, READ_VREG(VLD_MEM_VIFIFO_RP));
1282 break;
1283 } else
1284 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
1285 count++;
1286 } while (1);
1287}
1288
1289static int notify_v4l_eos(struct vdec_s *vdec)
1290{
1291 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private;
1292 struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
1293 struct vframe_s *vf = NULL;
1294 struct vdec_v4l2_buffer *fb = NULL;
1295
1296 if (hw->is_used_v4l && hw->eos) {
1297 if (kfifo_get(&hw->newframe_q, &vf) == 0 || vf == NULL) {
1298 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
1299 "%s fatal error, no available buffer slot.\n",
1300 __func__);
1301 return -1;
1302 }
1303
1304 if (vdec_v4l_get_buffer(hw->v4l2_ctx, &fb)) {
1305 pr_err("[%d] get fb fail.\n", ctx->id);
1306 return -1;
1307 }
1308
1309 vf->timestamp = ULONG_MAX;
1310 vf->v4l_mem_handle = (unsigned long)fb;
1311 vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L;
1312
1313 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
1314 vf_notify_receiver(vdec->vf_provider_name,
1315 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
1316
1317 pr_info("[%d] mpeg12 EOS notify.\n", ctx->id);
1318 }
1319
1320 return 0;
1321}
1322
1323static void vmjpeg_work(struct work_struct *work)
1324{
1325 struct vdec_mjpeg_hw_s *hw = container_of(work,
1326 struct vdec_mjpeg_hw_s, work);
1327 struct vdec_s *vdec = hw_to_vdec(hw);
1328
1329 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_BUFFER_DETAIL,
1330 "%s: result=%d,len=%d:%d\n",
1331 __func__, hw->dec_result,
1332 kfifo_len(&hw->newframe_q),
1333 kfifo_len(&hw->display_q));
1334 if (hw->dec_result == DEC_RESULT_DONE) {
1335 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
1336 hw->chunk = NULL;
1337 } else if (hw->dec_result == DEC_RESULT_AGAIN) {
1338 /*
1339 stream base: stream buf empty or timeout
1340 frame base: vdec_prepare_input fail
1341 */
1342 if (!vdec_has_more_input(hw_to_vdec(hw))) {
1343 hw->dec_result = DEC_RESULT_EOS;
1344 vdec_schedule_work(&hw->work);
1345 /*pr_info("%s: return\n",
1346 __func__);*/
1347 return;
1348 }
1349 } else if (hw->dec_result == DEC_RESULT_FORCE_EXIT) {
1350 pr_info("%s: force exit\n", __func__);
1351 if (hw->stat & STAT_ISR_REG) {
1352 amvdec_stop();
1353 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
1354 hw->stat &= ~STAT_ISR_REG;
1355 }
1356 } else if (hw->dec_result == DEC_RESULT_EOS) {
1357 pr_info("%s: end of stream\n", __func__);
1358 if (hw->stat & STAT_VDEC_RUN) {
1359 amvdec_stop();
1360 hw->stat &= ~STAT_VDEC_RUN;
1361 }
1362 hw->eos = 1;
1363 if (hw->is_used_v4l)
1364 notify_v4l_eos(vdec);
1365
1366 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
1367 hw->chunk = NULL;
1368 vdec_clean_input(hw_to_vdec(hw));
1369 }
1370 if (hw->stat & STAT_VDEC_RUN) {
1371 amvdec_stop();
1372 hw->stat &= ~STAT_VDEC_RUN;
1373 }
1374 /*disable mbox interrupt */
1375 WRITE_VREG(ASSIST_MBOX1_MASK, 0);
1376 wait_vmjpeg_search_done(hw);
1377 /* mark itself has all HW resource released and input released */
1378 if (vdec->parallel_dec == 1)
1379 vdec_core_finish_run(hw_to_vdec(hw), CORE_MASK_VDEC_1);
1380 else {
1381 vdec_core_finish_run(hw_to_vdec(hw), CORE_MASK_VDEC_1
1382 | CORE_MASK_HEVC);
1383 }
1384 del_timer_sync(&hw->check_timer);
1385 hw->stat &= ~STAT_TIMER_ARM;
1386
1387 if (hw->vdec_cb)
1388 hw->vdec_cb(hw_to_vdec(hw), hw->vdec_cb_arg);
1389}
1390
1391static int vmjpeg_stop(struct vdec_mjpeg_hw_s *hw)
1392{
1393 pr_info("%s ...count = %d\n", __func__, hw->frame_num);
1394
1395 if (hw->stat & STAT_VDEC_RUN) {
1396 amvdec_stop();
1397 pr_info("%s amvdec_stop\n", __func__);
1398 hw->stat &= ~STAT_VDEC_RUN;
1399 }
1400
1401 if (hw->stat & STAT_ISR_REG) {
1402 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
1403 hw->stat &= ~STAT_ISR_REG;
1404 }
1405
1406 if (hw->stat & STAT_TIMER_ARM) {
1407 del_timer_sync(&hw->check_timer);
1408 hw->stat &= ~STAT_TIMER_ARM;
1409 }
1410 cancel_work_sync(&hw->work);
1411 hw->init_flag = 0;
1412
1413 if (hw->mm_blk_handle) {
1414 decoder_bmmu_box_free(hw->mm_blk_handle);
1415 hw->mm_blk_handle = NULL;
1416 }
1417
1418 if (hw->fw) {
1419 vfree(hw->fw);
1420 hw->fw = NULL;
1421 }
1422
1423 return 0;
1424}
1425
1426static int ammvdec_mjpeg_probe(struct platform_device *pdev)
1427{
1428 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
1429 struct vdec_mjpeg_hw_s *hw = NULL;
1430 int config_val = 0;
1431
1432 if (pdata == NULL) {
1433 pr_info("ammvdec_mjpeg memory resource undefined.\n");
1434 return -EFAULT;
1435 }
1436
1437 hw = vzalloc(sizeof(struct vdec_mjpeg_hw_s));
1438 if (hw == NULL) {
1439 pr_info("\nammvdec_mjpeg device data allocation failed\n");
1440 return -ENOMEM;
1441 }
1442
1443 /* the ctx from v4l2 driver. */
1444 hw->v4l2_ctx = pdata->private;
1445
1446 pdata->private = hw;
1447 pdata->dec_status = vmjpeg_dec_status;
1448
1449 pdata->run = run;
1450 pdata->run_ready = run_ready;
1451 pdata->irq_handler = vmjpeg_isr;
1452 pdata->threaded_irq_handler = vmjpeg_isr_thread_fn;
1453 pdata->dump_state = vmjpeg_dump_state;
1454
1455 if (pdata->parallel_dec == 1) {
1456 int i;
1457 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) {
1458 hw->buffer_spec[i].y_canvas_index = -1;
1459 hw->buffer_spec[i].u_canvas_index = -1;
1460 hw->buffer_spec[i].v_canvas_index = -1;
1461 }
1462 }
1463
1464 if (pdata->use_vfm_path)
1465 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
1466 VFM_DEC_PROVIDER_NAME);
1467 else
1468 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
1469 PROVIDER_NAME ".%02x", pdev->id & 0xff);
1470
1471 if (((debug_enable & IGNORE_PARAM_FROM_CONFIG) == 0) && pdata->config_len) {
1472 mmjpeg_debug_print(DECODE_ID(hw), 0, "pdata->config: %s\n", pdata->config);
1473 if (get_config_int(pdata->config, "parm_v4l_buffer_margin",
1474 &config_val) == 0)
1475 hw->dynamic_buf_num_margin = config_val;
1476 else
1477 hw->dynamic_buf_num_margin = dynamic_buf_num_margin;
1478 } else {
1479 hw->dynamic_buf_num_margin = dynamic_buf_num_margin;
1480 }
1481
1482 hw->buf_num = vmjpeg_get_buf_num(hw);
1483
1484 vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
1485 &vf_provider_ops, pdata);
1486
1487 platform_set_drvdata(pdev, pdata);
1488
1489 hw->platform_dev = pdev;
1490
1491 if (pdata->sys_info) {
1492 hw->vmjpeg_amstream_dec_info = *pdata->sys_info;
1493 hw->is_used_v4l = (((unsigned long)
1494 hw->vmjpeg_amstream_dec_info.param & 0x80) >> 7);
1495 }
1496
1497 vdec_source_changed(VFORMAT_MJPEG,
1498 1920, 1080, 60);
1499 if (vmjpeg_init(pdata) < 0) {
1500 pr_info("ammvdec_mjpeg init failed.\n");
1501 if (hw) {
1502 vfree(hw);
1503 hw = NULL;
1504 }
1505 pdata->dec_status = NULL;
1506 return -ENODEV;
1507 }
1508 vdec_set_prepare_level(pdata, start_decode_buf_level);
1509
1510 if (pdata->parallel_dec == 1)
1511 vdec_core_request(pdata, CORE_MASK_VDEC_1);
1512 else {
1513 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
1514 | CORE_MASK_COMBINE);
1515 }
1516
1517 return 0;
1518}
1519
1520static int ammvdec_mjpeg_remove(struct platform_device *pdev)
1521{
1522 struct vdec_mjpeg_hw_s *hw =
1523 (struct vdec_mjpeg_hw_s *)
1524 (((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
1525 struct vdec_s *vdec;
1526 int i;
1527
1528 if (!hw)
1529 return -1;
1530 vdec = hw_to_vdec(hw);
1531
1532 vmjpeg_stop(hw);
1533
1534 if (vdec->parallel_dec == 1)
1535 vdec_core_release(hw_to_vdec(hw), CORE_MASK_VDEC_1);
1536 else
1537 vdec_core_release(hw_to_vdec(hw), CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
1538 vdec_set_status(hw_to_vdec(hw), VDEC_STATUS_DISCONNECTED);
1539 if (vdec->parallel_dec == 1) {
1540 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) {
1541 vdec->free_canvas_ex(hw->buffer_spec[i].y_canvas_index, vdec->id);
1542 vdec->free_canvas_ex(hw->buffer_spec[i].u_canvas_index, vdec->id);
1543 vdec->free_canvas_ex(hw->buffer_spec[i].v_canvas_index, vdec->id);
1544 }
1545 }
1546 vfree(hw);
1547
1548 pr_info("%s\n", __func__);
1549 return 0;
1550}
1551
1552/****************************************/
1553#ifdef CONFIG_PM
1554static int mmjpeg_suspend(struct device *dev)
1555{
1556 amvdec_suspend(to_platform_device(dev), dev->power.power_state);
1557 return 0;
1558}
1559
1560static int mmjpeg_resume(struct device *dev)
1561{
1562 amvdec_resume(to_platform_device(dev));
1563 return 0;
1564}
1565
1566static const struct dev_pm_ops mmjpeg_pm_ops = {
1567 SET_SYSTEM_SLEEP_PM_OPS(mmjpeg_suspend, mmjpeg_resume)
1568};
1569#endif
1570
1571static struct platform_driver ammvdec_mjpeg_driver = {
1572 .probe = ammvdec_mjpeg_probe,
1573 .remove = ammvdec_mjpeg_remove,
1574 .driver = {
1575 .name = DRIVER_NAME,
1576#ifdef CONFIG_PM
1577 .pm = &mmjpeg_pm_ops,
1578#endif
1579 }
1580};
1581
1582static struct codec_profile_t ammvdec_mjpeg_profile = {
1583 .name = "mmjpeg",
1584 .profile = ""
1585};
1586
1587static int __init ammvdec_mjpeg_driver_init_module(void)
1588{
1589 if (platform_driver_register(&ammvdec_mjpeg_driver)) {
1590 pr_err("failed to register ammvdec_mjpeg driver\n");
1591 return -ENODEV;
1592 }
1593 vcodec_profile_register(&ammvdec_mjpeg_profile);
1594 return 0;
1595}
1596
1597static void __exit ammvdec_mjpeg_driver_remove_module(void)
1598{
1599 platform_driver_unregister(&ammvdec_mjpeg_driver);
1600}
1601
1602/****************************************/
1603module_param(debug_enable, uint, 0664);
1604MODULE_PARM_DESC(debug_enable, "\n debug enable\n");
1605module_param(pre_decode_buf_level, int, 0664);
1606MODULE_PARM_DESC(pre_decode_buf_level,
1607 "\n ammvdec_h264 pre_decode_buf_level\n");
1608module_param(udebug_flag, uint, 0664);
1609MODULE_PARM_DESC(udebug_flag, "\n amvdec_mmpeg12 udebug_flag\n");
1610
1611module_param(dynamic_buf_num_margin, uint, 0664);
1612MODULE_PARM_DESC(dynamic_buf_num_margin, "\n dynamic_buf_num_margin\n");
1613
1614module_param(decode_timeout_val, uint, 0664);
1615MODULE_PARM_DESC(decode_timeout_val, "\n ammvdec_mjpeg decode_timeout_val\n");
1616
1617module_param_array(max_process_time, uint, &max_decode_instance_num, 0664);
1618
1619module_param(radr, uint, 0664);
1620MODULE_PARM_DESC(radr, "\nradr\n");
1621
1622module_param(start_decode_buf_level, uint, 0664);
1623MODULE_PARM_DESC(start_decode_buf_level, "\nstart_decode_buf_level\n");
1624
1625module_param(rval, uint, 0664);
1626MODULE_PARM_DESC(rval, "\nrval\n");
1627
1628module_param(without_display_mode, uint, 0664);
1629MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n");
1630
1631module_init(ammvdec_mjpeg_driver_init_module);
1632module_exit(ammvdec_mjpeg_driver_remove_module);
1633
1634MODULE_DESCRIPTION("AMLOGIC MJMPEG Video Decoder Driver");
1635MODULE_LICENSE("GPL");
1636MODULE_AUTHOR("Tim Yao <timyao@amlogic.com>");
1637
generated by cgit at 2024-05-19 19:58:20 (GMT)