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path: root/drivers/frame_provider/decoder/vav1/vav1.c (plain)
blob: 9cecb72a840a2d59fba4acc752685b4ff13979b8
1 /*
2 * drivers/amlogic/amports/vav1.c
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17#define DEBUG
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/types.h>
21#include <linux/errno.h>
22#include <linux/interrupt.h>
23#include <linux/semaphore.h>
24#include <linux/delay.h>
25#include <linux/timer.h>
26#include <linux/kfifo.h>
27#include <linux/kthread.h>
28#include <linux/spinlock.h>
29#include <linux/platform_device.h>
30#include <linux/amlogic/media/vfm/vframe.h>
31#include <linux/amlogic/media/utils/amstream.h>
32#include <linux/amlogic/media/utils/vformat.h>
33#include <linux/amlogic/media/frame_sync/ptsserv.h>
34#include <linux/amlogic/media/canvas/canvas.h>
35#include <linux/amlogic/media/vfm/vframe_provider.h>
36#include <linux/amlogic/media/vfm/vframe_receiver.h>
37#include <linux/dma-mapping.h>
38#include <linux/dma-contiguous.h>
39#include <linux/slab.h>
40#include <linux/amlogic/tee.h>
41#include "../../../stream_input/amports/amports_priv.h"
42#include <linux/amlogic/media/codec_mm/codec_mm.h>
43#include "../utils/decoder_mmu_box.h"
44#include "../utils/decoder_bmmu_box.h"
45
46#define MEM_NAME "codec_av1"
47/* #include <mach/am_regs.h> */
48#include <linux/amlogic/media/utils/vdec_reg.h>
49#include "../utils/vdec.h"
50#include "../utils/amvdec.h"
51#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
52#include "../utils/vdec_profile.h"
53#endif
54
55#include <linux/amlogic/media/video_sink/video.h>
56#include <linux/amlogic/media/codec_mm/configs.h>
57#include "../utils/config_parser.h"
58#include "../utils/firmware.h"
59#include "../../../common/chips/decoder_cpu_ver_info.h"
60#include "../../../amvdec_ports/vdec_drv_base.h"
61
62#define SUPPORT_V4L2
63//#define DEBUG_USE_VP9_DEVICE_NAME
64//#define BUFMGR_ONLY_OLD_CHIP
65
66#ifdef SUPPORT_V4L2
67#include "../utils/vdec_v4l2_buffer_ops.h"
68#endif
69
70#define AML
71#include "aom_av1_define.h"
72#include "av1_global.h"
73
74#define DUMP_FILMGRAIN
75#define MIX_STREAM_SUPPORT
76//#define MV_USE_FIXED_BUF
77//#define USE_SPEC_BUF_FOR_MMU_HEAD
78
79#define AOM_AV1_DBLK_INIT
80#define AOM_AV1_UPSCALE_INIT
81
82#define USE_DEC_PIC_END
83
84
85#include "vav1.h"
86
87#define FGS_TABLE_SIZE (512 * 128 / 8)
88
89#define AV1_GMC_PARAM_BUFF_ADDR 0x316d
90#define HEVCD_MPP_DECOMP_AXIURG_CTL 0x34c7
91#define HEVC_FGS_IDX 0x3660
92#define HEVC_FGS_DATA 0x3661
93#define HEVC_FGS_CTRL 0x3662
94#define AV1_SKIP_MODE_INFO 0x316c
95#define AV1_QUANT_WR 0x3146
96#define AV1_SEG_W_ADDR 0x3165
97#define AV1_SEG_R_ADDR 0x3166
98#define AV1_REF_SEG_INFO 0x3171
99#define HEVC_ASSIST_PIC_SIZE_FB_READ 0x300d
100#define PARSER_REF_SCALE_ENBL 0x316b
101#define HEVC_MPRED_MV_RPTR_1 0x3263
102#define HEVC_MPRED_MV_RPTR_2 0x3264
103#define HEVC_SAO_CTRL9 0x362d
104#define HEVC_FGS_TABLE_START 0x3666
105#define HEVC_FGS_TABLE_LENGTH 0x3667
106#define HEVC_DBLK_CDEF0 0x3515
107#define HEVC_DBLK_CDEF1 0x3516
108#define HEVC_DBLK_UPS1 0x351c
109#define HEVC_DBLK_UPS2 0x351d
110#define HEVC_DBLK_UPS3 0x351e
111#define HEVC_DBLK_UPS4 0x351f
112#define HEVC_DBLK_UPS5 0x3520
113#define AV1_UPSCALE_X0_QN 0x316e
114#define AV1_UPSCALE_STEP_QN 0x316f
115#define HEVC_DBLK_DBLK0 0x3523
116#define HEVC_DBLK_DBLK1 0x3524
117#define HEVC_DBLK_DBLK2 0x3525
118
119#define HW_MASK_FRONT 0x1
120#define HW_MASK_BACK 0x2
121
122#define AV1D_MPP_REFINFO_TBL_ACCCONFIG 0x3442
123#define AV1D_MPP_REFINFO_DATA 0x3443
124#define AV1D_MPP_REF_SCALE_ENBL 0x3441
125#define HEVC_MPRED_CTRL4 0x324c
126#define HEVC_CM_HEADER_START_ADDR 0x3628
127#define HEVC_DBLK_CFGB 0x350b
128#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464
129#define HEVC_SAO_MMU_VH1_ADDR 0x363b
130#define HEVC_SAO_MMU_VH0_ADDR 0x363a
131
132#define HEVC_MV_INFO 0x310d
133#define HEVC_QP_INFO 0x3137
134#define HEVC_SKIP_INFO 0x3136
135
136#define HEVC_CM_BODY_LENGTH2 0x3663
137#define HEVC_CM_HEADER_OFFSET2 0x3664
138#define HEVC_CM_HEADER_LENGTH2 0x3665
139
140#define HEVC_CM_HEADER_START_ADDR2 0x364a
141#define HEVC_SAO_MMU_DMA_CTRL2 0x364c
142#define HEVC_SAO_MMU_VH0_ADDR2 0x364d
143#define HEVC_SAO_MMU_VH1_ADDR2 0x364e
144#define HEVC_DW_VH0_ADDDR 0x365e
145#define HEVC_DW_VH1_ADDDR 0x365f
146
147#ifdef BUFMGR_ONLY_OLD_CHIP
148#undef AV1_SKIP_MODE_INFO
149#define AV1_SKIP_MODE_INFO HEVC_ASSIST_SCRATCH_B
150#endif
151
152
153#define AOM_AV1_DEC_IDLE 0
154#define AOM_AV1_DEC_FRAME_HEADER 1
155#define AOM_AV1_DEC_TILE_END 2
156#define AOM_AV1_DEC_TG_END 3
157#define AOM_AV1_DEC_LCU_END 4
158#define AOM_AV1_DECODE_SLICE 5
159#define AOM_AV1_SEARCH_HEAD 6
160#define AOM_AV1_DUMP_LMEM 7
161#define AOM_AV1_FGS_PARAM_CONT 8
162#define AOM_AV1_DISCARD_NAL 0x10
163
164/*status*/
165#define AOM_AV1_DEC_PIC_END 0xe0
166/*AOM_AV1_FGS_PARA:
167Bit[11] - 0 Read, 1 - Write
168Bit[10:8] - film_grain_params_ref_idx, For Write request
169*/
170#define AOM_AV1_FGS_PARAM 0xe1
171#define AOM_AV1_DEC_PIC_END_PRE 0xe2
172#define AOM_AV1_HEAD_PARSER_DONE 0xf0
173#define AOM_AV1_HEAD_SEARCH_DONE 0xf1
174#define AOM_AV1_SEQ_HEAD_PARSER_DONE 0xf2
175#define AOM_AV1_FRAME_HEAD_PARSER_DONE 0xf3
176#define AOM_AV1_FRAME_PARSER_DONE 0xf4
177#define AOM_AV1_REDUNDANT_FRAME_HEAD_PARSER_DONE 0xf5
178#define HEVC_ACTION_DONE 0xff
179
180#define AOM_DECODE_BUFEMPTY 0x20
181#define AOM_DECODE_TIMEOUT 0x21
182#define AOM_SEARCH_BUFEMPTY 0x22
183#define AOM_DECODE_OVER_SIZE 0x23
184#define AOM_EOS 0x24
185#define AOM_NAL_DECODE_DONE 0x25
186
187
188#define VF_POOL_SIZE 32
189
190#undef pr_info
191#define pr_info printk
192
193#define DECODE_MODE_SINGLE ((0x80 << 24) | 0)
194#define DECODE_MODE_MULTI_STREAMBASE ((0x80 << 24) | 1)
195#define DECODE_MODE_MULTI_FRAMEBASE ((0x80 << 24) | 2)
196#define DECODE_MODE_SINGLE_LOW_LATENCY ((0x80 << 24) | 3)
197#define DECODE_MODE_MULTI_FRAMEBASE_NOHEAD ((0x80 << 24) | 4)
198
199#define AV1_TRIGGER_FRAME_DONE 0x100
200#define AV1_TRIGGER_FRAME_ENABLE 0x200
201
202#define MV_MEM_UNIT 0x240
203/*---------------------------------------------------
204 * Include "parser_cmd.h"
205 *---------------------------------------------------
206 */
207#define PARSER_CMD_SKIP_CFG_0 0x0000090b
208
209#define PARSER_CMD_SKIP_CFG_1 0x1b14140f
210
211#define PARSER_CMD_SKIP_CFG_2 0x001b1910
212
213#define PARSER_CMD_NUMBER 37
214
215/*#define HEVC_PIC_STRUCT_SUPPORT*/
216/* to remove, fix build error */
217
218/*#define CODEC_MM_FLAGS_FOR_VDECODER 0*/
219
220#define MULTI_INSTANCE_SUPPORT
221#define SUPPORT_10BIT
222/* #define ERROR_HANDLE_DEBUG */
223
224#ifndef STAT_KTHREAD
225#define STAT_KTHREAD 0x40
226#endif
227
228#ifdef MULTI_INSTANCE_SUPPORT
229#define MAX_DECODE_INSTANCE_NUM 9
230
231#ifdef DEBUG_USE_VP9_DEVICE_NAME
232#define MULTI_DRIVER_NAME "ammvdec_vp9"
233#else
234#define MULTI_DRIVER_NAME "ammvdec_av1"
235#endif
236
237#define AUX_BUF_ALIGN(adr) ((adr + 0xf) & (~0xf))
238static u32 prefix_aux_buf_size = (16 * 1024);
239static u32 suffix_aux_buf_size;
240
241static unsigned int max_decode_instance_num
242 = MAX_DECODE_INSTANCE_NUM;
243static unsigned int decode_frame_count[MAX_DECODE_INSTANCE_NUM];
244static unsigned int display_frame_count[MAX_DECODE_INSTANCE_NUM];
245static unsigned int max_process_time[MAX_DECODE_INSTANCE_NUM];
246static unsigned int run_count[MAX_DECODE_INSTANCE_NUM];
247static unsigned int input_empty[MAX_DECODE_INSTANCE_NUM];
248static unsigned int not_run_ready[MAX_DECODE_INSTANCE_NUM];
249#ifdef AOM_AV1_MMU_DW
250static unsigned int dw_mmu_enable[MAX_DECODE_INSTANCE_NUM];
251#endif
252/* disable timeout for av1 mosaic JIRA SWPL-23326 */
253static u32 decode_timeout_val = 0;
254static int start_decode_buf_level = 0x8000;
255static u32 work_buf_size;
256static u32 force_pts_unstable;
257static u32 mv_buf_margin = 16;
258
259/* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */
260/* double_write_mode:
261 * 0, no double write;
262 * 1, 1:1 ratio;
263 * 2, (1/4):(1/4) ratio;
264 * 3, (1/4):(1/4) ratio, with both compressed frame included
265 * 4, (1/2):(1/2) ratio;
266 * 5, (1/2):(1/2) ratio, with both compressed frame included
267 * 0x10, double write only
268 * 0x20, mmu double write
269 * 0x100, if > 1080p,use mode 4,else use mode 1;
270 * 0x200, if > 1080p,use mode 2,else use mode 1;
271 * 0x300, if > 720p, use mode 4, else use mode 1;
272 */
273static u32 double_write_mode;
274
275#ifdef DEBUG_USE_VP9_DEVICE_NAME
276#define DRIVER_NAME "amvdec_vp9"
277#define MODULE_NAME "amvdec_vp9"
278#define DRIVER_HEADER_NAME "amvdec_vp9_header"
279#else
280#define DRIVER_NAME "amvdec_av1"
281#define MODULE_NAME "amvdec_av1"
282#define DRIVER_HEADER_NAME "amvdec_av1_header"
283#endif
284
285#define PUT_INTERVAL (HZ/100)
286#define ERROR_SYSTEM_RESET_COUNT 200
287
288#define PTS_NORMAL 0
289#define PTS_NONE_REF_USE_DURATION 1
290
291#define PTS_MODE_SWITCHING_THRESHOLD 3
292#define PTS_MODE_SWITCHING_RECOVERY_THREASHOLD 3
293
294#define DUR2PTS(x) ((x)*90/96)
295#define PTS2DUR(x) ((x)*96/90)
296
297
298struct AV1HW_s;
299static int vav1_vf_states(struct vframe_states *states, void *);
300static struct vframe_s *vav1_vf_peek(void *);
301static struct vframe_s *vav1_vf_get(void *);
302static void vav1_vf_put(struct vframe_s *, void *);
303static int vav1_event_cb(int type, void *data, void *private_data);
304
305static int vav1_stop(struct AV1HW_s *hw);
306#ifdef MULTI_INSTANCE_SUPPORT
307static s32 vav1_init(struct vdec_s *vdec);
308#else
309static s32 vav1_init(struct AV1HW_s *hw);
310#endif
311static void vav1_prot_init(struct AV1HW_s *hw, u32 mask);
312static int vav1_local_init(struct AV1HW_s *hw);
313static void vav1_put_timer_func(unsigned long arg);
314static void dump_data(struct AV1HW_s *hw, int size);
315static unsigned char get_data_check_sum
316 (struct AV1HW_s *hw, int size);
317static void dump_pic_list(struct AV1HW_s *hw);
318static int av1_alloc_mmu(
319 struct AV1HW_s *hw,
320 int cur_buf_idx,
321 int pic_width,
322 int pic_height,
323 unsigned short bit_depth,
324 unsigned int *mmu_index_adr);
325
326#ifdef DEBUG_USE_VP9_DEVICE_NAME
327static const char vav1_dec_id[] = "vvp9-dev";
328
329#define PROVIDER_NAME "decoder.vp9"
330#define MULTI_INSTANCE_PROVIDER_NAME "vdec.vp9"
331#else
332static const char vav1_dec_id[] = "vav1-dev";
333
334#define PROVIDER_NAME "decoder.av1"
335#define MULTI_INSTANCE_PROVIDER_NAME "vdec.av1"
336#endif
337#define DV_PROVIDER_NAME "dvbldec"
338
339static const struct vframe_operations_s vav1_vf_provider = {
340 .peek = vav1_vf_peek,
341 .get = vav1_vf_get,
342 .put = vav1_vf_put,
343 .event_cb = vav1_event_cb,
344 .vf_states = vav1_vf_states,
345};
346
347static struct vframe_provider_s vav1_vf_prov;
348
349static u32 bit_depth_luma;
350static u32 bit_depth_chroma;
351static u32 frame_width;
352static u32 frame_height;
353static u32 video_signal_type;
354static u32 force_dv_enable;
355static u32 on_no_keyframe_skiped;
356static u32 without_display_mode;
357
358#define PROB_SIZE (496 * 2 * 4)
359#define PROB_BUF_SIZE (0x5000)
360#define COUNT_BUF_SIZE (0x300 * 4 * 4)
361/*compute_losless_comp_body_size(4096, 2304, 1) = 18874368(0x1200000)*/
362#define MAX_FRAME_4K_NUM 0x1200
363#define MAX_FRAME_8K_NUM 0x4800
364
365#define HEVC_ASSIST_MMU_MAP_ADDR 0x3009
366
367
368/*USE_BUF_BLOCK*/
369struct BUF_s {
370 int index;
371 unsigned int alloc_flag;
372 /*buffer */
373 unsigned int cma_page_count;
374 unsigned long alloc_addr;
375 unsigned long start_adr;
376 unsigned int size;
377
378 unsigned int free_start_adr;
379 ulong v4l_ref_buf_addr;
380} /*BUF_t */;
381
382struct MVBUF_s {
383 unsigned long start_adr;
384 unsigned int size;
385 int used_flag;
386} /*MVBUF_t */;
387
388/*#define TEST_WR_PTR_INC*/
389/*#define WR_PTR_INC_NUM 128*/
390#define WR_PTR_INC_NUM 1
391
392//#define SIMULATION
393#define DOS_PROJECT
394#undef MEMORY_MAP_IN_REAL_CHIP
395
396/*#undef DOS_PROJECT*/
397/*#define MEMORY_MAP_IN_REAL_CHIP*/
398
399/*#define CONFIG_HEVC_CLK_FORCED_ON*/
400/*#define ENABLE_SWAP_TEST*/
401#ifndef BUFMGR_ONLY_OLD_CHIP
402#define MCRCC_ENABLE
403#endif
404
405#ifdef AV1_10B_NV21
406#else
407#define LOSLESS_COMPRESS_MODE
408#endif
409
410typedef unsigned int u32;
411typedef unsigned short u16;
412
413
414static u32 get_picture_qos;
415
416static u32 debug;
417
418static bool is_reset;
419/*for debug*/
420/*
421 udebug_flag:
422 bit 0, enable ucode print
423 bit 1, enable ucode detail print
424 bit [31:16] not 0, pos to dump lmem
425 bit 2, pop bits to lmem
426 bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
427*/
428static u32 udebug_flag;
429/*
430 when udebug_flag[1:0] is not 0
431 udebug_pause_pos not 0,
432 pause position
433*/
434static u32 udebug_pause_pos;
435/*
436 when udebug_flag[1:0] is not 0
437 and udebug_pause_pos is not 0,
438 pause only when DEBUG_REG2 is equal to this val
439*/
440static u32 udebug_pause_val;
441
442static u32 udebug_pause_decode_idx;
443
444
445#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
446static u32 dv_toggle_prov_name;
447#endif
448
449
450#define DEBUG_REG
451#ifdef DEBUG_REG
452void AV1_WRITE_VREG_DBG2(unsigned int adr, unsigned int val, int line)
453{
454 if (debug & AV1_DEBUG_REG)
455 pr_info("%d:%s(%x, %x)\n", line, __func__, adr, val);
456 if (adr != 0)
457 WRITE_VREG(adr, val);
458}
459
460#undef WRITE_VREG
461#define WRITE_VREG(a,v) AV1_WRITE_VREG_DBG2(a,v,__LINE__)
462#endif
463
464#define FRAME_CNT_WINDOW_SIZE 59
465#define RATE_CORRECTION_THRESHOLD 5
466/**************************************************
467
468AV1 buffer management start
469
470***************************************************/
471
472#define MMU_COMPRESS_HEADER_SIZE 0x48000
473#define MMU_COMPRESS_HEADER_SIZE_DW MMU_COMPRESS_HEADER_SIZE
474#define MMU_COMPRESS_8K_HEADER_SIZE (0x48000*4)
475#define MAX_SIZE_8K (8192 * 4608)
476#define MAX_SIZE_4K (4096 * 2304)
477#define IS_8K_SIZE(w, h) (((w) * (h)) > MAX_SIZE_4K)
478
479#define INVALID_IDX -1 /* Invalid buffer index.*/
480
481
482/*4 scratch frames for the new frames to support a maximum of 4 cores decoding
483 *in parallel, 3 for scaled references on the encoder.
484 *TODO(hkuang): Add ondemand frame buffers instead of hardcoding the number
485 * // of framebuffers.
486 *TODO(jkoleszar): These 3 extra references could probably come from the
487 *normal reference pool.
488 */
489//#define FRAME_BUFFERS (REF_FRAMES + 16)
490//#define REF_FRAMES_4K (6)
491#define REF_FRAMES_4K REF_FRAMES
492
493#ifdef USE_SPEC_BUF_FOR_MMU_HEAD
494#define HEADER_FRAME_BUFFERS (0)
495#elif (defined AOM_AV1_MMU_DW)
496#define HEADER_FRAME_BUFFERS (2 * FRAME_BUFFERS)
497#else
498#define HEADER_FRAME_BUFFERS (FRAME_BUFFERS)
499#endif
500#define MAX_BUF_NUM (FRAME_BUFFERS)
501#define MV_BUFFER_NUM FRAME_BUFFERS
502
503//#define FRAME_CONTEXTS_LOG2 2
504//#define FRAME_CONTEXTS (1 << FRAME_CONTEXTS_LOG2)
505/*buffer + header buffer + workspace*/
506#ifdef MV_USE_FIXED_BUF
507#define MAX_BMMU_BUFFER_NUM (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + 1)
508#define VF_BUFFER_IDX(n) (n)
509#define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n)
510#define WORK_SPACE_BUF_ID (FRAME_BUFFERS + HEADER_FRAME_BUFFERS)
511#else
512#define MAX_BMMU_BUFFER_NUM \
513 (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + MV_BUFFER_NUM + 1)
514#define VF_BUFFER_IDX(n) (n)
515#define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n)
516#define MV_BUFFER_IDX(n) (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + n)
517#define WORK_SPACE_BUF_ID \
518 (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + MV_BUFFER_NUM)
519#endif
520#ifdef AOM_AV1_MMU_DW
521#define DW_HEADER_BUFFER_IDX(n) (HEADER_BUFFER_IDX(HEADER_FRAME_BUFFERS/2) + n)
522#endif
523
524
525static void set_canvas(struct AV1HW_s *hw,
526 struct PIC_BUFFER_CONFIG_s *pic_config);
527
528static void fill_frame_info(struct AV1HW_s *hw,
529 struct PIC_BUFFER_CONFIG_s *frame,
530 unsigned int framesize,
531 unsigned int pts);
532
533
534static int compute_losless_comp_body_size(int width, int height,
535 uint8_t is_bit_depth_10);
536
537
538
539#ifdef MULTI_INSTANCE_SUPPORT
540#define DEC_RESULT_NONE 0
541#define DEC_RESULT_DONE 1
542#define DEC_RESULT_AGAIN 2
543#define DEC_RESULT_CONFIG_PARAM 3
544#define DEC_RESULT_ERROR 4
545#define DEC_INIT_PICLIST 5
546#define DEC_UNINIT_PICLIST 6
547#define DEC_RESULT_GET_DATA 7
548#define DEC_RESULT_GET_DATA_RETRY 8
549#define DEC_RESULT_EOS 9
550#define DEC_RESULT_FORCE_EXIT 10
551
552#define DEC_S1_RESULT_NONE 0
553#define DEC_S1_RESULT_DONE 1
554#define DEC_S1_RESULT_FORCE_EXIT 2
555#define DEC_S1_RESULT_TEST_TRIGGER_DONE 0xf0
556
557#ifdef FB_DECODING_TEST_SCHEDULE
558#define TEST_SET_NONE 0
559#define TEST_SET_PIC_DONE 1
560#define TEST_SET_S2_DONE 2
561#endif
562
563static void av1_work(struct work_struct *work);
564#endif
565
566#ifdef DUMP_FILMGRAIN
567u32 fg_dump_index = 0xff;
568#endif
569
570#ifdef AOM_AV1_DBLK_INIT
571struct loop_filter_info_n_s;
572struct loopfilter;
573struct segmentation_lf;
574#endif
575struct AV1HW_s {
576 AV1Decoder *pbi;
577 union param_u aom_param;
578 unsigned char frame_decoded;
579 unsigned char one_compressed_data_done;
580 unsigned char new_compressed_data;
581#if 1
582/*def CHECK_OBU_REDUNDANT_FRAME_HEADER*/
583 int obu_frame_frame_head_come_after_tile;
584#endif
585 unsigned char index;
586
587 struct device *cma_dev;
588 struct platform_device *platform_dev;
589 void (*vdec_cb)(struct vdec_s *, void *);
590 void *vdec_cb_arg;
591 struct vframe_chunk_s *chunk;
592 int dec_result;
593 struct work_struct work;
594 struct work_struct set_clk_work;
595 u32 start_shift_bytes;
596 u32 data_size;
597
598 struct BuffInfo_s work_space_buf_store;
599 unsigned long buf_start;
600 u32 buf_size;
601 u32 cma_alloc_count;
602 unsigned long cma_alloc_addr;
603 uint8_t eos;
604 unsigned long int start_process_time;
605 unsigned last_lcu_idx;
606 int decode_timeout_count;
607 unsigned timeout_num;
608 int save_buffer_mode;
609
610 int double_write_mode;
611
612 long used_4k_num;
613
614 unsigned char m_ins_flag;
615 char *provider_name;
616 union param_u param;
617 int frame_count;
618 int pic_count;
619 u32 stat;
620 struct timer_list timer;
621 u32 frame_dur;
622 u32 frame_ar;
623 int fatal_error;
624 uint8_t init_flag;
625 uint8_t config_next_ref_info_flag;
626 uint8_t first_sc_checked;
627 uint8_t process_busy;
628#define PROC_STATE_INIT 0
629#define PROC_STATE_DECODESLICE 1
630#define PROC_STATE_SENDAGAIN 2
631 uint8_t process_state;
632 u32 ucode_pause_pos;
633
634 int show_frame_num;
635 struct buff_s mc_buf_spec;
636 struct dec_sysinfo vav1_amstream_dec_info;
637 void *rpm_addr;
638 void *lmem_addr;
639 dma_addr_t rpm_phy_addr;
640 dma_addr_t lmem_phy_addr;
641 unsigned short *lmem_ptr;
642 unsigned short *debug_ptr;
643#ifdef DUMP_FILMGRAIN
644 dma_addr_t fg_phy_addr;
645 unsigned char *fg_ptr;
646 void *fg_addr;
647#endif
648 u32 fgs_valid;
649
650 u8 aux_data_dirty;
651 u32 prefix_aux_size;
652 u32 suffix_aux_size;
653 void *aux_addr;
654 dma_addr_t aux_phy_addr;
655 char *dv_data_buf;
656 int dv_data_size;
657
658 void *prob_buffer_addr;
659 void *count_buffer_addr;
660 dma_addr_t prob_buffer_phy_addr;
661 dma_addr_t count_buffer_phy_addr;
662
663 void *frame_mmu_map_addr;
664 dma_addr_t frame_mmu_map_phy_addr;
665#ifdef AOM_AV1_MMU_DW
666 void *dw_frame_mmu_map_addr;
667 dma_addr_t dw_frame_mmu_map_phy_addr;
668#endif
669 unsigned int use_cma_flag;
670
671 struct BUF_s m_BUF[MAX_BUF_NUM];
672 struct MVBUF_s m_mv_BUF[MV_BUFFER_NUM];
673 u32 used_buf_num;
674 DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
675 DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
676 DECLARE_KFIFO(pending_q, struct vframe_s *, VF_POOL_SIZE);
677 struct vframe_s vfpool[VF_POOL_SIZE];
678 u32 vf_pre_count;
679 u32 vf_get_count;
680 u32 vf_put_count;
681 int buf_num;
682 int pic_num;
683 int lcu_size_log2;
684 unsigned int losless_comp_body_size;
685
686 u32 video_signal_type;
687
688 u32 frame_mode_pts_save[FRAME_BUFFERS];
689 u64 frame_mode_pts64_save[FRAME_BUFFERS];
690
691 int pts_mode;
692 int last_lookup_pts;
693 int last_pts;
694 u64 last_lookup_pts_us64;
695 u64 last_pts_us64;
696 u64 shift_byte_count;
697
698 u32 pts_unstable;
699 u32 frame_cnt_window;
700 u32 pts1, pts2;
701 u32 last_duration;
702 u32 duration_from_pts_done;
703 bool av1_first_pts_ready;
704
705 u32 shift_byte_count_lo;
706 u32 shift_byte_count_hi;
707 int pts_mode_switching_count;
708 int pts_mode_recovery_count;
709
710 bool get_frame_dur;
711 u32 saved_resolution;
712
713 /**/
714 struct AV1_Common_s common;
715 struct RefCntBuffer_s *cur_buf;
716 int refresh_frame_flags;
717 uint8_t need_resync;
718 uint8_t hold_ref_buf;
719 uint8_t ready_for_new_data;
720 struct BufferPool_s av1_buffer_pool;
721
722 struct BuffInfo_s *work_space_buf;
723
724 struct buff_s *mc_buf;
725
726 unsigned int frame_width;
727 unsigned int frame_height;
728
729 unsigned short *rpm_ptr;
730 int init_pic_w;
731 int init_pic_h;
732 int lcu_total;
733
734 int current_lcu_size;
735
736 int slice_type;
737
738 int skip_flag;
739 int decode_idx;
740 int result_done_count;
741 uint8_t has_keyframe;
742 uint8_t wait_buf;
743 uint8_t error_flag;
744
745 /* bit 0, for decoding; bit 1, for displaying */
746 uint8_t ignore_bufmgr_error;
747 int PB_skip_mode;
748 int PB_skip_count_after_decoding;
749 /*hw*/
750
751 /**/
752 struct vdec_info *gvs;
753
754 u32 pre_stream_offset;
755
756 unsigned int dec_status;
757 u32 last_put_idx;
758 int new_frame_displayed;
759 void *mmu_box;
760 void *bmmu_box;
761 int mmu_enable;
762#ifdef AOM_AV1_MMU_DW
763 void *mmu_box_dw;
764 int dw_mmu_enable;
765#endif
766 struct vframe_master_display_colour_s vf_dp;
767 struct firmware_s *fw;
768 int max_pic_w;
769 int max_pic_h;
770
771 int need_cache_size;
772 u64 sc_start_time;
773 bool postproc_done;
774 int low_latency_flag;
775 bool no_head;
776 bool pic_list_init_done;
777 bool pic_list_init_done2;
778 bool is_used_v4l;
779 void *v4l2_ctx;
780 int frameinfo_enable;
781 struct vframe_qos_s vframe_qos;
782
783#ifdef AOM_AV1_DBLK_INIT
784 /*
785 * malloc may not work in real chip, please allocate memory for the following structures
786 */
787 struct loop_filter_info_n_s *lfi;
788 struct loopfilter *lf;
789 struct segmentation_lf *seg_4lf;
790#endif
791
792};
793static void av1_dump_state(struct vdec_s *vdec);
794
795int av1_print(struct AV1HW_s *hw,
796 int flag, const char *fmt, ...)
797{
798#define HEVC_PRINT_BUF 256
799 unsigned char buf[HEVC_PRINT_BUF];
800 int len = 0;
801
802 if (hw == NULL ||
803 (flag == 0) ||
804 (debug & flag)) {
805 va_list args;
806
807 va_start(args, fmt);
808 if (hw)
809 len = sprintf(buf, "[%d]", hw->index);
810 vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
811 pr_info("%s", buf);
812 va_end(args);
813 }
814 return 0;
815}
816
817unsigned char av1_is_debug(int flag)
818{
819 if ((flag == 0) || (debug & flag))
820 return 1;
821
822 return 0;
823}
824
825int av1_print2(int flag, const char *fmt, ...)
826{
827 unsigned char buf[HEVC_PRINT_BUF];
828 int len = 0;
829
830 if ((flag == 0) ||
831 (debug & flag)) {
832 va_list args;
833
834 va_start(args, fmt);
835 vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
836 pr_info("%s", buf);
837 va_end(args);
838 }
839 return 0;
840
841}
842
843static int is_oversize(int w, int h)
844{
845 int max = (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)?
846 MAX_SIZE_8K : MAX_SIZE_4K;
847
848 if (w <= 0 || h <= 0)
849 return true;
850
851 if (h != 0 && (w > max / h))
852 return true;
853
854 return false;
855}
856
857static int v4l_get_fb(struct aml_vcodec_ctx *ctx, struct vdec_fb **out)
858{
859 int ret = 0;
860
861 ret = ctx->dec_if->get_param(ctx->drv_handle,
862 GET_PARAM_FREE_FRAME_BUFFER, out);
863
864 return ret;
865}
866
867
868static inline bool close_to(int a, int b, int m)
869{
870 return (abs(a - b) < m) ? true : false;
871}
872
873#ifdef MULTI_INSTANCE_SUPPORT
874static int av1_print_cont(struct AV1HW_s *hw,
875 int flag, const char *fmt, ...)
876{
877 unsigned char buf[HEVC_PRINT_BUF];
878 int len = 0;
879
880 if (hw == NULL ||
881 (flag == 0) ||
882 (debug & flag)) {
883 va_list args;
884
885 va_start(args, fmt);
886 vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
887 pr_info("%s", buf);
888 va_end(args);
889 }
890 return 0;
891}
892
893static void trigger_schedule(struct AV1HW_s *hw)
894{
895 if (hw->vdec_cb)
896 hw->vdec_cb(hw_to_vdec(hw), hw->vdec_cb_arg);
897}
898
899static void reset_process_time(struct AV1HW_s *hw)
900{
901 if (hw->start_process_time) {
902 unsigned process_time =
903 1000 * (jiffies - hw->start_process_time) / HZ;
904 hw->start_process_time = 0;
905 if (process_time > max_process_time[hw->index])
906 max_process_time[hw->index] = process_time;
907 }
908}
909
910static void start_process_time(struct AV1HW_s *hw)
911{
912 hw->start_process_time = jiffies;
913 hw->decode_timeout_count = 0;
914 hw->last_lcu_idx = 0;
915}
916
917static void timeout_process(struct AV1HW_s *hw)
918{
919 reset_process_time(hw);
920 if (hw->process_busy) {
921 av1_print(hw,
922 0, "%s decoder timeout but process_busy\n", __func__);
923 if (debug)
924 av1_print(hw, 0, "debug disable timeout notify\n");
925 return;
926 }
927 hw->timeout_num++;
928 amhevc_stop();
929 av1_print(hw,
930 0, "%s decoder timeout\n", __func__);
931
932 hw->dec_result = DEC_RESULT_DONE;
933 vdec_schedule_work(&hw->work);
934}
935
936static u32 get_valid_double_write_mode(struct AV1HW_s *hw)
937{
938 u32 dw = ((double_write_mode & 0x80000000) == 0) ?
939 hw->double_write_mode :
940 (double_write_mode & 0x7fffffff);
941 if ((dw & 0x20) &&
942 ((dw & 0xf) == 2 || (dw & 0xf) == 3)) {
943 pr_info("MMU doueble write 1:4 not supported !!!\n");
944 dw = 0;
945 }
946 return dw;
947}
948
949static int get_double_write_mode(struct AV1HW_s *hw)
950{
951 u32 valid_dw_mode = get_valid_double_write_mode(hw);
952 u32 dw;
953 int w, h;
954 struct AV1_Common_s *cm = &hw->pbi->common;
955 struct PIC_BUFFER_CONFIG_s *cur_pic_config;
956
957 if (!cm->cur_frame)
958 return 1;/*no valid frame,*/
959 cur_pic_config = &cm->cur_frame->buf;
960 w = cur_pic_config->y_crop_width;
961 h = cur_pic_config->y_crop_height;
962
963 dw = 0x1; /*1:1*/
964 switch (valid_dw_mode) {
965 case 0x100:
966 if (w > 1920 && h > 1088)
967 dw = 0x4; /*1:2*/
968 break;
969 case 0x200:
970 if (w > 1920 && h > 1088)
971 dw = 0x2; /*1:4*/
972 break;
973 case 0x300:
974 if (w > 1280 && h > 720)
975 dw = 0x4; /*1:2*/
976 break;
977 default:
978 dw = valid_dw_mode;
979 break;
980 }
981 return dw;
982}
983
984/* for double write buf alloc */
985static int get_double_write_mode_init(struct AV1HW_s *hw)
986{
987 u32 valid_dw_mode = get_valid_double_write_mode(hw);
988 u32 dw;
989 int w = hw->init_pic_w;
990 int h = hw->init_pic_h;
991
992 dw = 0x1; /*1:1*/
993 switch (valid_dw_mode) {
994 case 0x100:
995 if (w > 1920 && h > 1088)
996 dw = 0x4; /*1:2*/
997 break;
998 case 0x200:
999 if (w > 1920 && h > 1088)
1000 dw = 0x2; /*1:4*/
1001 break;
1002 case 0x300:
1003 if (w > 1280 && h > 720)
1004 dw = 0x4; /*1:2*/
1005 break;
1006 default:
1007 dw = valid_dw_mode;
1008 break;
1009 }
1010 return dw;
1011}
1012#endif
1013
1014static int get_double_write_ratio(struct AV1HW_s *hw,
1015 int dw_mode)
1016{
1017 int ratio = 1;
1018 int dw_mode_ratio = dw_mode & 0xf;
1019 if ((dw_mode_ratio == 2) ||
1020 (dw_mode_ratio == 3))
1021 ratio = 4;
1022 else if (dw_mode_ratio == 4)
1023 ratio = 2;
1024 return ratio;
1025}
1026
1027//#define MAX_4K_NUM 0x1200
1028int av1_alloc_mmu(
1029 struct AV1HW_s *hw,
1030 int cur_buf_idx,
1031 int pic_width,
1032 int pic_height,
1033 unsigned short bit_depth,
1034 unsigned int *mmu_index_adr)
1035{
1036 int ret = 0;
1037 int bit_depth_10 = (bit_depth == AOM_BITS_10);
1038 int picture_size;
1039 int cur_mmu_4k_number, max_frame_num;
1040 if (!hw->mmu_box) {
1041 pr_err("error no mmu box!\n");
1042 return -1;
1043 }
1044 if (hw->double_write_mode & 0x10)
1045 return 0;
1046 if (bit_depth >= AOM_BITS_12) {
1047 hw->fatal_error = DECODER_FATAL_ERROR_SIZE_OVERFLOW;
1048 pr_err("fatal_error, un support bit depth 12!\n\n");
1049 return -1;
1050 }
1051 picture_size = compute_losless_comp_body_size(pic_width, pic_height,
1052 bit_depth_10);
1053 cur_mmu_4k_number = ((picture_size + (1 << 12) - 1) >> 12);
1054
1055 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
1056 max_frame_num = MAX_FRAME_8K_NUM;
1057 else
1058 max_frame_num = MAX_FRAME_4K_NUM;
1059
1060 if (cur_mmu_4k_number > max_frame_num) {
1061 pr_err("over max !! cur_mmu_4k_number 0x%x width %d height %d\n",
1062 cur_mmu_4k_number, pic_width, pic_height);
1063 return -1;
1064 }
1065 ret = decoder_mmu_box_alloc_idx(
1066 hw->mmu_box,
1067 cur_buf_idx,
1068 cur_mmu_4k_number,
1069 mmu_index_adr);
1070 return ret;
1071}
1072
1073#ifdef AOM_AV1_MMU_DW
1074static int compute_losless_comp_body_size_dw(int width, int height,
1075 uint8_t is_bit_depth_10);
1076
1077int av1_alloc_mmu_dw(
1078 struct AV1HW_s *hw,
1079 int cur_buf_idx,
1080 int pic_width,
1081 int pic_height,
1082 unsigned short bit_depth,
1083 unsigned int *mmu_index_adr)
1084{
1085 int ret = 0;
1086 int bit_depth_10 = (bit_depth == AOM_BITS_10);
1087 int picture_size;
1088 int cur_mmu_4k_number, max_frame_num;
1089 if (!hw->mmu_box_dw) {
1090 pr_err("error no mmu box!\n");
1091 return -1;
1092 }
1093 if (hw->double_write_mode & 0x10)
1094 return 0;
1095 if (bit_depth >= AOM_BITS_12) {
1096 hw->fatal_error = DECODER_FATAL_ERROR_SIZE_OVERFLOW;
1097 pr_err("fatal_error, un support bit depth 12!\n\n");
1098 return -1;
1099 }
1100 picture_size = compute_losless_comp_body_size_dw(pic_width, pic_height,
1101 bit_depth_10);
1102 cur_mmu_4k_number = ((picture_size + (1 << 12) - 1) >> 12);
1103
1104 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
1105 max_frame_num = MAX_FRAME_8K_NUM;
1106 else
1107 max_frame_num = MAX_FRAME_4K_NUM;
1108
1109 if (cur_mmu_4k_number > max_frame_num) {
1110 pr_err("over max !! cur_mmu_4k_number 0x%x width %d height %d\n",
1111 cur_mmu_4k_number, pic_width, pic_height);
1112 return -1;
1113 }
1114 ret = decoder_mmu_box_alloc_idx(
1115 hw->mmu_box_dw,
1116 cur_buf_idx,
1117 cur_mmu_4k_number,
1118 mmu_index_adr);
1119 return ret;
1120}
1121#endif
1122
1123#ifndef MV_USE_FIXED_BUF
1124static void dealloc_mv_bufs(struct AV1HW_s *hw)
1125{
1126 int i;
1127 for (i = 0; i < MV_BUFFER_NUM; i++) {
1128 if (hw->m_mv_BUF[i].start_adr) {
1129 if (debug)
1130 pr_info(
1131 "dealloc mv buf(%d) adr %ld size 0x%x used_flag %d\n",
1132 i, hw->m_mv_BUF[i].start_adr,
1133 hw->m_mv_BUF[i].size,
1134 hw->m_mv_BUF[i].used_flag);
1135 decoder_bmmu_box_free_idx(
1136 hw->bmmu_box,
1137 MV_BUFFER_IDX(i));
1138 hw->m_mv_BUF[i].start_adr = 0;
1139 hw->m_mv_BUF[i].size = 0;
1140 hw->m_mv_BUF[i].used_flag = 0;
1141 }
1142 }
1143}
1144
1145static int alloc_mv_buf(struct AV1HW_s *hw,
1146 int i, int size)
1147{
1148 int ret = 0;
1149 if (decoder_bmmu_box_alloc_buf_phy
1150 (hw->bmmu_box,
1151 MV_BUFFER_IDX(i), size,
1152 DRIVER_NAME,
1153 &hw->m_mv_BUF[i].start_adr) < 0) {
1154 hw->m_mv_BUF[i].start_adr = 0;
1155 ret = -1;
1156 } else {
1157 hw->m_mv_BUF[i].size = size;
1158 hw->m_mv_BUF[i].used_flag = 0;
1159 ret = 0;
1160 if (debug) {
1161 pr_info(
1162 "MV Buffer %d: start_adr %p size %x\n",
1163 i,
1164 (void *)hw->m_mv_BUF[i].start_adr,
1165 hw->m_mv_BUF[i].size);
1166 }
1167 }
1168 return ret;
1169}
1170
1171static int init_mv_buf_list(struct AV1HW_s *hw)
1172{
1173 int i;
1174 int ret = 0;
1175 int count = MV_BUFFER_NUM;
1176 int pic_width = hw->init_pic_w;
1177 int pic_height = hw->init_pic_h;
1178 int lcu_size = 64; /*fixed 64*/ /* !!!!! TO DO ...*/
1179 int pic_width_64 = (pic_width + 63) & (~0x3f);
1180 int pic_height_32 = (pic_height + 31) & (~0x1f);
1181 int pic_width_lcu = (pic_width_64 % lcu_size) ?
1182 pic_width_64 / lcu_size + 1
1183 : pic_width_64 / lcu_size;
1184 int pic_height_lcu = (pic_height_32 % lcu_size) ?
1185 pic_height_32 / lcu_size + 1
1186 : pic_height_32 / lcu_size;
1187 int lcu_total = pic_width_lcu * pic_height_lcu;
1188 int size = ((lcu_total * MV_MEM_UNIT) + 0xffff) &
1189 (~0xffff);
1190#if 0
1191 if (mv_buf_margin > 0)
1192 count = REF_FRAMES + mv_buf_margin;
1193 if (hw->init_pic_w > 2048 && hw->init_pic_h > 1088)
1194 count = REF_FRAMES_4K + mv_buf_margin;
1195#else
1196 if (debug)
1197 pr_info("%s, calculated mv size 0x%x\n",
1198 __func__, size);
1199 if (hw->init_pic_w > 4096 && hw->init_pic_h > 2048) {
1200 count = REF_FRAMES_4K + mv_buf_margin;
1201 size = 0x260000;
1202 } else if (hw->init_pic_w > 2048 && hw->init_pic_h > 1088) {
1203 count = REF_FRAMES_4K + mv_buf_margin;
1204 size = 0x130000;
1205 } else {
1206 count = REF_FRAMES + mv_buf_margin;
1207 size = 0x130000;
1208 }
1209#endif
1210 if (debug) {
1211 pr_info("%s w:%d, h:%d, count: %d, size 0x%x\n",
1212 __func__, hw->init_pic_w, hw->init_pic_h, count, size);
1213 }
1214
1215 for (i = 0;
1216 i < count && i < MV_BUFFER_NUM; i++) {
1217 if (alloc_mv_buf(hw, i, size) < 0) {
1218 ret = -1;
1219 break;
1220 }
1221 }
1222 return ret;
1223}
1224
1225static int get_mv_buf(struct AV1HW_s *hw,
1226 int *mv_buf_index,
1227 uint32_t *mpred_mv_wr_start_addr)
1228{
1229 int i;
1230 int ret = -1;
1231 for (i = 0; i < MV_BUFFER_NUM; i++) {
1232 if (hw->m_mv_BUF[i].start_adr &&
1233 hw->m_mv_BUF[i].used_flag == 0) {
1234 hw->m_mv_BUF[i].used_flag = 1;
1235 ret = i;
1236 break;
1237 }
1238 }
1239
1240 if (ret >= 0) {
1241 *mv_buf_index = ret;
1242 *mpred_mv_wr_start_addr =
1243 (hw->m_mv_BUF[ret].start_adr + 0xffff) &
1244 (~0xffff);
1245 if (debug & AV1_DEBUG_BUFMGR_MORE)
1246 pr_info(
1247 "%s => %d (%d) size 0x%x\n",
1248 __func__, ret,
1249 *mpred_mv_wr_start_addr,
1250 hw->m_mv_BUF[ret].size);
1251 } else {
1252 pr_info(
1253 "%s: Error, mv buf is not enough\n",
1254 __func__);
1255 }
1256 return ret;
1257}
1258static void put_mv_buf(struct AV1HW_s *hw,
1259 int *mv_buf_index)
1260{
1261 int i = *mv_buf_index;
1262 if (i >= MV_BUFFER_NUM) {
1263 if (debug & AV1_DEBUG_BUFMGR_MORE)
1264 pr_info(
1265 "%s: index %d beyond range\n",
1266 __func__, i);
1267 return;
1268 }
1269 if (debug & AV1_DEBUG_BUFMGR_MORE)
1270 pr_info(
1271 "%s(%d): used_flag(%d)\n",
1272 __func__, i,
1273 hw->m_mv_BUF[i].used_flag);
1274
1275 *mv_buf_index = -1;
1276 if (hw->m_mv_BUF[i].start_adr &&
1277 hw->m_mv_BUF[i].used_flag)
1278 hw->m_mv_BUF[i].used_flag = 0;
1279}
1280static void put_un_used_mv_bufs(struct AV1HW_s *hw)
1281{
1282 struct AV1_Common_s *const cm = &hw->pbi->common;
1283 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
1284 int i;
1285 for (i = 0; i < hw->used_buf_num; ++i) {
1286 if ((frame_bufs[i].ref_count == 0) &&
1287 (frame_bufs[i].buf.index != -1) &&
1288 (frame_bufs[i].buf.mv_buf_index >= 0)
1289 )
1290 put_mv_buf(hw, &frame_bufs[i].buf.mv_buf_index);
1291 }
1292}
1293#endif
1294
1295
1296static int get_free_buf_count(struct AV1HW_s *hw)
1297{
1298 struct AV1_Common_s *const cm = &hw->pbi->common;
1299 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
1300 int i;
1301 int free_buf_count = 0;
1302 for (i = 0; i < hw->used_buf_num; ++i)
1303 if ((frame_bufs[i].ref_count == 0) &&
1304 (frame_bufs[i].buf.vf_ref == 0) &&
1305 (frame_bufs[i].buf.index != -1)
1306 )
1307 free_buf_count++;
1308 return free_buf_count;
1309}
1310
1311int aom_bufmgr_init(struct AV1HW_s *hw, struct BuffInfo_s *buf_spec_i,
1312 struct buff_s *mc_buf_i) {
1313 struct AV1_Common_s *cm = &hw->pbi->common;
1314 if (debug)
1315 pr_info("%s %d %p\n", __func__, __LINE__, hw->pbi);
1316 hw->frame_count = 0;
1317 hw->pic_count = 0;
1318 hw->pre_stream_offset = 0;
1319 spin_lock_init(&cm->buffer_pool->lock);
1320 cm->prev_fb_idx = INVALID_IDX;
1321 cm->new_fb_idx = INVALID_IDX;
1322 hw->used_4k_num = -1;
1323 cm->cur_fb_idx_mmu = INVALID_IDX;
1324 pr_debug
1325 ("After aom_bufmgr_init, prev_fb_idx : %d, new_fb_idx : %d\r\n",
1326 cm->prev_fb_idx, cm->new_fb_idx);
1327 hw->need_resync = 1;
1328
1329 cm->current_video_frame = 0;
1330 hw->ready_for_new_data = 1;
1331
1332 /* private init */
1333 hw->work_space_buf = buf_spec_i;
1334 if (!hw->mmu_enable)
1335 hw->mc_buf = mc_buf_i;
1336
1337 hw->rpm_addr = NULL;
1338 hw->lmem_addr = NULL;
1339#ifdef DUMP_FILMGRAIN
1340 hw->fg_addr = NULL;
1341#endif
1342 hw->use_cma_flag = 0;
1343 hw->decode_idx = 0;
1344 hw->result_done_count = 0;
1345 /*int m_uiMaxCUWidth = 1<<7;*/
1346 /*int m_uiMaxCUHeight = 1<<7;*/
1347 hw->has_keyframe = 0;
1348 hw->skip_flag = 0;
1349 hw->wait_buf = 0;
1350 hw->error_flag = 0;
1351
1352 hw->pts_mode = PTS_NORMAL;
1353 hw->last_pts = 0;
1354 hw->last_lookup_pts = 0;
1355 hw->last_pts_us64 = 0;
1356 hw->last_lookup_pts_us64 = 0;
1357 hw->shift_byte_count = 0;
1358 hw->shift_byte_count_lo = 0;
1359 hw->shift_byte_count_hi = 0;
1360 hw->pts_mode_switching_count = 0;
1361 hw->pts_mode_recovery_count = 0;
1362
1363 hw->buf_num = 0;
1364 hw->pic_num = 0;
1365
1366 return 0;
1367}
1368
1369/*
1370struct AV1HW_s av1_decoder;
1371union param_u av1_param;
1372*/
1373/**************************************************
1374 *
1375 *AV1 buffer management end
1376 *
1377 ***************************************************
1378 */
1379
1380
1381#define HEVC_CM_BODY_START_ADDR 0x3626
1382#define HEVC_CM_BODY_LENGTH 0x3627
1383#define HEVC_CM_HEADER_LENGTH 0x3629
1384#define HEVC_CM_HEADER_OFFSET 0x362b
1385
1386#define LOSLESS_COMPRESS_MODE
1387
1388/*#define DECOMP_HEADR_SURGENT*/
1389#ifdef AV1_10B_NV21
1390static u32 mem_map_mode = 2 /* 0:linear 1:32x32 2:64x32*/
1391#else
1392static u32 mem_map_mode; /* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */
1393#endif
1394static u32 enable_mem_saving = 1;
1395static u32 force_w_h;
1396
1397static u32 force_fps;
1398
1399
1400const u32 av1_version = 201602101;
1401static u32 debug;
1402static u32 radr;
1403static u32 rval;
1404static u32 pop_shorts;
1405static u32 dbg_cmd;
1406static u32 dbg_skip_decode_index;
1407static u32 endian = 0xff0;
1408static u32 multi_frames_in_one_pack = 1;
1409#ifdef ERROR_HANDLE_DEBUG
1410static u32 dbg_nal_skip_flag;
1411 /* bit[0], skip vps; bit[1], skip sps; bit[2], skip pps */
1412static u32 dbg_nal_skip_count;
1413#endif
1414/*for debug*/
1415static u32 decode_pic_begin;
1416static uint slice_parse_begin;
1417static u32 step;
1418#ifdef MIX_STREAM_SUPPORT
1419static u32 buf_alloc_width = 4096;
1420static u32 buf_alloc_height = 2304;
1421static u32 av1_max_pic_w = 4096;
1422static u32 av1_max_pic_h = 2304;
1423
1424static u32 dynamic_buf_num_margin;
1425#else
1426static u32 buf_alloc_width;
1427static u32 buf_alloc_height;
1428static u32 dynamic_buf_num_margin = 7;
1429#endif
1430static u32 buf_alloc_depth = 10;
1431static u32 buf_alloc_size;
1432/*
1433 *bit[0]: 0,
1434 * bit[1]: 0, always release cma buffer when stop
1435 * bit[1]: 1, never release cma buffer when stop
1436 *bit[0]: 1, when stop, release cma buffer if blackout is 1;
1437 *do not release cma buffer is blackout is not 1
1438 *
1439 *bit[2]: 0, when start decoding, check current displayed buffer
1440 * (only for buffer decoded by AV1) if blackout is 0
1441 * 1, do not check current displayed buffer
1442 *
1443 *bit[3]: 1, if blackout is not 1, do not release current
1444 * displayed cma buffer always.
1445 */
1446/* set to 1 for fast play;
1447 * set to 8 for other case of "keep last frame"
1448 */
1449static u32 buffer_mode = 1;
1450/* buffer_mode_dbg: debug only*/
1451static u32 buffer_mode_dbg = 0xffff0000;
1452/**/
1453
1454/*
1455 *bit 0, 1: only display I picture;
1456 *bit 1, 1: only decode I picture;
1457 */
1458static u32 i_only_flag;
1459
1460static u32 low_latency_flag;
1461
1462static u32 no_head;
1463
1464static u32 max_decoding_time;
1465/*
1466 *error handling
1467 */
1468/*error_handle_policy:
1469 *bit 0: 0, auto skip error_skip_nal_count nals before error recovery;
1470 *1, skip error_skip_nal_count nals before error recovery;
1471 *bit 1 (valid only when bit0 == 1):
1472 *1, wait vps/sps/pps after error recovery;
1473 *bit 2 (valid only when bit0 == 0):
1474 *0, auto search after error recovery (av1_recover() called);
1475 *1, manual search after error recovery
1476 *(change to auto search after get IDR: WRITE_VREG(NAL_SEARCH_CTL, 0x2))
1477 *
1478 *bit 4: 0, set error_mark after reset/recover
1479 * 1, do not set error_mark after reset/recover
1480 *bit 5: 0, check total lcu for every picture
1481 * 1, do not check total lcu
1482 *
1483 */
1484
1485static u32 error_handle_policy;
1486/*static u32 parser_sei_enable = 1;*/
1487#define MAX_BUF_NUM_NORMAL 16
1488#define MAX_BUF_NUM_LESS 16
1489static u32 max_buf_num = MAX_BUF_NUM_NORMAL;
1490#define MAX_BUF_NUM_SAVE_BUF 8
1491
1492static u32 run_ready_min_buf_num = 2;
1493
1494
1495static DEFINE_MUTEX(vav1_mutex);
1496#ifndef MULTI_INSTANCE_SUPPORT
1497static struct device *cma_dev;
1498#endif
1499#define HEVC_DEC_STATUS_REG HEVC_ASSIST_SCRATCH_0
1500#define HEVC_FG_STATUS HEVC_ASSIST_SCRATCH_B
1501#define HEVC_RPM_BUFFER HEVC_ASSIST_SCRATCH_1
1502#define AOM_AV1_ADAPT_PROB_REG HEVC_ASSIST_SCRATCH_3
1503#define AOM_AV1_MMU_MAP_BUFFER HEVC_ASSIST_SCRATCH_4 // changed to use HEVC_ASSIST_MMU_MAP_ADDR
1504#define AOM_AV1_DAALA_TOP_BUFFER HEVC_ASSIST_SCRATCH_5
1505#define HEVC_SAO_UP HEVC_ASSIST_SCRATCH_6
1506//#define HEVC_STREAM_SWAP_BUFFER HEVC_ASSIST_SCRATCH_7
1507#define AOM_AV1_CDF_BUFFER_W HEVC_ASSIST_SCRATCH_8
1508#define AOM_AV1_CDF_BUFFER_R HEVC_ASSIST_SCRATCH_9
1509#define AOM_AV1_COUNT_SWAP_BUFFER HEVC_ASSIST_SCRATCH_A
1510#define AOM_AV1_SEG_MAP_BUFFER_W AV1_SEG_W_ADDR // HEVC_ASSIST_SCRATCH_B
1511#define AOM_AV1_SEG_MAP_BUFFER_R AV1_SEG_R_ADDR // HEVC_ASSIST_SCRATCH_C
1512//#define HEVC_sao_vb_size HEVC_ASSIST_SCRATCH_B
1513//#define HEVC_SAO_VB HEVC_ASSIST_SCRATCH_C
1514//#define HEVC_SCALELUT HEVC_ASSIST_SCRATCH_D
1515#define HEVC_WAIT_FLAG HEVC_ASSIST_SCRATCH_E
1516#define RPM_CMD_REG HEVC_ASSIST_SCRATCH_F
1517//#define HEVC_STREAM_SWAP_TEST HEVC_ASSIST_SCRATCH_L
1518
1519#ifdef MULTI_INSTANCE_SUPPORT
1520#define HEVC_DECODE_COUNT HEVC_ASSIST_SCRATCH_M
1521#define HEVC_DECODE_SIZE HEVC_ASSIST_SCRATCH_N
1522#else
1523#define HEVC_DECODE_PIC_BEGIN_REG HEVC_ASSIST_SCRATCH_M
1524#define HEVC_DECODE_PIC_NUM_REG HEVC_ASSIST_SCRATCH_N
1525#endif
1526#define AOM_AV1_SEGMENT_FEATURE AV1_QUANT_WR
1527
1528#define DEBUG_REG1 HEVC_ASSIST_SCRATCH_G
1529#define DEBUG_REG2 HEVC_ASSIST_SCRATCH_H
1530
1531#define LMEM_DUMP_ADR HEVC_ASSIST_SCRATCH_I
1532#define CUR_NAL_UNIT_TYPE HEVC_ASSIST_SCRATCH_J
1533#define DECODE_STOP_POS HEVC_ASSIST_SCRATCH_K
1534
1535#define PIC_END_LCU_COUNT HEVC_ASSIST_SCRATCH_2
1536
1537#define HEVC_AUX_ADR HEVC_ASSIST_SCRATCH_L
1538#define HEVC_AUX_DATA_SIZE HEVC_ASSIST_SCRATCH_7
1539
1540/*
1541 *ucode parser/search control
1542 *bit 0: 0, header auto parse; 1, header manual parse
1543 *bit 1: 0, auto skip for noneseamless stream; 1, no skip
1544 *bit [3:2]: valid when bit1==0;
1545 *0, auto skip nal before first vps/sps/pps/idr;
1546 *1, auto skip nal before first vps/sps/pps
1547 *2, auto skip nal before first vps/sps/pps,
1548 * and not decode until the first I slice (with slice address of 0)
1549 *
1550 *3, auto skip before first I slice (nal_type >=16 && nal_type<=21)
1551 *bit [15:4] nal skip count (valid when bit0 == 1 (manual mode) )
1552 *bit [16]: for NAL_UNIT_EOS when bit0 is 0:
1553 * 0, send SEARCH_DONE to arm ; 1, do not send SEARCH_DONE to arm
1554 *bit [17]: for NAL_SEI when bit0 is 0:
1555 * 0, do not parse SEI in ucode; 1, parse SEI in ucode
1556 *bit [31:20]: used by ucode for debug purpose
1557 */
1558#define NAL_SEARCH_CTL HEVC_ASSIST_SCRATCH_I
1559 /*[31:24] chip feature
1560 31: 0, use MBOX1; 1, use MBOX0
1561 [24:16] debug
1562 0x1, bufmgr only
1563 */
1564#define DECODE_MODE HEVC_ASSIST_SCRATCH_J
1565#define DECODE_STOP_POS HEVC_ASSIST_SCRATCH_K
1566
1567#define RPM_BUF_SIZE ((RPM_END - RPM_BEGIN) * 2)
1568#define LMEM_BUF_SIZE (0x600 * 2)
1569
1570#ifdef MAP_8K
1571static u32 seg_map_size = 0xd8000;
1572#else
1573static u32 seg_map_size = 0x36000;
1574#endif
1575
1576#define WORK_BUF_SPEC_NUM 2
1577static struct BuffInfo_s aom_workbuff_spec[WORK_BUF_SPEC_NUM]={
1578 { //8M bytes
1579 .max_width = 1920,
1580 .max_height = 1088,
1581 .ipp = {
1582 // IPP work space calculation : 4096 * (Y+CbCr+Flags) = 12k, round to 16k
1583 .buf_size = 0x4000,
1584 },
1585 .sao_abv = {
1586 .buf_size = 0x30000,
1587 },
1588 .sao_vb = {
1589 .buf_size = 0x30000,
1590 },
1591 .short_term_rps = {
1592 // SHORT_TERM_RPS - Max 64 set, 16 entry every set, total 64x16x2 = 2048 bytes (0x800)
1593 .buf_size = 0x800,
1594 },
1595 .vps = {
1596 // VPS STORE AREA - Max 16 VPS, each has 0x80 bytes, total 0x0800 bytes
1597 .buf_size = 0x800,
1598 },
1599 .seg_map = {
1600 // SEGMENT MAP AREA - 1920x1088/4/4 * 3 bits = 0xBF40 Bytes * 16 = 0xBF400
1601 .buf_size = 0xBF400,
1602 },
1603 .daala_top = {
1604 // DAALA TOP STORE AREA - 224 Bytes (use 256 Bytes for LPDDR4) per 128. Total 4096/128*256 = 0x2000
1605 .buf_size = 0x2000,
1606 },
1607 .sao_up = {
1608 // SAO UP STORE AREA - Max 640(10240/16) LCU, each has 16 bytes total 0x2800 bytes
1609 .buf_size = 0x2800,
1610 },
1611 .swap_buf = {
1612 // 256cyclex64bit = 2K bytes 0x800 (only 144 cycles valid)
1613 .buf_size = 0x800,
1614 },
1615 .cdf_buf = {
1616 // for context store/load 1024x256 x16 = 512K bytes 16*0x8000
1617 .buf_size = 0x80000,
1618 },
1619 .gmc_buf = {
1620 // for gmc_parameter store/load 128 x 16 = 2K bytes 0x800
1621 .buf_size = 0x800,
1622 },
1623 .scalelut = {
1624 // support up to 32 SCALELUT 1024x32 = 32Kbytes (0x8000)
1625 .buf_size = 0x8000,
1626 },
1627 .dblk_para = {
1628 // DBLK -> Max 256(4096/16) LCU, each para 1024bytes(total:0x40000), data 1024bytes(total:0x40000)
1629 .buf_size = 0x80000,
1630 },
1631 .dblk_data = {
1632 .buf_size = 0x80000,
1633 },
1634 .cdef_data = {
1635 .buf_size = 0x40000,
1636 },
1637 .ups_data = {
1638 .buf_size = 0x60000,
1639 },
1640 .fgs_table = {
1641 .buf_size = FGS_TABLE_SIZE * FRAME_BUFFERS, // 512x128bits
1642 },
1643#ifdef AOM_AV1_MMU
1644#define VBH_BUF_SIZE (2 * 16 * 2304)
1645#define VBH_BUF_COUNT 4
1646 .mmu_vbh = {
1647 .buf_size = VBH_BUF_SIZE * VBH_BUF_COUNT,
1648 //.buf_size = 0x5000, //2*16*(more than 2304)/4, 4K
1649 },
1650 .cm_header = {
1651 //.buf_size = MMU_COMPRESS_HEADER_SIZE*8, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
1652 .buf_size = MMU_COMPRESS_HEADER_SIZE*FRAME_BUFFERS, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
1653 },
1654#endif
1655#ifdef AOM_AV1_MMU_DW
1656 .mmu_vbh_dw = {
1657 .buf_size = VBH_BUF_SIZE * VBH_BUF_COUNT,
1658 //.buf_size = 0x5000, //2*16*(more than 2304)/4, 4K
1659 },
1660 .cm_header_dw = {
1661 //.buf_size = MMU_COMPRESS_HEADER_SIZE*8, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
1662 .buf_size = MMU_COMPRESS_HEADER_SIZE_DW*FRAME_BUFFERS, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
1663 },
1664#endif
1665 .mpred_above = {
1666 .buf_size = 0x10000, /* 2 * size of hw*/
1667 },
1668#ifdef MV_USE_FIXED_BUF
1669 .mpred_mv = {
1670 .buf_size = 0x40000*FRAME_BUFFERS, //1080p, 0x40000 per buffer
1671 },
1672#endif
1673 .rpm = {
1674 .buf_size = 0x80*2,
1675 },
1676 .lmem = {
1677 .buf_size = 0x400 * 2,
1678 }
1679 },
1680 {
1681#ifdef VPU_FILMGRAIN_DUMP
1682 .max_width = 640,
1683 .max_height = 480,
1684#else
1685 .max_width = 4096,
1686 .max_height = 2304,
1687#endif
1688 .ipp = {
1689 // IPP work space calculation : 4096 * (Y+CbCr+Flags) = 12k, round to 16k
1690 .buf_size = 0x4000,
1691 },
1692 .sao_abv = {
1693 .buf_size = 0x30000,
1694 },
1695 .sao_vb = {
1696 .buf_size = 0x30000,
1697 },
1698 .short_term_rps = {
1699 // SHORT_TERM_RPS - Max 64 set, 16 entry every set, total 64x16x2 = 2048 bytes (0x800)
1700 .buf_size = 0x800,
1701 },
1702 .vps = {
1703 // VPS STORE AREA - Max 16 VPS, each has 0x80 bytes, total 0x0800 bytes
1704 .buf_size = 0x800,
1705 },
1706 .seg_map = {
1707 // SEGMENT MAP AREA - 4096x2304/4/4 * 3 bits = 0x36000 Bytes * 16 = 0x360000
1708 .buf_size = 0x360000,
1709 },
1710 .daala_top = {
1711 // DAALA TOP STORE AREA - 224 Bytes (use 256 Bytes for LPDDR4) per 128. Total 4096/128*256 = 0x2000
1712 .buf_size = 0x2000,
1713 },
1714 .sao_up = {
1715 // SAO UP STORE AREA - Max 640(10240/16) LCU, each has 16 bytes total 0x2800 bytes
1716 .buf_size = 0x2800,
1717 },
1718 .swap_buf = {
1719 // 256cyclex64bit = 2K bytes 0x800 (only 144 cycles valid)
1720 .buf_size = 0x800,
1721 },
1722 .cdf_buf = {
1723 // for context store/load 1024x256 x16 = 512K bytes 16*0x8000
1724 .buf_size = 0x80000,
1725 },
1726 .gmc_buf = {
1727 // for gmc_parameter store/load 128 x 16 = 2K bytes 0x800
1728 .buf_size = 0x800,
1729 },
1730 .scalelut = {
1731 // support up to 32 SCALELUT 1024x32 = 32Kbytes (0x8000)
1732 .buf_size = 0x8000,
1733 },
1734 .dblk_para = {
1735 // DBLK -> Max 256(4096/16) LCU, each para 1024bytes(total:0x40000), data 1024bytes(total:0x40000)
1736 .buf_size = 0x80000,
1737 },
1738 .dblk_data = {
1739 .buf_size = 0x80000,
1740 },
1741 .cdef_data = {
1742 .buf_size = 0x40000,
1743 },
1744 .ups_data = {
1745 .buf_size = 0x60000,
1746 },
1747 .fgs_table = {
1748 .buf_size = FGS_TABLE_SIZE * FRAME_BUFFERS, // 512x128bits
1749 },
1750#ifdef AOM_AV1_MMU
1751 .mmu_vbh = {
1752 .buf_size = VBH_BUF_SIZE * VBH_BUF_COUNT,
1753 //.buf_size = 0x5000, //2*16*(more than 2304)/4, 4K
1754 },
1755 .cm_header = {
1756 //.buf_size = MMU_COMPRESS_HEADER_SIZE*8, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
1757 .buf_size = MMU_COMPRESS_HEADER_SIZE*FRAME_BUFFERS, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
1758 },
1759#endif
1760#ifdef AOM_AV1_MMU_DW
1761 .mmu_vbh_dw = {
1762 .buf_size = VBH_BUF_SIZE * VBH_BUF_COUNT,
1763 //.buf_size = 0x5000, //2*16*(more than 2304)/4, 4K
1764 },
1765 .cm_header_dw = {
1766 //.buf_size = MMU_COMPRESS_HEADER_SIZE*8, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
1767 .buf_size = MMU_COMPRESS_HEADER_SIZE_DW*FRAME_BUFFERS, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
1768 },
1769#endif
1770 .mpred_above = {
1771 .buf_size = 0x10000, /* 2 * size of hw*/
1772 },
1773#ifdef MV_USE_FIXED_BUF
1774 .mpred_mv = {
1775 /* .buf_size = 0x100000*16,
1776 //4k2k , 0x100000 per buffer */
1777 /* 4096x2304 , 0x120000 per buffer */
1778#if (defined MAP_8K)
1779#define MAX_ONE_MV_BUFFER_SIZE 0x260000
1780#else
1781#define MAX_ONE_MV_BUFFER_SIZE 0x130000
1782#endif
1783 .buf_size = MAX_ONE_MV_BUFFER_SIZE * FRAME_BUFFERS,
1784 },
1785#endif
1786 .rpm = {
1787 .buf_size = 0x80*2,
1788 },
1789 .lmem = {
1790 .buf_size = 0x400 * 2,
1791 }
1792
1793 }
1794};
1795
1796
1797/*
1798* AUX DATA Process
1799*/
1800static u32 init_aux_size;
1801static int aux_data_is_avaible(struct AV1HW_s *hw)
1802{
1803 u32 reg_val;
1804
1805 reg_val = READ_VREG(HEVC_AUX_DATA_SIZE);
1806 if (reg_val != 0 && reg_val != init_aux_size)
1807 return 1;
1808 else
1809 return 0;
1810}
1811
1812static void config_aux_buf(struct AV1HW_s *hw)
1813{
1814 WRITE_VREG(HEVC_AUX_ADR, hw->aux_phy_addr);
1815 init_aux_size = ((hw->prefix_aux_size >> 4) << 16) |
1816 (hw->suffix_aux_size >> 4);
1817 WRITE_VREG(HEVC_AUX_DATA_SIZE, init_aux_size);
1818}
1819
1820/*
1821* dv_meta_flag: 1, dolby meta (T35) only; 2, not include dolby meta (T35)
1822*/
1823static void set_aux_data(struct AV1HW_s *hw,
1824 char **aux_data_buf, int *aux_data_size,
1825 unsigned char suffix_flag,
1826 unsigned char dv_meta_flag)
1827{
1828 int i;
1829 unsigned short *aux_adr;
1830 unsigned int size_reg_val =
1831 READ_VREG(HEVC_AUX_DATA_SIZE);
1832 unsigned int aux_count = 0;
1833 int aux_size = 0;
1834 if (0 == aux_data_is_avaible(hw))
1835 return;
1836
1837 if (hw->aux_data_dirty ||
1838 hw->m_ins_flag == 0) {
1839
1840 hw->aux_data_dirty = 0;
1841 }
1842
1843 if (suffix_flag) {
1844 aux_adr = (unsigned short *)
1845 (hw->aux_addr +
1846 hw->prefix_aux_size);
1847 aux_count =
1848 ((size_reg_val & 0xffff) << 4)
1849 >> 1;
1850 aux_size =
1851 hw->suffix_aux_size;
1852 } else {
1853 aux_adr =
1854 (unsigned short *)hw->aux_addr;
1855 aux_count =
1856 ((size_reg_val >> 16) << 4)
1857 >> 1;
1858 aux_size =
1859 hw->prefix_aux_size;
1860 }
1861 if (debug & AV1_DEBUG_BUFMGR_MORE) {
1862 av1_print(hw, 0,
1863 "%s:old size %d count %d,suf %d dv_flag %d\r\n",
1864 __func__, *aux_data_size,
1865 aux_count, suffix_flag, dv_meta_flag);
1866 }
1867 if (aux_size > 0 && aux_count > 0) {
1868 int heads_size = 0;
1869 int new_size;
1870 char *new_buf;
1871
1872 for (i = 0; i < aux_count; i++) {
1873 unsigned char tag = aux_adr[i] >> 8;
1874 if (tag != 0 && tag != 0xff) {
1875 if (dv_meta_flag == 0)
1876 heads_size += 8;
1877 else if (dv_meta_flag == 1 && tag == 0x14)
1878 heads_size += 8;
1879 else if (dv_meta_flag == 2 && tag != 0x14)
1880 heads_size += 8;
1881 }
1882 }
1883 new_size = *aux_data_size + aux_count + heads_size;
1884 new_buf = vmalloc(new_size);
1885 if (new_buf) {
1886 unsigned char valid_tag = 0;
1887 unsigned char *h =
1888 new_buf +
1889 *aux_data_size;
1890 unsigned char *p = h + 8;
1891 int len = 0;
1892 int padding_len = 0;
1893 if (*aux_data_buf) {
1894 memcpy(new_buf, *aux_data_buf, *aux_data_size);
1895 vfree(*aux_data_buf);
1896 }
1897 *aux_data_buf = new_buf;
1898 for (i = 0; i < aux_count; i += 4) {
1899 int ii;
1900 unsigned char tag = aux_adr[i + 3] >> 8;
1901 if (tag != 0 && tag != 0xff) {
1902 if (dv_meta_flag == 0)
1903 valid_tag = 1;
1904 else if (dv_meta_flag == 1
1905 && tag == 0x14)
1906 valid_tag = 1;
1907 else if (dv_meta_flag == 2
1908 && tag != 0x14)
1909 valid_tag = 1;
1910 else
1911 valid_tag = 0;
1912 if (valid_tag && len > 0) {
1913 *aux_data_size +=
1914 (len + 8);
1915 h[0] = (len >> 24)
1916 & 0xff;
1917 h[1] = (len >> 16)
1918 & 0xff;
1919 h[2] = (len >> 8)
1920 & 0xff;
1921 h[3] = (len >> 0)
1922 & 0xff;
1923 h[6] =
1924 (padding_len >> 8)
1925 & 0xff;
1926 h[7] = (padding_len)
1927 & 0xff;
1928 h += (len + 8);
1929 p += 8;
1930 len = 0;
1931 padding_len = 0;
1932 }
1933 if (valid_tag) {
1934 h[4] = tag;
1935 h[5] = 0;
1936 h[6] = 0;
1937 h[7] = 0;
1938 }
1939 }
1940 if (valid_tag) {
1941 for (ii = 0; ii < 4; ii++) {
1942 unsigned short aa =
1943 aux_adr[i + 3
1944 - ii];
1945 *p = aa & 0xff;
1946 p++;
1947 len++;
1948 if ((aa >> 8) == 0xff)
1949 padding_len++;
1950 }
1951 }
1952 }
1953 if (len > 0) {
1954 *aux_data_size += (len + 8);
1955 h[0] = (len >> 24) & 0xff;
1956 h[1] = (len >> 16) & 0xff;
1957 h[2] = (len >> 8) & 0xff;
1958 h[3] = (len >> 0) & 0xff;
1959 h[6] = (padding_len >> 8) & 0xff;
1960 h[7] = (padding_len) & 0xff;
1961 }
1962 if (debug & AV1_DEBUG_BUFMGR_MORE) {
1963 av1_print(hw, 0,
1964 "aux: (size %d) suffix_flag %d\n",
1965 *aux_data_size, suffix_flag);
1966 for (i = 0; i < *aux_data_size; i++) {
1967 av1_print_cont(hw, 0,
1968 "%02x ", (*aux_data_buf)[i]);
1969 if (((i + 1) & 0xf) == 0)
1970 av1_print_cont(hw, 0, "\n");
1971 }
1972 av1_print_cont(hw, 0, "\n");
1973 }
1974
1975 } else {
1976 av1_print(hw, 0, "new buf alloc failed\n");
1977 if (*aux_data_buf)
1978 vfree(*aux_data_buf);
1979 *aux_data_buf = NULL;
1980 *aux_data_size = 0;
1981 }
1982 }
1983
1984}
1985
1986static void set_dv_data(struct AV1HW_s *hw)
1987{
1988 set_aux_data(hw, &hw->dv_data_buf,
1989 &hw->dv_data_size, 0, 1);
1990
1991}
1992
1993static void set_pic_aux_data(struct AV1HW_s *hw,
1994 struct PIC_BUFFER_CONFIG_s *pic, unsigned char suffix_flag,
1995 unsigned char dv_meta_flag)
1996{
1997 if (pic == NULL)
1998 return;
1999 set_aux_data(hw, &pic->aux_data_buf,
2000 &pic->aux_data_size, suffix_flag, dv_meta_flag);
2001}
2002
2003static void copy_dv_data(struct AV1HW_s *hw,
2004 struct PIC_BUFFER_CONFIG_s *pic)
2005{
2006 char *new_buf;
2007 int new_size;
2008 new_size = pic->aux_data_size + hw->dv_data_size;
2009 new_buf = vmalloc(new_size);
2010 if (new_buf) {
2011 if (debug & AV1_DEBUG_BUFMGR_MORE) {
2012 av1_print(hw, 0,
2013 "%s: (size %d) pic index %d\n",
2014 __func__,
2015 hw->dv_data_size, pic->index);
2016 }
2017 if (pic->aux_data_buf) {
2018 memcpy(new_buf, pic->aux_data_buf, pic->aux_data_size);
2019 vfree(pic->aux_data_buf);
2020 }
2021 memcpy(new_buf + pic->aux_data_size, hw->dv_data_buf, hw->dv_data_size);
2022 pic->aux_data_size += hw->dv_data_size;
2023 pic->aux_data_buf = new_buf;
2024 vfree(hw->dv_data_buf);
2025 hw->dv_data_buf = NULL;
2026 hw->dv_data_size = 0;
2027 }
2028
2029}
2030
2031static void release_aux_data(struct AV1HW_s *hw,
2032 struct PIC_BUFFER_CONFIG_s *pic)
2033{
2034 if (pic->aux_data_buf)
2035 vfree(pic->aux_data_buf);
2036 pic->aux_data_buf = NULL;
2037 pic->aux_data_size = 0;
2038}
2039
2040static void dump_aux_buf(struct AV1HW_s *hw)
2041{
2042 int i;
2043 unsigned short *aux_adr =
2044 (unsigned short *)
2045 hw->aux_addr;
2046 unsigned int aux_size =
2047 (READ_VREG(HEVC_AUX_DATA_SIZE)
2048 >> 16) << 4;
2049
2050 if (hw->prefix_aux_size > 0) {
2051 av1_print(hw, 0,
2052 "prefix aux: (size %d)\n",
2053 aux_size);
2054 for (i = 0; i <
2055 (aux_size >> 1); i++) {
2056 av1_print_cont(hw, 0,
2057 "%04x ",
2058 *(aux_adr + i));
2059 if (((i + 1) & 0xf)
2060 == 0)
2061 av1_print_cont(hw,
2062 0, "\n");
2063 }
2064 }
2065 if (hw->suffix_aux_size > 0) {
2066 aux_adr = (unsigned short *)
2067 (hw->aux_addr +
2068 hw->prefix_aux_size);
2069 aux_size =
2070 (READ_VREG(HEVC_AUX_DATA_SIZE) & 0xffff)
2071 << 4;
2072 av1_print(hw, 0,
2073 "suffix aux: (size %d)\n",
2074 aux_size);
2075 for (i = 0; i <
2076 (aux_size >> 1); i++) {
2077 av1_print_cont(hw, 0,
2078 "%04x ", *(aux_adr + i));
2079 if (((i + 1) & 0xf) == 0)
2080 av1_print_cont(hw, 0, "\n");
2081 }
2082 }
2083}
2084
2085/*
2086*
2087*/
2088
2089/*Losless compression body buffer size 4K per 64x32 (jt)*/
2090static int compute_losless_comp_body_size(int width, int height,
2091 uint8_t is_bit_depth_10)
2092{
2093 int width_x64;
2094 int height_x32;
2095 int bsize;
2096
2097 width_x64 = width + 63;
2098 width_x64 >>= 6;
2099 height_x32 = height + 31;
2100 height_x32 >>= 5;
2101 bsize = (is_bit_depth_10?4096:3200)*width_x64*height_x32;
2102 if (debug & AV1_DEBUG_BUFMGR_MORE)
2103 pr_info("%s(%d,%d,%d)=>%d\n",
2104 __func__, width, height,
2105 is_bit_depth_10, bsize);
2106
2107 return bsize;
2108}
2109
2110/* Losless compression header buffer size 32bytes per 128x64 (jt)*/
2111static int compute_losless_comp_header_size(int width, int height)
2112{
2113 int width_x128;
2114 int height_x64;
2115 int hsize;
2116
2117 width_x128 = width + 127;
2118 width_x128 >>= 7;
2119 height_x64 = height + 63;
2120 height_x64 >>= 6;
2121
2122 hsize = 32 * width_x128 * height_x64;
2123 if (debug & AV1_DEBUG_BUFMGR_MORE)
2124 pr_info("%s(%d,%d)=>%d\n",
2125 __func__, width, height,
2126 hsize);
2127
2128 return hsize;
2129}
2130
2131#ifdef AOM_AV1_MMU_DW
2132static int compute_losless_comp_body_size_dw(int width, int height,
2133 uint8_t is_bit_depth_10)
2134{
2135
2136 return compute_losless_comp_body_size(width, height, is_bit_depth_10);
2137}
2138
2139/* Losless compression header buffer size 32bytes per 128x64 (jt)*/
2140static int compute_losless_comp_header_size_dw(int width, int height)
2141{
2142 return compute_losless_comp_header_size(width, height);
2143}
2144#endif
2145
2146static void init_buff_spec(struct AV1HW_s *hw,
2147 struct BuffInfo_s *buf_spec)
2148{
2149 void *mem_start_virt;
2150
2151 buf_spec->ipp.buf_start =
2152 buf_spec->start_adr;
2153 buf_spec->sao_abv.buf_start =
2154 buf_spec->ipp.buf_start + buf_spec->ipp.buf_size;
2155
2156 buf_spec->sao_vb.buf_start =
2157 buf_spec->sao_abv.buf_start + buf_spec->sao_abv.buf_size;
2158 buf_spec->short_term_rps.buf_start =
2159 buf_spec->sao_vb.buf_start + buf_spec->sao_vb.buf_size;
2160 buf_spec->vps.buf_start =
2161 buf_spec->short_term_rps.buf_start + buf_spec->short_term_rps.buf_size;
2162 buf_spec->seg_map.buf_start =
2163 buf_spec->vps.buf_start + buf_spec->vps.buf_size;
2164 buf_spec->daala_top.buf_start =
2165 buf_spec->seg_map.buf_start + buf_spec->seg_map.buf_size;
2166 buf_spec->sao_up.buf_start =
2167 buf_spec->daala_top.buf_start + buf_spec->daala_top.buf_size;
2168 buf_spec->swap_buf.buf_start =
2169 buf_spec->sao_up.buf_start + buf_spec->sao_up.buf_size;
2170 buf_spec->cdf_buf.buf_start =
2171 buf_spec->swap_buf.buf_start + buf_spec->swap_buf.buf_size;
2172 buf_spec->gmc_buf.buf_start =
2173 buf_spec->cdf_buf.buf_start + buf_spec->cdf_buf.buf_size;
2174 buf_spec->scalelut.buf_start =
2175 buf_spec->gmc_buf.buf_start + buf_spec->gmc_buf.buf_size;
2176 buf_spec->dblk_para.buf_start =
2177 buf_spec->scalelut.buf_start + buf_spec->scalelut.buf_size;
2178 buf_spec->dblk_data.buf_start =
2179 buf_spec->dblk_para.buf_start + buf_spec->dblk_para.buf_size;
2180 buf_spec->cdef_data.buf_start =
2181 buf_spec->dblk_data.buf_start + buf_spec->dblk_data.buf_size;
2182 buf_spec->ups_data.buf_start =
2183 buf_spec->cdef_data.buf_start + buf_spec->cdef_data.buf_size;
2184 buf_spec->fgs_table.buf_start =
2185 buf_spec->ups_data.buf_start + buf_spec->ups_data.buf_size;
2186#ifdef AOM_AV1_MMU
2187 buf_spec->mmu_vbh.buf_start =
2188 buf_spec->fgs_table.buf_start + buf_spec->fgs_table.buf_size;
2189 buf_spec->cm_header.buf_start =
2190 buf_spec->mmu_vbh.buf_start + buf_spec->mmu_vbh.buf_size;
2191#ifdef AOM_AV1_MMU_DW
2192 buf_spec->mmu_vbh_dw.buf_start =
2193 buf_spec->cm_header.buf_start + buf_spec->cm_header.buf_size;
2194 buf_spec->cm_header_dw.buf_start =
2195 buf_spec->mmu_vbh_dw.buf_start + buf_spec->mmu_vbh_dw.buf_size;
2196 buf_spec->mpred_above.buf_start =
2197 buf_spec->cm_header_dw.buf_start + buf_spec->cm_header_dw.buf_size;
2198#else
2199 buf_spec->mpred_above.buf_start =
2200 buf_spec->cm_header.buf_start + buf_spec->cm_header.buf_size;
2201#endif
2202#else
2203 buf_spec->mpred_above.buf_start =
2204 buf_spec->fgs_table.buf_start + buf_spec->fgs_table.buf_size;
2205#endif
2206
2207#ifdef MV_USE_FIXED_BUF
2208 buf_spec->mpred_mv.buf_start =
2209 buf_spec->mpred_above.buf_start +
2210 buf_spec->mpred_above.buf_size;
2211
2212 buf_spec->rpm.buf_start =
2213 buf_spec->mpred_mv.buf_start +
2214 buf_spec->mpred_mv.buf_size;
2215#else
2216 buf_spec->rpm.buf_start =
2217 buf_spec->mpred_above.buf_start +
2218 buf_spec->mpred_above.buf_size;
2219
2220#endif
2221 buf_spec->lmem.buf_start =
2222 buf_spec->rpm.buf_start +
2223 buf_spec->rpm.buf_size;
2224 buf_spec->end_adr =
2225 buf_spec->lmem.buf_start +
2226 buf_spec->lmem.buf_size;
2227
2228 if (!hw)
2229 return;
2230
2231 if (!vdec_secure(hw_to_vdec(hw))) {
2232 mem_start_virt =
2233 codec_mm_phys_to_virt(buf_spec->dblk_para.buf_start);
2234 if (mem_start_virt) {
2235 memset(mem_start_virt, 0,
2236 buf_spec->dblk_para.buf_size);
2237 codec_mm_dma_flush(mem_start_virt,
2238 buf_spec->dblk_para.buf_size,
2239 DMA_TO_DEVICE);
2240 } else {
2241 mem_start_virt = codec_mm_vmap(
2242 buf_spec->dblk_para.buf_start,
2243 buf_spec->dblk_para.buf_size);
2244 if (mem_start_virt) {
2245 memset(mem_start_virt, 0,
2246 buf_spec->dblk_para.buf_size);
2247 codec_mm_dma_flush(mem_start_virt,
2248 buf_spec->dblk_para.buf_size,
2249 DMA_TO_DEVICE);
2250 codec_mm_unmap_phyaddr(mem_start_virt);
2251 } else {
2252 /*not virt for tvp playing,
2253 may need clear on ucode.*/
2254 pr_err("mem_start_virt failed\n");
2255 }
2256 }
2257 }
2258
2259 if (debug) {
2260 pr_info("%s workspace (%x %x) size = %x\n", __func__,
2261 buf_spec->start_adr, buf_spec->end_adr,
2262 buf_spec->end_adr - buf_spec->start_adr);
2263 }
2264
2265 if (debug) {
2266 pr_info("ipp.buf_start :%x\n",
2267 buf_spec->ipp.buf_start);
2268 pr_info("sao_abv.buf_start :%x\n",
2269 buf_spec->sao_abv.buf_start);
2270 pr_info("sao_vb.buf_start :%x\n",
2271 buf_spec->sao_vb.buf_start);
2272 pr_info("short_term_rps.buf_start :%x\n",
2273 buf_spec->short_term_rps.buf_start);
2274 pr_info("vps.buf_start :%x\n",
2275 buf_spec->vps.buf_start);
2276 pr_info("seg_map.buf_start :%x\n",
2277 buf_spec->seg_map.buf_start);
2278 pr_info("daala_top.buf_start :%x\n",
2279 buf_spec->daala_top.buf_start);
2280 pr_info("swap_buf.buf_start :%x\n",
2281 buf_spec->swap_buf.buf_start);
2282 pr_info("cdf_buf.buf_start :%x\n",
2283 buf_spec->cdf_buf.buf_start);
2284 pr_info("gmc_buf.buf_start :%x\n",
2285 buf_spec->gmc_buf.buf_start);
2286 pr_info("scalelut.buf_start :%x\n",
2287 buf_spec->scalelut.buf_start);
2288 pr_info("dblk_para.buf_start :%x\n",
2289 buf_spec->dblk_para.buf_start);
2290 pr_info("dblk_data.buf_start :%x\n",
2291 buf_spec->dblk_data.buf_start);
2292 pr_info("cdef_data.buf_start :%x\n",
2293 buf_spec->cdef_data.buf_start);
2294 pr_info("ups_data.buf_start :%x\n",
2295 buf_spec->ups_data.buf_start);
2296
2297#ifdef AOM_AV1_MMU
2298 pr_info("mmu_vbh.buf_start :%x\n",
2299 buf_spec->mmu_vbh.buf_start);
2300#endif
2301 pr_info("mpred_above.buf_start :%x\n",
2302 buf_spec->mpred_above.buf_start);
2303#ifdef MV_USE_FIXED_BUF
2304 pr_info("mpred_mv.buf_start :%x\n",
2305 buf_spec->mpred_mv.buf_start);
2306#endif
2307 if ((debug & AOM_AV1_DEBUG_SEND_PARAM_WITH_REG) == 0) {
2308 pr_info("rpm.buf_start :%x\n",
2309 buf_spec->rpm.buf_start);
2310 }
2311 }
2312}
2313
2314
2315
2316static void uninit_mmu_buffers(struct AV1HW_s *hw)
2317{
2318#ifndef MV_USE_FIXED_BUF
2319 dealloc_mv_bufs(hw);
2320#endif
2321 if (hw->mmu_box)
2322 decoder_mmu_box_free(hw->mmu_box);
2323 hw->mmu_box = NULL;
2324
2325#ifdef AOM_AV1_MMU_DW
2326 if (hw->mmu_box_dw)
2327 decoder_mmu_box_free(hw->mmu_box_dw);
2328 hw->mmu_box_dw = NULL;
2329#endif
2330 if (hw->bmmu_box)
2331 decoder_bmmu_box_free(hw->bmmu_box);
2332 hw->bmmu_box = NULL;
2333}
2334
2335
2336static int config_pic(struct AV1HW_s *hw,
2337 struct PIC_BUFFER_CONFIG_s *pic_config)
2338{
2339 int ret = -1;
2340 int i;
2341 int pic_width = hw->init_pic_w;
2342 int pic_height = hw->init_pic_h;
2343 //int lcu_size = ((params->p.seq_flags >> 6) & 0x1) ? 128 : 64;
2344 int lcu_size = hw->current_lcu_size;
2345
2346 int pic_width_64 = (pic_width + 63) & (~0x3f);
2347 int pic_height_32 = (pic_height + 31) & (~0x1f);
2348 int pic_width_lcu = (pic_width_64 % lcu_size) ?
2349 pic_width_64 / lcu_size + 1
2350 : pic_width_64 / lcu_size;
2351 int pic_height_lcu = (pic_height_32 % lcu_size) ?
2352 pic_height_32 / lcu_size + 1
2353 : pic_height_32 / lcu_size;
2354 int lcu_total = pic_width_lcu * pic_height_lcu;
2355#ifdef MV_USE_FIXED_BUF
2356 u32 mpred_mv_end = hw->work_space_buf->mpred_mv.buf_start +
2357 hw->work_space_buf->mpred_mv.buf_size;
2358#ifdef USE_DYNAMIC_MV_BUFFER
2359 int32_t MV_MEM_UNIT = (lcu_size == 128) ? (19*4*16) : (19*16);
2360 int32_t mv_buffer_size = (lcu_total*MV_MEM_UNIT);
2361#else
2362 int32_t mv_buffer_size = MAX_ONE_MV_BUFFER_SIZE;
2363#endif
2364
2365#endif
2366
2367 u32 y_adr = 0;
2368 int buf_size = 0;
2369
2370 int losless_comp_header_size =
2371 compute_losless_comp_header_size(pic_width,
2372 pic_height);
2373 int losless_comp_body_size = compute_losless_comp_body_size(pic_width,
2374 pic_height, buf_alloc_depth == 10);
2375 int mc_buffer_size = losless_comp_header_size + losless_comp_body_size;
2376 int mc_buffer_size_h = (mc_buffer_size + 0xffff) >> 16;
2377 int mc_buffer_size_u_v = 0;
2378 int mc_buffer_size_u_v_h = 0;
2379 int dw_mode = get_double_write_mode_init(hw);
2380 struct vdec_v4l2_buffer *fb = NULL;
2381
2382 hw->lcu_total = lcu_total;
2383
2384 if (dw_mode && (dw_mode & 0x20) == 0) {
2385 int pic_width_dw = pic_width /
2386 get_double_write_ratio(hw, dw_mode);
2387 int pic_height_dw = pic_height /
2388 get_double_write_ratio(hw, dw_mode);
2389
2390 int pic_width_64_dw = (pic_width_dw + 63) & (~0x3f);
2391 int pic_height_32_dw = (pic_height_dw + 31) & (~0x1f);
2392 int pic_width_lcu_dw = (pic_width_64_dw % lcu_size) ?
2393 pic_width_64_dw / lcu_size + 1
2394 : pic_width_64_dw / lcu_size;
2395 int pic_height_lcu_dw = (pic_height_32_dw % lcu_size) ?
2396 pic_height_32_dw / lcu_size + 1
2397 : pic_height_32_dw / lcu_size;
2398 int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw;
2399 mc_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2;
2400 mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff) >> 16;
2401 /*64k alignment*/
2402 buf_size = ((mc_buffer_size_u_v_h << 16) * 3);
2403 buf_size = ((buf_size + 0xffff) >> 16) << 16;
2404 }
2405
2406 if (mc_buffer_size & 0xffff) /*64k alignment*/
2407 mc_buffer_size_h += 1;
2408 if ((!hw->mmu_enable) && ((dw_mode & 0x10) == 0))
2409 buf_size += (mc_buffer_size_h << 16);
2410
2411#ifdef USE_SPEC_BUF_FOR_MMU_HEAD
2412 if (hw->mmu_enable) {
2413 pic_config->header_adr =
2414 hw->work_space_buf->cm_header.buf_start +
2415 (pic_config->index * MMU_COMPRESS_HEADER_SIZE);
2416
2417#ifdef AOM_AV1_MMU_DW
2418 if (hw->dw_mmu_enable) {
2419 pic_config->header_dw_adr =
2420 hw->work_space_buf->cm_header_dw.buf_start +
2421 (pic_config->index * MMU_COMPRESS_HEADER_SIZE_DW);
2422
2423 }
2424#endif
2425 }
2426
2427#else
2428/*!USE_SPEC_BUF_FOR_MMU_HEAD*/
2429 if (hw->mmu_enable) {
2430 pic_config->header_adr = decoder_bmmu_box_get_phy_addr(
2431 hw->bmmu_box, HEADER_BUFFER_IDX(pic_config->index));
2432
2433#ifdef AOM_AV1_MMU_DW
2434 if (hw->dw_mmu_enable) {
2435 pic_config->header_dw_adr = decoder_bmmu_box_get_phy_addr(
2436 hw->bmmu_box, DW_HEADER_BUFFER_IDX(pic_config->index));
2437
2438 }
2439 if (debug & AV1_DEBUG_BUFMGR_MORE) {
2440 pr_info("MMU dw header_adr (%d, %d) %d: %d\n",
2441 hw->dw_mmu_enable,
2442 DW_HEADER_BUFFER_IDX(pic_config->index),
2443 pic_config->index,
2444 pic_config->header_dw_adr);
2445 }
2446#endif
2447
2448 if (debug & AV1_DEBUG_BUFMGR_MORE) {
2449 pr_info("MMU header_adr %d: %d\n",
2450 pic_config->index, pic_config->header_adr);
2451 }
2452 }
2453#endif
2454
2455 i = pic_config->index;
2456#ifdef MV_USE_FIXED_BUF
2457 if ((hw->work_space_buf->mpred_mv.buf_start +
2458 ((i + 1) * mv_buffer_size))
2459 <= mpred_mv_end
2460 ) {
2461#endif
2462 if (buf_size > 0) {
2463 if (hw->is_used_v4l) {
2464#ifdef SUPPORT_V4L2
2465 ret = vdec_v4l_get_buffer(hw->v4l2_ctx, &fb);
2466#endif
2467 if (ret) {
2468 av1_print(hw, PRINT_FLAG_ERROR,
2469 "[%d] get fb fail.\n",
2470 ((struct aml_vcodec_ctx *)
2471 (hw->v4l2_ctx))->id);
2472 return ret;
2473 }
2474
2475 hw->m_BUF[i].v4l_ref_buf_addr = (ulong)fb;
2476#ifdef SUPPORT_V4L2
2477 pic_config->cma_alloc_addr = fb->m.mem[0].addr;
2478#endif
2479 av1_print(hw, PRINT_FLAG_V4L_DETAIL,
2480 "[%d] %s(), v4l ref buf addr: 0x%x\n",
2481 ((struct aml_vcodec_ctx *)
2482 (hw->v4l2_ctx))->id, __func__, fb);
2483 } else {
2484 ret = decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box,
2485 VF_BUFFER_IDX(i),
2486 buf_size, DRIVER_NAME,
2487 &pic_config->cma_alloc_addr);
2488 if (ret < 0) {
2489 pr_info(
2490 "decoder_bmmu_box_alloc_buf_phy idx %d size %d fail\n",
2491 VF_BUFFER_IDX(i),
2492 buf_size
2493 );
2494 return ret;
2495 }
2496 }
2497
2498 if (pic_config->cma_alloc_addr)
2499 y_adr = pic_config->cma_alloc_addr;
2500 else {
2501 pr_info(
2502 "decoder_bmmu_box_alloc_buf_phy idx %d size %d return null\n",
2503 VF_BUFFER_IDX(i),
2504 buf_size
2505 );
2506 return -1;
2507 }
2508 }
2509 {
2510 /*ensure get_pic_by_POC()
2511 not get the buffer not decoded*/
2512 pic_config->BUF_index = i;
2513 pic_config->lcu_total = lcu_total;
2514
2515 pic_config->comp_body_size = losless_comp_body_size;
2516 pic_config->buf_size = buf_size;
2517
2518 pic_config->mc_canvas_y = pic_config->index;
2519 pic_config->mc_canvas_u_v = pic_config->index;
2520 if (dw_mode & 0x10) {
2521 pic_config->dw_y_adr = y_adr;
2522 pic_config->dw_u_v_adr = y_adr +
2523 ((mc_buffer_size_u_v_h << 16) << 1);
2524
2525 pic_config->mc_canvas_y =
2526 (pic_config->index << 1);
2527 pic_config->mc_canvas_u_v =
2528 (pic_config->index << 1) + 1;
2529 } else if (dw_mode && (dw_mode & 0x20) == 0) {
2530 pic_config->dw_y_adr = y_adr;
2531 pic_config->dw_u_v_adr = pic_config->dw_y_adr +
2532 ((mc_buffer_size_u_v_h << 16) << 1);
2533 }
2534#ifdef MV_USE_FIXED_BUF
2535 pic_config->mpred_mv_wr_start_addr =
2536 hw->work_space_buf->mpred_mv.buf_start +
2537 (pic_config->index * mv_buffer_size);
2538#endif
2539#ifdef DUMP_FILMGRAIN
2540 if (pic_config->index == fg_dump_index) {
2541 pic_config->fgs_table_adr = hw->fg_phy_addr;
2542 pr_info("set buffer %d film grain table 0x%x\n",
2543 pic_config->index, pic_config->fgs_table_adr);
2544 } else
2545#endif
2546 pic_config->fgs_table_adr =
2547 hw->work_space_buf->fgs_table.buf_start +
2548 (pic_config->index * FGS_TABLE_SIZE);
2549
2550 if (debug) {
2551 pr_info
2552 ("%s index %d BUF_index %d ",
2553 __func__, pic_config->index,
2554 pic_config->BUF_index);
2555 pr_info
2556 ("comp_body_size %x comp_buf_size %x ",
2557 pic_config->comp_body_size,
2558 pic_config->buf_size);
2559 pr_info
2560 ("mpred_mv_wr_start_adr %d\n",
2561 pic_config->mpred_mv_wr_start_addr);
2562 pr_info("dw_y_adr %d, pic_config->dw_u_v_adr =%d\n",
2563 pic_config->dw_y_adr,
2564 pic_config->dw_u_v_adr);
2565 }
2566 ret = 0;
2567 }
2568#ifdef MV_USE_FIXED_BUF
2569 }
2570#endif
2571 return ret;
2572}
2573
2574#ifndef USE_SPEC_BUF_FOR_MMU_HEAD
2575static int vav1_mmu_compress_header_size(struct AV1HW_s *hw)
2576{
2577 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
2578 IS_8K_SIZE(hw->max_pic_w, hw->max_pic_h))
2579 return (MMU_COMPRESS_8K_HEADER_SIZE);
2580
2581 return (MMU_COMPRESS_HEADER_SIZE);
2582}
2583#endif
2584/*#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)*/
2585static int vav1_frame_mmu_map_size(struct AV1HW_s *hw)
2586{
2587 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
2588 IS_8K_SIZE(hw->max_pic_w, hw->max_pic_h))
2589 return (MAX_FRAME_8K_NUM * 4);
2590
2591 return (MAX_FRAME_4K_NUM * 4);
2592}
2593
2594#ifdef AOM_AV1_MMU_DW
2595static int vaom_dw_frame_mmu_map_size(struct AV1HW_s *hw)
2596{
2597 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
2598 IS_8K_SIZE(hw->max_pic_w, hw->max_pic_h))
2599 return (MAX_FRAME_8K_NUM * 4);
2600
2601 return (MAX_FRAME_4K_NUM * 4);
2602}
2603#endif
2604
2605static void init_pic_list(struct AV1HW_s *hw)
2606{
2607 int i;
2608 struct AV1_Common_s *cm = &hw->pbi->common;
2609 struct PIC_BUFFER_CONFIG_s *pic_config;
2610 struct vdec_s *vdec = hw_to_vdec(hw);
2611
2612#ifndef USE_SPEC_BUF_FOR_MMU_HEAD
2613 u32 header_size;
2614 if (hw->mmu_enable && ((hw->double_write_mode & 0x10) == 0)) {
2615 header_size = vav1_mmu_compress_header_size(hw);
2616 /*alloc AV1 compress header first*/
2617 for (i = 0; i < hw->used_buf_num; i++) {
2618 unsigned long buf_addr;
2619 if (decoder_bmmu_box_alloc_buf_phy
2620 (hw->bmmu_box,
2621 HEADER_BUFFER_IDX(i), header_size,
2622 DRIVER_HEADER_NAME,
2623 &buf_addr) < 0) {
2624 av1_print(hw, 0, "%s malloc compress header failed %d\n",
2625 DRIVER_HEADER_NAME, i);
2626 hw->fatal_error |= DECODER_FATAL_ERROR_NO_MEM;
2627 return;
2628 }
2629#ifdef AOM_AV1_MMU_DW
2630 if (hw->dw_mmu_enable) {
2631 if (decoder_bmmu_box_alloc_buf_phy
2632 (hw->bmmu_box,
2633 DW_HEADER_BUFFER_IDX(i), header_size,
2634 DRIVER_HEADER_NAME,
2635 &buf_addr) < 0) {
2636 av1_print(hw, 0, "%s malloc compress dw header failed %d\n",
2637 DRIVER_HEADER_NAME, i);
2638 hw->fatal_error |= DECODER_FATAL_ERROR_NO_MEM;
2639 return;
2640 }
2641 }
2642#endif
2643 }
2644 }
2645#endif
2646 for (i = 0; i < hw->used_buf_num; i++) {
2647 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
2648 pic_config->index = i;
2649 pic_config->BUF_index = -1;
2650 pic_config->mv_buf_index = -1;
2651 if (vdec->parallel_dec == 1) {
2652 pic_config->y_canvas_index = -1;
2653 pic_config->uv_canvas_index = -1;
2654 }
2655 if (config_pic(hw, pic_config) < 0) {
2656 if (debug)
2657 av1_print(hw, 0, "Config_pic %d fail\n",
2658 pic_config->index);
2659 pic_config->index = -1;
2660 break;
2661 }
2662 pic_config->y_crop_width = hw->init_pic_w;
2663 pic_config->y_crop_height = hw->init_pic_h;
2664 pic_config->double_write_mode = get_double_write_mode(hw);
2665
2666 if (pic_config->double_write_mode &&
2667 (pic_config->double_write_mode & 0x20) == 0) {
2668 set_canvas(hw, pic_config);
2669 }
2670 }
2671 for (; i < hw->used_buf_num; i++) {
2672 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
2673 pic_config->index = -1;
2674 pic_config->BUF_index = -1;
2675 pic_config->mv_buf_index = -1;
2676 if (vdec->parallel_dec == 1) {
2677 pic_config->y_canvas_index = -1;
2678 pic_config->uv_canvas_index = -1;
2679 }
2680 }
2681 av1_print(hw, AV1_DEBUG_BUFMGR, "%s ok, used_buf_num = %d\n",
2682 __func__, hw->used_buf_num);
2683
2684}
2685
2686static void init_pic_list_hw(struct AV1HW_s *hw)
2687{
2688 int i;
2689 struct AV1_Common_s *cm = &hw->pbi->common;
2690 struct PIC_BUFFER_CONFIG_s *pic_config;
2691 /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x0);*/
2692 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
2693 (0x1 << 1) | (0x1 << 2));
2694
2695
2696 for (i = 0; i < hw->used_buf_num; i++) {
2697 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
2698 if (pic_config->index < 0)
2699 break;
2700
2701 if (hw->mmu_enable && ((pic_config->double_write_mode & 0x10) == 0)) {
2702
2703 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
2704 pic_config->header_adr >> 5);
2705 } else {
2706 /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
2707 * pic_config->mc_y_adr
2708 * | (pic_config->mc_canvas_y << 8) | 0x1);
2709 */
2710 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
2711 pic_config->dw_y_adr >> 5);
2712 }
2713#ifndef LOSLESS_COMPRESS_MODE
2714 /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
2715 * pic_config->mc_u_v_adr
2716 * | (pic_config->mc_canvas_u_v << 8)| 0x1);
2717 */
2718 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
2719 pic_config->dw_u_v_adr >> 5);
2720#else
2721 if (pic_config->double_write_mode & 0x10) {
2722 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
2723 pic_config->dw_u_v_adr >> 5);
2724 }
2725#endif
2726 }
2727 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
2728
2729#ifdef CHANGE_REMOVED
2730 /*Zero out canvas registers in IPP -- avoid simulation X*/
2731 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2732 (0 << 8) | (0 << 1) | 1);
2733#else
2734 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2735 (1 << 8) | (0 << 1) | 1);
2736#endif
2737 for (i = 0; i < 32; i++)
2738 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
2739}
2740
2741
2742static void dump_pic_list(struct AV1HW_s *hw)
2743{
2744 struct AV1_Common_s *const cm = &hw->pbi->common;
2745 struct PIC_BUFFER_CONFIG_s *pic_config;
2746 int i;
2747 for (i = 0; i < FRAME_BUFFERS; i++) {
2748 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
2749 av1_print(hw, 0,
2750 "Buf(%d) index %d mv_buf_index %d ref_count %d vf_ref %d dec_idx %d slice_type %d w/h %d/%d adr%ld\n",
2751 i,
2752 pic_config->index,
2753#ifndef MV_USE_FIXED_BUF
2754 pic_config->mv_buf_index,
2755#else
2756 -1,
2757#endif
2758 cm->buffer_pool->
2759 frame_bufs[i].ref_count,
2760 pic_config->vf_ref,
2761 pic_config->decode_idx,
2762 pic_config->slice_type,
2763 pic_config->y_crop_width,
2764 pic_config->y_crop_height,
2765 pic_config->cma_alloc_addr
2766 );
2767 }
2768 return;
2769}
2770
2771void av1_release_buf(AV1Decoder *pbi, RefCntBuffer *const buf)
2772{
2773
2774#if 0
2775 //def CHANGE_DONE
2776 struct AV1HW_s *hw = (struct AV1HW_s *)(pbi->private_data);
2777 if (!hw->mmu_enable)
2778 return;
2779 //release_buffer_4k(&av1_mmumgr_m, buf->buf.index);
2780 decoder_mmu_box_free_idx(hw->mmu_box, buf->buf.index);
2781#ifdef AOM_AV1_MMU_DW
2782 //release_buffer_4k(&av1_mmumgr_dw, buf->buf.index);
2783 decoder_mmu_box_free_idx(hw->mmu_box_dw, buf->buf.index);
2784#endif
2785
2786#endif
2787}
2788
2789void av1_release_bufs(struct AV1HW_s *hw)
2790{
2791 /*struct AV1HW_s *hw = (struct AV1HW_s *)(pbi->private_data);*/
2792 AV1_COMMON *cm = &hw->pbi->common;
2793 RefCntBuffer *const frame_bufs = cm->buffer_pool->frame_bufs;
2794 int i;
2795 if (!hw->mmu_enable)
2796 return;
2797
2798 for (i = 0; i < FRAME_BUFFERS; ++i) {
2799 if (frame_bufs[i].buf.vf_ref == 0 &&
2800 frame_bufs[i].ref_count == 0 &&
2801 frame_bufs[i].buf.index >= 0) {
2802 //release_buffer_4k(&av1_mmumgr_m, i);
2803 decoder_mmu_box_free_idx(hw->mmu_box, i);
2804#ifdef AOM_AV1_MMU_DW
2805 //release_buffer_4k(&av1_mmumgr_dw, i);
2806 if (hw->dw_mmu_enable)
2807 decoder_mmu_box_free_idx(hw->mmu_box_dw, i);
2808#endif
2809 if (frame_bufs[i].buf.aux_data_buf)
2810 release_aux_data(hw, &frame_bufs[i].buf);
2811 }
2812 }
2813}
2814
2815static int config_pic_size(struct AV1HW_s *hw, unsigned short bit_depth)
2816{
2817 uint32_t data32;
2818 struct AV1_Common_s *cm = &hw->pbi->common;
2819 struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf;
2820 int losless_comp_header_size, losless_comp_body_size;
2821#ifdef AOM_AV1_MMU_DW
2822 int losless_comp_header_size_dw, losless_comp_body_size_dw;
2823#endif
2824 av1_print(hw, AOM_DEBUG_HW_MORE,
2825 " #### config_pic_size ####, bit_depth = %d\n", bit_depth);
2826
2827 frame_width = cur_pic_config->y_crop_width;
2828 frame_height = cur_pic_config->y_crop_height;
2829 cur_pic_config->bit_depth = bit_depth;
2830 cur_pic_config->double_write_mode = get_double_write_mode(hw);
2831
2832 /* use fixed maximum size // 128x128/4/4*3-bits = 384 Bytes
2833 seg_map_size =
2834 ((frame_width + 127) >> 7) * ((frame_height + 127) >> 7) * 384 ;
2835 */
2836 WRITE_VREG(HEVC_PARSER_PICTURE_SIZE,
2837 (frame_height << 16) | frame_width);
2838#ifdef DUAL_DECODE
2839#else
2840 WRITE_VREG(HEVC_ASSIST_PIC_SIZE_FB_READ,
2841 (frame_height << 16) | frame_width);
2842#endif
2843#ifdef AOM_AV1_MMU
2844
2845 //alloc_mmu(&av1_mmumgr_m, cm->cur_frame->buf.index, frame_width, frame_height, bit_depth);
2846#endif
2847#ifdef AOM_AV1_MMU_DW
2848
2849 //alloc_mmu(&av1_mmumgr_dw, cm->cur_frame->buf.index, frame_width, frame_height, bit_depth);
2850 losless_comp_header_size_dw =
2851 compute_losless_comp_header_size_dw(frame_width, frame_height);
2852 losless_comp_body_size_dw =
2853 compute_losless_comp_body_size_dw(frame_width, frame_height,
2854 (bit_depth == AOM_BITS_10));
2855#endif
2856
2857 losless_comp_header_size =
2858 compute_losless_comp_header_size
2859 (frame_width, frame_height);
2860 losless_comp_body_size =
2861 compute_losless_comp_body_size(frame_width,
2862 frame_height, (bit_depth == AOM_BITS_10));
2863
2864 cur_pic_config->comp_body_size = losless_comp_body_size;
2865
2866 av1_print(hw, AOM_DEBUG_HW_MORE,
2867 "%s: width %d height %d depth %d head_size 0x%x body_size 0x%x\r\n",
2868 __func__, frame_width, frame_height, bit_depth,
2869 losless_comp_header_size, losless_comp_body_size);
2870#ifdef LOSLESS_COMPRESS_MODE
2871 data32 = READ_VREG(HEVC_SAO_CTRL5);
2872 if (bit_depth == AOM_BITS_10)
2873 data32 &= ~(1<<9);
2874 else
2875 data32 |= (1<<9);
2876
2877 WRITE_VREG(HEVC_SAO_CTRL5, data32);
2878
2879 if (hw->mmu_enable) {
2880 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1,(0x1<< 4)); // bit[4] : paged_mem_mode
2881 } else {
2882 if (bit_depth == AOM_BITS_10)
2883 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0<<3)); // bit[3] smem mdoe
2884 else
2885 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (1<<3)); // bit[3] smem mdoe
2886 }
2887 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2,
2888 (losless_comp_body_size >> 5));
2889 /*
2890 WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,
2891 (0xff<<20) | (0xff<<10) | 0xff); //8-bit mode
2892 */
2893 WRITE_VREG(HEVC_CM_BODY_LENGTH,
2894 losless_comp_body_size);
2895 WRITE_VREG(HEVC_CM_HEADER_OFFSET,
2896 losless_comp_body_size);
2897 WRITE_VREG(HEVC_CM_HEADER_LENGTH,
2898 losless_comp_header_size);
2899
2900 if (get_double_write_mode(hw) & 0x10)
2901 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
2902
2903#else
2904 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1,0x1 << 31);
2905#endif
2906#ifdef AOM_AV1_MMU_DW
2907 if (hw->dw_mmu_enable) {
2908 WRITE_VREG(HEVC_CM_BODY_LENGTH2, losless_comp_body_size_dw);
2909 WRITE_VREG(HEVC_CM_HEADER_OFFSET2, losless_comp_body_size_dw);
2910 WRITE_VREG(HEVC_CM_HEADER_LENGTH2, losless_comp_header_size_dw);
2911 }
2912#endif
2913 return 0;
2914
2915}
2916
2917static int config_mc_buffer(struct AV1HW_s *hw, unsigned short bit_depth, unsigned char inter_flag)
2918{
2919 int32_t i;
2920 AV1_COMMON *cm = &hw->pbi->common;
2921 PIC_BUFFER_CONFIG* cur_pic_config = &cm->cur_frame->buf;
2922 uint8_t scale_enable = 0;
2923
2924 av1_print(hw, AOM_DEBUG_HW_MORE,
2925 " #### config_mc_buffer %s ####\n",
2926 inter_flag ? "inter" : "intra");
2927
2928#ifdef DEBUG_PRINT
2929 if (debug&AOM_AV1_DEBUG_BUFMGR)
2930 av1_print(hw, AOM_DEBUG_HW_MORE,
2931 "config_mc_buffer entered .....\n");
2932#endif
2933
2934 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2935 (0 << 8) | (0<<1) | 1);
2936 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
2937 (cur_pic_config->order_hint<<24) |
2938 (cur_pic_config->mc_canvas_u_v<<16) |
2939 (cur_pic_config->mc_canvas_u_v<<8)|
2940 cur_pic_config->mc_canvas_y);
2941 for (i = LAST_FRAME; i <= ALTREF_FRAME; i++) {
2942 PIC_BUFFER_CONFIG *pic_config; //cm->frame_refs[i].buf;
2943 if (inter_flag)
2944 pic_config = av1_get_ref_frame_spec_buf(cm, i);
2945 else
2946 pic_config = cur_pic_config;
2947 if (pic_config) {
2948 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
2949 (pic_config->order_hint<<24) |
2950 (pic_config->mc_canvas_u_v<<16) |
2951 (pic_config->mc_canvas_u_v<<8) |
2952 pic_config->mc_canvas_y);
2953 if (inter_flag)
2954 av1_print(hw, AOM_DEBUG_HW_MORE,
2955 "refid 0x%x mc_canvas_u_v 0x%x mc_canvas_y 0x%x order_hint 0x%x\n",
2956 i, pic_config->mc_canvas_u_v,
2957 pic_config->mc_canvas_y, pic_config->order_hint);
2958 } else {
2959 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
2960 }
2961 }
2962
2963 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2964 (16 << 8) | (0 << 1) | 1);
2965 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
2966 (cur_pic_config->order_hint << 24) |
2967 (cur_pic_config->mc_canvas_u_v << 16) |
2968 (cur_pic_config->mc_canvas_u_v << 8) |
2969 cur_pic_config->mc_canvas_y);
2970 for (i = LAST_FRAME; i <= ALTREF_FRAME; i++) {
2971 PIC_BUFFER_CONFIG *pic_config;
2972 if (inter_flag)
2973 pic_config = av1_get_ref_frame_spec_buf(cm, i);
2974 else
2975 pic_config = cur_pic_config;
2976
2977 if (pic_config) {
2978 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
2979 (pic_config->order_hint << 24)|
2980 (pic_config->mc_canvas_u_v << 16) |
2981 (pic_config->mc_canvas_u_v << 8) |
2982 pic_config->mc_canvas_y);
2983 } else {
2984 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
2985 }
2986 }
2987
2988 WRITE_VREG(AV1D_MPP_REFINFO_TBL_ACCCONFIG,
2989 (0x1 << 2) | (0x0 <<3)); // auto_inc start index:0 field:0
2990 for (i = 0; i <= ALTREF_FRAME; i++) {
2991 int32_t ref_pic_body_size;
2992 struct scale_factors * sf = NULL;
2993 PIC_BUFFER_CONFIG *pic_config;
2994
2995 if (inter_flag && i >= LAST_FRAME)
2996 pic_config = av1_get_ref_frame_spec_buf(cm, i);
2997 else
2998 pic_config = cur_pic_config;
2999
3000 if (pic_config) {
3001 ref_pic_body_size =
3002 compute_losless_comp_body_size(pic_config->y_crop_width,
3003 pic_config->y_crop_height, (bit_depth == AOM_BITS_10));
3004
3005 WRITE_VREG(AV1D_MPP_REFINFO_DATA, pic_config->y_crop_width);
3006 WRITE_VREG(AV1D_MPP_REFINFO_DATA, pic_config->y_crop_height);
3007 if (inter_flag && i >= LAST_FRAME) {
3008 av1_print(hw, AOM_DEBUG_HW_MORE,
3009 "refid %d: ref width/height(%d,%d), cur width/height(%d,%d) ref_pic_body_size 0x%x\n",
3010 i, pic_config->y_crop_width, pic_config->y_crop_height,
3011 cur_pic_config->y_crop_width, cur_pic_config->y_crop_height,
3012 ref_pic_body_size);
3013 }
3014 } else {
3015 ref_pic_body_size = 0;
3016 WRITE_VREG(AV1D_MPP_REFINFO_DATA, 0);
3017 WRITE_VREG(AV1D_MPP_REFINFO_DATA, 0);
3018 }
3019
3020 if (inter_flag && i >= LAST_FRAME)
3021 sf = av1_get_ref_scale_factors(cm, i);
3022
3023 if ((sf != NULL) && av1_is_scaled(sf)) {
3024 scale_enable |= (1 << i);
3025 }
3026
3027 if (sf) {
3028 WRITE_VREG(AV1D_MPP_REFINFO_DATA, sf->x_scale_fp);
3029 WRITE_VREG(AV1D_MPP_REFINFO_DATA, sf->y_scale_fp);
3030
3031 av1_print(hw, AOM_DEBUG_HW_MORE,
3032 "x_scale_fp %d, y_scale_fp %d\n",
3033 sf->x_scale_fp, sf->y_scale_fp);
3034 } else {
3035 WRITE_VREG(AV1D_MPP_REFINFO_DATA, REF_NO_SCALE); //1<<14
3036 WRITE_VREG(AV1D_MPP_REFINFO_DATA, REF_NO_SCALE);
3037 }
3038 if (hw->mmu_enable)
3039 WRITE_VREG(AV1D_MPP_REFINFO_DATA, 0);
3040 else
3041 WRITE_VREG(AV1D_MPP_REFINFO_DATA,
3042 ref_pic_body_size >> 5);
3043 }
3044 WRITE_VREG(AV1D_MPP_REF_SCALE_ENBL, scale_enable);
3045 WRITE_VREG(PARSER_REF_SCALE_ENBL, scale_enable);
3046 av1_print(hw, AOM_DEBUG_HW_MORE,
3047 "WRITE_VREG(PARSER_REF_SCALE_ENBL, 0x%x)\n",
3048 scale_enable);
3049 return 0;
3050}
3051
3052static void clear_mpred_hw(struct AV1HW_s *hw)
3053{
3054 unsigned int data32;
3055
3056 data32 = READ_VREG(HEVC_MPRED_CTRL4);
3057 data32 &= (~(1 << 6));
3058 WRITE_VREG(HEVC_MPRED_CTRL4, data32);
3059}
3060
3061static void config_mpred_hw(struct AV1HW_s *hw, unsigned char inter_flag)
3062{
3063 AV1_COMMON *cm = &hw->pbi->common;
3064 PIC_BUFFER_CONFIG *cur_pic_config = &cm->cur_frame->buf;
3065 //PIC_BUFFER_CONFIG *last_frame_pic_config = NULL;
3066 int i, j, pos, reg_i;
3067 int mv_cal_tpl_count = 0;
3068 unsigned int mv_ref_id[MFMV_STACK_SIZE] = {0, 0, 0};
3069 unsigned ref_offset_reg[] = {
3070 HEVC_MPRED_L0_REF06_POC,
3071 HEVC_MPRED_L0_REF07_POC,
3072 HEVC_MPRED_L0_REF08_POC,
3073 HEVC_MPRED_L0_REF09_POC,
3074 HEVC_MPRED_L0_REF10_POC,
3075 HEVC_MPRED_L0_REF11_POC,
3076 };
3077 unsigned ref_buf_reg[] = {
3078 HEVC_MPRED_L0_REF03_POC,
3079 HEVC_MPRED_L0_REF04_POC,
3080 HEVC_MPRED_L0_REF05_POC
3081 };
3082 unsigned ref_offset_val[6] =
3083 {0, 0, 0, 0, 0, 0};
3084 unsigned ref_buf_val[3] = {0, 0, 0};
3085
3086 uint32_t data32;
3087 int32_t mpred_curr_lcu_x;
3088 int32_t mpred_curr_lcu_y;
3089 //int32_t mpred_mv_rd_end_addr;
3090
3091 av1_print(hw, AOM_DEBUG_HW_MORE,
3092 " #### config_mpred_hw ####\n");
3093
3094 /*if (cm->prev_frame)
3095 last_frame_pic_config = &cm->prev_frame->buf;
3096 mpred_mv_rd_end_addr = last_frame_pic_config->mpred_mv_wr_start_addr
3097 + (last_frame_pic_config->lcu_total * MV_MEM_UNIT);
3098 */
3099
3100 data32 = READ_VREG(HEVC_MPRED_CURR_LCU);
3101 mpred_curr_lcu_x =data32 & 0xffff;
3102 mpred_curr_lcu_y =(data32>>16) & 0xffff;
3103
3104 av1_print(hw, AOM_DEBUG_HW_MORE,
3105 "cur pic index %d\n", cur_pic_config->index);
3106 /*printk("cur pic index %d col pic index %d\n",
3107 cur_pic_config->index, last_frame_pic_config->index);*/
3108
3109 //WRITE_VREG(HEVC_MPRED_CTRL3,0x24122412);
3110 WRITE_VREG(HEVC_MPRED_CTRL3, 0x13151315); // 'd19, 'd21 for AV1
3111 WRITE_VREG(HEVC_MPRED_ABV_START_ADDR,
3112 hw->pbi->work_space_buf->mpred_above.buf_start);
3113
3114#if 0
3115 data32 = READ_VREG(HEVC_MPRED_CTRL4);
3116 data32 &= (~(1<<6));
3117 data32 |= (cm->use_prev_frame_mvs << 6);
3118 WRITE_VREG(HEVC_MPRED_CTRL4, data32);
3119#endif
3120 if (inter_flag) {
3121 /* config sign_bias */
3122 //data32 = (cm->cur_frame_force_integer_mv & 0x1) << 9;
3123 data32 = READ_VREG(HEVC_MPRED_CTRL4);
3124 data32 &= (~(0xff << 12));
3125 //for (i = LAST_FRAME; i <= ALTREF_FRAME; i++) {
3126 /* HEVC_MPRED_CTRL4[bit 12] is for cm->ref_frame_sign_bias[0]
3127 instead of cm->ref_frame_sign_bias[LAST_FRAME] */
3128 for (i = 0; i <= ALTREF_FRAME; i++) {
3129 data32 |= ((cm->ref_frame_sign_bias[i] & 0x1) << (12 + i));
3130 }
3131 WRITE_VREG(HEVC_MPRED_CTRL4, data32);
3132 av1_print(hw, AOM_DEBUG_HW_MORE,
3133 "WRITE_VREG(HEVC_MPRED_CTRL4, 0x%x)\n", data32);
3134 }
3135#if 1
3136 data32 = (
3137 (cm->seq_params.order_hint_info.enable_order_hint << 27) |
3138 (cm->seq_params.order_hint_info.order_hint_bits_minus_1 << 24) |
3139 (cm->cur_frame->order_hint <<16 ) |
3140 (0x13 << 8) | (0x13 << 0));
3141#else
3142 data32 = READ_VREG(HEVC_MPRED_L0_REF00_POC);
3143 data32 &= (~(0xff << 16));
3144 data32 |= (cm->cur_frame->order_hint & 0xff);
3145 data32 &= (~(1 << 27));
3146 data32 |= (cm->seq_params.order_hint_info.enable_order_hint << 27);
3147#endif
3148 WRITE_VREG(HEVC_MPRED_L0_REF00_POC, data32);
3149 av1_print(hw, AOM_DEBUG_HW_MORE,
3150 "WRITE_VREG(HEVC_MPRED_L0_REF00_POC, 0x%x)\n", data32);
3151
3152 if (inter_flag) {
3153 /* config ref_buf id and order hint */
3154 data32 = 0;
3155 pos = 25;
3156 reg_i = 0;
3157 for (i = ALTREF_FRAME; i >= LAST_FRAME; i--) {
3158 PIC_BUFFER_CONFIG *pic_config =
3159 av1_get_ref_frame_spec_buf(cm, i);
3160 if (pic_config) {
3161 av1_print(hw, AOM_DEBUG_HW_MORE,
3162 "pic_config for %d th ref: index %d, reg[%d] pos %d\n",
3163 i, pic_config->index, reg_i, pos);
3164 data32 |= ((pic_config->index < 0)? 0 : pic_config->index) << pos;
3165 } else
3166 av1_print(hw, AOM_DEBUG_HW_MORE,
3167 "pic_config is null for %d th ref\n", i);
3168 if (pos == 0) {
3169 //WRITE_VREG(ref_buf_reg[reg_i], data32);
3170 ref_buf_val[reg_i] = data32;
3171 av1_print(hw, AOM_DEBUG_HW_MORE,
3172 "ref_buf_reg[%d], WRITE_VREG(0x%x, 0x%x)\n",
3173 reg_i, ref_buf_reg[reg_i], data32);
3174 reg_i++;
3175 data32 = 0;
3176 pos = 24; //for P_HEVC_MPRED_L0_REF04_POC
3177 } else {
3178 if (pos == 24)
3179 pos -= 8; //for P_HEVC_MPRED_L0_REF04_POC
3180 else
3181 pos -= 5; //for P_HEVC_MPRED_L0_REF03_POC
3182 }
3183 }
3184 for (i = ALTREF_FRAME; i >= LAST_FRAME; i--) {
3185 PIC_BUFFER_CONFIG *pic_config =
3186 av1_get_ref_frame_spec_buf(cm, i);
3187 if (pic_config) {
3188 av1_print(hw, AOM_DEBUG_HW_MORE,
3189 "pic_config for %d th ref: order_hint %d, reg[%d] pos %d\n",
3190 i, pic_config->order_hint, reg_i, pos);
3191 data32 |= ((pic_config->index < 0)? 0 : pic_config->order_hint) << pos;
3192 } else
3193 av1_print(hw, AOM_DEBUG_HW_MORE,
3194 "pic_config is null for %d th ref\n", i);
3195 if (pos == 0) {
3196 //WRITE_VREG(ref_buf_reg[reg_i], data32);
3197 ref_buf_val[reg_i] = data32;
3198 av1_print(hw, AOM_DEBUG_HW_MORE,
3199 "ref_buf_reg[%d], WRITE_VREG(0x%x, 0x%x)\n",
3200 reg_i, ref_buf_reg[reg_i], data32);
3201 reg_i++;
3202 data32 = 0;
3203 pos = 24;
3204 } else
3205 pos -= 8;
3206 }
3207 if (pos != 24) {
3208 //WRITE_VREG(ref_buf_reg[reg_i], data32);
3209 ref_buf_val[reg_i] = data32;
3210 av1_print(hw, AOM_DEBUG_HW_MORE,
3211 "ref_buf_reg[%d], WRITE_VREG(0x%x, 0x%x)\n",
3212 reg_i, ref_buf_reg[reg_i], data32);
3213 }
3214 /* config ref_offset */
3215 data32 = 0;
3216 pos = 24;
3217 mv_cal_tpl_count = 0;
3218 reg_i = 0;
3219 for (i = 0; i < cm->mv_ref_id_index; i++) {
3220 if (cm->mv_cal_tpl_mvs[i]) {
3221 mv_ref_id[mv_cal_tpl_count] = cm->mv_ref_id[i];
3222 mv_cal_tpl_count++;
3223 for (j = LAST_FRAME; j <= ALTREF_FRAME; j++) {
3224 /*offset can be negative*/
3225 unsigned char offval =
3226 cm->mv_ref_offset[i][j] & 0xff;
3227 data32 |= (offval << pos);
3228 if (pos == 0) {
3229 //WRITE_VREG(ref_offset_reg[reg_i], data32);
3230 ref_offset_val[reg_i] = data32;
3231 av1_print(hw, AOM_DEBUG_HW_MORE,
3232 "ref_offset_reg[%d], WRITE_VREG(0x%x, 0x%x)\n",
3233 reg_i, ref_offset_reg[reg_i], data32);
3234 reg_i++;
3235 data32 = 0;
3236 pos = 24;
3237 } else
3238 pos -= 8;
3239 }
3240 }
3241 }
3242 if (pos != 24) {
3243 //WRITE_VREG(ref_offset_reg[reg_i], data32);
3244 ref_offset_val[reg_i] = data32;
3245 av1_print(hw, AOM_DEBUG_HW_MORE,
3246 "ref_offset_reg[%d], WRITE_VREG(0x%x, 0x%x)\n",
3247 reg_i, ref_offset_reg[reg_i], data32);
3248 }
3249
3250 data32 = ref_offset_val[5] | //READ_VREG(HEVC_MPRED_L0_REF11_POC) |
3251 mv_cal_tpl_count | (mv_ref_id[0] << 2) |
3252 (mv_ref_id[1] << 5) | (mv_ref_id[2] << 8);
3253 ref_offset_val[5] = data32;
3254 //WRITE_VREG(HEVC_MPRED_L0_REF11_POC, data32);
3255 av1_print(hw, AOM_DEBUG_HW_MORE,
3256 "WRITE_VREG(HEVC_MPRED_L0_REF11_POC 0x%x, 0x%x)\n",
3257 HEVC_MPRED_L0_REF11_POC, data32);
3258 }
3259 for (i = 0; i < 3; i++)
3260 WRITE_VREG(ref_buf_reg[i], ref_buf_val[i]);
3261 for (i = 0; i < 6; i++)
3262 WRITE_VREG(ref_offset_reg[i], ref_offset_val[i]);
3263
3264 WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR,
3265 cur_pic_config->mpred_mv_wr_start_addr);
3266 WRITE_VREG(HEVC_MPRED_MV_WPTR,
3267 cur_pic_config->mpred_mv_wr_start_addr);
3268
3269 if (inter_flag) {
3270 for (i = 0; i < mv_cal_tpl_count; i++) {
3271 PIC_BUFFER_CONFIG *pic_config =
3272 av1_get_ref_frame_spec_buf(cm, mv_ref_id[i]);
3273 if (pic_config == NULL)
3274 continue;
3275 if (i == 0) {
3276 WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR,
3277 pic_config->mpred_mv_wr_start_addr);
3278 WRITE_VREG(HEVC_MPRED_MV_RPTR,
3279 pic_config->mpred_mv_wr_start_addr);
3280 } else if (i == 1) {
3281 WRITE_VREG(HEVC_MPRED_L0_REF01_POC,
3282 pic_config->mpred_mv_wr_start_addr);
3283 WRITE_VREG(HEVC_MPRED_MV_RPTR_1,
3284 pic_config->mpred_mv_wr_start_addr);
3285 } else if (i == 2) {
3286 WRITE_VREG(HEVC_MPRED_L0_REF02_POC,
3287 pic_config->mpred_mv_wr_start_addr);
3288 WRITE_VREG(HEVC_MPRED_MV_RPTR_2,
3289 pic_config->mpred_mv_wr_start_addr);
3290 } else {
3291 av1_print(hw, AOM_DEBUG_HW_MORE,
3292 "%s: mv_ref_id error\n", __func__);
3293 }
3294 }
3295 }
3296 data32 = READ_VREG(HEVC_MPRED_CTRL0);
3297 data32 &= ~((1 << 10) | (1 << 11));
3298 data32 |= (1 << 10); /*write enable*/
3299 av1_print(hw, AOM_DEBUG_HW_MORE,
3300 "current_frame.frame_type=%d, cur_frame->frame_type=%d, allow_ref_frame_mvs=%d\n",
3301 cm->current_frame.frame_type, cm->cur_frame->frame_type,
3302 cm->allow_ref_frame_mvs);
3303
3304 if (av1_frame_is_inter(&hw->pbi->common)) {
3305 if (cm->allow_ref_frame_mvs) {
3306 data32 |= (1 << 11); /*read enable*/
3307 }
3308 }
3309 av1_print(hw, AOM_DEBUG_HW_MORE,
3310 "WRITE_VREG(HEVC_MPRED_CTRL0 0x%x, 0x%x)\n",
3311 HEVC_MPRED_CTRL0, data32);
3312 WRITE_VREG(HEVC_MPRED_CTRL0, data32);
3313 /*
3314 printk("config_mpred: (%x) wr_start_addr %x from indx %d;
3315 (%x) rd_start_addr %x from index %d\n",
3316 cur_pic_config, cur_pic_config->mpred_mv_wr_start_addr, cur_pic_config->index,
3317 last_frame_pic_config, last_frame_pic_config->mpred_mv_wr_start_addr, last_frame_pic_config->index);
3318 data32 = ((pbi->lcu_x_num - pbi->tile_width_lcu)*MV_MEM_UNIT);
3319 WRITE_VREG(HEVC_MPRED_MV_WR_ROW_JUMP,data32);
3320 WRITE_VREG(HEVC_MPRED_MV_RD_ROW_JUMP,data32);
3321
3322 WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR, mpred_mv_rd_end_addr);
3323 */
3324}
3325
3326static void config_sao_hw(struct AV1HW_s *hw, union param_u *params)
3327{
3328 /*
3329 !!!!!!!!!!!!!!!!!!!!!!!!!TODO .... !!!!!!!!!!!
3330 mem_map_mode, endian, get_double_write_mode
3331 */
3332 AV1_COMMON *cm = &hw->pbi->common;
3333 PIC_BUFFER_CONFIG* pic_config = &cm->cur_frame->buf;
3334 uint32_t data32;
3335 int32_t lcu_size =
3336 ((params->p.seq_flags >> 6) & 0x1) ? 128 : 64;
3337 int32_t mc_buffer_size_u_v =
3338 pic_config->lcu_total*lcu_size*lcu_size/2;
3339 int32_t mc_buffer_size_u_v_h =
3340 (mc_buffer_size_u_v + 0xffff)>>16; //64k alignment
3341 av1_print(hw, AOM_DEBUG_HW_MORE,
3342 "[test.c] #### config_sao_hw ####, lcu_size %d\n", lcu_size);
3343 av1_print(hw, AOM_DEBUG_HW_MORE,
3344 "[config_sao_hw] lcu_total : %d\n", pic_config->lcu_total);
3345 av1_print(hw, AOM_DEBUG_HW_MORE,
3346 "[config_sao_hw] mc_y_adr : 0x%x\n", pic_config->mc_y_adr);
3347 av1_print(hw, AOM_DEBUG_HW_MORE,
3348 "[config_sao_hw] mc_u_v_adr : 0x%x\n", pic_config->mc_u_v_adr);
3349 av1_print(hw, AOM_DEBUG_HW_MORE,
3350 "[config_sao_hw] header_adr : 0x%x\n", pic_config->header_adr);
3351#ifdef AOM_AV1_MMU_DW
3352 if (hw->dw_mmu_enable)
3353 av1_print(hw, AOM_DEBUG_HW_MORE,
3354 "[config_sao_hw] header_dw_adr : 0x%x\n", pic_config->header_dw_adr);
3355#endif
3356 data32 = READ_VREG(HEVC_SAO_CTRL9) | (1 << 1);
3357 WRITE_VREG(HEVC_SAO_CTRL9, data32);
3358
3359 data32 = READ_VREG(HEVC_SAO_CTRL5);
3360 data32 |= (0x1 << 14); /* av1 mode */
3361 data32 |= (0xff << 16); /* dw {v1,v0,h1,h0} ctrl_y_cbus */
3362 WRITE_VREG(HEVC_SAO_CTRL5, data32);
3363
3364 WRITE_VREG(HEVC_SAO_CTRL0,
3365 lcu_size == 128 ? 0x7 : 0x6); /*lcu_size_log2*/
3366#ifdef LOSLESS_COMPRESS_MODE
3367 WRITE_VREG(HEVC_CM_BODY_START_ADDR, pic_config->mc_y_adr);
3368#ifdef AOM_AV1_MMU
3369 WRITE_VREG(HEVC_CM_HEADER_START_ADDR, pic_config->header_adr);
3370#endif
3371#ifdef AOM_AV1_MMU_DW
3372 if (hw->dw_mmu_enable)
3373 WRITE_VREG(HEVC_CM_HEADER_START_ADDR2, pic_config->header_dw_adr);
3374#endif
3375#else
3376/*!LOSLESS_COMPRESS_MODE*/
3377 WRITE_VREG(HEVC_SAO_Y_START_ADDR, pic_config->mc_y_adr);
3378#endif
3379
3380 av1_print(hw, AOM_DEBUG_HW_MORE,
3381 "[config_sao_hw] sao_body_addr:%x\n", pic_config->mc_y_adr);
3382 //printk("[config_sao_hw] sao_header_addr:%x\n", pic_config->mc_y_adr + losless_comp_body_size );
3383
3384#ifdef VPU_FILMGRAIN_DUMP
3385 // Let Microcode to increase
3386 // WRITE_VREG(HEVC_FGS_TABLE_START, pic_config->fgs_table_adr);
3387#else
3388 WRITE_VREG(HEVC_FGS_TABLE_START, pic_config->fgs_table_adr);
3389#endif
3390 WRITE_VREG(HEVC_FGS_TABLE_LENGTH, FGS_TABLE_SIZE * 8);
3391 av1_print(hw, AOM_DEBUG_HW_MORE,
3392 "[config_sao_hw] fgs_table adr:0x%x , length 0x%x bits\n",
3393 pic_config->fgs_table_adr, FGS_TABLE_SIZE * 8);
3394
3395 data32 = (mc_buffer_size_u_v_h<<16)<<1;
3396 //printk("data32 = %x, mc_buffer_size_u_v_h = %x, lcu_total = %x\n", data32, mc_buffer_size_u_v_h, pic_config->lcu_total);
3397 WRITE_VREG(HEVC_SAO_Y_LENGTH ,data32);
3398
3399#ifndef LOSLESS_COMPRESS_MODE
3400 WRITE_VREG(HEVC_SAO_C_START_ADDR, pic_config->mc_u_v_adr);
3401#else
3402#endif
3403
3404 data32 = (mc_buffer_size_u_v_h<<16);
3405 WRITE_VREG(HEVC_SAO_C_LENGTH ,data32);
3406
3407#ifndef LOSLESS_COMPRESS_MODE
3408 /* multi tile to do... */
3409 WRITE_VREG(HEVC_SAO_Y_WPTR, pic_config->mc_y_adr);
3410
3411 WRITE_VREG(HEVC_SAO_C_WPTR, pic_config->mc_u_v_adr);
3412#else
3413 if (get_double_write_mode(hw) &&
3414 (get_double_write_mode(hw) & 0x20) == 0) {
3415 WRITE_VREG(HEVC_SAO_Y_START_ADDR, pic_config->dw_y_adr);
3416 WRITE_VREG(HEVC_SAO_C_START_ADDR, pic_config->dw_u_v_adr);
3417 WRITE_VREG(HEVC_SAO_Y_WPTR, pic_config->dw_y_adr);
3418 WRITE_VREG(HEVC_SAO_C_WPTR, pic_config->dw_u_v_adr);
3419 } else {
3420 //WRITE_VREG(HEVC_SAO_Y_START_ADDR, 0xffffffff);
3421 //WRITE_VREG(HEVC_SAO_C_START_ADDR, 0xffffffff);
3422 }
3423#endif
3424
3425
3426#ifndef AOM_AV1_NV21
3427#ifdef AOM_AV1_MMU_DW
3428 if (hw->dw_mmu_enable) {
3429 }
3430#endif
3431#endif
3432
3433#ifdef AOM_AV1_NV21
3434#ifdef DOS_PROJECT
3435 data32 = READ_VREG(HEVC_SAO_CTRL1);
3436 data32 &= (~0x3000);
3437 data32 |= (MEM_MAP_MODE << 12); // [13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32
3438 data32 &= (~0x3);
3439 data32 |= 0x1; // [1]:dw_disable [0]:cm_disable
3440 WRITE_VREG(HEVC_SAO_CTRL1, data32);
3441
3442 data32 = READ_VREG(HEVC_SAO_CTRL5); // [23:22] dw_v1_ctrl [21:20] dw_v0_ctrl [19:18] dw_h1_ctrl [17:16] dw_h0_ctrl
3443 data32 &= ~(0xff << 16); // set them all 0 for AOM_AV1_NV21 (no down-scale)
3444 WRITE_VREG(HEVC_SAO_CTRL5, data32);
3445
3446 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
3447 data32 &= (~0x30);
3448 data32 |= (MEM_MAP_MODE << 4); // [5:4] -- address_format 00:linear 01:32x32 10:64x32
3449 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
3450#else
3451// m8baby test1902
3452 data32 = READ_VREG(HEVC_SAO_CTRL1);
3453 data32 &= (~0x3000);
3454 data32 |= (MEM_MAP_MODE << 12); // [13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32
3455 data32 &= (~0xff0);
3456 //data32 |= 0x670; // Big-Endian per 64-bit
3457 data32 |= 0x880; // Big-Endian per 64-bit
3458 data32 &= (~0x3);
3459 data32 |= 0x1; // [1]:dw_disable [0]:cm_disable
3460 WRITE_VREG(HEVC_SAO_CTRL1, data32);
3461
3462 data32 = READ_VREG(HEVC_SAO_CTRL5); // [23:22] dw_v1_ctrl [21:20] dw_v0_ctrl [19:18] dw_h1_ctrl [17:16] dw_h0_ctrl
3463 data32 &= ~(0xff << 16); // set them all 0 for AOM_AV1_NV21 (no down-scale)
3464 WRITE_VREG(HEVC_SAO_CTRL5, data32);
3465
3466 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
3467 data32 &= (~0x30);
3468 data32 |= (MEM_MAP_MODE << 4); // [5:4] -- address_format 00:linear 01:32x32 10:64x32
3469 data32 &= (~0xF);
3470 data32 |= 0x8; // Big-Endian per 64-bit
3471 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
3472#endif
3473#else
3474/*CHANGE_DONE nnn*/
3475 data32 = READ_VREG(HEVC_SAO_CTRL1);
3476 data32 &= (~0x3000);
3477 data32 |= (mem_map_mode <<
3478 12);
3479
3480/* [13:12] axi_aformat, 0-Linear,
3481 * 1-32x32, 2-64x32
3482 */
3483 data32 &= (~0xff0);
3484 /* data32 |= 0x670; // Big-Endian per 64-bit */
3485#ifdef AOM_AV1_MMU_DW
3486 if (hw->dw_mmu_enable == 0)
3487 data32 |= endian; /* Big-Endian per 64-bit */
3488#else
3489 data32 |= endian; /* Big-Endian per 64-bit */
3490#endif
3491 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
3492 data32 &= (~0x3); /*[1]:dw_disable [0]:cm_disable*/
3493 if (get_double_write_mode(hw) == 0)
3494 data32 |= 0x2; /*disable double write*/
3495 else if (get_double_write_mode(hw) & 0x10)
3496 data32 |= 0x1; /*disable cm*/
3497 } else { /* >= G12A dw write control */
3498 unsigned int data;
3499 data = READ_VREG(HEVC_DBLK_CFGB);
3500 data &= (~0x300); /*[8]:first write enable (compress) [9]:double write enable (uncompress)*/
3501 if (get_double_write_mode(hw) == 0)
3502 data |= (0x1 << 8); /*enable first write*/
3503 else if (get_double_write_mode(hw) & 0x10)
3504 data |= (0x1 << 9); /*double write only*/
3505 else
3506 data |= ((0x1 << 8) |(0x1 << 9));
3507 WRITE_VREG(HEVC_DBLK_CFGB, data);
3508 }
3509 WRITE_VREG(HEVC_SAO_CTRL1, data32);
3510
3511 if (get_double_write_mode(hw) & 0x10) {
3512 /* [23:22] dw_v1_ctrl
3513 *[21:20] dw_v0_ctrl
3514 *[19:18] dw_h1_ctrl
3515 *[17:16] dw_h0_ctrl
3516 */
3517 data32 = READ_VREG(HEVC_SAO_CTRL5);
3518 /*set them all 0 for H265_NV21 (no down-scale)*/
3519 data32 &= ~(0xff << 16);
3520 WRITE_VREG(HEVC_SAO_CTRL5, data32);
3521 } else {
3522 data32 = READ_VREG(HEVC_SAO_CTRL5);
3523 data32 &= (~(0xff << 16));
3524 if ((get_double_write_mode(hw) & 0xf) == 2 ||
3525 (get_double_write_mode(hw) & 0xf) == 3)
3526 data32 |= (0xff<<16);
3527 else if ((get_double_write_mode(hw) & 0xf) == 4 ||
3528 (get_double_write_mode(hw) & 0xf) == 5)
3529 data32 |= (0x33<<16);
3530 WRITE_VREG(HEVC_SAO_CTRL5, data32);
3531 }
3532
3533 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
3534 data32 &= (~0x30);
3535 /* [5:4] -- address_format 00:linear 01:32x32 10:64x32 */
3536 data32 |= (mem_map_mode <<
3537 4);
3538 data32 &= (~0xF);
3539 data32 |= 0xf; /* valid only when double write only */
3540 /*data32 |= 0x8;*/ /* Big-Endian per 64-bit */
3541 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
3542
3543#endif
3544
3545}
3546
3547
3548#ifdef AOM_AV1_DBLK_INIT
3549/*
3550 * Defines, declarations, sub-functions for av1 de-block loop filter Thr/Lvl table update
3551 * - struct segmentation_lf is for loop filter only (removed something)
3552 * - function "av1_loop_filter_init" and "av1_loop_filter_frame_init" will be instantiated in C_Entry
3553 * - av1_loop_filter_init run once before decoding start
3554 * - av1_loop_filter_frame_init run before every frame decoding start
3555 * - set video format to AOM_AV1 is in av1_loop_filter_init
3556 */
3557#define MAX_LOOP_FILTER 63
3558#define MAX_MODE_LF_DELTAS 2
3559#define MAX_SEGMENTS 8
3560#define MAX_MB_PLANE 3
3561
3562typedef enum {
3563 SEG_LVL_ALT_Q, // Use alternate Quantizer ....
3564 SEG_LVL_ALT_LF_Y_V, // Use alternate loop filter value on y plane vertical
3565 SEG_LVL_ALT_LF_Y_H, // Use alternate loop filter value on y plane horizontal
3566 SEG_LVL_ALT_LF_U, // Use alternate loop filter value on u plane
3567 SEG_LVL_ALT_LF_V, // Use alternate loop filter value on v plane
3568 SEG_LVL_REF_FRAME, // Optional Segment reference frame
3569 SEG_LVL_SKIP, // Optional Segment (0,0) + skip mode
3570 SEG_LVL_GLOBALMV,
3571 SEG_LVL_MAX
3572} SEG_LVL_FEATURES;
3573
3574static const SEG_LVL_FEATURES seg_lvl_lf_lut[MAX_MB_PLANE][2] = {
3575 { SEG_LVL_ALT_LF_Y_V, SEG_LVL_ALT_LF_Y_H },
3576 { SEG_LVL_ALT_LF_U, SEG_LVL_ALT_LF_U },
3577 { SEG_LVL_ALT_LF_V, SEG_LVL_ALT_LF_V }
3578};
3579
3580struct segmentation_lf { // for loopfilter only
3581 uint8_t enabled;
3582 /*
3583 SEG_LVL_ALT_LF_Y_V feature_enable: seg_lf_info_y[bit7]
3584 SEG_LVL_ALT_LF_Y_V data: seg_lf_info_y[bit0~6]
3585 SEG_LVL_ALT_LF_Y_H feature enable: seg_lf_info_y[bit15]
3586 SEG_LVL_ALT_LF_Y_H data: seg_lf_info_y[bit8~14]
3587 */
3588 uint16_t seg_lf_info_y[8];
3589 /*
3590 SEG_LVL_ALT_LF_U feature_enable: seg_lf_info_c[bit7]
3591 SEG_LVL_ALT_LF_U data: seg_lf_info_c[bit0~6]
3592 SEG_LVL_ALT_LF_V feature enable: seg_lf_info_c[bit15]
3593 SEG_LVL_ALT_LF_V data: seg_lf_info_c[bit8~14]
3594 */
3595 uint16_t seg_lf_info_c[8];
3596};
3597
3598typedef struct {
3599 uint8_t mblim;
3600 uint8_t lim;
3601 uint8_t hev_thr;
3602} loop_filter_thresh;
3603
3604typedef struct loop_filter_info_n_s {
3605 loop_filter_thresh lfthr[MAX_LOOP_FILTER + 1];
3606 uint8_t lvl[MAX_MB_PLANE][MAX_SEGMENTS][2][REF_FRAMES][MAX_MODE_LF_DELTAS];
3607} loop_filter_info_n;
3608
3609struct loopfilter {
3610 int32_t filter_level[2];
3611 int32_t filter_level_u;
3612 int32_t filter_level_v;
3613
3614 int32_t sharpness_level;
3615
3616 uint8_t mode_ref_delta_enabled;
3617 uint8_t mode_ref_delta_update;
3618
3619 // 0 = Intra, Last, Last2+Last3,
3620 // GF, BRF, ARF2, ARF
3621 int8_t ref_deltas[REF_FRAMES];
3622
3623 // 0 = ZERO_MV, MV
3624 int8_t mode_deltas[MAX_MODE_LF_DELTAS];
3625
3626 int32_t combine_vert_horz_lf;
3627
3628 int32_t lf_pic_cnt;
3629
3630//#if LOOP_FILTER_BITMASK
3631 //LoopFilterMask *lfm;
3632 //size_t lfm_num;
3633 //int lfm_stride;
3634 //LpfSuperblockInfo neighbor_sb_lpf_info;
3635//#endif // LOOP_FILTER_BITMASK
3636};
3637
3638static int32_t myclamp(int32_t value, int32_t low, int32_t high) {
3639 return value < low ? low : (value > high ? high : value);
3640}
3641
3642/*static int8_t extend_sign_7bits(uint8_t value) {
3643 return (((value>>6) & 0x1)<<7) | (value&0x7f);
3644}*/
3645
3646// convert data to int8_t variable
3647// value : signed data (with any bitwidth<8) which is assigned to uint8_t variable as an input
3648// bw : bitwidth of signed data, (from 1 to 7)
3649static int8_t conv2int8 (uint8_t value, uint8_t bw) {
3650 if (bw<1 || bw>7) return (int8_t)value;
3651 else {
3652 const uint8_t data_bits = value & ((1<<bw)-1);
3653 const uint8_t sign_bit = (value>>(bw-1)) & 0x1;
3654 const uint8_t sign_bit_ext = sign_bit | sign_bit<<1 | sign_bit<<2 | sign_bit<<3 | sign_bit<<4 | sign_bit<<5 | sign_bit<<6 | sign_bit<<7;
3655 return (int8_t)((sign_bit_ext<<bw) | data_bits);
3656 }
3657}
3658
3659static void av1_update_sharpness(loop_filter_info_n *lfi, int32_t sharpness_lvl) {
3660 int32_t lvl;
3661
3662 // For each possible value for the loop filter fill out limits
3663 for (lvl = 0; lvl <= MAX_LOOP_FILTER; lvl++) {
3664 // Set loop filter parameters that control sharpness.
3665 int32_t block_inside_limit =
3666 lvl >> ((sharpness_lvl > 0) + (sharpness_lvl > 4));
3667
3668 if (sharpness_lvl > 0) {
3669 if (block_inside_limit > (9 - sharpness_lvl))
3670 block_inside_limit = (9 - sharpness_lvl);
3671 }
3672
3673 if (block_inside_limit < 1)
3674 block_inside_limit = 1;
3675
3676 lfi->lfthr[lvl].lim = (uint8_t)block_inside_limit;
3677 lfi->lfthr[lvl].mblim = (uint8_t)(2 * (lvl + 2) + block_inside_limit);
3678 }
3679}
3680
3681// instantiate this function once when decode is started
3682void av1_loop_filter_init(loop_filter_info_n *lfi, struct loopfilter *lf) {
3683 int32_t i;
3684 uint32_t data32;
3685
3686 // init limits for given sharpness
3687 av1_update_sharpness(lfi, lf->sharpness_level);
3688
3689 // Write to register
3690 for (i = 0; i < 32; i++) {
3691 uint32_t thr;
3692 thr = ((lfi->lfthr[i*2+1].lim & 0x3f)<<8) |
3693 (lfi->lfthr[i*2+1].mblim & 0xff);
3694 thr = (thr<<16) | ((lfi->lfthr[i*2].lim & 0x3f)<<8) |
3695 (lfi->lfthr[i*2].mblim & 0xff);
3696 WRITE_VREG(HEVC_DBLK_CFG9, thr);
3697 }
3698 // video format is AOM_AV1
3699 data32 = (0x57 << 8) | // 1st/2nd write both enable
3700 (0x4 << 0); // aom_av1 video format
3701 WRITE_VREG(HEVC_DBLK_CFGB, data32);
3702 av1_print2(AOM_DEBUG_HW_MORE,
3703 "[DBLK DEBUG] CFGB : 0x%x\n", data32);
3704}
3705
3706// perform this function per frame
3707void av1_loop_filter_frame_init(AV1Decoder* pbi, struct segmentation_lf *seg,
3708 loop_filter_info_n *lfi,
3709 struct loopfilter *lf,
3710 int32_t pic_width) {
3711 BuffInfo_t* buf_spec = pbi->work_space_buf;
3712 int32_t i,dir;
3713 int32_t filt_lvl[MAX_MB_PLANE], filt_lvl_r[MAX_MB_PLANE];
3714 int32_t plane;
3715 int32_t seg_id;
3716 // n_shift is the multiplier for lf_deltas
3717 // the multiplier is 1 for when filter_lvl is between 0 and 31;
3718 // 2 when filter_lvl is between 32 and 63
3719
3720 // update limits if sharpness has changed
3721 av1_update_sharpness(lfi, lf->sharpness_level);
3722
3723 // Write to register
3724 for (i = 0; i < 32; i++) {
3725 uint32_t thr;
3726 thr = ((lfi->lfthr[i*2+1].lim & 0x3f)<<8)
3727 | (lfi->lfthr[i*2+1].mblim & 0xff);
3728 thr = (thr<<16) | ((lfi->lfthr[i*2].lim & 0x3f)<<8)
3729 | (lfi->lfthr[i*2].mblim & 0xff);
3730 WRITE_VREG(HEVC_DBLK_CFG9, thr);
3731 }
3732
3733 filt_lvl[0] = lf->filter_level[0];
3734 filt_lvl[1] = lf->filter_level_u;
3735 filt_lvl[2] = lf->filter_level_v;
3736
3737 filt_lvl_r[0] = lf->filter_level[1];
3738 filt_lvl_r[1] = lf->filter_level_u;
3739 filt_lvl_r[2] = lf->filter_level_v;
3740
3741#ifdef DBG_LPF_PRINT
3742 printk("LF_PRINT: pic_cnt(%d) base_filter_level(%d,%d,%d,%d)\n",
3743 lf->lf_pic_cnt, lf->filter_level[0],
3744 lf->filter_level[1], lf->filter_level_u, lf->filter_level_v);
3745#endif
3746
3747 for (plane = 0; plane < 3; plane++) {
3748 if (plane == 0 && !filt_lvl[0] && !filt_lvl_r[0])
3749 break;
3750 else if (plane == 1 && !filt_lvl[1])
3751 continue;
3752 else if (plane == 2 && !filt_lvl[2])
3753 continue;
3754
3755 for (seg_id = 0; seg_id < MAX_SEGMENTS; seg_id++) { // MAX_SEGMENTS==8
3756 for (dir = 0; dir < 2; ++dir) {
3757 int32_t lvl_seg = (dir == 0) ? filt_lvl[plane] : filt_lvl_r[plane];
3758 //assert(plane >= 0 && plane <= 2);
3759 const uint8_t seg_lf_info_y0 = seg->seg_lf_info_y[seg_id] & 0xff;
3760 const uint8_t seg_lf_info_y1 = (seg->seg_lf_info_y[seg_id]>>8) & 0xff;
3761 const uint8_t seg_lf_info_u = seg->seg_lf_info_c[seg_id] & 0xff;
3762 const uint8_t seg_lf_info_v = (seg->seg_lf_info_c[seg_id]>>8) & 0xff;
3763 const uint8_t seg_lf_info = (plane==2) ? seg_lf_info_v : (plane==1) ?
3764 seg_lf_info_u : ((dir==0) ? seg_lf_info_y0 : seg_lf_info_y1);
3765 const int8_t seg_lf_active = ((seg->enabled) && ((seg_lf_info>>7) & 0x1));
3766 const int8_t seg_lf_data = conv2int8(seg_lf_info,7);
3767#ifdef DBG_LPF_PRINT
3768 const int8_t seg_lf_data_clip = (seg_lf_data>63) ? 63 :
3769 (seg_lf_data<-63) ? -63 : seg_lf_data;
3770#endif
3771 if (seg_lf_active) {
3772 lvl_seg = myclamp(lvl_seg + (int32_t)seg_lf_data, 0, MAX_LOOP_FILTER);
3773 }
3774
3775#ifdef DBG_LPF_PRINT
3776 printk("LF_PRINT:plane(%d) seg_id(%d) dir(%d) seg_lf_info(%d,0x%x),lvl_seg(0x%x)\n",
3777 plane,seg_id,dir,seg_lf_active,seg_lf_data_clip,lvl_seg);
3778#endif
3779
3780 if (!lf->mode_ref_delta_enabled) {
3781 // we could get rid of this if we assume that deltas are set to
3782 // zero when not in use; encoder always uses deltas
3783 memset(lfi->lvl[plane][seg_id][dir], lvl_seg,
3784 sizeof(lfi->lvl[plane][seg_id][dir]));
3785 } else {
3786 int32_t ref, mode;
3787 const int32_t scale = 1 << (lvl_seg >> 5);
3788 const int32_t intra_lvl = lvl_seg + lf->ref_deltas[INTRA_FRAME] * scale;
3789 lfi->lvl[plane][seg_id][dir][INTRA_FRAME][0] =
3790 myclamp(intra_lvl, 0, MAX_LOOP_FILTER);
3791#ifdef DBG_LPF_PRINT
3792 printk("LF_PRINT:ref_deltas[INTRA_FRAME](%d)\n",lf->ref_deltas[INTRA_FRAME]);
3793#endif
3794 for (ref = LAST_FRAME; ref < REF_FRAMES; ++ref) { // LAST_FRAME==1 REF_FRAMES==8
3795 for (mode = 0; mode < MAX_MODE_LF_DELTAS; ++mode) { // MAX_MODE_LF_DELTAS==2
3796 const int32_t inter_lvl =
3797 lvl_seg + lf->ref_deltas[ref] * scale +
3798 lf->mode_deltas[mode] * scale;
3799 lfi->lvl[plane][seg_id][dir][ref][mode] =
3800 myclamp(inter_lvl, 0, MAX_LOOP_FILTER);
3801#ifdef DBG_LPF_PRINT
3802 printk("LF_PRINT:ref_deltas(%d) mode_deltas(%d)\n",
3803 lf->ref_deltas[ref], lf->mode_deltas[mode]);
3804#endif
3805 }
3806 }
3807 }
3808 }
3809 }
3810 }
3811
3812#ifdef DBG_LPF_PRINT
3813 for (i = 0; i <= MAX_LOOP_FILTER; i++) {
3814 printk("LF_PRINT:(%2d) thr=%d,blim=%3d,lim=%2d\n",
3815 i, lfi->lfthr[i].hev_thr,
3816 lfi->lfthr[i].mblim, lfi->lfthr[i].lim);
3817 }
3818 for (plane = 0; plane < 3; plane++) {
3819 for (seg_id = 0; seg_id < MAX_SEGMENTS; seg_id++) { // MAX_SEGMENTS==8
3820 for (dir = 0; dir < 2; ++dir) {
3821 int32_t mode;
3822 for (mode = 0; mode < 2; ++mode) {
3823 printk("assign {lvl[%d][%d][%d][0][%d],lvl[%d][%d][%d][1][%d],lvl[%d][%d][%d][2][%d],lvl[%d][%d][%d][3][%d],lvl[%d][%d][%d][4][%d],lvl[%d][%d][%d][5][%d],lvl[%d][%d][%d][6][%d],lvl[%d][%d][%d][7][%d]}={6'd%2d,6'd%2d,6'd%2d,6'd%2d,6'd%2d,6'd%2d,6'd%2d,6'd%2d};\n",
3824 plane, seg_id, dir, mode,
3825 plane, seg_id, dir, mode,
3826 plane, seg_id, dir, mode,
3827 plane, seg_id, dir, mode,
3828 plane, seg_id, dir, mode,
3829 plane, seg_id, dir, mode,
3830 plane, seg_id, dir, mode,
3831 plane, seg_id, dir, mode,
3832 lfi->lvl[plane][seg_id][dir][0][mode],
3833 lfi->lvl[plane][seg_id][dir][1][mode],
3834 lfi->lvl[plane][seg_id][dir][2][mode],
3835 lfi->lvl[plane][seg_id][dir][3][mode],
3836 lfi->lvl[plane][seg_id][dir][4][mode],
3837 lfi->lvl[plane][seg_id][dir][5][mode],
3838 lfi->lvl[plane][seg_id][dir][6][mode],
3839 lfi->lvl[plane][seg_id][dir][7][mode]);
3840 }
3841 }
3842 }
3843 }
3844#endif
3845 // Write to register
3846 for (i = 0; i < 192; i++) {
3847 uint32_t level;
3848 level = ((lfi->lvl[i>>6&3][i>>3&7][1][i&7][1] & 0x3f)<<24) |
3849 ((lfi->lvl[i>>6&3][i>>3&7][1][i&7][0] & 0x3f)<<16) |
3850 ((lfi->lvl[i>>6&3][i>>3&7][0][i&7][1] & 0x3f)<<8) |
3851 (lfi->lvl[i>>6&3][i>>3&7][0][i&7][0] & 0x3f);
3852 if (!lf->filter_level[0] && !lf->filter_level[1])
3853 level = 0;
3854 WRITE_VREG(HEVC_DBLK_CFGA, level);
3855 }
3856#ifdef DBG_LPF_DBLK_FORCED_OFF
3857 if (lf->lf_pic_cnt == 2) {
3858 printk("LF_PRINT: pic_cnt(%d) dblk forced off !!!\n", lf->lf_pic_cnt);
3859 WRITE_VREG(HEVC_DBLK_DBLK0, 0);
3860 } else
3861 WRITE_VREG(HEVC_DBLK_DBLK0,
3862 lf->filter_level[0] | lf->filter_level[1] << 6 |
3863 lf->filter_level_u << 12 | lf->filter_level_v << 18);
3864#else
3865 WRITE_VREG(HEVC_DBLK_DBLK0,
3866 lf->filter_level[0] | lf->filter_level[1]<<6 |
3867 lf->filter_level_u<<12 | lf->filter_level_v<<18);
3868#endif
3869 for (i =0; i < 10; i++)
3870 WRITE_VREG(HEVC_DBLK_DBLK1,
3871 ((i<2) ? lf->mode_deltas[i&1] : lf->ref_deltas[(i-2)&7]));
3872 for (i = 0; i < 8; i++)
3873 WRITE_VREG(HEVC_DBLK_DBLK2,
3874 (uint32_t)(seg->seg_lf_info_y[i]) | (uint32_t)(seg->seg_lf_info_c[i]<<16));
3875
3876 // Set P_HEVC_DBLK_CFGB again
3877 {
3878 uint32_t lpf_data32 = READ_VREG(HEVC_DBLK_CFGB);
3879 if (lf->mode_ref_delta_enabled)
3880 lpf_data32 |= (0x1<<28); // mode_ref_delta_enabled
3881 else
3882 lpf_data32 &= ~(0x1<<28);
3883 if (seg->enabled)
3884 lpf_data32 |= (0x1<<29); // seg enable
3885 else
3886 lpf_data32 &= ~(0x1<<29);
3887 if (pic_width >= 1280)
3888 lpf_data32 |= (0x1 << 4); // dblk pipeline mode=1 for performance
3889 else
3890 lpf_data32 &= ~(0x3 << 4);
3891 WRITE_VREG(HEVC_DBLK_CFGB, lpf_data32);
3892 }
3893 // Set CDEF
3894 WRITE_VREG(HEVC_DBLK_CDEF0, buf_spec->cdef_data.buf_start);
3895 {
3896 uint32_t cdef_data32 = (READ_VREG(HEVC_DBLK_CDEF1) & 0xffffff00);
3897 cdef_data32 |= 17; // TODO ERROR :: cdef temp dma address left offset
3898 WRITE_VREG(HEVC_DBLK_CDEF1, cdef_data32);
3899 }
3900 // Picture count
3901 lf->lf_pic_cnt++;
3902}
3903#endif // #ifdef AOM_AV1_DBLK_INIT
3904
3905#ifdef AOM_AV1_UPSCALE_INIT
3906/*
3907 * these functions here for upscaling updated in every picture
3908 */
3909#define RS_SUBPEL_BITS 6
3910#define RS_SUBPEL_MASK ((1 << RS_SUBPEL_BITS) - 1)
3911#define RS_SCALE_SUBPEL_BITS 14
3912#define RS_SCALE_SUBPEL_MASK ((1 << RS_SCALE_SUBPEL_BITS) - 1)
3913#define RS_SCALE_EXTRA_BITS (RS_SCALE_SUBPEL_BITS - RS_SUBPEL_BITS)
3914#define RS_SCALE_EXTRA_OFF (1 << (RS_SCALE_EXTRA_BITS - 1))
3915
3916static int32_t av1_get_upscale_convolve_step(int32_t in_length, int32_t out_length) {
3917 return ((in_length << RS_SCALE_SUBPEL_BITS) + out_length / 2) / out_length;
3918}
3919
3920static int32_t get_upscale_convolve_x0(int32_t in_length, int32_t out_length,
3921 int32_t x_step_qn) {
3922 const int32_t err = out_length * x_step_qn - (in_length << RS_SCALE_SUBPEL_BITS);
3923 const int32_t x0 =
3924 (-((out_length - in_length) << (RS_SCALE_SUBPEL_BITS - 1)) +
3925 out_length / 2) /
3926 out_length +
3927 RS_SCALE_EXTRA_OFF - err / 2;
3928 return (int32_t)((uint32_t)x0 & RS_SCALE_SUBPEL_MASK);
3929}
3930
3931void av1_upscale_frame_init(AV1Decoder* pbi, AV1_COMMON *cm, param_t* params)
3932{
3933 BuffInfo_t* buf_spec = pbi->work_space_buf;
3934 //uint32_t data32;
3935 const int32_t width = cm->dec_width;
3936 const int32_t superres_upscaled_width = cm->superres_upscaled_width;
3937 const int32_t x_step_qn_luma = av1_get_upscale_convolve_step(width, superres_upscaled_width);
3938 const int32_t x0_qn_luma = get_upscale_convolve_x0(width, superres_upscaled_width, x_step_qn_luma);
3939 const int32_t x_step_qn_chroma = av1_get_upscale_convolve_step((width+1)>>1, (superres_upscaled_width+1)>>1);
3940 const int32_t x0_qn_chroma = get_upscale_convolve_x0((width+1)>>1, (superres_upscaled_width+1)>>1, x_step_qn_chroma);
3941 av1_print2(AOM_DEBUG_HW_MORE,
3942 "UPS_PRINT: width(%d -> %d)\n",
3943 width, superres_upscaled_width);
3944 av1_print2(AOM_DEBUG_HW_MORE,
3945 "UPS_PRINT: xstep(%d,%d)(0x%X, 0x%X) x0qn(%d,%d)(0x%X, 0x%X)\n",
3946 x_step_qn_luma,x_step_qn_chroma,
3947 x_step_qn_luma,x_step_qn_chroma,
3948 x0_qn_luma,x0_qn_chroma,
3949 x0_qn_luma,x0_qn_chroma);
3950 WRITE_VREG(HEVC_DBLK_UPS1, buf_spec->ups_data.buf_start);
3951 WRITE_VREG(HEVC_DBLK_UPS2, x0_qn_luma); // x0_qn y
3952 WRITE_VREG(HEVC_DBLK_UPS3, x0_qn_chroma); // x0_qn c
3953 WRITE_VREG(HEVC_DBLK_UPS4, x_step_qn_luma); // x_step y
3954 WRITE_VREG(HEVC_DBLK_UPS5, x_step_qn_chroma); // x_step c
3955 WRITE_VREG(AV1_UPSCALE_X0_QN, (x0_qn_chroma<<16)|x0_qn_luma);
3956 WRITE_VREG(AV1_UPSCALE_STEP_QN, (x_step_qn_chroma<<16)|x_step_qn_luma);
3957
3958/*
3959 * TileR calculation here if cm needs an exactly accurate value
3960 */
3961//#define AV1_UPSCALE_TILER_CALCULATION
3962#ifdef AV1_UPSCALE_TILER_CALCULATION
3963 uint32_t upscl_enabled = 1; // 1 just for example, actually this is use_superres flag
3964 uint32_t tiler_x = 192; // 192 just for example, actually this is tile end
3965 uint32_t ux;
3966 uint32_t ux_tiler,ux_tiler_rnd32;
3967 uint32_t xqn_y;
3968 uint32_t xqn_c;
3969 uint32_t tiler_x_y = tiler_x - 8 - 3; // dblk/cdef left-shift-8 plus upscaling extra-3
3970 uint32_t tiler_x_c = (tiler_x/2) - 4 - 3; // dblk/cdef left-shift-4 plus upscaling extra-3
3971
3972 xqn_y = x0_qn_luma;
3973 xqn_c = x0_qn_chroma;
3974 ux_tiler = 0;
3975 ux_tiler_rnd32 = 0;
3976 for (ux=0; ux<16384; ux+=8) {
3977 uint32_t x1qn_y = xqn_y + x_step_qn_luma *( 7+3); // extra-3 is for lrf
3978 uint32_t x1qn_c = xqn_c + x_step_qn_chroma*( 3+3); // extra-3 is for lrf
3979 uint32_t x1qn_y_nxt = xqn_y + x_step_qn_luma *(8+7+3); // extra-3 is for lrf
3980 uint32_t x1qn_c_nxt = xqn_c + x_step_qn_chroma*(4+3+3); // extra-3 is for lrf
3981
3982 uint32_t x1_y = upscl_enabled ? (x1qn_y>>14) : ux +7+3;
3983 uint32_t x1_c = upscl_enabled ? (x1qn_c>>14) : (ux/2)+3+3;
3984 uint32_t x1_y_nxt = upscl_enabled ? (x1qn_y_nxt>>14) : ux +8+7+3;
3985 uint32_t x1_c_nxt = upscl_enabled ? (x1qn_c_nxt>>14) : (ux/2)+4+3+3;
3986
3987 if ((x1_y<tiler_x_y && x1_c<tiler_x_c) &&
3988 (x1_y_nxt>=tiler_x_y || x1_c_nxt>=tiler_x_c)) {
3989 ux_tiler = ux;
3990 ux_tiler_rnd32 = (ux_tiler/32 + (ux_tiler%32 ? 1 : 0)) * 32;
3991 break;
3992 }
3993
3994 xqn_y += x_step_qn_luma*8;
3995 xqn_c += x_step_qn_chroma*4;
3996 }
3997
3998 av1_print(hw, AOM_DEBUG_HW_MORE,
3999 "UPS_PRINT: xqn_y(0x%x), xqn_c(0x%x), x1qn_y(0x%x), x1qn_c(0x%x)\n",
4000 xqn_y, xqn_c, x1qn_y, x1qn_c);
4001 av1_print(hw, AOM_DEBUG_HW_MORE,
4002 "UPS_PRINT: ux_tiler(%d)(0x%x), ux_tiler_rnd32(%d)(0x%x)\n",
4003 ux_tiler, ux_tiler, ux_tiler_rnd32, ux_tiler_rnd32);
4004#endif
4005
4006 // TEMP write lrf register here
4007 //WRITE_VREG(HEVC_DBLK_LRF0, 1<<0 | 1<<2); // LRF UNIT SIZE
4008 //WRITE_VREG(HEVC_DBLK_LRF1, 3<<0 | 1<<8 | 1<<16 | 1<<24); // LRF UNIT NUMBER
4009
4010 // TEMP Global Enables write here
4011 /*
4012 const uint32_t dblk_enable = (!cm->allow_intrabc && !cm->single_tile_decoding && (cm->lf.filter_level[0] || cm->lf.filter_level[1]));
4013 const uint32_t cdef_enable = (!cm->allow_intrabc && !cm->single_tile_decoding && !cm->skip_loop_filter && !cm->coded_lossless && (cm->cdef_bits || cm->cdef_strengths[0] || cm->cdef_uv_strengths[0]));
4014 printk("LPF_ENABLES : dblk(%d) cdef(%d)\n", dblk_enable, cdef_enable);
4015 data32 = READ_VREG(HEVC_DBLK_CFGB );
4016 data32 &= ~(0xf<<20);
4017 data32 |= (dblk_enable<<20);
4018 data32 |= (cdef_enable<<23);
4019 WRITE_VREG(HEVC_DBLK_CFGB, data32);
4020 */
4021}
4022
4023#endif // #ifdef AOM_AV1_UPSCALE_INIT
4024
4025static void release_dblk_struct(struct AV1HW_s *hw)
4026{
4027#ifdef AOM_AV1_DBLK_INIT
4028 if (hw->lfi)
4029 vfree(hw->lfi);
4030 if (hw->lf)
4031 vfree(hw->lf);
4032 if (hw->seg_4lf)
4033 vfree(hw->seg_4lf);
4034 hw->lfi = NULL;
4035 hw->lf = NULL;
4036 hw->seg_4lf = NULL;
4037#endif
4038}
4039
4040static int init_dblk_struc(struct AV1HW_s *hw)
4041{
4042#ifdef AOM_AV1_DBLK_INIT
4043 hw->lfi = vmalloc(sizeof(loop_filter_info_n));
4044 hw->lf = vmalloc(sizeof(struct loopfilter));
4045 hw->seg_4lf = vmalloc(sizeof(struct segmentation_lf));
4046
4047 if (hw->lfi == NULL || hw->lf == NULL || hw->seg_4lf == NULL) {
4048 printk("[test.c] aom_loop_filter init malloc error!!!\n");
4049 release_dblk_struct(hw);
4050 return -1;
4051 }
4052
4053 hw->lf->mode_ref_delta_enabled = 1; // set default here
4054 hw->lf->mode_ref_delta_update = 1; // set default here
4055 hw->lf->sharpness_level = 0; // init to 0
4056 hw->lf->lf_pic_cnt = 0; // init to 0
4057#endif
4058 return 0;
4059}
4060
4061static void config_dblk_hw(struct AV1HW_s *hw)
4062{
4063 AV1Decoder *pbi = hw->pbi;
4064 AV1_COMMON *cm = &hw->pbi->common;
4065 loop_filter_info_n *lfi = hw->lfi;
4066 struct loopfilter *lf = hw->lf;
4067 struct segmentation_lf *seg_4lf = hw->seg_4lf;
4068 BuffInfo_t* buf_spec = pbi->work_space_buf;
4069 PIC_BUFFER_CONFIG* cur_pic_config = &cm->cur_frame->buf;
4070 PIC_BUFFER_CONFIG* prev_pic_config = &cm->prev_frame->buf;
4071 int i;
4072
4073#ifdef AOM_AV1_DBLK_INIT
4074#ifdef DUAL_DECODE
4075#else
4076 av1_print(hw, AOM_DEBUG_HW_MORE,
4077 "[test.c ref_delta] cur_frame : %p prev_frame : %p - %p \n",
4078 cm->cur_frame, cm->prev_frame,
4079 av1_get_primary_ref_frame_buf(cm));
4080 // get lf parameters from parser
4081 lf->mode_ref_delta_enabled =
4082 (hw->aom_param.p.loop_filter_mode_ref_delta_enabled & 1);
4083 lf->mode_ref_delta_update =
4084 ((hw->aom_param.p.loop_filter_mode_ref_delta_enabled >> 1) & 1);
4085 lf->sharpness_level =
4086 hw->aom_param.p.loop_filter_sharpness_level;
4087 if (((hw->aom_param.p.loop_filter_mode_ref_delta_enabled)&3) == 3) { // enabled but and update
4088 if (cm->prev_frame <= 0) {
4089 // already initialized in Microcode
4090 lf->ref_deltas[0] = conv2int8((uint8_t)(hw->aom_param.p.loop_filter_ref_deltas_0),7);
4091 lf->ref_deltas[1] = conv2int8((uint8_t)(hw->aom_param.p.loop_filter_ref_deltas_0>>8),7);
4092 lf->ref_deltas[2] = conv2int8((uint8_t)(hw->aom_param.p.loop_filter_ref_deltas_1),7);
4093 lf->ref_deltas[3] = conv2int8((uint8_t)(hw->aom_param.p.loop_filter_ref_deltas_1>>8),7);
4094 lf->ref_deltas[4] = conv2int8((uint8_t)(hw->aom_param.p.loop_filter_ref_deltas_2),7);
4095 lf->ref_deltas[5] = conv2int8((uint8_t)(hw->aom_param.p.loop_filter_ref_deltas_2>>8),7);
4096 lf->ref_deltas[6] = conv2int8((uint8_t)(hw->aom_param.p.loop_filter_ref_deltas_3),7);
4097 lf->ref_deltas[7] = conv2int8((uint8_t)(hw->aom_param.p.loop_filter_ref_deltas_3>>8),7);
4098 lf->mode_deltas[0] = conv2int8((uint8_t)(hw->aom_param.p.loop_filter_mode_deltas_0),7);
4099 lf->mode_deltas[1] = conv2int8((uint8_t)(hw->aom_param.p.loop_filter_mode_deltas_0>>8),7);
4100 } else {
4101 lf->ref_deltas[0] = (hw->aom_param.p.loop_filter_ref_deltas_0 & 0x80) ?
4102 conv2int8((uint8_t)(hw->aom_param.p.loop_filter_ref_deltas_0),7) :
4103 cm->prev_frame->ref_deltas[0];
4104 lf->ref_deltas[1] = (hw->aom_param.p.loop_filter_ref_deltas_0 & 0x8000) ?
4105 conv2int8((uint8_t)(hw->aom_param.p.loop_filter_ref_deltas_0>>8),7) :
4106 cm->prev_frame->ref_deltas[1];
4107 lf->ref_deltas[2] = (hw->aom_param.p.loop_filter_ref_deltas_1 & 0x80) ?
4108 conv2int8((uint8_t)(hw->aom_param.p.loop_filter_ref_deltas_1),7) :
4109 cm->prev_frame->ref_deltas[2];
4110 lf->ref_deltas[3] = (hw->aom_param.p.loop_filter_ref_deltas_1 & 0x8000) ?
4111 conv2int8((uint8_t)(hw->aom_param.p.loop_filter_ref_deltas_1>>8),7) :
4112 cm->prev_frame->ref_deltas[3];
4113 lf->ref_deltas[4] = (hw->aom_param.p.loop_filter_ref_deltas_2 & 0x80) ?
4114 conv2int8((uint8_t)(hw->aom_param.p.loop_filter_ref_deltas_2),7) :
4115 cm->prev_frame->ref_deltas[4];
4116 lf->ref_deltas[5] = (hw->aom_param.p.loop_filter_ref_deltas_2 & 0x8000) ?
4117 conv2int8((uint8_t)(hw->aom_param.p.loop_filter_ref_deltas_2>>8),7) :
4118 cm->prev_frame->ref_deltas[5];
4119 lf->ref_deltas[6] = (hw->aom_param.p.loop_filter_ref_deltas_3 & 0x80) ?
4120 conv2int8((uint8_t)(hw->aom_param.p.loop_filter_ref_deltas_3),7) :
4121 cm->prev_frame->ref_deltas[6];
4122 lf->ref_deltas[7] = (hw->aom_param.p.loop_filter_ref_deltas_3 & 0x8000) ?
4123 conv2int8((uint8_t)(hw->aom_param.p.loop_filter_ref_deltas_3>>8),7) :
4124 cm->prev_frame->ref_deltas[7];
4125 lf->mode_deltas[0] = (hw->aom_param.p.loop_filter_mode_deltas_0 & 0x80) ?
4126 conv2int8((uint8_t)(hw->aom_param.p.loop_filter_mode_deltas_0),7) :
4127 cm->prev_frame->mode_deltas[0];
4128 lf->mode_deltas[1] = (hw->aom_param.p.loop_filter_mode_deltas_0 & 0x8000) ?
4129 conv2int8((uint8_t)(hw->aom_param.p.loop_filter_mode_deltas_0>>8),7) :
4130 cm->prev_frame->mode_deltas[1];
4131 }
4132 } //else if (hw->aom_param.p.loop_filter_mode_ref_delta_enabled == 1) { // enabled but no update
4133 else { // match c code -- not enabled, still need to copy prev to used for next
4134 if ((cm->prev_frame <= 0) | (hw->aom_param.p.loop_filter_mode_ref_delta_enabled & 4)) {
4135 av1_print(hw, AOM_DEBUG_HW_MORE,
4136 "[test.c] mode_ref_delta set to default\n");
4137 lf->ref_deltas[0] = conv2int8((uint8_t)1,7);
4138 lf->ref_deltas[1] = conv2int8((uint8_t)0,7);
4139 lf->ref_deltas[2] = conv2int8((uint8_t)0,7);
4140 lf->ref_deltas[3] = conv2int8((uint8_t)0,7);
4141 lf->ref_deltas[4] = conv2int8((uint8_t)0xff,7);
4142 lf->ref_deltas[5] = conv2int8((uint8_t)0,7);
4143 lf->ref_deltas[6] = conv2int8((uint8_t)0xff,7);
4144 lf->ref_deltas[7] = conv2int8((uint8_t)0xff,7);
4145 lf->mode_deltas[0] = conv2int8((uint8_t)0,7);
4146 lf->mode_deltas[1] = conv2int8((uint8_t)0,7);
4147 } else {
4148 av1_print(hw, AOM_DEBUG_HW_MORE,
4149 "[test.c] mode_ref_delta copy from prev_frame\n");
4150 lf->ref_deltas[0] = cm->prev_frame->ref_deltas[0];
4151 lf->ref_deltas[1] = cm->prev_frame->ref_deltas[1];
4152 lf->ref_deltas[2] = cm->prev_frame->ref_deltas[2];
4153 lf->ref_deltas[3] = cm->prev_frame->ref_deltas[3];
4154 lf->ref_deltas[4] = cm->prev_frame->ref_deltas[4];
4155 lf->ref_deltas[5] = cm->prev_frame->ref_deltas[5];
4156 lf->ref_deltas[6] = cm->prev_frame->ref_deltas[6];
4157 lf->ref_deltas[7] = cm->prev_frame->ref_deltas[7];
4158 lf->mode_deltas[0] = cm->prev_frame->mode_deltas[0];
4159 lf->mode_deltas[1] = cm->prev_frame->mode_deltas[1];
4160 }
4161 }
4162 lf->filter_level[0] = hw->aom_param.p.loop_filter_level_0;
4163 lf->filter_level[1] = hw->aom_param.p.loop_filter_level_1;
4164 lf->filter_level_u = hw->aom_param.p.loop_filter_level_u;
4165 lf->filter_level_v = hw->aom_param.p.loop_filter_level_v;
4166
4167 cm->cur_frame->ref_deltas[0] = lf->ref_deltas[0];
4168 cm->cur_frame->ref_deltas[1] = lf->ref_deltas[1];
4169 cm->cur_frame->ref_deltas[2] = lf->ref_deltas[2];
4170 cm->cur_frame->ref_deltas[3] = lf->ref_deltas[3];
4171 cm->cur_frame->ref_deltas[4] = lf->ref_deltas[4];
4172 cm->cur_frame->ref_deltas[5] = lf->ref_deltas[5];
4173 cm->cur_frame->ref_deltas[6] = lf->ref_deltas[6];
4174 cm->cur_frame->ref_deltas[7] = lf->ref_deltas[7];
4175 cm->cur_frame->mode_deltas[0] = lf->mode_deltas[0];
4176 cm->cur_frame->mode_deltas[1] = lf->mode_deltas[1];
4177
4178 // get seg_4lf parameters from parser
4179 seg_4lf->enabled = hw->aom_param.p.segmentation_enabled & 1;
4180 cm->cur_frame->segmentation_enabled = hw->aom_param.p.segmentation_enabled & 1;
4181 cm->cur_frame->intra_only = (hw->aom_param.p.segmentation_enabled >> 2) & 1;
4182 cm->cur_frame->segmentation_update_map = (hw->aom_param.p.segmentation_enabled >> 3) & 1;
4183
4184 if (hw->aom_param.p.segmentation_enabled & 1) { // segmentation_enabled
4185 if (hw->aom_param.p.segmentation_enabled & 2) { // segmentation_update_data
4186 for (i = 0; i < MAX_SEGMENTS; i++) {
4187 seg_4lf->seg_lf_info_y[i] = hw->aom_param.p.seg_lf_info_y[i];
4188 seg_4lf->seg_lf_info_c[i] = hw->aom_param.p.seg_lf_info_c[i];
4189 #ifdef DBG_LPF_PRINT
4190 printk(" read seg_lf_info [%d] : 0x%x, 0x%x\n",
4191 i, seg_4lf->seg_lf_info_y[i], seg_4lf->seg_lf_info_c[i]);
4192 #endif
4193 }
4194 } // segmentation_update_data
4195 else { // no segmentation_update_data
4196 if (cm->prev_frame <= 0) {
4197 for (i=0;i<MAX_SEGMENTS;i++) {
4198 seg_4lf->seg_lf_info_y[i] = 0;
4199 seg_4lf->seg_lf_info_c[i] = 0;
4200 }
4201 } else {
4202 for (i = 0; i < MAX_SEGMENTS; i++) {
4203 seg_4lf->seg_lf_info_y[i] = cm->prev_frame->seg_lf_info_y[i];
4204 seg_4lf->seg_lf_info_c[i] = cm->prev_frame->seg_lf_info_c[i];
4205 #ifdef DBG_LPF_PRINT
4206 printk(" Refrence seg_lf_info [%d] : 0x%x, 0x%x\n",
4207 i, seg_4lf->seg_lf_info_y[i], seg_4lf->seg_lf_info_c[i]);
4208 #endif
4209 }
4210 }
4211 } // no segmentation_update_data
4212 } // segmentation_enabled
4213 else {
4214 for (i=0;i<MAX_SEGMENTS;i++) {
4215 seg_4lf->seg_lf_info_y[i] = 0;
4216 seg_4lf->seg_lf_info_c[i] = 0;
4217 }
4218 } // NOT segmentation_enabled
4219 for (i=0;i<MAX_SEGMENTS;i++) {
4220 cm->cur_frame->seg_lf_info_y[i] = seg_4lf->seg_lf_info_y[i];
4221 cm->cur_frame->seg_lf_info_c[i] = seg_4lf->seg_lf_info_c[i];
4222#ifdef DBG_LPF_PRINT
4223 printk(" SAVE seg_lf_info [%d] : 0x%x, 0x%x\n",
4224 i, cm->cur_frame->seg_lf_info_y[i],
4225 cm->cur_frame->seg_lf_info_c[i]);
4226#endif
4227 }
4228
4229 /*
4230 * Update loop filter Thr/Lvl table for every frame
4231 */
4232 av1_print(hw, AOM_DEBUG_HW_MORE,
4233 "[test.c] av1_loop_filter_frame_init (run before every frame decoding start)\n");
4234 av1_loop_filter_frame_init(pbi, seg_4lf, lfi, lf, cm->dec_width);
4235#endif // not DUAL_DECODE
4236#endif
4237
4238#ifdef AOM_AV1_UPSCALE_INIT
4239 /*
4240 * init for upscaling
4241 */
4242 av1_print(hw, AOM_DEBUG_HW_MORE,
4243 "[test.c] av1_upscale_frame_init (run before every frame decoding start)\n");
4244 av1_upscale_frame_init(pbi,
4245 &pbi->common, &hw->aom_param);
4246#endif // #ifdef AOM_AV1_UPSCALE_INIT
4247
4248 //BuffInfo_t* buf_spec = pbi->work_space_buf;
4249 av1_print(hw, AOM_DEBUG_HW_MORE,
4250 "[test.c] cur_frame : %p prev_frame : %p - %p \n",
4251 cm->cur_frame, cm->prev_frame, av1_get_primary_ref_frame_buf(cm));
4252 if (cm->cur_frame <= 0) {
4253 WRITE_VREG(AOM_AV1_CDF_BUFFER_W, buf_spec->cdf_buf.buf_start);
4254 WRITE_VREG(AOM_AV1_SEG_MAP_BUFFER_W, buf_spec->seg_map.buf_start);
4255 }
4256 else {
4257 av1_print(hw, AOM_DEBUG_HW_MORE,
4258 "[test.c] Config WRITE CDF_BUF/SEG_MAP_BUF : %d\n",
4259 cur_pic_config->index);
4260 WRITE_VREG(AOM_AV1_CDF_BUFFER_W,
4261 buf_spec->cdf_buf.buf_start + (0x8000*cur_pic_config->index));
4262 WRITE_VREG(AOM_AV1_SEG_MAP_BUFFER_W,
4263 buf_spec->seg_map.buf_start + (seg_map_size*cur_pic_config->index));
4264 }
4265 cm->cur_frame->seg_mi_rows = cm->cur_frame->mi_rows;
4266 cm->cur_frame->seg_mi_cols = cm->cur_frame->mi_cols;
4267 if (cm->prev_frame <= 0) {
4268 WRITE_VREG(AOM_AV1_CDF_BUFFER_R, buf_spec->cdf_buf.buf_start);
4269 WRITE_VREG(AOM_AV1_SEG_MAP_BUFFER_R, buf_spec->seg_map.buf_start);
4270 } else {
4271 av1_print(hw, AOM_DEBUG_HW_MORE,
4272 "[test.c] Config READ CDF_BUF/SEG_MAP_BUF : %d\n",
4273 prev_pic_config->index);
4274 WRITE_VREG(AOM_AV1_CDF_BUFFER_R,
4275 buf_spec->cdf_buf.buf_start + (0x8000*prev_pic_config->index));
4276 WRITE_VREG(AOM_AV1_SEG_MAP_BUFFER_R,
4277 buf_spec->seg_map.buf_start + (seg_map_size*prev_pic_config->index));
4278
4279 // segmentation_enabled but no segmentation_update_data
4280 if ((hw->aom_param.p.segmentation_enabled & 3) == 1) {
4281 av1_print(hw, AOM_DEBUG_HW_MORE,
4282 "[test.c] segfeatures_copy from prev_frame\n");
4283 for (i = 0; i < 8; i++) {
4284 WRITE_VREG(AOM_AV1_SEGMENT_FEATURE,
4285 cm->prev_frame->segment_feature[i]);
4286 }
4287 }
4288 // segmentation_enabled but no segmentation_update_map
4289 if ((hw->aom_param.p.segmentation_enabled & 9) == 1) {
4290 av1_print(hw, AOM_DEBUG_HW_MORE,
4291 "[test.c] seg_map_size copy from prev_frame\n");
4292 cm->cur_frame->seg_mi_rows = cm->prev_frame->seg_mi_rows;
4293 cm->cur_frame->seg_mi_cols = cm->prev_frame->seg_mi_cols;
4294 }
4295 }
4296#ifdef PRINT_HEVC_DATA_PATH_MONITOR
4297 {
4298 uint32_t total_clk_count;
4299 uint32_t path_transfer_count;
4300 uint32_t path_wait_count;
4301 float path_wait_ratio;
4302 if (pbi->decode_idx > 1) {
4303 WRITE_VREG(HEVC_PATH_MONITOR_CTRL, 0); // Disabble monitor and set rd_idx to 0
4304 total_clk_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
4305
4306 WRITE_VREG(HEVC_PATH_MONITOR_CTRL, (1<<4)); // Disabble monitor and set rd_idx to 0
4307
4308 // parser --> iqit
4309 path_transfer_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
4310 path_wait_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
4311 if (path_transfer_count == 0)
4312 path_wait_ratio = 0.0;
4313 else
4314 path_wait_ratio =
4315 (float)path_wait_count/(float)path_transfer_count;
4316 printk("[P%d HEVC PATH] Parser/IQIT/IPP/DBLK/OW/DDR/CMD WAITING \% : %.2f",
4317 pbi->decode_idx - 2,
4318 path_wait_ratio);
4319
4320 // iqit --> ipp
4321 path_transfer_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
4322 path_wait_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
4323 if (path_transfer_count == 0)
4324 path_wait_ratio = 0.0;
4325 else
4326 path_wait_ratio = (float)path_wait_count/(float)path_transfer_count;
4327 printk(" %.2f", path_wait_ratio);
4328
4329 // dblk <-- ipp
4330 path_transfer_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
4331 path_wait_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
4332 if (path_transfer_count == 0)
4333 path_wait_ratio = 0.0;
4334 else
4335 path_wait_ratio = (float)path_wait_count/(float)path_transfer_count;
4336 printk(" %.2f", path_wait_ratio);
4337
4338 // dblk --> ow
4339 path_transfer_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
4340 path_wait_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
4341 if (path_transfer_count == 0)
4342 path_wait_ratio = 0.0;
4343 else path_wait_ratio =
4344 (float)path_wait_count/(float)path_transfer_count;
4345 printk(" %.2f", path_wait_ratio);
4346
4347 // <--> DDR
4348 path_transfer_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
4349 path_wait_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
4350 if (path_transfer_count == 0)
4351 path_wait_ratio = 0.0;
4352 else path_wait_ratio =
4353 (float)path_wait_count/(float)path_transfer_count;
4354 printk(" %.2f", path_wait_ratio);
4355
4356 // CMD
4357 path_transfer_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
4358 path_wait_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
4359 if (path_transfer_count == 0)
4360 path_wait_ratio = 0.0;
4361 else
4362 path_wait_ratio = (float)path_wait_count/(float)path_transfer_count;
4363 printk(" %.2f\n", path_wait_ratio);
4364 }
4365 }
4366
4367#endif
4368
4369}
4370
4371static void aom_config_work_space_hw(struct AV1HW_s *hw, u32 mask)
4372{
4373 struct BuffInfo_s *buf_spec = hw->work_space_buf;
4374 unsigned int data32;
4375 av1_print(hw, AOM_DEBUG_HW_MORE, "%s %d\n", __func__, __LINE__);
4376 if (debug && hw->init_flag == 0)
4377 av1_print(hw, AOM_DEBUG_HW_MORE, "%s %x %x %x %x %x %x %x %x\n",
4378 __func__,
4379 buf_spec->ipp.buf_start,
4380 buf_spec->start_adr,
4381 buf_spec->short_term_rps.buf_start,
4382 buf_spec->sao_up.buf_start,
4383 buf_spec->swap_buf.buf_start,
4384 buf_spec->scalelut.buf_start,
4385 buf_spec->dblk_para.buf_start,
4386 buf_spec->dblk_data.buf_start);
4387 if (mask & HW_MASK_FRONT) {
4388 av1_print(hw, AOM_DEBUG_HW_MORE, "%s %d\n", __func__, __LINE__);
4389 if ((debug & AOM_AV1_DEBUG_SEND_PARAM_WITH_REG) == 0)
4390 WRITE_VREG(HEVC_RPM_BUFFER, (u32)hw->rpm_phy_addr);
4391
4392 /*WRITE_VREG(HEVC_STREAM_SWAP_BUFFER,
4393 buf_spec->swap_buf.buf_start);*/
4394 WRITE_VREG(LMEM_DUMP_ADR, (u32)hw->lmem_phy_addr);
4395
4396 }
4397
4398 av1_print(hw, AOM_DEBUG_HW_MORE, "%s %d\n", __func__, __LINE__);
4399
4400 WRITE_VREG(AOM_AV1_DAALA_TOP_BUFFER,
4401 buf_spec->daala_top.buf_start);
4402 WRITE_VREG(AV1_GMC_PARAM_BUFF_ADDR,
4403 buf_spec->gmc_buf.buf_start);
4404
4405 WRITE_VREG(HEVC_DBLK_CFG4,
4406 buf_spec->dblk_para.buf_start); // cfg_addr_cif
4407 WRITE_VREG(HEVC_DBLK_CFG5,
4408 buf_spec->dblk_data.buf_start); // cfg_addr_xio
4409
4410 if (mask & HW_MASK_BACK) {
4411#ifdef LOSLESS_COMPRESS_MODE
4412 int losless_comp_header_size =
4413 compute_losless_comp_header_size(hw->init_pic_w,
4414 hw->init_pic_h);
4415 int losless_comp_body_size =
4416 compute_losless_comp_body_size(hw->init_pic_w,
4417 hw->init_pic_h, buf_alloc_depth == 10);
4418#endif
4419#ifdef AOM_AV1_MMU_DW
4420 int losless_comp_header_size_dw =
4421 compute_losless_comp_header_size_dw(hw->init_pic_w,
4422 hw->init_pic_h);
4423 int losless_comp_body_size_dw =
4424 compute_losless_comp_body_size_dw(hw->init_pic_w,
4425 hw->init_pic_h, buf_alloc_depth == 10);
4426#endif
4427 WRITE_VREG(HEVCD_IPP_LINEBUFF_BASE,
4428 buf_spec->ipp.buf_start);
4429 WRITE_VREG(HEVC_SAO_UP, buf_spec->sao_up.buf_start);
4430 //WRITE_VREG(HEVC_SCALELUT, buf_spec->scalelut.buf_start);
4431#ifdef CHANGE_REMOVED
4432 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
4433 /* cfg_addr_adp*/
4434 WRITE_VREG(HEVC_DBLK_CFGE, buf_spec->dblk_para.buf_start);
4435 if (debug & AV1_DEBUG_BUFMGR_MORE)
4436 pr_info("Write HEVC_DBLK_CFGE\n");
4437 }
4438#endif
4439 /* cfg_p_addr */
4440 WRITE_VREG(HEVC_DBLK_CFG4, buf_spec->dblk_para.buf_start);
4441 /* cfg_d_addr */
4442 WRITE_VREG(HEVC_DBLK_CFG5, buf_spec->dblk_data.buf_start);
4443
4444#ifdef CHANGE_REMOVED
4445 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
4446 /*
4447 * data32 = (READ_VREG(HEVC_DBLK_CFG3)>>8) & 0xff; // xio left offset, default is 0x40
4448 * data32 = data32 * 2;
4449 * data32 = (READ_VREG(HEVC_DBLK_CFG3)>>16) & 0xff; // adp left offset, default is 0x040
4450 * data32 = data32 * 2;
4451 */
4452 WRITE_VREG(HEVC_DBLK_CFG3, 0x808010); // make left storage 2 x 4k]
4453 }
4454#endif
4455#ifdef LOSLESS_COMPRESS_MODE
4456 if (hw->mmu_enable) {
4457 /*bit[4] : paged_mem_mode*/
4458 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
4459#ifdef CHANGE_REMOVED
4460 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_SM1)
4461#endif
4462 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0);
4463 } else {
4464 /*if (cur_pic_config->bit_depth == AOM_BITS_10)
4465 * WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0<<3));
4466 */
4467 /*bit[3] smem mdoe*/
4468 /*else WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (1<<3));*/
4469 /*bit[3] smem mdoe*/
4470 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2,
4471 (losless_comp_body_size >> 5));
4472 }
4473 /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL2,
4474 (losless_comp_body_size >> 5));*/
4475 /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,
4476 (0xff<<20) | (0xff<<10) | 0xff);*/
4477 /*8-bit mode */
4478 WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size);
4479 WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size);
4480 WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size);
4481 if (get_double_write_mode(hw) & 0x10)
4482 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
4483#else
4484 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
4485#endif
4486
4487 if (hw->mmu_enable) {
4488 WRITE_VREG(HEVC_SAO_MMU_VH0_ADDR, buf_spec->mmu_vbh.buf_start);
4489 WRITE_VREG(HEVC_SAO_MMU_VH1_ADDR, buf_spec->mmu_vbh.buf_start
4490 + VBH_BUF_SIZE);
4491 /*data32 = READ_VREG(HEVC_SAO_CTRL9);*/
4492 /*data32 |= 0x1;*/
4493 /*WRITE_VREG(HEVC_SAO_CTRL9, data32);*/
4494
4495 /* use HEVC_CM_HEADER_START_ADDR */
4496 data32 = READ_VREG(HEVC_SAO_CTRL5);
4497 data32 |= (1<<10);
4498 WRITE_VREG(HEVC_SAO_CTRL5, data32);
4499 }
4500#ifdef AOM_AV1_MMU_DW
4501 data32 = READ_VREG(HEVC_SAO_CTRL5);
4502 if (hw->dw_mmu_enable) {
4503 data32 = READ_VREG(HEVC_SAO_CTRL9);
4504 data32 |= (1<<10);
4505 WRITE_VREG(HEVC_SAO_CTRL9, data32);
4506
4507 WRITE_VREG(HEVC_CM_BODY_LENGTH2,losless_comp_body_size_dw);
4508 WRITE_VREG(HEVC_CM_HEADER_OFFSET2,losless_comp_body_size_dw);
4509 WRITE_VREG(HEVC_CM_HEADER_LENGTH2,losless_comp_header_size_dw);
4510
4511 WRITE_VREG(HEVC_SAO_MMU_VH0_ADDR2, buf_spec->mmu_vbh_dw.buf_start);
4512 WRITE_VREG(HEVC_SAO_MMU_VH1_ADDR2, buf_spec->mmu_vbh_dw.buf_start
4513 + VBH_BUF_SIZE);
4514
4515 WRITE_VREG(HEVC_DW_VH0_ADDDR, buf_spec->mmu_vbh_dw.buf_start
4516 + (2 * VBH_BUF_SIZE));
4517 WRITE_VREG(HEVC_DW_VH1_ADDDR, buf_spec->mmu_vbh_dw.buf_start
4518 + (3 * VBH_BUF_SIZE));
4519
4520 /* use HEVC_CM_HEADER_START_ADDR */
4521 data32 |= (1<<15);
4522 } else
4523 data32 &= ~(1<<15);
4524 WRITE_VREG(HEVC_SAO_CTRL5, data32);
4525#endif
4526
4527 WRITE_VREG(LMEM_DUMP_ADR, (u32)hw->lmem_phy_addr);
4528#ifdef CHANGE_REMOVED
4529
4530 WRITE_VREG(AV1_SEG_MAP_BUFFER, buf_spec->seg_map.buf_start);
4531
4532 /**/
4533 WRITE_VREG(AV1_PROB_SWAP_BUFFER, hw->prob_buffer_phy_addr);
4534 WRITE_VREG(AV1_COUNT_SWAP_BUFFER, hw->count_buffer_phy_addr);
4535 if (hw->mmu_enable) {
4536 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A)
4537 WRITE_VREG(HEVC_ASSIST_MMU_MAP_ADDR, hw->frame_mmu_map_phy_addr);
4538 else
4539 WRITE_VREG(AV1_MMU_MAP_BUFFER, hw->frame_mmu_map_phy_addr);
4540 }
4541#else
4542 if (hw->mmu_enable)
4543 WRITE_VREG(HEVC_SAO_MMU_DMA_CTRL, hw->frame_mmu_map_phy_addr);
4544#ifdef AOM_AV1_MMU_DW
4545 if (hw->dw_mmu_enable) {
4546 WRITE_VREG(HEVC_SAO_MMU_DMA_CTRL2, hw->dw_frame_mmu_map_phy_addr);
4547 //default of 0xffffffff will disable dw
4548 WRITE_VREG(HEVC_SAO_Y_START_ADDR, 0);
4549 WRITE_VREG(HEVC_SAO_C_START_ADDR, 0);
4550 }
4551#endif
4552#endif
4553 }
4554
4555 config_aux_buf(hw);
4556}
4557
4558#ifdef MCRCC_ENABLE
4559static u32 mcrcc_cache_alg_flag = 1;
4560static void mcrcc_perfcount_reset(struct AV1HW_s *hw);
4561static void decomp_perfcount_reset(struct AV1HW_s *hw);
4562#endif
4563
4564static void aom_init_decoder_hw(struct AV1HW_s *hw, u32 mask)
4565{
4566 unsigned int data32;
4567 int i;
4568 const unsigned short parser_cmd[PARSER_CMD_NUMBER] = {
4569 0x0401, 0x8401, 0x0800, 0x0402, 0x9002, 0x1423,
4570 0x8CC3, 0x1423, 0x8804, 0x9825, 0x0800, 0x04FE,
4571 0x8406, 0x8411, 0x1800, 0x8408, 0x8409, 0x8C2A,
4572 0x9C2B, 0x1C00, 0x840F, 0x8407, 0x8000, 0x8408,
4573 0x2000, 0xA800, 0x8410, 0x04DE, 0x840C, 0x840D,
4574 0xAC00, 0xA000, 0x08C0, 0x08E0, 0xA40E, 0xFC00,
4575 0x7C00
4576 };
4577#if 0
4578 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
4579 /* Set MCR fetch priorities*/
4580 data32 = 0x1 | (0x1 << 2) | (0x1 <<3) |
4581 (24 << 4) | (32 << 11) | (24 << 18) | (32 << 25);
4582 WRITE_VREG(HEVCD_MPP_DECOMP_AXIURG_CTL, data32);
4583 }
4584#endif
4585 /*if (debug & AV1_DEBUG_BUFMGR_MORE)
4586 pr_info("%s\n", __func__);*/
4587 if (mask & HW_MASK_FRONT) {
4588 data32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
4589#ifdef CHANGE_REMOVED
4590#if 1
4591 /* set bit 31~29 to 3 if HEVC_STREAM_FIFO_CTL[29] is 1 */
4592 data32 &= ~(7 << 29);
4593 data32 |= (3 << 29);
4594#endif
4595 data32 = data32 |
4596 (1 << 24) |/*stream_buffer_empty_int_amrisc_enable*/
4597 (1 << 22) |/*stream_fifo_empty_int_amrisc_enable*/
4598 (1 << 7) |/*dec_done_int_cpu_enable*/
4599 (1 << 4) |/*startcode_found_int_cpu_enable*/
4600 (0 << 3) |/*startcode_found_int_amrisc_enable*/
4601 (1 << 0) /*parser_int_enable*/
4602 ;
4603#else
4604 data32 = data32 & 0x03ffffff;
4605 data32 = data32 |
4606 (3 << 29) | // stream_buffer_empty_int_ctl ( 0x200 interrupt)
4607 (3 << 26) | // stream_fifo_empty_int_ctl ( 4 interrupt)
4608 (1 << 24) | // stream_buffer_empty_int_amrisc_enable
4609 (1 << 22) | // stream_fifo_empty_int_amrisc_enable
4610#ifdef AOM_AV1_HED_FB
4611#ifdef DUAL_DECODE
4612 // For HALT CCPU test. Use Pull inside CCPU to generate interrupt
4613 // (1 << 9) | // fed_fb_slice_done_int_amrisc_enable
4614#else
4615 (1 << 10) | // fed_fb_slice_done_int_cpu_enable
4616#endif
4617#endif
4618 (1 << 7) | // dec_done_int_cpu_enable
4619 (1 << 4) | // startcode_found_int_cpu_enable
4620 (0 << 3) | // startcode_found_int_amrisc_enable
4621 (1 << 0) // parser_int_enable
4622 ;
4623#endif
4624 WRITE_VREG(HEVC_PARSER_INT_CONTROL, data32);
4625
4626 data32 = READ_VREG(HEVC_SHIFT_STATUS);
4627 data32 = data32 |
4628 (0 << 1) |/*emulation_check_off AV1
4629 do not have emulation*/
4630 (1 << 0)/*startcode_check_on*/
4631 ;
4632 WRITE_VREG(HEVC_SHIFT_STATUS, data32);
4633 WRITE_VREG(HEVC_SHIFT_CONTROL,
4634 (0 << 14) | /*disable_start_code_protect*/
4635 (1 << 10) | /*length_zero_startcode_en for AV1*/
4636 (1 << 9) | /*length_valid_startcode_en for AV1*/
4637 (3 << 6) | /*sft_valid_wr_position*/
4638 (2 << 4) | /*emulate_code_length_sub_1*/
4639 (3 << 1) | /*start_code_length_sub_1
4640 AV1 use 0x00000001 as startcode (4 Bytes)*/
4641 (1 << 0) /*stream_shift_enable*/
4642 );
4643
4644 WRITE_VREG(HEVC_CABAC_CONTROL,
4645 (1 << 0)/*cabac_enable*/
4646 );
4647
4648 WRITE_VREG(HEVC_PARSER_CORE_CONTROL,
4649 (1 << 0)/* hevc_parser_core_clk_en*/
4650 );
4651
4652 WRITE_VREG(HEVC_DEC_STATUS_REG, 0);
4653 }
4654
4655 if (mask & HW_MASK_BACK) {
4656 /*Initial IQIT_SCALELUT memory
4657 -- just to avoid X in simulation*/
4658
4659 WRITE_VREG(HEVC_IQIT_SCALELUT_WR_ADDR, 0);/*cfg_p_addr*/
4660 for (i = 0; i < 1024; i++)
4661 WRITE_VREG(HEVC_IQIT_SCALELUT_DATA, 0);
4662 }
4663
4664 if (mask & HW_MASK_FRONT) {
4665 u32 decode_mode;
4666/*
4667#ifdef ENABLE_SWAP_TEST
4668 WRITE_VREG(HEVC_STREAM_SWAP_TEST, 100);
4669#else
4670 WRITE_VREG(HEVC_STREAM_SWAP_TEST, 0);
4671#endif
4672*/
4673#ifdef MULTI_INSTANCE_SUPPORT
4674 if (!hw->m_ins_flag) {
4675 if (hw->low_latency_flag)
4676 decode_mode = DECODE_MODE_SINGLE_LOW_LATENCY;
4677 else
4678 decode_mode = DECODE_MODE_SINGLE;
4679 } else if (vdec_frame_based(hw_to_vdec(hw)))
4680 decode_mode = hw->no_head ?
4681 DECODE_MODE_MULTI_FRAMEBASE_NOHEAD :
4682 DECODE_MODE_MULTI_FRAMEBASE;
4683 else
4684 decode_mode = DECODE_MODE_MULTI_STREAMBASE;
4685 if (debug & AOM_DEBUG_BUFMGR_ONLY)
4686 decode_mode |= (1 << 16);
4687 WRITE_VREG(DECODE_MODE, decode_mode);
4688 WRITE_VREG(HEVC_DECODE_SIZE, 0);
4689 WRITE_VREG(HEVC_DECODE_COUNT, 0);
4690#else
4691 WRITE_VREG(DECODE_MODE, DECODE_MODE_SINGLE);
4692 WRITE_VREG(HEVC_DECODE_PIC_BEGIN_REG, 0);
4693 WRITE_VREG(HEVC_DECODE_PIC_NUM_REG, 0x7fffffff); /*to remove*/
4694#endif
4695 /*Send parser_cmd*/
4696 WRITE_VREG(HEVC_PARSER_CMD_WRITE, (1 << 16) | (0 << 0));
4697 for (i = 0; i < PARSER_CMD_NUMBER; i++)
4698 WRITE_VREG(HEVC_PARSER_CMD_WRITE, parser_cmd[i]);
4699 WRITE_VREG(HEVC_PARSER_CMD_SKIP_0, PARSER_CMD_SKIP_CFG_0);
4700 WRITE_VREG(HEVC_PARSER_CMD_SKIP_1, PARSER_CMD_SKIP_CFG_1);
4701 WRITE_VREG(HEVC_PARSER_CMD_SKIP_2, PARSER_CMD_SKIP_CFG_2);
4702
4703
4704 WRITE_VREG(HEVC_PARSER_IF_CONTROL,
4705 /* (1 << 8) |*/ /*sao_sw_pred_enable*/
4706 (1 << 5) | /*parser_sao_if_en*/
4707 (1 << 2) | /*parser_mpred_if_en*/
4708 (1 << 0) /*parser_scaler_if_en*/
4709 );
4710 }
4711
4712 if (mask & HW_MASK_BACK) {
4713 /*Changed to Start MPRED in microcode*/
4714 /*
4715 pr_info("[test.c] Start MPRED\n");
4716 WRITE_VREG(HEVC_MPRED_INT_STATUS,
4717 (1<<31)
4718 );
4719 */
4720 WRITE_VREG(HEVCD_IPP_TOP_CNTL,
4721 (0 << 1) | /*enable ipp*/
4722 (1 << 0) /*software reset ipp and mpp*/
4723 );
4724#ifdef CHANGE_REMOVED
4725 WRITE_VREG(HEVCD_IPP_TOP_CNTL,
4726 (1 << 1) | /*enable ipp*/
4727 (0 << 0) /*software reset ipp and mpp*/
4728 );
4729#else
4730 WRITE_VREG(HEVCD_IPP_TOP_CNTL,
4731 (3 << 4) | // av1
4732 (1 << 1) | /*enable ipp*/
4733 (0 << 0) /*software reset ipp and mpp*/
4734 );
4735#endif
4736 if (get_double_write_mode(hw) & 0x10) {
4737 /*Enable NV21 reference read mode for MC*/
4738 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
4739 }
4740#ifdef MCRCC_ENABLE
4741 /*Initialize mcrcc and decomp perf counters*/
4742 if (mcrcc_cache_alg_flag &&
4743 hw->init_flag == 0) {
4744 mcrcc_perfcount_reset(hw);
4745 decomp_perfcount_reset(hw);
4746 }
4747#endif
4748 }
4749#ifdef CHANGE_REMOVED
4750#else
4751// Set MCR fetch priorities
4752 data32 = 0x1 | (0x1 << 2) | (0x1 <<3) |
4753 (24 << 4) | (32 << 11) | (24 << 18) | (32 << 25);
4754 WRITE_VREG(HEVCD_MPP_DECOMP_AXIURG_CTL, data32);
4755#endif
4756 return;
4757}
4758
4759
4760#ifdef CONFIG_HEVC_CLK_FORCED_ON
4761static void config_av1_clk_forced_on(void)
4762{
4763 unsigned int rdata32;
4764 /*IQIT*/
4765 rdata32 = READ_VREG(HEVC_IQIT_CLK_RST_CTRL);
4766 WRITE_VREG(HEVC_IQIT_CLK_RST_CTRL, rdata32 | (0x1 << 2));
4767
4768 /* DBLK*/
4769 rdata32 = READ_VREG(HEVC_DBLK_CFG0);
4770 WRITE_VREG(HEVC_DBLK_CFG0, rdata32 | (0x1 << 2));
4771
4772 /* SAO*/
4773 rdata32 = READ_VREG(HEVC_SAO_CTRL1);
4774 WRITE_VREG(HEVC_SAO_CTRL1, rdata32 | (0x1 << 2));
4775
4776 /*MPRED*/
4777 rdata32 = READ_VREG(HEVC_MPRED_CTRL1);
4778 WRITE_VREG(HEVC_MPRED_CTRL1, rdata32 | (0x1 << 24));
4779
4780 /* PARSER*/
4781 rdata32 = READ_VREG(HEVC_STREAM_CONTROL);
4782 WRITE_VREG(HEVC_STREAM_CONTROL, rdata32 | (0x1 << 15));
4783 rdata32 = READ_VREG(HEVC_SHIFT_CONTROL);
4784 WRITE_VREG(HEVC_SHIFT_CONTROL, rdata32 | (0x1 << 15));
4785 rdata32 = READ_VREG(HEVC_CABAC_CONTROL);
4786 WRITE_VREG(HEVC_CABAC_CONTROL, rdata32 | (0x1 << 13));
4787 rdata32 = READ_VREG(HEVC_PARSER_CORE_CONTROL);
4788 WRITE_VREG(HEVC_PARSER_CORE_CONTROL, rdata32 | (0x1 << 15));
4789 rdata32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
4790 WRITE_VREG(HEVC_PARSER_INT_CONTROL, rdata32 | (0x1 << 15));
4791 rdata32 = READ_VREG(HEVC_PARSER_IF_CONTROL);
4792 WRITE_VREG(HEVC_PARSER_IF_CONTROL,
4793 rdata32 | (0x1 << 6) | (0x1 << 3) | (0x1 << 1));
4794
4795 /*IPP*/
4796 rdata32 = READ_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG);
4797 WRITE_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG, rdata32 | 0xffffffff);
4798
4799 /* MCRCC*/
4800 rdata32 = READ_VREG(HEVCD_MCRCC_CTL1);
4801 WRITE_VREG(HEVCD_MCRCC_CTL1, rdata32 | (0x1 << 3));
4802}
4803#endif
4804
4805
4806static void av1_local_uninit(struct AV1HW_s *hw)
4807{
4808 hw->rpm_ptr = NULL;
4809 hw->lmem_ptr = NULL;
4810#ifdef DUMP_FILMGRAIN
4811 hw->fg_ptr = NULL;
4812 if (hw->fg_addr) {
4813 if (hw->fg_phy_addr)
4814 dma_free_coherent(amports_get_dma_device(),
4815 FGS_TABLE_SIZE, hw->fg_addr,
4816 hw->fg_phy_addr);
4817 hw->fg_addr = NULL;
4818 }
4819#endif
4820 if (hw->rpm_addr) {
4821 dma_free_coherent(amports_get_dma_device(),
4822 RPM_BUF_SIZE,
4823 hw->rpm_addr,
4824 hw->rpm_phy_addr);
4825 hw->rpm_addr = NULL;
4826 }
4827 if (hw->aux_addr) {
4828 dma_free_coherent(amports_get_dma_device(),
4829 hw->prefix_aux_size + hw->suffix_aux_size, hw->aux_addr,
4830 hw->aux_phy_addr);
4831 hw->aux_addr = NULL;
4832 }
4833 if (hw->lmem_addr) {
4834 if (hw->lmem_phy_addr)
4835 dma_free_coherent(amports_get_dma_device(),
4836 LMEM_BUF_SIZE, hw->lmem_addr,
4837 hw->lmem_phy_addr);
4838 hw->lmem_addr = NULL;
4839 }
4840 if (hw->prob_buffer_addr) {
4841 if (hw->prob_buffer_phy_addr)
4842 dma_free_coherent(amports_get_dma_device(),
4843 PROB_BUF_SIZE, hw->prob_buffer_addr,
4844 hw->prob_buffer_phy_addr);
4845
4846 hw->prob_buffer_addr = NULL;
4847 }
4848 if (hw->count_buffer_addr) {
4849 if (hw->count_buffer_phy_addr)
4850 dma_free_coherent(amports_get_dma_device(),
4851 COUNT_BUF_SIZE, hw->count_buffer_addr,
4852 hw->count_buffer_phy_addr);
4853
4854 hw->count_buffer_addr = NULL;
4855 }
4856 if (hw->mmu_enable) {
4857 u32 mmu_map_size = vav1_frame_mmu_map_size(hw);
4858 if (hw->frame_mmu_map_addr) {
4859 if (hw->frame_mmu_map_phy_addr)
4860 dma_free_coherent(amports_get_dma_device(),
4861 mmu_map_size,
4862 hw->frame_mmu_map_addr,
4863 hw->frame_mmu_map_phy_addr);
4864 hw->frame_mmu_map_addr = NULL;
4865 }
4866 }
4867#ifdef AOM_AV1_MMU_DW
4868 if (hw->dw_mmu_enable) {
4869 u32 mmu_map_size = vaom_dw_frame_mmu_map_size(hw);
4870 if (hw->dw_frame_mmu_map_addr) {
4871 if (hw->dw_frame_mmu_map_phy_addr)
4872 dma_free_coherent(amports_get_dma_device(),
4873 mmu_map_size,
4874 hw->dw_frame_mmu_map_addr,
4875 hw->dw_frame_mmu_map_phy_addr);
4876 hw->dw_frame_mmu_map_addr = NULL;
4877 }
4878 }
4879#endif
4880 if (hw->gvs)
4881 vfree(hw->gvs);
4882 hw->gvs = NULL;
4883}
4884
4885static int av1_local_init(struct AV1HW_s *hw)
4886{
4887 int ret = -1;
4888 /*int losless_comp_header_size, losless_comp_body_size;*/
4889
4890 struct BuffInfo_s *cur_buf_info = NULL;
4891
4892 memset(&hw->param, 0, sizeof(union param_u));
4893#ifdef MULTI_INSTANCE_SUPPORT
4894 cur_buf_info = &hw->work_space_buf_store;
4895 hw->pbi->work_space_buf = cur_buf_info;
4896
4897 if (vdec_is_support_4k()) {
4898 memcpy(cur_buf_info, &aom_workbuff_spec[1], /* 8k */
4899 sizeof(struct BuffInfo_s));
4900 } else
4901 memcpy(cur_buf_info, &aom_workbuff_spec[0],/* 1080p */
4902 sizeof(struct BuffInfo_s));
4903
4904 cur_buf_info->start_adr = hw->buf_start;
4905 if (!hw->mmu_enable)
4906 hw->mc_buf_spec.buf_end = hw->buf_start + hw->buf_size;
4907
4908#else
4909/*! MULTI_INSTANCE_SUPPORT*/
4910 if (vdec_is_support_4k()) {
4911 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
4912 cur_buf_info = &aom_workbuff_spec[1];/* 8k work space */
4913 else
4914 cur_buf_info = &aom_workbuff_spec[1];/* 4k2k work space */
4915 } else
4916 cur_buf_info = &aom_workbuff_spec[0];/* 1080p work space */
4917
4918#endif
4919
4920 init_buff_spec(hw, cur_buf_info);
4921 aom_bufmgr_init(hw, cur_buf_info, NULL);
4922
4923 if (!vdec_is_support_4k()
4924 && (buf_alloc_width > 1920 && buf_alloc_height > 1088)) {
4925 buf_alloc_width = 1920;
4926 buf_alloc_height = 1088;
4927 if (hw->max_pic_w > 1920 && hw->max_pic_h > 1088) {
4928 hw->max_pic_w = 1920;
4929 hw->max_pic_h = 1088;
4930 }
4931 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
4932#if 0
4933 buf_alloc_width = 8192;
4934 buf_alloc_height = 4608;
4935#else
4936 buf_alloc_width = 4096;
4937 buf_alloc_height = 2304;
4938#endif
4939 }
4940 hw->init_pic_w = hw->max_pic_w ? hw->max_pic_w :
4941 (buf_alloc_width ? buf_alloc_width :
4942 (hw->vav1_amstream_dec_info.width ?
4943 hw->vav1_amstream_dec_info.width :
4944 hw->work_space_buf->max_width));
4945 hw->init_pic_h = hw->max_pic_h ? hw->max_pic_h :
4946 (buf_alloc_height ? buf_alloc_height :
4947 (hw->vav1_amstream_dec_info.height ?
4948 hw->vav1_amstream_dec_info.height :
4949 hw->work_space_buf->max_height));
4950
4951 hw->pbi->frame_width = hw->init_pic_w;
4952 hw->pbi->frame_height = hw->init_pic_h;
4953
4954 /* video is not support unaligned with 64 in tl1
4955 ** vdec canvas mode will be linear when dump yuv is set
4956 */
4957 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
4958 (hw->double_write_mode != 0) &&
4959 (((hw->max_pic_w % 64) != 0) ||
4960 (hw->vav1_amstream_dec_info.width % 64) != 0)) {
4961 if (hw_to_vdec(hw)->canvas_mode !=
4962 CANVAS_BLKMODE_LINEAR)
4963 mem_map_mode = 2;
4964 else {
4965 mem_map_mode = 0;
4966 av1_print(hw, AOM_DEBUG_HW_MORE, "vdec blkmod linear, force mem_map_mode 0\n");
4967 }
4968 }
4969
4970#if 0
4971//ndef MV_USE_FIXED_BUF
4972 if (init_mv_buf_list(hw) < 0) {
4973 pr_err("%s: init_mv_buf_list fail\n", __func__);
4974 return -1;
4975 }
4976#endif
4977 if (hw->save_buffer_mode)
4978 hw->used_buf_num = MAX_BUF_NUM_SAVE_BUF;
4979 else
4980 hw->used_buf_num = max_buf_num;
4981 if (hw->used_buf_num > MAX_BUF_NUM)
4982 hw->used_buf_num = MAX_BUF_NUM;
4983 if (hw->used_buf_num > FRAME_BUFFERS)
4984 hw->used_buf_num = FRAME_BUFFERS;
4985
4986 hw->pts_unstable = ((unsigned long)(hw->vav1_amstream_dec_info.param)
4987 & 0x40) >> 6;
4988
4989 if ((debug & AOM_AV1_DEBUG_SEND_PARAM_WITH_REG) == 0) {
4990 hw->rpm_addr = dma_alloc_coherent(amports_get_dma_device(),
4991 RPM_BUF_SIZE,
4992 &hw->rpm_phy_addr, GFP_KERNEL);
4993 if (hw->rpm_addr == NULL) {
4994 pr_err("%s: failed to alloc rpm buffer\n", __func__);
4995 return -1;
4996 }
4997
4998 hw->rpm_ptr = hw->rpm_addr;
4999 }
5000
5001 if (prefix_aux_buf_size > 0 ||
5002 suffix_aux_buf_size > 0) {
5003 u32 aux_buf_size;
5004
5005 hw->prefix_aux_size = AUX_BUF_ALIGN(prefix_aux_buf_size);
5006 hw->suffix_aux_size = AUX_BUF_ALIGN(suffix_aux_buf_size);
5007 aux_buf_size = hw->prefix_aux_size + hw->suffix_aux_size;
5008 hw->aux_addr =dma_alloc_coherent(amports_get_dma_device(),
5009 aux_buf_size, &hw->aux_phy_addr, GFP_KERNEL);
5010 if (hw->aux_addr == NULL) {
5011 pr_err("%s: failed to alloc rpm buffer\n", __func__);
5012 return -1;
5013 }
5014 }
5015#ifdef DUMP_FILMGRAIN
5016 hw->fg_addr = dma_alloc_coherent(amports_get_dma_device(),
5017 FGS_TABLE_SIZE,
5018 &hw->fg_phy_addr, GFP_KERNEL);
5019 if (hw->fg_addr == NULL) {
5020 pr_err("%s: failed to alloc fg buffer\n", __func__);
5021 }
5022 hw->fg_ptr = hw->fg_addr;
5023#endif
5024 hw->lmem_addr = dma_alloc_coherent(amports_get_dma_device(),
5025 LMEM_BUF_SIZE,
5026 &hw->lmem_phy_addr, GFP_KERNEL);
5027 if (hw->lmem_addr == NULL) {
5028 pr_err("%s: failed to alloc lmem buffer\n", __func__);
5029 return -1;
5030 }
5031 hw->lmem_ptr = hw->lmem_addr;
5032
5033 hw->prob_buffer_addr = dma_alloc_coherent(amports_get_dma_device(),
5034 PROB_BUF_SIZE,
5035 &hw->prob_buffer_phy_addr, GFP_KERNEL);
5036 if (hw->prob_buffer_addr == NULL) {
5037 pr_err("%s: failed to alloc prob_buffer\n", __func__);
5038 return -1;
5039 }
5040 memset(hw->prob_buffer_addr, 0, PROB_BUF_SIZE);
5041 hw->count_buffer_addr = dma_alloc_coherent(amports_get_dma_device(),
5042 COUNT_BUF_SIZE,
5043 &hw->count_buffer_phy_addr, GFP_KERNEL);
5044 if (hw->count_buffer_addr == NULL) {
5045 pr_err("%s: failed to alloc count_buffer\n", __func__);
5046 return -1;
5047 }
5048 memset(hw->count_buffer_addr, 0, COUNT_BUF_SIZE);
5049
5050 if (hw->mmu_enable) {
5051 u32 mmu_map_size = vav1_frame_mmu_map_size(hw);
5052 hw->frame_mmu_map_addr =
5053 dma_alloc_coherent(amports_get_dma_device(),
5054 mmu_map_size,
5055 &hw->frame_mmu_map_phy_addr, GFP_KERNEL);
5056 if (hw->frame_mmu_map_addr == NULL) {
5057 pr_err("%s: failed to alloc count_buffer\n", __func__);
5058 return -1;
5059 }
5060 memset(hw->frame_mmu_map_addr, 0, mmu_map_size);
5061 }
5062#ifdef AOM_AV1_MMU_DW
5063 if (hw->dw_mmu_enable) {
5064 u32 mmu_map_size = vaom_dw_frame_mmu_map_size(hw);
5065 hw->dw_frame_mmu_map_addr =
5066 dma_alloc_coherent(amports_get_dma_device(),
5067 mmu_map_size,
5068 &hw->dw_frame_mmu_map_phy_addr, GFP_KERNEL);
5069 if (hw->dw_frame_mmu_map_addr == NULL) {
5070 pr_err("%s: failed to alloc count_buffer\n", __func__);
5071 return -1;
5072 }
5073 memset(hw->dw_frame_mmu_map_addr, 0, mmu_map_size);
5074 }
5075#endif
5076 ret = 0;
5077 return ret;
5078}
5079
5080
5081#define spec2canvas(x) \
5082 (((x)->uv_canvas_index << 16) | \
5083 ((x)->uv_canvas_index << 8) | \
5084 ((x)->y_canvas_index << 0))
5085
5086
5087static void set_canvas(struct AV1HW_s *hw,
5088 struct PIC_BUFFER_CONFIG_s *pic_config)
5089{
5090 struct vdec_s *vdec = hw_to_vdec(hw);
5091 int canvas_w = ALIGN(pic_config->y_crop_width, 64)/4;
5092 int canvas_h = ALIGN(pic_config->y_crop_height, 32)/4;
5093 int blkmode = mem_map_mode;
5094 /*CANVAS_BLKMODE_64X32*/
5095 if (pic_config->double_write_mode) {
5096 canvas_w = pic_config->y_crop_width /
5097 get_double_write_ratio(hw,
5098 pic_config->double_write_mode);
5099 canvas_h = pic_config->y_crop_height /
5100 get_double_write_ratio(hw,
5101 pic_config->double_write_mode);
5102
5103 if (mem_map_mode == 0)
5104 canvas_w = ALIGN(canvas_w, 32);
5105 else
5106 canvas_w = ALIGN(canvas_w, 64);
5107 canvas_h = ALIGN(canvas_h, 32);
5108
5109 if (vdec->parallel_dec == 1) {
5110 if (pic_config->y_canvas_index == -1)
5111 pic_config->y_canvas_index =
5112 vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
5113 if (pic_config->uv_canvas_index == -1)
5114 pic_config->uv_canvas_index =
5115 vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
5116 } else {
5117 pic_config->y_canvas_index = 128 + pic_config->index * 2;
5118 pic_config->uv_canvas_index = 128 + pic_config->index * 2 + 1;
5119 }
5120
5121 canvas_config_ex(pic_config->y_canvas_index,
5122 pic_config->dw_y_adr, canvas_w, canvas_h,
5123 CANVAS_ADDR_NOWRAP, blkmode, 0x7);
5124 canvas_config_ex(pic_config->uv_canvas_index,
5125 pic_config->dw_u_v_adr, canvas_w, canvas_h,
5126 CANVAS_ADDR_NOWRAP, blkmode, 0x7);
5127
5128#ifdef MULTI_INSTANCE_SUPPORT
5129 pic_config->canvas_config[0].phy_addr =
5130 pic_config->dw_y_adr;
5131 pic_config->canvas_config[0].width =
5132 canvas_w;
5133 pic_config->canvas_config[0].height =
5134 canvas_h;
5135 pic_config->canvas_config[0].block_mode =
5136 blkmode;
5137 pic_config->canvas_config[0].endian = 7;
5138
5139 pic_config->canvas_config[1].phy_addr =
5140 pic_config->dw_u_v_adr;
5141 pic_config->canvas_config[1].width =
5142 canvas_w;
5143 pic_config->canvas_config[1].height =
5144 canvas_h;
5145 pic_config->canvas_config[1].block_mode =
5146 blkmode;
5147 pic_config->canvas_config[1].endian = 7;
5148#endif
5149 }
5150}
5151
5152static void set_frame_info(struct AV1HW_s *hw, struct vframe_s *vf)
5153{
5154 unsigned int ar;
5155 vf->duration = hw->frame_dur;
5156 vf->duration_pulldown = 0;
5157 vf->flag = 0;
5158 vf->prop.master_display_colour = hw->vf_dp;
5159 vf->signal_type = hw->video_signal_type;
5160 if (vf->compWidth && vf->compHeight)
5161 hw->frame_ar = vf->compHeight * 0x100 / vf->compWidth;
5162 ar = min_t(u32, hw->frame_ar, DISP_RATIO_ASPECT_RATIO_MAX);
5163 vf->ratio_control = (ar << DISP_RATIO_ASPECT_RATIO_BIT);
5164
5165}
5166
5167static int vav1_vf_states(struct vframe_states *states, void *op_arg)
5168{
5169 struct AV1HW_s *hw = (struct AV1HW_s *)op_arg;
5170
5171 states->vf_pool_size = VF_POOL_SIZE;
5172 states->buf_free_num = kfifo_len(&hw->newframe_q);
5173 states->buf_avail_num = kfifo_len(&hw->display_q);
5174
5175 if (step == 2)
5176 states->buf_avail_num = 0;
5177 return 0;
5178}
5179
5180static struct vframe_s *vav1_vf_peek(void *op_arg)
5181{
5182 struct vframe_s *vf[2] = {0, 0};
5183 struct AV1HW_s *hw = (struct AV1HW_s *)op_arg;
5184
5185 if (step == 2)
5186 return NULL;
5187
5188 if (kfifo_out_peek(&hw->display_q, (void *)&vf, 2)) {
5189 if (vf[1]) {
5190 vf[0]->next_vf_pts_valid = true;
5191 vf[0]->next_vf_pts = vf[1]->pts;
5192 } else
5193 vf[0]->next_vf_pts_valid = false;
5194 return vf[0];
5195 }
5196
5197 return NULL;
5198}
5199
5200static struct vframe_s *vav1_vf_get(void *op_arg)
5201{
5202 struct vframe_s *vf;
5203 struct AV1HW_s *hw = (struct AV1HW_s *)op_arg;
5204
5205 if (step == 2)
5206 return NULL;
5207 else if (step == 1)
5208 step = 2;
5209
5210 if (kfifo_get(&hw->display_q, &vf)) {
5211 struct vframe_s *next_vf;
5212 uint8_t index = vf->index & 0xff;
5213 if (index < hw->used_buf_num) {
5214 hw->vf_get_count++;
5215 if (debug & AOM_DEBUG_VFRAME) {
5216 struct BufferPool_s *pool = hw->pbi->common.buffer_pool;
5217 struct PIC_BUFFER_CONFIG_s *pic =
5218 &pool->frame_bufs[index].buf;
5219 unsigned long flags;
5220 lock_buffer_pool(hw->pbi->common.buffer_pool, flags);
5221 av1_print(hw, AOM_DEBUG_VFRAME, "%s index 0x%x type 0x%x w/h %d/%d, aux size %d, pts %d, %lld\n",
5222 __func__, vf->index, vf->type,
5223 vf->width, vf->height,
5224 pic->aux_data_size,
5225 vf->pts,
5226 vf->pts_us64);
5227 unlock_buffer_pool(hw->pbi->common.buffer_pool, flags);
5228 }
5229
5230 if (kfifo_peek(&hw->display_q, &next_vf)) {
5231 vf->next_vf_pts_valid = true;
5232 vf->next_vf_pts = next_vf->pts;
5233 } else
5234 vf->next_vf_pts_valid = false;
5235#ifdef DUMP_FILMGRAIN
5236 if (index == fg_dump_index) {
5237 unsigned long flags;
5238 int ii;
5239 lock_buffer_pool(hw->pbi->common.buffer_pool, flags);
5240 pr_info("FGS_TABLE for buffer %d:\n", index);
5241 for (ii = 0; ii < FGS_TABLE_SIZE; ii++) {
5242 pr_info("%02x ", hw->fg_ptr[ii]);
5243 if (((ii+ 1) & 0xf) == 0)
5244 pr_info("\n");
5245 }
5246 unlock_buffer_pool(hw->pbi->common.buffer_pool, flags);
5247 }
5248#endif
5249
5250 return vf;
5251 }
5252 }
5253 return NULL;
5254}
5255
5256static void vav1_vf_put(struct vframe_s *vf, void *op_arg)
5257{
5258 struct AV1HW_s *hw = (struct AV1HW_s *)op_arg;
5259 uint8_t index = vf->index & 0xff;
5260 unsigned long flags;
5261
5262 if ((vf == NULL) || (hw == NULL))
5263 return;
5264
5265 kfifo_put(&hw->newframe_q, (const struct vframe_s *)vf);
5266 hw->vf_put_count++;
5267 if (debug & AOM_DEBUG_VFRAME) {
5268 lock_buffer_pool(hw->pbi->common.buffer_pool, flags);
5269 av1_print(hw, AOM_DEBUG_VFRAME, "%s index 0x%x type 0x%x w/h %d/%d, pts %d, %lld\n",
5270 __func__, vf->index, vf->type,
5271 vf->width, vf->height,
5272 vf->pts,
5273 vf->pts_us64);
5274 unlock_buffer_pool(hw->pbi->common.buffer_pool, flags);
5275 }
5276
5277 if (index < hw->used_buf_num) {
5278 struct AV1_Common_s *cm = &hw->pbi->common;
5279 struct BufferPool_s *pool = cm->buffer_pool;
5280
5281 lock_buffer_pool(hw->pbi->common.buffer_pool, flags);
5282 if ((debug & AV1_DEBUG_IGNORE_VF_REF) == 0) {
5283 if (pool->frame_bufs[index].buf.vf_ref > 0)
5284 pool->frame_bufs[index].buf.vf_ref--;
5285 }
5286 if (hw->wait_buf)
5287 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG,
5288 0x1);
5289 hw->last_put_idx = index;
5290 hw->new_frame_displayed++;
5291 unlock_buffer_pool(hw->pbi->common.buffer_pool, flags);
5292 }
5293
5294}
5295
5296static int vav1_event_cb(int type, void *data, void *op_arg)
5297{
5298 unsigned long flags;
5299 struct AV1HW_s *hw = (struct AV1HW_s *)op_arg;
5300 struct AV1_Common_s *cm = &hw->pbi->common;
5301 struct BufferPool_s *pool = cm->buffer_pool;
5302
5303 if (type & VFRAME_EVENT_RECEIVER_RESET) {
5304#if 0
5305 unsigned long flags;
5306
5307 amhevc_stop();
5308#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
5309 vf_light_unreg_provider(&vav1_vf_prov);
5310#endif
5311 spin_lock_irqsave(&hw->lock, flags);
5312 vav1_local_init();
5313 vav1_prot_init();
5314 spin_unlock_irqrestore(&hw->lock, flags);
5315#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
5316 vf_reg_provider(&vav1_vf_prov);
5317#endif
5318 amhevc_start();
5319#endif
5320 } else if (type & VFRAME_EVENT_RECEIVER_GET_AUX_DATA) {
5321 struct provider_aux_req_s *req =
5322 (struct provider_aux_req_s *)data;
5323 unsigned char index;
5324
5325 lock_buffer_pool(hw->pbi->common.buffer_pool, flags);
5326 index = req->vf->index & 0xff;
5327 req->aux_buf = NULL;
5328 req->aux_size = 0;
5329 if (req->bot_flag)
5330 index = (req->vf->index >> 8) & 0xff;
5331 if (index != 0xff
5332 && index < hw->used_buf_num) {
5333 struct PIC_BUFFER_CONFIG_s *pic_config =
5334 &pool->frame_bufs[index].buf;
5335 req->aux_buf = pic_config->aux_data_buf;
5336 req->aux_size = pic_config->aux_data_size;
5337#if 0
5338//def CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5339 if (hw->bypass_dvenl && !dolby_meta_with_el)
5340 req->dv_enhance_exist = false;
5341 else
5342 req->dv_enhance_exist =
5343 pic_config->dv_enhance_exist;
5344 av1_print(hw, AOM_DEBUG_VFRAME,
5345 "query dv_enhance_exist for pic (vf 0x%p, poc %d index %d) flag => %d, aux sizd 0x%x\n",
5346 req->vf,
5347 pic_config->POC, index,
5348 req->dv_enhance_exist, req->aux_size);
5349#else
5350 req->dv_enhance_exist = 0;
5351#endif
5352 }
5353 unlock_buffer_pool(hw->pbi->common.buffer_pool, flags);
5354
5355 if (debug & AOM_DEBUG_AUX_DATA)
5356 av1_print(hw, 0,
5357 "%s(type 0x%x vf index 0x%x)=>size 0x%x\n",
5358 __func__, type, index, req->aux_size);
5359#if 0
5360//def CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5361 } else if (type & VFRAME_EVENT_RECEIVER_DOLBY_BYPASS_EL) {
5362 if ((force_bypass_dvenl & 0x80000000) == 0) {
5363 av1_print(hw, 0,
5364 "%s: VFRAME_EVENT_RECEIVER_DOLBY_BYPASS_EL\n",
5365 __func__);
5366 hw->bypass_dvenl_enable = 1;
5367 }
5368
5369#endif
5370 }
5371 return 0;
5372}
5373
5374void av1_inc_vf_ref(struct AV1HW_s *hw, int index)
5375{
5376 struct AV1_Common_s *cm = &hw->pbi->common;
5377
5378 if ((debug & AV1_DEBUG_IGNORE_VF_REF) == 0) {
5379 cm->buffer_pool->frame_bufs[index].buf.vf_ref++;
5380
5381 av1_print(hw, AV1_DEBUG_BUFMGR_MORE, "%s index = %d new vf_ref = %d\r\n",
5382 __func__, index,
5383 cm->buffer_pool->frame_bufs[index].buf.vf_ref);
5384 }
5385}
5386
5387static int frame_duration_adapt(struct AV1HW_s *hw, struct vframe_s *vf, u32 valid)
5388{
5389 u32 old_duration, pts_duration = 0;
5390 u32 pts = vf->pts;
5391
5392 if (hw->get_frame_dur == true)
5393 return true;
5394
5395 hw->frame_cnt_window++;
5396 if (!(hw->av1_first_pts_ready == 1)) {
5397 if (valid) {
5398 hw->pts1 = pts;
5399 hw->frame_cnt_window = 0;
5400 hw->duration_from_pts_done = 0;
5401 hw->av1_first_pts_ready = 1;
5402 } else {
5403 return false;
5404 }
5405 } else {
5406 if (pts < hw->pts1) {
5407 if (hw->frame_cnt_window > FRAME_CNT_WINDOW_SIZE) {
5408 hw->pts1 = pts;
5409 hw->frame_cnt_window = 0;
5410 }
5411 }
5412
5413 if (valid && (hw->frame_cnt_window > FRAME_CNT_WINDOW_SIZE) &&
5414 (pts > hw->pts1) && (hw->duration_from_pts_done == 0)) {
5415 old_duration = hw->frame_dur;
5416 hw->pts2 = pts;
5417 pts_duration = (((hw->pts2 - hw->pts1) * 16) /
5418 (hw->frame_cnt_window * 15));
5419
5420 if (close_to(pts_duration, old_duration, 2000)) {
5421 hw->frame_dur = pts_duration;
5422 av1_print(hw, AV1_DEBUG_OUT_PTS,
5423 "use calc duration %d\n", pts_duration);
5424 }
5425
5426 if (hw->duration_from_pts_done == 0) {
5427 if (close_to(pts_duration, old_duration, RATE_CORRECTION_THRESHOLD)) {
5428 hw->duration_from_pts_done = 1;
5429 } else {
5430 if (!close_to(pts_duration,
5431 old_duration, 1000) &&
5432 !close_to(pts_duration,
5433 hw->frame_dur, 1000) &&
5434 close_to(pts_duration,
5435 hw->last_duration, 200)) {
5436 /* frame_dur must
5437 * wrong,recover it.
5438 */
5439 hw->frame_dur = pts_duration;
5440 }
5441 hw->pts1 = hw->pts2;
5442 hw->frame_cnt_window = 0;
5443 hw->duration_from_pts_done = 0;
5444 }
5445 }
5446 hw->last_duration = pts_duration;
5447 }
5448 }
5449 return true;
5450}
5451
5452static void update_vf_memhandle(struct AV1HW_s *hw,
5453 struct vframe_s *vf, struct PIC_BUFFER_CONFIG_s *pic)
5454{
5455 if (pic->index < 0) {
5456 vf->mem_handle = NULL;
5457 vf->mem_head_handle = NULL;
5458 } else if (vf->type & VIDTYPE_SCATTER) {
5459#ifdef AOM_AV1_MMU_DW
5460 if (pic->double_write_mode & 0x20 &&
5461 (debug & AOM_DEBUG_DW_DISP_MAIN) == 0) {
5462 vf->mem_handle =
5463 decoder_mmu_box_get_mem_handle(
5464 hw->mmu_box_dw, pic->index);
5465 vf->mem_head_handle =
5466 decoder_bmmu_box_get_mem_handle(
5467 hw->bmmu_box,
5468 DW_HEADER_BUFFER_IDX(pic->BUF_index));
5469 } else
5470#endif
5471 {
5472 vf->mem_handle =
5473 decoder_mmu_box_get_mem_handle(
5474 hw->mmu_box, pic->index);
5475 vf->mem_head_handle =
5476 decoder_bmmu_box_get_mem_handle(
5477 hw->bmmu_box,
5478 HEADER_BUFFER_IDX(pic->BUF_index));
5479 }
5480#ifdef USE_SPEC_BUF_FOR_MMU_HEAD
5481 vf->mem_head_handle = NULL;
5482#endif
5483 } else {
5484 vf->mem_handle =
5485 decoder_bmmu_box_get_mem_handle(
5486 hw->bmmu_box, VF_BUFFER_IDX(pic->BUF_index));
5487 vf->mem_head_handle = NULL;
5488 /*vf->mem_head_handle =
5489 *decoder_bmmu_box_get_mem_handle(
5490 *hw->bmmu_box, VF_BUFFER_IDX(BUF_index));
5491 */
5492 }
5493}
5494
5495static int prepare_display_buf(struct AV1HW_s *hw,
5496 struct PIC_BUFFER_CONFIG_s *pic_config)
5497{
5498 struct vframe_s *vf = NULL;
5499 int stream_offset = pic_config->stream_offset;
5500 unsigned short slice_type = pic_config->slice_type;
5501 u32 pts_valid = 0, pts_us64_valid = 0;
5502 u32 pts_save;
5503 u64 pts_us64_save;
5504 u32 frame_size;
5505 int i;
5506
5507 av1_print(hw, AOM_DEBUG_VFRAME, "%s index = %d\r\n", __func__, pic_config->index);
5508 if (kfifo_get(&hw->newframe_q, &vf) == 0) {
5509 av1_print(hw, 0, "fatal error, no available buffer slot.");
5510 return -1;
5511 }
5512
5513 if (pic_config->double_write_mode &&
5514 (pic_config->double_write_mode & 0x20) == 0)
5515 set_canvas(hw, pic_config);
5516
5517 display_frame_count[hw->index]++;
5518 if (vf) {
5519 if (!force_pts_unstable) {
5520 if ((pic_config->pts == 0) || (pic_config->pts <= hw->last_pts)) {
5521 for (i = (FRAME_BUFFERS - 1); i > 0; i--) {
5522 if ((hw->last_pts == hw->frame_mode_pts_save[i]) ||
5523 (hw->last_pts_us64 == hw->frame_mode_pts64_save[i])) {
5524 pic_config->pts = hw->frame_mode_pts_save[i - 1];
5525 pic_config->pts64 = hw->frame_mode_pts64_save[i - 1];
5526 break;
5527 }
5528 }
5529 if ((i == 0) || (pic_config->pts <= hw->last_pts)) {
5530 av1_print(hw, AV1_DEBUG_OUT_PTS,
5531 "no found pts %d, set 0. %d, %d\n",
5532 i, pic_config->pts, hw->last_pts);
5533 pic_config->pts = 0;
5534 pic_config->pts64 = 0;
5535 }
5536 }
5537 }
5538 if (hw->is_used_v4l) {
5539 vf->v4l_mem_handle
5540 = hw->m_BUF[pic_config->BUF_index].v4l_ref_buf_addr;
5541 av1_print(hw, PRINT_FLAG_V4L_DETAIL,
5542 "[%d] %s(), v4l mem handle: 0x%lx\n",
5543 ((struct aml_vcodec_ctx *)(hw->v4l2_ctx))->id,
5544 __func__, vf->v4l_mem_handle);
5545 }
5546
5547#ifdef MULTI_INSTANCE_SUPPORT
5548 if (vdec_frame_based(hw_to_vdec(hw))) {
5549 vf->pts = pic_config->pts;
5550 vf->pts_us64 = pic_config->pts64;
5551 if (vf->pts != 0 || vf->pts_us64 != 0) {
5552 pts_valid = 1;
5553 pts_us64_valid = 1;
5554 } else {
5555 pts_valid = 0;
5556 pts_us64_valid = 0;
5557 }
5558 } else
5559#endif
5560 /* if (pts_lookup_offset(PTS_TYPE_VIDEO,
5561 * stream_offset, &vf->pts, 0) != 0) {
5562 */
5563 if (pts_lookup_offset_us64
5564 (PTS_TYPE_VIDEO, stream_offset, &vf->pts,
5565 &frame_size, 0,
5566 &vf->pts_us64) != 0) {
5567#ifdef DEBUG_PTS
5568 hw->pts_missed++;
5569#endif
5570 vf->pts = 0;
5571 vf->pts_us64 = 0;
5572 pts_valid = 0;
5573 pts_us64_valid = 0;
5574 } else {
5575#ifdef DEBUG_PTS
5576 hw->pts_hit++;
5577#endif
5578 pts_valid = 1;
5579 pts_us64_valid = 1;
5580 }
5581 /*
5582 if (vdec_frame_based(hw_to_vdec(hw)) && (!hw->get_frame_dur) && hw->last_lookup_pts_us64 && hw->last_pts
5583 && ((vf->pts_us64 > hw->last_lookup_pts_us64) ||(vf->pts > hw->last_pts) )) {
5584 if (vf->pts > hw->last_pts)
5585 hw->frame_dur = PTS2DUR(vf->pts -hw->last_pts);
5586 av1_print(hw, 0,
5587 "AV1 frame mode dur=%d,pts(%d,%lld) last pts(%d,%lld)\n",
5588 hw->frame_dur, vf->pts,
5589 vf->pts_us64, hw->last_pts, hw->last_lookup_pts_us64);
5590 hw->get_frame_dur = true;
5591 hw->pts_mode = PTS_NONE_REF_USE_DURATION;
5592 hw->duration_from_pts_done = 1;
5593 }
5594 */
5595 fill_frame_info(hw, pic_config, frame_size, vf->pts);
5596
5597 pts_save = vf->pts;
5598 pts_us64_save = vf->pts_us64;
5599 if (hw->pts_unstable) {
5600 frame_duration_adapt(hw, vf, pts_valid);
5601 if (hw->duration_from_pts_done) {
5602 hw->pts_mode = PTS_NONE_REF_USE_DURATION;
5603 } else {
5604 if (pts_valid || pts_us64_valid)
5605 hw->pts_mode = PTS_NORMAL;
5606 }
5607 }
5608
5609 if ((hw->pts_mode == PTS_NORMAL) && (vf->pts != 0)
5610 && hw->get_frame_dur) {
5611 int pts_diff = (int)vf->pts - hw->last_lookup_pts;
5612
5613 if (pts_diff < 0) {
5614 hw->pts_mode_switching_count++;
5615 hw->pts_mode_recovery_count = 0;
5616
5617 if (hw->pts_mode_switching_count >=
5618 PTS_MODE_SWITCHING_THRESHOLD) {
5619 hw->pts_mode =
5620 PTS_NONE_REF_USE_DURATION;
5621 pr_info
5622 ("HEVC: switch to n_d mode.\n");
5623 }
5624
5625 } else {
5626 int p = PTS_MODE_SWITCHING_RECOVERY_THREASHOLD;
5627
5628 hw->pts_mode_recovery_count++;
5629 if (hw->pts_mode_recovery_count > p) {
5630 hw->pts_mode_switching_count = 0;
5631 hw->pts_mode_recovery_count = 0;
5632 }
5633 }
5634 }
5635
5636 if (vf->pts != 0)
5637 hw->last_lookup_pts = vf->pts;
5638
5639 if ((hw->pts_mode == PTS_NONE_REF_USE_DURATION)
5640 && (slice_type != KEY_FRAME))
5641 vf->pts = hw->last_pts + DUR2PTS(hw->frame_dur);
5642 hw->last_pts = vf->pts;
5643
5644 if (vf->pts_us64 != 0)
5645 hw->last_lookup_pts_us64 = vf->pts_us64;
5646
5647 if ((hw->pts_mode == PTS_NONE_REF_USE_DURATION)
5648 && (slice_type != KEY_FRAME)) {
5649 vf->pts_us64 =
5650 hw->last_pts_us64 +
5651 (DUR2PTS(hw->frame_dur) * 100 / 9);
5652 }
5653 hw->last_pts_us64 = vf->pts_us64;
5654
5655 av1_print(hw, AV1_DEBUG_OUT_PTS,
5656 "AV1 dec out slice_type %d pts: pts_mode=%d,dur=%d,pts(%d, %lld)(%d, %lld)\n",
5657 slice_type, hw->pts_mode, hw->frame_dur, vf->pts,
5658 vf->pts_us64, pts_save, pts_us64_save);
5659
5660
5661 if (hw->pts_mode == PTS_NONE_REF_USE_DURATION) {
5662 vf->disp_pts = vf->pts;
5663 vf->disp_pts_us64 = vf->pts_us64;
5664 vf->pts = pts_save;
5665 vf->pts_us64 = pts_us64_save;
5666 } else {
5667 vf->disp_pts = 0;
5668 vf->disp_pts_us64 = 0;
5669 }
5670
5671 vf->index = 0xff00 | pic_config->index;
5672
5673 if (pic_config->double_write_mode & 0x10) {
5674 /* double write only */
5675 vf->compBodyAddr = 0;
5676 vf->compHeadAddr = 0;
5677#ifdef AOM_AV1_MMU_DW
5678 vf->dwBodyAddr = 0;
5679 vf->dwHeadAddr = 0;
5680#endif
5681 } else {
5682 if (hw->mmu_enable) {
5683 vf->compBodyAddr = 0;
5684 vf->compHeadAddr = pic_config->header_adr;
5685 vf->fgs_table_adr = pic_config->fgs_table_adr;
5686 vf->fgs_valid = hw->fgs_valid;
5687#ifdef AOM_AV1_MMU_DW
5688 vf->dwBodyAddr = 0;
5689 vf->dwHeadAddr = 0;
5690 if (pic_config->double_write_mode & 0x20) {
5691 u32 mode = pic_config->double_write_mode & 0xf;
5692 if (mode == 5 || mode == 3)
5693 vf->dwHeadAddr = pic_config->header_dw_adr;
5694 else if ((mode == 1 || mode == 2 || mode == 4)
5695 && (debug & AOM_DEBUG_DW_DISP_MAIN) == 0) {
5696 vf->compHeadAddr = pic_config->header_dw_adr;
5697 vf->fgs_valid = 0;
5698 av1_print(hw, AOM_DEBUG_VFRAME,
5699 "Use dw mmu for display\n");
5700 }
5701 }
5702#endif
5703 } else {
5704 /*vf->compBodyAddr = pic_config->mc_y_adr;
5705 *vf->compHeadAddr = pic_config->mc_y_adr +
5706 *pic_config->comp_body_size; */
5707 /*head adr*/
5708 }
5709 vf->canvas0Addr = vf->canvas1Addr = 0;
5710 }
5711 if (pic_config->double_write_mode &&
5712 (pic_config->double_write_mode & 0x20) == 0) {
5713 vf->type = VIDTYPE_PROGRESSIVE |
5714 VIDTYPE_VIU_FIELD;
5715 vf->type |= VIDTYPE_VIU_NV21;
5716 if ((pic_config->double_write_mode == 3 ||
5717 pic_config->double_write_mode == 5) &&
5718 (!IS_8K_SIZE(pic_config->y_crop_width,
5719 pic_config->y_crop_height))) {
5720 vf->type |= VIDTYPE_COMPRESS;
5721 if (hw->mmu_enable)
5722 vf->type |= VIDTYPE_SCATTER;
5723 }
5724#ifdef MULTI_INSTANCE_SUPPORT
5725 if (hw->m_ins_flag) {
5726 vf->canvas0Addr = vf->canvas1Addr = -1;
5727 vf->plane_num = 2;
5728 vf->canvas0_config[0] =
5729 pic_config->canvas_config[0];
5730 vf->canvas0_config[1] =
5731 pic_config->canvas_config[1];
5732 vf->canvas1_config[0] =
5733 pic_config->canvas_config[0];
5734 vf->canvas1_config[1] =
5735 pic_config->canvas_config[1];
5736
5737 } else
5738#endif
5739 vf->canvas0Addr = vf->canvas1Addr =
5740 spec2canvas(pic_config);
5741 } else {
5742 vf->canvas0Addr = vf->canvas1Addr = 0;
5743 vf->type = VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
5744 if (hw->mmu_enable)
5745 vf->type |= VIDTYPE_SCATTER;
5746 }
5747
5748 switch (pic_config->bit_depth) {
5749 case AOM_BITS_8:
5750 vf->bitdepth = BITDEPTH_Y8 |
5751 BITDEPTH_U8 | BITDEPTH_V8;
5752 break;
5753 case AOM_BITS_10:
5754 case AOM_BITS_12:
5755 vf->bitdepth = BITDEPTH_Y10 |
5756 BITDEPTH_U10 | BITDEPTH_V10;
5757 break;
5758 default:
5759 vf->bitdepth = BITDEPTH_Y10 |
5760 BITDEPTH_U10 | BITDEPTH_V10;
5761 break;
5762 }
5763 if ((vf->type & VIDTYPE_COMPRESS) == 0)
5764 vf->bitdepth =
5765 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
5766 if (pic_config->bit_depth == AOM_BITS_8)
5767 vf->bitdepth |= BITDEPTH_SAVING_MODE;
5768
5769 /* if ((vf->width!=pic_config->width)|
5770 * (vf->height!=pic_config->height))
5771 */
5772 /* pr_info("aaa: %d/%d, %d/%d\n",
5773 vf->width,vf->height, pic_config->width,
5774 pic_config->height); */
5775 vf->width = pic_config->y_crop_width /
5776 get_double_write_ratio(hw,
5777 pic_config->double_write_mode);
5778 vf->height = pic_config->y_crop_height /
5779 get_double_write_ratio(hw,
5780 pic_config->double_write_mode);
5781 if (force_w_h != 0) {
5782 vf->width = (force_w_h >> 16) & 0xffff;
5783 vf->height = force_w_h & 0xffff;
5784 }
5785 if ((pic_config->double_write_mode & 0x20) &&
5786 ((pic_config->double_write_mode & 0xf) == 2 ||
5787 (pic_config->double_write_mode & 0xf) == 4)) {
5788 vf->compWidth = pic_config->y_crop_width /
5789 get_double_write_ratio(hw,
5790 pic_config->double_write_mode);
5791 vf->compHeight = pic_config->y_crop_height /
5792 get_double_write_ratio(hw,
5793 pic_config->double_write_mode);
5794 } else {
5795 vf->compWidth = pic_config->y_crop_width;
5796 vf->compHeight = pic_config->y_crop_height;
5797 }
5798 set_frame_info(hw, vf);
5799 if (force_fps & 0x100) {
5800 u32 rate = force_fps & 0xff;
5801
5802 if (rate)
5803 vf->duration = 96000/rate;
5804 else
5805 vf->duration = 0;
5806 }
5807 update_vf_memhandle(hw, vf, pic_config);
5808 if (!(pic_config->y_crop_width == 196
5809 && pic_config->y_crop_height == 196
5810 && (debug & AV1_DEBUG_NO_TRIGGER_FRAME) == 0
5811 && (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX))) {
5812 av1_inc_vf_ref(hw, pic_config->index);
5813 decoder_do_frame_check(hw_to_vdec(hw), vf);
5814 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
5815 ATRACE_COUNTER(MODULE_NAME, vf->pts);
5816 hw->vf_pre_count++;
5817#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
5818 /*count info*/
5819 gvs->frame_dur = hw->frame_dur;
5820 vdec_count_info(gvs, 0, stream_offset);
5821#endif
5822 hw_to_vdec(hw)->vdec_fps_detec(hw_to_vdec(hw)->id);
5823 if (without_display_mode == 0) {
5824 vf_notify_receiver(hw->provider_name,
5825 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
5826 } else
5827 vav1_vf_put(vav1_vf_get(hw), hw);
5828 } else {
5829 hw->stat |= AV1_TRIGGER_FRAME_DONE;
5830 hevc_source_changed(VFORMAT_AV1, 196, 196, 30);
5831 pr_debug("[%s %d] drop trigger frame width %d height %d state 0x%x\n",
5832 __func__, __LINE__, vf->width,
5833 vf->height, hw->stat);
5834 }
5835 }
5836
5837 return 0;
5838}
5839
5840void av1_raw_write_image(AV1Decoder *pbi, PIC_BUFFER_CONFIG *sd)
5841{
5842 sd->stream_offset = pbi->pre_stream_offset;
5843 prepare_display_buf((struct AV1HW_s *)(pbi->private_data), sd);
5844 pbi->pre_stream_offset = READ_VREG(HEVC_SHIFT_BYTE_COUNT);
5845}
5846
5847static int notify_v4l_eos(struct vdec_s *vdec)
5848{
5849 struct AV1HW_s *hw = (struct AV1HW_s *)vdec->private;
5850 struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
5851 struct vframe_s *vf = NULL;
5852 struct vdec_fb *fb = NULL;
5853
5854 if (hw->is_used_v4l && hw->eos) {
5855 if (kfifo_get(&hw->newframe_q, &vf) == 0 || vf == NULL) {
5856 av1_print(hw, 0,
5857 "%s fatal error, no available buffer slot.\n",
5858 __func__);
5859 return -1;
5860 }
5861
5862 if (v4l_get_fb(hw->v4l2_ctx, &fb)) {
5863 pr_err("[%d] get fb fail.\n", ctx->id);
5864 return -1;
5865 }
5866
5867 vf->timestamp = ULONG_MAX;
5868 vf->v4l_mem_handle = (unsigned long)fb;
5869 vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L;
5870
5871 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
5872 vf_notify_receiver(vdec->vf_provider_name,
5873 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
5874
5875 av1_print(hw, AOM_DEBUG_HW_MORE, "[%d] AV1 EOS notify.\n", ctx->id);
5876 }
5877
5878 return 0;
5879}
5880
5881static void get_rpm_param(union param_u *params)
5882{
5883 int i;
5884 unsigned int data32;
5885
5886 if (debug & AV1_DEBUG_BUFMGR)
5887 pr_info("enter %s\r\n", __func__);
5888 for (i = 0; i < 128; i++) {
5889 do {
5890 data32 = READ_VREG(RPM_CMD_REG);
5891 /*pr_info("%x\n", data32);*/
5892 } while ((data32 & 0x10000) == 0);
5893 params->l.data[i] = data32&0xffff;
5894 /*pr_info("%x\n", data32);*/
5895 WRITE_VREG(RPM_CMD_REG, 0);
5896 }
5897 if (debug & AV1_DEBUG_BUFMGR)
5898 pr_info("leave %s\r\n", __func__);
5899}
5900
5901static void av1_recycle_mmu_buf_tail(struct AV1HW_s *hw)
5902{
5903#ifdef CHANGE_REMOVED
5904 struct AV1_Common_s *const cm = &hw->pbi->common;
5905 if (hw->double_write_mode & 0x10)
5906 return;
5907 if (cm->cur_fb_idx_mmu != INVALID_IDX) {
5908 if (hw->used_4k_num == -1) {
5909 hw->used_4k_num =
5910 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
5911 if (hw->m_ins_flag)
5912 hevc_mmu_dma_check(hw_to_vdec(hw));
5913 }
5914 decoder_mmu_box_free_idx_tail(hw->mmu_box,
5915 cm->cur_fb_idx_mmu, hw->used_4k_num);
5916 cm->cur_fb_idx_mmu = INVALID_IDX;
5917 hw->used_4k_num = -1;
5918 }
5919#endif
5920}
5921
5922#ifdef MULTI_INSTANCE_SUPPORT
5923static void av1_recycle_mmu_buf(struct AV1HW_s *hw)
5924{
5925#ifdef CHANGE_REMOVED
5926 struct AV1_Common_s *const cm = &hw->pbi->common;
5927 if (hw->double_write_mode & 0x10)
5928 return;
5929 if (cm->cur_fb_idx_mmu != INVALID_IDX) {
5930 decoder_mmu_box_free_idx(hw->mmu_box,
5931 cm->cur_fb_idx_mmu);
5932
5933 cm->cur_fb_idx_mmu = INVALID_IDX;
5934 hw->used_4k_num = -1;
5935 }
5936#endif
5937}
5938#endif
5939
5940
5941static void dec_again_process(struct AV1HW_s *hw)
5942{
5943 amhevc_stop();
5944 hw->dec_result = DEC_RESULT_AGAIN;
5945 if (hw->process_state ==
5946 PROC_STATE_DECODESLICE) {
5947 hw->process_state =
5948 PROC_STATE_SENDAGAIN;
5949 if (hw->mmu_enable)
5950 av1_recycle_mmu_buf(hw);
5951 }
5952 reset_process_time(hw);
5953 vdec_schedule_work(&hw->work);
5954}
5955
5956static void read_film_grain_reg(struct AV1HW_s *hw)
5957{
5958 AV1_COMMON *cm = &hw->pbi->common;
5959 int i;
5960 if (cm->cur_frame == NULL) {
5961 av1_print(hw, AOM_DEBUG_HW_MORE, "%s, cur_frame not exist!!!\n", __func__);
5962 return;
5963 } else
5964 av1_print(hw, AOM_DEBUG_HW_MORE, "%s\n", __func__);
5965 WRITE_VREG(HEVC_FGS_IDX, 0);
5966 for (i = 0; i < FILM_GRAIN_REG_SIZE; i++) {
5967 cm->cur_frame->film_grain_reg[i] = READ_VREG(HEVC_FGS_DATA);
5968 }
5969 cm->cur_frame->film_grain_reg_valid = 1;
5970}
5971
5972static void config_film_grain_reg(struct AV1HW_s *hw, int film_grain_params_ref_idx)
5973{
5974
5975 AV1_COMMON *cm = &hw->pbi->common;
5976 int i;
5977 unsigned char found = 0;
5978 RefCntBuffer *buf;
5979 av1_print(hw, AOM_DEBUG_HW_MORE,
5980 " ## %s frome reference idx %d\n",
5981 __func__, film_grain_params_ref_idx);
5982 for (i = 0; i < INTER_REFS_PER_FRAME; ++i) {
5983 if (film_grain_params_ref_idx == cm->remapped_ref_idx[i]) {
5984 found = 1;
5985 break;
5986 }
5987 }
5988 if (!found) {
5989 av1_print(hw, AOM_DEBUG_HW_MORE,
5990 "%s Error, Invalid film grain reference idx %d\n",
5991 __func__, film_grain_params_ref_idx);
5992 return;
5993 }
5994 buf = cm->ref_frame_map[film_grain_params_ref_idx];
5995
5996 if (buf->film_grain_reg_valid == 0) {
5997 av1_print(hw, AOM_DEBUG_HW_MORE,
5998 "%s Error, film grain register data invalid for reference idx %d\n",
5999 __func__, film_grain_params_ref_idx);
6000 return;
6001 }
6002
6003 if (cm->cur_frame == NULL) {
6004 av1_print(hw, AOM_DEBUG_HW_MORE,
6005 "%s, cur_frame not exist!!!\n", __func__);
6006 }
6007 WRITE_VREG(HEVC_FGS_IDX, 0);
6008 for (i = 0; i < FILM_GRAIN_REG_SIZE; i++) {
6009 WRITE_VREG(HEVC_FGS_DATA, buf->film_grain_reg[i]);
6010 if (cm->cur_frame)
6011 cm->cur_frame->film_grain_reg[i] = buf->film_grain_reg[i];
6012 }
6013 if (cm->cur_frame)
6014 cm->cur_frame->film_grain_reg_valid = 1;
6015 WRITE_VREG(HEVC_FGS_CTRL, READ_VREG(HEVC_FGS_CTRL) | 1); // set fil_grain_start
6016}
6017
6018
6019void config_next_ref_info_hw(struct AV1HW_s *hw)
6020{
6021 int j;
6022 AV1_COMMON *const cm = &hw->pbi->common;
6023 av1_set_next_ref_frame_map(hw->pbi);
6024 WRITE_VREG(HEVC_PARSER_MEM_WR_ADDR, 0x1000);
6025 for (j = 0; j < 12; j++) {
6026 unsigned int info =
6027 av1_get_next_used_ref_info(cm, j);
6028 WRITE_VREG(HEVC_PARSER_MEM_RW_DATA, info);
6029 av1_print(hw, AOM_DEBUG_HW_MORE,
6030 "config next ref info %d 0x%x\n", j, info);
6031 }
6032}
6033
6034
6035
6036#ifdef PRINT_HEVC_DATA_PATH_MONITOR
6037void datapath_monitor(struct AV1HW_s *hw)
6038{
6039 uint32_t total_clk_count;
6040 uint32_t path_transfer_count;
6041 uint32_t path_wait_count;
6042 float path_wait_ratio;
6043 if (pbi->decode_idx > 1) {
6044 WRITE_VREG(HEVC_PATH_MONITOR_CTRL, 0); // Disabble monitor and set rd_idx to 0
6045 total_clk_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
6046
6047 WRITE_VREG(HEVC_PATH_MONITOR_CTRL, (1<<4)); // Disabble monitor and set rd_idx to 0
6048
6049// parser --> iqit
6050 path_transfer_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
6051 path_wait_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
6052 if (path_transfer_count == 0) path_wait_ratio = 0.0;
6053 else path_wait_ratio = (float)path_wait_count/(float)path_transfer_count;
6054 printk("[P%d HEVC PATH] Parser/IQIT/IPP/DBLK/OW/DDR/CMD WAITING \% : %.2f",
6055 pbi->decode_idx - 2, path_wait_ratio);
6056
6057// iqit --> ipp
6058 path_transfer_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
6059 path_wait_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
6060 if (path_transfer_count == 0) path_wait_ratio = 0.0;
6061 else path_wait_ratio = (float)path_wait_count/(float)path_transfer_count;
6062 printk(" %.2f", path_wait_ratio);
6063
6064// dblk <-- ipp
6065 path_transfer_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
6066 path_wait_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
6067 if (path_transfer_count == 0) path_wait_ratio = 0.0;
6068 else path_wait_ratio = (float)path_wait_count/(float)path_transfer_count;
6069 printk(" %.2f", path_wait_ratio);
6070
6071// dblk --> ow
6072 path_transfer_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
6073 path_wait_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
6074 if (path_transfer_count == 0) path_wait_ratio = 0.0;
6075 else path_wait_ratio = (float)path_wait_count/(float)path_transfer_count;
6076 printk(" %.2f", path_wait_ratio);
6077
6078// <--> DDR
6079 path_transfer_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
6080 path_wait_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
6081 if (path_transfer_count == 0) path_wait_ratio = 0.0;
6082 else path_wait_ratio = (float)path_wait_count/(float)path_transfer_count;
6083 printk(" %.2f", path_wait_ratio);
6084
6085// CMD
6086 path_transfer_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
6087 path_wait_count = READ_VREG(HEVC_PATH_MONITOR_DATA);
6088 if (path_transfer_count == 0) path_wait_ratio = 0.0;
6089 else path_wait_ratio = (float)path_wait_count/(float)path_transfer_count;
6090 printk(" %.2f\n", path_wait_ratio);
6091 }
6092}
6093
6094#endif
6095
6096#ifdef MCRCC_ENABLE
6097
6098static int mcrcc_hit_rate;
6099static int mcrcc_bypass_rate;
6100
6101#define C_Reg_Wr WRITE_VREG
6102static void C_Reg_Rd(unsigned int adr, unsigned int *val)
6103{
6104 *val = READ_VREG(adr);
6105}
6106
6107static void mcrcc_perfcount_reset(struct AV1HW_s *hw)
6108{
6109 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE,
6110 "[cache_util.c] Entered mcrcc_perfcount_reset...\n");
6111 C_Reg_Wr(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x1);
6112 C_Reg_Wr(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x0);
6113 return;
6114}
6115
6116static unsigned raw_mcr_cnt_total_prev;
6117static unsigned hit_mcr_0_cnt_total_prev;
6118static unsigned hit_mcr_1_cnt_total_prev;
6119static unsigned byp_mcr_cnt_nchcanv_total_prev;
6120static unsigned byp_mcr_cnt_nchoutwin_total_prev;
6121
6122static void mcrcc_get_hitrate(struct AV1HW_s *hw, unsigned reset_pre)
6123{
6124 unsigned delta_hit_mcr_0_cnt;
6125 unsigned delta_hit_mcr_1_cnt;
6126 unsigned delta_raw_mcr_cnt;
6127 unsigned delta_mcr_cnt_nchcanv;
6128 unsigned delta_mcr_cnt_nchoutwin;
6129
6130 unsigned tmp;
6131 unsigned raw_mcr_cnt;
6132 unsigned hit_mcr_cnt;
6133 unsigned byp_mcr_cnt_nchoutwin;
6134 unsigned byp_mcr_cnt_nchcanv;
6135 int hitrate;
6136
6137 if (reset_pre) {
6138 raw_mcr_cnt_total_prev = 0;
6139 hit_mcr_0_cnt_total_prev = 0;
6140 hit_mcr_1_cnt_total_prev = 0;
6141 byp_mcr_cnt_nchcanv_total_prev = 0;
6142 byp_mcr_cnt_nchoutwin_total_prev = 0;
6143 }
6144 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "[cache_util.c] Entered mcrcc_get_hitrate...\n");
6145 C_Reg_Wr(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x0<<1));
6146 C_Reg_Rd(HEVCD_MCRCC_PERFMON_DATA, &raw_mcr_cnt);
6147 C_Reg_Wr(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x1<<1));
6148 C_Reg_Rd(HEVCD_MCRCC_PERFMON_DATA, &hit_mcr_cnt);
6149 C_Reg_Wr(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x2<<1));
6150 C_Reg_Rd(HEVCD_MCRCC_PERFMON_DATA, &byp_mcr_cnt_nchoutwin);
6151 C_Reg_Wr(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x3<<1));
6152 C_Reg_Rd(HEVCD_MCRCC_PERFMON_DATA, &byp_mcr_cnt_nchcanv);
6153
6154 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "raw_mcr_cnt_total: %d\n",raw_mcr_cnt);
6155 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "hit_mcr_cnt_total: %d\n",hit_mcr_cnt);
6156 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "byp_mcr_cnt_nchoutwin_total: %d\n",byp_mcr_cnt_nchoutwin);
6157 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "byp_mcr_cnt_nchcanv_total: %d\n",byp_mcr_cnt_nchcanv);
6158
6159 delta_raw_mcr_cnt = raw_mcr_cnt - raw_mcr_cnt_total_prev;
6160 delta_mcr_cnt_nchcanv = byp_mcr_cnt_nchcanv - byp_mcr_cnt_nchcanv_total_prev;
6161 delta_mcr_cnt_nchoutwin = byp_mcr_cnt_nchoutwin - byp_mcr_cnt_nchoutwin_total_prev;
6162 raw_mcr_cnt_total_prev = raw_mcr_cnt;
6163 byp_mcr_cnt_nchcanv_total_prev = byp_mcr_cnt_nchcanv;
6164 byp_mcr_cnt_nchoutwin_total_prev = byp_mcr_cnt_nchoutwin;
6165
6166 C_Reg_Wr(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x4<<1));
6167 C_Reg_Rd(HEVCD_MCRCC_PERFMON_DATA, &tmp);
6168 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "miss_mcr_0_cnt_total: %d\n",tmp);
6169 C_Reg_Wr(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x5<<1));
6170 C_Reg_Rd(HEVCD_MCRCC_PERFMON_DATA, &tmp);
6171 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "miss_mcr_1_cnt_total: %d\n",tmp);
6172 C_Reg_Wr(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x6<<1));
6173 C_Reg_Rd(HEVCD_MCRCC_PERFMON_DATA, &tmp);
6174 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "hit_mcr_0_cnt_total: %d\n",tmp);
6175 delta_hit_mcr_0_cnt = tmp - hit_mcr_0_cnt_total_prev;
6176 hit_mcr_0_cnt_total_prev = tmp;
6177 C_Reg_Wr(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x7<<1));
6178 C_Reg_Rd(HEVCD_MCRCC_PERFMON_DATA, &tmp);
6179 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "hit_mcr_1_cnt_total: %d\n",tmp);
6180 delta_hit_mcr_1_cnt = tmp - hit_mcr_1_cnt_total_prev;
6181 hit_mcr_1_cnt_total_prev = tmp;
6182
6183 if ( delta_raw_mcr_cnt != 0 ) {
6184 hitrate = 100 * delta_hit_mcr_0_cnt/ delta_raw_mcr_cnt;
6185 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "CANV0_HIT_RATE : %d\n", hitrate);
6186 hitrate = 100 * delta_hit_mcr_1_cnt/delta_raw_mcr_cnt;
6187 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "CANV1_HIT_RATE : %d\n", hitrate);
6188 hitrate = 100 * delta_mcr_cnt_nchcanv/delta_raw_mcr_cnt;
6189 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "NONCACH_CANV_BYP_RATE : %d\n", hitrate);
6190 hitrate = 100 * delta_mcr_cnt_nchoutwin/delta_raw_mcr_cnt;
6191 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "CACHE_OUTWIN_BYP_RATE : %d\n", hitrate);
6192 }
6193
6194 if (raw_mcr_cnt != 0)
6195 {
6196 hitrate = 100*hit_mcr_cnt/raw_mcr_cnt;
6197 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "MCRCC_HIT_RATE : %d\n", hitrate);
6198 hitrate = 100*(byp_mcr_cnt_nchoutwin + byp_mcr_cnt_nchcanv)/raw_mcr_cnt;
6199 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "MCRCC_BYP_RATE : %d\n", hitrate);
6200 } else {
6201 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "MCRCC_HIT_RATE : na\n");
6202 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "MCRCC_BYP_RATE : na\n");
6203 }
6204 mcrcc_hit_rate = 100*hit_mcr_cnt/raw_mcr_cnt;
6205 mcrcc_bypass_rate = 100*(byp_mcr_cnt_nchoutwin + byp_mcr_cnt_nchcanv)/raw_mcr_cnt;
6206
6207 return;
6208}
6209
6210static void decomp_perfcount_reset(struct AV1HW_s *hw)
6211{
6212 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "[cache_util.c] Entered decomp_perfcount_reset...\n");
6213 C_Reg_Wr(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x1);
6214 C_Reg_Wr(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x0);
6215 return;
6216}
6217
6218static void decomp_get_hitrate(struct AV1HW_s *hw)
6219{
6220 unsigned raw_mcr_cnt;
6221 unsigned hit_mcr_cnt;
6222 int hitrate;
6223
6224 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "[cache_util.c] Entered decomp_get_hitrate...\n");
6225 C_Reg_Wr(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x0<<1));
6226 C_Reg_Rd(HEVCD_MPP_DECOMP_PERFMON_DATA, &raw_mcr_cnt);
6227 C_Reg_Wr(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x1<<1));
6228 C_Reg_Rd(HEVCD_MPP_DECOMP_PERFMON_DATA, &hit_mcr_cnt);
6229
6230 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "hcache_raw_cnt_total: %d\n",raw_mcr_cnt);
6231 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "hcache_hit_cnt_total: %d\n",hit_mcr_cnt);
6232
6233 if ( raw_mcr_cnt != 0 ) {
6234 hitrate = 100*hit_mcr_cnt/raw_mcr_cnt;
6235 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "DECOMP_HCACHE_HIT_RATE : %.2f\%\n", hitrate);
6236 } else {
6237 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "DECOMP_HCACHE_HIT_RATE : na\n");
6238 }
6239 C_Reg_Wr(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x2<<1));
6240 C_Reg_Rd(HEVCD_MPP_DECOMP_PERFMON_DATA, &raw_mcr_cnt);
6241 C_Reg_Wr(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x3<<1));
6242 C_Reg_Rd(HEVCD_MPP_DECOMP_PERFMON_DATA, &hit_mcr_cnt);
6243
6244 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "dcache_raw_cnt_total: %d\n",raw_mcr_cnt);
6245 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "dcache_hit_cnt_total: %d\n",hit_mcr_cnt);
6246
6247 if ( raw_mcr_cnt != 0 ) {
6248 hitrate = 100*hit_mcr_cnt/raw_mcr_cnt;
6249 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "DECOMP_DCACHE_HIT_RATE : %d\n", hitrate);
6250
6251 //hitrate = ((float)hit_mcr_cnt/(float)raw_mcr_cnt);
6252 //hitrate = (mcrcc_hit_rate + (mcrcc_bypass_rate * hitrate))*100;
6253 hitrate = mcrcc_hit_rate + (mcrcc_bypass_rate * hit_mcr_cnt/raw_mcr_cnt);
6254 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "MCRCC_DECOMP_DCACHE_EFFECTIVE_HIT_RATE : %d\n", hitrate);
6255
6256 } else {
6257 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "DECOMP_DCACHE_HIT_RATE : na\n");
6258 }
6259
6260 return;
6261}
6262
6263static void decomp_get_comprate(struct AV1HW_s *hw)
6264{
6265 unsigned raw_ucomp_cnt;
6266 unsigned fast_comp_cnt;
6267 unsigned slow_comp_cnt;
6268 int comprate;
6269
6270 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "[cache_util.c] Entered decomp_get_comprate...\n");
6271 C_Reg_Wr(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x4<<1));
6272 C_Reg_Rd(HEVCD_MPP_DECOMP_PERFMON_DATA, &fast_comp_cnt);
6273 C_Reg_Wr(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x5<<1));
6274 C_Reg_Rd(HEVCD_MPP_DECOMP_PERFMON_DATA, &slow_comp_cnt);
6275 C_Reg_Wr(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x6<<1));
6276 C_Reg_Rd(HEVCD_MPP_DECOMP_PERFMON_DATA, &raw_ucomp_cnt);
6277
6278 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "decomp_fast_comp_total: %d\n",fast_comp_cnt);
6279 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "decomp_slow_comp_total: %d\n",slow_comp_cnt);
6280 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "decomp_raw_uncomp_total: %d\n",raw_ucomp_cnt);
6281
6282 if ( raw_ucomp_cnt != 0 )
6283 {
6284 comprate = 100*(fast_comp_cnt + slow_comp_cnt)/raw_ucomp_cnt;
6285 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "DECOMP_COMP_RATIO : %d\n", comprate);
6286 } else
6287 {
6288 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "DECOMP_COMP_RATIO : na\n");
6289 }
6290 return;
6291}
6292
6293static void dump_hit_rate(struct AV1HW_s *hw)
6294{
6295 if (debug & AV1_DEBUG_CACHE_HIT_RATE) {
6296 mcrcc_get_hitrate(hw, hw->m_ins_flag);
6297 decomp_get_hitrate(hw);
6298 decomp_get_comprate(hw);
6299 }
6300}
6301
6302static uint32_t mcrcc_get_abs_frame_distance(struct AV1HW_s *hw, uint32_t refid, uint32_t ref_ohint, uint32_t curr_ohint, uint32_t ohint_bits_min1)
6303{
6304 int32_t diff_ohint0;
6305 int32_t diff_ohint1;
6306 uint32_t abs_dist;
6307 uint32_t m;
6308 uint32_t m_min1;
6309
6310 diff_ohint0 = ref_ohint - curr_ohint;
6311
6312 m = (1 << ohint_bits_min1);
6313 m_min1 = m -1;
6314
6315 diff_ohint1 = (diff_ohint0 & m_min1 ) - (diff_ohint0 & m);
6316
6317 abs_dist = (diff_ohint1 < 0) ? -diff_ohint1 : diff_ohint1;
6318
6319 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE,
6320 "[cache_util.c] refid:%0x ref_orderhint:%0x curr_orderhint:%0x orderhint_bits_min1:%0x abd_dist:%0x\n",
6321 refid, ref_ohint, curr_ohint, ohint_bits_min1,abs_dist);
6322
6323 return abs_dist;
6324}
6325
6326static void config_mcrcc_axi_hw_nearest_ref(struct AV1HW_s *hw)
6327{
6328 uint32_t i;
6329 uint32_t rdata32;
6330 uint32_t dist_array[8];
6331 uint32_t refcanvas_array[2];
6332 uint32_t orderhint_bits;
6333 unsigned char is_inter;
6334 AV1_COMMON *cm = &hw->pbi->common;
6335 PIC_BUFFER_CONFIG *curr_pic_config;
6336 int32_t curr_orderhint;
6337 int cindex0 = LAST_FRAME;
6338 uint32_t last_ref_orderhint_dist = 1023; // large distance
6339 uint32_t curr_ref_orderhint_dist = 1023; // large distance
6340 int cindex1;
6341 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE,
6342 "[test.c] #### config_mcrcc_axi_hw ####\n");
6343
6344 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2); // reset mcrcc
6345
6346 is_inter = av1_frame_is_inter(&hw->pbi->common); //((pbi->common.frame_type != KEY_FRAME) && (!pbi->common.intra_only)) ? 1 : 0;
6347 if ( !is_inter ) { // I-PIC
6348 //WRITE_VREG(HEVCD_MCRCC_CTL1, 0x1); // remove reset -- disables clock
6349 WRITE_VREG(HEVCD_MCRCC_CTL2, 0xffffffff); // Replace with current-frame canvas
6350 WRITE_VREG(HEVCD_MCRCC_CTL3, 0xffffffff); //
6351 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0); // enable mcrcc progressive-mode
6352 return;
6353 }
6354
6355#if 0
6356 //printk("before call mcrcc_get_hitrate\r\n");
6357 mcrcc_get_hitrate(hw);
6358 decomp_get_hitrate(hw);
6359 decomp_get_comprate(hw);
6360#endif
6361
6362 // Find absolute orderhint delta
6363 curr_pic_config = &cm->cur_frame->buf;
6364 curr_orderhint = curr_pic_config->order_hint;
6365 orderhint_bits = cm->seq_params.order_hint_info.order_hint_bits_minus_1;
6366 for (i = LAST_FRAME; i <= ALTREF_FRAME; i++) {
6367 int32_t ref_orderhint = 0;
6368 PIC_BUFFER_CONFIG *pic_config;
6369 //int32_t tmp;
6370 pic_config = av1_get_ref_frame_spec_buf(cm,i);
6371 if (pic_config)
6372 ref_orderhint = pic_config->order_hint;
6373 //tmp = curr_orderhint - ref_orderhint;
6374 //dist_array[i] = (tmp < 0) ? -tmp : tmp;
6375 dist_array[i] = mcrcc_get_abs_frame_distance(hw, i,ref_orderhint, curr_orderhint, orderhint_bits);
6376 }
6377 // Get smallest orderhint distance refid
6378 for (i = LAST_FRAME; i <= ALTREF_FRAME; i++) {
6379 PIC_BUFFER_CONFIG *pic_config;
6380 pic_config = av1_get_ref_frame_spec_buf(cm, i);
6381 curr_ref_orderhint_dist = dist_array[i];
6382 if ( curr_ref_orderhint_dist < last_ref_orderhint_dist) {
6383 cindex0 = i;
6384 last_ref_orderhint_dist = curr_ref_orderhint_dist;
6385 }
6386 }
6387 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (cindex0 << 8) | (1<<1) | 0);
6388 refcanvas_array[0] = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR) & 0xffff;
6389
6390 last_ref_orderhint_dist = 1023; // large distance
6391 curr_ref_orderhint_dist = 1023; // large distance
6392 // Get 2nd smallest orderhint distance refid
6393 cindex1 = LAST_FRAME;
6394 for (i = LAST_FRAME; i <= ALTREF_FRAME; i++) {
6395 PIC_BUFFER_CONFIG *pic_config;
6396 pic_config = av1_get_ref_frame_spec_buf(cm, i);
6397 curr_ref_orderhint_dist = dist_array[i];
6398 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (i << 8) | (1<<1) | 0);
6399 refcanvas_array[1] = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR) & 0xffff;
6400 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "[cache_util.c] curr_ref_orderhint_dist:%x last_ref_orderhint_dist:%x refcanvas_array[0]:%x refcanvas_array[1]:%x\n",
6401 curr_ref_orderhint_dist, last_ref_orderhint_dist, refcanvas_array[0],refcanvas_array[1]);
6402 if ((curr_ref_orderhint_dist < last_ref_orderhint_dist) && (refcanvas_array[0] != refcanvas_array[1])) {
6403 cindex1 = i;
6404 last_ref_orderhint_dist = curr_ref_orderhint_dist;
6405 }
6406 }
6407
6408 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (cindex0 << 8) | (1<<1) | 0);
6409 refcanvas_array[0] = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6410 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (cindex1 << 8) | (1<<1) | 0);
6411 refcanvas_array[1] = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6412
6413 av1_print(hw, AV1_DEBUG_CACHE_HIT_RATE, "[cache_util.c] refcanvas_array[0](index %d):%x refcanvas_array[1](index %d):%x\n",
6414 cindex0, refcanvas_array[0], cindex1, refcanvas_array[1]);
6415
6416 // lowest delta_picnum
6417 rdata32 = refcanvas_array[0];
6418 rdata32 = rdata32 & 0xffff;
6419 rdata32 = rdata32 | ( rdata32 << 16);
6420 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
6421
6422 // 2nd-lowest delta_picnum
6423 rdata32 = refcanvas_array[1];
6424 rdata32 = rdata32 & 0xffff;
6425 rdata32 = rdata32 | ( rdata32 << 16);
6426 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
6427
6428 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0); // enable mcrcc progressive-mode
6429 return;
6430}
6431
6432
6433#endif
6434
6435int av1_continue_decoding(struct AV1HW_s *hw, int obu_type)
6436{
6437 int ret;
6438#if 1
6439 //def CHANGE_DONE
6440 AV1Decoder *pbi = hw->pbi;
6441 AV1_COMMON *const cm = &pbi->common;
6442 int i;
6443
6444 av1_print(hw, AOM_DEBUG_HW_MORE,
6445 "%s: pbi %p cm %p cur_frame %p %d\n",
6446 __func__, pbi, cm, cm->cur_frame,
6447 pbi->bufmgr_proc_count);
6448
6449 //pre_decode_idx = pbi->decode_idx;
6450 if (pbi->bufmgr_proc_count == 0 ||
6451 hw->one_compressed_data_done) {
6452 hw->new_compressed_data = 1;
6453 hw->one_compressed_data_done = 0;
6454 } else {
6455 hw->new_compressed_data = 0;
6456 }
6457 ret = av1_bufmgr_process(pbi, &hw->aom_param,
6458 hw->new_compressed_data, obu_type);
6459 av1_print(hw, AOM_DEBUG_HW_MORE,
6460 "%s: pbi %p cm %p cur_frame %p\n",
6461 __func__, pbi, cm, cm->cur_frame);
6462
6463 av1_print(hw, AOM_DEBUG_HW_MORE,
6464 "1+++++++++++++++++++++++++++++++++++%d %p\n",
6465 ret, cm->cur_frame);
6466 if (hw->new_compressed_data)
6467 WRITE_VREG(PIC_END_LCU_COUNT, 0);
6468
6469 if (ret > 0) {
6470 /* the case when cm->show_existing_frame is 1 */
6471 /*case 3016*/
6472 av1_print(hw, AOM_DEBUG_HW_MORE,
6473 "Decoding done (index=%d, show_existing_frame = %d)\n",
6474 cm->cur_frame? cm->cur_frame->buf.index:-1,
6475 cm->show_existing_frame
6476 );
6477
6478 if (cm->cur_frame) {
6479 PIC_BUFFER_CONFIG* cur_pic_config = &cm->cur_frame->buf;
6480 if (debug &
6481 AV1_DEBUG_BUFMGR_MORE)
6482 dump_aux_buf(hw);
6483 set_pic_aux_data(hw,
6484 cur_pic_config, 0, 0);
6485 }
6486 config_next_ref_info_hw(hw);
6487
6488 av1_print(hw, AOM_DEBUG_HW_MORE,
6489 "aom_bufmgr_process=> %d,decode done, AOM_AV1_SEARCH_HEAD\r\n", ret);
6490 WRITE_VREG(HEVC_DEC_STATUS_REG, AOM_AV1_SEARCH_HEAD);
6491 pbi->decode_idx++;
6492 pbi->bufmgr_proc_count++;
6493 hw->frame_decoded = 1;
6494 return 0;
6495 }
6496 else if (ret < 0) {
6497 hw->frame_decoded = 1;
6498 av1_print(hw, AOM_DEBUG_HW_MORE,
6499 "aom_bufmgr_process=> %d, bufmgr e.r.r.o.r., AOM_AV1_SEARCH_HEAD\r\n", ret);
6500 WRITE_VREG(HEVC_DEC_STATUS_REG, AOM_AV1_SEARCH_HEAD);
6501 return 0;
6502 }
6503 else if (ret == 0) {
6504 PIC_BUFFER_CONFIG* cur_pic_config = &cm->cur_frame->buf;
6505 PIC_BUFFER_CONFIG* prev_pic_config = &cm->prev_frame->buf;
6506 //struct segmentation_lf *seg_4lf = &hw->seg_4lf_store;
6507 if (debug &
6508 AV1_DEBUG_BUFMGR_MORE)
6509 dump_aux_buf(hw);
6510 set_dv_data(hw);
6511 if (cm->show_frame &&
6512 hw->dv_data_buf != NULL)
6513 copy_dv_data(hw, cur_pic_config);
6514 /* to do:..
6515 set_pic_aux_data(hw,
6516 cur_pic_config, 0, 2);*/
6517 hw->frame_decoded = 0;
6518 pbi->bufmgr_proc_count++;
6519 if (hw->new_compressed_data == 0) {
6520 WRITE_VREG(HEVC_DEC_STATUS_REG, AOM_AV1_DECODE_SLICE);
6521 return 0;
6522 }
6523 av1_print(hw, AOM_DEBUG_HW_MORE,
6524 " [PICTURE %d] cm->cur_frame->mi_size : (%d X %d) y_crop_size :(%d X %d)\n",
6525 hw->frame_count,
6526 cm->cur_frame->mi_cols,
6527 cm->cur_frame->mi_rows,
6528 cur_pic_config->y_crop_width,
6529 cur_pic_config->y_crop_height);
6530 if (cm->prev_frame > 0) {
6531 av1_print(hw, AOM_DEBUG_HW_MORE,
6532 " [SEGMENT] cm->prev_frame->segmentation_enabled : %d\n",
6533 cm->prev_frame->segmentation_enabled);
6534 av1_print(hw, AOM_DEBUG_HW_MORE,
6535 " [SEGMENT] cm->prev_frame->mi_size : (%d X %d)\n",
6536 cm->prev_frame->mi_cols, cm->prev_frame->mi_rows);
6537 }
6538 cm->cur_frame->prev_segmentation_enabled = (cm->prev_frame > 0) ?
6539 (cm->prev_frame->segmentation_enabled & (cm->prev_frame->segmentation_update_map
6540 | cm->prev_frame->prev_segmentation_enabled) &
6541 (cm->cur_frame->mi_rows == cm->prev_frame->mi_rows) &
6542 (cm->cur_frame->mi_cols == cm->prev_frame->mi_cols)) : 0;
6543 WRITE_VREG(AV1_SKIP_MODE_INFO,
6544 (cm->cur_frame->prev_segmentation_enabled << 31) |
6545 (((cm->prev_frame > 0) ? cm->prev_frame->intra_only : 0) << 30) |
6546 (((cm->prev_frame > 0) ? prev_pic_config->index : 0x1f) << 24) |
6547 (((cm->cur_frame > 0) ? cur_pic_config->index : 0x1f) << 16) |
6548 (cm->current_frame.skip_mode_info.ref_frame_idx_0 & 0xf) |
6549 ((cm->current_frame.skip_mode_info.ref_frame_idx_1 & 0xf) << 4) |
6550 (cm->current_frame.skip_mode_info.skip_mode_allowed << 8));
6551 cur_pic_config->decode_idx = pbi->decode_idx;
6552
6553 av1_print(hw, AOM_DEBUG_HW_MORE,
6554 "Decode Frame Data %d frame_type %d (%d) bufmgr_proc_count %d\n",
6555 pbi->decode_idx,
6556 cm->cur_frame->frame_type,
6557 cm->current_frame.frame_type,
6558 pbi->bufmgr_proc_count);
6559 pbi->decode_idx++;
6560 hw->frame_count++;
6561 cur_pic_config->slice_type = cm->cur_frame->frame_type;
6562 if (hw->chunk) {
6563 cur_pic_config->pts = hw->chunk->pts;
6564 cur_pic_config->pts64 = hw->chunk->pts64;
6565 hw->chunk->pts = 0;
6566 hw->chunk->pts64 = 0;
6567 //pr_info("continue_decode: pic %p, pts %d\n",cur_pic_config, hw->chunk->pts);
6568 }
6569#ifdef DUAL_DECODE
6570#else
6571 config_pic_size(hw, hw->aom_param.p.bit_depth);
6572#endif
6573 if (get_mv_buf(hw,
6574 &cm->cur_frame->buf.mv_buf_index,
6575 &cm->cur_frame->buf.mpred_mv_wr_start_addr
6576 ) < 0) {
6577 av1_print(hw, 0,
6578 "%s: Error get_mv_buf fail\n",
6579 __func__);
6580 ret = -1;
6581 }
6582
6583 if (ret >= 0 && hw->mmu_enable && ((hw->double_write_mode & 0x10) == 0)) {
6584 ret = av1_alloc_mmu(hw,
6585 cm->cur_frame->buf.index,
6586 cur_pic_config->y_crop_width,
6587 cur_pic_config->y_crop_height,
6588 hw->aom_param.p.bit_depth,
6589 hw->frame_mmu_map_addr);
6590 if (ret >= 0)
6591 cm->cur_fb_idx_mmu = cm->cur_frame->buf.index;
6592 else
6593 pr_err("can't alloc need mmu1,idx %d ret =%d\n",
6594 cm->cur_frame->buf.index, ret);
6595#ifdef AOM_AV1_MMU_DW
6596 if (hw->dw_mmu_enable) {
6597 ret = av1_alloc_mmu_dw(hw,
6598 cm->cur_frame->buf.index,
6599 cur_pic_config->y_crop_width,
6600 cur_pic_config->y_crop_height,
6601 hw->aom_param.p.bit_depth,
6602 hw->dw_frame_mmu_map_addr);
6603 if (ret >= 0)
6604 cm->cur_fb_idx_mmu_dw = cm->cur_frame->buf.index;
6605 else
6606 pr_err("can't alloc need dw mmu1,idx %d ret =%d\n",
6607 cm->cur_frame->buf.index, ret);
6608 }
6609#endif
6610 } else {
6611 ret = 0;
6612 }
6613 if (av1_frame_is_inter(&hw->pbi->common)) {
6614 //if ((pbi->common.frame_type != KEY_FRAME) && (!pbi->common.intra_only)) {
6615#ifdef DUAL_DECODE
6616#else
6617 config_mc_buffer(hw, hw->aom_param.p.bit_depth, 1);
6618#endif
6619 config_mpred_hw(hw, 1);
6620 }
6621 else {
6622 config_mc_buffer(hw, hw->aom_param.p.bit_depth, 0);
6623 clear_mpred_hw(hw);
6624 config_mpred_hw(hw, 0);
6625 }
6626#ifdef DUAL_DECODE
6627#else
6628#ifdef MCRCC_ENABLE
6629 config_mcrcc_axi_hw_nearest_ref(hw);
6630#endif
6631 config_sao_hw(hw, &hw->aom_param);
6632#endif
6633
6634 config_dblk_hw(hw);
6635
6636 av1_print(hw, AOM_DEBUG_HW_MORE, "HEVC_DEC_STATUS_REG <= AOM_AV1_DECODE_SLICE\n");
6637 WRITE_VREG(HEVC_DEC_STATUS_REG, AOM_AV1_DECODE_SLICE);
6638
6639 // Save segment_feature while hardware decoding
6640 if (hw->seg_4lf->enabled) {
6641 for (i = 0; i < 8; i++) {
6642 cm->cur_frame->segment_feature[i] = READ_VREG(AOM_AV1_SEGMENT_FEATURE);
6643 }
6644 } else {
6645 for (i = 0; i < 8; i++) {
6646 cm->cur_frame->segment_feature[i] = (0x80000000 | (i << 22));
6647 }
6648 }
6649 WRITE_VREG(HEVC_PARSER_MEM_WR_ADDR, 0x1010 + (cur_pic_config->index));
6650 if (hw->aom_param.p.segmentation_enabled & 1) // segmentation_enabled
6651 WRITE_VREG(HEVC_PARSER_MEM_RW_DATA, READ_VREG(AV1_REF_SEG_INFO));
6652 else
6653 WRITE_VREG(HEVC_PARSER_MEM_RW_DATA, 0);
6654 } else {
6655 av1_print(hw, AOM_DEBUG_HW_MORE, "Sequence head, Search next start code\n");
6656 cm->prev_fb_idx = INVALID_IDX;
6657 //skip, search next start code
6658 WRITE_VREG(HEVC_DEC_STATUS_REG, AOM_AV1_DECODE_SLICE);
6659 }
6660 return ret;
6661
6662#else
6663
6664 bit_depth_luma = av1_param.p.bit_depth;
6665 bit_depth_chroma = av1_param.p.bit_depth;
6666
6667 if (hw->process_state != PROC_STATE_SENDAGAIN) {
6668 ret = av1_bufmgr_process(hw, &av1_param);
6669 if (!hw->m_ins_flag)
6670 hw->result_done_count++;
6671 } else {
6672 union param_u *params = &av1_param;
6673 if (hw->mmu_enable && ((hw->double_write_mode & 0x10) == 0)) {
6674 ret = av1_alloc_mmu(hw,
6675 cm->new_fb_idx,
6676 params->p.width,
6677 params->p.height,
6678 params->p.bit_depth,
6679 hw->frame_mmu_map_addr);
6680 if (ret >= 0)
6681 cm->cur_fb_idx_mmu = cm->new_fb_idx;
6682 else
6683 pr_err("can't alloc need mmu1,idx %d ret =%d\n",
6684 cm->new_fb_idx, ret);
6685 } else {
6686 ret = 0;
6687 }
6688 WRITE_VREG(HEVC_PARSER_PICTURE_SIZE,
6689 (params->p.height << 16) | params->p.width);
6690 }
6691 if (ret < 0) {
6692 pr_info("av1_bufmgr_process=> %d, AV1_10B_DISCARD_NAL\r\n", ret);
6693 WRITE_VREG(HEVC_DEC_STATUS_REG, AV1_10B_DISCARD_NAL);
6694 cm->show_frame = 0;
6695 if (hw->mmu_enable)
6696 av1_recycle_mmu_buf(hw);
6697
6698 if (hw->m_ins_flag) {
6699 hw->dec_result = DEC_RESULT_DONE;
6700 amhevc_stop();
6701 vdec_schedule_work(&hw->work);
6702 }
6703 return ret;
6704 } else if (ret == 0) {
6705 struct PIC_BUFFER_CONFIG_s *cur_pic_config
6706 = &cm->cur_frame->buf;
6707 cur_pic_config->decode_idx = hw->frame_count;
6708
6709 if (hw->process_state != PROC_STATE_SENDAGAIN) {
6710 if (!hw->m_ins_flag) {
6711 hw->frame_count++;
6712 decode_frame_count[hw->index]
6713 = hw->frame_count;
6714 }
6715 if (hw->chunk) {
6716 cur_pic_config->pts = hw->chunk->pts;
6717 cur_pic_config->pts64 = hw->chunk->pts64;
6718 }
6719 }
6720 /*pr_info("Decode Frame Data %d\n", hw->frame_count);*/
6721 config_pic_size(hw, av1_param.p.bit_depth);
6722
6723 if ((hw->common.frame_type != KEY_FRAME)
6724 && (!hw->common.intra_only)) {
6725 config_mc_buffer(hw, av1_param.p.bit_depth);
6726 config_mpred_hw(hw);
6727 } else {
6728 clear_mpred_hw(hw);
6729 }
6730#ifdef MCRCC_ENABLE
6731 if (mcrcc_cache_alg_flag)
6732 config_mcrcc_axi_hw_new(hw);
6733 else
6734 config_mcrcc_axi_hw(hw);
6735#endif
6736 config_sao_hw(hw, &av1_param);
6737 /*pr_info("HEVC_DEC_STATUS_REG <= AV1_10B_DECODE_SLICE\n");*/
6738 WRITE_VREG(HEVC_DEC_STATUS_REG, AV1_10B_DECODE_SLICE);
6739 } else {
6740 pr_info("Skip search next start code\n");
6741 cm->prev_fb_idx = INVALID_IDX;
6742 /*skip, search next start code*/
6743 WRITE_VREG(HEVC_DEC_STATUS_REG, AV1_10B_DECODE_SLICE);
6744 }
6745 hw->process_state = PROC_STATE_DECODESLICE;
6746 if (hw->mmu_enable && ((hw->double_write_mode & 0x10) == 0)) {
6747 if (hw->last_put_idx < hw->used_buf_num) {
6748 struct RefCntBuffer_s *frame_bufs =
6749 cm->buffer_pool->frame_bufs;
6750 int i = hw->last_put_idx;
6751 /*free not used buffers.*/
6752 if ((frame_bufs[i].ref_count == 0) &&
6753 (frame_bufs[i].buf.vf_ref == 0) &&
6754 (frame_bufs[i].buf.index != -1)) {
6755 decoder_mmu_box_free_idx(hw->mmu_box, i);
6756 }
6757 hw->last_put_idx = -1;
6758 }
6759 }
6760 return ret;
6761#endif
6762}
6763
6764static void fill_frame_info(struct AV1HW_s *hw,
6765 struct PIC_BUFFER_CONFIG_s *frame,
6766 unsigned int framesize,
6767 unsigned int pts)
6768{
6769 struct vframe_qos_s *vframe_qos = &hw->vframe_qos;
6770
6771 if (frame->slice_type == KEY_FRAME)
6772 vframe_qos->type = 1;
6773 else if (frame->slice_type == INTER_FRAME)
6774 vframe_qos->type = 2;
6775/*
6776#define SHOW_QOS_INFO
6777*/
6778 vframe_qos->size = framesize;
6779 vframe_qos->pts = pts;
6780#ifdef SHOW_QOS_INFO
6781 av1_print(hw, 0, "slice:%d\n", frame->slice_type);
6782#endif
6783 vframe_qos->max_mv = frame->max_mv;
6784 vframe_qos->avg_mv = frame->avg_mv;
6785 vframe_qos->min_mv = frame->min_mv;
6786#ifdef SHOW_QOS_INFO
6787 av1_print(hw, 0, "mv: max:%d, avg:%d, min:%d\n",
6788 vframe_qos->max_mv,
6789 vframe_qos->avg_mv,
6790 vframe_qos->min_mv);
6791#endif
6792 vframe_qos->max_qp = frame->max_qp;
6793 vframe_qos->avg_qp = frame->avg_qp;
6794 vframe_qos->min_qp = frame->min_qp;
6795#ifdef SHOW_QOS_INFO
6796 av1_print(hw, 0, "qp: max:%d, avg:%d, min:%d\n",
6797 vframe_qos->max_qp,
6798 vframe_qos->avg_qp,
6799 vframe_qos->min_qp);
6800#endif
6801 vframe_qos->max_skip = frame->max_skip;
6802 vframe_qos->avg_skip = frame->avg_skip;
6803 vframe_qos->min_skip = frame->min_skip;
6804#ifdef SHOW_QOS_INFO
6805 av1_print(hw, 0, "skip: max:%d, avg:%d, min:%d\n",
6806 vframe_qos->max_skip,
6807 vframe_qos->avg_skip,
6808 vframe_qos->min_skip);
6809#endif
6810 vframe_qos->num++;
6811 /*
6812 if (hw->frameinfo_enable)
6813 vdec_fill_frame_info(vframe_qos, 1);
6814 */
6815}
6816
6817/* only when we decoded one field or one frame,
6818we can call this function to get qos info*/
6819static void get_picture_qos_info(struct AV1HW_s *hw)
6820{
6821 struct PIC_BUFFER_CONFIG_s *frame = &hw->cur_buf->buf;
6822
6823 if (!frame)
6824 return;
6825
6826 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
6827 unsigned char a[3];
6828 unsigned char i, j, t;
6829 unsigned long data;
6830
6831 data = READ_VREG(HEVC_MV_INFO);
6832 if (frame->slice_type == KEY_FRAME)
6833 data = 0;
6834 a[0] = data & 0xff;
6835 a[1] = (data >> 8) & 0xff;
6836 a[2] = (data >> 16) & 0xff;
6837
6838 for (i = 0; i < 3; i++) {
6839 for (j = i+1; j < 3; j++) {
6840 if (a[j] < a[i]) {
6841 t = a[j];
6842 a[j] = a[i];
6843 a[i] = t;
6844 } else if (a[j] == a[i]) {
6845 a[i]++;
6846 t = a[j];
6847 a[j] = a[i];
6848 a[i] = t;
6849 }
6850 }
6851 }
6852 frame->max_mv = a[2];
6853 frame->avg_mv = a[1];
6854 frame->min_mv = a[0];
6855
6856 av1_print(hw, AV1_DEBUG_QOS_INFO,
6857 "mv data %x a[0]= %x a[1]= %x a[2]= %x\n",
6858 data, a[0], a[1], a[2]);
6859
6860 data = READ_VREG(HEVC_QP_INFO);
6861 a[0] = data & 0x1f;
6862 a[1] = (data >> 8) & 0x3f;
6863 a[2] = (data >> 16) & 0x7f;
6864
6865 for (i = 0; i < 3; i++) {
6866 for (j = i+1; j < 3; j++) {
6867 if (a[j] < a[i]) {
6868 t = a[j];
6869 a[j] = a[i];
6870 a[i] = t;
6871 } else if (a[j] == a[i]) {
6872 a[i]++;
6873 t = a[j];
6874 a[j] = a[i];
6875 a[i] = t;
6876 }
6877 }
6878 }
6879 frame->max_qp = a[2];
6880 frame->avg_qp = a[1];
6881 frame->min_qp = a[0];
6882
6883 av1_print(hw, AV1_DEBUG_QOS_INFO,
6884 "qp data %x a[0]= %x a[1]= %x a[2]= %x\n",
6885 data, a[0], a[1], a[2]);
6886
6887 data = READ_VREG(HEVC_SKIP_INFO);
6888 a[0] = data & 0x1f;
6889 a[1] = (data >> 8) & 0x3f;
6890 a[2] = (data >> 16) & 0x7f;
6891
6892 for (i = 0; i < 3; i++) {
6893 for (j = i+1; j < 3; j++) {
6894 if (a[j] < a[i]) {
6895 t = a[j];
6896 a[j] = a[i];
6897 a[i] = t;
6898 } else if (a[j] == a[i]) {
6899 a[i]++;
6900 t = a[j];
6901 a[j] = a[i];
6902 a[i] = t;
6903 }
6904 }
6905 }
6906 frame->max_skip = a[2];
6907 frame->avg_skip = a[1];
6908 frame->min_skip = a[0];
6909
6910 av1_print(hw, AV1_DEBUG_QOS_INFO,
6911 "skip data %x a[0]= %x a[1]= %x a[2]= %x\n",
6912 data, a[0], a[1], a[2]);
6913 } else {
6914 uint32_t blk88_y_count;
6915 uint32_t blk88_c_count;
6916 uint32_t blk22_mv_count;
6917 uint32_t rdata32;
6918 int32_t mv_hi;
6919 int32_t mv_lo;
6920 uint32_t rdata32_l;
6921 uint32_t mvx_L0_hi;
6922 uint32_t mvy_L0_hi;
6923 uint32_t mvx_L1_hi;
6924 uint32_t mvy_L1_hi;
6925 int64_t value;
6926 uint64_t temp_value;
6927 int pic_number = frame->decode_idx;
6928
6929 frame->max_mv = 0;
6930 frame->avg_mv = 0;
6931 frame->min_mv = 0;
6932
6933 frame->max_skip = 0;
6934 frame->avg_skip = 0;
6935 frame->min_skip = 0;
6936
6937 frame->max_qp = 0;
6938 frame->avg_qp = 0;
6939 frame->min_qp = 0;
6940
6941 av1_print(hw, AV1_DEBUG_QOS_INFO, "slice_type:%d, poc:%d\n",
6942 frame->slice_type,
6943 pic_number);
6944
6945 /* set rd_idx to 0 */
6946 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, 0);
6947
6948 blk88_y_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
6949 if (blk88_y_count == 0) {
6950
6951 av1_print(hw, AV1_DEBUG_QOS_INFO,
6952 "[Picture %d Quality] NO Data yet.\n",
6953 pic_number);
6954
6955 /* reset all counts */
6956 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
6957 return;
6958 }
6959 /* qp_y_sum */
6960 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
6961
6962 av1_print(hw, AV1_DEBUG_QOS_INFO,
6963 "[Picture %d Quality] Y QP AVG : %d (%d/%d)\n",
6964 pic_number, rdata32/blk88_y_count,
6965 rdata32, blk88_y_count);
6966
6967 frame->avg_qp = rdata32/blk88_y_count;
6968 /* intra_y_count */
6969 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
6970
6971 av1_print(hw, AV1_DEBUG_QOS_INFO,
6972 "[Picture %d Quality] Y intra rate : %d%c (%d)\n",
6973 pic_number, rdata32*100/blk88_y_count,
6974 '%', rdata32);
6975
6976 /* skipped_y_count */
6977 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
6978
6979 av1_print(hw, AV1_DEBUG_QOS_INFO,
6980 "[Picture %d Quality] Y skipped rate : %d%c (%d)\n",
6981 pic_number, rdata32*100/blk88_y_count,
6982 '%', rdata32);
6983
6984 frame->avg_skip = rdata32*100/blk88_y_count;
6985 /* coeff_non_zero_y_count */
6986 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
6987
6988 av1_print(hw, AV1_DEBUG_QOS_INFO,
6989 "[Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n",
6990 pic_number, (100 - rdata32*100/(blk88_y_count*1)),
6991 '%', rdata32);
6992
6993 /* blk66_c_count */
6994 blk88_c_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
6995 if (blk88_c_count == 0) {
6996 av1_print(hw, AV1_DEBUG_QOS_INFO,
6997 "[Picture %d Quality] NO Data yet.\n",
6998 pic_number);
6999 /* reset all counts */
7000 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
7001 return;
7002 }
7003 /* qp_c_sum */
7004 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7005
7006 av1_print(hw, AV1_DEBUG_QOS_INFO,
7007 "[Picture %d Quality] C QP AVG : %d (%d/%d)\n",
7008 pic_number, rdata32/blk88_c_count,
7009 rdata32, blk88_c_count);
7010
7011 /* intra_c_count */
7012 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7013
7014 av1_print(hw, AV1_DEBUG_QOS_INFO,
7015 "[Picture %d Quality] C intra rate : %d%c (%d)\n",
7016 pic_number, rdata32*100/blk88_c_count,
7017 '%', rdata32);
7018
7019 /* skipped_cu_c_count */
7020 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7021
7022 av1_print(hw, AV1_DEBUG_QOS_INFO,
7023 "[Picture %d Quality] C skipped rate : %d%c (%d)\n",
7024 pic_number, rdata32*100/blk88_c_count,
7025 '%', rdata32);
7026
7027 /* coeff_non_zero_c_count */
7028 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7029
7030 av1_print(hw, AV1_DEBUG_QOS_INFO,
7031 "[Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n",
7032 pic_number, (100 - rdata32*100/(blk88_c_count*1)),
7033 '%', rdata32);
7034
7035 /* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0],
7036 1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */
7037 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7038
7039 av1_print(hw, AV1_DEBUG_QOS_INFO,
7040 "[Picture %d Quality] Y QP min : %d\n",
7041 pic_number, (rdata32>>0)&0xff);
7042
7043 frame->min_qp = (rdata32>>0)&0xff;
7044
7045 av1_print(hw, AV1_DEBUG_QOS_INFO,
7046 "[Picture %d Quality] Y QP max : %d\n",
7047 pic_number, (rdata32>>8)&0xff);
7048
7049 frame->max_qp = (rdata32>>8)&0xff;
7050
7051 av1_print(hw, AV1_DEBUG_QOS_INFO,
7052 "[Picture %d Quality] C QP min : %d\n",
7053 pic_number, (rdata32>>16)&0xff);
7054 av1_print(hw, AV1_DEBUG_QOS_INFO,
7055 "[Picture %d Quality] C QP max : %d\n",
7056 pic_number, (rdata32>>24)&0xff);
7057
7058 /* blk22_mv_count */
7059 blk22_mv_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
7060 if (blk22_mv_count == 0) {
7061 av1_print(hw, AV1_DEBUG_QOS_INFO,
7062 "[Picture %d Quality] NO MV Data yet.\n",
7063 pic_number);
7064 /* reset all counts */
7065 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
7066 return;
7067 }
7068 /* mvy_L1_count[39:32], mvx_L1_count[39:32],
7069 mvy_L0_count[39:32], mvx_L0_count[39:32] */
7070 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7071 /* should all be 0x00 or 0xff */
7072 av1_print(hw, AV1_DEBUG_QOS_INFO,
7073 "[Picture %d Quality] MV AVG High Bits: 0x%X\n",
7074 pic_number, rdata32);
7075
7076 mvx_L0_hi = ((rdata32>>0)&0xff);
7077 mvy_L0_hi = ((rdata32>>8)&0xff);
7078 mvx_L1_hi = ((rdata32>>16)&0xff);
7079 mvy_L1_hi = ((rdata32>>24)&0xff);
7080
7081 /* mvx_L0_count[31:0] */
7082 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
7083 temp_value = mvx_L0_hi;
7084 temp_value = (temp_value << 32) | rdata32_l;
7085
7086 if (mvx_L0_hi & 0x80)
7087 value = 0xFFFFFFF000000000 | temp_value;
7088 else
7089 value = temp_value;
7090
7091 value = div_s64(value, blk22_mv_count);
7092
7093 av1_print(hw, AV1_DEBUG_QOS_INFO,
7094 "[Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n",
7095 pic_number, (int)value,
7096 value, blk22_mv_count);
7097
7098 frame->avg_mv = value;
7099
7100 /* mvy_L0_count[31:0] */
7101 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
7102 temp_value = mvy_L0_hi;
7103 temp_value = (temp_value << 32) | rdata32_l;
7104
7105 if (mvy_L0_hi & 0x80)
7106 value = 0xFFFFFFF000000000 | temp_value;
7107 else
7108 value = temp_value;
7109
7110 av1_print(hw, AV1_DEBUG_QOS_INFO,
7111 "[Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n",
7112 pic_number, rdata32_l/blk22_mv_count,
7113 value, blk22_mv_count);
7114
7115 /* mvx_L1_count[31:0] */
7116 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
7117 temp_value = mvx_L1_hi;
7118 temp_value = (temp_value << 32) | rdata32_l;
7119 if (mvx_L1_hi & 0x80)
7120 value = 0xFFFFFFF000000000 | temp_value;
7121 else
7122 value = temp_value;
7123
7124 av1_print(hw, AV1_DEBUG_QOS_INFO,
7125 "[Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n",
7126 pic_number, rdata32_l/blk22_mv_count,
7127 value, blk22_mv_count);
7128
7129 /* mvy_L1_count[31:0] */
7130 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
7131 temp_value = mvy_L1_hi;
7132 temp_value = (temp_value << 32) | rdata32_l;
7133 if (mvy_L1_hi & 0x80)
7134 value = 0xFFFFFFF000000000 | temp_value;
7135 else
7136 value = temp_value;
7137
7138 av1_print(hw, AV1_DEBUG_QOS_INFO,
7139 "[Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n",
7140 pic_number, rdata32_l/blk22_mv_count,
7141 value, blk22_mv_count);
7142
7143 /* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */
7144 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7145 mv_hi = (rdata32>>16)&0xffff;
7146 if (mv_hi & 0x8000)
7147 mv_hi = 0x8000 - mv_hi;
7148
7149 av1_print(hw, AV1_DEBUG_QOS_INFO,
7150 "[Picture %d Quality] MVX_L0 MAX : %d\n",
7151 pic_number, mv_hi);
7152
7153 frame->max_mv = mv_hi;
7154
7155 mv_lo = (rdata32>>0)&0xffff;
7156 if (mv_lo & 0x8000)
7157 mv_lo = 0x8000 - mv_lo;
7158
7159 av1_print(hw, AV1_DEBUG_QOS_INFO,
7160 "[Picture %d Quality] MVX_L0 MIN : %d\n",
7161 pic_number, mv_lo);
7162
7163 frame->min_mv = mv_lo;
7164
7165 /* {mvy_L0_max, mvy_L0_min} */
7166 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7167 mv_hi = (rdata32>>16)&0xffff;
7168 if (mv_hi & 0x8000)
7169 mv_hi = 0x8000 - mv_hi;
7170
7171 av1_print(hw, AV1_DEBUG_QOS_INFO,
7172 "[Picture %d Quality] MVY_L0 MAX : %d\n",
7173 pic_number, mv_hi);
7174
7175 mv_lo = (rdata32>>0)&0xffff;
7176 if (mv_lo & 0x8000)
7177 mv_lo = 0x8000 - mv_lo;
7178
7179 av1_print(hw, AV1_DEBUG_QOS_INFO,
7180 "[Picture %d Quality] MVY_L0 MIN : %d\n",
7181 pic_number, mv_lo);
7182
7183 /* {mvx_L1_max, mvx_L1_min} */
7184 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7185 mv_hi = (rdata32>>16)&0xffff;
7186 if (mv_hi & 0x8000)
7187 mv_hi = 0x8000 - mv_hi;
7188
7189 av1_print(hw, AV1_DEBUG_QOS_INFO,
7190 "[Picture %d Quality] MVX_L1 MAX : %d\n",
7191 pic_number, mv_hi);
7192
7193 mv_lo = (rdata32>>0)&0xffff;
7194 if (mv_lo & 0x8000)
7195 mv_lo = 0x8000 - mv_lo;
7196
7197 av1_print(hw, AV1_DEBUG_QOS_INFO,
7198 "[Picture %d Quality] MVX_L1 MIN : %d\n",
7199 pic_number, mv_lo);
7200
7201 /* {mvy_L1_max, mvy_L1_min} */
7202 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7203 mv_hi = (rdata32>>16)&0xffff;
7204 if (mv_hi & 0x8000)
7205 mv_hi = 0x8000 - mv_hi;
7206
7207 av1_print(hw, AV1_DEBUG_QOS_INFO,
7208 "[Picture %d Quality] MVY_L1 MAX : %d\n",
7209 pic_number, mv_hi);
7210
7211 mv_lo = (rdata32>>0)&0xffff;
7212 if (mv_lo & 0x8000)
7213 mv_lo = 0x8000 - mv_lo;
7214
7215 av1_print(hw, AV1_DEBUG_QOS_INFO,
7216 "[Picture %d Quality] MVY_L1 MIN : %d\n",
7217 pic_number, mv_lo);
7218
7219 rdata32 = READ_VREG(HEVC_PIC_QUALITY_CTRL);
7220
7221 av1_print(hw, AV1_DEBUG_QOS_INFO,
7222 "[Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n",
7223 pic_number, rdata32);
7224
7225 /* reset all counts */
7226 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
7227 }
7228}
7229
7230static int load_param(struct AV1HW_s *hw, union param_u *params, uint32_t dec_status)
7231{
7232 int i;
7233 unsigned long flags;
7234 int head_type = 0;
7235 if (dec_status == AOM_AV1_SEQ_HEAD_PARSER_DONE)
7236 head_type = OBU_SEQUENCE_HEADER;
7237 else if (dec_status == AOM_AV1_FRAME_HEAD_PARSER_DONE)
7238 head_type = OBU_FRAME_HEADER;
7239 else if (dec_status == AOM_AV1_FRAME_PARSER_DONE)
7240 head_type = OBU_FRAME;
7241 else if (dec_status == AOM_AV1_REDUNDANT_FRAME_HEAD_PARSER_DONE)
7242 head_type = OBU_REDUNDANT_FRAME_HEADER;
7243 else {
7244 //printf("Error, dec_status of 0x%x, not supported!!!\n", dec_status);
7245 return -1;
7246 }
7247 av1_print2(AOM_DEBUG_HW_MORE, "load_param: ret 0x%x\n", head_type);
7248
7249 if (debug&AOM_AV1_DEBUG_SEND_PARAM_WITH_REG) {
7250 get_rpm_param(params);
7251 }
7252 else {
7253 for (i = 0; i < (RPM_END-RPM_BEGIN); i += 4) {
7254 int32_t ii;
7255 for (ii = 0; ii < 4; ii++) {
7256 params->l.data[i+ii]=hw->rpm_ptr[i+3-ii];
7257 }
7258 }
7259 }
7260
7261 params->p.enable_ref_frame_mvs = (params->p.seq_flags >> 7) & 0x1;
7262 params->p.enable_superres = (params->p.seq_flags >> 15) & 0x1;
7263
7264 if (debug & AV1_DEBUG_BUFMGR_MORE) {
7265 lock_buffer_pool(hw->pbi->common.buffer_pool, flags);
7266 pr_info("aom_param: (%d)\n", hw->pbi->decode_idx);
7267 //pbi->slice_idx++;
7268 for ( i = 0; i < (RPM_END-RPM_BEGIN); i++) {
7269 pr_info("%04x ", params->l.data[i]);
7270 if (((i + 1) & 0xf) == 0)
7271 pr_info("\n");
7272 }
7273 unlock_buffer_pool(hw->pbi->common.buffer_pool, flags);
7274 }
7275 return head_type;
7276}
7277
7278static int av1_postproc(struct AV1HW_s *hw)
7279{
7280 if (hw->postproc_done)
7281 return 0;
7282 hw->postproc_done = 1;
7283 return av1_bufmgr_postproc(hw->pbi, hw->frame_decoded);
7284}
7285
7286static irqreturn_t vav1_isr_thread_fn(int irq, void *data)
7287{
7288 struct AV1HW_s *hw = (struct AV1HW_s *)data;
7289 unsigned int dec_status = hw->dec_status;
7290 int obu_type;
7291
7292 /*if (hw->wait_buf)
7293 * pr_info("set wait_buf to 0\r\n");
7294 */
7295 if (hw->eos)
7296 return IRQ_HANDLED;
7297 hw->wait_buf = 0;
7298 if ((dec_status == AOM_NAL_DECODE_DONE) ||
7299 (dec_status == AOM_SEARCH_BUFEMPTY) ||
7300 (dec_status == AOM_DECODE_BUFEMPTY)
7301 ) {
7302 if (hw->m_ins_flag) {
7303 reset_process_time(hw);
7304 if (!vdec_frame_based(hw_to_vdec(hw)))
7305 dec_again_process(hw);
7306 else {
7307 hw->dec_result = DEC_RESULT_DONE;
7308 vdec_schedule_work(&hw->work);
7309 }
7310 }
7311 hw->process_busy = 0;
7312 return IRQ_HANDLED;
7313 } else if (dec_status == AOM_AV1_DEC_PIC_END) {
7314 struct AV1_Common_s *const cm = &hw->pbi->common;
7315#if 1
7316 u32 fg_reg0, fg_reg1, num_y_points, num_cb_points, num_cr_points;
7317 WRITE_VREG(HEVC_FGS_IDX, 0);
7318 fg_reg0 = READ_VREG(HEVC_FGS_DATA);
7319 fg_reg1 = READ_VREG(HEVC_FGS_DATA);
7320 num_y_points = fg_reg1 & 0xf;
7321 num_cr_points = (fg_reg1 >> 8) & 0xf;
7322 num_cb_points = (fg_reg1 >> 4) & 0xf;
7323 if ((num_y_points > 0) ||
7324 ((num_cb_points > 0) | ((fg_reg0 >> 17) & 0x1)) ||
7325 ((num_cr_points > 0) | ((fg_reg0 >> 17) & 0x1)))
7326 hw->fgs_valid = 1;
7327 else
7328 hw->fgs_valid = 0;
7329 av1_print(hw, AOM_DEBUG_HW_MORE,
7330 "fg_data0 0x%x fg_data1 0x%x fg_valid %d\n",
7331 fg_reg0, fg_reg1, hw->fgs_valid);
7332#else
7333 if (READ_VREG(HEVC_FGS_CTRL) &
7334 ((1 << 4) | (1 << 5) | (1 << 6)))
7335 hw->fgs_valid = 1;
7336 else
7337 hw->fgs_valid = 0;
7338#endif
7339 decode_frame_count[hw->index] = hw->frame_count;
7340 if (hw->m_ins_flag) {
7341#ifdef USE_DEC_PIC_END
7342 if (READ_VREG(PIC_END_LCU_COUNT) != 0) {
7343 hw->frame_decoded = 1;
7344 /*
7345 In c module, multi obus are put in one packet, which is decoded
7346 with av1_receive_compressed_data().
7347 For STREAM_MODE or SINGLE_MODE, there is no packet boundary,
7348 we assume each packet must and only include one picture of data (LCUs)
7349 or cm->show_existing_frame is 1
7350 */
7351 av1_print(hw, AOM_DEBUG_HW_MORE,
7352 "Decoding done (index %d), fgs_valid %d data_size 0x%x shiftbyte 0x%x\n",
7353 cm->cur_frame? cm->cur_frame->buf.index:-1,
7354 hw->fgs_valid,
7355 hw->data_size,
7356 READ_VREG(HEVC_SHIFT_BYTE_COUNT));
7357 hw->config_next_ref_info_flag = 1; /*to do: low_latency_flag case*/
7358 //config_next_ref_info_hw(hw);
7359 }
7360#endif
7361
7362 if (get_picture_qos)
7363 get_picture_qos_info(hw);
7364
7365 reset_process_time(hw);
7366
7367 /*
7368 if (debug &
7369 AV1_DEBUG_BUFMGR_MORE)
7370 dump_aux_buf(hw);
7371 set_aux_data(hw,
7372 &cm->cur_frame->buf, 0, 0);
7373 */
7374 if (/*hw->vf_pre_count == 0 ||*/ hw->low_latency_flag)
7375 av1_postproc(hw);
7376
7377 if (multi_frames_in_one_pack &&
7378 hw->frame_decoded &&
7379 READ_VREG(HEVC_SHIFT_BYTE_COUNT) < hw->data_size) {
7380 WRITE_VREG(HEVC_DEC_STATUS_REG, AOM_AV1_SEARCH_HEAD);
7381 av1_print(hw, AOM_DEBUG_HW_MORE,
7382 "PIC_END, fgs_valid %d search head ...\n",
7383 hw->fgs_valid);
7384 if (hw->config_next_ref_info_flag)
7385 config_next_ref_info_hw(hw);
7386 } else {
7387 hw->dec_result = DEC_RESULT_DONE;
7388 amhevc_stop();
7389#ifdef MCRCC_ENABLE
7390 if (mcrcc_cache_alg_flag)
7391 dump_hit_rate(hw);
7392#endif
7393 vdec_schedule_work(&hw->work);
7394 }
7395 } else {
7396 av1_print(hw, AOM_DEBUG_HW_MORE,
7397 "PIC_END, fgs_valid %d search head ...\n",
7398 hw->fgs_valid);
7399 WRITE_VREG(HEVC_DEC_STATUS_REG, AOM_AV1_SEARCH_HEAD);
7400#ifdef USE_DEC_PIC_END
7401 if (READ_VREG(PIC_END_LCU_COUNT) != 0) {
7402 hw->frame_decoded = 1;
7403 /*
7404 In c module, multi obus are put in one packet, which is decoded
7405 with av1_receive_compressed_data().
7406 For STREAM_MODE or SINGLE_MODE, there is no packet boundary,
7407 we assume each packet must and only include one picture of data (LCUs)
7408 or cm->show_existing_frame is 1
7409 */
7410 av1_print(hw, AOM_DEBUG_HW_MORE, "Decoding done (index %d)\n",
7411 cm->cur_frame? cm->cur_frame->buf.index:-1);
7412 config_next_ref_info_hw(hw);
7413 }
7414#endif
7415 /*
7416 if (debug &
7417 AV1_DEBUG_BUFMGR_MORE)
7418 dump_aux_buf(hw);
7419 set_aux_data(hw,
7420 &cm->cur_frame->buf, 0, 0);
7421 */
7422 if (hw->low_latency_flag) {
7423 av1_postproc(hw);
7424 vdec_profile(hw_to_vdec(hw), VDEC_PROFILE_EVENT_CB);
7425 if (debug & PRINT_FLAG_VDEC_DETAIL)
7426 pr_info("%s AV1 frame done \n", __func__);
7427 }
7428 }
7429
7430 hw->process_busy = 0;
7431 return IRQ_HANDLED;
7432 }
7433
7434 if (dec_status == AOM_EOS) {
7435 if (hw->m_ins_flag)
7436 reset_process_time(hw);
7437
7438 av1_print(hw, AOM_DEBUG_HW_MORE, "AV1_EOS, flush buffer\r\n");
7439
7440 av1_postproc(hw);
7441
7442 av1_print(hw, AOM_DEBUG_HW_MORE, "send AV1_10B_DISCARD_NAL\r\n");
7443 WRITE_VREG(HEVC_DEC_STATUS_REG, AOM_AV1_DISCARD_NAL);
7444 hw->process_busy = 0;
7445 if (hw->m_ins_flag) {
7446 hw->dec_result = DEC_RESULT_DONE;
7447 amhevc_stop();
7448 vdec_schedule_work(&hw->work);
7449 }
7450 return IRQ_HANDLED;
7451 } else if (dec_status == AOM_DECODE_OVER_SIZE) {
7452 av1_print(hw, AOM_DEBUG_HW_MORE, "av1 decode oversize !!\n");
7453 debug |= (AV1_DEBUG_DIS_LOC_ERROR_PROC |
7454 AV1_DEBUG_DIS_SYS_ERROR_PROC);
7455 hw->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
7456 hw->process_busy = 0;
7457 if (hw->m_ins_flag)
7458 reset_process_time(hw);
7459 return IRQ_HANDLED;
7460 }
7461
7462 obu_type = load_param(hw, &hw->aom_param, dec_status);
7463 if (obu_type < 0) {
7464 hw->process_busy = 0;
7465 return IRQ_HANDLED;
7466 }
7467
7468 if (obu_type == OBU_SEQUENCE_HEADER) {
7469 int next_lcu_size;
7470 av1_bufmgr_process(hw->pbi, &hw->aom_param, 0, obu_type);
7471
7472 bit_depth_luma = hw->aom_param.p.bit_depth;
7473 bit_depth_chroma = hw->aom_param.p.bit_depth;
7474 next_lcu_size = ((hw->aom_param.p.seq_flags >> 6) & 0x1) ? 128 : 64;
7475 hw->video_signal_type = (hw->aom_param.p.video_signal_type << 16
7476 | hw->aom_param.p.color_description);
7477
7478 if (next_lcu_size != hw->current_lcu_size) {
7479 av1_print(hw, AOM_DEBUG_HW_MORE,
7480 " ## lcu_size changed from %d to %d\n",
7481 hw->current_lcu_size, next_lcu_size);
7482 hw->current_lcu_size = next_lcu_size;
7483 }
7484
7485 if (!hw->pic_list_init_done) {
7486#if 0
7487 if (hw->m_ins_flag) {
7488 /* picture list init.*/
7489 hw->dec_result = DEC_INIT_PICLIST;
7490 vdec_schedule_work(&hw->work);
7491 } else
7492#endif
7493 {
7494 init_pic_list(hw);
7495 init_pic_list_hw(hw);
7496#ifndef MV_USE_FIXED_BUF
7497 if (init_mv_buf_list(hw) < 0) {
7498 pr_err("%s: !!!!Error, init_mv_buf_list fail\n", __func__);
7499 }
7500#endif
7501 }
7502 hw->pic_list_init_done = true;
7503 }
7504 av1_print(hw, AOM_DEBUG_HW_MORE,
7505 "AOM_AV1_SEQ_HEAD_PARSER_DONE, search head ...\n");
7506 WRITE_VREG(HEVC_DEC_STATUS_REG, AOM_AV1_SEARCH_HEAD);
7507 hw->process_busy = 0;
7508 return IRQ_HANDLED;
7509 }
7510#ifndef USE_DEC_PIC_END
7511 //if (pbi->wait_buf) {
7512 if (pbi->bufmgr_proc_count > 0) {
7513 if (READ_VREG(PIC_END_LCU_COUNT) != 0) {
7514 hw->frame_decoded = 1;
7515 /*
7516 In c module, multi obus are put in one packet, which is decoded
7517 with av1_receive_compressed_data().
7518 For STREAM_MODE or SINGLE_MODE, there is no packet boundary,
7519 we assume each packet must and only include one picture of data (LCUs)
7520 or cm->show_existing_frame is 1
7521 */
7522 av1_print(hw, AOM_DEBUG_HW_MORE, "Decoding done (index %d)\n",
7523 cm->cur_frame? cm->cur_frame->buf.index:-1);
7524 }
7525 }
7526#endif
7527#if 1
7528/*def CHECK_OBU_REDUNDANT_FRAME_HEADER*/
7529 if (debug & AOM_DEBUG_BUFMGR_ONLY) {
7530 if (READ_VREG(PIC_END_LCU_COUNT) != 0)
7531 hw->obu_frame_frame_head_come_after_tile = 0;
7532
7533 if (obu_type == OBU_FRAME_HEADER ||
7534 obu_type == OBU_FRAME) {
7535 hw->obu_frame_frame_head_come_after_tile = 1;
7536 } else if (obu_type == OBU_REDUNDANT_FRAME_HEADER &&
7537 hw->obu_frame_frame_head_come_after_tile == 0) {
7538 if (hw->frame_decoded == 1) {
7539 av1_print(hw, AOM_DEBUG_HW_MORE,
7540 "Warning, OBU_REDUNDANT_FRAME_HEADER come without OBU_FRAME or OBU_FRAME_HEAD\n");
7541 hw->frame_decoded = 0;
7542 }
7543 }
7544 }
7545#endif
7546 if (hw->frame_decoded)
7547 hw->one_compressed_data_done = 1;
7548
7549 if (hw->m_ins_flag)
7550 reset_process_time(hw);
7551
7552
7553 if (hw->process_state != PROC_STATE_SENDAGAIN
7554 ) {
7555 if (hw->mmu_enable)
7556 av1_recycle_mmu_buf_tail(hw);
7557
7558
7559 if (hw->one_compressed_data_done) {
7560 av1_postproc(hw);
7561 av1_release_bufs(hw);
7562#ifndef MV_USE_FIXED_BUF
7563 put_un_used_mv_bufs(hw);
7564#endif
7565 }
7566 }
7567
7568 av1_continue_decoding(hw, obu_type);
7569 hw->postproc_done = 0;
7570 hw->process_busy = 0;
7571
7572 if (hw->m_ins_flag)
7573 start_process_time(hw);
7574
7575 return IRQ_HANDLED;
7576}
7577
7578static irqreturn_t vav1_isr(int irq, void *data)
7579{
7580 int i;
7581 unsigned int dec_status;
7582 struct AV1HW_s *hw = (struct AV1HW_s *)data;
7583 //struct AV1_Common_s *const cm = &hw->pbi->common;
7584 uint debug_tag;
7585
7586 WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1);
7587
7588 dec_status = READ_VREG(HEVC_DEC_STATUS_REG) & 0xff;
7589 if (!hw)
7590 return IRQ_HANDLED;
7591 if (hw->init_flag == 0)
7592 return IRQ_HANDLED;
7593 if (hw->process_busy)/*on process.*/
7594 return IRQ_HANDLED;
7595 hw->dec_status = dec_status;
7596 hw->process_busy = 1;
7597 if (debug & AV1_DEBUG_BUFMGR)
7598 av1_print(hw, AV1_DEBUG_BUFMGR,
7599 "av1 isr (%d) dec status = 0x%x, lcu 0x%x shiftbyte 0x%x (%x %x lev %x, wr %x, rd %x)\n",
7600 irq,
7601 dec_status, READ_VREG(HEVC_PARSER_LCU_START),
7602 READ_VREG(HEVC_SHIFT_BYTE_COUNT),
7603 READ_VREG(HEVC_STREAM_START_ADDR),
7604 READ_VREG(HEVC_STREAM_END_ADDR),
7605 READ_VREG(HEVC_STREAM_LEVEL),
7606 READ_VREG(HEVC_STREAM_WR_PTR),
7607 READ_VREG(HEVC_STREAM_RD_PTR)
7608 );
7609
7610 debug_tag = READ_HREG(DEBUG_REG1);
7611 if (debug_tag & 0x10000) {
7612 pr_info("LMEM<tag %x>:\n", READ_HREG(DEBUG_REG1));
7613 for (i = 0; i < 0x400; i += 4) {
7614 int ii;
7615 if ((i & 0xf) == 0)
7616 pr_info("%03x: ", i);
7617 for (ii = 0; ii < 4; ii++) {
7618 pr_info("%04x ",
7619 hw->lmem_ptr[i + 3 - ii]);
7620 }
7621 if (((i + ii) & 0xf) == 0)
7622 pr_info("\n");
7623 }
7624 if (((udebug_pause_pos & 0xffff)
7625 == (debug_tag & 0xffff)) &&
7626 (udebug_pause_decode_idx == 0 ||
7627 udebug_pause_decode_idx == hw->result_done_count) &&
7628 (udebug_pause_val == 0 ||
7629 udebug_pause_val == READ_HREG(DEBUG_REG2))) {
7630 udebug_pause_pos &= 0xffff;
7631 hw->ucode_pause_pos = udebug_pause_pos;
7632 }
7633 else if (debug_tag & 0x20000)
7634 hw->ucode_pause_pos = 0xffffffff;
7635 if (hw->ucode_pause_pos)
7636 reset_process_time(hw);
7637 else
7638 WRITE_HREG(DEBUG_REG1, 0);
7639 } else if (debug_tag != 0) {
7640 pr_info(
7641 "dbg%x: %x lcu %x\n", READ_HREG(DEBUG_REG1),
7642 READ_HREG(DEBUG_REG2),
7643 READ_VREG(HEVC_PARSER_LCU_START));
7644
7645 if (((udebug_pause_pos & 0xffff)
7646 == (debug_tag & 0xffff)) &&
7647 (udebug_pause_decode_idx == 0 ||
7648 udebug_pause_decode_idx == hw->result_done_count) &&
7649 (udebug_pause_val == 0 ||
7650 udebug_pause_val == READ_HREG(DEBUG_REG2))) {
7651 udebug_pause_pos &= 0xffff;
7652 hw->ucode_pause_pos = udebug_pause_pos;
7653 }
7654 if (hw->ucode_pause_pos)
7655 reset_process_time(hw);
7656 else
7657 WRITE_HREG(DEBUG_REG1, 0);
7658 hw->process_busy = 0;
7659 return IRQ_HANDLED;
7660 }
7661
7662 //if (READ_VREG(HEVC_FG_STATUS) == AOM_AV1_FGS_PARAM) {
7663 if (hw->dec_status == AOM_AV1_FGS_PARAM) {
7664 uint32_t status_val = READ_VREG(HEVC_FG_STATUS);
7665 WRITE_VREG(HEVC_FG_STATUS, AOM_AV1_FGS_PARAM_CONT);
7666 WRITE_VREG(HEVC_DEC_STATUS_REG, AOM_AV1_FGS_PARAM_CONT);
7667 // Bit[11] - 0 Read, 1 - Write
7668 // Bit[10:8] - film_grain_params_ref_idx // For Write request
7669 if ((status_val >> 11) & 0x1) {
7670 uint32_t film_grain_params_ref_idx = (status_val >> 8) & 0x7;
7671 config_film_grain_reg(hw, film_grain_params_ref_idx);
7672 }
7673 else
7674 read_film_grain_reg(hw);
7675 hw->process_busy = 0;
7676 return IRQ_HANDLED;
7677 }
7678
7679 if (!hw->m_ins_flag) {
7680 av1_print(hw, AV1_DEBUG_BUFMGR,
7681 "error flag = %d\n", hw->error_flag);
7682 if (hw->error_flag == 1) {
7683 hw->error_flag = 2;
7684 hw->process_busy = 0;
7685 return IRQ_HANDLED;
7686 } else if (hw->error_flag == 3) {
7687 hw->process_busy = 0;
7688 return IRQ_HANDLED;
7689 }
7690 }
7691 if (get_free_buf_count(hw) <= 0) {
7692 /*
7693 if (hw->wait_buf == 0)
7694 pr_info("set wait_buf to 1\r\n");
7695 */
7696 hw->wait_buf = 1;
7697 hw->process_busy = 0;
7698 av1_print(hw, AV1_DEBUG_BUFMGR,
7699 "free buf not enough = %d\n",
7700 get_free_buf_count(hw));
7701 return IRQ_HANDLED;
7702 }
7703 return IRQ_WAKE_THREAD;
7704}
7705
7706static void av1_set_clk(struct work_struct *work)
7707{
7708 struct AV1HW_s *hw = container_of(work,
7709 struct AV1HW_s, set_clk_work);
7710 int fps = 96000 / hw->frame_dur;
7711
7712 if (hevc_source_changed(VFORMAT_AV1,
7713 frame_width, frame_height, fps) > 0)
7714 hw->saved_resolution = frame_width *
7715 frame_height * fps;
7716}
7717
7718static void vav1_put_timer_func(unsigned long arg)
7719{
7720 struct AV1HW_s *hw = (struct AV1HW_s *)arg;
7721 struct timer_list *timer = &hw->timer;
7722 uint8_t empty_flag;
7723 unsigned int buf_level;
7724
7725 enum receviver_start_e state = RECEIVER_INACTIVE;
7726
7727 if (hw->m_ins_flag) {
7728 if (hw_to_vdec(hw)->next_status
7729 == VDEC_STATUS_DISCONNECTED) {
7730 hw->dec_result = DEC_RESULT_FORCE_EXIT;
7731 vdec_schedule_work(&hw->work);
7732 pr_debug(
7733 "vdec requested to be disconnected\n");
7734 return;
7735 }
7736 }
7737 if (hw->init_flag == 0) {
7738 if (hw->stat & STAT_TIMER_ARM) {
7739 timer->expires = jiffies + PUT_INTERVAL;
7740 add_timer(&hw->timer);
7741 }
7742 return;
7743 }
7744 if (hw->m_ins_flag == 0) {
7745 if (vf_get_receiver(hw->provider_name)) {
7746 state =
7747 vf_notify_receiver(hw->provider_name,
7748 VFRAME_EVENT_PROVIDER_QUREY_STATE,
7749 NULL);
7750 if ((state == RECEIVER_STATE_NULL)
7751 || (state == RECEIVER_STATE_NONE))
7752 state = RECEIVER_INACTIVE;
7753 } else
7754 state = RECEIVER_INACTIVE;
7755
7756 empty_flag = (READ_VREG(HEVC_PARSER_INT_STATUS) >> 6) & 0x1;
7757 /* error watchdog */
7758 if (empty_flag == 0) {
7759 /* decoder has input */
7760 if ((debug & AV1_DEBUG_DIS_LOC_ERROR_PROC) == 0) {
7761
7762 buf_level = READ_VREG(HEVC_STREAM_LEVEL);
7763 /* receiver has no buffer to recycle */
7764 if ((state == RECEIVER_INACTIVE) &&
7765 (kfifo_is_empty(&hw->display_q) &&
7766 buf_level > 0x200)
7767 ) {
7768 WRITE_VREG
7769 (HEVC_ASSIST_MBOX0_IRQ_REG,
7770 0x1);
7771 }
7772 }
7773
7774 if ((debug & AV1_DEBUG_DIS_SYS_ERROR_PROC) == 0) {
7775 /* receiver has no buffer to recycle */
7776 /*if ((state == RECEIVER_INACTIVE) &&
7777 * (kfifo_is_empty(&hw->display_q))) {
7778 *pr_info("AV1 something error,need reset\n");
7779 *}
7780 */
7781 }
7782 }
7783 }
7784#ifdef MULTI_INSTANCE_SUPPORT
7785 else {
7786 if (
7787 (decode_timeout_val > 0) &&
7788 (hw->start_process_time > 0) &&
7789 ((1000 * (jiffies - hw->start_process_time) / HZ)
7790 > decode_timeout_val)
7791 ) {
7792 int current_lcu_idx =
7793 READ_VREG(HEVC_PARSER_LCU_START)
7794 & 0xffffff;
7795 if (hw->last_lcu_idx == current_lcu_idx) {
7796 if (hw->decode_timeout_count > 0)
7797 hw->decode_timeout_count--;
7798 if (hw->decode_timeout_count == 0) {
7799 if (input_frame_based(
7800 hw_to_vdec(hw)) ||
7801 (READ_VREG(HEVC_STREAM_LEVEL) > 0x200))
7802 timeout_process(hw);
7803 else {
7804 av1_print(hw, 0,
7805 "timeout & empty, again\n");
7806 dec_again_process(hw);
7807 }
7808 }
7809 } else {
7810 start_process_time(hw);
7811 hw->last_lcu_idx = current_lcu_idx;
7812 }
7813 }
7814 }
7815#endif
7816
7817 if ((hw->ucode_pause_pos != 0) &&
7818 (hw->ucode_pause_pos != 0xffffffff) &&
7819 udebug_pause_pos != hw->ucode_pause_pos) {
7820 hw->ucode_pause_pos = 0;
7821 WRITE_HREG(DEBUG_REG1, 0);
7822 }
7823#ifdef MULTI_INSTANCE_SUPPORT
7824 if (debug & AV1_DEBUG_FORCE_SEND_AGAIN) {
7825 av1_print(hw, AOM_DEBUG_HW_MORE,
7826 "Force Send Again\r\n");
7827 debug &= ~AV1_DEBUG_FORCE_SEND_AGAIN;
7828 reset_process_time(hw);
7829 hw->dec_result = DEC_RESULT_AGAIN;
7830 if (hw->process_state ==
7831 PROC_STATE_DECODESLICE) {
7832 if (hw->mmu_enable)
7833 av1_recycle_mmu_buf(hw);
7834 hw->process_state =
7835 PROC_STATE_SENDAGAIN;
7836 }
7837 amhevc_stop();
7838
7839 vdec_schedule_work(&hw->work);
7840 }
7841
7842 if (debug & AV1_DEBUG_DUMP_DATA) {
7843 debug &= ~AV1_DEBUG_DUMP_DATA;
7844 av1_print(hw, 0,
7845 "%s: chunk size 0x%x off 0x%x sum 0x%x\n",
7846 __func__,
7847 hw->chunk->size,
7848 hw->chunk->offset,
7849 get_data_check_sum(hw, hw->chunk->size)
7850 );
7851 dump_data(hw, hw->chunk->size);
7852 }
7853#endif
7854 if (debug & AV1_DEBUG_DUMP_PIC_LIST) {
7855 /*dump_pic_list(hw);*/
7856 av1_dump_state(hw_to_vdec(hw));
7857 debug &= ~AV1_DEBUG_DUMP_PIC_LIST;
7858 }
7859 if (debug & AV1_DEBUG_TRIG_SLICE_SEGMENT_PROC) {
7860 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1);
7861 debug &= ~AV1_DEBUG_TRIG_SLICE_SEGMENT_PROC;
7862 }
7863 /*if (debug & AV1_DEBUG_HW_RESET) {
7864 }*/
7865
7866 if (radr != 0) {
7867 if ((radr >> 24) != 0) {
7868 int count = radr >> 24;
7869 int adr = radr & 0xffffff;
7870 int i;
7871 for (i = 0; i < count; i++)
7872 pr_info("READ_VREG(%x)=%x\n", adr+i, READ_VREG(adr+i));
7873 } else if (rval != 0) {
7874 WRITE_VREG(radr, rval);
7875 pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
7876 } else
7877 pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
7878 rval = 0;
7879 radr = 0;
7880 }
7881 if (pop_shorts != 0) {
7882 int i;
7883 u32 sum = 0;
7884
7885 pr_info("pop stream 0x%x shorts\r\n", pop_shorts);
7886 for (i = 0; i < pop_shorts; i++) {
7887 u32 data =
7888 (READ_HREG(HEVC_SHIFTED_DATA) >> 16);
7889 WRITE_HREG(HEVC_SHIFT_COMMAND,
7890 (1<<7)|16);
7891 if ((i & 0xf) == 0)
7892 pr_info("%04x:", i);
7893 pr_info("%04x ", data);
7894 if (((i + 1) & 0xf) == 0)
7895 pr_info("\r\n");
7896 sum += data;
7897 }
7898 pr_info("\r\nsum = %x\r\n", sum);
7899 pop_shorts = 0;
7900 }
7901 if (dbg_cmd != 0) {
7902 if (dbg_cmd == 1) {
7903 u32 disp_laddr;
7904
7905 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXBB &&
7906 get_double_write_mode(hw) == 0) {
7907 disp_laddr =
7908 READ_VCBUS_REG(AFBC_BODY_BADDR) << 4;
7909 } else {
7910 struct canvas_s cur_canvas;
7911
7912 canvas_read((READ_VCBUS_REG(VD1_IF0_CANVAS0)
7913 & 0xff), &cur_canvas);
7914 disp_laddr = cur_canvas.addr;
7915 }
7916 pr_info("current displayed buffer address %x\r\n",
7917 disp_laddr);
7918 }
7919 dbg_cmd = 0;
7920 }
7921 /*don't changed at start.*/
7922 if (hw->get_frame_dur && hw->show_frame_num > 60 &&
7923 hw->frame_dur > 0 && hw->saved_resolution !=
7924 frame_width * frame_height *
7925 (96000 / hw->frame_dur))
7926 vdec_schedule_work(&hw->set_clk_work);
7927
7928 timer->expires = jiffies + PUT_INTERVAL;
7929 add_timer(timer);
7930}
7931
7932
7933int vav1_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
7934{
7935 struct AV1HW_s *av1 =
7936 (struct AV1HW_s *)vdec->private;
7937
7938 if (!av1)
7939 return -1;
7940
7941 vstatus->frame_width = frame_width;
7942 vstatus->frame_height = frame_height;
7943 if (av1->frame_dur != 0)
7944 vstatus->frame_rate = 96000 / av1->frame_dur;
7945 else
7946 vstatus->frame_rate = -1;
7947 vstatus->error_count = 0;
7948 vstatus->status = av1->stat | av1->fatal_error;
7949 vstatus->frame_dur = av1->frame_dur;
7950#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
7951 vstatus->bit_rate = gvs->bit_rate;
7952 vstatus->frame_data = gvs->frame_data;
7953 vstatus->total_data = gvs->total_data;
7954 vstatus->frame_count = gvs->frame_count;
7955 vstatus->error_frame_count = gvs->error_frame_count;
7956 vstatus->drop_frame_count = gvs->drop_frame_count;
7957 vstatus->total_data = gvs->total_data;
7958 vstatus->samp_cnt = gvs->samp_cnt;
7959 vstatus->offset = gvs->offset;
7960 snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
7961 "%s", DRIVER_NAME);
7962#endif
7963 return 0;
7964}
7965
7966int vav1_set_isreset(struct vdec_s *vdec, int isreset)
7967{
7968 is_reset = isreset;
7969 return 0;
7970}
7971
7972#if 0
7973static void AV1_DECODE_INIT(void)
7974{
7975 /* enable av1 clocks */
7976 WRITE_VREG(DOS_GCLK_EN3, 0xffffffff);
7977 /* *************************************************************** */
7978 /* Power ON HEVC */
7979 /* *************************************************************** */
7980 /* Powerup HEVC */
7981 WRITE_VREG(AO_RTI_GEN_PWR_SLEEP0,
7982 READ_VREG(AO_RTI_GEN_PWR_SLEEP0) & (~(0x3 << 6)));
7983 WRITE_VREG(DOS_MEM_PD_HEVC, 0x0);
7984 WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) | (0x3ffff << 2));
7985 WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) & (~(0x3ffff << 2)));
7986 /* remove isolations */
7987 WRITE_VREG(AO_RTI_GEN_PWR_ISO0,
7988 READ_VREG(AO_RTI_GEN_PWR_ISO0) & (~(0x3 << 10)));
7989
7990}
7991#endif
7992
7993static void vav1_prot_init(struct AV1HW_s *hw, u32 mask)
7994{
7995 unsigned int data32;
7996 /* AV1_DECODE_INIT(); */
7997 av1_print(hw, AOM_DEBUG_HW_MORE, "%s %d\n", __func__, __LINE__);
7998
7999 aom_config_work_space_hw(hw, mask);
8000 if (mask & HW_MASK_BACK) {
8001 //to do: .. for single instance, called after init_pic_list()
8002 if (hw->m_ins_flag)
8003 init_pic_list_hw(hw);
8004 }
8005
8006 aom_init_decoder_hw(hw, mask);
8007
8008#ifdef AOM_AV1_DBLK_INIT
8009 av1_print(hw, AOM_DEBUG_HW_MORE,
8010 "[test.c] av1_loop_filter_init (run once before decoding start)\n");
8011 av1_loop_filter_init(hw->lfi, hw->lf);
8012#endif
8013 if ((mask & HW_MASK_FRONT) == 0)
8014 return;
8015#if 1
8016 if (debug & AV1_DEBUG_BUFMGR_MORE)
8017 pr_info("%s\n", __func__);
8018 data32 = READ_VREG(HEVC_STREAM_CONTROL);
8019 data32 = data32 |
8020 (1 << 0)/*stream_fetch_enable*/
8021 ;
8022 WRITE_VREG(HEVC_STREAM_CONTROL, data32);
8023
8024 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
8025 if (debug & AV1_DEBUG_BUFMGR)
8026 pr_info("[test.c] Config STREAM_FIFO_CTL\n");
8027 data32 = READ_VREG(HEVC_STREAM_FIFO_CTL);
8028 data32 = data32 |
8029 (1 << 29) // stream_fifo_hole
8030 ;
8031 WRITE_VREG(HEVC_STREAM_FIFO_CTL, data32);
8032 }
8033#if 0
8034 data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
8035 if (data32 != 0x00000100) {
8036 pr_info("av1 prot init error %d\n", __LINE__);
8037 return;
8038 }
8039 data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
8040 if (data32 != 0x00000300) {
8041 pr_info("av1 prot init error %d\n", __LINE__);
8042 return;
8043 }
8044 WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x12345678);
8045 WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x9abcdef0);
8046 data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
8047 if (data32 != 0x12345678) {
8048 pr_info("av1 prot init error %d\n", __LINE__);
8049 return;
8050 }
8051 data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
8052 if (data32 != 0x9abcdef0) {
8053 pr_info("av1 prot init error %d\n", __LINE__);
8054 return;
8055 }
8056#endif
8057 WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x000000001);
8058 WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x00000300);
8059#endif
8060
8061
8062
8063 WRITE_VREG(HEVC_WAIT_FLAG, 1);
8064
8065 /* WRITE_VREG(HEVC_MPSR, 1); */
8066
8067 /* clear mailbox interrupt */
8068 WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1);
8069
8070 /* enable mailbox interrupt */
8071 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 1);
8072
8073 /* disable PSCALE for hardware sharing */
8074 WRITE_VREG(HEVC_PSCALE_CTRL, 0);
8075
8076 WRITE_VREG(DEBUG_REG1, 0x0);
8077 /*check vps/sps/pps/i-slice in ucode*/
8078 WRITE_VREG(NAL_SEARCH_CTL, 0x8);
8079
8080 WRITE_VREG(DECODE_STOP_POS, udebug_flag);
8081}
8082
8083static int vav1_local_init(struct AV1HW_s *hw)
8084{
8085 int i;
8086 int ret;
8087 int width, height;
8088
8089 hw->gvs = vzalloc(sizeof(struct vdec_info));
8090 if (NULL == hw->gvs) {
8091 pr_info("the struct of vdec status malloc failed.\n");
8092 return -1;
8093 }
8094#ifdef DEBUG_PTS
8095 hw->pts_missed = 0;
8096 hw->pts_hit = 0;
8097#endif
8098 hw->new_frame_displayed = 0;
8099 hw->last_put_idx = -1;
8100 hw->saved_resolution = 0;
8101 hw->get_frame_dur = false;
8102 on_no_keyframe_skiped = 0;
8103 hw->duration_from_pts_done = 0;
8104 hw->av1_first_pts_ready = 0;
8105 hw->frame_cnt_window = 0;
8106 width = hw->vav1_amstream_dec_info.width;
8107 height = hw->vav1_amstream_dec_info.height;
8108 hw->frame_dur =
8109 (hw->vav1_amstream_dec_info.rate ==
8110 0) ? 3200 : hw->vav1_amstream_dec_info.rate;
8111 if (width && height)
8112 hw->frame_ar = height * 0x100 / width;
8113/*
8114 *TODO:FOR VERSION
8115 */
8116 pr_info("av1: ver (%d,%d) decinfo: %dx%d rate=%d\n", av1_version,
8117 0, width, height, hw->frame_dur);
8118
8119 if (hw->frame_dur == 0)
8120 hw->frame_dur = 96000 / 24;
8121
8122 INIT_KFIFO(hw->display_q);
8123 INIT_KFIFO(hw->newframe_q);
8124
8125
8126 for (i = 0; i < VF_POOL_SIZE; i++) {
8127 const struct vframe_s *vf = &hw->vfpool[i];
8128
8129 hw->vfpool[i].index = -1;
8130 kfifo_put(&hw->newframe_q, vf);
8131 }
8132
8133
8134 ret = av1_local_init(hw);
8135
8136 if (force_pts_unstable) {
8137 if (!hw->pts_unstable) {
8138 hw->pts_unstable =
8139 (hw->vav1_amstream_dec_info.rate == 0)?1:0;
8140 pr_info("set pts unstable\n");
8141 }
8142 }
8143 return ret;
8144}
8145
8146
8147#ifdef MULTI_INSTANCE_SUPPORT
8148static s32 vav1_init(struct vdec_s *vdec)
8149{
8150 struct AV1HW_s *hw = (struct AV1HW_s *)vdec->private;
8151#else
8152static s32 vav1_init(struct AV1HW_s *hw)
8153{
8154#endif
8155 int ret;
8156 int fw_size = 0x1000 * 16;
8157 struct firmware_s *fw = NULL;
8158
8159 hw->stat |= STAT_TIMER_INIT;
8160
8161 if (vav1_local_init(hw) < 0)
8162 return -EBUSY;
8163
8164 fw = vmalloc(sizeof(struct firmware_s) + fw_size);
8165 if (IS_ERR_OR_NULL(fw))
8166 return -ENOMEM;
8167
8168 av1_print(hw, AOM_DEBUG_HW_MORE, "%s %d\n", __func__, __LINE__);
8169#ifdef DEBUG_USE_VP9_DEVICE_NAME
8170 if (get_firmware_data(VIDEO_DEC_VP9_MMU, fw->data) < 0) {
8171#else
8172 if (get_firmware_data(VIDEO_DEC_AV1_MMU, fw->data) < 0) {
8173#endif
8174 pr_err("get firmware fail.\n");
8175 printk("%s %d\n", __func__, __LINE__);
8176 vfree(fw);
8177 return -1;
8178 }
8179 av1_print(hw, AOM_DEBUG_HW_MORE, "%s %d\n", __func__, __LINE__);
8180
8181 fw->len = fw_size;
8182
8183 INIT_WORK(&hw->set_clk_work, av1_set_clk);
8184 init_timer(&hw->timer);
8185
8186#ifdef MULTI_INSTANCE_SUPPORT
8187 if (hw->m_ins_flag) {
8188 hw->timer.data = (ulong) hw;
8189 hw->timer.function = vav1_put_timer_func;
8190 hw->timer.expires = jiffies + PUT_INTERVAL;
8191
8192 /*add_timer(&hw->timer);
8193
8194 hw->stat |= STAT_TIMER_ARM;
8195 hw->stat |= STAT_ISR_REG;*/
8196
8197 INIT_WORK(&hw->work, av1_work);
8198 hw->fw = fw;
8199
8200 return 0; /*multi instance return */
8201 }
8202#endif
8203 amhevc_enable();
8204
8205 ret = amhevc_loadmc_ex(VFORMAT_AV1, NULL, fw->data);
8206 if (ret < 0) {
8207 amhevc_disable();
8208 vfree(fw);
8209 pr_err("AV1: the %s fw loading failed, err: %x\n",
8210 tee_enabled() ? "TEE" : "local", ret);
8211 return -EBUSY;
8212 }
8213
8214 vfree(fw);
8215
8216 hw->stat |= STAT_MC_LOAD;
8217
8218 /* enable AMRISC side protocol */
8219 vav1_prot_init(hw, HW_MASK_FRONT | HW_MASK_BACK);
8220
8221 if (vdec_request_threaded_irq(VDEC_IRQ_0,
8222 vav1_isr,
8223 vav1_isr_thread_fn,
8224 IRQF_ONESHOT,/*run thread on this irq disabled*/
8225 "vav1-irq", (void *)hw)) {
8226 pr_info("vav1 irq register error.\n");
8227 amhevc_disable();
8228 return -ENOENT;
8229 }
8230
8231 hw->stat |= STAT_ISR_REG;
8232
8233 if (force_dv_enable)
8234 hw->provider_name = DV_PROVIDER_NAME;
8235 else
8236 hw->provider_name = PROVIDER_NAME;
8237#ifdef MULTI_INSTANCE_SUPPORT
8238 vf_provider_init(&vav1_vf_prov, hw->provider_name,
8239 &vav1_vf_provider, hw);
8240 vf_reg_provider(&vav1_vf_prov);
8241 vf_notify_receiver(hw->provider_name, VFRAME_EVENT_PROVIDER_START, NULL);
8242 if (hw->frame_dur != 0) {
8243 if (!is_reset)
8244 vf_notify_receiver(hw->provider_name,
8245 VFRAME_EVENT_PROVIDER_FR_HINT,
8246 (void *)
8247 ((unsigned long)hw->frame_dur));
8248 }
8249#else
8250 vf_provider_init(&vav1_vf_prov, hw->provider_name, &vav1_vf_provider,
8251 hw);
8252 vf_reg_provider(&vav1_vf_prov);
8253 vf_notify_receiver(hw->provider_name, VFRAME_EVENT_PROVIDER_START, NULL);
8254 if (!is_reset)
8255 vf_notify_receiver(hw->provider_name, VFRAME_EVENT_PROVIDER_FR_HINT,
8256 (void *)((unsigned long)hw->frame_dur));
8257#endif
8258 hw->stat |= STAT_VF_HOOK;
8259
8260 hw->timer.data = (ulong)hw;
8261 hw->timer.function = vav1_put_timer_func;
8262 hw->timer.expires = jiffies + PUT_INTERVAL;
8263
8264 hw->stat |= STAT_VDEC_RUN;
8265
8266 add_timer(&hw->timer);
8267
8268 hw->stat |= STAT_TIMER_ARM;
8269
8270 amhevc_start();
8271
8272 hw->init_flag = 1;
8273 hw->process_busy = 0;
8274 pr_info("%d, vav1_init, RP=0x%x\n",
8275 __LINE__, READ_VREG(HEVC_STREAM_RD_PTR));
8276 return 0;
8277}
8278
8279static int vmav1_stop(struct AV1HW_s *hw)
8280{
8281 hw->init_flag = 0;
8282
8283 if (hw->stat & STAT_VDEC_RUN) {
8284 amhevc_stop();
8285 hw->stat &= ~STAT_VDEC_RUN;
8286 }
8287 if (hw->stat & STAT_ISR_REG) {
8288 vdec_free_irq(VDEC_IRQ_0, (void *)hw);
8289 hw->stat &= ~STAT_ISR_REG;
8290 }
8291 if (hw->stat & STAT_TIMER_ARM) {
8292 del_timer_sync(&hw->timer);
8293 hw->stat &= ~STAT_TIMER_ARM;
8294 }
8295
8296 if (hw->stat & STAT_VF_HOOK) {
8297 if (!is_reset)
8298 vf_notify_receiver(hw->provider_name,
8299 VFRAME_EVENT_PROVIDER_FR_END_HINT,
8300 NULL);
8301
8302 vf_unreg_provider(&vav1_vf_prov);
8303 hw->stat &= ~STAT_VF_HOOK;
8304 }
8305 av1_local_uninit(hw);
8306 reset_process_time(hw);
8307 cancel_work_sync(&hw->work);
8308 cancel_work_sync(&hw->set_clk_work);
8309 uninit_mmu_buffers(hw);
8310 if (hw->fw)
8311 vfree(hw->fw);
8312 hw->fw = NULL;
8313 return 0;
8314}
8315
8316static int vav1_stop(struct AV1HW_s *hw)
8317{
8318
8319 hw->init_flag = 0;
8320 hw->first_sc_checked = 0;
8321 if (hw->stat & STAT_VDEC_RUN) {
8322 amhevc_stop();
8323 hw->stat &= ~STAT_VDEC_RUN;
8324 }
8325
8326 if (hw->stat & STAT_ISR_REG) {
8327#ifdef MULTI_INSTANCE_SUPPORT
8328 if (!hw->m_ins_flag)
8329#endif
8330 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0);
8331 vdec_free_irq(VDEC_IRQ_0, (void *)hw);
8332 hw->stat &= ~STAT_ISR_REG;
8333 }
8334
8335 if (hw->stat & STAT_TIMER_ARM) {
8336 del_timer_sync(&hw->timer);
8337 hw->stat &= ~STAT_TIMER_ARM;
8338 }
8339
8340 if (hw->stat & STAT_VF_HOOK) {
8341 if (!is_reset)
8342 vf_notify_receiver(hw->provider_name,
8343 VFRAME_EVENT_PROVIDER_FR_END_HINT,
8344 NULL);
8345
8346 vf_unreg_provider(&vav1_vf_prov);
8347 hw->stat &= ~STAT_VF_HOOK;
8348 }
8349 av1_local_uninit(hw);
8350
8351 cancel_work_sync(&hw->set_clk_work);
8352#ifdef MULTI_INSTANCE_SUPPORT
8353 if (hw->m_ins_flag) {
8354 cancel_work_sync(&hw->work);
8355 } else
8356 amhevc_disable();
8357#else
8358 amhevc_disable();
8359#endif
8360 uninit_mmu_buffers(hw);
8361
8362 vfree(hw->fw);
8363 hw->fw = NULL;
8364 return 0;
8365}
8366static int amvdec_av1_mmu_init(struct AV1HW_s *hw)
8367{
8368 int tvp_flag = vdec_secure(hw_to_vdec(hw)) ?
8369 CODEC_MM_FLAGS_TVP : 0;
8370 int buf_size = 48;
8371
8372 if ((hw->max_pic_w * hw->max_pic_h > 1280*736) &&
8373 (hw->max_pic_w * hw->max_pic_h <= 1920*1088)) {
8374 buf_size = 12;
8375 } else if ((hw->max_pic_w * hw->max_pic_h > 0) &&
8376 (hw->max_pic_w * hw->max_pic_h <= 1280*736)) {
8377 buf_size = 4;
8378 }
8379 hw->need_cache_size = buf_size * SZ_1M;
8380 hw->sc_start_time = get_jiffies_64();
8381 if (hw->mmu_enable && ((hw->double_write_mode & 0x10) == 0)) {
8382 int count = FRAME_BUFFERS;
8383 hw->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME,
8384 hw->index /* * 2*/, count,
8385 hw->need_cache_size,
8386 tvp_flag
8387 );
8388 if (!hw->mmu_box) {
8389 pr_err("av1 alloc mmu box failed!!\n");
8390 return -1;
8391 }
8392#ifdef AOM_AV1_MMU_DW
8393 if (hw->dw_mmu_enable) {
8394 hw->mmu_box_dw = decoder_mmu_box_alloc_box(DRIVER_NAME,
8395 hw->index /** 2 + 1*/, count,
8396 hw->need_cache_size,
8397 tvp_flag
8398 );
8399 if (!hw->mmu_box_dw) {
8400 pr_err("av1 alloc dw mmu box failed!!\n");
8401 return -1;
8402 }
8403 }
8404#endif
8405
8406 }
8407 hw->bmmu_box = decoder_bmmu_box_alloc_box(
8408 DRIVER_NAME,
8409 hw->index,
8410 MAX_BMMU_BUFFER_NUM,
8411 4 + PAGE_SHIFT,
8412 CODEC_MM_FLAGS_CMA_CLEAR |
8413 CODEC_MM_FLAGS_FOR_VDECODER |
8414 tvp_flag);
8415 av1_print(hw, AV1_DEBUG_BUFMGR,
8416 "%s, MAX_BMMU_BUFFER_NUM = %d\n",
8417 __func__,
8418 MAX_BMMU_BUFFER_NUM);
8419 if (!hw->bmmu_box) {
8420 pr_err("av1 alloc bmmu box failed!!\n");
8421 return -1;
8422 }
8423 return 0;
8424}
8425
8426static struct AV1HW_s *gHevc;
8427
8428
8429static int amvdec_av1_probe(struct platform_device *pdev)
8430{
8431 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
8432 struct BUF_s BUF[MAX_BUF_NUM];
8433 struct AV1HW_s *hw;
8434 AV1Decoder *pbi;
8435 int ret;
8436#ifndef MULTI_INSTANCE_SUPPORT
8437 int i;
8438#endif
8439 pr_debug("%s\n", __func__);
8440
8441 mutex_lock(&vav1_mutex);
8442 hw = vmalloc(sizeof(struct AV1HW_s));
8443 if (hw == NULL) {
8444 av1_print(hw, 0, "\namvdec_av1 device data allocation failed\n");
8445 mutex_unlock(&vav1_mutex);
8446 return -ENOMEM;
8447 }
8448
8449 gHevc = hw;
8450 memcpy(&BUF[0], &hw->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
8451 memset(hw, 0, sizeof(struct AV1HW_s));
8452 memcpy(&hw->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
8453
8454 if (init_dblk_struc(hw) < 0) {
8455 av1_print(hw, 0, "\nammvdec_av1 device data allocation failed\n");
8456 vfree(hw);
8457 return -ENOMEM;
8458 }
8459
8460 pbi = av1_decoder_create(&hw->av1_buffer_pool); //&aom_decoder;
8461 hw->pbi = pbi;
8462 if (hw->pbi == NULL) {
8463 pr_info("\nammvdec_av1 device data allocation failed\n");
8464 release_dblk_struct(hw);
8465 vfree(hw);
8466 return -ENOMEM;
8467 }
8468 //hw->pbi->common.buffer_pool = &hw->av1_buffer_pool; //????
8469 hw->pbi->private_data = hw;
8470
8471 hw->init_flag = 0;
8472 hw->first_sc_checked= 0;
8473 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
8474 av1_max_pic_w = 8192;
8475 av1_max_pic_h = 4608;
8476 }
8477 hw->max_pic_w = av1_max_pic_w;
8478 hw->max_pic_h = av1_max_pic_h;
8479
8480#ifdef MULTI_INSTANCE_SUPPORT
8481 hw->eos = 0;
8482 hw->start_process_time = 0;
8483 hw->timeout_num = 0;
8484#endif
8485 hw->fatal_error = 0;
8486 hw->show_frame_num = 0;
8487 if (pdata == NULL) {
8488 av1_print(hw, 0, "\namvdec_av1 memory resource undefined.\n");
8489 vfree(hw);
8490 mutex_unlock(&vav1_mutex);
8491 return -EFAULT;
8492 }
8493 hw->m_ins_flag = 0;
8494#ifdef MULTI_INSTANCE_SUPPORT
8495 hw->platform_dev = pdev;
8496 platform_set_drvdata(pdev, pdata);
8497#endif
8498 hw->double_write_mode = double_write_mode;
8499 hw->mmu_enable = 1;
8500#ifdef AOM_AV1_MMU_DW
8501 hw->dw_mmu_enable =
8502 get_double_write_mode_init(hw) & 0x20 ? 1 : 0;
8503#endif
8504 if (amvdec_av1_mmu_init(hw) < 0) {
8505 vfree(hw);
8506 mutex_unlock(&vav1_mutex);
8507 pr_err("av1 alloc bmmu box failed!!\n");
8508 return -1;
8509 }
8510
8511 ret = decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, WORK_SPACE_BUF_ID,
8512 work_buf_size, DRIVER_NAME, &pdata->mem_start);
8513 if (ret < 0) {
8514 uninit_mmu_buffers(hw);
8515 vfree(hw);
8516 mutex_unlock(&vav1_mutex);
8517 return ret;
8518 }
8519 hw->buf_size = work_buf_size;
8520
8521#ifdef MULTI_INSTANCE_SUPPORT
8522 hw->buf_start = pdata->mem_start;
8523#else
8524 if (!hw->mmu_enable)
8525 hw->mc_buf_spec.buf_end = pdata->mem_start + hw->buf_size;
8526
8527 for (i = 0; i < WORK_BUF_SPEC_NUM; i++)
8528 aom_workbuff_spec[i].start_adr = pdata->mem_start;
8529#endif
8530
8531 if (debug) {
8532 av1_print(hw, AOM_DEBUG_HW_MORE, "===AV1 decoder mem resource 0x%lx size 0x%x\n",
8533 pdata->mem_start, hw->buf_size);
8534 }
8535
8536 if (pdata->sys_info)
8537 hw->vav1_amstream_dec_info = *pdata->sys_info;
8538 else {
8539 hw->vav1_amstream_dec_info.width = 0;
8540 hw->vav1_amstream_dec_info.height = 0;
8541 hw->vav1_amstream_dec_info.rate = 30;
8542 }
8543 hw->no_head = no_head;
8544#ifdef MULTI_INSTANCE_SUPPORT
8545 hw->cma_dev = pdata->cma_dev;
8546#else
8547 cma_dev = pdata->cma_dev;
8548#endif
8549
8550#ifdef MULTI_INSTANCE_SUPPORT
8551 pdata->private = hw;
8552 pdata->dec_status = vav1_dec_status;
8553 pdata->set_isreset = vav1_set_isreset;
8554 is_reset = 0;
8555 if (vav1_init(pdata) < 0) {
8556#else
8557 if (vav1_init(hw) < 0) {
8558#endif
8559 av1_print(hw, 0, "\namvdec_av1 init failed.\n");
8560 av1_local_uninit(hw);
8561 uninit_mmu_buffers(hw);
8562 vfree(hw);
8563 pdata->dec_status = NULL;
8564 mutex_unlock(&vav1_mutex);
8565 return -ENODEV;
8566 }
8567 /*set the max clk for smooth playing...*/
8568 hevc_source_changed(VFORMAT_AV1,
8569 4096, 2048, 60);
8570 mutex_unlock(&vav1_mutex);
8571
8572 return 0;
8573}
8574
8575static int amvdec_av1_remove(struct platform_device *pdev)
8576{
8577 struct AV1HW_s *hw = gHevc;
8578 struct vdec_s *vdec = hw_to_vdec(hw);
8579 int i;
8580
8581 if (debug)
8582 av1_print(hw, AOM_DEBUG_HW_MORE, "amvdec_av1_remove\n");
8583
8584 mutex_lock(&vav1_mutex);
8585
8586 vav1_stop(hw);
8587
8588 hevc_source_changed(VFORMAT_AV1, 0, 0, 0);
8589
8590 if (vdec->parallel_dec == 1) {
8591 for (i = 0; i < FRAME_BUFFERS; i++) {
8592 vdec->free_canvas_ex(hw->pbi->common.buffer_pool->
8593 frame_bufs[i].buf.y_canvas_index, vdec->id);
8594 vdec->free_canvas_ex(hw->pbi->common.buffer_pool->
8595 frame_bufs[i].buf.uv_canvas_index, vdec->id);
8596 }
8597 }
8598
8599#ifdef DEBUG_PTS
8600 pr_info("pts missed %ld, pts hit %ld, duration %d\n",
8601 hw->pts_missed, hw->pts_hit, hw->frame_dur);
8602#endif
8603 vfree(hw->pbi);
8604 release_dblk_struct(hw);
8605 vfree(hw);
8606 mutex_unlock(&vav1_mutex);
8607
8608 return 0;
8609}
8610
8611/****************************************/
8612#ifdef CONFIG_PM
8613static int av1_suspend(struct device *dev)
8614{
8615 amhevc_suspend(to_platform_device(dev), dev->power.power_state);
8616 return 0;
8617}
8618
8619static int av1_resume(struct device *dev)
8620{
8621 amhevc_resume(to_platform_device(dev));
8622 return 0;
8623}
8624
8625static const struct dev_pm_ops av1_pm_ops = {
8626 SET_SYSTEM_SLEEP_PM_OPS(av1_suspend, av1_resume)
8627};
8628#endif
8629
8630static struct platform_driver amvdec_av1_driver = {
8631 .probe = amvdec_av1_probe,
8632 .remove = amvdec_av1_remove,
8633 .driver = {
8634 .name = DRIVER_NAME,
8635#ifdef CONFIG_PM
8636 .pm = &av1_pm_ops,
8637#endif
8638 }
8639};
8640
8641static struct codec_profile_t amvdec_av1_profile = {
8642#ifdef DEBUG_USE_VP9_DEVICE_NAME
8643 .name = "vp9",
8644#else
8645 .name = "av1",
8646#endif
8647 .profile = ""
8648};
8649
8650static struct codec_profile_t amvdec_av1_profile_mult;
8651
8652static unsigned char get_data_check_sum
8653 (struct AV1HW_s *hw, int size)
8654{
8655 int jj;
8656 int sum = 0;
8657 u8 *data = NULL;
8658
8659 if (!hw->chunk->block->is_mapped)
8660 data = codec_mm_vmap(hw->chunk->block->start +
8661 hw->chunk->offset, size);
8662 else
8663 data = ((u8 *)hw->chunk->block->start_virt) +
8664 hw->chunk->offset;
8665
8666 for (jj = 0; jj < size; jj++)
8667 sum += data[jj];
8668
8669 if (!hw->chunk->block->is_mapped)
8670 codec_mm_unmap_phyaddr(data);
8671 return sum;
8672}
8673
8674static void dump_data(struct AV1HW_s *hw, int size)
8675{
8676 int jj;
8677 u8 *data = NULL;
8678 int padding_size = hw->chunk->offset &
8679 (VDEC_FIFO_ALIGN - 1);
8680
8681 if (!hw->chunk->block->is_mapped)
8682 data = codec_mm_vmap(hw->chunk->block->start +
8683 hw->chunk->offset, size);
8684 else
8685 data = ((u8 *)hw->chunk->block->start_virt) +
8686 hw->chunk->offset;
8687
8688 av1_print(hw, 0, "padding: ");
8689 for (jj = padding_size; jj > 0; jj--)
8690 av1_print_cont(hw,
8691 0,
8692 "%02x ", *(data - jj));
8693 av1_print_cont(hw, 0, "data adr %p\n",
8694 data);
8695
8696 for (jj = 0; jj < size; jj++) {
8697 if ((jj & 0xf) == 0)
8698 av1_print(hw,
8699 0,
8700 "%06x:", jj);
8701 av1_print_cont(hw,
8702 0,
8703 "%02x ", data[jj]);
8704 if (((jj + 1) & 0xf) == 0)
8705 av1_print(hw,
8706 0,
8707 "\n");
8708 }
8709 av1_print(hw,
8710 0,
8711 "\n");
8712
8713 if (!hw->chunk->block->is_mapped)
8714 codec_mm_unmap_phyaddr(data);
8715}
8716
8717static void av1_work(struct work_struct *work)
8718{
8719 struct AV1HW_s *hw = container_of(work,
8720 struct AV1HW_s, work);
8721 struct vdec_s *vdec = hw_to_vdec(hw);
8722 /* finished decoding one frame or error,
8723 * notify vdec core to switch context
8724 */
8725 av1_print(hw, PRINT_FLAG_VDEC_DETAIL,
8726 "%s dec_result %d %x %x %x\n",
8727 __func__,
8728 hw->dec_result,
8729 READ_VREG(HEVC_STREAM_LEVEL),
8730 READ_VREG(HEVC_STREAM_WR_PTR),
8731 READ_VREG(HEVC_STREAM_RD_PTR));
8732 if (((hw->dec_result == DEC_RESULT_GET_DATA) ||
8733 (hw->dec_result == DEC_RESULT_GET_DATA_RETRY))
8734 && (hw_to_vdec(hw)->next_status !=
8735 VDEC_STATUS_DISCONNECTED)) {
8736 if (!vdec_has_more_input(vdec)) {
8737 hw->dec_result = DEC_RESULT_EOS;
8738 vdec_schedule_work(&hw->work);
8739 return;
8740 }
8741
8742 if (hw->dec_result == DEC_RESULT_GET_DATA) {
8743 av1_print(hw, PRINT_FLAG_VDEC_STATUS,
8744 "%s DEC_RESULT_GET_DATA %x %x %x\n",
8745 __func__,
8746 READ_VREG(HEVC_STREAM_LEVEL),
8747 READ_VREG(HEVC_STREAM_WR_PTR),
8748 READ_VREG(HEVC_STREAM_RD_PTR));
8749 vdec_vframe_dirty(vdec, hw->chunk);
8750 vdec_clean_input(vdec);
8751 }
8752
8753 if (get_free_buf_count(hw) >=
8754 run_ready_min_buf_num) {
8755 int r;
8756 int decode_size;
8757 r = vdec_prepare_input(vdec, &hw->chunk);
8758 if (r < 0) {
8759 hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
8760
8761 av1_print(hw,
8762 PRINT_FLAG_VDEC_DETAIL,
8763 "amvdec_vh265: Insufficient data\n");
8764
8765 vdec_schedule_work(&hw->work);
8766 return;
8767 }
8768 hw->dec_result = DEC_RESULT_NONE;
8769 av1_print(hw, PRINT_FLAG_VDEC_STATUS,
8770 "%s: chunk size 0x%x sum 0x%x\n",
8771 __func__, r,
8772 (debug & PRINT_FLAG_VDEC_STATUS) ?
8773 get_data_check_sum(hw, r) : 0
8774 );
8775
8776 if (debug & PRINT_FLAG_VDEC_DATA)
8777 dump_data(hw, hw->chunk->size);
8778
8779 decode_size = hw->chunk->size +
8780 (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
8781
8782 WRITE_VREG(HEVC_DECODE_SIZE,
8783 READ_VREG(HEVC_DECODE_SIZE) + decode_size);
8784
8785 vdec_enable_input(vdec);
8786
8787 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
8788
8789 start_process_time(hw);
8790
8791 } else {
8792 hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
8793
8794 av1_print(hw, PRINT_FLAG_VDEC_DETAIL,
8795 "amvdec_vh265: Insufficient data\n");
8796
8797 vdec_schedule_work(&hw->work);
8798 }
8799 return;
8800 } else if (hw->dec_result == DEC_RESULT_DONE) {
8801 /* if (!hw->ctx_valid)
8802 hw->ctx_valid = 1; */
8803 hw->result_done_count++;
8804 hw->process_state = PROC_STATE_INIT;
8805
8806 if (hw->mmu_enable)
8807 hw->used_4k_num =
8808 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
8809 av1_print(hw, PRINT_FLAG_VDEC_STATUS,
8810 "%s (===> %d) dec_result %d (%d) %x %x %x shiftbytes 0x%x decbytes 0x%x\n",
8811 __func__,
8812 hw->frame_count,
8813 hw->dec_result,
8814 hw->result_done_count,
8815 READ_VREG(HEVC_STREAM_LEVEL),
8816 READ_VREG(HEVC_STREAM_WR_PTR),
8817 READ_VREG(HEVC_STREAM_RD_PTR),
8818 READ_VREG(HEVC_SHIFT_BYTE_COUNT),
8819 READ_VREG(HEVC_SHIFT_BYTE_COUNT) -
8820 hw->start_shift_bytes
8821 );
8822 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
8823 } else if (hw->dec_result == DEC_RESULT_AGAIN) {
8824 /*
8825 stream base: stream buf empty or timeout
8826 frame base: vdec_prepare_input fail
8827 */
8828 if (!vdec_has_more_input(vdec)) {
8829 hw->dec_result = DEC_RESULT_EOS;
8830 vdec_schedule_work(&hw->work);
8831 return;
8832 }
8833 } else if (hw->dec_result == DEC_RESULT_EOS) {
8834 av1_print(hw, PRINT_FLAG_VDEC_STATUS,
8835 "%s: end of stream\n",
8836 __func__);
8837 hw->eos = 1;
8838 av1_postproc(hw);
8839
8840 if (hw->is_used_v4l)
8841 notify_v4l_eos(hw_to_vdec(hw));
8842
8843 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
8844 } else if (hw->dec_result == DEC_RESULT_FORCE_EXIT) {
8845 av1_print(hw, PRINT_FLAG_VDEC_STATUS,
8846 "%s: force exit\n",
8847 __func__);
8848 if (hw->stat & STAT_VDEC_RUN) {
8849 amhevc_stop();
8850 hw->stat &= ~STAT_VDEC_RUN;
8851 }
8852
8853 if (hw->stat & STAT_ISR_REG) {
8854#ifdef MULTI_INSTANCE_SUPPORT
8855 if (!hw->m_ins_flag)
8856#endif
8857 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0);
8858 vdec_free_irq(VDEC_IRQ_0, (void *)hw);
8859 hw->stat &= ~STAT_ISR_REG;
8860 }
8861 }
8862 if (hw->stat & STAT_VDEC_RUN) {
8863 amhevc_stop();
8864 hw->stat &= ~STAT_VDEC_RUN;
8865 }
8866
8867 if (hw->stat & STAT_TIMER_ARM) {
8868 del_timer_sync(&hw->timer);
8869 hw->stat &= ~STAT_TIMER_ARM;
8870 }
8871 /* mark itself has all HW resource released and input released */
8872 if (vdec->parallel_dec == 1)
8873 vdec_core_finish_run(vdec, CORE_MASK_HEVC);
8874 else
8875 vdec_core_finish_run(hw_to_vdec(hw), CORE_MASK_VDEC_1
8876 | CORE_MASK_HEVC);
8877 trigger_schedule(hw);
8878}
8879
8880static int av1_hw_ctx_restore(struct AV1HW_s *hw)
8881{
8882 vav1_prot_init(hw, HW_MASK_FRONT | HW_MASK_BACK);
8883 return 0;
8884}
8885static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask)
8886{
8887 struct AV1HW_s *hw =
8888 (struct AV1HW_s *)vdec->private;
8889 int tvp = vdec_secure(hw_to_vdec(hw)) ?
8890 CODEC_MM_FLAGS_TVP : 0;
8891 unsigned long ret = 0;
8892
8893 if (!hw->pic_list_init_done2 || hw->eos)
8894 return ret;
8895 if (!hw->first_sc_checked && hw->mmu_enable) {
8896 int size = decoder_mmu_box_sc_check(hw->mmu_box, tvp);
8897 hw->first_sc_checked = 1;
8898 av1_print(hw, 0, "av1 cached=%d need_size=%d speed= %d ms\n",
8899 size, (hw->need_cache_size >> PAGE_SHIFT),
8900 (int)(get_jiffies_64() - hw->sc_start_time) * 1000/HZ);
8901#ifdef AOM_AV1_MMU_DW
8902 /*!!!!!! To do ... */
8903 if (hw->dw_mmu_enable) {
8904
8905 }
8906#endif
8907 }
8908
8909 if (get_free_buf_count(hw) >=
8910 run_ready_min_buf_num) {
8911 if (vdec->parallel_dec == 1)
8912 ret = CORE_MASK_HEVC;
8913 else
8914 ret = CORE_MASK_VDEC_1 | CORE_MASK_HEVC;
8915 }
8916 if (ret)
8917 not_run_ready[hw->index] = 0;
8918 else
8919 not_run_ready[hw->index]++;
8920
8921 /*av1_print(hw,
8922 PRINT_FLAG_VDEC_DETAIL, "%s mask %lx=>%lx\r\n",
8923 __func__, mask, ret);*/
8924 return ret;
8925}
8926
8927static void av1_frame_mode_pts_save(struct AV1HW_s *hw)
8928{
8929 int i;
8930
8931 if (hw->chunk == NULL)
8932 return;
8933 av1_print(hw, AV1_DEBUG_OUT_PTS,
8934 "run front: pts %d, pts64 %lld\n", hw->chunk->pts, hw->chunk->pts64);
8935 for (i = (FRAME_BUFFERS - 1); i > 0; i--) {
8936 hw->frame_mode_pts_save[i] = hw->frame_mode_pts_save[i - 1];
8937 hw->frame_mode_pts64_save[i] = hw->frame_mode_pts64_save[i - 1];
8938 }
8939 hw->frame_mode_pts_save[0] = hw->chunk->pts;
8940 hw->frame_mode_pts64_save[0] = hw->chunk->pts64;
8941}
8942
8943static void run_front(struct vdec_s *vdec)
8944{
8945 struct AV1HW_s *hw =
8946 (struct AV1HW_s *)vdec->private;
8947 int ret, size;
8948
8949 run_count[hw->index]++;
8950 /* hw->chunk = vdec_prepare_input(vdec); */
8951 hevc_reset_core(vdec);
8952
8953 size = vdec_prepare_input(vdec, &hw->chunk);
8954 if (size < 0) {
8955 input_empty[hw->index]++;
8956
8957 hw->dec_result = DEC_RESULT_AGAIN;
8958
8959 av1_print(hw, PRINT_FLAG_VDEC_DETAIL,
8960 "ammvdec_av1: Insufficient data\n");
8961
8962 vdec_schedule_work(&hw->work);
8963 return;
8964 }
8965 input_empty[hw->index] = 0;
8966 hw->dec_result = DEC_RESULT_NONE;
8967 hw->start_shift_bytes = READ_VREG(HEVC_SHIFT_BYTE_COUNT);
8968
8969 av1_frame_mode_pts_save(hw);
8970 if (debug & PRINT_FLAG_VDEC_STATUS) {
8971 /*int ii;*/
8972 av1_print(hw, 0,
8973 "%s (%d): size 0x%x (0x%x 0x%x) sum 0x%x (%x %x %x %x %x) bytes 0x%x\n",
8974 __func__,
8975 hw->frame_count, size,
8976 hw->chunk ? hw->chunk->size : 0,
8977 hw->chunk ? hw->chunk->offset : 0,
8978 hw->chunk ? ((vdec_frame_based(vdec) &&
8979 (debug & PRINT_FLAG_VDEC_STATUS)) ?
8980 get_data_check_sum(hw, size) : 0) : 0,
8981 READ_VREG(HEVC_STREAM_START_ADDR),
8982 READ_VREG(HEVC_STREAM_END_ADDR),
8983 READ_VREG(HEVC_STREAM_LEVEL),
8984 READ_VREG(HEVC_STREAM_WR_PTR),
8985 READ_VREG(HEVC_STREAM_RD_PTR),
8986 hw->start_shift_bytes);
8987#if 0
8988 if (vdec_frame_based(vdec) && hw->chunk) {
8989 u8 *data = NULL;
8990
8991 if (!hw->chunk->block->is_mapped)
8992 data = codec_mm_vmap(hw->chunk->block->start +
8993 hw->chunk->offset, 8);
8994 else
8995 data = ((u8 *)hw->chunk->block->start_virt) +
8996 hw->chunk->offset;
8997
8998 av1_print_cont(hw, 0, "data adr %p:",
8999 data);
9000 for (ii = 0; ii < 8; ii++)
9001 av1_print_cont(hw, 0, "%02x ",
9002 data[ii]);
9003
9004 if (!hw->chunk->block->is_mapped)
9005 codec_mm_unmap_phyaddr(data);
9006 }
9007 av1_print_cont(hw, 0, "\r\n");
9008#endif
9009 }
9010 if (vdec->mc_loaded) {
9011 /*firmware have load before,
9012 and not changes to another.
9013 ignore reload.
9014 */
9015 } else {
9016#ifdef DEBUG_USE_VP9_DEVICE_NAME
9017 ret = amhevc_loadmc_ex(VFORMAT_VP9, NULL, hw->fw->data);
9018#else
9019 ret = amhevc_loadmc_ex(VFORMAT_AV1, NULL, hw->fw->data);
9020#endif
9021 if (ret < 0) {
9022 amhevc_disable();
9023 av1_print(hw, PRINT_FLAG_ERROR,
9024 "AV1: the %s fw loading failed, err: %x\n",
9025 tee_enabled() ? "TEE" : "local", ret);
9026 hw->dec_result = DEC_RESULT_FORCE_EXIT;
9027 vdec_schedule_work(&hw->work);
9028 return;
9029 }
9030 vdec->mc_loaded = 1;
9031#ifdef DEBUG_USE_VP9_DEVICE_NAME
9032 vdec->mc_type = VFORMAT_VP9;
9033#else
9034 vdec->mc_type = VFORMAT_AV1;
9035#endif
9036 }
9037
9038 if (av1_hw_ctx_restore(hw) < 0) {
9039 vdec_schedule_work(&hw->work);
9040 return;
9041 }
9042
9043 vdec_enable_input(vdec);
9044
9045 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
9046
9047 if (vdec_frame_based(vdec)) {
9048 if (debug & PRINT_FLAG_VDEC_DATA)
9049 dump_data(hw, hw->chunk->size);
9050
9051 WRITE_VREG(HEVC_SHIFT_BYTE_COUNT, 0);
9052 size = hw->chunk->size +
9053 (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
9054 }
9055 hw->data_size = size;
9056 WRITE_VREG(HEVC_DECODE_SIZE, size);
9057 WRITE_VREG(HEVC_DECODE_COUNT, hw->result_done_count);
9058 WRITE_VREG(LMEM_DUMP_ADR, (u32)hw->lmem_phy_addr);
9059 if (hw->config_next_ref_info_flag)
9060 config_next_ref_info_hw(hw);
9061 hw->config_next_ref_info_flag = 0;
9062 hw->init_flag = 1;
9063
9064 av1_print(hw, PRINT_FLAG_VDEC_DETAIL,
9065 "%s: start hw (%x %x %x) HEVC_DECODE_SIZE 0x%x\n",
9066 __func__,
9067 READ_VREG(HEVC_DEC_STATUS_REG),
9068 READ_VREG(HEVC_MPC_E),
9069 READ_VREG(HEVC_MPSR),
9070 READ_VREG(HEVC_DECODE_SIZE));
9071
9072 start_process_time(hw);
9073 mod_timer(&hw->timer, jiffies);
9074 hw->stat |= STAT_TIMER_ARM;
9075 hw->stat |= STAT_ISR_REG;
9076 amhevc_start();
9077 hw->stat |= STAT_VDEC_RUN;
9078}
9079
9080static void run(struct vdec_s *vdec, unsigned long mask,
9081 void (*callback)(struct vdec_s *, void *), void *arg)
9082{
9083 struct AV1HW_s *hw =
9084 (struct AV1HW_s *)vdec->private;
9085
9086 av1_print(hw,
9087 PRINT_FLAG_VDEC_DETAIL, "%s mask %lx\r\n",
9088 __func__, mask);
9089
9090 run_count[hw->index]++;
9091 hw->vdec_cb_arg = arg;
9092 hw->vdec_cb = callback;
9093 run_front(vdec);
9094}
9095
9096static void reset(struct vdec_s *vdec)
9097{
9098
9099 struct AV1HW_s *hw =
9100 (struct AV1HW_s *)vdec->private;
9101
9102 av1_print(hw,
9103 PRINT_FLAG_VDEC_DETAIL, "%s\r\n", __func__);
9104
9105}
9106
9107static irqreturn_t av1_irq_cb(struct vdec_s *vdec, int irq)
9108{
9109 struct AV1HW_s *hw =
9110 (struct AV1HW_s *)vdec->private;
9111 return vav1_isr(0, hw);
9112}
9113
9114static irqreturn_t av1_threaded_irq_cb(struct vdec_s *vdec, int irq)
9115{
9116 struct AV1HW_s *hw =
9117 (struct AV1HW_s *)vdec->private;
9118 return vav1_isr_thread_fn(0, hw);
9119}
9120
9121static void av1_dump_state(struct vdec_s *vdec)
9122{
9123 struct AV1HW_s *hw =
9124 (struct AV1HW_s *)vdec->private;
9125 struct AV1_Common_s *const cm = &hw->pbi->common;
9126 int i;
9127 av1_print(hw, 0, "====== %s\n", __func__);
9128
9129 av1_print(hw, 0,
9130 "width/height (%d/%d), used_buf_num %d\n",
9131 cm->width,
9132 cm->height,
9133 hw->used_buf_num
9134 );
9135
9136 av1_print(hw, 0,
9137 "is_framebase(%d), eos %d, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d low_latency %d no_head %d \n",
9138 input_frame_based(vdec),
9139 hw->eos,
9140 hw->dec_result,
9141 decode_frame_count[hw->index],
9142 display_frame_count[hw->index],
9143 run_count[hw->index],
9144 not_run_ready[hw->index],
9145 input_empty[hw->index],
9146 hw->low_latency_flag,
9147 hw->no_head
9148 );
9149
9150 if (vf_get_receiver(vdec->vf_provider_name)) {
9151 enum receviver_start_e state =
9152 vf_notify_receiver(vdec->vf_provider_name,
9153 VFRAME_EVENT_PROVIDER_QUREY_STATE,
9154 NULL);
9155 av1_print(hw, 0,
9156 "\nreceiver(%s) state %d\n",
9157 vdec->vf_provider_name,
9158 state);
9159 }
9160
9161 av1_print(hw, 0,
9162 "%s, newq(%d/%d), dispq(%d/%d), vf prepare/get/put (%d/%d/%d), free_buf_count %d (min %d for run_ready)\n",
9163 __func__,
9164 kfifo_len(&hw->newframe_q),
9165 VF_POOL_SIZE,
9166 kfifo_len(&hw->display_q),
9167 VF_POOL_SIZE,
9168 hw->vf_pre_count,
9169 hw->vf_get_count,
9170 hw->vf_put_count,
9171 get_free_buf_count(hw),
9172 run_ready_min_buf_num
9173 );
9174
9175 dump_pic_list(hw);
9176
9177 for (i = 0; i < MAX_BUF_NUM; i++) {
9178 av1_print(hw, 0,
9179 "mv_Buf(%d) start_adr 0x%x size 0x%x used %d\n",
9180 i,
9181 hw->m_mv_BUF[i].start_adr,
9182 hw->m_mv_BUF[i].size,
9183 hw->m_mv_BUF[i].used_flag);
9184 }
9185
9186 av1_print(hw, 0,
9187 "HEVC_DEC_STATUS_REG=0x%x\n",
9188 READ_VREG(HEVC_DEC_STATUS_REG));
9189 av1_print(hw, 0,
9190 "HEVC_MPC_E=0x%x\n",
9191 READ_VREG(HEVC_MPC_E));
9192 av1_print(hw, 0,
9193 "DECODE_MODE=0x%x\n",
9194 READ_VREG(DECODE_MODE));
9195 av1_print(hw, 0,
9196 "NAL_SEARCH_CTL=0x%x\n",
9197 READ_VREG(NAL_SEARCH_CTL));
9198 av1_print(hw, 0,
9199 "HEVC_PARSER_LCU_START=0x%x\n",
9200 READ_VREG(HEVC_PARSER_LCU_START));
9201 av1_print(hw, 0,
9202 "HEVC_DECODE_SIZE=0x%x\n",
9203 READ_VREG(HEVC_DECODE_SIZE));
9204 av1_print(hw, 0,
9205 "HEVC_SHIFT_BYTE_COUNT=0x%x\n",
9206 READ_VREG(HEVC_SHIFT_BYTE_COUNT));
9207 av1_print(hw, 0,
9208 "HEVC_STREAM_START_ADDR=0x%x\n",
9209 READ_VREG(HEVC_STREAM_START_ADDR));
9210 av1_print(hw, 0,
9211 "HEVC_STREAM_END_ADDR=0x%x\n",
9212 READ_VREG(HEVC_STREAM_END_ADDR));
9213 av1_print(hw, 0,
9214 "HEVC_STREAM_LEVEL=0x%x\n",
9215 READ_VREG(HEVC_STREAM_LEVEL));
9216 av1_print(hw, 0,
9217 "HEVC_STREAM_WR_PTR=0x%x\n",
9218 READ_VREG(HEVC_STREAM_WR_PTR));
9219 av1_print(hw, 0,
9220 "HEVC_STREAM_RD_PTR=0x%x\n",
9221 READ_VREG(HEVC_STREAM_RD_PTR));
9222 av1_print(hw, 0,
9223 "PARSER_VIDEO_RP=0x%x\n",
9224 READ_PARSER_REG(PARSER_VIDEO_RP));
9225 av1_print(hw, 0,
9226 "PARSER_VIDEO_WP=0x%x\n",
9227 READ_PARSER_REG(PARSER_VIDEO_WP));
9228
9229 if (input_frame_based(vdec) &&
9230 (debug & PRINT_FLAG_VDEC_DATA)
9231 ) {
9232 int jj;
9233 if (hw->chunk && hw->chunk->block &&
9234 hw->chunk->size > 0) {
9235 u8 *data = NULL;
9236
9237 if (!hw->chunk->block->is_mapped)
9238 data = codec_mm_vmap(
9239 hw->chunk->block->start +
9240 hw->chunk->offset,
9241 hw->chunk->size);
9242 else
9243 data = ((u8 *)hw->chunk->block->start_virt)
9244 + hw->chunk->offset;
9245 av1_print(hw, 0,
9246 "frame data size 0x%x\n",
9247 hw->chunk->size);
9248 for (jj = 0; jj < hw->chunk->size; jj++) {
9249 if ((jj & 0xf) == 0)
9250 av1_print(hw, 0,
9251 "%06x:", jj);
9252 av1_print_cont(hw, 0,
9253 "%02x ", data[jj]);
9254 if (((jj + 1) & 0xf) == 0)
9255 av1_print_cont(hw, 0,
9256 "\n");
9257 }
9258
9259 if (!hw->chunk->block->is_mapped)
9260 codec_mm_unmap_phyaddr(data);
9261 }
9262 }
9263
9264}
9265
9266static int ammvdec_av1_probe(struct platform_device *pdev)
9267{
9268 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
9269 int ret;
9270 int config_val;
9271 struct vframe_content_light_level_s content_light_level;
9272 struct vframe_master_display_colour_s vf_dp;
9273
9274 struct BUF_s BUF[MAX_BUF_NUM];
9275 struct AV1HW_s *hw = NULL;
9276 pr_debug("%s\n", __func__);
9277
9278 if (pdata == NULL) {
9279 av1_print(hw, 0, "\nammvdec_av1 memory resource undefined.\n");
9280 return -EFAULT;
9281 }
9282 /*hw = (struct AV1HW_s *)devm_kzalloc(&pdev->dev,
9283 sizeof(struct AV1HW_s), GFP_KERNEL);*/
9284 memset(&vf_dp, 0, sizeof(struct vframe_master_display_colour_s));
9285 hw = vmalloc(sizeof(struct AV1HW_s));
9286 if (hw == NULL) {
9287 av1_print(hw, 0, "\nammvdec_av1 device data allocation failed\n");
9288 return -ENOMEM;
9289 }
9290 memset(hw, 0, sizeof(struct AV1HW_s));
9291
9292 if (init_dblk_struc(hw) < 0) {
9293 av1_print(hw, 0, "\nammvdec_av1 device data allocation failed\n");
9294 vfree(hw);
9295 return -ENOMEM;
9296 }
9297
9298 hw->pbi = av1_decoder_create(&hw->av1_buffer_pool); //&aom_decoder;
9299 if (hw->pbi == NULL) {
9300 av1_print(hw, 0, "\nammvdec_av1 device data allocation failed\n");
9301 release_dblk_struct(hw);
9302 vfree(hw);
9303 return -ENOMEM;
9304 }
9305 hw->pbi->private_data = hw;
9306 /* the ctx from v4l2 driver. */
9307 hw->v4l2_ctx = pdata->private;
9308
9309 pdata->private = hw;
9310 pdata->dec_status = vav1_dec_status;
9311 /* pdata->set_trickmode = set_trickmode; */
9312 pdata->run_ready = run_ready;
9313 pdata->run = run;
9314 pdata->reset = reset;
9315 pdata->irq_handler = av1_irq_cb;
9316 pdata->threaded_irq_handler = av1_threaded_irq_cb;
9317 pdata->dump_state = av1_dump_state;
9318
9319 memcpy(&BUF[0], &hw->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
9320 memcpy(&hw->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
9321
9322 hw->index = pdev->id;
9323
9324 if (pdata->use_vfm_path)
9325 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
9326 VFM_DEC_PROVIDER_NAME);
9327#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9328 else if (vdec_dual(pdata)) {
9329 struct AV1HW_s *hevc_pair = NULL;
9330
9331 if (dv_toggle_prov_name) /*debug purpose*/
9332 snprintf(pdata->vf_provider_name,
9333 VDEC_PROVIDER_NAME_SIZE,
9334 (pdata->master) ? VFM_DEC_DVBL_PROVIDER_NAME :
9335 VFM_DEC_DVEL_PROVIDER_NAME);
9336 else
9337 snprintf(pdata->vf_provider_name,
9338 VDEC_PROVIDER_NAME_SIZE,
9339 (pdata->master) ? VFM_DEC_DVEL_PROVIDER_NAME :
9340 VFM_DEC_DVBL_PROVIDER_NAME);
9341 if (pdata->master)
9342 hevc_pair = (struct AV1HW_s *)pdata->master->private;
9343 else if (pdata->slave)
9344 hevc_pair = (struct AV1HW_s *)pdata->slave->private;
9345
9346 if (hevc_pair)
9347 hw->shift_byte_count_lo = hevc_pair->shift_byte_count_lo;
9348 }
9349#endif
9350 else
9351 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
9352 MULTI_INSTANCE_PROVIDER_NAME ".%02x", pdev->id & 0xff);
9353
9354 vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
9355 &vav1_vf_provider, hw);
9356
9357 hw->provider_name = pdata->vf_provider_name;
9358 platform_set_drvdata(pdev, pdata);
9359
9360 hw->platform_dev = pdev;
9361 hw->video_signal_type = 0;
9362 hw->m_ins_flag = 1;
9363
9364 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX)
9365 hw->stat |= AV1_TRIGGER_FRAME_ENABLE;
9366
9367 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
9368 hw->max_pic_w = 8192;
9369 hw->max_pic_h = 4608;
9370 } else {
9371 hw->max_pic_w = 4096;
9372 hw->max_pic_h = 2304;
9373 }
9374#if 1
9375 if ((debug & IGNORE_PARAM_FROM_CONFIG) == 0 &&
9376 pdata->config_len) {
9377#ifdef MULTI_INSTANCE_SUPPORT
9378 int av1_buf_width = 0;
9379 int av1_buf_height = 0;
9380 /*use ptr config for doubel_write_mode, etc*/
9381 av1_print(hw, 0, "pdata->config=%s\n", pdata->config);
9382 if (get_config_int(pdata->config, "av1_double_write_mode",
9383 &config_val) == 0)
9384 hw->double_write_mode = config_val;
9385 else
9386 hw->double_write_mode = double_write_mode;
9387
9388 if (get_config_int(pdata->config, "save_buffer_mode",
9389 &config_val) == 0)
9390 hw->save_buffer_mode = config_val;
9391 else
9392 hw->save_buffer_mode = 0;
9393 if (get_config_int(pdata->config, "av1_buf_width",
9394 &config_val) == 0) {
9395 av1_buf_width = config_val;
9396 }
9397 if (get_config_int(pdata->config, "av1_buf_height",
9398 &config_val) == 0) {
9399 av1_buf_height = config_val;
9400 }
9401
9402 if (get_config_int(pdata->config, "no_head",
9403 &config_val) == 0)
9404 hw->no_head = config_val;
9405 else
9406 hw->no_head = no_head;
9407
9408 /*use ptr config for max_pic_w, etc*/
9409 if (get_config_int(pdata->config, "av1_max_pic_w",
9410 &config_val) == 0) {
9411 hw->max_pic_w = config_val;
9412 }
9413 if (get_config_int(pdata->config, "av1_max_pic_h",
9414 &config_val) == 0) {
9415 hw->max_pic_h = config_val;
9416 }
9417 if ((hw->max_pic_w * hw->max_pic_h)
9418 < (av1_buf_width * av1_buf_height)) {
9419 hw->max_pic_w = av1_buf_width;
9420 hw->max_pic_h = av1_buf_height;
9421 av1_print(hw, 0, "use buf resolution\n");
9422 }
9423#endif
9424 if (get_config_int(pdata->config, "HDRStaticInfo",
9425 &vf_dp.present_flag) == 0
9426 && vf_dp.present_flag == 1) {
9427 get_config_int(pdata->config, "mG.x",
9428 &vf_dp.primaries[0][0]);
9429 get_config_int(pdata->config, "mG.y",
9430 &vf_dp.primaries[0][1]);
9431 get_config_int(pdata->config, "mB.x",
9432 &vf_dp.primaries[1][0]);
9433 get_config_int(pdata->config, "mB.y",
9434 &vf_dp.primaries[1][1]);
9435 get_config_int(pdata->config, "mR.x",
9436 &vf_dp.primaries[2][0]);
9437 get_config_int(pdata->config, "mR.y",
9438 &vf_dp.primaries[2][1]);
9439 get_config_int(pdata->config, "mW.x",
9440 &vf_dp.white_point[0]);
9441 get_config_int(pdata->config, "mW.y",
9442 &vf_dp.white_point[1]);
9443 get_config_int(pdata->config, "mMaxDL",
9444 &vf_dp.luminance[0]);
9445 get_config_int(pdata->config, "mMinDL",
9446 &vf_dp.luminance[1]);
9447 vf_dp.content_light_level.present_flag = 1;
9448 get_config_int(pdata->config, "mMaxCLL",
9449 &content_light_level.max_content);
9450 get_config_int(pdata->config, "mMaxFALL",
9451 &content_light_level.max_pic_average);
9452 vf_dp.content_light_level = content_light_level;
9453 hw->video_signal_type = (1 << 29)
9454 | (5 << 26) /* unspecified */
9455 | (0 << 25) /* limit */
9456 | (1 << 24) /* color available */
9457 | (9 << 16) /* 2020 */
9458 | (16 << 8) /* 2084 */
9459 | (9 << 0); /* 2020 */
9460 }
9461 hw->vf_dp = vf_dp;
9462 } else
9463#endif
9464 {
9465 /*hw->vav1_amstream_dec_info.width = 0;
9466 hw->vav1_amstream_dec_info.height = 0;
9467 hw->vav1_amstream_dec_info.rate = 30;*/
9468 hw->double_write_mode = double_write_mode;
9469 }
9470 if (is_oversize(hw->max_pic_w, hw->max_pic_h)) {
9471 pr_err("over size: %dx%d, probe failed\n",
9472 hw->max_pic_w, hw->max_pic_h);
9473 return -1;
9474 }
9475 hw->mmu_enable = 1;
9476 video_signal_type = hw->video_signal_type;
9477
9478 if (pdata->sys_info) {
9479 hw->vav1_amstream_dec_info = *pdata->sys_info;
9480 if ((unsigned long) hw->vav1_amstream_dec_info.param
9481 & 0x08) {
9482 hw->low_latency_flag = 1;
9483 } else
9484 hw->low_latency_flag = 0;
9485 } else {
9486 hw->vav1_amstream_dec_info.width = 0;
9487 hw->vav1_amstream_dec_info.height = 0;
9488 hw->vav1_amstream_dec_info.rate = 30;
9489 }
9490
9491 hw->is_used_v4l = (((unsigned long)
9492 hw->vav1_amstream_dec_info.param & 0x80) >> 7);
9493 if (hw->is_used_v4l) {
9494 hw->double_write_mode = 0x10;
9495 hw->mmu_enable = 0;
9496 hw->max_pic_w = 1920;
9497 hw->max_pic_h = 1080;
9498 }
9499#ifdef AOM_AV1_MMU_DW
9500 hw->dw_mmu_enable =
9501 get_double_write_mode_init(hw) & 0x20 ? 1 : 0;
9502
9503#endif
9504 av1_print(hw, 0,
9505 "no_head %d low_latency %d\n",
9506 hw->no_head, hw->low_latency_flag);
9507#if 0
9508 hw->buf_start = pdata->mem_start;
9509 hw->buf_size = pdata->mem_end - pdata->mem_start + 1;
9510#else
9511 if (amvdec_av1_mmu_init(hw) < 0) {
9512 pr_err("av1 alloc bmmu box failed!!\n");
9513 /* devm_kfree(&pdev->dev, (void *)hw); */
9514 vfree((void *)hw);
9515 pdata->dec_status = NULL;
9516 return -1;
9517 }
9518
9519 hw->cma_alloc_count = PAGE_ALIGN(work_buf_size) / PAGE_SIZE;
9520 ret = decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, WORK_SPACE_BUF_ID,
9521 hw->cma_alloc_count * PAGE_SIZE, DRIVER_NAME,
9522 &hw->cma_alloc_addr);
9523 if (ret < 0) {
9524 uninit_mmu_buffers(hw);
9525 /* devm_kfree(&pdev->dev, (void *)hw); */
9526 vfree((void *)hw);
9527 pdata->dec_status = NULL;
9528 return ret;
9529 }
9530 hw->buf_start = hw->cma_alloc_addr;
9531 hw->buf_size = work_buf_size;
9532#endif
9533
9534 hw->init_flag = 0;
9535 hw->first_sc_checked = 0;
9536 hw->fatal_error = 0;
9537 hw->show_frame_num = 0;
9538
9539 if (debug) {
9540 av1_print(hw, AOM_DEBUG_HW_MORE, "===AV1 decoder mem resource 0x%lx size 0x%x\n",
9541 hw->buf_start,
9542 hw->buf_size);
9543 }
9544
9545 hw->cma_dev = pdata->cma_dev;
9546 if (vav1_init(pdata) < 0) {
9547 av1_print(hw, 0, "\namvdec_av1 init failed.\n");
9548 av1_local_uninit(hw);
9549 uninit_mmu_buffers(hw);
9550 /* devm_kfree(&pdev->dev, (void *)hw); */
9551 vfree((void *)hw);
9552 pdata->dec_status = NULL;
9553 return -ENODEV;
9554 }
9555 vdec_set_prepare_level(pdata, start_decode_buf_level);
9556 hevc_source_changed(VFORMAT_AV1,
9557 4096, 2048, 60);
9558
9559 if (pdata->parallel_dec == 1)
9560 vdec_core_request(pdata, CORE_MASK_HEVC);
9561 else
9562 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9563 | CORE_MASK_COMBINE);
9564
9565 hw->pic_list_init_done2 = true;
9566 return 0;
9567}
9568
9569static int ammvdec_av1_remove(struct platform_device *pdev)
9570{
9571 struct AV1HW_s *hw = (struct AV1HW_s *)
9572 (((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
9573 struct vdec_s *vdec = hw_to_vdec(hw);
9574 int i;
9575 if (debug)
9576 av1_print(hw, AOM_DEBUG_HW_MORE, "amvdec_av1_remove\n");
9577
9578 vmav1_stop(hw);
9579
9580 if (vdec->parallel_dec == 1)
9581 vdec_core_release(hw_to_vdec(hw), CORE_MASK_HEVC);
9582 else
9583 vdec_core_release(hw_to_vdec(hw), CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
9584
9585 vdec_set_status(hw_to_vdec(hw), VDEC_STATUS_DISCONNECTED);
9586
9587 if (vdec->parallel_dec == 1) {
9588 for (i = 0; i < FRAME_BUFFERS; i++) {
9589 vdec->free_canvas_ex
9590 (hw->pbi->common.buffer_pool->frame_bufs[i].buf.y_canvas_index,
9591 vdec->id);
9592 vdec->free_canvas_ex
9593 (hw->pbi->common.buffer_pool->frame_bufs[i].buf.uv_canvas_index,
9594 vdec->id);
9595 }
9596 }
9597
9598
9599#ifdef DEBUG_PTS
9600 pr_info("pts missed %ld, pts hit %ld, duration %d\n",
9601 hw->pts_missed, hw->pts_hit, hw->frame_dur);
9602#endif
9603 /* devm_kfree(&pdev->dev, (void *)hw); */
9604 vfree(hw->pbi);
9605 release_dblk_struct(hw);
9606 vfree((void *)hw);
9607 return 0;
9608}
9609
9610static struct platform_driver ammvdec_av1_driver = {
9611 .probe = ammvdec_av1_probe,
9612 .remove = ammvdec_av1_remove,
9613 .driver = {
9614 .name = MULTI_DRIVER_NAME,
9615#ifdef CONFIG_PM
9616 .pm = &av1_pm_ops,
9617#endif
9618 }
9619};
9620#endif
9621static struct mconfig av1_configs[] = {
9622 MC_PU32("bit_depth_luma", &bit_depth_luma),
9623 MC_PU32("bit_depth_chroma", &bit_depth_chroma),
9624 MC_PU32("frame_width", &frame_width),
9625 MC_PU32("frame_height", &frame_height),
9626 MC_PU32("debug", &debug),
9627 MC_PU32("radr", &radr),
9628 MC_PU32("rval", &rval),
9629 MC_PU32("pop_shorts", &pop_shorts),
9630 MC_PU32("dbg_cmd", &dbg_cmd),
9631 MC_PU32("dbg_skip_decode_index", &dbg_skip_decode_index),
9632 MC_PU32("endian", &endian),
9633 MC_PU32("step", &step),
9634 MC_PU32("udebug_flag", &udebug_flag),
9635 MC_PU32("decode_pic_begin", &decode_pic_begin),
9636 MC_PU32("slice_parse_begin", &slice_parse_begin),
9637 MC_PU32("i_only_flag", &i_only_flag),
9638 MC_PU32("error_handle_policy", &error_handle_policy),
9639 MC_PU32("buf_alloc_width", &buf_alloc_width),
9640 MC_PU32("buf_alloc_height", &buf_alloc_height),
9641 MC_PU32("buf_alloc_depth", &buf_alloc_depth),
9642 MC_PU32("buf_alloc_size", &buf_alloc_size),
9643 MC_PU32("buffer_mode", &buffer_mode),
9644 MC_PU32("buffer_mode_dbg", &buffer_mode_dbg),
9645 MC_PU32("max_buf_num", &max_buf_num),
9646 MC_PU32("dynamic_buf_num_margin", &dynamic_buf_num_margin),
9647 MC_PU32("mem_map_mode", &mem_map_mode),
9648 MC_PU32("double_write_mode", &double_write_mode),
9649 MC_PU32("enable_mem_saving", &enable_mem_saving),
9650 MC_PU32("force_w_h", &force_w_h),
9651 MC_PU32("force_fps", &force_fps),
9652 MC_PU32("max_decoding_time", &max_decoding_time),
9653 MC_PU32("on_no_keyframe_skiped", &on_no_keyframe_skiped),
9654 MC_PU32("start_decode_buf_level", &start_decode_buf_level),
9655 MC_PU32("decode_timeout_val", &decode_timeout_val),
9656 MC_PU32("av1_max_pic_w", &av1_max_pic_w),
9657 MC_PU32("av1_max_pic_h", &av1_max_pic_h),
9658};
9659static struct mconfig_node av1_node;
9660
9661static int __init amvdec_av1_driver_init_module(void)
9662{
9663
9664 struct BuffInfo_s *p_buf_info;
9665#ifdef BUFMGR_ONLY_OLD_CHIP
9666 debug |= AOM_DEBUG_BUFMGR_ONLY;
9667#endif
9668
9669 if (vdec_is_support_4k()) {
9670 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
9671 p_buf_info = &aom_workbuff_spec[1];
9672 else
9673 p_buf_info = &aom_workbuff_spec[1];
9674 } else
9675 p_buf_info = &aom_workbuff_spec[0];
9676
9677 init_buff_spec(NULL, p_buf_info);
9678 work_buf_size =
9679 (p_buf_info->end_adr - p_buf_info->start_adr
9680 + 0xffff) & (~0xffff);
9681
9682 pr_debug("amvdec_av1 module init\n");
9683
9684 error_handle_policy = 0;
9685
9686#ifdef ERROR_HANDLE_DEBUG
9687 dbg_nal_skip_flag = 0;
9688 dbg_nal_skip_count = 0;
9689#endif
9690 udebug_flag = 0;
9691 decode_pic_begin = 0;
9692 slice_parse_begin = 0;
9693 step = 0;
9694 buf_alloc_size = 0;
9695#ifdef MULTI_INSTANCE_SUPPORT
9696 if (platform_driver_register(&ammvdec_av1_driver))
9697 pr_err("failed to register ammvdec_av1 driver\n");
9698
9699#endif
9700 if (platform_driver_register(&amvdec_av1_driver)) {
9701 pr_err("failed to register amvdec_av1 driver\n");
9702 return -ENODEV;
9703 }
9704
9705 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TM2) {
9706 amvdec_av1_profile.profile =
9707 "4k, 10bit, dwrite, compressed, no_head";
9708 } else {
9709 amvdec_av1_profile.name = "av1_unsupport";
9710 }
9711
9712 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A)
9713 max_buf_num = MAX_BUF_NUM_LESS;
9714
9715 vcodec_profile_register(&amvdec_av1_profile);
9716 amvdec_av1_profile_mult = amvdec_av1_profile;
9717#ifdef DEBUG_USE_VP9_DEVICE_NAME
9718
9719 amvdec_av1_profile_mult.name = "mvp9";
9720 vcodec_profile_register(&amvdec_av1_profile_mult);
9721 INIT_REG_NODE_CONFIGS("media.decoder", &av1_node,
9722 "vp9", av1_configs, CONFIG_FOR_RW);
9723
9724#else
9725 amvdec_av1_profile_mult.name = "mav1";
9726 vcodec_profile_register(&amvdec_av1_profile_mult);
9727 INIT_REG_NODE_CONFIGS("media.decoder", &av1_node,
9728 "av1", av1_configs, CONFIG_FOR_RW);
9729#endif
9730
9731 return 0;
9732}
9733
9734static void __exit amvdec_av1_driver_remove_module(void)
9735{
9736 pr_debug("amvdec_av1 module remove.\n");
9737#ifdef MULTI_INSTANCE_SUPPORT
9738 platform_driver_unregister(&ammvdec_av1_driver);
9739#endif
9740 platform_driver_unregister(&amvdec_av1_driver);
9741}
9742
9743/****************************************/
9744module_param(force_dv_enable, uint, 0664);
9745MODULE_PARM_DESC(force_dv_enable, "\n amvdec_av1 force_dv_enable\n");
9746
9747module_param(bit_depth_luma, uint, 0664);
9748MODULE_PARM_DESC(bit_depth_luma, "\n amvdec_av1 bit_depth_luma\n");
9749
9750module_param(bit_depth_chroma, uint, 0664);
9751MODULE_PARM_DESC(bit_depth_chroma, "\n amvdec_av1 bit_depth_chroma\n");
9752
9753module_param(frame_width, uint, 0664);
9754MODULE_PARM_DESC(frame_width, "\n amvdec_av1 frame_width\n");
9755
9756module_param(frame_height, uint, 0664);
9757MODULE_PARM_DESC(frame_height, "\n amvdec_av1 frame_height\n");
9758
9759module_param(multi_frames_in_one_pack, uint, 0664);
9760MODULE_PARM_DESC(multi_frames_in_one_pack, "\n multi_frames_in_one_pack\n");
9761
9762module_param(debug, uint, 0664);
9763MODULE_PARM_DESC(debug, "\n amvdec_av1 debug\n");
9764
9765module_param(radr, uint, 0664);
9766MODULE_PARM_DESC(radr, "\n radr\n");
9767
9768module_param(rval, uint, 0664);
9769MODULE_PARM_DESC(rval, "\n rval\n");
9770
9771module_param(pop_shorts, uint, 0664);
9772MODULE_PARM_DESC(pop_shorts, "\n rval\n");
9773
9774module_param(dbg_cmd, uint, 0664);
9775MODULE_PARM_DESC(dbg_cmd, "\n dbg_cmd\n");
9776
9777module_param(dbg_skip_decode_index, uint, 0664);
9778MODULE_PARM_DESC(dbg_skip_decode_index, "\n dbg_skip_decode_index\n");
9779
9780module_param(endian, uint, 0664);
9781MODULE_PARM_DESC(endian, "\n rval\n");
9782
9783module_param(step, uint, 0664);
9784MODULE_PARM_DESC(step, "\n amvdec_av1 step\n");
9785
9786module_param(decode_pic_begin, uint, 0664);
9787MODULE_PARM_DESC(decode_pic_begin, "\n amvdec_av1 decode_pic_begin\n");
9788
9789module_param(slice_parse_begin, uint, 0664);
9790MODULE_PARM_DESC(slice_parse_begin, "\n amvdec_av1 slice_parse_begin\n");
9791
9792module_param(i_only_flag, uint, 0664);
9793MODULE_PARM_DESC(i_only_flag, "\n amvdec_av1 i_only_flag\n");
9794
9795module_param(low_latency_flag, uint, 0664);
9796MODULE_PARM_DESC(low_latency_flag, "\n amvdec_av1 low_latency_flag\n");
9797
9798module_param(no_head, uint, 0664);
9799MODULE_PARM_DESC(no_head, "\n amvdec_av1 no_head\n");
9800
9801module_param(error_handle_policy, uint, 0664);
9802MODULE_PARM_DESC(error_handle_policy, "\n amvdec_av1 error_handle_policy\n");
9803
9804module_param(buf_alloc_width, uint, 0664);
9805MODULE_PARM_DESC(buf_alloc_width, "\n buf_alloc_width\n");
9806
9807module_param(buf_alloc_height, uint, 0664);
9808MODULE_PARM_DESC(buf_alloc_height, "\n buf_alloc_height\n");
9809
9810module_param(buf_alloc_depth, uint, 0664);
9811MODULE_PARM_DESC(buf_alloc_depth, "\n buf_alloc_depth\n");
9812
9813module_param(buf_alloc_size, uint, 0664);
9814MODULE_PARM_DESC(buf_alloc_size, "\n buf_alloc_size\n");
9815
9816module_param(buffer_mode, uint, 0664);
9817MODULE_PARM_DESC(buffer_mode, "\n buffer_mode\n");
9818
9819module_param(buffer_mode_dbg, uint, 0664);
9820MODULE_PARM_DESC(buffer_mode_dbg, "\n buffer_mode_dbg\n");
9821/*USE_BUF_BLOCK*/
9822module_param(max_buf_num, uint, 0664);
9823MODULE_PARM_DESC(max_buf_num, "\n max_buf_num\n");
9824
9825module_param(dynamic_buf_num_margin, uint, 0664);
9826MODULE_PARM_DESC(dynamic_buf_num_margin, "\n dynamic_buf_num_margin\n");
9827
9828module_param(mv_buf_margin, uint, 0664);
9829MODULE_PARM_DESC(mv_buf_margin, "\n mv_buf_margin\n");
9830
9831module_param(run_ready_min_buf_num, uint, 0664);
9832MODULE_PARM_DESC(run_ready_min_buf_num, "\n run_ready_min_buf_num\n");
9833
9834/**/
9835
9836module_param(mem_map_mode, uint, 0664);
9837MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n");
9838
9839#ifdef SUPPORT_10BIT
9840module_param(double_write_mode, uint, 0664);
9841MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n");
9842
9843module_param(enable_mem_saving, uint, 0664);
9844MODULE_PARM_DESC(enable_mem_saving, "\n enable_mem_saving\n");
9845
9846module_param(force_w_h, uint, 0664);
9847MODULE_PARM_DESC(force_w_h, "\n force_w_h\n");
9848#endif
9849
9850module_param(force_fps, uint, 0664);
9851MODULE_PARM_DESC(force_fps, "\n force_fps\n");
9852
9853module_param(max_decoding_time, uint, 0664);
9854MODULE_PARM_DESC(max_decoding_time, "\n max_decoding_time\n");
9855
9856module_param(on_no_keyframe_skiped, uint, 0664);
9857MODULE_PARM_DESC(on_no_keyframe_skiped, "\n on_no_keyframe_skiped\n");
9858
9859#ifdef MCRCC_ENABLE
9860module_param(mcrcc_cache_alg_flag, uint, 0664);
9861MODULE_PARM_DESC(mcrcc_cache_alg_flag, "\n mcrcc_cache_alg_flag\n");
9862#endif
9863
9864#ifdef MULTI_INSTANCE_SUPPORT
9865module_param(start_decode_buf_level, int, 0664);
9866MODULE_PARM_DESC(start_decode_buf_level,
9867 "\n av1 start_decode_buf_level\n");
9868
9869module_param(decode_timeout_val, uint, 0664);
9870MODULE_PARM_DESC(decode_timeout_val,
9871 "\n av1 decode_timeout_val\n");
9872
9873module_param(av1_max_pic_w, uint, 0664);
9874MODULE_PARM_DESC(av1_max_pic_w, "\n av1_max_pic_w\n");
9875
9876module_param(av1_max_pic_h, uint, 0664);
9877MODULE_PARM_DESC(av1_max_pic_h, "\n av1_max_pic_h\n");
9878
9879module_param_array(decode_frame_count, uint,
9880 &max_decode_instance_num, 0664);
9881
9882module_param_array(display_frame_count, uint,
9883 &max_decode_instance_num, 0664);
9884
9885module_param_array(max_process_time, uint,
9886 &max_decode_instance_num, 0664);
9887
9888module_param_array(run_count, uint,
9889 &max_decode_instance_num, 0664);
9890
9891module_param_array(input_empty, uint,
9892 &max_decode_instance_num, 0664);
9893
9894module_param_array(not_run_ready, uint,
9895 &max_decode_instance_num, 0664);
9896
9897#ifdef AOM_AV1_MMU_DW
9898module_param_array(dw_mmu_enable, uint,
9899 &max_decode_instance_num, 0664);
9900#endif
9901
9902module_param(prefix_aux_buf_size, uint, 0664);
9903MODULE_PARM_DESC(prefix_aux_buf_size, "\n prefix_aux_buf_size\n");
9904
9905module_param(suffix_aux_buf_size, uint, 0664);
9906MODULE_PARM_DESC(suffix_aux_buf_size, "\n suffix_aux_buf_size\n");
9907
9908#endif
9909
9910#ifdef DUMP_FILMGRAIN
9911module_param(fg_dump_index, uint, 0664);
9912MODULE_PARM_DESC(fg_dump_index, "\n fg_dump_index\n");
9913#endif
9914
9915module_param(get_picture_qos, uint, 0664);
9916MODULE_PARM_DESC(get_picture_qos, "\n amvdec_av1 get_picture_qos\n");
9917
9918module_param(udebug_flag, uint, 0664);
9919MODULE_PARM_DESC(udebug_flag, "\n amvdec_h265 udebug_flag\n");
9920
9921#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9922module_param(dv_toggle_prov_name, uint, 0664);
9923MODULE_PARM_DESC(dv_toggle_prov_name, "\n dv_toggle_prov_name\n");
9924#endif
9925
9926module_param(udebug_pause_pos, uint, 0664);
9927MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n");
9928
9929module_param(udebug_pause_val, uint, 0664);
9930MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n");
9931
9932module_param(udebug_pause_decode_idx, uint, 0664);
9933MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n");
9934
9935module_param(force_pts_unstable, uint, 0664);
9936MODULE_PARM_DESC(force_pts_unstable, "\n force_pts_unstable\n");
9937
9938module_param(without_display_mode, uint, 0664);
9939MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n");
9940
9941module_init(amvdec_av1_driver_init_module);
9942module_exit(amvdec_av1_driver_remove_module);
9943
9944MODULE_DESCRIPTION("AMLOGIC av1 Video Decoder Driver");
9945MODULE_LICENSE("GPL");
9946
9947
generated by cgit at 2024-05-19 18:23:45 (GMT)