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path: root/drivers/frame_provider/decoder/vp9/vvp9.c (plain)
blob: 661ff59299a9bf8f65ae1581dc14b75e27fed6d7
1 /*
2 * drivers/amlogic/amports/vvp9.c
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17#define DEBUG
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/types.h>
21#include <linux/errno.h>
22#include <linux/interrupt.h>
23#include <linux/semaphore.h>
24#include <linux/delay.h>
25#include <linux/timer.h>
26#include <linux/kfifo.h>
27#include <linux/kthread.h>
28#include <linux/spinlock.h>
29#include <linux/platform_device.h>
30#include <linux/amlogic/media/vfm/vframe.h>
31#include <linux/amlogic/media/utils/amstream.h>
32#include <linux/amlogic/media/utils/vformat.h>
33#include <linux/amlogic/media/frame_sync/ptsserv.h>
34#include <linux/amlogic/media/canvas/canvas.h>
35#include <linux/amlogic/media/vfm/vframe_provider.h>
36#include <linux/amlogic/media/vfm/vframe_receiver.h>
37#include <linux/dma-mapping.h>
38#include <linux/dma-contiguous.h>
39#include <linux/slab.h>
40#include <linux/amlogic/tee.h>
41#include "../../../stream_input/amports/amports_priv.h"
42#include <linux/amlogic/media/codec_mm/codec_mm.h>
43#include "../utils/decoder_mmu_box.h"
44#include "../utils/decoder_bmmu_box.h"
45
46#define MEM_NAME "codec_vp9"
47/* #include <mach/am_regs.h> */
48#include <linux/amlogic/media/utils/vdec_reg.h>
49#include "../utils/vdec.h"
50#include "../utils/amvdec.h"
51#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
52#include "../utils/vdec_profile.h"
53#endif
54
55#include <linux/amlogic/media/video_sink/video.h>
56#include <linux/amlogic/media/codec_mm/configs.h>
57#include "../utils/config_parser.h"
58#include "../utils/firmware.h"
59#include "../../../common/chips/decoder_cpu_ver_info.h"
60#include "../utils/vdec_v4l2_buffer_ops.h"
61#include <media/v4l2-mem2mem.h>
62
63#define MIX_STREAM_SUPPORT
64
65#include "vvp9.h"
66
67
68/*#define SUPPORT_FB_DECODING*/
69/*#define FB_DECODING_TEST_SCHEDULE*/
70
71
72#define HW_MASK_FRONT 0x1
73#define HW_MASK_BACK 0x2
74
75#define VP9D_MPP_REFINFO_TBL_ACCCONFIG 0x3442
76#define VP9D_MPP_REFINFO_DATA 0x3443
77#define VP9D_MPP_REF_SCALE_ENBL 0x3441
78#define HEVC_MPRED_CTRL4 0x324c
79#define HEVC_CM_HEADER_START_ADDR 0x3628
80#define HEVC_DBLK_CFGB 0x350b
81#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464
82#define HEVC_SAO_MMU_VH1_ADDR 0x363b
83#define HEVC_SAO_MMU_VH0_ADDR 0x363a
84
85#define HEVC_MV_INFO 0x310d
86#define HEVC_QP_INFO 0x3137
87#define HEVC_SKIP_INFO 0x3136
88
89#define VP9_10B_DEC_IDLE 0
90#define VP9_10B_DEC_FRAME_HEADER 1
91#define VP9_10B_DEC_SLICE_SEGMENT 2
92#define VP9_10B_DECODE_SLICE 5
93#define VP9_10B_DISCARD_NAL 6
94#define VP9_DUMP_LMEM 7
95#define HEVC_DECPIC_DATA_DONE 0xa
96#define HEVC_DECPIC_DATA_ERROR 0xb
97#define HEVC_NAL_DECODE_DONE 0xe
98#define HEVC_DECODE_BUFEMPTY 0x20
99#define HEVC_DECODE_TIMEOUT 0x21
100#define HEVC_SEARCH_BUFEMPTY 0x22
101#define HEVC_DECODE_OVER_SIZE 0x23
102#define HEVC_S2_DECODING_DONE 0x50
103#define VP9_HEAD_PARSER_DONE 0xf0
104#define VP9_HEAD_SEARCH_DONE 0xf1
105#define VP9_EOS 0xf2
106#define HEVC_ACTION_DONE 0xff
107
108#define VF_POOL_SIZE 32
109
110#undef pr_info
111#define pr_info printk
112
113#define DECODE_MODE_SINGLE ((0x80 << 24) | 0)
114#define DECODE_MODE_MULTI_STREAMBASE ((0x80 << 24) | 1)
115#define DECODE_MODE_MULTI_FRAMEBASE ((0x80 << 24) | 2)
116#define DECODE_MODE_SINGLE_LOW_LATENCY ((0x80 << 24) | 3)
117#define DECODE_MODE_MULTI_FRAMEBASE_NOHEAD ((0x80 << 24) | 4)
118
119#define VP9_TRIGGER_FRAME_DONE 0x100
120#define VP9_TRIGGER_FRAME_ENABLE 0x200
121
122#define MV_MEM_UNIT 0x240
123/*---------------------------------------------------
124 * Include "parser_cmd.h"
125 *---------------------------------------------------
126 */
127#define PARSER_CMD_SKIP_CFG_0 0x0000090b
128
129#define PARSER_CMD_SKIP_CFG_1 0x1b14140f
130
131#define PARSER_CMD_SKIP_CFG_2 0x001b1910
132
133#define PARSER_CMD_NUMBER 37
134
135/*#define HEVC_PIC_STRUCT_SUPPORT*/
136/* to remove, fix build error */
137
138/*#define CODEC_MM_FLAGS_FOR_VDECODER 0*/
139
140#define MULTI_INSTANCE_SUPPORT
141#define SUPPORT_10BIT
142/* #define ERROR_HANDLE_DEBUG */
143
144#ifndef STAT_KTHREAD
145#define STAT_KTHREAD 0x40
146#endif
147
148#ifdef MULTI_INSTANCE_SUPPORT
149#define MAX_DECODE_INSTANCE_NUM 9
150#define MULTI_DRIVER_NAME "ammvdec_vp9"
151static unsigned int max_decode_instance_num
152 = MAX_DECODE_INSTANCE_NUM;
153static unsigned int decode_frame_count[MAX_DECODE_INSTANCE_NUM];
154static unsigned int display_frame_count[MAX_DECODE_INSTANCE_NUM];
155static unsigned int max_process_time[MAX_DECODE_INSTANCE_NUM];
156static unsigned int run_count[MAX_DECODE_INSTANCE_NUM];
157static unsigned int input_empty[MAX_DECODE_INSTANCE_NUM];
158static unsigned int not_run_ready[MAX_DECODE_INSTANCE_NUM];
159
160static u32 decode_timeout_val = 200;
161static int start_decode_buf_level = 0x8000;
162static u32 work_buf_size;
163
164static u32 force_pts_unstable;
165
166static u32 mv_buf_margin;
167
168/* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */
169/* double_write_mode:
170 * 0, no double write;
171 * 1, 1:1 ratio;
172 * 2, (1/4):(1/4) ratio;
173 * 3, (1/4):(1/4) ratio, with both compressed frame included
174 * 4, (1/2):(1/2) ratio;
175 * 0x10, double write only
176 * 0x100, if > 1080p,use mode 4,else use mode 1;
177 * 0x200, if > 1080p,use mode 2,else use mode 1;
178 * 0x300, if > 720p, use mode 4, else use mode 1;
179 */
180static u32 double_write_mode;
181
182#define DRIVER_NAME "amvdec_vp9"
183#define MODULE_NAME "amvdec_vp9"
184#define DRIVER_HEADER_NAME "amvdec_vp9_header"
185
186
187#define PUT_INTERVAL (HZ/100)
188#define ERROR_SYSTEM_RESET_COUNT 200
189
190#define PTS_NORMAL 0
191#define PTS_NONE_REF_USE_DURATION 1
192
193#define PTS_MODE_SWITCHING_THRESHOLD 3
194#define PTS_MODE_SWITCHING_RECOVERY_THREASHOLD 3
195
196#define DUR2PTS(x) ((x)*90/96)
197
198struct VP9Decoder_s;
199static int vvp9_vf_states(struct vframe_states *states, void *);
200static struct vframe_s *vvp9_vf_peek(void *);
201static struct vframe_s *vvp9_vf_get(void *);
202static void vvp9_vf_put(struct vframe_s *, void *);
203static int vvp9_event_cb(int type, void *data, void *private_data);
204
205static int vvp9_stop(struct VP9Decoder_s *pbi);
206#ifdef MULTI_INSTANCE_SUPPORT
207static s32 vvp9_init(struct vdec_s *vdec);
208#else
209static s32 vvp9_init(struct VP9Decoder_s *pbi);
210#endif
211static void vvp9_prot_init(struct VP9Decoder_s *pbi, u32 mask);
212static int vvp9_local_init(struct VP9Decoder_s *pbi);
213static void vvp9_put_timer_func(unsigned long arg);
214static void dump_data(struct VP9Decoder_s *pbi, int size);
215static unsigned char get_data_check_sum
216 (struct VP9Decoder_s *pbi, int size);
217static void dump_pic_list(struct VP9Decoder_s *pbi);
218static int vp9_alloc_mmu(
219 struct VP9Decoder_s *pbi,
220 int cur_buf_idx,
221 int pic_width,
222 int pic_height,
223 unsigned short bit_depth,
224 unsigned int *mmu_index_adr);
225
226
227static const char vvp9_dec_id[] = "vvp9-dev";
228
229#define PROVIDER_NAME "decoder.vp9"
230#define MULTI_INSTANCE_PROVIDER_NAME "vdec.vp9"
231
232static const struct vframe_operations_s vvp9_vf_provider = {
233 .peek = vvp9_vf_peek,
234 .get = vvp9_vf_get,
235 .put = vvp9_vf_put,
236 .event_cb = vvp9_event_cb,
237 .vf_states = vvp9_vf_states,
238};
239
240static struct vframe_provider_s vvp9_vf_prov;
241
242static u32 bit_depth_luma;
243static u32 bit_depth_chroma;
244static u32 frame_width;
245static u32 frame_height;
246static u32 video_signal_type;
247
248static u32 on_no_keyframe_skiped;
249
250#define PROB_SIZE (496 * 2 * 4)
251#define PROB_BUF_SIZE (0x5000)
252#define COUNT_BUF_SIZE (0x300 * 4 * 4)
253/*compute_losless_comp_body_size(4096, 2304, 1) = 18874368(0x1200000)*/
254#define MAX_FRAME_4K_NUM 0x1200
255#define MAX_FRAME_8K_NUM 0x4800
256
257#define HEVC_ASSIST_MMU_MAP_ADDR 0x3009
258
259#ifdef SUPPORT_FB_DECODING
260/* register define */
261#define HEVC_ASSIST_HED_FB_W_CTL 0x3006
262#define HEVC_ASSIST_HED_FB_R_CTL 0x3007
263#define HEVC_ASSIST_HED_FB_ADDR 0x3008
264#define HEVC_ASSIST_FB_MMU_MAP_ADDR 0x300a
265#define HEVC_ASSIST_FBD_MMU_MAP_ADDR 0x300b
266
267
268#define MAX_STAGE_PAGE_NUM 0x1200
269#define STAGE_MMU_MAP_SIZE (MAX_STAGE_PAGE_NUM * 4)
270#endif
271static inline int div_r32(int64_t m, int n)
272{
273/*
274 *return (int)(m/n)
275 */
276#ifndef CONFIG_ARM64
277 int64_t qu = 0;
278 qu = div_s64(m, n);
279 return (int)qu;
280#else
281 return (int)(m/n);
282#endif
283}
284
285/*USE_BUF_BLOCK*/
286struct BUF_s {
287 int index;
288 unsigned int alloc_flag;
289 /*buffer */
290 unsigned int cma_page_count;
291 unsigned long alloc_addr;
292 unsigned long start_adr;
293 unsigned int size;
294
295 unsigned int free_start_adr;
296 ulong v4l_ref_buf_addr;
297 ulong header_addr;
298 u32 header_size;
299 u32 luma_size;
300 ulong chroma_addr;
301 u32 chroma_size;
302} /*BUF_t */;
303
304struct MVBUF_s {
305 unsigned long start_adr;
306 unsigned int size;
307 int used_flag;
308} /*MVBUF_t */;
309
310 /* #undef BUFMGR_ONLY to enable hardware configuration */
311
312/*#define TEST_WR_PTR_INC*/
313/*#define WR_PTR_INC_NUM 128*/
314#define WR_PTR_INC_NUM 1
315
316#define SIMULATION
317#define DOS_PROJECT
318#undef MEMORY_MAP_IN_REAL_CHIP
319
320/*#undef DOS_PROJECT*/
321/*#define MEMORY_MAP_IN_REAL_CHIP*/
322
323/*#define BUFFER_MGR_ONLY*/
324/*#define CONFIG_HEVC_CLK_FORCED_ON*/
325/*#define ENABLE_SWAP_TEST*/
326#define MCRCC_ENABLE
327
328#define VP9_LPF_LVL_UPDATE
329/*#define DBG_LF_PRINT*/
330
331#ifdef VP9_10B_NV21
332#else
333#define LOSLESS_COMPRESS_MODE
334#endif
335
336#define DOUBLE_WRITE_YSTART_TEMP 0x02000000
337#define DOUBLE_WRITE_CSTART_TEMP 0x02900000
338
339
340
341typedef unsigned int u32;
342typedef unsigned short u16;
343
344#define VP9_DEBUG_BUFMGR 0x01
345#define VP9_DEBUG_BUFMGR_MORE 0x02
346#define VP9_DEBUG_BUFMGR_DETAIL 0x04
347#define VP9_DEBUG_OUT_PTS 0x10
348#define VP9_DEBUG_SEND_PARAM_WITH_REG 0x100
349#define VP9_DEBUG_MERGE 0x200
350#define VP9_DEBUG_DBG_LF_PRINT 0x400
351#define VP9_DEBUG_REG 0x800
352#define VP9_DEBUG_2_STAGE 0x1000
353#define VP9_DEBUG_2_STAGE_MORE 0x2000
354#define VP9_DEBUG_QOS_INFO 0x4000
355#define VP9_DEBUG_DIS_LOC_ERROR_PROC 0x10000
356#define VP9_DEBUG_DIS_SYS_ERROR_PROC 0x20000
357#define VP9_DEBUG_DUMP_PIC_LIST 0x40000
358#define VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC 0x80000
359#define VP9_DEBUG_NO_TRIGGER_FRAME 0x100000
360#define VP9_DEBUG_LOAD_UCODE_FROM_FILE 0x200000
361#define VP9_DEBUG_FORCE_SEND_AGAIN 0x400000
362#define VP9_DEBUG_DUMP_DATA 0x800000
363#define VP9_DEBUG_CACHE 0x1000000
364#define VP9_DEBUG_CACHE_HIT_RATE 0x2000000
365#define IGNORE_PARAM_FROM_CONFIG 0x8000000
366#ifdef MULTI_INSTANCE_SUPPORT
367#define PRINT_FLAG_ERROR 0x0
368#define PRINT_FLAG_V4L_DETAIL 0x10000000
369#define PRINT_FLAG_VDEC_STATUS 0x20000000
370#define PRINT_FLAG_VDEC_DETAIL 0x40000000
371#define PRINT_FLAG_VDEC_DATA 0x80000000
372#endif
373
374static u32 debug;
375static bool is_reset;
376/*for debug*/
377/*
378 udebug_flag:
379 bit 0, enable ucode print
380 bit 1, enable ucode detail print
381 bit [31:16] not 0, pos to dump lmem
382 bit 2, pop bits to lmem
383 bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
384*/
385static u32 udebug_flag;
386/*
387 when udebug_flag[1:0] is not 0
388 udebug_pause_pos not 0,
389 pause position
390*/
391static u32 udebug_pause_pos;
392/*
393 when udebug_flag[1:0] is not 0
394 and udebug_pause_pos is not 0,
395 pause only when DEBUG_REG2 is equal to this val
396*/
397static u32 udebug_pause_val;
398
399static u32 udebug_pause_decode_idx;
400
401static u32 without_display_mode;
402
403/*
404 *[3:0] 0: default use config from omx.
405 * 1: force enable fence.
406 * 2: disable fence.
407 *[7:4] 0: fence use for driver.
408 * 1: fence fd use for app.
409 */
410static u32 force_config_fence;
411
412#define DEBUG_REG
413#ifdef DEBUG_REG
414void WRITE_VREG_DBG2(unsigned int adr, unsigned int val)
415{
416 if (debug & VP9_DEBUG_REG)
417 pr_info("%s(%x, %x)\n", __func__, adr, val);
418 if (adr != 0)
419 WRITE_VREG(adr, val);
420}
421
422#undef WRITE_VREG
423#define WRITE_VREG WRITE_VREG_DBG2
424#endif
425
426#define FRAME_CNT_WINDOW_SIZE 59
427#define RATE_CORRECTION_THRESHOLD 5
428/**************************************************
429
430VP9 buffer management start
431
432***************************************************/
433
434#define MMU_COMPRESS_HEADER_SIZE 0x48000
435#define MMU_COMPRESS_8K_HEADER_SIZE (0x48000*4)
436#define MAX_SIZE_8K (8192 * 4608)
437#define MAX_SIZE_4K (4096 * 2304)
438#define IS_8K_SIZE(w, h) (((w) * (h)) > MAX_SIZE_4K)
439
440#define INVALID_IDX -1 /* Invalid buffer index.*/
441
442#define RPM_BEGIN 0x200
443#define RPM_END 0x280
444
445union param_u {
446 struct {
447 unsigned short data[RPM_END - RPM_BEGIN];
448 } l;
449 struct {
450 /* from ucode lmem, do not change this struct */
451 unsigned short profile;
452 unsigned short show_existing_frame;
453 unsigned short frame_to_show_idx;
454 unsigned short frame_type; /*1 bit*/
455 unsigned short show_frame; /*1 bit*/
456 unsigned short error_resilient_mode; /*1 bit*/
457 unsigned short intra_only; /*1 bit*/
458 unsigned short display_size_present; /*1 bit*/
459 unsigned short reset_frame_context;
460 unsigned short refresh_frame_flags;
461 unsigned short width;
462 unsigned short height;
463 unsigned short display_width;
464 unsigned short display_height;
465 /*
466 *bit[11:8] - ref_frame_info_0 (ref(3-bits), ref_frame_sign_bias(1-bit))
467 *bit[7:4] - ref_frame_info_1 (ref(3-bits), ref_frame_sign_bias(1-bit))
468 *bit[3:0] - ref_frame_info_2 (ref(3-bits), ref_frame_sign_bias(1-bit))
469 */
470 unsigned short ref_info;
471 /*
472 *bit[2]: same_frame_size0
473 *bit[1]: same_frame_size1
474 *bit[0]: same_frame_size2
475 */
476 unsigned short same_frame_size;
477
478 unsigned short mode_ref_delta_enabled;
479 unsigned short ref_deltas[4];
480 unsigned short mode_deltas[2];
481 unsigned short filter_level;
482 unsigned short sharpness_level;
483 unsigned short bit_depth;
484 unsigned short seg_quant_info[8];
485 unsigned short seg_enabled;
486 unsigned short seg_abs_delta;
487 /* bit 15: feature enabled; bit 8, sign; bit[5:0], data */
488 unsigned short seg_lf_info[8];
489 } p;
490};
491
492
493struct vpx_codec_frame_buffer_s {
494 uint8_t *data; /**< Pointer to the data buffer */
495 size_t size; /**< Size of data in bytes */
496 void *priv; /**< Frame's private data */
497};
498
499enum vpx_color_space_t {
500 VPX_CS_UNKNOWN = 0, /**< Unknown */
501 VPX_CS_BT_601 = 1, /**< BT.601 */
502 VPX_CS_BT_709 = 2, /**< BT.709 */
503 VPX_CS_SMPTE_170 = 3, /**< SMPTE.170 */
504 VPX_CS_SMPTE_240 = 4, /**< SMPTE.240 */
505 VPX_CS_BT_2020 = 5, /**< BT.2020 */
506 VPX_CS_RESERVED = 6, /**< Reserved */
507 VPX_CS_SRGB = 7 /**< sRGB */
508}; /**< alias for enum vpx_color_space */
509
510enum vpx_bit_depth_t {
511 VPX_BITS_8 = 8, /**< 8 bits */
512 VPX_BITS_10 = 10, /**< 10 bits */
513 VPX_BITS_12 = 12, /**< 12 bits */
514};
515
516#define MAX_SLICE_NUM 1024
517struct PIC_BUFFER_CONFIG_s {
518 int index;
519 int BUF_index;
520 int mv_buf_index;
521 int comp_body_size;
522 int buf_size;
523 int vf_ref;
524 int y_canvas_index;
525 int uv_canvas_index;
526#ifdef MULTI_INSTANCE_SUPPORT
527 struct canvas_config_s canvas_config[2];
528#endif
529 int decode_idx;
530 int slice_type;
531 int stream_offset;
532 u32 pts;
533 u64 pts64;
534 u64 timestamp;
535 uint8_t error_mark;
536 /**/
537 int slice_idx;
538 /*buffer*/
539 unsigned long header_adr;
540 unsigned long mpred_mv_wr_start_addr;
541 /*unsigned long mc_y_adr;
542 *unsigned long mc_u_v_adr;
543 */
544 unsigned int dw_y_adr;
545 unsigned int dw_u_v_adr;
546 int mc_canvas_y;
547 int mc_canvas_u_v;
548
549 int lcu_total;
550 /**/
551 int y_width;
552 int y_height;
553 int y_crop_width;
554 int y_crop_height;
555 int y_stride;
556
557 int uv_width;
558 int uv_height;
559 int uv_crop_width;
560 int uv_crop_height;
561 int uv_stride;
562
563 int alpha_width;
564 int alpha_height;
565 int alpha_stride;
566
567 uint8_t *y_buffer;
568 uint8_t *u_buffer;
569 uint8_t *v_buffer;
570 uint8_t *alpha_buffer;
571
572 uint8_t *buffer_alloc;
573 int buffer_alloc_sz;
574 int border;
575 int frame_size;
576 int subsampling_x;
577 int subsampling_y;
578 unsigned int bit_depth;
579 enum vpx_color_space_t color_space;
580
581 int corrupted;
582 int flags;
583 unsigned long cma_alloc_addr;
584
585 int double_write_mode;
586
587 /* picture qos infomation*/
588 int max_qp;
589 int avg_qp;
590 int min_qp;
591 int max_skip;
592 int avg_skip;
593 int min_skip;
594 int max_mv;
595 int min_mv;
596 int avg_mv;
597
598 u32 hw_decode_time;
599 u32 frame_size2; // For frame base mode
600 bool vframe_bound;
601
602 /* vdec sync. */
603 struct fence *fence;
604
605 /* hdr10 plus data */
606 u32 hdr10p_data_size;
607 char *hdr10p_data_buf;
608} PIC_BUFFER_CONFIG;
609
610enum BITSTREAM_PROFILE {
611 PROFILE_0,
612 PROFILE_1,
613 PROFILE_2,
614 PROFILE_3,
615 MAX_PROFILES
616};
617
618enum FRAME_TYPE {
619 KEY_FRAME = 0,
620 INTER_FRAME = 1,
621 FRAME_TYPES,
622};
623
624enum REFERENCE_MODE {
625 SINGLE_REFERENCE = 0,
626 COMPOUND_REFERENCE = 1,
627 REFERENCE_MODE_SELECT = 2,
628 REFERENCE_MODES = 3,
629};
630
631#define NONE -1
632#define INTRA_FRAME 0
633#define LAST_FRAME 1
634#define GOLDEN_FRAME 2
635#define ALTREF_FRAME 3
636#define MAX_REF_FRAMES 4
637
638#define REFS_PER_FRAME 3
639
640#define REF_FRAMES_LOG2 3
641#define REF_FRAMES (1 << REF_FRAMES_LOG2)
642#define REF_FRAMES_4K (6)
643
644/*4 scratch frames for the new frames to support a maximum of 4 cores decoding
645 *in parallel, 3 for scaled references on the encoder.
646 *TODO(hkuang): Add ondemand frame buffers instead of hardcoding the number
647 * // of framebuffers.
648 *TODO(jkoleszar): These 3 extra references could probably come from the
649 *normal reference pool.
650 */
651#define FRAME_BUFFERS (REF_FRAMES + 16)
652#define HEADER_FRAME_BUFFERS (FRAME_BUFFERS)
653#define MAX_BUF_NUM (FRAME_BUFFERS)
654#define MV_BUFFER_NUM FRAME_BUFFERS
655#ifdef SUPPORT_FB_DECODING
656#define STAGE_MAX_BUFFERS 16
657#else
658#define STAGE_MAX_BUFFERS 0
659#endif
660
661#define FRAME_CONTEXTS_LOG2 2
662#define FRAME_CONTEXTS (1 << FRAME_CONTEXTS_LOG2)
663/*buffer + header buffer + workspace*/
664#ifdef MV_USE_FIXED_BUF
665#define MAX_BMMU_BUFFER_NUM (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + 1)
666#define VF_BUFFER_IDX(n) (n)
667#define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n)
668#define WORK_SPACE_BUF_ID (FRAME_BUFFERS + HEADER_FRAME_BUFFERS)
669#else
670#define MAX_BMMU_BUFFER_NUM \
671 (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + MV_BUFFER_NUM + 1)
672#define VF_BUFFER_IDX(n) (n)
673#define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n)
674#define MV_BUFFER_IDX(n) (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + n)
675#define WORK_SPACE_BUF_ID \
676 (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + MV_BUFFER_NUM)
677#endif
678
679struct RefCntBuffer_s {
680 int ref_count;
681 /*MV_REF *mvs;*/
682 int mi_rows;
683 int mi_cols;
684 struct vpx_codec_frame_buffer_s raw_frame_buffer;
685 struct PIC_BUFFER_CONFIG_s buf;
686
687/*The Following variables will only be used in frame parallel decode.
688 *
689 *frame_worker_owner indicates which FrameWorker owns this buffer. NULL means
690 *that no FrameWorker owns, or is decoding, this buffer.
691 *VP9Worker *frame_worker_owner;
692 *
693 *row and col indicate which position frame has been decoded to in real
694 *pixel unit. They are reset to -1 when decoding begins and set to INT_MAX
695 *when the frame is fully decoded.
696 */
697 int row;
698 int col;
699} RefCntBuffer;
700
701struct RefBuffer_s {
702/*TODO(dkovalev): idx is not really required and should be removed, now it
703 *is used in vp9_onyxd_if.c
704 */
705 int idx;
706 struct PIC_BUFFER_CONFIG_s *buf;
707 /*struct scale_factors sf;*/
708} RefBuffer;
709
710struct InternalFrameBuffer_s {
711 uint8_t *data;
712 size_t size;
713 int in_use;
714} InternalFrameBuffer;
715
716struct InternalFrameBufferList_s {
717 int num_internal_frame_buffers;
718 struct InternalFrameBuffer_s *int_fb;
719} InternalFrameBufferList;
720
721struct BufferPool_s {
722/*Protect BufferPool from being accessed by several FrameWorkers at
723 *the same time during frame parallel decode.
724 *TODO(hkuang): Try to use atomic variable instead of locking the whole pool.
725 *
726 *Private data associated with the frame buffer callbacks.
727 *void *cb_priv;
728 *
729 *vpx_get_frame_buffer_cb_fn_t get_fb_cb;
730 *vpx_release_frame_buffer_cb_fn_t release_fb_cb;
731 */
732
733 struct RefCntBuffer_s frame_bufs[FRAME_BUFFERS];
734
735/*Frame buffers allocated internally by the codec.*/
736 struct InternalFrameBufferList_s int_frame_buffers;
737 unsigned long flags;
738 spinlock_t lock;
739
740} BufferPool;
741
742#define lock_buffer_pool(pool, flags) \
743 spin_lock_irqsave(&pool->lock, flags)
744
745#define unlock_buffer_pool(pool, flags) \
746 spin_unlock_irqrestore(&pool->lock, flags)
747
748struct VP9_Common_s {
749 enum vpx_color_space_t color_space;
750 int width;
751 int height;
752 int display_width;
753 int display_height;
754 int last_width;
755 int last_height;
756
757 int subsampling_x;
758 int subsampling_y;
759
760 int use_highbitdepth;/*Marks if we need to use 16bit frame buffers.*/
761
762 struct PIC_BUFFER_CONFIG_s *frame_to_show;
763 struct RefCntBuffer_s *prev_frame;
764
765 /*TODO(hkuang): Combine this with cur_buf in macroblockd.*/
766 struct RefCntBuffer_s *cur_frame;
767
768 int ref_frame_map[REF_FRAMES]; /* maps fb_idx to reference slot */
769
770 /*Prepare ref_frame_map for the next frame.
771 *Only used in frame parallel decode.
772 */
773 int next_ref_frame_map[REF_FRAMES];
774
775 /* TODO(jkoleszar): could expand active_ref_idx to 4,
776 *with 0 as intra, and roll new_fb_idx into it.
777 */
778
779 /*Each frame can reference REFS_PER_FRAME buffers*/
780 struct RefBuffer_s frame_refs[REFS_PER_FRAME];
781
782 int prev_fb_idx;
783 int new_fb_idx;
784 int cur_fb_idx_mmu;
785 /*last frame's frame type for motion search*/
786 enum FRAME_TYPE last_frame_type;
787 enum FRAME_TYPE frame_type;
788
789 int show_frame;
790 int last_show_frame;
791 int show_existing_frame;
792
793 /*Flag signaling that the frame is encoded using only INTRA modes.*/
794 uint8_t intra_only;
795 uint8_t last_intra_only;
796
797 int allow_high_precision_mv;
798
799 /*Flag signaling that the frame context should be reset to default
800 *values. 0 or 1 implies don't reset, 2 reset just the context
801 *specified in the frame header, 3 reset all contexts.
802 */
803 int reset_frame_context;
804
805 /*MBs, mb_rows/cols is in 16-pixel units; mi_rows/cols is in
806 * MODE_INFO (8-pixel) units.
807 */
808 int MBs;
809 int mb_rows, mi_rows;
810 int mb_cols, mi_cols;
811 int mi_stride;
812
813 /*Whether to use previous frame's motion vectors for prediction.*/
814 int use_prev_frame_mvs;
815
816 int refresh_frame_context; /* Two state 0 = NO, 1 = YES */
817
818 int ref_frame_sign_bias[MAX_REF_FRAMES]; /* Two state 0, 1 */
819
820 /*struct loopfilter lf;*/
821 /*struct segmentation seg;*/
822
823 /*TODO(hkuang):Remove this as it is the same as frame_parallel_decode*/
824 /* in pbi.*/
825 int frame_parallel_decode; /* frame-based threading.*/
826
827 /*Context probabilities for reference frame prediction*/
828 /*MV_REFERENCE_FRAME comp_fixed_ref;*/
829 /*MV_REFERENCE_FRAME comp_var_ref[2];*/
830 enum REFERENCE_MODE reference_mode;
831
832 /*FRAME_CONTEXT *fc; */ /* this frame entropy */
833 /*FRAME_CONTEXT *frame_contexts; */ /*FRAME_CONTEXTS*/
834 /*unsigned int frame_context_idx; *//* Context to use/update */
835 /*FRAME_COUNTS counts;*/
836
837 unsigned int current_video_frame;
838 enum BITSTREAM_PROFILE profile;
839
840 enum vpx_bit_depth_t bit_depth;
841
842 int error_resilient_mode;
843 int frame_parallel_decoding_mode;
844
845 int byte_alignment;
846 int skip_loop_filter;
847
848 /*External BufferPool passed from outside.*/
849 struct BufferPool_s *buffer_pool;
850
851 int above_context_alloc_cols;
852
853};
854
855static void set_canvas(struct VP9Decoder_s *pbi,
856 struct PIC_BUFFER_CONFIG_s *pic_config);
857static int prepare_display_buf(struct VP9Decoder_s *pbi,
858 struct PIC_BUFFER_CONFIG_s *pic_config);
859
860static void fill_frame_info(struct VP9Decoder_s *pbi,
861 struct PIC_BUFFER_CONFIG_s *frame,
862 unsigned int framesize,
863 unsigned int pts);
864
865static struct PIC_BUFFER_CONFIG_s *get_frame_new_buffer(struct VP9_Common_s *cm)
866{
867 return &cm->buffer_pool->frame_bufs[cm->new_fb_idx].buf;
868}
869
870static void ref_cnt_fb(struct RefCntBuffer_s *bufs, int *idx, int new_idx)
871{
872 const int ref_index = *idx;
873
874 if (ref_index >= 0 && bufs[ref_index].ref_count > 0) {
875 bufs[ref_index].ref_count--;
876 /*pr_info("[MMU DEBUG 2] dec ref_count[%d] : %d\r\n",
877 * ref_index, bufs[ref_index].ref_count);
878 */
879 }
880
881 *idx = new_idx;
882
883 bufs[new_idx].ref_count++;
884 /*pr_info("[MMU DEBUG 3] inc ref_count[%d] : %d\r\n",
885 * new_idx, bufs[new_idx].ref_count);
886 */
887}
888
889int vp9_release_frame_buffer(struct vpx_codec_frame_buffer_s *fb)
890{
891 struct InternalFrameBuffer_s *const int_fb =
892 (struct InternalFrameBuffer_s *)fb->priv;
893 if (int_fb)
894 int_fb->in_use = 0;
895 return 0;
896}
897
898static int compute_losless_comp_body_size(int width, int height,
899 uint8_t is_bit_depth_10);
900
901static void setup_display_size(struct VP9_Common_s *cm, union param_u *params,
902 int print_header_info)
903{
904 cm->display_width = cm->width;
905 cm->display_height = cm->height;
906 if (params->p.display_size_present) {
907 if (print_header_info)
908 pr_info(" * 1-bit display_size_present read : 1\n");
909 cm->display_width = params->p.display_width;
910 cm->display_height = params->p.display_height;
911 /*vp9_read_frame_size(rb, &cm->display_width,
912 * &cm->display_height);
913 */
914 } else {
915 if (print_header_info)
916 pr_info(" * 1-bit display_size_present read : 0\n");
917 }
918}
919
920
921uint8_t print_header_info = 0;
922
923struct buff_s {
924 u32 buf_start;
925 u32 buf_size;
926 u32 buf_end;
927} buff_t;
928
929struct BuffInfo_s {
930 u32 max_width;
931 u32 max_height;
932 u32 start_adr;
933 u32 end_adr;
934 struct buff_s ipp;
935 struct buff_s sao_abv;
936 struct buff_s sao_vb;
937 struct buff_s short_term_rps;
938 struct buff_s vps;
939 struct buff_s sps;
940 struct buff_s pps;
941 struct buff_s sao_up;
942 struct buff_s swap_buf;
943 struct buff_s swap_buf2;
944 struct buff_s scalelut;
945 struct buff_s dblk_para;
946 struct buff_s dblk_data;
947 struct buff_s seg_map;
948 struct buff_s mmu_vbh;
949 struct buff_s cm_header;
950 struct buff_s mpred_above;
951#ifdef MV_USE_FIXED_BUF
952 struct buff_s mpred_mv;
953#endif
954 struct buff_s rpm;
955 struct buff_s lmem;
956} BuffInfo_t;
957#ifdef MULTI_INSTANCE_SUPPORT
958#define DEC_RESULT_NONE 0
959#define DEC_RESULT_DONE 1
960#define DEC_RESULT_AGAIN 2
961#define DEC_RESULT_CONFIG_PARAM 3
962#define DEC_RESULT_ERROR 4
963#define DEC_INIT_PICLIST 5
964#define DEC_UNINIT_PICLIST 6
965#define DEC_RESULT_GET_DATA 7
966#define DEC_RESULT_GET_DATA_RETRY 8
967#define DEC_RESULT_EOS 9
968#define DEC_RESULT_FORCE_EXIT 10
969#define DEC_RESULT_NEED_MORE_BUFFER 11
970#define DEC_V4L2_CONTINUE_DECODING 18
971
972#define DEC_S1_RESULT_NONE 0
973#define DEC_S1_RESULT_DONE 1
974#define DEC_S1_RESULT_FORCE_EXIT 2
975#define DEC_S1_RESULT_TEST_TRIGGER_DONE 0xf0
976
977#ifdef FB_DECODING_TEST_SCHEDULE
978#define TEST_SET_NONE 0
979#define TEST_SET_PIC_DONE 1
980#define TEST_SET_S2_DONE 2
981#endif
982
983static void vp9_work(struct work_struct *work);
984#endif
985struct loop_filter_info_n;
986struct loopfilter;
987struct segmentation;
988
989#ifdef SUPPORT_FB_DECODING
990static void mpred_process(struct VP9Decoder_s *pbi);
991static void vp9_s1_work(struct work_struct *work);
992
993struct stage_buf_s {
994 int index;
995 unsigned short rpm[RPM_END - RPM_BEGIN];
996};
997
998static unsigned int not_run2_ready[MAX_DECODE_INSTANCE_NUM];
999
1000static unsigned int run2_count[MAX_DECODE_INSTANCE_NUM];
1001
1002#ifdef FB_DECODING_TEST_SCHEDULE
1003u32 stage_buf_num; /* = 16;*/
1004#else
1005u32 stage_buf_num;
1006#endif
1007#endif
1008
1009struct VP9Decoder_s {
1010#ifdef MULTI_INSTANCE_SUPPORT
1011 unsigned char index;
1012
1013 struct device *cma_dev;
1014 struct platform_device *platform_dev;
1015 void (*vdec_cb)(struct vdec_s *, void *);
1016 void *vdec_cb_arg;
1017 struct vframe_chunk_s *chunk;
1018 int dec_result;
1019 struct work_struct work;
1020 struct work_struct recycle_mmu_work;
1021 struct work_struct set_clk_work;
1022 u32 start_shift_bytes;
1023
1024 struct BuffInfo_s work_space_buf_store;
1025 unsigned long buf_start;
1026 u32 buf_size;
1027 u32 cma_alloc_count;
1028 unsigned long cma_alloc_addr;
1029 uint8_t eos;
1030 unsigned long int start_process_time;
1031 unsigned last_lcu_idx;
1032 int decode_timeout_count;
1033 unsigned timeout_num;
1034 int save_buffer_mode;
1035
1036 int double_write_mode;
1037#endif
1038 long used_4k_num;
1039
1040 unsigned char m_ins_flag;
1041 char *provider_name;
1042 union param_u param;
1043 int frame_count;
1044 int pic_count;
1045 u32 stat;
1046 struct timer_list timer;
1047 u32 frame_dur;
1048 u32 frame_ar;
1049 int fatal_error;
1050 uint8_t init_flag;
1051 uint8_t first_sc_checked;
1052 uint8_t process_busy;
1053#define PROC_STATE_INIT 0
1054#define PROC_STATE_DECODESLICE 1
1055#define PROC_STATE_SENDAGAIN 2
1056 uint8_t process_state;
1057 u32 ucode_pause_pos;
1058
1059 int show_frame_num;
1060 struct buff_s mc_buf_spec;
1061 struct dec_sysinfo vvp9_amstream_dec_info;
1062 void *rpm_addr;
1063 void *lmem_addr;
1064 dma_addr_t rpm_phy_addr;
1065 dma_addr_t lmem_phy_addr;
1066 unsigned short *lmem_ptr;
1067 unsigned short *debug_ptr;
1068
1069 void *prob_buffer_addr;
1070 void *count_buffer_addr;
1071 dma_addr_t prob_buffer_phy_addr;
1072 dma_addr_t count_buffer_phy_addr;
1073
1074 void *frame_mmu_map_addr;
1075 dma_addr_t frame_mmu_map_phy_addr;
1076
1077 unsigned int use_cma_flag;
1078
1079 struct BUF_s m_BUF[MAX_BUF_NUM];
1080 struct MVBUF_s m_mv_BUF[MV_BUFFER_NUM];
1081 u32 used_buf_num;
1082 DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
1083 DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
1084 DECLARE_KFIFO(pending_q, struct vframe_s *, VF_POOL_SIZE);
1085 struct vframe_s vfpool[VF_POOL_SIZE];
1086 u32 vf_pre_count;
1087 u32 vf_get_count;
1088 u32 vf_put_count;
1089 int buf_num;
1090 int pic_num;
1091 int lcu_size_log2;
1092 unsigned int losless_comp_body_size;
1093
1094 u32 video_signal_type;
1095
1096 int pts_mode;
1097 int last_lookup_pts;
1098 int last_pts;
1099 u64 last_lookup_pts_us64;
1100 u64 last_pts_us64;
1101 u64 shift_byte_count;
1102
1103 u32 pts_unstable;
1104 u32 frame_cnt_window;
1105 u32 pts1, pts2;
1106 u32 last_duration;
1107 u32 duration_from_pts_done;
1108 bool vp9_first_pts_ready;
1109
1110 u32 shift_byte_count_lo;
1111 u32 shift_byte_count_hi;
1112 int pts_mode_switching_count;
1113 int pts_mode_recovery_count;
1114
1115 bool get_frame_dur;
1116 u32 saved_resolution;
1117
1118 /**/
1119 struct VP9_Common_s common;
1120 struct RefCntBuffer_s *cur_buf;
1121 int refresh_frame_flags;
1122 uint8_t need_resync;
1123 uint8_t hold_ref_buf;
1124 uint8_t ready_for_new_data;
1125 struct BufferPool_s vp9_buffer_pool;
1126
1127 struct BuffInfo_s *work_space_buf;
1128
1129 struct buff_s *mc_buf;
1130
1131 unsigned int frame_width;
1132 unsigned int frame_height;
1133
1134 unsigned short *rpm_ptr;
1135 int init_pic_w;
1136 int init_pic_h;
1137 int lcu_total;
1138 int lcu_size;
1139
1140 int slice_type;
1141
1142 int skip_flag;
1143 int decode_idx;
1144 int slice_idx;
1145 uint8_t has_keyframe;
1146 uint8_t wait_buf;
1147 uint8_t error_flag;
1148
1149 /* bit 0, for decoding; bit 1, for displaying */
1150 uint8_t ignore_bufmgr_error;
1151 int PB_skip_mode;
1152 int PB_skip_count_after_decoding;
1153 /*hw*/
1154
1155 /*lf*/
1156 int default_filt_lvl;
1157 struct loop_filter_info_n *lfi;
1158 struct loopfilter *lf;
1159 struct segmentation *seg_4lf;
1160 /**/
1161 struct vdec_info *gvs;
1162
1163 u32 pre_stream_offset;
1164
1165 unsigned int dec_status;
1166 u32 last_put_idx;
1167 int new_frame_displayed;
1168 void *mmu_box;
1169 void *bmmu_box;
1170 int mmu_enable;
1171 struct vframe_master_display_colour_s vf_dp;
1172 struct firmware_s *fw;
1173 int max_pic_w;
1174 int max_pic_h;
1175#ifdef SUPPORT_FB_DECODING
1176 int dec_s1_result;
1177 int s1_test_cmd;
1178 struct work_struct s1_work;
1179 int used_stage_buf_num;
1180 int s1_pos;
1181 int s2_pos;
1182 void *stage_mmu_map_addr;
1183 dma_addr_t stage_mmu_map_phy_addr;
1184 struct stage_buf_s *s1_buf;
1185 struct stage_buf_s *s2_buf;
1186 struct stage_buf_s *stage_bufs
1187 [STAGE_MAX_BUFFERS];
1188 unsigned char run2_busy;
1189
1190 int s1_mv_buf_index;
1191 int s1_mv_buf_index_pre;
1192 int s1_mv_buf_index_pre_pre;
1193 unsigned long s1_mpred_mv_wr_start_addr;
1194 unsigned long s1_mpred_mv_wr_start_addr_pre;
1195 unsigned short s1_intra_only;
1196 unsigned short s1_frame_type;
1197 unsigned short s1_width;
1198 unsigned short s1_height;
1199 unsigned short s1_last_show_frame;
1200 union param_u s1_param;
1201 u8 back_not_run_ready;
1202#endif
1203 int need_cache_size;
1204 u64 sc_start_time;
1205 bool postproc_done;
1206 int low_latency_flag;
1207 bool no_head;
1208 bool pic_list_init_done;
1209 bool pic_list_init_done2;
1210 bool is_used_v4l;
1211 void *v4l2_ctx;
1212 bool v4l_params_parsed;
1213 int frameinfo_enable;
1214 struct vframe_qos_s vframe_qos;
1215 u32 mem_map_mode;
1216 u32 dynamic_buf_num_margin;
1217 struct vframe_s vframe_dummy;
1218 unsigned int res_ch_flag;
1219 /*struct VP9Decoder_s vp9_decoder;*/
1220 union param_u vp9_param;
1221 int sidebind_type;
1222 int sidebind_channel_id;
1223 bool enable_fence;
1224 int fence_usage;
1225 u32 frame_mode_pts_save[FRAME_BUFFERS];
1226 u64 frame_mode_pts64_save[FRAME_BUFFERS];
1227 int run_ready_min_buf_num;
1228 int one_package_frame_cnt;
1229};
1230
1231static int vp9_print(struct VP9Decoder_s *pbi,
1232 int flag, const char *fmt, ...)
1233{
1234#define HEVC_PRINT_BUF 256
1235 unsigned char buf[HEVC_PRINT_BUF];
1236 int len = 0;
1237
1238 if (pbi == NULL ||
1239 (flag == 0) ||
1240 (debug & flag)) {
1241 va_list args;
1242
1243 va_start(args, fmt);
1244 if (pbi)
1245 len = sprintf(buf, "[%d]", pbi->index);
1246 vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
1247 pr_debug("%s", buf);
1248 va_end(args);
1249 }
1250 return 0;
1251}
1252
1253static int is_oversize(int w, int h)
1254{
1255 int max = (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)?
1256 MAX_SIZE_8K : MAX_SIZE_4K;
1257
1258 if (w <= 0 || h <= 0)
1259 return true;
1260
1261 if (h != 0 && (w > max / h))
1262 return true;
1263
1264 return false;
1265}
1266
1267static int v4l_alloc_and_config_pic(struct VP9Decoder_s *pbi,
1268 struct PIC_BUFFER_CONFIG_s *pic);
1269
1270static void resize_context_buffers(struct VP9Decoder_s *pbi,
1271 struct VP9_Common_s *cm, int width, int height)
1272{
1273 if (cm->width != width || cm->height != height) {
1274 /* to do ..*/
1275 if (pbi != NULL) {
1276 pbi->vp9_first_pts_ready = 0;
1277 pbi->duration_from_pts_done = 0;
1278 }
1279 pr_info("%s (%d,%d)=>(%d,%d)\r\n", __func__, cm->width,
1280 cm->height, width, height);
1281 cm->width = width;
1282 cm->height = height;
1283 }
1284 /*
1285 *if (cm->cur_frame->mvs == NULL ||
1286 * cm->mi_rows > cm->cur_frame->mi_rows ||
1287 * cm->mi_cols > cm->cur_frame->mi_cols) {
1288 * resize_mv_buffer(cm);
1289 *}
1290 */
1291}
1292
1293static int valid_ref_frame_size(int ref_width, int ref_height,
1294 int this_width, int this_height) {
1295 return 2 * this_width >= ref_width &&
1296 2 * this_height >= ref_height &&
1297 this_width <= 16 * ref_width &&
1298 this_height <= 16 * ref_height;
1299}
1300
1301/*
1302 *static int valid_ref_frame_img_fmt(enum vpx_bit_depth_t ref_bit_depth,
1303 * int ref_xss, int ref_yss,
1304 * enum vpx_bit_depth_t this_bit_depth,
1305 * int this_xss, int this_yss) {
1306 * return ref_bit_depth == this_bit_depth && ref_xss == this_xss &&
1307 * ref_yss == this_yss;
1308 *}
1309 */
1310
1311
1312static int setup_frame_size(
1313 struct VP9Decoder_s *pbi,
1314 struct VP9_Common_s *cm, union param_u *params,
1315 unsigned int *mmu_index_adr,
1316 int print_header_info) {
1317 int width, height;
1318 struct BufferPool_s * const pool = cm->buffer_pool;
1319 struct PIC_BUFFER_CONFIG_s *ybf;
1320 int ret = 0;
1321
1322 width = params->p.width;
1323 height = params->p.height;
1324 if (is_oversize(width, height)) {
1325 vp9_print(pbi, 0, "%s, Error: Invalid frame size\n", __func__);
1326 return -1;
1327 }
1328
1329 /*vp9_read_frame_size(rb, &width, &height);*/
1330 if (print_header_info)
1331 pr_info(" * 16-bits w read : %d (width : %d)\n", width, height);
1332 if (print_header_info)
1333 pr_info
1334 (" * 16-bits h read : %d (height : %d)\n", width, height);
1335
1336 WRITE_VREG(HEVC_PARSER_PICTURE_SIZE, (height << 16) | width);
1337#ifdef VP9_10B_HED_FB
1338 WRITE_VREG(HEVC_ASSIST_PIC_SIZE_FB_READ, (height << 16) | width);
1339#endif
1340 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
1341 ret = vp9_alloc_mmu(pbi,
1342 cm->new_fb_idx,
1343 params->p.width,
1344 params->p.height,
1345 params->p.bit_depth,
1346 mmu_index_adr);
1347 if (ret != 0) {
1348 pr_err("can't alloc need mmu1,idx %d ret =%d\n",
1349 cm->new_fb_idx,
1350 ret);
1351 return ret;
1352 }
1353 cm->cur_fb_idx_mmu = cm->new_fb_idx;
1354 }
1355
1356 resize_context_buffers(pbi, cm, width, height);
1357 setup_display_size(cm, params, print_header_info);
1358#if 0
1359 lock_buffer_pool(pool);
1360 if (vp9_realloc_frame_buffer(
1361 get_frame_new_buffer(cm), cm->width, cm->height,
1362 cm->subsampling_x, cm->subsampling_y,
1363#if CONFIG_VP9_HIGHBITDEPTH
1364 cm->use_highbitdepth,
1365#endif
1366 VP9_DEC_BORDER_IN_PIXELS,
1367 cm->byte_alignment,
1368 &pool->frame_bufs[cm->new_fb_idx].raw_frame_buffer,
1369 pool->get_fb_cb, pool->cb_priv)) {
1370 unlock_buffer_pool(pool);
1371 vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR,
1372 "Failed to allocate frame buffer");
1373 }
1374 unlock_buffer_pool(pool);
1375#else
1376 /* porting */
1377 ybf = get_frame_new_buffer(cm);
1378 if (!ybf)
1379 return -1;
1380
1381 ybf->y_crop_width = width;
1382 ybf->y_crop_height = height;
1383 ybf->bit_depth = params->p.bit_depth;
1384#endif
1385 pool->frame_bufs[cm->new_fb_idx].buf.subsampling_x = cm->subsampling_x;
1386 pool->frame_bufs[cm->new_fb_idx].buf.subsampling_y = cm->subsampling_y;
1387 pool->frame_bufs[cm->new_fb_idx].buf.bit_depth =
1388 (unsigned int)cm->bit_depth;
1389 pool->frame_bufs[cm->new_fb_idx].buf.color_space = cm->color_space;
1390 return ret;
1391}
1392
1393static int setup_frame_size_with_refs(
1394 struct VP9Decoder_s *pbi,
1395 struct VP9_Common_s *cm,
1396 union param_u *params,
1397 unsigned int *mmu_index_adr,
1398 int print_header_info) {
1399
1400 int width, height;
1401 int found = 0, i;
1402 int has_valid_ref_frame = 0;
1403 struct PIC_BUFFER_CONFIG_s *ybf;
1404 struct BufferPool_s * const pool = cm->buffer_pool;
1405 int ret = 0;
1406
1407 for (i = 0; i < REFS_PER_FRAME; ++i) {
1408 if ((params->p.same_frame_size >>
1409 (REFS_PER_FRAME - i - 1)) & 0x1) {
1410 struct PIC_BUFFER_CONFIG_s *const buf =
1411 cm->frame_refs[i].buf;
1412 /*if (print_header_info)
1413 * pr_info
1414 * ("1-bit same_frame_size[%d] read : 1\n", i);
1415 */
1416 width = buf->y_crop_width;
1417 height = buf->y_crop_height;
1418 /*if (print_header_info)
1419 * pr_info
1420 * (" - same_frame_size width : %d\n", width);
1421 */
1422 /*if (print_header_info)
1423 * pr_info
1424 * (" - same_frame_size height : %d\n", height);
1425 */
1426 found = 1;
1427 break;
1428 } else {
1429 /*if (print_header_info)
1430 * pr_info
1431 * ("1-bit same_frame_size[%d] read : 0\n", i);
1432 */
1433 }
1434 }
1435
1436 if (!found) {
1437 /*vp9_read_frame_size(rb, &width, &height);*/
1438 width = params->p.width;
1439 height = params->p.height;
1440 /*if (print_header_info)
1441 * pr_info
1442 * (" * 16-bits w read : %d (width : %d)\n",
1443 * width, height);
1444 *if (print_header_info)
1445 * pr_info
1446 * (" * 16-bits h read : %d (height : %d)\n",
1447 * width, height);
1448 */
1449 }
1450
1451 if (is_oversize(width, height)) {
1452 vp9_print(pbi, 0, "%s, Error: Invalid frame size\n", __func__);
1453 return -1;
1454 }
1455
1456 params->p.width = width;
1457 params->p.height = height;
1458
1459 WRITE_VREG(HEVC_PARSER_PICTURE_SIZE, (height << 16) | width);
1460 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
1461 /*if(cm->prev_fb_idx >= 0) release_unused_4k(cm->prev_fb_idx);
1462 *cm->prev_fb_idx = cm->new_fb_idx;
1463 */
1464 /* pr_info
1465 * ("[DEBUG DEBUG]Before alloc_mmu,
1466 * prev_fb_idx : %d, new_fb_idx : %d\r\n",
1467 * cm->prev_fb_idx, cm->new_fb_idx);
1468 */
1469 ret = vp9_alloc_mmu(pbi, cm->new_fb_idx,
1470 params->p.width, params->p.height,
1471 params->p.bit_depth, mmu_index_adr);
1472 if (ret != 0) {
1473 pr_err("can't alloc need mmu,idx %d\r\n",
1474 cm->new_fb_idx);
1475 return ret;
1476 }
1477 cm->cur_fb_idx_mmu = cm->new_fb_idx;
1478 }
1479
1480 /*Check to make sure at least one of frames that this frame references
1481 *has valid dimensions.
1482 */
1483 for (i = 0; i < REFS_PER_FRAME; ++i) {
1484 struct RefBuffer_s * const ref_frame = &cm->frame_refs[i];
1485
1486 has_valid_ref_frame |=
1487 valid_ref_frame_size(ref_frame->buf->y_crop_width,
1488 ref_frame->buf->y_crop_height,
1489 width, height);
1490 }
1491 if (!has_valid_ref_frame) {
1492 pr_err("Error: Referenced frame has invalid size\r\n");
1493 return -1;
1494 }
1495#if 0
1496 for (i = 0; i < REFS_PER_FRAME; ++i) {
1497 struct RefBuffer_s * const ref_frame =
1498 &cm->frame_refs[i];
1499 if (!valid_ref_frame_img_fmt(
1500 ref_frame->buf->bit_depth,
1501 ref_frame->buf->subsampling_x,
1502 ref_frame->buf->subsampling_y,
1503 cm->bit_depth,
1504 cm->subsampling_x,
1505 cm->subsampling_y))
1506 pr_err
1507 ("Referenced frame incompatible color fmt\r\n");
1508 return -1;
1509 }
1510#endif
1511 resize_context_buffers(pbi, cm, width, height);
1512 setup_display_size(cm, params, print_header_info);
1513
1514#if 0
1515 lock_buffer_pool(pool);
1516 if (vp9_realloc_frame_buffer(
1517 get_frame_new_buffer(cm), cm->width, cm->height,
1518 cm->subsampling_x, cm->subsampling_y,
1519#if CONFIG_VP9_HIGHBITDEPTH
1520 cm->use_highbitdepth,
1521#endif
1522 VP9_DEC_BORDER_IN_PIXELS,
1523 cm->byte_alignment,
1524 &pool->frame_bufs[cm->new_fb_idx].raw_frame_buffer,
1525 pool->get_fb_cb,
1526 pool->cb_priv)) {
1527 unlock_buffer_pool(pool);
1528 vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR,
1529 "Failed to allocate frame buffer");
1530 }
1531 unlock_buffer_pool(pool);
1532#else
1533 /* porting */
1534 ybf = get_frame_new_buffer(cm);
1535 if (!ybf)
1536 return -1;
1537
1538 ybf->y_crop_width = width;
1539 ybf->y_crop_height = height;
1540 ybf->bit_depth = params->p.bit_depth;
1541#endif
1542 pool->frame_bufs[cm->new_fb_idx].buf.subsampling_x = cm->subsampling_x;
1543 pool->frame_bufs[cm->new_fb_idx].buf.subsampling_y = cm->subsampling_y;
1544 pool->frame_bufs[cm->new_fb_idx].buf.bit_depth =
1545 (unsigned int)cm->bit_depth;
1546 pool->frame_bufs[cm->new_fb_idx].buf.color_space = cm->color_space;
1547 return ret;
1548}
1549
1550static inline bool close_to(int a, int b, int m)
1551{
1552 return (abs(a - b) < m) ? true : false;
1553}
1554
1555#ifdef MULTI_INSTANCE_SUPPORT
1556static int vp9_print_cont(struct VP9Decoder_s *pbi,
1557 int flag, const char *fmt, ...)
1558{
1559 unsigned char buf[HEVC_PRINT_BUF];
1560 int len = 0;
1561
1562 if (pbi == NULL ||
1563 (flag == 0) ||
1564 (debug & flag)) {
1565 va_list args;
1566
1567 va_start(args, fmt);
1568 vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
1569 pr_debug("%s", buf);
1570 va_end(args);
1571 }
1572 return 0;
1573}
1574
1575static void trigger_schedule(struct VP9Decoder_s *pbi)
1576{
1577 if (pbi->is_used_v4l) {
1578 struct aml_vcodec_ctx *ctx =
1579 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
1580
1581 if (ctx->param_sets_from_ucode &&
1582 !pbi->v4l_params_parsed)
1583 vdec_v4l_write_frame_sync(ctx);
1584 }
1585
1586 if (pbi->vdec_cb)
1587 pbi->vdec_cb(hw_to_vdec(pbi), pbi->vdec_cb_arg);
1588}
1589
1590static void reset_process_time(struct VP9Decoder_s *pbi)
1591{
1592 if (pbi->start_process_time) {
1593 unsigned process_time =
1594 1000 * (jiffies - pbi->start_process_time) / HZ;
1595 pbi->start_process_time = 0;
1596 if (process_time > max_process_time[pbi->index])
1597 max_process_time[pbi->index] = process_time;
1598 }
1599}
1600
1601static void start_process_time(struct VP9Decoder_s *pbi)
1602{
1603 pbi->start_process_time = jiffies;
1604 pbi->decode_timeout_count = 0;
1605 pbi->last_lcu_idx = 0;
1606}
1607
1608static void timeout_process(struct VP9Decoder_s *pbi)
1609{
1610 pbi->timeout_num++;
1611 amhevc_stop();
1612 vp9_print(pbi,
1613 0, "%s decoder timeout\n", __func__);
1614
1615 pbi->dec_result = DEC_RESULT_DONE;
1616 reset_process_time(pbi);
1617 vdec_schedule_work(&pbi->work);
1618}
1619
1620static u32 get_valid_double_write_mode(struct VP9Decoder_s *pbi)
1621{
1622 return ((double_write_mode & 0x80000000) == 0) ?
1623 pbi->double_write_mode :
1624 (double_write_mode & 0x7fffffff);
1625}
1626
1627static int v4l_parser_get_double_write_mode(struct VP9Decoder_s *pbi)
1628{
1629 u32 valid_dw_mode = get_valid_double_write_mode(pbi);
1630 u32 dw;
1631 int w, h;
1632
1633 /* mask for supporting double write value bigger than 0x100 */
1634 if (valid_dw_mode & 0xffffff00) {
1635 w = pbi->frame_width;
1636 h = pbi->frame_height;
1637
1638 dw = 0x1; /*1:1*/
1639 switch (valid_dw_mode) {
1640 case 0x100:
1641 if (w > 1920 && h > 1088)
1642 dw = 0x4; /*1:2*/
1643 break;
1644 case 0x200:
1645 if (w > 1920 && h > 1088)
1646 dw = 0x2; /*1:4*/
1647 break;
1648 case 0x300:
1649 if (w > 1280 && h > 720)
1650 dw = 0x4; /*1:2*/
1651 break;
1652 default:
1653 break;
1654 }
1655 return dw;
1656 }
1657
1658 return valid_dw_mode;
1659}
1660
1661
1662static int get_double_write_mode(struct VP9Decoder_s *pbi)
1663{
1664 u32 valid_dw_mode = get_valid_double_write_mode(pbi);
1665 u32 dw;
1666 int w, h;
1667 struct VP9_Common_s *cm = &pbi->common;
1668 struct PIC_BUFFER_CONFIG_s *cur_pic_config;
1669
1670 /* mask for supporting double write value bigger than 0x100 */
1671 if (valid_dw_mode & 0xffffff00) {
1672 if (!cm->cur_frame)
1673 return 1;/*no valid frame,*/
1674 cur_pic_config = &cm->cur_frame->buf;
1675 w = cur_pic_config->y_crop_width;
1676 h = cur_pic_config->y_crop_height;
1677
1678 dw = 0x1; /*1:1*/
1679 switch (valid_dw_mode) {
1680 case 0x100:
1681 if (w > 1920 && h > 1088)
1682 dw = 0x4; /*1:2*/
1683 break;
1684 case 0x200:
1685 if (w > 1920 && h > 1088)
1686 dw = 0x2; /*1:4*/
1687 break;
1688 case 0x300:
1689 if (w > 1280 && h > 720)
1690 dw = 0x4; /*1:2*/
1691 break;
1692 default:
1693 break;
1694 }
1695 return dw;
1696 }
1697
1698 return valid_dw_mode;
1699}
1700
1701/* for double write buf alloc */
1702static int get_double_write_mode_init(struct VP9Decoder_s *pbi)
1703{
1704 u32 valid_dw_mode = get_valid_double_write_mode(pbi);
1705 u32 dw;
1706 int w = pbi->init_pic_w;
1707 int h = pbi->init_pic_h;
1708
1709 dw = 0x1; /*1:1*/
1710 switch (valid_dw_mode) {
1711 case 0x100:
1712 if (w > 1920 && h > 1088)
1713 dw = 0x4; /*1:2*/
1714 break;
1715 case 0x200:
1716 if (w > 1920 && h > 1088)
1717 dw = 0x2; /*1:4*/
1718 break;
1719 case 0x300:
1720 if (w > 1280 && h > 720)
1721 dw = 0x4; /*1:2*/
1722 break;
1723 default:
1724 dw = valid_dw_mode;
1725 break;
1726 }
1727 return dw;
1728}
1729#endif
1730
1731static int get_double_write_ratio(struct VP9Decoder_s *pbi,
1732 int dw_mode)
1733{
1734 int ratio = 1;
1735 if ((dw_mode == 2) ||
1736 (dw_mode == 3))
1737 ratio = 4;
1738 else if (dw_mode == 4)
1739 ratio = 2;
1740 return ratio;
1741}
1742
1743//#define MAX_4K_NUM 0x1200
1744
1745int vp9_alloc_mmu(
1746 struct VP9Decoder_s *pbi,
1747 int cur_buf_idx,
1748 int pic_width,
1749 int pic_height,
1750 unsigned short bit_depth,
1751 unsigned int *mmu_index_adr)
1752{
1753 int bit_depth_10 = (bit_depth == VPX_BITS_10);
1754 int picture_size;
1755 int cur_mmu_4k_number, max_frame_num;
1756 if (!pbi->mmu_box) {
1757 pr_err("error no mmu box!\n");
1758 return -1;
1759 }
1760 if (get_double_write_mode(pbi) == 0x10)
1761 return 0;
1762 if (bit_depth >= VPX_BITS_12) {
1763 pbi->fatal_error = DECODER_FATAL_ERROR_SIZE_OVERFLOW;
1764 pr_err("fatal_error, un support bit depth 12!\n\n");
1765 return -1;
1766 }
1767 picture_size = compute_losless_comp_body_size(pic_width, pic_height,
1768 bit_depth_10);
1769 cur_mmu_4k_number = ((picture_size + (1 << 12) - 1) >> 12);
1770
1771 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
1772 max_frame_num = MAX_FRAME_8K_NUM;
1773 else
1774 max_frame_num = MAX_FRAME_4K_NUM;
1775
1776 if (cur_mmu_4k_number > max_frame_num) {
1777 pr_err("over max !! cur_mmu_4k_number 0x%x width %d height %d\n",
1778 cur_mmu_4k_number, pic_width, pic_height);
1779 return -1;
1780 }
1781
1782 return decoder_mmu_box_alloc_idx(
1783 pbi->mmu_box,
1784 cur_buf_idx,
1785 cur_mmu_4k_number,
1786 mmu_index_adr);
1787}
1788
1789
1790#ifndef MV_USE_FIXED_BUF
1791static void dealloc_mv_bufs(struct VP9Decoder_s *pbi)
1792{
1793 int i;
1794 for (i = 0; i < MV_BUFFER_NUM; i++) {
1795 if (pbi->m_mv_BUF[i].start_adr) {
1796 if (debug)
1797 pr_info(
1798 "dealloc mv buf(%d) adr %ld size 0x%x used_flag %d\n",
1799 i, pbi->m_mv_BUF[i].start_adr,
1800 pbi->m_mv_BUF[i].size,
1801 pbi->m_mv_BUF[i].used_flag);
1802 decoder_bmmu_box_free_idx(
1803 pbi->bmmu_box,
1804 MV_BUFFER_IDX(i));
1805 pbi->m_mv_BUF[i].start_adr = 0;
1806 pbi->m_mv_BUF[i].size = 0;
1807 pbi->m_mv_BUF[i].used_flag = 0;
1808 }
1809 }
1810}
1811
1812static int alloc_mv_buf(struct VP9Decoder_s *pbi,
1813 int i, int size)
1814{
1815 int ret = 0;
1816
1817 if (pbi->m_mv_BUF[i].start_adr &&
1818 size > pbi->m_mv_BUF[i].size) {
1819 dealloc_mv_bufs(pbi);
1820 } else if (pbi->m_mv_BUF[i].start_adr)
1821 return 0;
1822
1823 if (decoder_bmmu_box_alloc_buf_phy
1824 (pbi->bmmu_box,
1825 MV_BUFFER_IDX(i), size,
1826 DRIVER_NAME,
1827 &pbi->m_mv_BUF[i].start_adr) < 0) {
1828 pbi->m_mv_BUF[i].start_adr = 0;
1829 ret = -1;
1830 } else {
1831 pbi->m_mv_BUF[i].size = size;
1832 pbi->m_mv_BUF[i].used_flag = 0;
1833 ret = 0;
1834 if (debug) {
1835 pr_info(
1836 "MV Buffer %d: start_adr %p size %x\n",
1837 i,
1838 (void *)pbi->m_mv_BUF[i].start_adr,
1839 pbi->m_mv_BUF[i].size);
1840 }
1841 }
1842 return ret;
1843}
1844
1845static int init_mv_buf_list(struct VP9Decoder_s *pbi)
1846{
1847 int i;
1848 int ret = 0;
1849 int count = MV_BUFFER_NUM;
1850 int pic_width = pbi->init_pic_w;
1851 int pic_height = pbi->init_pic_h;
1852 int lcu_size = 64; /*fixed 64*/
1853 int pic_width_64 = (pic_width + 63) & (~0x3f);
1854 int pic_height_32 = (pic_height + 31) & (~0x1f);
1855 int pic_width_lcu = (pic_width_64 % lcu_size) ?
1856 pic_width_64 / lcu_size + 1
1857 : pic_width_64 / lcu_size;
1858 int pic_height_lcu = (pic_height_32 % lcu_size) ?
1859 pic_height_32 / lcu_size + 1
1860 : pic_height_32 / lcu_size;
1861 int lcu_total = pic_width_lcu * pic_height_lcu;
1862 int size = ((lcu_total * MV_MEM_UNIT) + 0xffff) &
1863 (~0xffff);
1864 if (mv_buf_margin > 0)
1865 count = REF_FRAMES + mv_buf_margin;
1866
1867 if (pbi->init_pic_w > 2048 && pbi->init_pic_h > 1088)
1868 count = REF_FRAMES_4K + mv_buf_margin;
1869
1870 if (debug) {
1871 pr_info("%s w:%d, h:%d, count: %d\n",
1872 __func__, pbi->init_pic_w, pbi->init_pic_h, count);
1873 }
1874
1875 for (i = 0;
1876 i < count && i < MV_BUFFER_NUM; i++) {
1877 if (alloc_mv_buf(pbi, i, size) < 0) {
1878 ret = -1;
1879 break;
1880 }
1881 }
1882 return ret;
1883}
1884
1885static int get_mv_buf(struct VP9Decoder_s *pbi,
1886 int *mv_buf_index,
1887 unsigned long *mpred_mv_wr_start_addr)
1888{
1889 int i;
1890 int ret = -1;
1891 for (i = 0; i < MV_BUFFER_NUM; i++) {
1892 if (pbi->m_mv_BUF[i].start_adr &&
1893 pbi->m_mv_BUF[i].used_flag == 0) {
1894 pbi->m_mv_BUF[i].used_flag = 1;
1895 ret = i;
1896 break;
1897 }
1898 }
1899
1900 if (ret >= 0) {
1901 *mv_buf_index = ret;
1902 *mpred_mv_wr_start_addr =
1903 (pbi->m_mv_BUF[ret].start_adr + 0xffff) &
1904 (~0xffff);
1905 if (debug & VP9_DEBUG_BUFMGR_MORE)
1906 pr_info(
1907 "%s => %d (%ld) size 0x%x\n",
1908 __func__, ret,
1909 *mpred_mv_wr_start_addr,
1910 pbi->m_mv_BUF[ret].size);
1911 } else {
1912 pr_info(
1913 "%s: Error, mv buf is not enough\n",
1914 __func__);
1915 }
1916 return ret;
1917}
1918
1919static void put_mv_buf(struct VP9Decoder_s *pbi,
1920 int *mv_buf_index)
1921{
1922 int i = *mv_buf_index;
1923 if (i >= MV_BUFFER_NUM) {
1924 if (debug & VP9_DEBUG_BUFMGR_MORE)
1925 pr_info(
1926 "%s: index %d beyond range\n",
1927 __func__, i);
1928 return;
1929 }
1930 if (debug & VP9_DEBUG_BUFMGR_MORE)
1931 pr_info(
1932 "%s(%d): used_flag(%d)\n",
1933 __func__, i,
1934 pbi->m_mv_BUF[i].used_flag);
1935
1936 *mv_buf_index = -1;
1937 if (pbi->m_mv_BUF[i].start_adr &&
1938 pbi->m_mv_BUF[i].used_flag)
1939 pbi->m_mv_BUF[i].used_flag = 0;
1940}
1941
1942static void put_un_used_mv_bufs(struct VP9Decoder_s *pbi)
1943{
1944 struct VP9_Common_s *const cm = &pbi->common;
1945 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
1946 int i;
1947 for (i = 0; i < pbi->used_buf_num; ++i) {
1948 if ((frame_bufs[i].ref_count == 0) &&
1949 (frame_bufs[i].buf.index != -1) &&
1950 (frame_bufs[i].buf.mv_buf_index >= 0)
1951 )
1952 put_mv_buf(pbi, &frame_bufs[i].buf.mv_buf_index);
1953 }
1954}
1955
1956#ifdef SUPPORT_FB_DECODING
1957static bool mv_buf_available(struct VP9Decoder_s *pbi)
1958{
1959 int i;
1960 bool ret = 0;
1961 for (i = 0; i < MV_BUFFER_NUM; i++) {
1962 if (pbi->m_mv_BUF[i].start_adr &&
1963 pbi->m_mv_BUF[i].used_flag == 0) {
1964 ret = 1;
1965 break;
1966 }
1967 }
1968 return ret;
1969}
1970#endif
1971#endif
1972
1973#ifdef SUPPORT_FB_DECODING
1974static void init_stage_buf(struct VP9Decoder_s *pbi)
1975{
1976 uint i;
1977 for (i = 0; i < STAGE_MAX_BUFFERS
1978 && i < stage_buf_num; i++) {
1979 pbi->stage_bufs[i] =
1980 vmalloc(sizeof(struct stage_buf_s));
1981 if (pbi->stage_bufs[i] == NULL) {
1982 vp9_print(pbi,
1983 0, "%s vmalloc fail\n", __func__);
1984 break;
1985 }
1986 pbi->stage_bufs[i]->index = i;
1987 }
1988 pbi->used_stage_buf_num = i;
1989 pbi->s1_pos = 0;
1990 pbi->s2_pos = 0;
1991 pbi->s1_buf = NULL;
1992 pbi->s2_buf = NULL;
1993 pbi->s1_mv_buf_index = FRAME_BUFFERS;
1994 pbi->s1_mv_buf_index_pre = FRAME_BUFFERS;
1995 pbi->s1_mv_buf_index_pre_pre = FRAME_BUFFERS;
1996
1997 if (pbi->used_stage_buf_num > 0)
1998 vp9_print(pbi,
1999 0, "%s 2 stage decoding buf %d\n",
2000 __func__,
2001 pbi->used_stage_buf_num);
2002}
2003
2004static void uninit_stage_buf(struct VP9Decoder_s *pbi)
2005{
2006 int i;
2007 for (i = 0; i < pbi->used_stage_buf_num; i++) {
2008 if (pbi->stage_bufs[i])
2009 vfree(pbi->stage_bufs[i]);
2010 pbi->stage_bufs[i] = NULL;
2011 }
2012 pbi->used_stage_buf_num = 0;
2013 pbi->s1_pos = 0;
2014 pbi->s2_pos = 0;
2015 pbi->s1_buf = NULL;
2016 pbi->s2_buf = NULL;
2017}
2018
2019static int get_s1_buf(
2020 struct VP9Decoder_s *pbi)
2021{
2022 struct stage_buf_s *buf = NULL;
2023 int ret = -1;
2024 int buf_page_num = MAX_STAGE_PAGE_NUM;
2025 int next_s1_pos = pbi->s1_pos + 1;
2026
2027 if (next_s1_pos >= pbi->used_stage_buf_num)
2028 next_s1_pos = 0;
2029 if (next_s1_pos == pbi->s2_pos) {
2030 pbi->s1_buf = NULL;
2031 return ret;
2032 }
2033
2034 buf = pbi->stage_bufs[pbi->s1_pos];
2035 ret = decoder_mmu_box_alloc_idx(
2036 pbi->mmu_box,
2037 buf->index,
2038 buf_page_num,
2039 pbi->stage_mmu_map_addr);
2040 if (ret < 0) {
2041 vp9_print(pbi, 0,
2042 "%s decoder_mmu_box_alloc fail for index %d (s1_pos %d s2_pos %d)\n",
2043 __func__, buf->index,
2044 pbi->s1_pos, pbi->s2_pos);
2045 buf = NULL;
2046 } else {
2047 vp9_print(pbi, VP9_DEBUG_2_STAGE,
2048 "%s decoder_mmu_box_alloc %d page for index %d (s1_pos %d s2_pos %d)\n",
2049 __func__, buf_page_num, buf->index,
2050 pbi->s1_pos, pbi->s2_pos);
2051 }
2052 pbi->s1_buf = buf;
2053 return ret;
2054}
2055
2056static void inc_s1_pos(struct VP9Decoder_s *pbi)
2057{
2058 struct stage_buf_s *buf =
2059 pbi->stage_bufs[pbi->s1_pos];
2060
2061 int used_page_num =
2062#ifdef FB_DECODING_TEST_SCHEDULE
2063 MAX_STAGE_PAGE_NUM/2;
2064#else
2065 (READ_VREG(HEVC_ASSIST_HED_FB_W_CTL) >> 16);
2066#endif
2067 decoder_mmu_box_free_idx_tail(pbi->mmu_box,
2068 FRAME_BUFFERS + buf->index, used_page_num);
2069
2070 pbi->s1_pos++;
2071 if (pbi->s1_pos >= pbi->used_stage_buf_num)
2072 pbi->s1_pos = 0;
2073
2074 vp9_print(pbi, VP9_DEBUG_2_STAGE,
2075 "%s (used_page_num %d) for index %d (s1_pos %d s2_pos %d)\n",
2076 __func__, used_page_num, buf->index,
2077 pbi->s1_pos, pbi->s2_pos);
2078}
2079
2080#define s2_buf_available(pbi) (pbi->s1_pos != pbi->s2_pos)
2081
2082static int get_s2_buf(
2083 struct VP9Decoder_s *pbi)
2084{
2085 int ret = -1;
2086 struct stage_buf_s *buf = NULL;
2087 if (s2_buf_available(pbi)) {
2088 buf = pbi->stage_bufs[pbi->s2_pos];
2089 vp9_print(pbi, VP9_DEBUG_2_STAGE,
2090 "%s for index %d (s1_pos %d s2_pos %d)\n",
2091 __func__, buf->index,
2092 pbi->s1_pos, pbi->s2_pos);
2093 pbi->s2_buf = buf;
2094 ret = 0;
2095 }
2096 return ret;
2097}
2098
2099static void inc_s2_pos(struct VP9Decoder_s *pbi)
2100{
2101 struct stage_buf_s *buf =
2102 pbi->stage_bufs[pbi->s2_pos];
2103 decoder_mmu_box_free_idx(pbi->mmu_box,
2104 FRAME_BUFFERS + buf->index);
2105 pbi->s2_pos++;
2106 if (pbi->s2_pos >= pbi->used_stage_buf_num)
2107 pbi->s2_pos = 0;
2108 vp9_print(pbi, VP9_DEBUG_2_STAGE,
2109 "%s for index %d (s1_pos %d s2_pos %d)\n",
2110 __func__, buf->index,
2111 pbi->s1_pos, pbi->s2_pos);
2112}
2113
2114static int get_free_stage_buf_num(struct VP9Decoder_s *pbi)
2115{
2116 int num;
2117 if (pbi->s1_pos >= pbi->s2_pos)
2118 num = pbi->used_stage_buf_num -
2119 (pbi->s1_pos - pbi->s2_pos) - 1;
2120 else
2121 num = (pbi->s2_pos - pbi->s1_pos) - 1;
2122 return num;
2123}
2124
2125#ifndef FB_DECODING_TEST_SCHEDULE
2126static DEFINE_SPINLOCK(fb_core_spin_lock);
2127
2128static u8 is_s2_decoding_finished(struct VP9Decoder_s *pbi)
2129{
2130 /* to do: VLSI review
2131 completion of last LCU decoding in BACK
2132 */
2133 return 1;
2134}
2135
2136static void start_s1_decoding(struct VP9Decoder_s *pbi)
2137{
2138 /* to do: VLSI review
2139 after parser, how to start LCU decoding in BACK
2140 */
2141}
2142
2143static void fb_reset_core(struct vdec_s *vdec, u32 mask)
2144{
2145 /* to do: VLSI review
2146 1. how to disconnect DMC for FRONT and BACK
2147 2. reset bit 13, 24, FRONT or BACK ??
2148 */
2149
2150 unsigned long flags;
2151 u32 reset_bits = 0;
2152 if (mask & HW_MASK_FRONT)
2153 WRITE_VREG(HEVC_STREAM_CONTROL, 0);
2154 spin_lock_irqsave(&fb_core_spin_lock, flags);
2155 codec_dmcbus_write(DMC_REQ_CTRL,
2156 codec_dmcbus_read(DMC_REQ_CTRL) & (~(1 << 4)));
2157 spin_unlock_irqrestore(&fb_core_spin_lock, flags);
2158
2159 while (!(codec_dmcbus_read(DMC_CHAN_STS)
2160 & (1 << 4)))
2161 ;
2162
2163 if ((mask & HW_MASK_FRONT) &&
2164 input_frame_based(vdec))
2165 WRITE_VREG(HEVC_STREAM_CONTROL, 0);
2166
2167 /*
2168 * 2: assist
2169 * 3: parser
2170 * 4: parser_state
2171 * 8: dblk
2172 * 11:mcpu
2173 * 12:ccpu
2174 * 13:ddr
2175 * 14:iqit
2176 * 15:ipp
2177 * 17:qdct
2178 * 18:mpred
2179 * 19:sao
2180 * 24:hevc_afifo
2181 */
2182 if (mask & HW_MASK_FRONT) {
2183 reset_bits =
2184 (1<<3)|(1<<4)|(1<<11)|
2185 (1<<12)|(1<<18);
2186 }
2187 if (mask & HW_MASK_BACK) {
2188 reset_bits =
2189 (1<<8)|(1<<13)|(1<<14)|(1<<15)|
2190 (1<<17)|(1<<19)|(1<<24);
2191 }
2192 WRITE_VREG(DOS_SW_RESET3, reset_bits);
2193#if 0
2194 (1<<3)|(1<<4)|(1<<8)|(1<<11)|
2195 (1<<12)|(1<<13)|(1<<14)|(1<<15)|
2196 (1<<17)|(1<<18)|(1<<19)|(1<<24);
2197#endif
2198 WRITE_VREG(DOS_SW_RESET3, 0);
2199
2200
2201 spin_lock_irqsave(&fb_core_spin_lock, flags);
2202 codec_dmcbus_write(DMC_REQ_CTRL,
2203 codec_dmcbus_read(DMC_REQ_CTRL) | (1 << 4));
2204 spin_unlock_irqrestore(&fb_core_spin_lock, flags);
2205
2206}
2207#endif
2208
2209#endif
2210
2211static void init_pic_list_hw(struct VP9Decoder_s *pbi);
2212
2213static int get_free_fb(struct VP9Decoder_s *pbi)
2214{
2215 struct VP9_Common_s *const cm = &pbi->common;
2216 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
2217 int i;
2218 unsigned long flags;
2219
2220 lock_buffer_pool(cm->buffer_pool, flags);
2221 if (debug & VP9_DEBUG_BUFMGR_MORE) {
2222 for (i = 0; i < pbi->used_buf_num; ++i) {
2223 pr_info("%s:%d, ref_count %d vf_ref %d index %d\r\n",
2224 __func__, i, frame_bufs[i].ref_count,
2225 frame_bufs[i].buf.vf_ref,
2226 frame_bufs[i].buf.index);
2227 }
2228 }
2229 for (i = 0; i < pbi->used_buf_num; ++i) {
2230 if ((frame_bufs[i].ref_count == 0) &&
2231 (frame_bufs[i].buf.vf_ref == 0) &&
2232 (frame_bufs[i].buf.index != -1)
2233 )
2234 break;
2235 }
2236 if (i != pbi->used_buf_num) {
2237 frame_bufs[i].ref_count = 1;
2238 /*pr_info("[MMU DEBUG 1] set ref_count[%d] : %d\r\n",
2239 i, frame_bufs[i].ref_count);*/
2240 } else {
2241 /* Reset i to be INVALID_IDX to indicate
2242 no free buffer found*/
2243 i = INVALID_IDX;
2244 }
2245
2246 unlock_buffer_pool(cm->buffer_pool, flags);
2247 return i;
2248}
2249
2250static int v4l_get_free_fb(struct VP9Decoder_s *pbi)
2251{
2252 struct VP9_Common_s *const cm = &pbi->common;
2253 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
2254 struct aml_vcodec_ctx * v4l = pbi->v4l2_ctx;
2255 struct v4l_buff_pool *pool = &v4l->cap_pool;
2256 struct PIC_BUFFER_CONFIG_s *pic = NULL;
2257 int i, idx = INVALID_IDX;
2258 ulong flags;
2259
2260 lock_buffer_pool(cm->buffer_pool, flags);
2261
2262 for (i = 0; i < pool->in; ++i) {
2263 u32 state = (pool->seq[i] >> 16);
2264 u32 index = (pool->seq[i] & 0xffff);
2265
2266 switch (state) {
2267 case V4L_CAP_BUFF_IN_DEC:
2268 pic = &frame_bufs[i].buf;
2269 if ((frame_bufs[i].ref_count == 0) &&
2270 (pic->vf_ref == 0) &&
2271 (pic->index != -1) &&
2272 pic->cma_alloc_addr) {
2273 idx = i;
2274 }
2275 break;
2276 case V4L_CAP_BUFF_IN_M2M:
2277 pic = &frame_bufs[index].buf;
2278 pic->y_crop_width = pbi->frame_width;
2279 pic->y_crop_height = pbi->frame_height;
2280 if (!v4l_alloc_and_config_pic(pbi, pic)) {
2281 set_canvas(pbi, pic);
2282 init_pic_list_hw(pbi);
2283 idx = index;
2284 }
2285 break;
2286 default:
2287 pr_err("v4l buffer state err %d.\n", state);
2288 break;
2289 }
2290
2291 if (idx != INVALID_IDX) {
2292 frame_bufs[idx].ref_count = 1;
2293 break;
2294 }
2295 }
2296
2297 unlock_buffer_pool(cm->buffer_pool, flags);
2298
2299 return idx;
2300}
2301
2302static int get_free_buf_count(struct VP9Decoder_s *pbi)
2303{
2304 struct VP9_Common_s *const cm = &pbi->common;
2305 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
2306 int i;
2307 int free_buf_count = 0;
2308 for (i = 0; i < pbi->used_buf_num; ++i)
2309 if ((frame_bufs[i].ref_count == 0) &&
2310 (frame_bufs[i].buf.vf_ref == 0) &&
2311 (frame_bufs[i].buf.index != -1)
2312 )
2313 free_buf_count++;
2314 return free_buf_count;
2315}
2316
2317static void decrease_ref_count(int idx, struct RefCntBuffer_s *const frame_bufs,
2318 struct BufferPool_s *const pool)
2319{
2320 if (idx >= 0) {
2321 --frame_bufs[idx].ref_count;
2322 /*pr_info("[MMU DEBUG 7] dec ref_count[%d] : %d\r\n", idx,
2323 * frame_bufs[idx].ref_count);
2324 */
2325 /*A worker may only get a free framebuffer index when
2326 *calling get_free_fb. But the private buffer is not set up
2327 *until finish decoding header. So any error happens during
2328 *decoding header, the frame_bufs will not have valid priv
2329 *buffer.
2330 */
2331
2332 if (frame_bufs[idx].ref_count == 0 &&
2333 frame_bufs[idx].raw_frame_buffer.priv)
2334 vp9_release_frame_buffer
2335 (&frame_bufs[idx].raw_frame_buffer);
2336 }
2337}
2338
2339static void generate_next_ref_frames(struct VP9Decoder_s *pbi)
2340{
2341 struct VP9_Common_s *const cm = &pbi->common;
2342 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
2343 struct BufferPool_s *const pool = cm->buffer_pool;
2344 int mask, ref_index = 0;
2345 unsigned long flags;
2346
2347 /* Generate next_ref_frame_map.*/
2348 lock_buffer_pool(pool, flags);
2349 for (mask = pbi->refresh_frame_flags; mask; mask >>= 1) {
2350 if (mask & 1) {
2351 cm->next_ref_frame_map[ref_index] = cm->new_fb_idx;
2352 ++frame_bufs[cm->new_fb_idx].ref_count;
2353 /*pr_info("[MMU DEBUG 4] inc ref_count[%d] : %d\r\n",
2354 *cm->new_fb_idx, frame_bufs[cm->new_fb_idx].ref_count);
2355 */
2356 } else
2357 cm->next_ref_frame_map[ref_index] =
2358 cm->ref_frame_map[ref_index];
2359 /* Current thread holds the reference frame.*/
2360 if (cm->ref_frame_map[ref_index] >= 0) {
2361 ++frame_bufs[cm->ref_frame_map[ref_index]].ref_count;
2362 /*pr_info
2363 *("[MMU DEBUG 5] inc ref_count[%d] : %d\r\n",
2364 *cm->ref_frame_map[ref_index],
2365 *frame_bufs[cm->ref_frame_map[ref_index]].ref_count);
2366 */
2367 }
2368 ++ref_index;
2369 }
2370
2371 for (; ref_index < REF_FRAMES; ++ref_index) {
2372 cm->next_ref_frame_map[ref_index] =
2373 cm->ref_frame_map[ref_index];
2374 /* Current thread holds the reference frame.*/
2375 if (cm->ref_frame_map[ref_index] >= 0) {
2376 ++frame_bufs[cm->ref_frame_map[ref_index]].ref_count;
2377 /*pr_info("[MMU DEBUG 6] inc ref_count[%d] : %d\r\n",
2378 *cm->ref_frame_map[ref_index],
2379 *frame_bufs[cm->ref_frame_map[ref_index]].ref_count);
2380 */
2381 }
2382 }
2383 unlock_buffer_pool(pool, flags);
2384 return;
2385}
2386
2387static void refresh_ref_frames(struct VP9Decoder_s *pbi)
2388
2389{
2390 struct VP9_Common_s *const cm = &pbi->common;
2391 struct BufferPool_s *pool = cm->buffer_pool;
2392 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
2393 int mask, ref_index = 0;
2394 unsigned long flags;
2395
2396 lock_buffer_pool(pool, flags);
2397 for (mask = pbi->refresh_frame_flags; mask; mask >>= 1) {
2398 const int old_idx = cm->ref_frame_map[ref_index];
2399 /*Current thread releases the holding of reference frame.*/
2400 decrease_ref_count(old_idx, frame_bufs, pool);
2401
2402 /*Release the reference frame in reference map.*/
2403 if ((mask & 1) && old_idx >= 0)
2404 decrease_ref_count(old_idx, frame_bufs, pool);
2405 cm->ref_frame_map[ref_index] =
2406 cm->next_ref_frame_map[ref_index];
2407 ++ref_index;
2408 }
2409
2410 /*Current thread releases the holding of reference frame.*/
2411 for (; ref_index < REF_FRAMES && !cm->show_existing_frame;
2412 ++ref_index) {
2413 const int old_idx = cm->ref_frame_map[ref_index];
2414
2415 decrease_ref_count(old_idx, frame_bufs, pool);
2416 cm->ref_frame_map[ref_index] =
2417 cm->next_ref_frame_map[ref_index];
2418 }
2419 unlock_buffer_pool(pool, flags);
2420 return;
2421}
2422
2423int vp9_bufmgr_process(struct VP9Decoder_s *pbi, union param_u *params)
2424{
2425 struct VP9_Common_s *const cm = &pbi->common;
2426 struct BufferPool_s *pool = cm->buffer_pool;
2427 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
2428 struct PIC_BUFFER_CONFIG_s *pic = NULL;
2429 int i;
2430 int ret;
2431
2432 pbi->ready_for_new_data = 0;
2433
2434 if (pbi->has_keyframe == 0 &&
2435 params->p.frame_type != KEY_FRAME){
2436 on_no_keyframe_skiped++;
2437 return -2;
2438 }
2439 pbi->has_keyframe = 1;
2440 on_no_keyframe_skiped = 0;
2441#if 0
2442 if (pbi->mmu_enable) {
2443 if (!pbi->m_ins_flag)
2444 pbi->used_4k_num = (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
2445 if (cm->prev_fb_idx >= 0) {
2446 decoder_mmu_box_free_idx_tail(pbi->mmu_box,
2447 cm->prev_fb_idx, pbi->used_4k_num);
2448 }
2449 }
2450#endif
2451 if (cm->new_fb_idx >= 0
2452 && frame_bufs[cm->new_fb_idx].ref_count == 0){
2453 vp9_release_frame_buffer
2454 (&frame_bufs[cm->new_fb_idx].raw_frame_buffer);
2455 }
2456 /*pr_info("Before get_free_fb, prev_fb_idx : %d, new_fb_idx : %d\r\n",
2457 cm->prev_fb_idx, cm->new_fb_idx);*/
2458#ifndef MV_USE_FIXED_BUF
2459 put_un_used_mv_bufs(pbi);
2460 if (debug & VP9_DEBUG_BUFMGR_DETAIL)
2461 dump_pic_list(pbi);
2462#endif
2463 cm->new_fb_idx = pbi->is_used_v4l ?
2464 v4l_get_free_fb(pbi) :
2465 get_free_fb(pbi);
2466 if (cm->new_fb_idx == INVALID_IDX) {
2467 pr_info("get_free_fb error\r\n");
2468 return -1;
2469 }
2470
2471#ifndef MV_USE_FIXED_BUF
2472#ifdef SUPPORT_FB_DECODING
2473 if (pbi->used_stage_buf_num == 0) {
2474#endif
2475 if (get_mv_buf(pbi,
2476 &pool->frame_bufs[cm->new_fb_idx].
2477 buf.mv_buf_index,
2478 &pool->frame_bufs[cm->new_fb_idx].
2479 buf.mpred_mv_wr_start_addr
2480 ) < 0) {
2481 pr_info("get_mv_buf fail\r\n");
2482 return -1;
2483 }
2484 if (debug & VP9_DEBUG_BUFMGR_DETAIL)
2485 dump_pic_list(pbi);
2486#ifdef SUPPORT_FB_DECODING
2487 }
2488#endif
2489#endif
2490 cm->cur_frame = &pool->frame_bufs[cm->new_fb_idx];
2491 /*if (debug & VP9_DEBUG_BUFMGR)
2492 pr_info("[VP9 DEBUG]%s(get_free_fb): %d\r\n", __func__,
2493 cm->new_fb_idx);*/
2494
2495 pbi->cur_buf = &frame_bufs[cm->new_fb_idx];
2496 if (pbi->mmu_enable) {
2497 /* moved to after picture size ready
2498 *alloc_mmu(cm, params->p.width, params->p.height,
2499 *params->p.bit_depth, pbi->frame_mmu_map_addr);
2500 */
2501 cm->prev_fb_idx = cm->new_fb_idx;
2502 }
2503 /*read_uncompressed_header()*/
2504 cm->last_frame_type = cm->frame_type;
2505 cm->last_intra_only = cm->intra_only;
2506 cm->profile = params->p.profile;
2507 if (cm->profile >= MAX_PROFILES) {
2508 pr_err("Error: Unsupported profile %d\r\n", cm->profile);
2509 return -1;
2510 }
2511 cm->show_existing_frame = params->p.show_existing_frame;
2512 if (cm->show_existing_frame) {
2513 /* Show an existing frame directly.*/
2514 int frame_to_show_idx = params->p.frame_to_show_idx;
2515 int frame_to_show;
2516 unsigned long flags;
2517 if (frame_to_show_idx >= REF_FRAMES) {
2518 pr_info("frame_to_show_idx %d exceed max index\r\n",
2519 frame_to_show_idx);
2520 return -1;
2521 }
2522
2523 frame_to_show = cm->ref_frame_map[frame_to_show_idx];
2524 /*pr_info("frame_to_show %d\r\n", frame_to_show);*/
2525 lock_buffer_pool(pool, flags);
2526 if (frame_to_show < 0 ||
2527 frame_bufs[frame_to_show].ref_count < 1) {
2528 unlock_buffer_pool(pool, flags);
2529 pr_err
2530 ("Error:Buffer %d does not contain a decoded frame",
2531 frame_to_show);
2532 return -1;
2533 }
2534
2535 ref_cnt_fb(frame_bufs, &cm->new_fb_idx, frame_to_show);
2536 unlock_buffer_pool(pool, flags);
2537 pbi->refresh_frame_flags = 0;
2538 /*cm->lf.filter_level = 0;*/
2539 cm->show_frame = 1;
2540
2541 /*
2542 *if (pbi->frame_parallel_decode) {
2543 * for (i = 0; i < REF_FRAMES; ++i)
2544 * cm->next_ref_frame_map[i] =
2545 * cm->ref_frame_map[i];
2546 *}
2547 */
2548 /* do not decode, search next start code */
2549 return 1;
2550 }
2551 cm->frame_type = params->p.frame_type;
2552 cm->show_frame = params->p.show_frame;
2553 cm->bit_depth = params->p.bit_depth;
2554 cm->error_resilient_mode = params->p.error_resilient_mode;
2555
2556
2557 if (cm->frame_type == KEY_FRAME) {
2558 pbi->refresh_frame_flags = (1 << REF_FRAMES) - 1;
2559
2560 for (i = 0; i < REFS_PER_FRAME; ++i) {
2561 cm->frame_refs[i].idx = INVALID_IDX;
2562 cm->frame_refs[i].buf = NULL;
2563 }
2564
2565 ret = setup_frame_size(pbi,
2566 cm, params, pbi->frame_mmu_map_addr,
2567 print_header_info);
2568 if (ret)
2569 return -1;
2570 if (pbi->need_resync) {
2571 memset(&cm->ref_frame_map, -1,
2572 sizeof(cm->ref_frame_map));
2573 pbi->need_resync = 0;
2574 }
2575 } else {
2576 cm->intra_only = cm->show_frame ? 0 : params->p.intra_only;
2577 /*if (print_header_info) {
2578 * if (cm->show_frame)
2579 * pr_info
2580 * ("intra_only set to 0 because of show_frame\n");
2581 * else
2582 * pr_info
2583 * ("1-bit intra_only read: %d\n", cm->intra_only);
2584 *}
2585 */
2586
2587
2588 cm->reset_frame_context = cm->error_resilient_mode ?
2589 0 : params->p.reset_frame_context;
2590 if (print_header_info) {
2591 if (cm->error_resilient_mode)
2592 pr_info
2593 ("reset to 0 error_resilient_mode\n");
2594 else
2595 pr_info
2596 (" * 2-bits reset_frame_context read : %d\n",
2597 cm->reset_frame_context);
2598 }
2599
2600 if (cm->intra_only) {
2601 if (cm->profile > PROFILE_0) {
2602 /*read_bitdepth_colorspace_sampling(cm,
2603 * rb, print_header_info);
2604 */
2605 } else {
2606 /*NOTE: The intra-only frame header
2607 *does not include the specification
2608 *of either the color format or
2609 *color sub-sampling
2610 *in profile 0. VP9 specifies that the default
2611 *color format should be YUV 4:2:0 in this
2612 *case (normative).
2613 */
2614 cm->color_space = VPX_CS_BT_601;
2615 cm->subsampling_y = cm->subsampling_x = 1;
2616 cm->bit_depth = VPX_BITS_8;
2617 cm->use_highbitdepth = 0;
2618 }
2619
2620 pbi->refresh_frame_flags =
2621 params->p.refresh_frame_flags;
2622 /*if (print_header_info)
2623 * pr_info("*%d-bits refresh_frame read:0x%x\n",
2624 * REF_FRAMES, pbi->refresh_frame_flags);
2625 */
2626 ret = setup_frame_size(pbi,
2627 cm,
2628 params,
2629 pbi->frame_mmu_map_addr,
2630 print_header_info);
2631 if (ret)
2632 return -1;
2633 if (pbi->need_resync) {
2634 memset(&cm->ref_frame_map, -1,
2635 sizeof(cm->ref_frame_map));
2636 pbi->need_resync = 0;
2637 }
2638 } else if (pbi->need_resync != 1) { /* Skip if need resync */
2639 pbi->refresh_frame_flags =
2640 params->p.refresh_frame_flags;
2641 if (print_header_info)
2642 pr_info
2643 ("*%d-bits refresh_frame read:0x%x\n",
2644 REF_FRAMES, pbi->refresh_frame_flags);
2645 for (i = 0; i < REFS_PER_FRAME; ++i) {
2646 const int ref =
2647 (params->p.ref_info >>
2648 (((REFS_PER_FRAME-i-1)*4)+1))
2649 & 0x7;
2650 const int idx =
2651 cm->ref_frame_map[ref];
2652 struct RefBuffer_s * const ref_frame =
2653 &cm->frame_refs[i];
2654 if (print_header_info)
2655 pr_info("*%d-bits ref[%d]read:%d\n",
2656 REF_FRAMES_LOG2, i, ref);
2657 ref_frame->idx = idx;
2658 ref_frame->buf = &frame_bufs[idx].buf;
2659 cm->ref_frame_sign_bias[LAST_FRAME + i]
2660 = (params->p.ref_info >>
2661 ((REFS_PER_FRAME-i-1)*4)) & 0x1;
2662 if (print_header_info)
2663 pr_info("1bit ref_frame_sign_bias");
2664 /*pr_info
2665 *("%dread: %d\n",
2666 *LAST_FRAME+i,
2667 *cm->ref_frame_sign_bias
2668 *[LAST_FRAME + i]);
2669 */
2670 /*pr_info
2671 *("[VP9 DEBUG]%s(get ref):%d\r\n",
2672 *__func__, ref_frame->idx);
2673 */
2674
2675 }
2676
2677 ret = setup_frame_size_with_refs(
2678 pbi,
2679 cm,
2680 params,
2681 pbi->frame_mmu_map_addr,
2682 print_header_info);
2683 if (ret)
2684 return -1;
2685 for (i = 0; i < REFS_PER_FRAME; ++i) {
2686 /*struct RefBuffer_s *const ref_buf =
2687 *&cm->frame_refs[i];
2688 */
2689 /* to do:
2690 *vp9_setup_scale_factors_for_frame
2691 */
2692 }
2693 }
2694 }
2695
2696 pic = get_frame_new_buffer(cm);
2697 if (!pic)
2698 return -1;
2699
2700 pic->bit_depth = cm->bit_depth;
2701 pic->color_space = cm->color_space;
2702 pic->slice_type = cm->frame_type;
2703
2704 if (pbi->need_resync) {
2705 pr_err
2706 ("Error: Keyframe/intra-only frame required to reset\r\n");
2707 return -1;
2708 }
2709 generate_next_ref_frames(pbi);
2710 pbi->hold_ref_buf = 1;
2711
2712#if 0
2713 if (frame_is_intra_only(cm) || cm->error_resilient_mode)
2714 vp9_setup_past_independence(cm);
2715 setup_loopfilter(&cm->lf, rb, print_header_info);
2716 setup_quantization(cm, &pbi->mb, rb, print_header_info);
2717 setup_segmentation(&cm->seg, rb, print_header_info);
2718 setup_segmentation_dequant(cm, print_header_info);
2719
2720 setup_tile_info(cm, rb, print_header_info);
2721 sz = vp9_rb_read_literal(rb, 16);
2722 if (print_header_info)
2723 pr_info(" * 16-bits size read : %d (0x%x)\n", sz, sz);
2724
2725 if (sz == 0)
2726 vpx_internal_error(&cm->error, VPX_CODEC_CORRUPT_FRAME,
2727 "Invalid header size");
2728#endif
2729 /*end read_uncompressed_header()*/
2730 cm->use_prev_frame_mvs = !cm->error_resilient_mode &&
2731 cm->width == cm->last_width &&
2732 cm->height == cm->last_height &&
2733 !cm->last_intra_only &&
2734 cm->last_show_frame &&
2735 (cm->last_frame_type != KEY_FRAME);
2736
2737 /*pr_info
2738 *("set use_prev_frame_mvs to %d (last_width %d last_height %d",
2739 *cm->use_prev_frame_mvs, cm->last_width, cm->last_height);
2740 *pr_info
2741 *(" last_intra_only %d last_show_frame %d last_frame_type %d)\n",
2742 *cm->last_intra_only, cm->last_show_frame, cm->last_frame_type);
2743 */
2744
2745 if (pbi->enable_fence && cm->show_frame) {
2746 struct PIC_BUFFER_CONFIG_s *pic = &cm->cur_frame->buf;
2747 struct vdec_s *vdec = hw_to_vdec(pbi);
2748
2749 /* create fence for each buffers. */
2750 ret = vdec_timeline_create_fence(&vdec->sync);
2751 if (ret < 0)
2752 return ret;
2753
2754 pic->fence = vdec->sync.fence;
2755 pic->bit_depth = cm->bit_depth;
2756 pic->slice_type = cm->frame_type;
2757 pic->stream_offset = pbi->pre_stream_offset;
2758
2759 if (pbi->chunk) {
2760 pic->pts = pbi->chunk->pts;
2761 pic->pts64 = pbi->chunk->pts64;
2762 pic->timestamp = pbi->chunk->timestamp;
2763 }
2764
2765 /* post video vframe. */
2766 prepare_display_buf(pbi, pic);
2767 }
2768
2769 return 0;
2770}
2771
2772
2773void swap_frame_buffers(struct VP9Decoder_s *pbi)
2774{
2775 int ref_index = 0;
2776 struct VP9_Common_s *const cm = &pbi->common;
2777 struct BufferPool_s *const pool = cm->buffer_pool;
2778 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
2779 unsigned long flags;
2780 refresh_ref_frames(pbi);
2781 pbi->hold_ref_buf = 0;
2782 cm->frame_to_show = get_frame_new_buffer(cm);
2783
2784 if (cm->frame_to_show) {
2785 /*if (!pbi->frame_parallel_decode || !cm->show_frame) {*/
2786 lock_buffer_pool(pool, flags);
2787 --frame_bufs[cm->new_fb_idx].ref_count;
2788 /*pr_info("[MMU DEBUG 8] dec ref_count[%d] : %d\r\n", cm->new_fb_idx,
2789 * frame_bufs[cm->new_fb_idx].ref_count);
2790 */
2791 unlock_buffer_pool(pool, flags);
2792 /*}*/
2793 }
2794
2795 /*Invalidate these references until the next frame starts.*/
2796 for (ref_index = 0; ref_index < 3; ref_index++)
2797 cm->frame_refs[ref_index].idx = -1;
2798}
2799
2800#if 0
2801static void check_resync(vpx_codec_alg_priv_t *const ctx,
2802 const struct VP9Decoder_s *const pbi)
2803{
2804 /* Clear resync flag if worker got a key frame or intra only frame.*/
2805 if (ctx->need_resync == 1 && pbi->need_resync == 0 &&
2806 (pbi->common.intra_only || pbi->common.frame_type == KEY_FRAME))
2807 ctx->need_resync = 0;
2808}
2809#endif
2810
2811int vp9_get_raw_frame(struct VP9Decoder_s *pbi, struct PIC_BUFFER_CONFIG_s *sd)
2812{
2813 struct VP9_Common_s *const cm = &pbi->common;
2814 int ret = -1;
2815
2816 if (pbi->ready_for_new_data == 1)
2817 return ret;
2818
2819 pbi->ready_for_new_data = 1;
2820
2821 /* no raw frame to show!!! */
2822 if (!cm->show_frame)
2823 return ret;
2824
2825 /* may not be get buff in v4l2 */
2826 if (!cm->frame_to_show)
2827 return ret;
2828
2829 pbi->ready_for_new_data = 1;
2830
2831 *sd = *cm->frame_to_show;
2832 ret = 0;
2833
2834 return ret;
2835}
2836
2837int vp9_bufmgr_init(struct VP9Decoder_s *pbi, struct BuffInfo_s *buf_spec_i,
2838 struct buff_s *mc_buf_i) {
2839 struct VP9_Common_s *cm = &pbi->common;
2840
2841 /*memset(pbi, 0, sizeof(struct VP9Decoder_s));*/
2842 pbi->frame_count = 0;
2843 pbi->pic_count = 0;
2844 pbi->pre_stream_offset = 0;
2845 cm->buffer_pool = &pbi->vp9_buffer_pool;
2846 spin_lock_init(&cm->buffer_pool->lock);
2847 cm->prev_fb_idx = INVALID_IDX;
2848 cm->new_fb_idx = INVALID_IDX;
2849 pbi->used_4k_num = -1;
2850 cm->cur_fb_idx_mmu = INVALID_IDX;
2851 pr_debug
2852 ("After vp9_bufmgr_init, prev_fb_idx : %d, new_fb_idx : %d\r\n",
2853 cm->prev_fb_idx, cm->new_fb_idx);
2854 pbi->need_resync = 1;
2855 /* Initialize the references to not point to any frame buffers.*/
2856 memset(&cm->ref_frame_map, -1, sizeof(cm->ref_frame_map));
2857 memset(&cm->next_ref_frame_map, -1, sizeof(cm->next_ref_frame_map));
2858 cm->current_video_frame = 0;
2859 pbi->ready_for_new_data = 1;
2860
2861 /* private init */
2862 pbi->work_space_buf = buf_spec_i;
2863 if (!pbi->mmu_enable)
2864 pbi->mc_buf = mc_buf_i;
2865
2866 pbi->rpm_addr = NULL;
2867 pbi->lmem_addr = NULL;
2868
2869 pbi->use_cma_flag = 0;
2870 pbi->decode_idx = 0;
2871 pbi->slice_idx = 0;
2872 /*int m_uiMaxCUWidth = 1<<7;*/
2873 /*int m_uiMaxCUHeight = 1<<7;*/
2874 pbi->has_keyframe = 0;
2875 pbi->skip_flag = 0;
2876 pbi->wait_buf = 0;
2877 pbi->error_flag = 0;
2878
2879 pbi->pts_mode = PTS_NORMAL;
2880 pbi->last_pts = 0;
2881 pbi->last_lookup_pts = 0;
2882 pbi->last_pts_us64 = 0;
2883 pbi->last_lookup_pts_us64 = 0;
2884 pbi->shift_byte_count = 0;
2885 pbi->shift_byte_count_lo = 0;
2886 pbi->shift_byte_count_hi = 0;
2887 pbi->pts_mode_switching_count = 0;
2888 pbi->pts_mode_recovery_count = 0;
2889
2890 pbi->buf_num = 0;
2891 pbi->pic_num = 0;
2892
2893 return 0;
2894}
2895
2896int vp9_bufmgr_postproc(struct VP9Decoder_s *pbi)
2897{
2898 struct vdec_s *vdec = hw_to_vdec(pbi);
2899 struct VP9_Common_s *cm = &pbi->common;
2900 struct PIC_BUFFER_CONFIG_s sd;
2901
2902 if (pbi->postproc_done)
2903 return 0;
2904 pbi->postproc_done = 1;
2905 swap_frame_buffers(pbi);
2906 if (!cm->show_existing_frame) {
2907 cm->last_show_frame = cm->show_frame;
2908 cm->prev_frame = cm->cur_frame;
2909#if 0
2910 if (cm->seg.enabled && !pbi->frame_parallel_decode)
2911 vp9_swap_current_and_last_seg_map(cm);
2912#endif
2913 }
2914 cm->last_width = cm->width;
2915 cm->last_height = cm->height;
2916 if (cm->show_frame)
2917 cm->current_video_frame++;
2918
2919 if (vp9_get_raw_frame(pbi, &sd) == 0) {
2920 /*pr_info("Display frame index %d\r\n", sd.index);*/
2921 sd.stream_offset = pbi->pre_stream_offset;
2922
2923 if (pbi->enable_fence) {
2924 /* notify signal to wake up wq of fence. */
2925 vdec_timeline_increase(&vdec->sync, 1);
2926 } else {
2927 prepare_display_buf(pbi, &sd);
2928 }
2929
2930 pbi->pre_stream_offset = READ_VREG(HEVC_SHIFT_BYTE_COUNT);
2931 }
2932
2933/* else
2934 * pr_info
2935 * ("Not display this frame,ready_for_new_data%d show_frame%d\r\n",
2936 * pbi->ready_for_new_data, cm->show_frame);
2937 */
2938 return 0;
2939}
2940
2941/**************************************************
2942 *
2943 *VP9 buffer management end
2944 *
2945 ***************************************************
2946 */
2947
2948
2949#define HEVC_CM_BODY_START_ADDR 0x3626
2950#define HEVC_CM_BODY_LENGTH 0x3627
2951#define HEVC_CM_HEADER_LENGTH 0x3629
2952#define HEVC_CM_HEADER_OFFSET 0x362b
2953
2954#define LOSLESS_COMPRESS_MODE
2955
2956/*#define DECOMP_HEADR_SURGENT*/
2957#ifdef VP9_10B_NV21
2958static u32 mem_map_mode = 2 /* 0:linear 1:32x32 2:64x32*/
2959#else
2960static u32 mem_map_mode; /* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */
2961#endif
2962static u32 enable_mem_saving = 1;
2963static u32 force_w_h;
2964
2965static u32 force_fps;
2966
2967
2968const u32 vp9_version = 201602101;
2969static u32 debug;
2970static u32 radr;
2971static u32 rval;
2972static u32 pop_shorts;
2973static u32 dbg_cmd;
2974static u32 dbg_skip_decode_index;
2975static u32 endian = 0xff0;
2976#ifdef ERROR_HANDLE_DEBUG
2977static u32 dbg_nal_skip_flag;
2978 /* bit[0], skip vps; bit[1], skip sps; bit[2], skip pps */
2979static u32 dbg_nal_skip_count;
2980#endif
2981/*for debug*/
2982static u32 decode_pic_begin;
2983static uint slice_parse_begin;
2984static u32 step;
2985#ifdef MIX_STREAM_SUPPORT
2986static u32 buf_alloc_width = 4096;
2987static u32 buf_alloc_height = 2304;
2988static u32 vp9_max_pic_w = 4096;
2989static u32 vp9_max_pic_h = 2304;
2990
2991static u32 dynamic_buf_num_margin;
2992#else
2993static u32 buf_alloc_width;
2994static u32 buf_alloc_height;
2995static u32 dynamic_buf_num_margin = 7;
2996#endif
2997static u32 buf_alloc_depth = 10;
2998static u32 buf_alloc_size;
2999/*
3000 *bit[0]: 0,
3001 * bit[1]: 0, always release cma buffer when stop
3002 * bit[1]: 1, never release cma buffer when stop
3003 *bit[0]: 1, when stop, release cma buffer if blackout is 1;
3004 *do not release cma buffer is blackout is not 1
3005 *
3006 *bit[2]: 0, when start decoding, check current displayed buffer
3007 * (only for buffer decoded by vp9) if blackout is 0
3008 * 1, do not check current displayed buffer
3009 *
3010 *bit[3]: 1, if blackout is not 1, do not release current
3011 * displayed cma buffer always.
3012 */
3013/* set to 1 for fast play;
3014 * set to 8 for other case of "keep last frame"
3015 */
3016static u32 buffer_mode = 1;
3017/* buffer_mode_dbg: debug only*/
3018static u32 buffer_mode_dbg = 0xffff0000;
3019/**/
3020
3021/*
3022 *bit 0, 1: only display I picture;
3023 *bit 1, 1: only decode I picture;
3024 */
3025static u32 i_only_flag;
3026
3027static u32 low_latency_flag;
3028
3029static u32 no_head;
3030
3031static u32 max_decoding_time;
3032/*
3033 *error handling
3034 */
3035/*error_handle_policy:
3036 *bit 0: 0, auto skip error_skip_nal_count nals before error recovery;
3037 *1, skip error_skip_nal_count nals before error recovery;
3038 *bit 1 (valid only when bit0 == 1):
3039 *1, wait vps/sps/pps after error recovery;
3040 *bit 2 (valid only when bit0 == 0):
3041 *0, auto search after error recovery (vp9_recover() called);
3042 *1, manual search after error recovery
3043 *(change to auto search after get IDR: WRITE_VREG(NAL_SEARCH_CTL, 0x2))
3044 *
3045 *bit 4: 0, set error_mark after reset/recover
3046 * 1, do not set error_mark after reset/recover
3047 *bit 5: 0, check total lcu for every picture
3048 * 1, do not check total lcu
3049 *
3050 */
3051
3052static u32 error_handle_policy;
3053/*static u32 parser_sei_enable = 1;*/
3054#define MAX_BUF_NUM_NORMAL 12
3055#define MAX_BUF_NUM_LESS 10
3056static u32 max_buf_num = MAX_BUF_NUM_NORMAL;
3057#define MAX_BUF_NUM_SAVE_BUF 8
3058
3059static u32 run_ready_min_buf_num = 2;
3060
3061
3062static DEFINE_MUTEX(vvp9_mutex);
3063#ifndef MULTI_INSTANCE_SUPPORT
3064static struct device *cma_dev;
3065#endif
3066
3067#define HEVC_DEC_STATUS_REG HEVC_ASSIST_SCRATCH_0
3068#define HEVC_RPM_BUFFER HEVC_ASSIST_SCRATCH_1
3069#define HEVC_SHORT_TERM_RPS HEVC_ASSIST_SCRATCH_2
3070#define VP9_ADAPT_PROB_REG HEVC_ASSIST_SCRATCH_3
3071#define VP9_MMU_MAP_BUFFER HEVC_ASSIST_SCRATCH_4
3072#define HEVC_PPS_BUFFER HEVC_ASSIST_SCRATCH_5
3073#define HEVC_SAO_UP HEVC_ASSIST_SCRATCH_6
3074#define HEVC_STREAM_SWAP_BUFFER HEVC_ASSIST_SCRATCH_7
3075#define HEVC_STREAM_SWAP_BUFFER2 HEVC_ASSIST_SCRATCH_8
3076#define VP9_PROB_SWAP_BUFFER HEVC_ASSIST_SCRATCH_9
3077#define VP9_COUNT_SWAP_BUFFER HEVC_ASSIST_SCRATCH_A
3078#define VP9_SEG_MAP_BUFFER HEVC_ASSIST_SCRATCH_B
3079#define HEVC_SCALELUT HEVC_ASSIST_SCRATCH_D
3080#define HEVC_WAIT_FLAG HEVC_ASSIST_SCRATCH_E
3081#define RPM_CMD_REG HEVC_ASSIST_SCRATCH_F
3082#define LMEM_DUMP_ADR HEVC_ASSIST_SCRATCH_F
3083#define HEVC_STREAM_SWAP_TEST HEVC_ASSIST_SCRATCH_L
3084#ifdef MULTI_INSTANCE_SUPPORT
3085#define HEVC_DECODE_COUNT HEVC_ASSIST_SCRATCH_M
3086#define HEVC_DECODE_SIZE HEVC_ASSIST_SCRATCH_N
3087#else
3088#define HEVC_DECODE_PIC_BEGIN_REG HEVC_ASSIST_SCRATCH_M
3089#define HEVC_DECODE_PIC_NUM_REG HEVC_ASSIST_SCRATCH_N
3090#endif
3091#define DEBUG_REG1 HEVC_ASSIST_SCRATCH_G
3092#define DEBUG_REG2 HEVC_ASSIST_SCRATCH_H
3093
3094
3095/*
3096 *ucode parser/search control
3097 *bit 0: 0, header auto parse; 1, header manual parse
3098 *bit 1: 0, auto skip for noneseamless stream; 1, no skip
3099 *bit [3:2]: valid when bit1==0;
3100 *0, auto skip nal before first vps/sps/pps/idr;
3101 *1, auto skip nal before first vps/sps/pps
3102 *2, auto skip nal before first vps/sps/pps,
3103 * and not decode until the first I slice (with slice address of 0)
3104 *
3105 *3, auto skip before first I slice (nal_type >=16 && nal_type<=21)
3106 *bit [15:4] nal skip count (valid when bit0 == 1 (manual mode) )
3107 *bit [16]: for NAL_UNIT_EOS when bit0 is 0:
3108 * 0, send SEARCH_DONE to arm ; 1, do not send SEARCH_DONE to arm
3109 *bit [17]: for NAL_SEI when bit0 is 0:
3110 * 0, do not parse SEI in ucode; 1, parse SEI in ucode
3111 *bit [31:20]: used by ucode for debug purpose
3112 */
3113#define NAL_SEARCH_CTL HEVC_ASSIST_SCRATCH_I
3114 /*[31:24] chip feature
3115 31: 0, use MBOX1; 1, use MBOX0
3116 */
3117#define DECODE_MODE HEVC_ASSIST_SCRATCH_J
3118#define DECODE_STOP_POS HEVC_ASSIST_SCRATCH_K
3119
3120#ifdef MULTI_INSTANCE_SUPPORT
3121#define RPM_BUF_SIZE (0x400 * 2)
3122#else
3123#define RPM_BUF_SIZE (0x80*2)
3124#endif
3125#define LMEM_BUF_SIZE (0x400 * 2)
3126
3127#define WORK_BUF_SPEC_NUM 3
3128static struct BuffInfo_s amvvp9_workbuff_spec[WORK_BUF_SPEC_NUM] = {
3129 {
3130 /* 8M bytes */
3131 .max_width = 1920,
3132 .max_height = 1088,
3133 .ipp = {
3134 /* IPP work space calculation :
3135 * 4096 * (Y+CbCr+Flags) = 12k, round to 16k
3136 */
3137 .buf_size = 0x4000,
3138 },
3139 .sao_abv = {
3140 .buf_size = 0x30000,
3141 },
3142 .sao_vb = {
3143 .buf_size = 0x30000,
3144 },
3145 .short_term_rps = {
3146 /* SHORT_TERM_RPS - Max 64 set, 16 entry every set,
3147 * total 64x16x2 = 2048 bytes (0x800)
3148 */
3149 .buf_size = 0x800,
3150 },
3151 .vps = {
3152 /* VPS STORE AREA - Max 16 VPS, each has 0x80 bytes,
3153 * total 0x0800 bytes
3154 */
3155 .buf_size = 0x800,
3156 },
3157 .sps = {
3158 /* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes,
3159 * total 0x0800 bytes
3160 */
3161 .buf_size = 0x800,
3162 },
3163 .pps = {
3164 /* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes,
3165 * total 0x2000 bytes
3166 */
3167 .buf_size = 0x2000,
3168 },
3169 .sao_up = {
3170 /* SAO UP STORE AREA - Max 640(10240/16) LCU,
3171 * each has 16 bytes total 0x2800 bytes
3172 */
3173 .buf_size = 0x2800,
3174 },
3175 .swap_buf = {
3176 /* 256cyclex64bit = 2K bytes 0x800
3177 * (only 144 cycles valid)
3178 */
3179 .buf_size = 0x800,
3180 },
3181 .swap_buf2 = {
3182 .buf_size = 0x800,
3183 },
3184 .scalelut = {
3185 /* support up to 32 SCALELUT 1024x32 =
3186 * 32Kbytes (0x8000)
3187 */
3188 .buf_size = 0x8000,
3189 },
3190 .dblk_para = {
3191 /* DBLK -> Max 256(4096/16) LCU,
3192 *each para 1024bytes(total:0x40000),
3193 *data 1024bytes(total:0x40000)
3194 */
3195 .buf_size = 0x80000,
3196 },
3197 .dblk_data = {
3198 .buf_size = 0x80000,
3199 },
3200 .seg_map = {
3201 /*4096x2304/64/64 *24 = 0xd800 Bytes*/
3202 .buf_size = 0xd800,
3203 },
3204 .mmu_vbh = {
3205 .buf_size = 0x5000, /*2*16*(more than 2304)/4, 4K*/
3206 },
3207#if 0
3208 .cm_header = {
3209 /*add one for keeper.*/
3210 .buf_size = MMU_COMPRESS_HEADER_SIZE *
3211 (FRAME_BUFFERS + 1),
3212 /* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) */
3213 },
3214#endif
3215 .mpred_above = {
3216 .buf_size = 0x10000, /* 2 * size of hevc*/
3217 },
3218#ifdef MV_USE_FIXED_BUF
3219 .mpred_mv = {/* 1080p, 0x40000 per buffer */
3220 .buf_size = 0x40000 * FRAME_BUFFERS,
3221 },
3222#endif
3223 .rpm = {
3224 .buf_size = RPM_BUF_SIZE,
3225 },
3226 .lmem = {
3227 .buf_size = 0x400 * 2,
3228 }
3229 },
3230 {
3231 .max_width = 4096,
3232 .max_height = 2304,
3233 .ipp = {
3234 /* IPP work space calculation :
3235 * 4096 * (Y+CbCr+Flags) = 12k, round to 16k
3236 */
3237 .buf_size = 0x4000,
3238 },
3239 .sao_abv = {
3240 .buf_size = 0x30000,
3241 },
3242 .sao_vb = {
3243 .buf_size = 0x30000,
3244 },
3245 .short_term_rps = {
3246 /* SHORT_TERM_RPS - Max 64 set, 16 entry every set,
3247 * total 64x16x2 = 2048 bytes (0x800)
3248 */
3249 .buf_size = 0x800,
3250 },
3251 .vps = {
3252 /* VPS STORE AREA - Max 16 VPS, each has 0x80 bytes,
3253 * total 0x0800 bytes
3254 */
3255 .buf_size = 0x800,
3256 },
3257 .sps = {
3258 /* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes,
3259 * total 0x0800 bytes
3260 */
3261 .buf_size = 0x800,
3262 },
3263 .pps = {
3264 /* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes,
3265 * total 0x2000 bytes
3266 */
3267 .buf_size = 0x2000,
3268 },
3269 .sao_up = {
3270 /* SAO UP STORE AREA - Max 640(10240/16) LCU,
3271 * each has 16 bytes total 0x2800 bytes
3272 */
3273 .buf_size = 0x2800,
3274 },
3275 .swap_buf = {
3276 /* 256cyclex64bit = 2K bytes 0x800
3277 * (only 144 cycles valid)
3278 */
3279 .buf_size = 0x800,
3280 },
3281 .swap_buf2 = {
3282 .buf_size = 0x800,
3283 },
3284 .scalelut = {
3285 /* support up to 32 SCALELUT 1024x32 = 32Kbytes
3286 * (0x8000)
3287 */
3288 .buf_size = 0x8000,
3289 },
3290 .dblk_para = {
3291 /* DBLK -> Max 256(4096/16) LCU,
3292 *each para 1024bytes(total:0x40000),
3293 *data 1024bytes(total:0x40000)
3294 */
3295 .buf_size = 0x80000,
3296 },
3297 .dblk_data = {
3298 .buf_size = 0x80000,
3299 },
3300 .seg_map = {
3301 /*4096x2304/64/64 *24 = 0xd800 Bytes*/
3302 .buf_size = 0xd800,
3303 },
3304 .mmu_vbh = {
3305 .buf_size = 0x5000,/*2*16*(more than 2304)/4, 4K*/
3306 },
3307#if 0
3308 .cm_header = {
3309 /*add one for keeper.*/
3310 .buf_size = MMU_COMPRESS_HEADER_SIZE *
3311 (FRAME_BUFFERS + 1),
3312 /* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) */
3313 },
3314#endif
3315 .mpred_above = {
3316 .buf_size = 0x10000, /* 2 * size of hevc*/
3317 },
3318#ifdef MV_USE_FIXED_BUF
3319 .mpred_mv = {
3320 /* .buf_size = 0x100000*16,
3321 * //4k2k , 0x100000 per buffer
3322 */
3323 /* 4096x2304 , 0x120000 per buffer */
3324 .buf_size = 0x120000 * FRAME_BUFFERS,
3325 },
3326#endif
3327 .rpm = {
3328 .buf_size = RPM_BUF_SIZE,
3329 },
3330 .lmem = {
3331 .buf_size = 0x400 * 2,
3332 }
3333 },
3334 {
3335 .max_width = 4096*2,
3336 .max_height = 2304*2,
3337 .ipp = {
3338 // IPP work space calculation : 4096 * (Y+CbCr+Flags) = 12k, round to 16k
3339 .buf_size = 0x4000*2,
3340 },
3341 .sao_abv = {
3342 .buf_size = 0x30000*2,
3343 },
3344 .sao_vb = {
3345 .buf_size = 0x30000*2,
3346 },
3347 .short_term_rps = {
3348 // SHORT_TERM_RPS - Max 64 set, 16 entry every set, total 64x16x2 = 2048 bytes (0x800)
3349 .buf_size = 0x800,
3350 },
3351 .vps = {
3352 // VPS STORE AREA - Max 16 VPS, each has 0x80 bytes, total 0x0800 bytes
3353 .buf_size = 0x800,
3354 },
3355 .sps = {
3356 // SPS STORE AREA - Max 16 SPS, each has 0x80 bytes, total 0x0800 bytes
3357 .buf_size = 0x800,
3358 },
3359 .pps = {
3360 // PPS STORE AREA - Max 64 PPS, each has 0x80 bytes, total 0x2000 bytes
3361 .buf_size = 0x2000,
3362 },
3363 .sao_up = {
3364 // SAO UP STORE AREA - Max 640(10240/16) LCU, each has 16 bytes total 0x2800 bytes
3365 .buf_size = 0x2800*2,
3366 },
3367 .swap_buf = {
3368 // 256cyclex64bit = 2K bytes 0x800 (only 144 cycles valid)
3369 .buf_size = 0x800,
3370 },
3371 .swap_buf2 = {
3372 .buf_size = 0x800,
3373 },
3374 .scalelut = {
3375 // support up to 32 SCALELUT 1024x32 = 32Kbytes (0x8000)
3376 .buf_size = 0x8000*2,
3377 },
3378 .dblk_para = {
3379 // DBLK -> Max 256(4096/16) LCU, each para 1024bytes(total:0x40000), data 1024bytes(total:0x40000)
3380 .buf_size = 0x80000*2,
3381 },
3382 .dblk_data = {
3383 .buf_size = 0x80000*2,
3384 },
3385 .seg_map = {
3386 /*4096x2304/64/64 *24 = 0xd800 Bytes*/
3387 .buf_size = 0xd800*4,
3388 },
3389 .mmu_vbh = {
3390 .buf_size = 0x5000*2, //2*16*(more than 2304)/4, 4K
3391 },
3392#if 0
3393 .cm_header = {
3394 //.buf_size = MMU_COMPRESS_HEADER_SIZE*8, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
3395 .buf_size = MMU_COMPRESS_HEADER_SIZE*16, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
3396 },
3397#endif
3398 .mpred_above = {
3399 .buf_size = 0x10000*2, /* 2 * size of hevc*/
3400 },
3401#ifdef MV_USE_FIXED_BUF
3402 .mpred_mv = {
3403 //4k2k , 0x100000 per buffer */
3404 /* 4096x2304 , 0x120000 per buffer */
3405 .buf_size = 0x120000 * FRAME_BUFFERS * 4,
3406 },
3407#endif
3408 .rpm = {
3409 .buf_size = RPM_BUF_SIZE,
3410 },
3411 .lmem = {
3412 .buf_size = 0x400 * 2,
3413 }
3414 }
3415};
3416
3417
3418/*Losless compression body buffer size 4K per 64x32 (jt)*/
3419int compute_losless_comp_body_size(int width, int height,
3420 uint8_t is_bit_depth_10)
3421{
3422 int width_x64;
3423 int height_x32;
3424 int bsize;
3425
3426 width_x64 = width + 63;
3427 width_x64 >>= 6;
3428 height_x32 = height + 31;
3429 height_x32 >>= 5;
3430 bsize = (is_bit_depth_10?4096:3200)*width_x64*height_x32;
3431 if (debug & VP9_DEBUG_BUFMGR_MORE)
3432 pr_info("%s(%d,%d,%d)=>%d\n",
3433 __func__, width, height,
3434 is_bit_depth_10, bsize);
3435
3436 return bsize;
3437}
3438
3439/* Losless compression header buffer size 32bytes per 128x64 (jt)*/
3440static int compute_losless_comp_header_size(int width, int height)
3441{
3442 int width_x128;
3443 int height_x64;
3444 int hsize;
3445
3446 width_x128 = width + 127;
3447 width_x128 >>= 7;
3448 height_x64 = height + 63;
3449 height_x64 >>= 6;
3450
3451 hsize = 32 * width_x128 * height_x64;
3452 if (debug & VP9_DEBUG_BUFMGR_MORE)
3453 pr_info("%s(%d,%d)=>%d\n",
3454 __func__, width, height,
3455 hsize);
3456
3457 return hsize;
3458}
3459
3460static void init_buff_spec(struct VP9Decoder_s *pbi,
3461 struct BuffInfo_s *buf_spec)
3462{
3463 void *mem_start_virt;
3464
3465 buf_spec->ipp.buf_start = buf_spec->start_adr;
3466 buf_spec->sao_abv.buf_start =
3467 buf_spec->ipp.buf_start + buf_spec->ipp.buf_size;
3468
3469 buf_spec->sao_vb.buf_start =
3470 buf_spec->sao_abv.buf_start + buf_spec->sao_abv.buf_size;
3471 buf_spec->short_term_rps.buf_start =
3472 buf_spec->sao_vb.buf_start + buf_spec->sao_vb.buf_size;
3473 buf_spec->vps.buf_start =
3474 buf_spec->short_term_rps.buf_start +
3475 buf_spec->short_term_rps.buf_size;
3476 buf_spec->sps.buf_start =
3477 buf_spec->vps.buf_start + buf_spec->vps.buf_size;
3478 buf_spec->pps.buf_start =
3479 buf_spec->sps.buf_start + buf_spec->sps.buf_size;
3480 buf_spec->sao_up.buf_start =
3481 buf_spec->pps.buf_start + buf_spec->pps.buf_size;
3482 buf_spec->swap_buf.buf_start =
3483 buf_spec->sao_up.buf_start + buf_spec->sao_up.buf_size;
3484 buf_spec->swap_buf2.buf_start =
3485 buf_spec->swap_buf.buf_start + buf_spec->swap_buf.buf_size;
3486 buf_spec->scalelut.buf_start =
3487 buf_spec->swap_buf2.buf_start + buf_spec->swap_buf2.buf_size;
3488 buf_spec->dblk_para.buf_start =
3489 buf_spec->scalelut.buf_start + buf_spec->scalelut.buf_size;
3490 buf_spec->dblk_data.buf_start =
3491 buf_spec->dblk_para.buf_start + buf_spec->dblk_para.buf_size;
3492 buf_spec->seg_map.buf_start =
3493 buf_spec->dblk_data.buf_start + buf_spec->dblk_data.buf_size;
3494 if (pbi == NULL || pbi->mmu_enable) {
3495 buf_spec->mmu_vbh.buf_start =
3496 buf_spec->seg_map.buf_start +
3497 buf_spec->seg_map.buf_size;
3498 buf_spec->mpred_above.buf_start =
3499 buf_spec->mmu_vbh.buf_start +
3500 buf_spec->mmu_vbh.buf_size;
3501 } else {
3502 buf_spec->mpred_above.buf_start =
3503 buf_spec->seg_map.buf_start + buf_spec->seg_map.buf_size;
3504 }
3505#ifdef MV_USE_FIXED_BUF
3506 buf_spec->mpred_mv.buf_start =
3507 buf_spec->mpred_above.buf_start +
3508 buf_spec->mpred_above.buf_size;
3509
3510 buf_spec->rpm.buf_start =
3511 buf_spec->mpred_mv.buf_start +
3512 buf_spec->mpred_mv.buf_size;
3513#else
3514 buf_spec->rpm.buf_start =
3515 buf_spec->mpred_above.buf_start +
3516 buf_spec->mpred_above.buf_size;
3517
3518#endif
3519 buf_spec->lmem.buf_start =
3520 buf_spec->rpm.buf_start +
3521 buf_spec->rpm.buf_size;
3522 buf_spec->end_adr =
3523 buf_spec->lmem.buf_start +
3524 buf_spec->lmem.buf_size;
3525
3526 if (!pbi)
3527 return;
3528
3529 if (!vdec_secure(hw_to_vdec(pbi))) {
3530 mem_start_virt =
3531 codec_mm_phys_to_virt(buf_spec->dblk_para.buf_start);
3532 if (mem_start_virt) {
3533 memset(mem_start_virt, 0,
3534 buf_spec->dblk_para.buf_size);
3535 codec_mm_dma_flush(mem_start_virt,
3536 buf_spec->dblk_para.buf_size,
3537 DMA_TO_DEVICE);
3538 } else {
3539 mem_start_virt = codec_mm_vmap(
3540 buf_spec->dblk_para.buf_start,
3541 buf_spec->dblk_para.buf_size);
3542 if (mem_start_virt) {
3543 memset(mem_start_virt, 0,
3544 buf_spec->dblk_para.buf_size);
3545 codec_mm_dma_flush(mem_start_virt,
3546 buf_spec->dblk_para.buf_size,
3547 DMA_TO_DEVICE);
3548 codec_mm_unmap_phyaddr(mem_start_virt);
3549 } else {
3550 /*not virt for tvp playing,
3551 may need clear on ucode.*/
3552 pr_err("mem_start_virt failed\n");
3553 }
3554 }
3555 }
3556
3557 if (debug) {
3558 pr_info("%s workspace (%x %x) size = %x\n", __func__,
3559 buf_spec->start_adr, buf_spec->end_adr,
3560 buf_spec->end_adr - buf_spec->start_adr);
3561 }
3562
3563 if (debug) {
3564 pr_info("ipp.buf_start :%x\n",
3565 buf_spec->ipp.buf_start);
3566 pr_info("sao_abv.buf_start :%x\n",
3567 buf_spec->sao_abv.buf_start);
3568 pr_info("sao_vb.buf_start :%x\n",
3569 buf_spec->sao_vb.buf_start);
3570 pr_info("short_term_rps.buf_start :%x\n",
3571 buf_spec->short_term_rps.buf_start);
3572 pr_info("vps.buf_start :%x\n",
3573 buf_spec->vps.buf_start);
3574 pr_info("sps.buf_start :%x\n",
3575 buf_spec->sps.buf_start);
3576 pr_info("pps.buf_start :%x\n",
3577 buf_spec->pps.buf_start);
3578 pr_info("sao_up.buf_start :%x\n",
3579 buf_spec->sao_up.buf_start);
3580 pr_info("swap_buf.buf_start :%x\n",
3581 buf_spec->swap_buf.buf_start);
3582 pr_info("swap_buf2.buf_start :%x\n",
3583 buf_spec->swap_buf2.buf_start);
3584 pr_info("scalelut.buf_start :%x\n",
3585 buf_spec->scalelut.buf_start);
3586 pr_info("dblk_para.buf_start :%x\n",
3587 buf_spec->dblk_para.buf_start);
3588 pr_info("dblk_data.buf_start :%x\n",
3589 buf_spec->dblk_data.buf_start);
3590 pr_info("seg_map.buf_start :%x\n",
3591 buf_spec->seg_map.buf_start);
3592 if (pbi->mmu_enable) {
3593 pr_info("mmu_vbh.buf_start :%x\n",
3594 buf_spec->mmu_vbh.buf_start);
3595 }
3596 pr_info("mpred_above.buf_start :%x\n",
3597 buf_spec->mpred_above.buf_start);
3598#ifdef MV_USE_FIXED_BUF
3599 pr_info("mpred_mv.buf_start :%x\n",
3600 buf_spec->mpred_mv.buf_start);
3601#endif
3602 if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0) {
3603 pr_info("rpm.buf_start :%x\n",
3604 buf_spec->rpm.buf_start);
3605 }
3606 }
3607}
3608
3609/* cache_util.c */
3610#define THODIYIL_MCRCC_CANVAS_ALGX 4
3611
3612static u32 mcrcc_cache_alg_flag = THODIYIL_MCRCC_CANVAS_ALGX;
3613
3614static void mcrcc_perfcount_reset(void)
3615{
3616 if (debug & VP9_DEBUG_CACHE)
3617 pr_info("[cache_util.c] Entered mcrcc_perfcount_reset...\n");
3618 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x1);
3619 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x0);
3620 return;
3621}
3622
3623static unsigned raw_mcr_cnt_total_prev;
3624static unsigned hit_mcr_0_cnt_total_prev;
3625static unsigned hit_mcr_1_cnt_total_prev;
3626static unsigned byp_mcr_cnt_nchcanv_total_prev;
3627static unsigned byp_mcr_cnt_nchoutwin_total_prev;
3628
3629static void mcrcc_get_hitrate(unsigned reset_pre)
3630{
3631 unsigned delta_hit_mcr_0_cnt;
3632 unsigned delta_hit_mcr_1_cnt;
3633 unsigned delta_raw_mcr_cnt;
3634 unsigned delta_mcr_cnt_nchcanv;
3635 unsigned delta_mcr_cnt_nchoutwin;
3636
3637 unsigned tmp;
3638 unsigned raw_mcr_cnt;
3639 unsigned hit_mcr_cnt;
3640 unsigned byp_mcr_cnt_nchoutwin;
3641 unsigned byp_mcr_cnt_nchcanv;
3642 int hitrate;
3643 if (reset_pre) {
3644 raw_mcr_cnt_total_prev = 0;
3645 hit_mcr_0_cnt_total_prev = 0;
3646 hit_mcr_1_cnt_total_prev = 0;
3647 byp_mcr_cnt_nchcanv_total_prev = 0;
3648 byp_mcr_cnt_nchoutwin_total_prev = 0;
3649 }
3650 if (debug & VP9_DEBUG_CACHE)
3651 pr_info("[cache_util.c] Entered mcrcc_get_hitrate...\n");
3652 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x0<<1));
3653 raw_mcr_cnt = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3654 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x1<<1));
3655 hit_mcr_cnt = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3656 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x2<<1));
3657 byp_mcr_cnt_nchoutwin = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3658 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x3<<1));
3659 byp_mcr_cnt_nchcanv = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3660
3661 if (debug & VP9_DEBUG_CACHE)
3662 pr_info("raw_mcr_cnt_total: %d\n",
3663 raw_mcr_cnt);
3664 if (debug & VP9_DEBUG_CACHE)
3665 pr_info("hit_mcr_cnt_total: %d\n",
3666 hit_mcr_cnt);
3667 if (debug & VP9_DEBUG_CACHE)
3668 pr_info("byp_mcr_cnt_nchoutwin_total: %d\n",
3669 byp_mcr_cnt_nchoutwin);
3670 if (debug & VP9_DEBUG_CACHE)
3671 pr_info("byp_mcr_cnt_nchcanv_total: %d\n",
3672 byp_mcr_cnt_nchcanv);
3673
3674 delta_raw_mcr_cnt = raw_mcr_cnt -
3675 raw_mcr_cnt_total_prev;
3676 delta_mcr_cnt_nchcanv = byp_mcr_cnt_nchcanv -
3677 byp_mcr_cnt_nchcanv_total_prev;
3678 delta_mcr_cnt_nchoutwin = byp_mcr_cnt_nchoutwin -
3679 byp_mcr_cnt_nchoutwin_total_prev;
3680 raw_mcr_cnt_total_prev = raw_mcr_cnt;
3681 byp_mcr_cnt_nchcanv_total_prev = byp_mcr_cnt_nchcanv;
3682 byp_mcr_cnt_nchoutwin_total_prev = byp_mcr_cnt_nchoutwin;
3683
3684 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x4<<1));
3685 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3686 if (debug & VP9_DEBUG_CACHE)
3687 pr_info("miss_mcr_0_cnt_total: %d\n", tmp);
3688 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x5<<1));
3689 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3690 if (debug & VP9_DEBUG_CACHE)
3691 pr_info("miss_mcr_1_cnt_total: %d\n", tmp);
3692 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x6<<1));
3693 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3694 if (debug & VP9_DEBUG_CACHE)
3695 pr_info("hit_mcr_0_cnt_total: %d\n", tmp);
3696 delta_hit_mcr_0_cnt = tmp - hit_mcr_0_cnt_total_prev;
3697 hit_mcr_0_cnt_total_prev = tmp;
3698 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x7<<1));
3699 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3700 if (debug & VP9_DEBUG_CACHE)
3701 pr_info("hit_mcr_1_cnt_total: %d\n", tmp);
3702 delta_hit_mcr_1_cnt = tmp - hit_mcr_1_cnt_total_prev;
3703 hit_mcr_1_cnt_total_prev = tmp;
3704
3705 if (delta_raw_mcr_cnt != 0) {
3706 hitrate = 100 * delta_hit_mcr_0_cnt
3707 / delta_raw_mcr_cnt;
3708 if (debug & VP9_DEBUG_CACHE)
3709 pr_info("CANV0_HIT_RATE : %d\n", hitrate);
3710 hitrate = 100 * delta_hit_mcr_1_cnt
3711 / delta_raw_mcr_cnt;
3712 if (debug & VP9_DEBUG_CACHE)
3713 pr_info("CANV1_HIT_RATE : %d\n", hitrate);
3714 hitrate = 100 * delta_mcr_cnt_nchcanv
3715 / delta_raw_mcr_cnt;
3716 if (debug & VP9_DEBUG_CACHE)
3717 pr_info("NONCACH_CANV_BYP_RATE : %d\n", hitrate);
3718 hitrate = 100 * delta_mcr_cnt_nchoutwin
3719 / delta_raw_mcr_cnt;
3720 if (debug & VP9_DEBUG_CACHE)
3721 pr_info("CACHE_OUTWIN_BYP_RATE : %d\n", hitrate);
3722 }
3723
3724
3725 if (raw_mcr_cnt != 0) {
3726 hitrate = 100 * hit_mcr_cnt / raw_mcr_cnt;
3727 if (debug & VP9_DEBUG_CACHE)
3728 pr_info("MCRCC_HIT_RATE : %d\n", hitrate);
3729 hitrate = 100 * (byp_mcr_cnt_nchoutwin + byp_mcr_cnt_nchcanv)
3730 / raw_mcr_cnt;
3731 if (debug & VP9_DEBUG_CACHE)
3732 pr_info("MCRCC_BYP_RATE : %d\n", hitrate);
3733 } else {
3734 if (debug & VP9_DEBUG_CACHE)
3735 pr_info("MCRCC_HIT_RATE : na\n");
3736 if (debug & VP9_DEBUG_CACHE)
3737 pr_info("MCRCC_BYP_RATE : na\n");
3738 }
3739 return;
3740}
3741
3742
3743static void decomp_perfcount_reset(void)
3744{
3745 if (debug & VP9_DEBUG_CACHE)
3746 pr_info("[cache_util.c] Entered decomp_perfcount_reset...\n");
3747 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x1);
3748 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x0);
3749 return;
3750}
3751
3752static void decomp_get_hitrate(void)
3753{
3754 unsigned raw_mcr_cnt;
3755 unsigned hit_mcr_cnt;
3756 int hitrate;
3757 if (debug & VP9_DEBUG_CACHE)
3758 pr_info("[cache_util.c] Entered decomp_get_hitrate...\n");
3759 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x0<<1));
3760 raw_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3761 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x1<<1));
3762 hit_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3763
3764 if (debug & VP9_DEBUG_CACHE)
3765 pr_info("hcache_raw_cnt_total: %d\n", raw_mcr_cnt);
3766 if (debug & VP9_DEBUG_CACHE)
3767 pr_info("hcache_hit_cnt_total: %d\n", hit_mcr_cnt);
3768
3769 if (raw_mcr_cnt != 0) {
3770 hitrate = hit_mcr_cnt * 100 / raw_mcr_cnt;
3771 if (debug & VP9_DEBUG_CACHE)
3772 pr_info("DECOMP_HCACHE_HIT_RATE : %d\n", hitrate);
3773 } else {
3774 if (debug & VP9_DEBUG_CACHE)
3775 pr_info("DECOMP_HCACHE_HIT_RATE : na\n");
3776 }
3777 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x2<<1));
3778 raw_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3779 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x3<<1));
3780 hit_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3781
3782 if (debug & VP9_DEBUG_CACHE)
3783 pr_info("dcache_raw_cnt_total: %d\n", raw_mcr_cnt);
3784 if (debug & VP9_DEBUG_CACHE)
3785 pr_info("dcache_hit_cnt_total: %d\n", hit_mcr_cnt);
3786
3787 if (raw_mcr_cnt != 0) {
3788 hitrate = hit_mcr_cnt * 100 / raw_mcr_cnt;
3789 if (debug & VP9_DEBUG_CACHE)
3790 pr_info("DECOMP_DCACHE_HIT_RATE : %d\n", hitrate);
3791 } else {
3792 if (debug & VP9_DEBUG_CACHE)
3793 pr_info("DECOMP_DCACHE_HIT_RATE : na\n");
3794 }
3795 return;
3796}
3797
3798static void decomp_get_comprate(void)
3799{
3800 unsigned raw_ucomp_cnt;
3801 unsigned fast_comp_cnt;
3802 unsigned slow_comp_cnt;
3803 int comprate;
3804
3805 if (debug & VP9_DEBUG_CACHE)
3806 pr_info("[cache_util.c] Entered decomp_get_comprate...\n");
3807 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x4<<1));
3808 fast_comp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3809 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x5<<1));
3810 slow_comp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3811 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x6<<1));
3812 raw_ucomp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3813
3814 if (debug & VP9_DEBUG_CACHE)
3815 pr_info("decomp_fast_comp_total: %d\n", fast_comp_cnt);
3816 if (debug & VP9_DEBUG_CACHE)
3817 pr_info("decomp_slow_comp_total: %d\n", slow_comp_cnt);
3818 if (debug & VP9_DEBUG_CACHE)
3819 pr_info("decomp_raw_uncomp_total: %d\n", raw_ucomp_cnt);
3820
3821 if (raw_ucomp_cnt != 0) {
3822 comprate = (fast_comp_cnt + slow_comp_cnt)
3823 * 100 / raw_ucomp_cnt;
3824 if (debug & VP9_DEBUG_CACHE)
3825 pr_info("DECOMP_COMP_RATIO : %d\n", comprate);
3826 } else {
3827 if (debug & VP9_DEBUG_CACHE)
3828 pr_info("DECOMP_COMP_RATIO : na\n");
3829 }
3830 return;
3831}
3832/* cache_util.c end */
3833
3834/*====================================================
3835 *========================================================================
3836 *vp9_prob define
3837 *========================================================================
3838 */
3839#define VP9_PARTITION_START 0
3840#define VP9_PARTITION_SIZE_STEP (3 * 4)
3841#define VP9_PARTITION_ONE_SIZE (4 * VP9_PARTITION_SIZE_STEP)
3842#define VP9_PARTITION_KEY_START 0
3843#define VP9_PARTITION_P_START VP9_PARTITION_ONE_SIZE
3844#define VP9_PARTITION_SIZE (2 * VP9_PARTITION_ONE_SIZE)
3845#define VP9_SKIP_START (VP9_PARTITION_START + VP9_PARTITION_SIZE)
3846#define VP9_SKIP_SIZE 4 /* only use 3*/
3847#define VP9_TX_MODE_START (VP9_SKIP_START+VP9_SKIP_SIZE)
3848#define VP9_TX_MODE_8_0_OFFSET 0
3849#define VP9_TX_MODE_8_1_OFFSET 1
3850#define VP9_TX_MODE_16_0_OFFSET 2
3851#define VP9_TX_MODE_16_1_OFFSET 4
3852#define VP9_TX_MODE_32_0_OFFSET 6
3853#define VP9_TX_MODE_32_1_OFFSET 9
3854#define VP9_TX_MODE_SIZE 12
3855#define VP9_COEF_START (VP9_TX_MODE_START+VP9_TX_MODE_SIZE)
3856#define VP9_COEF_BAND_0_OFFSET 0
3857#define VP9_COEF_BAND_1_OFFSET (VP9_COEF_BAND_0_OFFSET + 3 * 3 + 1)
3858#define VP9_COEF_BAND_2_OFFSET (VP9_COEF_BAND_1_OFFSET + 6 * 3)
3859#define VP9_COEF_BAND_3_OFFSET (VP9_COEF_BAND_2_OFFSET + 6 * 3)
3860#define VP9_COEF_BAND_4_OFFSET (VP9_COEF_BAND_3_OFFSET + 6 * 3)
3861#define VP9_COEF_BAND_5_OFFSET (VP9_COEF_BAND_4_OFFSET + 6 * 3)
3862#define VP9_COEF_SIZE_ONE_SET 100 /* ((3 +5*6)*3 + 1 padding)*/
3863#define VP9_COEF_4X4_START (VP9_COEF_START + 0 * VP9_COEF_SIZE_ONE_SET)
3864#define VP9_COEF_8X8_START (VP9_COEF_START + 4 * VP9_COEF_SIZE_ONE_SET)
3865#define VP9_COEF_16X16_START (VP9_COEF_START + 8 * VP9_COEF_SIZE_ONE_SET)
3866#define VP9_COEF_32X32_START (VP9_COEF_START + 12 * VP9_COEF_SIZE_ONE_SET)
3867#define VP9_COEF_SIZE_PLANE (2 * VP9_COEF_SIZE_ONE_SET)
3868#define VP9_COEF_SIZE (4 * 2 * 2 * VP9_COEF_SIZE_ONE_SET)
3869#define VP9_INTER_MODE_START (VP9_COEF_START+VP9_COEF_SIZE)
3870#define VP9_INTER_MODE_SIZE 24 /* only use 21 ( #*7)*/
3871#define VP9_INTERP_START (VP9_INTER_MODE_START+VP9_INTER_MODE_SIZE)
3872#define VP9_INTERP_SIZE 8
3873#define VP9_INTRA_INTER_START (VP9_INTERP_START+VP9_INTERP_SIZE)
3874#define VP9_INTRA_INTER_SIZE 4
3875#define VP9_INTERP_INTRA_INTER_START VP9_INTERP_START
3876#define VP9_INTERP_INTRA_INTER_SIZE (VP9_INTERP_SIZE + VP9_INTRA_INTER_SIZE)
3877#define VP9_COMP_INTER_START \
3878 (VP9_INTERP_INTRA_INTER_START+VP9_INTERP_INTRA_INTER_SIZE)
3879#define VP9_COMP_INTER_SIZE 5
3880#define VP9_COMP_REF_START (VP9_COMP_INTER_START+VP9_COMP_INTER_SIZE)
3881#define VP9_COMP_REF_SIZE 5
3882#define VP9_SINGLE_REF_START (VP9_COMP_REF_START+VP9_COMP_REF_SIZE)
3883#define VP9_SINGLE_REF_SIZE 10
3884#define VP9_REF_MODE_START VP9_COMP_INTER_START
3885#define VP9_REF_MODE_SIZE \
3886 (VP9_COMP_INTER_SIZE+VP9_COMP_REF_SIZE+VP9_SINGLE_REF_SIZE)
3887#define VP9_IF_Y_MODE_START (VP9_REF_MODE_START+VP9_REF_MODE_SIZE)
3888#define VP9_IF_Y_MODE_SIZE 36
3889#define VP9_IF_UV_MODE_START (VP9_IF_Y_MODE_START+VP9_IF_Y_MODE_SIZE)
3890#define VP9_IF_UV_MODE_SIZE 92 /* only use 90*/
3891#define VP9_MV_JOINTS_START (VP9_IF_UV_MODE_START+VP9_IF_UV_MODE_SIZE)
3892#define VP9_MV_JOINTS_SIZE 3
3893#define VP9_MV_SIGN_0_START (VP9_MV_JOINTS_START+VP9_MV_JOINTS_SIZE)
3894#define VP9_MV_SIGN_0_SIZE 1
3895#define VP9_MV_CLASSES_0_START (VP9_MV_SIGN_0_START+VP9_MV_SIGN_0_SIZE)
3896#define VP9_MV_CLASSES_0_SIZE 10
3897#define VP9_MV_CLASS0_0_START (VP9_MV_CLASSES_0_START+VP9_MV_CLASSES_0_SIZE)
3898#define VP9_MV_CLASS0_0_SIZE 1
3899#define VP9_MV_BITS_0_START (VP9_MV_CLASS0_0_START+VP9_MV_CLASS0_0_SIZE)
3900#define VP9_MV_BITS_0_SIZE 10
3901#define VP9_MV_SIGN_1_START (VP9_MV_BITS_0_START+VP9_MV_BITS_0_SIZE)
3902#define VP9_MV_SIGN_1_SIZE 1
3903#define VP9_MV_CLASSES_1_START \
3904 (VP9_MV_SIGN_1_START+VP9_MV_SIGN_1_SIZE)
3905#define VP9_MV_CLASSES_1_SIZE 10
3906#define VP9_MV_CLASS0_1_START \
3907 (VP9_MV_CLASSES_1_START+VP9_MV_CLASSES_1_SIZE)
3908#define VP9_MV_CLASS0_1_SIZE 1
3909#define VP9_MV_BITS_1_START \
3910 (VP9_MV_CLASS0_1_START+VP9_MV_CLASS0_1_SIZE)
3911#define VP9_MV_BITS_1_SIZE 10
3912#define VP9_MV_CLASS0_FP_0_START \
3913 (VP9_MV_BITS_1_START+VP9_MV_BITS_1_SIZE)
3914#define VP9_MV_CLASS0_FP_0_SIZE 9
3915#define VP9_MV_CLASS0_FP_1_START \
3916 (VP9_MV_CLASS0_FP_0_START+VP9_MV_CLASS0_FP_0_SIZE)
3917#define VP9_MV_CLASS0_FP_1_SIZE 9
3918#define VP9_MV_CLASS0_HP_0_START \
3919 (VP9_MV_CLASS0_FP_1_START+VP9_MV_CLASS0_FP_1_SIZE)
3920#define VP9_MV_CLASS0_HP_0_SIZE 2
3921#define VP9_MV_CLASS0_HP_1_START \
3922 (VP9_MV_CLASS0_HP_0_START+VP9_MV_CLASS0_HP_0_SIZE)
3923#define VP9_MV_CLASS0_HP_1_SIZE 2
3924#define VP9_MV_START VP9_MV_JOINTS_START
3925#define VP9_MV_SIZE 72 /*only use 69*/
3926
3927#define VP9_TOTAL_SIZE (VP9_MV_START + VP9_MV_SIZE)
3928
3929
3930/*========================================================================
3931 * vp9_count_mem define
3932 *========================================================================
3933 */
3934#define VP9_COEF_COUNT_START 0
3935#define VP9_COEF_COUNT_BAND_0_OFFSET 0
3936#define VP9_COEF_COUNT_BAND_1_OFFSET \
3937 (VP9_COEF_COUNT_BAND_0_OFFSET + 3*5)
3938#define VP9_COEF_COUNT_BAND_2_OFFSET \
3939 (VP9_COEF_COUNT_BAND_1_OFFSET + 6*5)
3940#define VP9_COEF_COUNT_BAND_3_OFFSET \
3941 (VP9_COEF_COUNT_BAND_2_OFFSET + 6*5)
3942#define VP9_COEF_COUNT_BAND_4_OFFSET \
3943 (VP9_COEF_COUNT_BAND_3_OFFSET + 6*5)
3944#define VP9_COEF_COUNT_BAND_5_OFFSET \
3945 (VP9_COEF_COUNT_BAND_4_OFFSET + 6*5)
3946#define VP9_COEF_COUNT_SIZE_ONE_SET 165 /* ((3 +5*6)*5 */
3947#define VP9_COEF_COUNT_4X4_START \
3948 (VP9_COEF_COUNT_START + 0*VP9_COEF_COUNT_SIZE_ONE_SET)
3949#define VP9_COEF_COUNT_8X8_START \
3950 (VP9_COEF_COUNT_START + 4*VP9_COEF_COUNT_SIZE_ONE_SET)
3951#define VP9_COEF_COUNT_16X16_START \
3952 (VP9_COEF_COUNT_START + 8*VP9_COEF_COUNT_SIZE_ONE_SET)
3953#define VP9_COEF_COUNT_32X32_START \
3954 (VP9_COEF_COUNT_START + 12*VP9_COEF_COUNT_SIZE_ONE_SET)
3955#define VP9_COEF_COUNT_SIZE_PLANE (2 * VP9_COEF_COUNT_SIZE_ONE_SET)
3956#define VP9_COEF_COUNT_SIZE (4 * 2 * 2 * VP9_COEF_COUNT_SIZE_ONE_SET)
3957
3958#define VP9_INTRA_INTER_COUNT_START \
3959 (VP9_COEF_COUNT_START+VP9_COEF_COUNT_SIZE)
3960#define VP9_INTRA_INTER_COUNT_SIZE (4*2)
3961#define VP9_COMP_INTER_COUNT_START \
3962 (VP9_INTRA_INTER_COUNT_START+VP9_INTRA_INTER_COUNT_SIZE)
3963#define VP9_COMP_INTER_COUNT_SIZE (5*2)
3964#define VP9_COMP_REF_COUNT_START \
3965 (VP9_COMP_INTER_COUNT_START+VP9_COMP_INTER_COUNT_SIZE)
3966#define VP9_COMP_REF_COUNT_SIZE (5*2)
3967#define VP9_SINGLE_REF_COUNT_START \
3968 (VP9_COMP_REF_COUNT_START+VP9_COMP_REF_COUNT_SIZE)
3969#define VP9_SINGLE_REF_COUNT_SIZE (10*2)
3970#define VP9_TX_MODE_COUNT_START \
3971 (VP9_SINGLE_REF_COUNT_START+VP9_SINGLE_REF_COUNT_SIZE)
3972#define VP9_TX_MODE_COUNT_SIZE (12*2)
3973#define VP9_SKIP_COUNT_START \
3974 (VP9_TX_MODE_COUNT_START+VP9_TX_MODE_COUNT_SIZE)
3975#define VP9_SKIP_COUNT_SIZE (3*2)
3976#define VP9_MV_SIGN_0_COUNT_START \
3977 (VP9_SKIP_COUNT_START+VP9_SKIP_COUNT_SIZE)
3978#define VP9_MV_SIGN_0_COUNT_SIZE (1*2)
3979#define VP9_MV_SIGN_1_COUNT_START \
3980 (VP9_MV_SIGN_0_COUNT_START+VP9_MV_SIGN_0_COUNT_SIZE)
3981#define VP9_MV_SIGN_1_COUNT_SIZE (1*2)
3982#define VP9_MV_BITS_0_COUNT_START \
3983 (VP9_MV_SIGN_1_COUNT_START+VP9_MV_SIGN_1_COUNT_SIZE)
3984#define VP9_MV_BITS_0_COUNT_SIZE (10*2)
3985#define VP9_MV_BITS_1_COUNT_START \
3986 (VP9_MV_BITS_0_COUNT_START+VP9_MV_BITS_0_COUNT_SIZE)
3987#define VP9_MV_BITS_1_COUNT_SIZE (10*2)
3988#define VP9_MV_CLASS0_HP_0_COUNT_START \
3989 (VP9_MV_BITS_1_COUNT_START+VP9_MV_BITS_1_COUNT_SIZE)
3990#define VP9_MV_CLASS0_HP_0_COUNT_SIZE (2*2)
3991#define VP9_MV_CLASS0_HP_1_COUNT_START \
3992 (VP9_MV_CLASS0_HP_0_COUNT_START+VP9_MV_CLASS0_HP_0_COUNT_SIZE)
3993#define VP9_MV_CLASS0_HP_1_COUNT_SIZE (2*2)
3994/* Start merge_tree*/
3995#define VP9_INTER_MODE_COUNT_START \
3996 (VP9_MV_CLASS0_HP_1_COUNT_START+VP9_MV_CLASS0_HP_1_COUNT_SIZE)
3997#define VP9_INTER_MODE_COUNT_SIZE (7*4)
3998#define VP9_IF_Y_MODE_COUNT_START \
3999 (VP9_INTER_MODE_COUNT_START+VP9_INTER_MODE_COUNT_SIZE)
4000#define VP9_IF_Y_MODE_COUNT_SIZE (10*4)
4001#define VP9_IF_UV_MODE_COUNT_START \
4002 (VP9_IF_Y_MODE_COUNT_START+VP9_IF_Y_MODE_COUNT_SIZE)
4003#define VP9_IF_UV_MODE_COUNT_SIZE (10*10)
4004#define VP9_PARTITION_P_COUNT_START \
4005 (VP9_IF_UV_MODE_COUNT_START+VP9_IF_UV_MODE_COUNT_SIZE)
4006#define VP9_PARTITION_P_COUNT_SIZE (4*4*4)
4007#define VP9_INTERP_COUNT_START \
4008 (VP9_PARTITION_P_COUNT_START+VP9_PARTITION_P_COUNT_SIZE)
4009#define VP9_INTERP_COUNT_SIZE (4*3)
4010#define VP9_MV_JOINTS_COUNT_START \
4011 (VP9_INTERP_COUNT_START+VP9_INTERP_COUNT_SIZE)
4012#define VP9_MV_JOINTS_COUNT_SIZE (1 * 4)
4013#define VP9_MV_CLASSES_0_COUNT_START \
4014 (VP9_MV_JOINTS_COUNT_START+VP9_MV_JOINTS_COUNT_SIZE)
4015#define VP9_MV_CLASSES_0_COUNT_SIZE (1*11)
4016#define VP9_MV_CLASS0_0_COUNT_START \
4017 (VP9_MV_CLASSES_0_COUNT_START+VP9_MV_CLASSES_0_COUNT_SIZE)
4018#define VP9_MV_CLASS0_0_COUNT_SIZE (1*2)
4019#define VP9_MV_CLASSES_1_COUNT_START \
4020 (VP9_MV_CLASS0_0_COUNT_START+VP9_MV_CLASS0_0_COUNT_SIZE)
4021#define VP9_MV_CLASSES_1_COUNT_SIZE (1*11)
4022#define VP9_MV_CLASS0_1_COUNT_START \
4023 (VP9_MV_CLASSES_1_COUNT_START+VP9_MV_CLASSES_1_COUNT_SIZE)
4024#define VP9_MV_CLASS0_1_COUNT_SIZE (1*2)
4025#define VP9_MV_CLASS0_FP_0_COUNT_START \
4026 (VP9_MV_CLASS0_1_COUNT_START+VP9_MV_CLASS0_1_COUNT_SIZE)
4027#define VP9_MV_CLASS0_FP_0_COUNT_SIZE (3*4)
4028#define VP9_MV_CLASS0_FP_1_COUNT_START \
4029 (VP9_MV_CLASS0_FP_0_COUNT_START+VP9_MV_CLASS0_FP_0_COUNT_SIZE)
4030#define VP9_MV_CLASS0_FP_1_COUNT_SIZE (3*4)
4031
4032
4033#define DC_PRED 0 /* Average of above and left pixels*/
4034#define V_PRED 1 /* Vertical*/
4035#define H_PRED 2 /* Horizontal*/
4036#define D45_PRED 3 /*Directional 45 deg = round(arctan(1/1) * 180/pi)*/
4037#define D135_PRED 4 /* Directional 135 deg = 180 - 45*/
4038#define D117_PRED 5 /* Directional 117 deg = 180 - 63*/
4039#define D153_PRED 6 /* Directional 153 deg = 180 - 27*/
4040#define D207_PRED 7 /* Directional 207 deg = 180 + 27*/
4041#define D63_PRED 8 /*Directional 63 deg = round(arctan(2/1) * 180/pi)*/
4042#define TM_PRED 9 /*True-motion*/
4043
4044int clip_prob(int p)
4045{
4046 return (p > 255) ? 255 : (p < 1) ? 1 : p;
4047}
4048
4049#define ROUND_POWER_OF_TWO(value, n) \
4050 (((value) + (1 << ((n) - 1))) >> (n))
4051
4052#define MODE_MV_COUNT_SAT 20
4053static const int count_to_update_factor[MODE_MV_COUNT_SAT + 1] = {
4054 0, 6, 12, 19, 25, 32, 38, 44, 51, 57, 64,
4055 70, 76, 83, 89, 96, 102, 108, 115, 121, 128
4056};
4057
4058void vp9_tree_merge_probs(unsigned int *prev_prob, unsigned int *cur_prob,
4059 int coef_node_start, int tree_left, int tree_right, int tree_i,
4060 int node) {
4061
4062 int prob_32, prob_res, prob_shift;
4063 int pre_prob, new_prob;
4064 int den, m_count, get_prob, factor;
4065
4066 prob_32 = prev_prob[coef_node_start / 4 * 2];
4067 prob_res = coef_node_start & 3;
4068 prob_shift = prob_res * 8;
4069 pre_prob = (prob_32 >> prob_shift) & 0xff;
4070
4071 den = tree_left + tree_right;
4072
4073 if (den == 0)
4074 new_prob = pre_prob;
4075 else {
4076 m_count = (den < MODE_MV_COUNT_SAT) ?
4077 den : MODE_MV_COUNT_SAT;
4078 get_prob = clip_prob(
4079 div_r32(((int64_t)tree_left * 256 + (den >> 1)),
4080 den));
4081 /*weighted_prob*/
4082 factor = count_to_update_factor[m_count];
4083 new_prob = ROUND_POWER_OF_TWO(pre_prob * (256 - factor)
4084 + get_prob * factor, 8);
4085 }
4086 cur_prob[coef_node_start / 4 * 2] = (cur_prob[coef_node_start / 4 * 2]
4087 & (~(0xff << prob_shift))) | (new_prob << prob_shift);
4088
4089 /*pr_info(" - [%d][%d] 0x%02X --> 0x%02X (0x%X 0x%X) (%X)\n",
4090 *tree_i, node, pre_prob, new_prob, tree_left, tree_right,
4091 *cur_prob[coef_node_start/4*2]);
4092 */
4093}
4094
4095
4096/*void adapt_coef_probs(void)*/
4097void adapt_coef_probs(int pic_count, int prev_kf, int cur_kf, int pre_fc,
4098 unsigned int *prev_prob, unsigned int *cur_prob, unsigned int *count)
4099{
4100 /* 80 * 64bits = 0xF00 ( use 0x1000 4K bytes)
4101 *unsigned int prev_prob[496*2];
4102 *unsigned int cur_prob[496*2];
4103 *0x300 * 128bits = 0x3000 (32K Bytes)
4104 *unsigned int count[0x300*4];
4105 */
4106
4107 int tx_size, coef_tx_size_start, coef_count_tx_size_start;
4108 int plane, coef_plane_start, coef_count_plane_start;
4109 int type, coef_type_start, coef_count_type_start;
4110 int band, coef_band_start, coef_count_band_start;
4111 int cxt_num;
4112 int cxt, coef_cxt_start, coef_count_cxt_start;
4113 int node, coef_node_start, coef_count_node_start;
4114
4115 int tree_i, tree_left, tree_right;
4116 int mvd_i;
4117
4118 int count_sat = 24;
4119 /*int update_factor = 112;*/ /*If COEF_MAX_UPDATE_FACTOR_AFTER_KEY,
4120 *use 128
4121 */
4122 /* If COEF_MAX_UPDATE_FACTOR_AFTER_KEY, use 128*/
4123 /*int update_factor = (pic_count == 1) ? 128 : 112;*/
4124 int update_factor = cur_kf ? 112 :
4125 prev_kf ? 128 : 112;
4126
4127 int prob_32;
4128 int prob_res;
4129 int prob_shift;
4130 int pre_prob;
4131
4132 int num, den;
4133 int get_prob;
4134 int m_count;
4135 int factor;
4136
4137 int new_prob;
4138
4139 if (debug & VP9_DEBUG_MERGE)
4140 pr_info
4141 ("\n ##adapt_coef_probs (pre_fc : %d ,prev_kf : %d,cur_kf : %d)##\n\n",
4142 pre_fc, prev_kf, cur_kf);
4143
4144 /*adapt_coef_probs*/
4145 for (tx_size = 0; tx_size < 4; tx_size++) {
4146 coef_tx_size_start = VP9_COEF_START
4147 + tx_size * 4 * VP9_COEF_SIZE_ONE_SET;
4148 coef_count_tx_size_start = VP9_COEF_COUNT_START
4149 + tx_size * 4 * VP9_COEF_COUNT_SIZE_ONE_SET;
4150 coef_plane_start = coef_tx_size_start;
4151 coef_count_plane_start = coef_count_tx_size_start;
4152 for (plane = 0; plane < 2; plane++) {
4153 coef_type_start = coef_plane_start;
4154 coef_count_type_start = coef_count_plane_start;
4155 for (type = 0; type < 2; type++) {
4156 coef_band_start = coef_type_start;
4157 coef_count_band_start = coef_count_type_start;
4158 for (band = 0; band < 6; band++) {
4159 if (band == 0)
4160 cxt_num = 3;
4161 else
4162 cxt_num = 6;
4163 coef_cxt_start = coef_band_start;
4164 coef_count_cxt_start =
4165 coef_count_band_start;
4166 for (cxt = 0; cxt < cxt_num; cxt++) {
4167 const int n0 =
4168 count[coef_count_cxt_start];
4169 const int n1 =
4170 count[coef_count_cxt_start + 1];
4171 const int n2 =
4172 count[coef_count_cxt_start + 2];
4173 const int neob =
4174 count[coef_count_cxt_start + 3];
4175 const int nneob =
4176 count[coef_count_cxt_start + 4];
4177 const unsigned int
4178 branch_ct[3][2] = {
4179 { neob, nneob },
4180 { n0, n1 + n2 },
4181 { n1, n2 }
4182 };
4183 coef_node_start =
4184 coef_cxt_start;
4185 for
4186 (node = 0; node < 3; node++) {
4187 prob_32 =
4188 prev_prob[
4189 coef_node_start
4190 / 4 * 2];
4191 prob_res =
4192 coef_node_start & 3;
4193 prob_shift =
4194 prob_res * 8;
4195 pre_prob =
4196 (prob_32 >> prob_shift)
4197 & 0xff;
4198
4199 /*get_binary_prob*/
4200 num =
4201 branch_ct[node][0];
4202 den =
4203 branch_ct[node][0] +
4204 branch_ct[node][1];
4205 m_count = (den <
4206 count_sat)
4207 ? den : count_sat;
4208
4209 get_prob =
4210 (den == 0) ? 128u :
4211 clip_prob(
4212 div_r32(((int64_t)
4213 num * 256
4214 + (den >> 1)),
4215 den));
4216
4217 factor =
4218 update_factor * m_count
4219 / count_sat;
4220 new_prob =
4221 ROUND_POWER_OF_TWO
4222 (pre_prob *
4223 (256 - factor) +
4224 get_prob * factor, 8);
4225
4226 cur_prob[coef_node_start
4227 / 4 * 2] =
4228 (cur_prob
4229 [coef_node_start
4230 / 4 * 2] & (~(0xff <<
4231 prob_shift))) |
4232 (new_prob <<
4233 prob_shift);
4234
4235 coef_node_start += 1;
4236 }
4237
4238 coef_cxt_start =
4239 coef_cxt_start + 3;
4240 coef_count_cxt_start =
4241 coef_count_cxt_start
4242 + 5;
4243 }
4244 if (band == 0) {
4245 coef_band_start += 10;
4246 coef_count_band_start += 15;
4247 } else {
4248 coef_band_start += 18;
4249 coef_count_band_start += 30;
4250 }
4251 }
4252 coef_type_start += VP9_COEF_SIZE_ONE_SET;
4253 coef_count_type_start +=
4254 VP9_COEF_COUNT_SIZE_ONE_SET;
4255 }
4256 coef_plane_start += 2 * VP9_COEF_SIZE_ONE_SET;
4257 coef_count_plane_start +=
4258 2 * VP9_COEF_COUNT_SIZE_ONE_SET;
4259 }
4260 }
4261
4262 if (cur_kf == 0) {
4263 /*mode_mv_merge_probs - merge_intra_inter_prob*/
4264 for (coef_count_node_start = VP9_INTRA_INTER_COUNT_START;
4265 coef_count_node_start < (VP9_MV_CLASS0_HP_1_COUNT_START +
4266 VP9_MV_CLASS0_HP_1_COUNT_SIZE); coef_count_node_start += 2) {
4267
4268 if (coef_count_node_start ==
4269 VP9_INTRA_INTER_COUNT_START) {
4270 if (debug & VP9_DEBUG_MERGE)
4271 pr_info(" # merge_intra_inter_prob\n");
4272 coef_node_start = VP9_INTRA_INTER_START;
4273 } else if (coef_count_node_start ==
4274 VP9_COMP_INTER_COUNT_START) {
4275 if (debug & VP9_DEBUG_MERGE)
4276 pr_info(" # merge_comp_inter_prob\n");
4277 coef_node_start = VP9_COMP_INTER_START;
4278 }
4279 /*
4280 *else if (coef_count_node_start ==
4281 * VP9_COMP_REF_COUNT_START) {
4282 * pr_info(" # merge_comp_inter_prob\n");
4283 * coef_node_start = VP9_COMP_REF_START;
4284 *}
4285 *else if (coef_count_node_start ==
4286 * VP9_SINGLE_REF_COUNT_START) {
4287 * pr_info(" # merge_comp_inter_prob\n");
4288 * coef_node_start = VP9_SINGLE_REF_START;
4289 *}
4290 */
4291 else if (coef_count_node_start ==
4292 VP9_TX_MODE_COUNT_START) {
4293 if (debug & VP9_DEBUG_MERGE)
4294 pr_info(" # merge_tx_mode_probs\n");
4295 coef_node_start = VP9_TX_MODE_START;
4296 } else if (coef_count_node_start ==
4297 VP9_SKIP_COUNT_START) {
4298 if (debug & VP9_DEBUG_MERGE)
4299 pr_info(" # merge_skip_probs\n");
4300 coef_node_start = VP9_SKIP_START;
4301 } else if (coef_count_node_start ==
4302 VP9_MV_SIGN_0_COUNT_START) {
4303 if (debug & VP9_DEBUG_MERGE)
4304 pr_info(" # merge_sign_0\n");
4305 coef_node_start = VP9_MV_SIGN_0_START;
4306 } else if (coef_count_node_start ==
4307 VP9_MV_SIGN_1_COUNT_START) {
4308 if (debug & VP9_DEBUG_MERGE)
4309 pr_info(" # merge_sign_1\n");
4310 coef_node_start = VP9_MV_SIGN_1_START;
4311 } else if (coef_count_node_start ==
4312 VP9_MV_BITS_0_COUNT_START) {
4313 if (debug & VP9_DEBUG_MERGE)
4314 pr_info(" # merge_bits_0\n");
4315 coef_node_start = VP9_MV_BITS_0_START;
4316 } else if (coef_count_node_start ==
4317 VP9_MV_BITS_1_COUNT_START) {
4318 if (debug & VP9_DEBUG_MERGE)
4319 pr_info(" # merge_bits_1\n");
4320 coef_node_start = VP9_MV_BITS_1_START;
4321 } else if (coef_count_node_start ==
4322 VP9_MV_CLASS0_HP_0_COUNT_START) {
4323 if (debug & VP9_DEBUG_MERGE)
4324 pr_info(" # merge_class0_hp\n");
4325 coef_node_start = VP9_MV_CLASS0_HP_0_START;
4326 }
4327
4328
4329 den = count[coef_count_node_start] +
4330 count[coef_count_node_start + 1];
4331
4332 prob_32 = prev_prob[coef_node_start / 4 * 2];
4333 prob_res = coef_node_start & 3;
4334 prob_shift = prob_res * 8;
4335 pre_prob = (prob_32 >> prob_shift) & 0xff;
4336
4337 if (den == 0)
4338 new_prob = pre_prob;
4339 else {
4340 m_count = (den < MODE_MV_COUNT_SAT) ?
4341 den : MODE_MV_COUNT_SAT;
4342 get_prob =
4343 clip_prob(
4344 div_r32(((int64_t)count[coef_count_node_start]
4345 * 256 + (den >> 1)),
4346 den));
4347 /*weighted_prob*/
4348 factor = count_to_update_factor[m_count];
4349 new_prob =
4350 ROUND_POWER_OF_TWO(pre_prob * (256 - factor)
4351 + get_prob * factor, 8);
4352 }
4353 cur_prob[coef_node_start / 4 * 2] =
4354 (cur_prob[coef_node_start / 4 * 2] &
4355 (~(0xff << prob_shift)))
4356 | (new_prob << prob_shift);
4357
4358 coef_node_start = coef_node_start + 1;
4359 }
4360 if (debug & VP9_DEBUG_MERGE)
4361 pr_info(" # merge_vp9_inter_mode_tree\n");
4362 coef_node_start = VP9_INTER_MODE_START;
4363 coef_count_node_start = VP9_INTER_MODE_COUNT_START;
4364 for (tree_i = 0; tree_i < 7; tree_i++) {
4365 for (node = 0; node < 3; node++) {
4366 switch (node) {
4367 case 2:
4368 tree_left =
4369 count[coef_count_node_start + 1];
4370 tree_right =
4371 count[coef_count_node_start + 3];
4372 break;
4373 case 1:
4374 tree_left =
4375 count[coef_count_node_start + 0];
4376 tree_right =
4377 count[coef_count_node_start + 1]
4378 + count[coef_count_node_start + 3];
4379 break;
4380 default:
4381 tree_left =
4382 count[coef_count_node_start + 2];
4383 tree_right =
4384 count[coef_count_node_start + 0]
4385 + count[coef_count_node_start + 1]
4386 + count[coef_count_node_start + 3];
4387 break;
4388
4389 }
4390
4391 vp9_tree_merge_probs(prev_prob, cur_prob,
4392 coef_node_start, tree_left, tree_right,
4393 tree_i, node);
4394
4395 coef_node_start = coef_node_start + 1;
4396 }
4397 coef_count_node_start = coef_count_node_start + 4;
4398 }
4399 if (debug & VP9_DEBUG_MERGE)
4400 pr_info(" # merge_vp9_intra_mode_tree\n");
4401 coef_node_start = VP9_IF_Y_MODE_START;
4402 coef_count_node_start = VP9_IF_Y_MODE_COUNT_START;
4403 for (tree_i = 0; tree_i < 14; tree_i++) {
4404 for (node = 0; node < 9; node++) {
4405 switch (node) {
4406 case 8:
4407 tree_left =
4408 count[coef_count_node_start+D153_PRED];
4409 tree_right =
4410 count[coef_count_node_start+D207_PRED];
4411 break;
4412 case 7:
4413 tree_left =
4414 count[coef_count_node_start+D63_PRED];
4415 tree_right =
4416 count[coef_count_node_start+D207_PRED] +
4417 count[coef_count_node_start+D153_PRED];
4418 break;
4419 case 6:
4420 tree_left =
4421 count[coef_count_node_start + D45_PRED];
4422 tree_right =
4423 count[coef_count_node_start+D207_PRED] +
4424 count[coef_count_node_start+D153_PRED] +
4425 count[coef_count_node_start+D63_PRED];
4426 break;
4427 case 5:
4428 tree_left =
4429 count[coef_count_node_start+D135_PRED];
4430 tree_right =
4431 count[coef_count_node_start+D117_PRED];
4432 break;
4433 case 4:
4434 tree_left =
4435 count[coef_count_node_start+H_PRED];
4436 tree_right =
4437 count[coef_count_node_start+D117_PRED] +
4438 count[coef_count_node_start+D135_PRED];
4439 break;
4440 case 3:
4441 tree_left =
4442 count[coef_count_node_start+H_PRED] +
4443 count[coef_count_node_start+D117_PRED] +
4444 count[coef_count_node_start+D135_PRED];
4445 tree_right =
4446 count[coef_count_node_start+D45_PRED] +
4447 count[coef_count_node_start+D207_PRED] +
4448 count[coef_count_node_start+D153_PRED] +
4449 count[coef_count_node_start+D63_PRED];
4450 break;
4451 case 2:
4452 tree_left =
4453 count[coef_count_node_start+V_PRED];
4454 tree_right =
4455 count[coef_count_node_start+H_PRED] +
4456 count[coef_count_node_start+D117_PRED] +
4457 count[coef_count_node_start+D135_PRED] +
4458 count[coef_count_node_start+D45_PRED] +
4459 count[coef_count_node_start+D207_PRED] +
4460 count[coef_count_node_start+D153_PRED] +
4461 count[coef_count_node_start+D63_PRED];
4462 break;
4463 case 1:
4464 tree_left =
4465 count[coef_count_node_start+TM_PRED];
4466 tree_right =
4467 count[coef_count_node_start+V_PRED] +
4468 count[coef_count_node_start+H_PRED] +
4469 count[coef_count_node_start+D117_PRED] +
4470 count[coef_count_node_start+D135_PRED] +
4471 count[coef_count_node_start+D45_PRED] +
4472 count[coef_count_node_start+D207_PRED] +
4473 count[coef_count_node_start+D153_PRED] +
4474 count[coef_count_node_start+D63_PRED];
4475 break;
4476 default:
4477 tree_left =
4478 count[coef_count_node_start+DC_PRED];
4479 tree_right =
4480 count[coef_count_node_start+TM_PRED] +
4481 count[coef_count_node_start+V_PRED] +
4482 count[coef_count_node_start+H_PRED] +
4483 count[coef_count_node_start+D117_PRED] +
4484 count[coef_count_node_start+D135_PRED] +
4485 count[coef_count_node_start+D45_PRED] +
4486 count[coef_count_node_start+D207_PRED] +
4487 count[coef_count_node_start+D153_PRED] +
4488 count[coef_count_node_start+D63_PRED];
4489 break;
4490
4491 }
4492
4493 vp9_tree_merge_probs(prev_prob, cur_prob,
4494 coef_node_start, tree_left, tree_right,
4495 tree_i, node);
4496
4497 coef_node_start = coef_node_start + 1;
4498 }
4499 coef_count_node_start = coef_count_node_start + 10;
4500 }
4501
4502 if (debug & VP9_DEBUG_MERGE)
4503 pr_info(" # merge_vp9_partition_tree\n");
4504 coef_node_start = VP9_PARTITION_P_START;
4505 coef_count_node_start = VP9_PARTITION_P_COUNT_START;
4506 for (tree_i = 0; tree_i < 16; tree_i++) {
4507 for (node = 0; node < 3; node++) {
4508 switch (node) {
4509 case 2:
4510 tree_left =
4511 count[coef_count_node_start + 2];
4512 tree_right =
4513 count[coef_count_node_start + 3];
4514 break;
4515 case 1:
4516 tree_left =
4517 count[coef_count_node_start + 1];
4518 tree_right =
4519 count[coef_count_node_start + 2] +
4520 count[coef_count_node_start + 3];
4521 break;
4522 default:
4523 tree_left =
4524 count[coef_count_node_start + 0];
4525 tree_right =
4526 count[coef_count_node_start + 1] +
4527 count[coef_count_node_start + 2] +
4528 count[coef_count_node_start + 3];
4529 break;
4530
4531 }
4532
4533 vp9_tree_merge_probs(prev_prob, cur_prob,
4534 coef_node_start,
4535 tree_left, tree_right, tree_i, node);
4536
4537 coef_node_start = coef_node_start + 1;
4538 }
4539 coef_count_node_start = coef_count_node_start + 4;
4540 }
4541
4542 if (debug & VP9_DEBUG_MERGE)
4543 pr_info(" # merge_vp9_switchable_interp_tree\n");
4544 coef_node_start = VP9_INTERP_START;
4545 coef_count_node_start = VP9_INTERP_COUNT_START;
4546 for (tree_i = 0; tree_i < 4; tree_i++) {
4547 for (node = 0; node < 2; node++) {
4548 switch (node) {
4549 case 1:
4550 tree_left =
4551 count[coef_count_node_start + 1];
4552 tree_right =
4553 count[coef_count_node_start + 2];
4554 break;
4555 default:
4556 tree_left =
4557 count[coef_count_node_start + 0];
4558 tree_right =
4559 count[coef_count_node_start + 1] +
4560 count[coef_count_node_start + 2];
4561 break;
4562
4563 }
4564
4565 vp9_tree_merge_probs(prev_prob, cur_prob,
4566 coef_node_start,
4567 tree_left, tree_right, tree_i, node);
4568
4569 coef_node_start = coef_node_start + 1;
4570 }
4571 coef_count_node_start = coef_count_node_start + 3;
4572 }
4573
4574 if (debug & VP9_DEBUG_MERGE)
4575 pr_info("# merge_vp9_mv_joint_tree\n");
4576 coef_node_start = VP9_MV_JOINTS_START;
4577 coef_count_node_start = VP9_MV_JOINTS_COUNT_START;
4578 for (tree_i = 0; tree_i < 1; tree_i++) {
4579 for (node = 0; node < 3; node++) {
4580 switch (node) {
4581 case 2:
4582 tree_left =
4583 count[coef_count_node_start + 2];
4584 tree_right =
4585 count[coef_count_node_start + 3];
4586 break;
4587 case 1:
4588 tree_left =
4589 count[coef_count_node_start + 1];
4590 tree_right =
4591 count[coef_count_node_start + 2] +
4592 count[coef_count_node_start + 3];
4593 break;
4594 default:
4595 tree_left =
4596 count[coef_count_node_start + 0];
4597 tree_right =
4598 count[coef_count_node_start + 1] +
4599 count[coef_count_node_start + 2] +
4600 count[coef_count_node_start + 3];
4601 break;
4602 }
4603
4604 vp9_tree_merge_probs(prev_prob, cur_prob,
4605 coef_node_start,
4606 tree_left, tree_right, tree_i, node);
4607
4608 coef_node_start = coef_node_start + 1;
4609 }
4610 coef_count_node_start = coef_count_node_start + 4;
4611 }
4612
4613 for (mvd_i = 0; mvd_i < 2; mvd_i++) {
4614 if (debug & VP9_DEBUG_MERGE)
4615 pr_info(" # merge_vp9_mv_class_tree [%d] -\n", mvd_i);
4616 coef_node_start =
4617 mvd_i ? VP9_MV_CLASSES_1_START : VP9_MV_CLASSES_0_START;
4618 coef_count_node_start =
4619 mvd_i ? VP9_MV_CLASSES_1_COUNT_START
4620 : VP9_MV_CLASSES_0_COUNT_START;
4621 tree_i = 0;
4622 for (node = 0; node < 10; node++) {
4623 switch (node) {
4624 case 9:
4625 tree_left =
4626 count[coef_count_node_start + 9];
4627 tree_right =
4628 count[coef_count_node_start + 10];
4629 break;
4630 case 8:
4631 tree_left =
4632 count[coef_count_node_start + 7];
4633 tree_right =
4634 count[coef_count_node_start + 8];
4635 break;
4636 case 7:
4637 tree_left =
4638 count[coef_count_node_start + 7] +
4639 count[coef_count_node_start + 8];
4640 tree_right =
4641 count[coef_count_node_start + 9] +
4642 count[coef_count_node_start + 10];
4643 break;
4644 case 6:
4645 tree_left =
4646 count[coef_count_node_start + 6];
4647 tree_right =
4648 count[coef_count_node_start + 7] +
4649 count[coef_count_node_start + 8] +
4650 count[coef_count_node_start + 9] +
4651 count[coef_count_node_start + 10];
4652 break;
4653 case 5:
4654 tree_left =
4655 count[coef_count_node_start + 4];
4656 tree_right =
4657 count[coef_count_node_start + 5];
4658 break;
4659 case 4:
4660 tree_left =
4661 count[coef_count_node_start + 4] +
4662 count[coef_count_node_start + 5];
4663 tree_right =
4664 count[coef_count_node_start + 6] +
4665 count[coef_count_node_start + 7] +
4666 count[coef_count_node_start + 8] +
4667 count[coef_count_node_start + 9] +
4668 count[coef_count_node_start + 10];
4669 break;
4670 case 3:
4671 tree_left =
4672 count[coef_count_node_start + 2];
4673 tree_right =
4674 count[coef_count_node_start + 3];
4675 break;
4676 case 2:
4677 tree_left =
4678 count[coef_count_node_start + 2] +
4679 count[coef_count_node_start + 3];
4680 tree_right =
4681 count[coef_count_node_start + 4] +
4682 count[coef_count_node_start + 5] +
4683 count[coef_count_node_start + 6] +
4684 count[coef_count_node_start + 7] +
4685 count[coef_count_node_start + 8] +
4686 count[coef_count_node_start + 9] +
4687 count[coef_count_node_start + 10];
4688 break;
4689 case 1:
4690 tree_left =
4691 count[coef_count_node_start + 1];
4692 tree_right =
4693 count[coef_count_node_start + 2] +
4694 count[coef_count_node_start + 3] +
4695 count[coef_count_node_start + 4] +
4696 count[coef_count_node_start + 5] +
4697 count[coef_count_node_start + 6] +
4698 count[coef_count_node_start + 7] +
4699 count[coef_count_node_start + 8] +
4700 count[coef_count_node_start + 9] +
4701 count[coef_count_node_start + 10];
4702 break;
4703 default:
4704 tree_left =
4705 count[coef_count_node_start + 0];
4706 tree_right =
4707 count[coef_count_node_start + 1] +
4708 count[coef_count_node_start + 2] +
4709 count[coef_count_node_start + 3] +
4710 count[coef_count_node_start + 4] +
4711 count[coef_count_node_start + 5] +
4712 count[coef_count_node_start + 6] +
4713 count[coef_count_node_start + 7] +
4714 count[coef_count_node_start + 8] +
4715 count[coef_count_node_start + 9] +
4716 count[coef_count_node_start + 10];
4717 break;
4718
4719 }
4720
4721 vp9_tree_merge_probs(prev_prob, cur_prob,
4722 coef_node_start, tree_left, tree_right,
4723 tree_i, node);
4724
4725 coef_node_start = coef_node_start + 1;
4726 }
4727
4728 if (debug & VP9_DEBUG_MERGE)
4729 pr_info(" # merge_vp9_mv_class0_tree [%d] -\n", mvd_i);
4730 coef_node_start =
4731 mvd_i ? VP9_MV_CLASS0_1_START : VP9_MV_CLASS0_0_START;
4732 coef_count_node_start =
4733 mvd_i ? VP9_MV_CLASS0_1_COUNT_START :
4734 VP9_MV_CLASS0_0_COUNT_START;
4735 tree_i = 0;
4736 node = 0;
4737 tree_left = count[coef_count_node_start + 0];
4738 tree_right = count[coef_count_node_start + 1];
4739
4740 vp9_tree_merge_probs(prev_prob, cur_prob, coef_node_start,
4741 tree_left, tree_right, tree_i, node);
4742 if (debug & VP9_DEBUG_MERGE)
4743 pr_info(" # merge_vp9_mv_fp_tree_class0_fp [%d] -\n",
4744 mvd_i);
4745 coef_node_start =
4746 mvd_i ? VP9_MV_CLASS0_FP_1_START :
4747 VP9_MV_CLASS0_FP_0_START;
4748 coef_count_node_start =
4749 mvd_i ? VP9_MV_CLASS0_FP_1_COUNT_START :
4750 VP9_MV_CLASS0_FP_0_COUNT_START;
4751 for (tree_i = 0; tree_i < 3; tree_i++) {
4752 for (node = 0; node < 3; node++) {
4753 switch (node) {
4754 case 2:
4755 tree_left =
4756 count[coef_count_node_start + 2];
4757 tree_right =
4758 count[coef_count_node_start + 3];
4759 break;
4760 case 1:
4761 tree_left =
4762 count[coef_count_node_start + 1];
4763 tree_right =
4764 count[coef_count_node_start + 2]
4765 + count[coef_count_node_start + 3];
4766 break;
4767 default:
4768 tree_left =
4769 count[coef_count_node_start + 0];
4770 tree_right =
4771 count[coef_count_node_start + 1]
4772 + count[coef_count_node_start + 2]
4773 + count[coef_count_node_start + 3];
4774 break;
4775
4776 }
4777
4778 vp9_tree_merge_probs(prev_prob, cur_prob,
4779 coef_node_start, tree_left, tree_right,
4780 tree_i, node);
4781
4782 coef_node_start = coef_node_start + 1;
4783 }
4784 coef_count_node_start = coef_count_node_start + 4;
4785 }
4786
4787 } /* for mvd_i (mvd_y or mvd_x)*/
4788}
4789
4790}
4791
4792static bool v4l_is_there_vframe_bound(struct VP9Decoder_s *pbi)
4793{
4794 int i;
4795 struct VP9_Common_s *const cm = &pbi->common;
4796 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
4797
4798 for (i = 0; i < pbi->used_buf_num; ++i) {
4799 if (frame_bufs[i].buf.vframe_bound)
4800 return true;
4801 }
4802
4803 return false;
4804}
4805
4806static void v4l_mmu_buffer_release(struct VP9Decoder_s *pbi)
4807{
4808 struct VP9_Common_s *const cm = &pbi->common;
4809 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
4810 int i;
4811
4812 /* release workspace */
4813 if (pbi->bmmu_box)
4814 decoder_bmmu_box_free_idx(pbi->bmmu_box,
4815 WORK_SPACE_BUF_ID);
4816 /*
4817 * it's only when vframe get back to driver, right now we can be sure
4818 * that vframe and fd are related. if the playback exits, the capture
4819 * requires the upper app to release when the fd is closed, and others
4820 * buffers drivers are released by driver.
4821 */
4822 for (i = 0; i < pbi->used_buf_num; ++i) {
4823 if (!frame_bufs[i].buf.vframe_bound) {
4824 if (pbi->bmmu_box)
4825 decoder_bmmu_box_free_idx(pbi->bmmu_box,
4826 HEADER_BUFFER_IDX(i));
4827 if (pbi->mmu_box)
4828 decoder_mmu_box_free_idx(pbi->mmu_box, i);
4829
4830 vp9_print(pbi, PRINT_FLAG_V4L_DETAIL,
4831 "%s free buffer[%d], bmmu_box: %p, mmu_box: %p\n",
4832 __func__, i, pbi->bmmu_box, pbi->mmu_box);
4833 }
4834 }
4835}
4836
4837static void uninit_mmu_buffers(struct VP9Decoder_s *pbi)
4838{
4839#ifndef MV_USE_FIXED_BUF
4840 dealloc_mv_bufs(pbi);
4841#endif
4842 if (pbi->is_used_v4l &&
4843 v4l_is_there_vframe_bound(pbi)) {
4844 if (get_double_write_mode(pbi) != 0x10) {
4845 v4l_mmu_buffer_release(pbi);
4846 return;
4847 }
4848 }
4849
4850 if (pbi->mmu_box)
4851 decoder_mmu_box_free(pbi->mmu_box);
4852 pbi->mmu_box = NULL;
4853
4854 if (pbi->bmmu_box)
4855 decoder_bmmu_box_free(pbi->bmmu_box);
4856 pbi->bmmu_box = NULL;
4857}
4858
4859static int calc_luc_quantity(u32 w, u32 h)
4860{
4861 int lcu_size = 64; /*fixed 64*/
4862 int pic_width_64 = (w + 63) & (~0x3f);
4863 int pic_height_32 = (h + 31) & (~0x1f);
4864 int pic_width_lcu = (pic_width_64 % lcu_size) ?
4865 pic_width_64 / lcu_size + 1 : pic_width_64 / lcu_size;
4866 int pic_height_lcu = (pic_height_32 % lcu_size) ?
4867 pic_height_32 / lcu_size + 1 : pic_height_32 / lcu_size;
4868
4869 return pic_width_lcu * pic_height_lcu;
4870}
4871
4872static int v4l_alloc_and_config_pic(struct VP9Decoder_s *pbi,
4873 struct PIC_BUFFER_CONFIG_s *pic)
4874{
4875 int ret = -1;
4876 int i = pic->index;
4877 int dw_mode = get_double_write_mode_init(pbi);
4878 int lcu_total = calc_luc_quantity(pbi->frame_width, pbi->frame_height);
4879#ifdef MV_USE_FIXED_BUF
4880 u32 mpred_mv_end = pbi->work_space_buf->mpred_mv.buf_start +
4881 pbi->work_space_buf->mpred_mv.buf_size;
4882#endif
4883 struct vdec_v4l2_buffer *fb = NULL;
4884
4885 if (i < 0)
4886 return ret;
4887
4888 ret = vdec_v4l_get_buffer(pbi->v4l2_ctx, &fb);
4889 if (ret < 0) {
4890 vp9_print(pbi, 0, "[%d] VP9 get buffer fail.\n",
4891 ((struct aml_vcodec_ctx *) (pbi->v4l2_ctx))->id);
4892 return ret;
4893 }
4894
4895 if (pbi->mmu_enable) {
4896 pbi->m_BUF[i].header_addr = decoder_bmmu_box_get_phy_addr(
4897 pbi->bmmu_box, HEADER_BUFFER_IDX(i));
4898 if (debug & VP9_DEBUG_BUFMGR_MORE) {
4899 pr_info("MMU header_adr %d: %ld\n",
4900 i, pbi->m_BUF[i].header_addr);
4901 }
4902 }
4903
4904#ifdef MV_USE_FIXED_BUF
4905 if ((pbi->work_space_buf->mpred_mv.buf_start +
4906 (((i + 1) * lcu_total) * MV_MEM_UNIT))
4907 <= mpred_mv_end) {
4908#endif
4909 pbi->m_BUF[i].v4l_ref_buf_addr = (ulong)fb;
4910 pic->cma_alloc_addr = fb->m.mem[0].addr;
4911 if (fb->num_planes == 1) {
4912 pbi->m_BUF[i].start_adr = fb->m.mem[0].addr;
4913 pbi->m_BUF[i].luma_size = fb->m.mem[0].offset;
4914 pbi->m_BUF[i].size = fb->m.mem[0].size;
4915 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
4916 pic->dw_y_adr = pbi->m_BUF[i].start_adr;
4917 pic->dw_u_v_adr = pic->dw_y_adr + pbi->m_BUF[i].luma_size;
4918 } else if (fb->num_planes == 2) {
4919 pbi->m_BUF[i].start_adr = fb->m.mem[0].addr;
4920 pbi->m_BUF[i].size = fb->m.mem[0].size;
4921 pbi->m_BUF[i].chroma_addr = fb->m.mem[1].addr;
4922 pbi->m_BUF[i].chroma_size = fb->m.mem[1].size;
4923 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
4924 fb->m.mem[1].bytes_used = fb->m.mem[1].size;
4925 pic->dw_y_adr = pbi->m_BUF[i].start_adr;
4926 pic->dw_u_v_adr = pbi->m_BUF[i].chroma_addr;
4927 }
4928
4929 /* config frame buffer */
4930 if (pbi->mmu_enable)
4931 pic->header_adr = pbi->m_BUF[i].header_addr;
4932
4933 pic->BUF_index = i;
4934 pic->lcu_total = lcu_total;
4935 pic->mc_canvas_y = pic->index;
4936 pic->mc_canvas_u_v = pic->index;
4937
4938 if (dw_mode & 0x10) {
4939 pic->mc_canvas_y = (pic->index << 1);
4940 pic->mc_canvas_u_v = (pic->index << 1) + 1;
4941 }
4942
4943#ifdef MV_USE_FIXED_BUF
4944 pic->mpred_mv_wr_start_addr =
4945 pbi->work_space_buf->mpred_mv.buf_start +
4946 ((pic->index * lcu_total) * MV_MEM_UNIT);
4947#endif
4948 if (debug) {
4949 pr_info("%s index %d BUF_index %d ",
4950 __func__, pic->index,
4951 pic->BUF_index);
4952 pr_info("comp_body_size %x comp_buf_size %x ",
4953 pic->comp_body_size,
4954 pic->buf_size);
4955 pr_info("mpred_mv_wr_start_adr %ld\n",
4956 pic->mpred_mv_wr_start_addr);
4957 pr_info("dw_y_adr %d, pic_config->dw_u_v_adr =%d\n",
4958 pic->dw_y_adr,
4959 pic->dw_u_v_adr);
4960 }
4961#ifdef MV_USE_FIXED_BUF
4962 }
4963#endif
4964 return ret;
4965}
4966
4967static int config_pic(struct VP9Decoder_s *pbi,
4968 struct PIC_BUFFER_CONFIG_s *pic_config)
4969{
4970 int ret = -1;
4971 int i;
4972 int pic_width = pbi->init_pic_w;
4973 int pic_height = pbi->init_pic_h;
4974 int lcu_size = 64; /*fixed 64*/
4975 int pic_width_64 = (pic_width + 63) & (~0x3f);
4976 int pic_height_32 = (pic_height + 31) & (~0x1f);
4977 int pic_width_lcu = (pic_width_64 % lcu_size) ?
4978 pic_width_64 / lcu_size + 1
4979 : pic_width_64 / lcu_size;
4980 int pic_height_lcu = (pic_height_32 % lcu_size) ?
4981 pic_height_32 / lcu_size + 1
4982 : pic_height_32 / lcu_size;
4983 int lcu_total = pic_width_lcu * pic_height_lcu;
4984#ifdef MV_USE_FIXED_BUF
4985 u32 mpred_mv_end = pbi->work_space_buf->mpred_mv.buf_start +
4986 pbi->work_space_buf->mpred_mv.buf_size;
4987#endif
4988 u32 y_adr = 0;
4989 int buf_size = 0;
4990
4991 int losless_comp_header_size =
4992 compute_losless_comp_header_size(pic_width,
4993 pic_height);
4994 int losless_comp_body_size = compute_losless_comp_body_size(pic_width,
4995 pic_height, buf_alloc_depth == 10);
4996 int mc_buffer_size = losless_comp_header_size + losless_comp_body_size;
4997 int mc_buffer_size_h = (mc_buffer_size + 0xffff) >> 16;
4998 int mc_buffer_size_u_v = 0;
4999 int mc_buffer_size_u_v_h = 0;
5000 int dw_mode = get_double_write_mode_init(pbi);
5001
5002 pbi->lcu_total = lcu_total;
5003
5004 if (dw_mode) {
5005 int pic_width_dw = pic_width /
5006 get_double_write_ratio(pbi, dw_mode);
5007 int pic_height_dw = pic_height /
5008 get_double_write_ratio(pbi, dw_mode);
5009
5010 int pic_width_64_dw = (pic_width_dw + 63) & (~0x3f);
5011 int pic_height_32_dw = (pic_height_dw + 31) & (~0x1f);
5012 int pic_width_lcu_dw = (pic_width_64_dw % lcu_size) ?
5013 pic_width_64_dw / lcu_size + 1
5014 : pic_width_64_dw / lcu_size;
5015 int pic_height_lcu_dw = (pic_height_32_dw % lcu_size) ?
5016 pic_height_32_dw / lcu_size + 1
5017 : pic_height_32_dw / lcu_size;
5018 int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw;
5019 mc_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2;
5020 mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff) >> 16;
5021 /*64k alignment*/
5022 buf_size = ((mc_buffer_size_u_v_h << 16) * 3);
5023 buf_size = ((buf_size + 0xffff) >> 16) << 16;
5024 }
5025
5026 if (mc_buffer_size & 0xffff) /*64k alignment*/
5027 mc_buffer_size_h += 1;
5028 if ((!pbi->mmu_enable) && ((dw_mode & 0x10) == 0))
5029 buf_size += (mc_buffer_size_h << 16);
5030
5031 if (pbi->mmu_enable) {
5032 pic_config->header_adr = decoder_bmmu_box_get_phy_addr(
5033 pbi->bmmu_box, HEADER_BUFFER_IDX(pic_config->index));
5034
5035 if (debug & VP9_DEBUG_BUFMGR_MORE) {
5036 pr_info("MMU header_adr %d: %ld\n",
5037 pic_config->index, pic_config->header_adr);
5038 }
5039 }
5040
5041 i = pic_config->index;
5042#ifdef MV_USE_FIXED_BUF
5043 if ((pbi->work_space_buf->mpred_mv.buf_start +
5044 (((i + 1) * lcu_total) * MV_MEM_UNIT))
5045 <= mpred_mv_end
5046 ) {
5047#endif
5048 if (buf_size > 0) {
5049 ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box,
5050 VF_BUFFER_IDX(i),
5051 buf_size, DRIVER_NAME,
5052 &pic_config->cma_alloc_addr);
5053 if (ret < 0) {
5054 pr_info(
5055 "decoder_bmmu_box_alloc_buf_phy idx %d size %d fail\n",
5056 VF_BUFFER_IDX(i),
5057 buf_size
5058 );
5059 return ret;
5060 }
5061
5062 if (pic_config->cma_alloc_addr)
5063 y_adr = pic_config->cma_alloc_addr;
5064 else {
5065 pr_info(
5066 "decoder_bmmu_box_alloc_buf_phy idx %d size %d return null\n",
5067 VF_BUFFER_IDX(i),
5068 buf_size
5069 );
5070 return -1;
5071 }
5072 }
5073 {
5074 /*ensure get_pic_by_POC()
5075 not get the buffer not decoded*/
5076 pic_config->BUF_index = i;
5077 pic_config->lcu_total = lcu_total;
5078
5079 pic_config->comp_body_size = losless_comp_body_size;
5080 pic_config->buf_size = buf_size;
5081
5082 pic_config->mc_canvas_y = pic_config->index;
5083 pic_config->mc_canvas_u_v = pic_config->index;
5084 if (dw_mode & 0x10) {
5085 pic_config->dw_y_adr = y_adr;
5086 pic_config->dw_u_v_adr = y_adr +
5087 ((mc_buffer_size_u_v_h << 16) << 1);
5088
5089 pic_config->mc_canvas_y =
5090 (pic_config->index << 1);
5091 pic_config->mc_canvas_u_v =
5092 (pic_config->index << 1) + 1;
5093 } else if (dw_mode) {
5094 pic_config->dw_y_adr = y_adr;
5095 pic_config->dw_u_v_adr = pic_config->dw_y_adr +
5096 ((mc_buffer_size_u_v_h << 16) << 1);
5097 }
5098#ifdef MV_USE_FIXED_BUF
5099 pic_config->mpred_mv_wr_start_addr =
5100 pbi->work_space_buf->mpred_mv.buf_start +
5101 ((pic_config->index * lcu_total)
5102 * MV_MEM_UNIT);
5103#endif
5104 if (debug) {
5105 pr_info
5106 ("%s index %d BUF_index %d ",
5107 __func__, pic_config->index,
5108 pic_config->BUF_index);
5109 pr_info
5110 ("comp_body_size %x comp_buf_size %x ",
5111 pic_config->comp_body_size,
5112 pic_config->buf_size);
5113 pr_info
5114 ("mpred_mv_wr_start_adr %ld\n",
5115 pic_config->mpred_mv_wr_start_addr);
5116 pr_info("dw_y_adr %d, pic_config->dw_u_v_adr =%d\n",
5117 pic_config->dw_y_adr,
5118 pic_config->dw_u_v_adr);
5119 }
5120 ret = 0;
5121 }
5122#ifdef MV_USE_FIXED_BUF
5123 }
5124#endif
5125 return ret;
5126}
5127
5128static int vvp9_mmu_compress_header_size(struct VP9Decoder_s *pbi)
5129{
5130 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
5131 IS_8K_SIZE(pbi->max_pic_w, pbi->max_pic_h))
5132 return (MMU_COMPRESS_8K_HEADER_SIZE);
5133
5134 return (MMU_COMPRESS_HEADER_SIZE);
5135}
5136
5137/*#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)*/
5138static int vvp9_frame_mmu_map_size(struct VP9Decoder_s *pbi)
5139{
5140 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
5141 IS_8K_SIZE(pbi->max_pic_w, pbi->max_pic_h))
5142 return (MAX_FRAME_8K_NUM * 4);
5143
5144 return (MAX_FRAME_4K_NUM * 4);
5145}
5146
5147static void init_pic_list(struct VP9Decoder_s *pbi)
5148{
5149 int i;
5150 struct VP9_Common_s *cm = &pbi->common;
5151 struct PIC_BUFFER_CONFIG_s *pic_config;
5152 u32 header_size;
5153 struct vdec_s *vdec = hw_to_vdec(pbi);
5154
5155 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
5156 header_size = vvp9_mmu_compress_header_size(pbi);
5157 /*alloc VP9 compress header first*/
5158 for (i = 0; i < pbi->used_buf_num; i++) {
5159 unsigned long buf_addr;
5160 if (decoder_bmmu_box_alloc_buf_phy
5161 (pbi->bmmu_box,
5162 HEADER_BUFFER_IDX(i), header_size,
5163 DRIVER_HEADER_NAME,
5164 &buf_addr) < 0) {
5165 pr_info("%s malloc compress header failed %d\n",
5166 DRIVER_HEADER_NAME, i);
5167 pbi->fatal_error |= DECODER_FATAL_ERROR_NO_MEM;
5168 return;
5169 }
5170 }
5171 }
5172 for (i = 0; i < pbi->used_buf_num; i++) {
5173 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
5174 pic_config->index = i;
5175 pic_config->BUF_index = -1;
5176 pic_config->mv_buf_index = -1;
5177 if (vdec->parallel_dec == 1) {
5178 pic_config->y_canvas_index = -1;
5179 pic_config->uv_canvas_index = -1;
5180 }
5181 pic_config->y_crop_width = pbi->init_pic_w;
5182 pic_config->y_crop_height = pbi->init_pic_h;
5183 pic_config->double_write_mode = get_double_write_mode(pbi);
5184
5185 if (!pbi->is_used_v4l) {
5186 if (config_pic(pbi, pic_config) < 0) {
5187 if (debug)
5188 pr_info("Config_pic %d fail\n",
5189 pic_config->index);
5190 pic_config->index = -1;
5191 break;
5192 }
5193
5194 if (pic_config->double_write_mode) {
5195 set_canvas(pbi, pic_config);
5196 }
5197 }
5198 }
5199 for (; i < pbi->used_buf_num; i++) {
5200 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
5201 pic_config->index = -1;
5202 pic_config->BUF_index = -1;
5203 pic_config->mv_buf_index = -1;
5204 if (vdec->parallel_dec == 1) {
5205 pic_config->y_canvas_index = -1;
5206 pic_config->uv_canvas_index = -1;
5207 }
5208 }
5209 pr_info("%s ok, used_buf_num = %d\n",
5210 __func__, pbi->used_buf_num);
5211}
5212
5213static void init_pic_list_hw(struct VP9Decoder_s *pbi)
5214{
5215 int i;
5216 struct VP9_Common_s *cm = &pbi->common;
5217 struct PIC_BUFFER_CONFIG_s *pic_config;
5218 /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x0);*/
5219 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
5220 (0x1 << 1) | (0x1 << 2));
5221
5222
5223 for (i = 0; i < pbi->used_buf_num; i++) {
5224 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
5225 if (pic_config->index < 0)
5226 break;
5227
5228 if (pbi->mmu_enable && ((pic_config->double_write_mode & 0x10) == 0)) {
5229
5230 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
5231 pic_config->header_adr >> 5);
5232 } else {
5233 /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
5234 * pic_config->mc_y_adr
5235 * | (pic_config->mc_canvas_y << 8) | 0x1);
5236 */
5237 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
5238 pic_config->dw_y_adr >> 5);
5239 }
5240#ifndef LOSLESS_COMPRESS_MODE
5241 /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
5242 * pic_config->mc_u_v_adr
5243 * | (pic_config->mc_canvas_u_v << 8)| 0x1);
5244 */
5245 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
5246 pic_config->header_adr >> 5);
5247#else
5248 if (pic_config->double_write_mode & 0x10) {
5249 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
5250 pic_config->dw_u_v_adr >> 5);
5251 }
5252#endif
5253 }
5254 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
5255
5256 /*Zero out canvas registers in IPP -- avoid simulation X*/
5257 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
5258 (0 << 8) | (0 << 1) | 1);
5259 for (i = 0; i < 32; i++)
5260 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
5261}
5262
5263
5264static void dump_pic_list(struct VP9Decoder_s *pbi)
5265{
5266 struct VP9_Common_s *const cm = &pbi->common;
5267 struct PIC_BUFFER_CONFIG_s *pic_config;
5268 int i;
5269 for (i = 0; i < FRAME_BUFFERS; i++) {
5270 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
5271 vp9_print(pbi, 0,
5272 "Buf(%d) index %d mv_buf_index %d ref_count %d vf_ref %d dec_idx %d slice_type %d w/h %d/%d adr%ld\n",
5273 i,
5274 pic_config->index,
5275#ifndef MV_USE_FIXED_BUF
5276 pic_config->mv_buf_index,
5277#else
5278 -1,
5279#endif
5280 cm->buffer_pool->
5281 frame_bufs[i].ref_count,
5282 pic_config->vf_ref,
5283 pic_config->decode_idx,
5284 pic_config->slice_type,
5285 pic_config->y_crop_width,
5286 pic_config->y_crop_height,
5287 pic_config->cma_alloc_addr
5288 );
5289 }
5290 return;
5291}
5292
5293static int config_pic_size(struct VP9Decoder_s *pbi, unsigned short bit_depth)
5294{
5295#ifdef LOSLESS_COMPRESS_MODE
5296 unsigned int data32;
5297#endif
5298 int losless_comp_header_size, losless_comp_body_size;
5299 struct VP9_Common_s *cm = &pbi->common;
5300 struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf;
5301
5302 frame_width = cur_pic_config->y_crop_width;
5303 frame_height = cur_pic_config->y_crop_height;
5304 cur_pic_config->bit_depth = bit_depth;
5305 cur_pic_config->double_write_mode = get_double_write_mode(pbi);
5306 losless_comp_header_size =
5307 compute_losless_comp_header_size(cur_pic_config->y_crop_width,
5308 cur_pic_config->y_crop_height);
5309 losless_comp_body_size =
5310 compute_losless_comp_body_size(cur_pic_config->y_crop_width,
5311 cur_pic_config->y_crop_height, (bit_depth == VPX_BITS_10));
5312 cur_pic_config->comp_body_size = losless_comp_body_size;
5313#ifdef LOSLESS_COMPRESS_MODE
5314 data32 = READ_VREG(HEVC_SAO_CTRL5);
5315 if (bit_depth == VPX_BITS_10)
5316 data32 &= ~(1 << 9);
5317 else
5318 data32 |= (1 << 9);
5319
5320 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5321
5322 if (pbi->mmu_enable) {
5323 /*bit[4] : paged_mem_mode*/
5324 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
5325 } else {
5326 /*bit[3] smem mdoe*/
5327 if (bit_depth == VPX_BITS_10)
5328 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0 << 3));
5329 else
5330 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (1 << 3));
5331 }
5332 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_SM1)
5333 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, (losless_comp_body_size >> 5));
5334 /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,(0xff<<20) | (0xff<<10) | 0xff);*/
5335 WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size);
5336 WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size);
5337 WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size);
5338 if (get_double_write_mode(pbi) & 0x10)
5339 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5340#else
5341 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5342#endif
5343 return 0;
5344}
5345
5346static int config_mc_buffer(struct VP9Decoder_s *pbi, unsigned short bit_depth)
5347{
5348 int i;
5349 struct VP9_Common_s *cm = &pbi->common;
5350 struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf;
5351 uint8_t scale_enable = 0;
5352
5353 if (debug&VP9_DEBUG_BUFMGR_MORE)
5354 pr_info("config_mc_buffer entered .....\n");
5355
5356 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
5357 (0 << 8) | (0 << 1) | 1);
5358 for (i = 0; i < REFS_PER_FRAME; ++i) {
5359 struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf;
5360 if (!pic_config)
5361 continue;
5362 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
5363 (pic_config->mc_canvas_u_v << 16)
5364 | (pic_config->mc_canvas_u_v << 8)
5365 | pic_config->mc_canvas_y);
5366 if (debug & VP9_DEBUG_BUFMGR_MORE)
5367 pr_info("refid %x mc_canvas_u_v %x mc_canvas_y %x\n",
5368 i, pic_config->mc_canvas_u_v,
5369 pic_config->mc_canvas_y);
5370 }
5371 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
5372 (16 << 8) | (0 << 1) | 1);
5373 for (i = 0; i < REFS_PER_FRAME; ++i) {
5374 struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf;
5375 if (!pic_config)
5376 continue;
5377 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
5378 (pic_config->mc_canvas_u_v << 16)
5379 | (pic_config->mc_canvas_u_v << 8)
5380 | pic_config->mc_canvas_y);
5381 }
5382
5383 /*auto_inc start index:0 field:0*/
5384 WRITE_VREG(VP9D_MPP_REFINFO_TBL_ACCCONFIG, 0x1 << 2);
5385 /*index 0:last 1:golden 2:altref*/
5386 for (i = 0; i < REFS_PER_FRAME; i++) {
5387 int ref_pic_body_size;
5388 struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf;
5389 if (!pic_config)
5390 continue;
5391 WRITE_VREG(VP9D_MPP_REFINFO_DATA, pic_config->y_crop_width);
5392 WRITE_VREG(VP9D_MPP_REFINFO_DATA, pic_config->y_crop_height);
5393
5394 if (pic_config->y_crop_width != cur_pic_config->y_crop_width ||
5395 pic_config->y_crop_height != cur_pic_config->y_crop_height) {
5396 scale_enable |= (1 << i);
5397 }
5398 ref_pic_body_size =
5399 compute_losless_comp_body_size(pic_config->y_crop_width,
5400 pic_config->y_crop_height, (bit_depth == VPX_BITS_10));
5401 WRITE_VREG(VP9D_MPP_REFINFO_DATA,
5402 (pic_config->y_crop_width << 14)
5403 / cur_pic_config->y_crop_width);
5404 WRITE_VREG(VP9D_MPP_REFINFO_DATA,
5405 (pic_config->y_crop_height << 14)
5406 / cur_pic_config->y_crop_height);
5407 if (pbi->mmu_enable)
5408 WRITE_VREG(VP9D_MPP_REFINFO_DATA, 0);
5409 else
5410 WRITE_VREG(VP9D_MPP_REFINFO_DATA, ref_pic_body_size >> 5);
5411 }
5412 WRITE_VREG(VP9D_MPP_REF_SCALE_ENBL, scale_enable);
5413 return 0;
5414}
5415
5416static void clear_mpred_hw(struct VP9Decoder_s *pbi)
5417{
5418 unsigned int data32;
5419
5420 data32 = READ_VREG(HEVC_MPRED_CTRL4);
5421 data32 &= (~(1 << 6));
5422 WRITE_VREG(HEVC_MPRED_CTRL4, data32);
5423}
5424
5425static void config_mpred_hw(struct VP9Decoder_s *pbi)
5426{
5427 struct VP9_Common_s *cm = &pbi->common;
5428 struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf;
5429 struct PIC_BUFFER_CONFIG_s *last_frame_pic_config =
5430 &cm->prev_frame->buf;
5431
5432 unsigned int data32;
5433 int mpred_curr_lcu_x;
5434 int mpred_curr_lcu_y;
5435 int mpred_mv_rd_end_addr;
5436
5437
5438 mpred_mv_rd_end_addr = last_frame_pic_config->mpred_mv_wr_start_addr
5439 + (last_frame_pic_config->lcu_total * MV_MEM_UNIT);
5440
5441 data32 = READ_VREG(HEVC_MPRED_CURR_LCU);
5442 mpred_curr_lcu_x = data32 & 0xffff;
5443 mpred_curr_lcu_y = (data32 >> 16) & 0xffff;
5444
5445 if (debug & VP9_DEBUG_BUFMGR)
5446 pr_info("cur pic_config index %d col pic_config index %d\n",
5447 cur_pic_config->index, last_frame_pic_config->index);
5448 WRITE_VREG(HEVC_MPRED_CTRL3, 0x24122412);
5449 WRITE_VREG(HEVC_MPRED_ABV_START_ADDR,
5450 pbi->work_space_buf->mpred_above.buf_start);
5451
5452 data32 = READ_VREG(HEVC_MPRED_CTRL4);
5453
5454 data32 &= (~(1 << 6));
5455 data32 |= (cm->use_prev_frame_mvs << 6);
5456 WRITE_VREG(HEVC_MPRED_CTRL4, data32);
5457
5458 WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR,
5459 cur_pic_config->mpred_mv_wr_start_addr);
5460 WRITE_VREG(HEVC_MPRED_MV_WPTR, cur_pic_config->mpred_mv_wr_start_addr);
5461
5462 WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR,
5463 last_frame_pic_config->mpred_mv_wr_start_addr);
5464 WRITE_VREG(HEVC_MPRED_MV_RPTR,
5465 last_frame_pic_config->mpred_mv_wr_start_addr);
5466 /*data32 = ((pbi->lcu_x_num - pbi->tile_width_lcu)*MV_MEM_UNIT);*/
5467 /*WRITE_VREG(HEVC_MPRED_MV_WR_ROW_JUMP,data32);*/
5468 /*WRITE_VREG(HEVC_MPRED_MV_RD_ROW_JUMP,data32);*/
5469 WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR, mpred_mv_rd_end_addr);
5470
5471}
5472
5473static void config_sao_hw(struct VP9Decoder_s *pbi, union param_u *params)
5474{
5475 struct VP9_Common_s *cm = &pbi->common;
5476 struct PIC_BUFFER_CONFIG_s *pic_config = &cm->cur_frame->buf;
5477
5478 unsigned int data32;
5479 int lcu_size = 64;
5480 int mc_buffer_size_u_v =
5481 pic_config->lcu_total * lcu_size*lcu_size/2;
5482 int mc_buffer_size_u_v_h =
5483 (mc_buffer_size_u_v + 0xffff) >> 16;/*64k alignment*/
5484 struct aml_vcodec_ctx * v4l2_ctx = pbi->v4l2_ctx;
5485
5486 if (get_double_write_mode(pbi)) {
5487 WRITE_VREG(HEVC_SAO_Y_START_ADDR, pic_config->dw_y_adr);
5488 WRITE_VREG(HEVC_SAO_C_START_ADDR, pic_config->dw_u_v_adr);
5489 WRITE_VREG(HEVC_SAO_Y_WPTR, pic_config->dw_y_adr);
5490 WRITE_VREG(HEVC_SAO_C_WPTR, pic_config->dw_u_v_adr);
5491 } else {
5492 WRITE_VREG(HEVC_SAO_Y_START_ADDR, 0xffffffff);
5493 WRITE_VREG(HEVC_SAO_C_START_ADDR, 0xffffffff);
5494 }
5495 if (pbi->mmu_enable)
5496 WRITE_VREG(HEVC_CM_HEADER_START_ADDR, pic_config->header_adr);
5497
5498 data32 = (mc_buffer_size_u_v_h << 16) << 1;
5499 /*pr_info("data32=%x,mc_buffer_size_u_v_h=%x,lcu_total=%x\n",
5500 * data32, mc_buffer_size_u_v_h, pic_config->lcu_total);
5501 */
5502 WRITE_VREG(HEVC_SAO_Y_LENGTH, data32);
5503
5504 data32 = (mc_buffer_size_u_v_h << 16);
5505 WRITE_VREG(HEVC_SAO_C_LENGTH, data32);
5506
5507#ifdef VP9_10B_NV21
5508#ifdef DOS_PROJECT
5509 data32 = READ_VREG(HEVC_SAO_CTRL1);
5510 data32 &= (~0x3000);
5511 /*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/
5512 data32 |= (pbi->mem_map_mode << 12);
5513 data32 &= (~0x3);
5514 data32 |= 0x1; /* [1]:dw_disable [0]:cm_disable*/
5515 WRITE_VREG(HEVC_SAO_CTRL1, data32);
5516 /*[23:22] dw_v1_ctrl [21:20] dw_v0_ctrl [19:18] dw_h1_ctrl
5517 * [17:16] dw_h0_ctrl
5518 */
5519 data32 = READ_VREG(HEVC_SAO_CTRL5);
5520 /*set them all 0 for H265_NV21 (no down-scale)*/
5521 data32 &= ~(0xff << 16);
5522 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5523 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
5524 data32 &= (~0x30);
5525 /*[5:4] address_format 00:linear 01:32x32 10:64x32*/
5526 data32 |= (pbi->mem_map_mode << 4);
5527 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
5528#else
5529 /*m8baby test1902*/
5530 data32 = READ_VREG(HEVC_SAO_CTRL1);
5531 data32 &= (~0x3000);
5532 /*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/
5533 data32 |= (pbi->mem_map_mode << 12);
5534 data32 &= (~0xff0);
5535 /*data32 |= 0x670;*/ /*Big-Endian per 64-bit*/
5536 data32 |= 0x880; /*.Big-Endian per 64-bit */
5537 data32 &= (~0x3);
5538 data32 |= 0x1; /*[1]:dw_disable [0]:cm_disable*/
5539 WRITE_VREG(HEVC_SAO_CTRL1, data32);
5540 /* [23:22] dw_v1_ctrl [21:20] dw_v0_ctrl
5541 *[19:18] dw_h1_ctrl [17:16] dw_h0_ctrl
5542 */
5543 data32 = READ_VREG(HEVC_SAO_CTRL5);
5544 /* set them all 0 for H265_NV21 (no down-scale)*/
5545 data32 &= ~(0xff << 16);
5546 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5547
5548 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
5549 data32 &= (~0x30);
5550 /*[5:4] address_format 00:linear 01:32x32 10:64x32*/
5551 data32 |= (pbi->mem_map_mode << 4);
5552 data32 &= (~0xF);
5553 data32 |= 0x8; /*Big-Endian per 64-bit*/
5554 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
5555#endif
5556#else
5557 data32 = READ_VREG(HEVC_SAO_CTRL1);
5558 data32 &= (~0x3000);
5559 data32 |= (pbi->mem_map_mode <<
5560 12);
5561
5562/* [13:12] axi_aformat, 0-Linear,
5563 * 1-32x32, 2-64x32
5564 */
5565 data32 &= (~0xff0);
5566 /* data32 |= 0x670; // Big-Endian per 64-bit */
5567 data32 |= endian; /* Big-Endian per 64-bit */
5568 data32 &= (~0x3); /*[1]:dw_disable [0]:cm_disable*/
5569 if (get_double_write_mode(pbi) == 0)
5570 data32 |= 0x2; /*disable double write*/
5571 else if (get_double_write_mode(pbi) & 0x10)
5572 data32 |= 0x1; /*disable cm*/
5573 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) { /* >= G12A dw write control */
5574 unsigned int data;
5575 data = READ_VREG(HEVC_DBLK_CFGB);
5576 data &= (~0x300); /*[8]:first write enable (compress) [9]:double write enable (uncompress)*/
5577 if (get_double_write_mode(pbi) == 0)
5578 data |= (0x1 << 8); /*enable first write*/
5579 else if (get_double_write_mode(pbi) & 0x10)
5580 data |= (0x1 << 9); /*double write only*/
5581 else
5582 data |= ((0x1 << 8) |(0x1 << 9));
5583 WRITE_VREG(HEVC_DBLK_CFGB, data);
5584 }
5585
5586 /* swap uv */
5587 if (pbi->is_used_v4l) {
5588 if ((v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21) ||
5589 (v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
5590 data32 &= ~(1 << 8); /* NV21 */
5591 else
5592 data32 |= (1 << 8); /* NV12 */
5593 }
5594
5595 /*
5596 * [31:24] ar_fifo1_axi_thred
5597 * [23:16] ar_fifo0_axi_thred
5598 * [15:14] axi_linealign, 0-16bytes, 1-32bytes, 2-64bytes
5599 * [13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32
5600 * [11:08] axi_lendian_C
5601 * [07:04] axi_lendian_Y
5602 * [3] reserved
5603 * [2] clk_forceon
5604 * [1] dw_disable:disable double write output
5605 * [0] cm_disable:disable compress output
5606 */
5607 WRITE_VREG(HEVC_SAO_CTRL1, data32);
5608
5609 if (get_double_write_mode(pbi) & 0x10) {
5610 /* [23:22] dw_v1_ctrl
5611 *[21:20] dw_v0_ctrl
5612 *[19:18] dw_h1_ctrl
5613 *[17:16] dw_h0_ctrl
5614 */
5615 data32 = READ_VREG(HEVC_SAO_CTRL5);
5616 /*set them all 0 for H265_NV21 (no down-scale)*/
5617 data32 &= ~(0xff << 16);
5618 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5619 } else {
5620 data32 = READ_VREG(HEVC_SAO_CTRL5);
5621 data32 &= (~(0xff << 16));
5622 if (get_double_write_mode(pbi) == 2 ||
5623 get_double_write_mode(pbi) == 3)
5624 data32 |= (0xff<<16);
5625 else if (get_double_write_mode(pbi) == 4)
5626 data32 |= (0x33<<16);
5627 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5628 }
5629
5630 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
5631 data32 &= (~0x30);
5632 /* [5:4] -- address_format 00:linear 01:32x32 10:64x32 */
5633 data32 |= (pbi->mem_map_mode <<
5634 4);
5635 data32 &= (~0xF);
5636 data32 |= 0xf; /* valid only when double write only */
5637 /*data32 |= 0x8;*/ /* Big-Endian per 64-bit */
5638
5639 /* swap uv */
5640 if (pbi->is_used_v4l) {
5641 if ((v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21) ||
5642 (v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
5643 data32 |= (1 << 12); /* NV21 */
5644 else
5645 data32 &= ~(1 << 12); /* NV12 */
5646 }
5647
5648 /*
5649 * [3:0] little_endian
5650 * [5:4] address_format 00:linear 01:32x32 10:64x32
5651 * [7:6] reserved
5652 * [9:8] Linear_LineAlignment 00:16byte 01:32byte 10:64byte
5653 * [11:10] reserved
5654 * [12] CbCr_byte_swap
5655 * [31:13] reserved
5656 */
5657 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
5658#endif
5659}
5660
5661static void vp9_config_work_space_hw(struct VP9Decoder_s *pbi, u32 mask)
5662{
5663 struct BuffInfo_s *buf_spec = pbi->work_space_buf;
5664 unsigned int data32;
5665
5666 if (debug && pbi->init_flag == 0)
5667 pr_info("%s %x %x %x %x %x %x %x %x %x %x %x %x\n",
5668 __func__,
5669 buf_spec->ipp.buf_start,
5670 buf_spec->start_adr,
5671 buf_spec->short_term_rps.buf_start,
5672 buf_spec->vps.buf_start,
5673 buf_spec->sps.buf_start,
5674 buf_spec->pps.buf_start,
5675 buf_spec->sao_up.buf_start,
5676 buf_spec->swap_buf.buf_start,
5677 buf_spec->swap_buf2.buf_start,
5678 buf_spec->scalelut.buf_start,
5679 buf_spec->dblk_para.buf_start,
5680 buf_spec->dblk_data.buf_start);
5681
5682 if (mask & HW_MASK_FRONT) {
5683 if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0)
5684 WRITE_VREG(HEVC_RPM_BUFFER, (u32)pbi->rpm_phy_addr);
5685
5686 WRITE_VREG(HEVC_SHORT_TERM_RPS,
5687 buf_spec->short_term_rps.buf_start);
5688 /*WRITE_VREG(HEVC_VPS_BUFFER, buf_spec->vps.buf_start);*/
5689 /*WRITE_VREG(HEVC_SPS_BUFFER, buf_spec->sps.buf_start);*/
5690 WRITE_VREG(HEVC_PPS_BUFFER, buf_spec->pps.buf_start);
5691 WRITE_VREG(HEVC_STREAM_SWAP_BUFFER,
5692 buf_spec->swap_buf.buf_start);
5693 WRITE_VREG(HEVC_STREAM_SWAP_BUFFER2,
5694 buf_spec->swap_buf2.buf_start);
5695 WRITE_VREG(LMEM_DUMP_ADR, (u32)pbi->lmem_phy_addr);
5696
5697 }
5698
5699 if (mask & HW_MASK_BACK) {
5700#ifdef LOSLESS_COMPRESS_MODE
5701 int losless_comp_header_size =
5702 compute_losless_comp_header_size(pbi->init_pic_w,
5703 pbi->init_pic_h);
5704 int losless_comp_body_size =
5705 compute_losless_comp_body_size(pbi->init_pic_w,
5706 pbi->init_pic_h, buf_alloc_depth == 10);
5707#endif
5708 WRITE_VREG(HEVCD_IPP_LINEBUFF_BASE,
5709 buf_spec->ipp.buf_start);
5710 WRITE_VREG(HEVC_SAO_UP, buf_spec->sao_up.buf_start);
5711 WRITE_VREG(HEVC_SCALELUT, buf_spec->scalelut.buf_start);
5712 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
5713 /* cfg_addr_adp*/
5714 WRITE_VREG(HEVC_DBLK_CFGE, buf_spec->dblk_para.buf_start);
5715 if (debug & VP9_DEBUG_BUFMGR_MORE)
5716 pr_info("Write HEVC_DBLK_CFGE\n");
5717 }
5718 /* cfg_p_addr */
5719 WRITE_VREG(HEVC_DBLK_CFG4, buf_spec->dblk_para.buf_start);
5720 /* cfg_d_addr */
5721 WRITE_VREG(HEVC_DBLK_CFG5, buf_spec->dblk_data.buf_start);
5722
5723 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
5724 /*
5725 * data32 = (READ_VREG(P_HEVC_DBLK_CFG3)>>8) & 0xff; // xio left offset, default is 0x40
5726 * data32 = data32 * 2;
5727 * data32 = (READ_VREG(P_HEVC_DBLK_CFG3)>>16) & 0xff; // adp left offset, default is 0x040
5728 * data32 = data32 * 2;
5729 */
5730 WRITE_VREG(HEVC_DBLK_CFG3, 0x808010); // make left storage 2 x 4k]
5731 }
5732#ifdef LOSLESS_COMPRESS_MODE
5733 if (pbi->mmu_enable) {
5734 /*bit[4] : paged_mem_mode*/
5735 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
5736 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_SM1)
5737 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0);
5738 } else {
5739 /*if(cur_pic_config->bit_depth == VPX_BITS_10)
5740 * WRITE_VREG(P_HEVCD_MPP_DECOMP_CTL1, (0<<3));
5741 */
5742 /*bit[3] smem mdoe*/
5743 /*else WRITE_VREG(P_HEVCD_MPP_DECOMP_CTL1, (1<<3));*/
5744 /*bit[3] smem mdoe*/
5745 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2,
5746 (losless_comp_body_size >> 5));
5747 }
5748 /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL2,
5749 (losless_comp_body_size >> 5));*/
5750 /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,
5751 (0xff<<20) | (0xff<<10) | 0xff);*/
5752 /*8-bit mode */
5753 WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size);
5754 WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size);
5755 WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size);
5756 if (get_double_write_mode(pbi) & 0x10)
5757 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5758#else
5759 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5760#endif
5761
5762 if (pbi->mmu_enable) {
5763 WRITE_VREG(HEVC_SAO_MMU_VH0_ADDR, buf_spec->mmu_vbh.buf_start);
5764 WRITE_VREG(HEVC_SAO_MMU_VH1_ADDR, buf_spec->mmu_vbh.buf_start
5765 + buf_spec->mmu_vbh.buf_size/2);
5766 /*data32 = READ_VREG(P_HEVC_SAO_CTRL9);*/
5767 /*data32 |= 0x1;*/
5768 /*WRITE_VREG(P_HEVC_SAO_CTRL9, data32);*/
5769
5770 /* use HEVC_CM_HEADER_START_ADDR */
5771 data32 = READ_VREG(HEVC_SAO_CTRL5);
5772 data32 |= (1<<10);
5773 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5774 }
5775
5776 WRITE_VREG(VP9_SEG_MAP_BUFFER, buf_spec->seg_map.buf_start);
5777
5778 WRITE_VREG(LMEM_DUMP_ADR, (u32)pbi->lmem_phy_addr);
5779 /**/
5780 WRITE_VREG(VP9_PROB_SWAP_BUFFER, pbi->prob_buffer_phy_addr);
5781 WRITE_VREG(VP9_COUNT_SWAP_BUFFER, pbi->count_buffer_phy_addr);
5782 if (pbi->mmu_enable) {
5783 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A)
5784 WRITE_VREG(HEVC_ASSIST_MMU_MAP_ADDR, pbi->frame_mmu_map_phy_addr);
5785 else
5786 WRITE_VREG(VP9_MMU_MAP_BUFFER, pbi->frame_mmu_map_phy_addr);
5787 }
5788 }
5789}
5790
5791
5792#ifdef VP9_LPF_LVL_UPDATE
5793/*
5794 * Defines, declarations, sub-functions for vp9 de-block loop
5795 filter Thr/Lvl table update
5796 * - struct segmentation is for loop filter only (removed something)
5797 * - function "vp9_loop_filter_init" and "vp9_loop_filter_frame_init" will
5798 be instantiated in C_Entry
5799 * - vp9_loop_filter_init run once before decoding start
5800 * - vp9_loop_filter_frame_init run before every frame decoding start
5801 * - set video format to VP9 is in vp9_loop_filter_init
5802 */
5803#define MAX_LOOP_FILTER 63
5804#define MAX_REF_LF_DELTAS 4
5805#define MAX_MODE_LF_DELTAS 2
5806/*#define INTRA_FRAME 0*/
5807/*#define LAST_FRAME 1*/
5808/*#define MAX_REF_FRAMES 4*/
5809#define SEGMENT_DELTADATA 0
5810#define SEGMENT_ABSDATA 1
5811#define MAX_SEGMENTS 8
5812/*.#define SEG_TREE_PROBS (MAX_SEGMENTS-1)*/
5813/*no use for loop filter, if this struct for common use, pls add it back*/
5814/*#define PREDICTION_PROBS 3*/
5815/* no use for loop filter, if this struct for common use, pls add it back*/
5816
5817enum SEG_LVL_FEATURES {
5818 SEG_LVL_ALT_Q = 0, /*Use alternate Quantizer ....*/
5819 SEG_LVL_ALT_LF = 1, /*Use alternate loop filter value...*/
5820 SEG_LVL_REF_FRAME = 2, /*Optional Segment reference frame*/
5821 SEG_LVL_SKIP = 3, /*Optional Segment (0,0) + skip mode*/
5822 SEG_LVL_MAX = 4 /*Number of features supported*/
5823};
5824
5825struct segmentation {
5826 uint8_t enabled;
5827 uint8_t update_map;
5828 uint8_t update_data;
5829 uint8_t abs_delta;
5830 uint8_t temporal_update;
5831
5832 /*no use for loop filter, if this struct
5833 *for common use, pls add it back
5834 */
5835 /*vp9_prob tree_probs[SEG_TREE_PROBS]; */
5836 /* no use for loop filter, if this struct
5837 * for common use, pls add it back
5838 */
5839 /*vp9_prob pred_probs[PREDICTION_PROBS];*/
5840
5841 int16_t feature_data[MAX_SEGMENTS][SEG_LVL_MAX];
5842 unsigned int feature_mask[MAX_SEGMENTS];
5843};
5844
5845struct loop_filter_thresh {
5846 uint8_t mblim;
5847 uint8_t lim;
5848 uint8_t hev_thr;
5849};
5850
5851struct loop_filter_info_n {
5852 struct loop_filter_thresh lfthr[MAX_LOOP_FILTER + 1];
5853 uint8_t lvl[MAX_SEGMENTS][MAX_REF_FRAMES][MAX_MODE_LF_DELTAS];
5854};
5855
5856struct loopfilter {
5857 int filter_level;
5858
5859 int sharpness_level;
5860 int last_sharpness_level;
5861
5862 uint8_t mode_ref_delta_enabled;
5863 uint8_t mode_ref_delta_update;
5864
5865 /*0 = Intra, Last, GF, ARF*/
5866 signed char ref_deltas[MAX_REF_LF_DELTAS];
5867 signed char last_ref_deltas[MAX_REF_LF_DELTAS];
5868
5869 /*0 = ZERO_MV, MV*/
5870 signed char mode_deltas[MAX_MODE_LF_DELTAS];
5871 signed char last_mode_deltas[MAX_MODE_LF_DELTAS];
5872};
5873
5874static int vp9_clamp(int value, int low, int high)
5875{
5876 return value < low ? low : (value > high ? high : value);
5877}
5878
5879int segfeature_active(struct segmentation *seg,
5880 int segment_id,
5881 enum SEG_LVL_FEATURES feature_id) {
5882 return seg->enabled &&
5883 (seg->feature_mask[segment_id] & (1 << feature_id));
5884}
5885
5886int get_segdata(struct segmentation *seg, int segment_id,
5887 enum SEG_LVL_FEATURES feature_id) {
5888 return seg->feature_data[segment_id][feature_id];
5889}
5890
5891static void vp9_update_sharpness(struct loop_filter_info_n *lfi,
5892 int sharpness_lvl)
5893{
5894 int lvl;
5895 /*For each possible value for the loop filter fill out limits*/
5896 for (lvl = 0; lvl <= MAX_LOOP_FILTER; lvl++) {
5897 /*Set loop filter parameters that control sharpness.*/
5898 int block_inside_limit = lvl >> ((sharpness_lvl > 0) +
5899 (sharpness_lvl > 4));
5900
5901 if (sharpness_lvl > 0) {
5902 if (block_inside_limit > (9 - sharpness_lvl))
5903 block_inside_limit = (9 - sharpness_lvl);
5904 }
5905
5906 if (block_inside_limit < 1)
5907 block_inside_limit = 1;
5908
5909 lfi->lfthr[lvl].lim = (uint8_t)block_inside_limit;
5910 lfi->lfthr[lvl].mblim = (uint8_t)(2 * (lvl + 2) +
5911 block_inside_limit);
5912 }
5913}
5914
5915/*instantiate this function once when decode is started*/
5916void vp9_loop_filter_init(struct VP9Decoder_s *pbi)
5917{
5918 struct loop_filter_info_n *lfi = pbi->lfi;
5919 struct loopfilter *lf = pbi->lf;
5920 struct segmentation *seg_4lf = pbi->seg_4lf;
5921 int i;
5922 unsigned int data32;
5923
5924 memset(lfi, 0, sizeof(struct loop_filter_info_n));
5925 memset(lf, 0, sizeof(struct loopfilter));
5926 memset(seg_4lf, 0, sizeof(struct segmentation));
5927 lf->sharpness_level = 0; /*init to 0 */
5928 /*init limits for given sharpness*/
5929 vp9_update_sharpness(lfi, lf->sharpness_level);
5930 lf->last_sharpness_level = lf->sharpness_level;
5931 /*init hev threshold const vectors (actually no use)
5932 *for (i = 0; i <= MAX_LOOP_FILTER; i++)
5933 * lfi->lfthr[i].hev_thr = (uint8_t)(i >> 4);
5934 */
5935
5936 /*Write to register*/
5937 for (i = 0; i < 32; i++) {
5938 unsigned int thr;
5939
5940 thr = ((lfi->lfthr[i * 2 + 1].lim & 0x3f)<<8) |
5941 (lfi->lfthr[i * 2 + 1].mblim & 0xff);
5942 thr = (thr<<16) | ((lfi->lfthr[i*2].lim & 0x3f)<<8) |
5943 (lfi->lfthr[i * 2].mblim & 0xff);
5944 WRITE_VREG(HEVC_DBLK_CFG9, thr);
5945 }
5946
5947 /*video format is VP9*/
5948 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
5949 data32 = (0x3 << 14) | // (dw fifo thres r and b)
5950 (0x3 << 12) | // (dw fifo thres r or b)
5951 (0x3 << 10) | // (dw fifo thres not r/b)
5952 (0x3 << 8) | // 1st/2nd write both enable
5953 (0x1 << 0); // vp9 video format
5954 if (get_double_write_mode(pbi) == 0x10)
5955 data32 &= (~0x100);
5956 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
5957 data32 = (0x57 << 8) | /*1st/2nd write both enable*/
5958 (0x1 << 0); /*vp9 video format*/
5959 if (get_double_write_mode(pbi) == 0x10)
5960 data32 &= (~0x100);
5961 } else
5962 data32 = 0x40400001;
5963
5964 WRITE_VREG(HEVC_DBLK_CFGB, data32);
5965 if (debug & VP9_DEBUG_BUFMGR_MORE)
5966 pr_info("[DBLK DEBUG] CFGB : 0x%x\n", data32);
5967}
5968 /* perform this function per frame*/
5969void vp9_loop_filter_frame_init(struct segmentation *seg,
5970 struct loop_filter_info_n *lfi, struct loopfilter *lf,
5971 int default_filt_lvl) {
5972 int i;
5973 int seg_id;
5974 /*n_shift is the multiplier for lf_deltas
5975 *the multiplier is 1 for when filter_lvl is between 0 and 31;
5976 *2 when filter_lvl is between 32 and 63
5977 */
5978 const int scale = 1 << (default_filt_lvl >> 5);
5979
5980 /*update limits if sharpness has changed*/
5981 if (lf->last_sharpness_level != lf->sharpness_level) {
5982 vp9_update_sharpness(lfi, lf->sharpness_level);
5983 lf->last_sharpness_level = lf->sharpness_level;
5984
5985 /*Write to register*/
5986 for (i = 0; i < 32; i++) {
5987 unsigned int thr;
5988
5989 thr = ((lfi->lfthr[i * 2 + 1].lim & 0x3f) << 8)
5990 | (lfi->lfthr[i * 2 + 1].mblim & 0xff);
5991 thr = (thr << 16) | ((lfi->lfthr[i * 2].lim & 0x3f) << 8)
5992 | (lfi->lfthr[i * 2].mblim & 0xff);
5993 WRITE_VREG(HEVC_DBLK_CFG9, thr);
5994 }
5995 }
5996
5997 for (seg_id = 0; seg_id < MAX_SEGMENTS; seg_id++) {/*MAX_SEGMENTS = 8*/
5998 int lvl_seg = default_filt_lvl;
5999
6000 if (segfeature_active(seg, seg_id, SEG_LVL_ALT_LF)) {
6001 const int data = get_segdata(seg, seg_id,
6002 SEG_LVL_ALT_LF);
6003 lvl_seg = vp9_clamp(seg->abs_delta == SEGMENT_ABSDATA ?
6004 data : default_filt_lvl + data,
6005 0, MAX_LOOP_FILTER);
6006#ifdef DBG_LF_PRINT
6007 pr_info("segfeature_active!!!seg_id=%d,lvl_seg=%d\n", seg_id, lvl_seg);
6008#endif
6009 }
6010
6011 if (!lf->mode_ref_delta_enabled) {
6012 /*we could get rid of this if we assume that deltas are set to
6013 *zero when not in use; encoder always uses deltas
6014 */
6015 memset(lfi->lvl[seg_id], lvl_seg, sizeof(lfi->lvl[seg_id]));
6016 } else {
6017 int ref, mode;
6018 const int intra_lvl = lvl_seg + lf->ref_deltas[INTRA_FRAME]
6019 * scale;
6020#ifdef DBG_LF_PRINT
6021 pr_info("LF_PRINT:vp9_loop_filter_frame_init,seg_id=%d\n", seg_id);
6022 pr_info("ref_deltas[INTRA_FRAME]=%d\n", lf->ref_deltas[INTRA_FRAME]);
6023#endif
6024 lfi->lvl[seg_id][INTRA_FRAME][0] =
6025 vp9_clamp(intra_lvl, 0, MAX_LOOP_FILTER);
6026
6027 for (ref = LAST_FRAME; ref < MAX_REF_FRAMES; ++ref) {
6028 /* LAST_FRAME = 1, MAX_REF_FRAMES = 4*/
6029 for (mode = 0; mode < MAX_MODE_LF_DELTAS; ++mode) {
6030 /*MAX_MODE_LF_DELTAS = 2*/
6031 const int inter_lvl =
6032 lvl_seg + lf->ref_deltas[ref] * scale
6033 + lf->mode_deltas[mode] * scale;
6034#ifdef DBG_LF_PRINT
6035#endif
6036 lfi->lvl[seg_id][ref][mode] =
6037 vp9_clamp(inter_lvl, 0,
6038 MAX_LOOP_FILTER);
6039 }
6040 }
6041 }
6042 }
6043
6044#ifdef DBG_LF_PRINT
6045 /*print out thr/lvl table per frame*/
6046 for (i = 0; i <= MAX_LOOP_FILTER; i++) {
6047 pr_info("LF_PRINT:(%d)thr=%d,blim=%d,lim=%d\n",
6048 i, lfi->lfthr[i].hev_thr, lfi->lfthr[i].mblim,
6049 lfi->lfthr[i].lim);
6050 }
6051 for (seg_id = 0; seg_id < MAX_SEGMENTS; seg_id++) {
6052 pr_info("LF_PRINT:lvl(seg_id=%d)(mode=0,%d,%d,%d,%d)\n",
6053 seg_id, lfi->lvl[seg_id][0][0],
6054 lfi->lvl[seg_id][1][0], lfi->lvl[seg_id][2][0],
6055 lfi->lvl[seg_id][3][0]);
6056 pr_info("i(mode=1,%d,%d,%d,%d)\n", lfi->lvl[seg_id][0][1],
6057 lfi->lvl[seg_id][1][1], lfi->lvl[seg_id][2][1],
6058 lfi->lvl[seg_id][3][1]);
6059 }
6060#endif
6061
6062 /*Write to register */
6063 for (i = 0; i < 16; i++) {
6064 unsigned int level;
6065
6066 level = ((lfi->lvl[i >> 1][3][i & 1] & 0x3f) << 24) |
6067 ((lfi->lvl[i >> 1][2][i & 1] & 0x3f) << 16) |
6068 ((lfi->lvl[i >> 1][1][i & 1] & 0x3f) << 8) |
6069 (lfi->lvl[i >> 1][0][i & 1] & 0x3f);
6070 if (!default_filt_lvl)
6071 level = 0;
6072 WRITE_VREG(HEVC_DBLK_CFGA, level);
6073 }
6074}
6075/* VP9_LPF_LVL_UPDATE */
6076#endif
6077
6078static void vp9_init_decoder_hw(struct VP9Decoder_s *pbi, u32 mask)
6079{
6080 unsigned int data32;
6081 int i;
6082 const unsigned short parser_cmd[PARSER_CMD_NUMBER] = {
6083 0x0401, 0x8401, 0x0800, 0x0402, 0x9002, 0x1423,
6084 0x8CC3, 0x1423, 0x8804, 0x9825, 0x0800, 0x04FE,
6085 0x8406, 0x8411, 0x1800, 0x8408, 0x8409, 0x8C2A,
6086 0x9C2B, 0x1C00, 0x840F, 0x8407, 0x8000, 0x8408,
6087 0x2000, 0xA800, 0x8410, 0x04DE, 0x840C, 0x840D,
6088 0xAC00, 0xA000, 0x08C0, 0x08E0, 0xA40E, 0xFC00,
6089 0x7C00
6090 };
6091#if 0
6092 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
6093 /* Set MCR fetch priorities*/
6094 data32 = 0x1 | (0x1 << 2) | (0x1 <<3) |
6095 (24 << 4) | (32 << 11) | (24 << 18) | (32 << 25);
6096 WRITE_VREG(HEVCD_MPP_DECOMP_AXIURG_CTL, data32);
6097 }
6098#endif
6099 /*if (debug & VP9_DEBUG_BUFMGR_MORE)
6100 pr_info("%s\n", __func__);*/
6101 if (mask & HW_MASK_FRONT) {
6102 data32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
6103#if 1
6104 /* set bit 31~29 to 3 if HEVC_STREAM_FIFO_CTL[29] is 1 */
6105 data32 &= ~(7 << 29);
6106 data32 |= (3 << 29);
6107#endif
6108 data32 = data32 |
6109 (1 << 24) |/*stream_buffer_empty_int_amrisc_enable*/
6110 (1 << 22) |/*stream_fifo_empty_int_amrisc_enable*/
6111 (1 << 7) |/*dec_done_int_cpu_enable*/
6112 (1 << 4) |/*startcode_found_int_cpu_enable*/
6113 (0 << 3) |/*startcode_found_int_amrisc_enable*/
6114 (1 << 0) /*parser_int_enable*/
6115 ;
6116#ifdef SUPPORT_FB_DECODING
6117#ifndef FB_DECODING_TEST_SCHEDULE
6118 /*fed_fb_slice_done_int_cpu_enable*/
6119 if (pbi->used_stage_buf_num > 0)
6120 data32 |= (1 << 10);
6121#endif
6122#endif
6123 WRITE_VREG(HEVC_PARSER_INT_CONTROL, data32);
6124
6125 data32 = READ_VREG(HEVC_SHIFT_STATUS);
6126 data32 = data32 |
6127 (0 << 1) |/*emulation_check_off VP9
6128 do not have emulation*/
6129 (1 << 0)/*startcode_check_on*/
6130 ;
6131 WRITE_VREG(HEVC_SHIFT_STATUS, data32);
6132 WRITE_VREG(HEVC_SHIFT_CONTROL,
6133 (0 << 14) | /*disable_start_code_protect*/
6134 (1 << 10) | /*length_zero_startcode_en for VP9*/
6135 (1 << 9) | /*length_valid_startcode_en for VP9*/
6136 (3 << 6) | /*sft_valid_wr_position*/
6137 (2 << 4) | /*emulate_code_length_sub_1*/
6138 (3 << 1) | /*start_code_length_sub_1
6139 VP9 use 0x00000001 as startcode (4 Bytes)*/
6140 (1 << 0) /*stream_shift_enable*/
6141 );
6142
6143 WRITE_VREG(HEVC_CABAC_CONTROL,
6144 (1 << 0)/*cabac_enable*/
6145 );
6146
6147 WRITE_VREG(HEVC_PARSER_CORE_CONTROL,
6148 (1 << 0)/* hevc_parser_core_clk_en*/
6149 );
6150
6151
6152 WRITE_VREG(HEVC_DEC_STATUS_REG, 0);
6153
6154 }
6155
6156 if (mask & HW_MASK_BACK) {
6157 /*Initial IQIT_SCALELUT memory
6158 -- just to avoid X in simulation*/
6159
6160 WRITE_VREG(HEVC_IQIT_SCALELUT_WR_ADDR, 0);/*cfg_p_addr*/
6161 for (i = 0; i < 1024; i++)
6162 WRITE_VREG(HEVC_IQIT_SCALELUT_DATA, 0);
6163 }
6164
6165 if (mask & HW_MASK_FRONT) {
6166 u32 decode_mode;
6167#ifdef ENABLE_SWAP_TEST
6168 WRITE_VREG(HEVC_STREAM_SWAP_TEST, 100);
6169#else
6170 WRITE_VREG(HEVC_STREAM_SWAP_TEST, 0);
6171#endif
6172#ifdef MULTI_INSTANCE_SUPPORT
6173 if (!pbi->m_ins_flag) {
6174 if (pbi->low_latency_flag)
6175 decode_mode = DECODE_MODE_SINGLE_LOW_LATENCY;
6176 else
6177 decode_mode = DECODE_MODE_SINGLE;
6178 } else if (vdec_frame_based(hw_to_vdec(pbi)))
6179 decode_mode = pbi->no_head ?
6180 DECODE_MODE_MULTI_FRAMEBASE_NOHEAD :
6181 DECODE_MODE_MULTI_FRAMEBASE;
6182 else
6183 decode_mode = DECODE_MODE_MULTI_STREAMBASE;
6184#ifdef SUPPORT_FB_DECODING
6185#ifndef FB_DECODING_TEST_SCHEDULE
6186 if (pbi->used_stage_buf_num > 0)
6187 decode_mode |= (0x01 << 24);
6188#endif
6189#endif
6190 WRITE_VREG(DECODE_MODE, decode_mode);
6191 WRITE_VREG(HEVC_DECODE_SIZE, 0);
6192 WRITE_VREG(HEVC_DECODE_COUNT, 0);
6193#else
6194 WRITE_VREG(DECODE_MODE, DECODE_MODE_SINGLE);
6195 WRITE_VREG(HEVC_DECODE_PIC_BEGIN_REG, 0);
6196 WRITE_VREG(HEVC_DECODE_PIC_NUM_REG, 0x7fffffff); /*to remove*/
6197#endif
6198 /*Send parser_cmd*/
6199 WRITE_VREG(HEVC_PARSER_CMD_WRITE, (1 << 16) | (0 << 0));
6200 for (i = 0; i < PARSER_CMD_NUMBER; i++)
6201 WRITE_VREG(HEVC_PARSER_CMD_WRITE, parser_cmd[i]);
6202 WRITE_VREG(HEVC_PARSER_CMD_SKIP_0, PARSER_CMD_SKIP_CFG_0);
6203 WRITE_VREG(HEVC_PARSER_CMD_SKIP_1, PARSER_CMD_SKIP_CFG_1);
6204 WRITE_VREG(HEVC_PARSER_CMD_SKIP_2, PARSER_CMD_SKIP_CFG_2);
6205
6206
6207 WRITE_VREG(HEVC_PARSER_IF_CONTROL,
6208 /* (1 << 8) |*/ /*sao_sw_pred_enable*/
6209 (1 << 5) | /*parser_sao_if_en*/
6210 (1 << 2) | /*parser_mpred_if_en*/
6211 (1 << 0) /*parser_scaler_if_en*/
6212 );
6213 }
6214
6215 if (mask & HW_MASK_BACK) {
6216 /*Changed to Start MPRED in microcode*/
6217 /*
6218 pr_info("[test.c] Start MPRED\n");
6219 WRITE_VREG(HEVC_MPRED_INT_STATUS,
6220 (1<<31)
6221 );
6222 */
6223 WRITE_VREG(HEVCD_IPP_TOP_CNTL,
6224 (0 << 1) | /*enable ipp*/
6225 (1 << 0) /*software reset ipp and mpp*/
6226 );
6227 WRITE_VREG(HEVCD_IPP_TOP_CNTL,
6228 (1 << 1) | /*enable ipp*/
6229 (0 << 0) /*software reset ipp and mpp*/
6230 );
6231 if (get_double_write_mode(pbi) & 0x10) {
6232 /*Enable NV21 reference read mode for MC*/
6233 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
6234 }
6235
6236 /*Initialize mcrcc and decomp perf counters*/
6237 if (mcrcc_cache_alg_flag &&
6238 pbi->init_flag == 0) {
6239 mcrcc_perfcount_reset();
6240 decomp_perfcount_reset();
6241 }
6242 }
6243 return;
6244}
6245
6246
6247#ifdef CONFIG_HEVC_CLK_FORCED_ON
6248static void config_vp9_clk_forced_on(void)
6249{
6250 unsigned int rdata32;
6251 /*IQIT*/
6252 rdata32 = READ_VREG(HEVC_IQIT_CLK_RST_CTRL);
6253 WRITE_VREG(HEVC_IQIT_CLK_RST_CTRL, rdata32 | (0x1 << 2));
6254
6255 /* DBLK*/
6256 rdata32 = READ_VREG(HEVC_DBLK_CFG0);
6257 WRITE_VREG(HEVC_DBLK_CFG0, rdata32 | (0x1 << 2));
6258
6259 /* SAO*/
6260 rdata32 = READ_VREG(HEVC_SAO_CTRL1);
6261 WRITE_VREG(HEVC_SAO_CTRL1, rdata32 | (0x1 << 2));
6262
6263 /*MPRED*/
6264 rdata32 = READ_VREG(HEVC_MPRED_CTRL1);
6265 WRITE_VREG(HEVC_MPRED_CTRL1, rdata32 | (0x1 << 24));
6266
6267 /* PARSER*/
6268 rdata32 = READ_VREG(HEVC_STREAM_CONTROL);
6269 WRITE_VREG(HEVC_STREAM_CONTROL, rdata32 | (0x1 << 15));
6270 rdata32 = READ_VREG(HEVC_SHIFT_CONTROL);
6271 WRITE_VREG(HEVC_SHIFT_CONTROL, rdata32 | (0x1 << 15));
6272 rdata32 = READ_VREG(HEVC_CABAC_CONTROL);
6273 WRITE_VREG(HEVC_CABAC_CONTROL, rdata32 | (0x1 << 13));
6274 rdata32 = READ_VREG(HEVC_PARSER_CORE_CONTROL);
6275 WRITE_VREG(HEVC_PARSER_CORE_CONTROL, rdata32 | (0x1 << 15));
6276 rdata32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
6277 WRITE_VREG(HEVC_PARSER_INT_CONTROL, rdata32 | (0x1 << 15));
6278 rdata32 = READ_VREG(HEVC_PARSER_IF_CONTROL);
6279 WRITE_VREG(HEVC_PARSER_IF_CONTROL,
6280 rdata32 | (0x1 << 6) | (0x1 << 3) | (0x1 << 1));
6281
6282 /*IPP*/
6283 rdata32 = READ_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG);
6284 WRITE_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG, rdata32 | 0xffffffff);
6285
6286 /* MCRCC*/
6287 rdata32 = READ_VREG(HEVCD_MCRCC_CTL1);
6288 WRITE_VREG(HEVCD_MCRCC_CTL1, rdata32 | (0x1 << 3));
6289}
6290#endif
6291
6292
6293#ifdef MCRCC_ENABLE
6294static void dump_hit_rate(struct VP9Decoder_s *pbi)
6295{
6296 if (debug & VP9_DEBUG_CACHE_HIT_RATE) {
6297 mcrcc_get_hitrate(pbi->m_ins_flag);
6298 decomp_get_hitrate();
6299 decomp_get_comprate();
6300 }
6301}
6302
6303static void config_mcrcc_axi_hw(struct VP9Decoder_s *pbi)
6304{
6305 unsigned int rdata32;
6306 unsigned short is_inter;
6307 /*pr_info("Entered config_mcrcc_axi_hw...\n");*/
6308 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2);/* reset mcrcc*/
6309 is_inter = ((pbi->common.frame_type != KEY_FRAME) &&
6310 (!pbi->common.intra_only)) ? 1 : 0;
6311 if (!is_inter) { /* I-PIC*/
6312 /*remove reset -- disables clock*/
6313 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
6314 return;
6315 }
6316
6317 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
6318 mcrcc_get_hitrate(pbi->m_ins_flag);
6319 decomp_get_hitrate();
6320 decomp_get_comprate();
6321 }
6322
6323 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
6324 (0 << 8) | (1 << 1) | 0);
6325 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6326 rdata32 = rdata32 & 0xffff;
6327 rdata32 = rdata32 | (rdata32 << 16);
6328 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
6329 /*Programme canvas1 */
6330 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6331 rdata32 = rdata32 & 0xffff;
6332 rdata32 = rdata32 | (rdata32 << 16);
6333 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
6334 /*enable mcrcc progressive-mode*/
6335 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0);
6336}
6337
6338static void config_mcrcc_axi_hw_new(struct VP9Decoder_s *pbi)
6339{
6340 u32 curr_picnum = -1;
6341 u32 lastref_picnum = -1;
6342 u32 goldenref_picnum = -1;
6343 u32 altref_picnum = -1;
6344
6345 u32 lastref_delta_picnum;
6346 u32 goldenref_delta_picnum;
6347 u32 altref_delta_picnum;
6348
6349 u32 rdata32;
6350
6351 u32 lastcanvas;
6352 u32 goldencanvas;
6353 u32 altrefcanvas;
6354
6355 u16 is_inter;
6356 u16 lastref_inref;
6357 u16 goldenref_inref;
6358 u16 altref_inref;
6359
6360 u32 refcanvas_array[3], utmp;
6361 int deltapicnum_array[3], tmp;
6362
6363 struct VP9_Common_s *cm = &pbi->common;
6364 struct PIC_BUFFER_CONFIG_s *cur_pic_config
6365 = &cm->cur_frame->buf;
6366 curr_picnum = cur_pic_config->decode_idx;
6367 if (cm->frame_refs[0].buf)
6368 lastref_picnum = cm->frame_refs[0].buf->decode_idx;
6369 if (cm->frame_refs[1].buf)
6370 goldenref_picnum = cm->frame_refs[1].buf->decode_idx;
6371 if (cm->frame_refs[2].buf)
6372 altref_picnum = cm->frame_refs[2].buf->decode_idx;
6373
6374 lastref_delta_picnum = (lastref_picnum >= curr_picnum) ?
6375 (lastref_picnum - curr_picnum) : (curr_picnum - lastref_picnum);
6376 goldenref_delta_picnum = (goldenref_picnum >= curr_picnum) ?
6377 (goldenref_picnum - curr_picnum) :
6378 (curr_picnum - goldenref_picnum);
6379 altref_delta_picnum =
6380 (altref_picnum >= curr_picnum) ?
6381 (altref_picnum - curr_picnum) : (curr_picnum - altref_picnum);
6382
6383 lastref_inref = (cm->frame_refs[0].idx != INVALID_IDX) ? 1 : 0;
6384 goldenref_inref = (cm->frame_refs[1].idx != INVALID_IDX) ? 1 : 0;
6385 altref_inref = (cm->frame_refs[2].idx != INVALID_IDX) ? 1 : 0;
6386
6387 if (debug & VP9_DEBUG_CACHE)
6388 pr_info("%s--0--lastref_inref:%d goldenref_inref:%d altref_inref:%d\n",
6389 __func__, lastref_inref, goldenref_inref, altref_inref);
6390
6391 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2); /* reset mcrcc */
6392
6393 is_inter = ((pbi->common.frame_type != KEY_FRAME)
6394 && (!pbi->common.intra_only)) ? 1 : 0;
6395
6396 if (!is_inter) { /* I-PIC */
6397 /* remove reset -- disables clock */
6398 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
6399 return;
6400 }
6401
6402 if (!pbi->m_ins_flag)
6403 dump_hit_rate(pbi);
6404
6405 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (0 << 8) | (1<<1) | 0);
6406 lastcanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6407 goldencanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6408 altrefcanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6409
6410 if (debug & VP9_DEBUG_CACHE)
6411 pr_info("[test.c] lastref_canv:%x goldenref_canv:%x altref_canv:%x\n",
6412 lastcanvas, goldencanvas, altrefcanvas);
6413
6414 altref_inref = ((altref_inref == 1) &&
6415 (altrefcanvas != (goldenref_inref
6416 ? goldencanvas : 0xffffffff)) &&
6417 (altrefcanvas != (lastref_inref ?
6418 lastcanvas : 0xffffffff))) ? 1 : 0;
6419 goldenref_inref = ((goldenref_inref == 1) &&
6420 (goldencanvas != (lastref_inref ?
6421 lastcanvas : 0xffffffff))) ? 1 : 0;
6422 if (debug & VP9_DEBUG_CACHE)
6423 pr_info("[test.c]--1--lastref_inref:%d goldenref_inref:%d altref_inref:%d\n",
6424 lastref_inref, goldenref_inref, altref_inref);
6425
6426 altref_delta_picnum = altref_inref ? altref_delta_picnum : 0x7fffffff;
6427 goldenref_delta_picnum = goldenref_inref ?
6428 goldenref_delta_picnum : 0x7fffffff;
6429 lastref_delta_picnum = lastref_inref ?
6430 lastref_delta_picnum : 0x7fffffff;
6431 if (debug & VP9_DEBUG_CACHE)
6432 pr_info("[test.c]--1--lastref_delta_picnum:%d goldenref_delta_picnum:%d altref_delta_picnum:%d\n",
6433 lastref_delta_picnum, goldenref_delta_picnum,
6434 altref_delta_picnum);
6435 /*ARRAY SORT HERE DELTA/CANVAS ARRAY SORT -- use DELTA*/
6436
6437 refcanvas_array[0] = lastcanvas;
6438 refcanvas_array[1] = goldencanvas;
6439 refcanvas_array[2] = altrefcanvas;
6440
6441 deltapicnum_array[0] = lastref_delta_picnum;
6442 deltapicnum_array[1] = goldenref_delta_picnum;
6443 deltapicnum_array[2] = altref_delta_picnum;
6444
6445 /* sort0 : 2-to-1 */
6446 if (deltapicnum_array[2] < deltapicnum_array[1]) {
6447 utmp = refcanvas_array[2];
6448 refcanvas_array[2] = refcanvas_array[1];
6449 refcanvas_array[1] = utmp;
6450 tmp = deltapicnum_array[2];
6451 deltapicnum_array[2] = deltapicnum_array[1];
6452 deltapicnum_array[1] = tmp;
6453 }
6454 /* sort1 : 1-to-0 */
6455 if (deltapicnum_array[1] < deltapicnum_array[0]) {
6456 utmp = refcanvas_array[1];
6457 refcanvas_array[1] = refcanvas_array[0];
6458 refcanvas_array[0] = utmp;
6459 tmp = deltapicnum_array[1];
6460 deltapicnum_array[1] = deltapicnum_array[0];
6461 deltapicnum_array[0] = tmp;
6462 }
6463 /* sort2 : 2-to-1 */
6464 if (deltapicnum_array[2] < deltapicnum_array[1]) {
6465 utmp = refcanvas_array[2]; refcanvas_array[2] =
6466 refcanvas_array[1]; refcanvas_array[1] = utmp;
6467 tmp = deltapicnum_array[2]; deltapicnum_array[2] =
6468 deltapicnum_array[1]; deltapicnum_array[1] = tmp;
6469 }
6470 if (mcrcc_cache_alg_flag ==
6471 THODIYIL_MCRCC_CANVAS_ALGX) { /*09/15/2017*/
6472 /* lowest delta_picnum */
6473 rdata32 = refcanvas_array[0];
6474 rdata32 = rdata32 & 0xffff;
6475 rdata32 = rdata32 | (rdata32 << 16);
6476 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
6477
6478 /* 2nd-lowest delta_picnum */
6479 rdata32 = refcanvas_array[1];
6480 rdata32 = rdata32 & 0xffff;
6481 rdata32 = rdata32 | (rdata32 << 16);
6482 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
6483 } else {
6484 /* previous version -- LAST/GOLDEN ALWAYS -- before 09/13/2017*/
6485 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
6486 (0 << 8) | (1<<1) | 0);
6487 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6488 rdata32 = rdata32 & 0xffff;
6489 rdata32 = rdata32 | (rdata32 << 16);
6490 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
6491
6492 /* Programme canvas1 */
6493 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6494 rdata32 = rdata32 & 0xffff;
6495 rdata32 = rdata32 | (rdata32 << 16);
6496 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
6497 }
6498
6499 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0); /* enable mcrcc progressive-mode */
6500 return;
6501}
6502
6503#endif
6504
6505
6506static void free_lf_buf(struct VP9Decoder_s *pbi)
6507{
6508 if (pbi->lfi)
6509 vfree(pbi->lfi);
6510 if (pbi->lf)
6511 vfree(pbi->lf);
6512 if (pbi->seg_4lf)
6513 vfree(pbi->seg_4lf);
6514 pbi->lfi = NULL;
6515 pbi->lf = NULL;
6516 pbi->seg_4lf = NULL;
6517}
6518
6519static int alloc_lf_buf(struct VP9Decoder_s *pbi)
6520{
6521 pbi->lfi = vmalloc(sizeof(struct loop_filter_info_n));
6522 pbi->lf = vmalloc(sizeof(struct loopfilter));
6523 pbi->seg_4lf = vmalloc(sizeof(struct segmentation));
6524 if (pbi->lfi == NULL || pbi->lf == NULL || pbi->seg_4lf == NULL) {
6525 free_lf_buf(pbi);
6526 pr_err("[test.c] vp9_loop_filter init malloc error!!!\n");
6527 return -1;
6528 }
6529 return 0;
6530}
6531
6532static void vp9_local_uninit(struct VP9Decoder_s *pbi)
6533{
6534 pbi->rpm_ptr = NULL;
6535 pbi->lmem_ptr = NULL;
6536 if (pbi->rpm_addr) {
6537 dma_free_coherent(amports_get_dma_device(),
6538 RPM_BUF_SIZE,
6539 pbi->rpm_addr,
6540 pbi->rpm_phy_addr);
6541 pbi->rpm_addr = NULL;
6542 }
6543 if (pbi->lmem_addr) {
6544 if (pbi->lmem_phy_addr)
6545 dma_free_coherent(amports_get_dma_device(),
6546 LMEM_BUF_SIZE, pbi->lmem_addr,
6547 pbi->lmem_phy_addr);
6548 pbi->lmem_addr = NULL;
6549 }
6550 if (pbi->prob_buffer_addr) {
6551 if (pbi->prob_buffer_phy_addr)
6552 dma_free_coherent(amports_get_dma_device(),
6553 PROB_BUF_SIZE, pbi->prob_buffer_addr,
6554 pbi->prob_buffer_phy_addr);
6555
6556 pbi->prob_buffer_addr = NULL;
6557 }
6558 if (pbi->count_buffer_addr) {
6559 if (pbi->count_buffer_phy_addr)
6560 dma_free_coherent(amports_get_dma_device(),
6561 COUNT_BUF_SIZE, pbi->count_buffer_addr,
6562 pbi->count_buffer_phy_addr);
6563
6564 pbi->count_buffer_addr = NULL;
6565 }
6566 if (pbi->mmu_enable) {
6567 u32 mmu_map_size = vvp9_frame_mmu_map_size(pbi);
6568 if (pbi->frame_mmu_map_addr) {
6569 if (pbi->frame_mmu_map_phy_addr)
6570 dma_free_coherent(amports_get_dma_device(),
6571 mmu_map_size,
6572 pbi->frame_mmu_map_addr,
6573 pbi->frame_mmu_map_phy_addr);
6574 pbi->frame_mmu_map_addr = NULL;
6575 }
6576 }
6577#ifdef SUPPORT_FB_DECODING
6578 if (pbi->stage_mmu_map_addr) {
6579 if (pbi->stage_mmu_map_phy_addr)
6580 dma_free_coherent(amports_get_dma_device(),
6581 STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS,
6582 pbi->stage_mmu_map_addr,
6583 pbi->stage_mmu_map_phy_addr);
6584 pbi->stage_mmu_map_addr = NULL;
6585 }
6586
6587 uninit_stage_buf(pbi);
6588#endif
6589
6590#ifdef VP9_LPF_LVL_UPDATE
6591 free_lf_buf(pbi);
6592#endif
6593 if (pbi->gvs)
6594 vfree(pbi->gvs);
6595 pbi->gvs = NULL;
6596}
6597
6598static int vp9_local_init(struct VP9Decoder_s *pbi)
6599{
6600 int ret = -1;
6601 /*int losless_comp_header_size, losless_comp_body_size;*/
6602
6603 struct BuffInfo_s *cur_buf_info = NULL;
6604
6605 memset(&pbi->param, 0, sizeof(union param_u));
6606 memset(&pbi->common, 0, sizeof(struct VP9_Common_s));
6607#ifdef MULTI_INSTANCE_SUPPORT
6608 cur_buf_info = &pbi->work_space_buf_store;
6609
6610 if (vdec_is_support_4k()) {
6611 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
6612 memcpy(cur_buf_info, &amvvp9_workbuff_spec[2], /* 8k */
6613 sizeof(struct BuffInfo_s));
6614 } else
6615 memcpy(cur_buf_info, &amvvp9_workbuff_spec[1], /* 4k */
6616 sizeof(struct BuffInfo_s));
6617 } else
6618 memcpy(cur_buf_info, &amvvp9_workbuff_spec[0],/* 1080p */
6619 sizeof(struct BuffInfo_s));
6620
6621 cur_buf_info->start_adr = pbi->buf_start;
6622 if (!pbi->mmu_enable)
6623 pbi->mc_buf_spec.buf_end = pbi->buf_start + pbi->buf_size;
6624
6625#else
6626/*! MULTI_INSTANCE_SUPPORT*/
6627 if (vdec_is_support_4k()) {
6628 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
6629 cur_buf_info = &amvvp9_workbuff_spec[2];/* 8k work space */
6630 else
6631 cur_buf_info = &amvvp9_workbuff_spec[1];/* 4k2k work space */
6632 } else
6633 cur_buf_info = &amvvp9_workbuff_spec[0];/* 1080p work space */
6634
6635#endif
6636
6637 init_buff_spec(pbi, cur_buf_info);
6638 vp9_bufmgr_init(pbi, cur_buf_info, NULL);
6639
6640 if (!vdec_is_support_4k()
6641 && (buf_alloc_width > 1920 && buf_alloc_height > 1088)) {
6642 buf_alloc_width = 1920;
6643 buf_alloc_height = 1088;
6644 if (pbi->max_pic_w > 1920 && pbi->max_pic_h > 1088) {
6645 pbi->max_pic_w = 1920;
6646 pbi->max_pic_h = 1088;
6647 }
6648 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
6649 buf_alloc_width = 8192;
6650 buf_alloc_height = 4608;
6651 }
6652 pbi->init_pic_w = pbi->max_pic_w ? pbi->max_pic_w :
6653 (buf_alloc_width ? buf_alloc_width :
6654 (pbi->vvp9_amstream_dec_info.width ?
6655 pbi->vvp9_amstream_dec_info.width :
6656 pbi->work_space_buf->max_width));
6657 pbi->init_pic_h = pbi->max_pic_h ? pbi->max_pic_h :
6658 (buf_alloc_height ? buf_alloc_height :
6659 (pbi->vvp9_amstream_dec_info.height ?
6660 pbi->vvp9_amstream_dec_info.height :
6661 pbi->work_space_buf->max_height));
6662
6663 /* video is not support unaligned with 64 in tl1
6664 ** vdec canvas mode will be linear when dump yuv is set
6665 */
6666 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) &&
6667 (pbi->double_write_mode != 0) &&
6668 (((pbi->max_pic_w % 64) != 0) ||
6669 (pbi->vvp9_amstream_dec_info.width % 64) != 0)) {
6670 if (hw_to_vdec(pbi)->canvas_mode !=
6671 CANVAS_BLKMODE_LINEAR)
6672 pbi->mem_map_mode = 2;
6673 else {
6674 pbi->mem_map_mode = 0;
6675 pr_info("vdec blkmod linear, force mem_map_mode 0\n");
6676 }
6677 }
6678
6679#ifndef MV_USE_FIXED_BUF
6680 if (init_mv_buf_list(pbi) < 0) {
6681 pr_err("%s: init_mv_buf_list fail\n", __func__);
6682 return -1;
6683 }
6684#endif
6685 if (pbi->save_buffer_mode)
6686 pbi->used_buf_num = MAX_BUF_NUM_SAVE_BUF;
6687 else {
6688 if (pbi->is_used_v4l)
6689 pbi->used_buf_num = 5 + pbi->dynamic_buf_num_margin;
6690 else
6691 pbi->used_buf_num = max_buf_num;
6692 }
6693
6694 if (pbi->used_buf_num > MAX_BUF_NUM)
6695 pbi->used_buf_num = MAX_BUF_NUM;
6696 if (pbi->used_buf_num > FRAME_BUFFERS)
6697 pbi->used_buf_num = FRAME_BUFFERS;
6698
6699 pbi->pts_unstable = ((unsigned long)(pbi->vvp9_amstream_dec_info.param)
6700 & 0x40) >> 6;
6701
6702 if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0) {
6703 pbi->rpm_addr = dma_alloc_coherent(amports_get_dma_device(),
6704 RPM_BUF_SIZE,
6705 &pbi->rpm_phy_addr, GFP_KERNEL);
6706 if (pbi->rpm_addr == NULL) {
6707 pr_err("%s: failed to alloc rpm buffer\n", __func__);
6708 return -1;
6709 }
6710
6711 pbi->rpm_ptr = pbi->rpm_addr;
6712 }
6713
6714 pbi->lmem_addr = dma_alloc_coherent(amports_get_dma_device(),
6715 LMEM_BUF_SIZE,
6716 &pbi->lmem_phy_addr, GFP_KERNEL);
6717 if (pbi->lmem_addr == NULL) {
6718 pr_err("%s: failed to alloc lmem buffer\n", __func__);
6719 return -1;
6720 }
6721 pbi->lmem_ptr = pbi->lmem_addr;
6722
6723 pbi->prob_buffer_addr = dma_alloc_coherent(amports_get_dma_device(),
6724 PROB_BUF_SIZE,
6725 &pbi->prob_buffer_phy_addr, GFP_KERNEL);
6726 if (pbi->prob_buffer_addr == NULL) {
6727 pr_err("%s: failed to alloc prob_buffer\n", __func__);
6728 return -1;
6729 }
6730 memset(pbi->prob_buffer_addr, 0, PROB_BUF_SIZE);
6731 pbi->count_buffer_addr = dma_alloc_coherent(amports_get_dma_device(),
6732 COUNT_BUF_SIZE,
6733 &pbi->count_buffer_phy_addr, GFP_KERNEL);
6734 if (pbi->count_buffer_addr == NULL) {
6735 pr_err("%s: failed to alloc count_buffer\n", __func__);
6736 return -1;
6737 }
6738 memset(pbi->count_buffer_addr, 0, COUNT_BUF_SIZE);
6739
6740 if (pbi->mmu_enable) {
6741 u32 mmu_map_size = vvp9_frame_mmu_map_size(pbi);
6742 pbi->frame_mmu_map_addr =
6743 dma_alloc_coherent(amports_get_dma_device(),
6744 mmu_map_size,
6745 &pbi->frame_mmu_map_phy_addr, GFP_KERNEL);
6746 if (pbi->frame_mmu_map_addr == NULL) {
6747 pr_err("%s: failed to alloc count_buffer\n", __func__);
6748 return -1;
6749 }
6750 memset(pbi->frame_mmu_map_addr, 0, COUNT_BUF_SIZE);
6751 }
6752#ifdef SUPPORT_FB_DECODING
6753 if (pbi->m_ins_flag && stage_buf_num > 0) {
6754 pbi->stage_mmu_map_addr =
6755 dma_alloc_coherent(amports_get_dma_device(),
6756 STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS,
6757 &pbi->stage_mmu_map_phy_addr, GFP_KERNEL);
6758 if (pbi->stage_mmu_map_addr == NULL) {
6759 pr_err("%s: failed to alloc count_buffer\n", __func__);
6760 return -1;
6761 }
6762 memset(pbi->stage_mmu_map_addr,
6763 0, STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS);
6764
6765 init_stage_buf(pbi);
6766 }
6767#endif
6768
6769 ret = 0;
6770 return ret;
6771}
6772
6773/********************************************
6774 * Mailbox command
6775 ********************************************/
6776#define CMD_FINISHED 0
6777#define CMD_ALLOC_VIEW 1
6778#define CMD_FRAME_DISPLAY 3
6779#define CMD_DEBUG 10
6780
6781
6782#define DECODE_BUFFER_NUM_MAX 32
6783#define DISPLAY_BUFFER_NUM 6
6784
6785#define video_domain_addr(adr) (adr&0x7fffffff)
6786#define DECODER_WORK_SPACE_SIZE 0x800000
6787
6788#define spec2canvas(x) \
6789 (((x)->uv_canvas_index << 16) | \
6790 ((x)->uv_canvas_index << 8) | \
6791 ((x)->y_canvas_index << 0))
6792
6793
6794static void set_canvas(struct VP9Decoder_s *pbi,
6795 struct PIC_BUFFER_CONFIG_s *pic_config)
6796{
6797 struct vdec_s *vdec = hw_to_vdec(pbi);
6798 int canvas_w = ALIGN(pic_config->y_crop_width, 64)/4;
6799 int canvas_h = ALIGN(pic_config->y_crop_height, 32)/4;
6800 int blkmode = pbi->mem_map_mode;
6801 /*CANVAS_BLKMODE_64X32*/
6802 if (pic_config->double_write_mode) {
6803 canvas_w = pic_config->y_crop_width /
6804 get_double_write_ratio(pbi,
6805 pic_config->double_write_mode);
6806 canvas_h = pic_config->y_crop_height /
6807 get_double_write_ratio(pbi,
6808 pic_config->double_write_mode);
6809
6810 if (pbi->mem_map_mode == 0)
6811 canvas_w = ALIGN(canvas_w, 32);
6812 else
6813 canvas_w = ALIGN(canvas_w, 64);
6814 canvas_h = ALIGN(canvas_h, 32);
6815
6816 if (vdec->parallel_dec == 1) {
6817 if (pic_config->y_canvas_index == -1)
6818 pic_config->y_canvas_index =
6819 vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
6820 if (pic_config->uv_canvas_index == -1)
6821 pic_config->uv_canvas_index =
6822 vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
6823 } else {
6824 pic_config->y_canvas_index = 128 + pic_config->index * 2;
6825 pic_config->uv_canvas_index = 128 + pic_config->index * 2 + 1;
6826 }
6827
6828 canvas_config_ex(pic_config->y_canvas_index,
6829 pic_config->dw_y_adr, canvas_w, canvas_h,
6830 CANVAS_ADDR_NOWRAP, blkmode, pbi->is_used_v4l ? 0 : 7);
6831 canvas_config_ex(pic_config->uv_canvas_index,
6832 pic_config->dw_u_v_adr, canvas_w, canvas_h,
6833 CANVAS_ADDR_NOWRAP, blkmode, pbi->is_used_v4l ? 0 : 7);
6834
6835#ifdef MULTI_INSTANCE_SUPPORT
6836 pic_config->canvas_config[0].phy_addr =
6837 pic_config->dw_y_adr;
6838 pic_config->canvas_config[0].width =
6839 canvas_w;
6840 pic_config->canvas_config[0].height =
6841 canvas_h;
6842 pic_config->canvas_config[0].block_mode =
6843 blkmode;
6844 pic_config->canvas_config[0].endian = pbi->is_used_v4l ? 0 : 7;
6845
6846 pic_config->canvas_config[1].phy_addr =
6847 pic_config->dw_u_v_adr;
6848 pic_config->canvas_config[1].width =
6849 canvas_w;
6850 pic_config->canvas_config[1].height =
6851 canvas_h;
6852 pic_config->canvas_config[1].block_mode =
6853 blkmode;
6854 pic_config->canvas_config[1].endian = pbi->is_used_v4l ? 0 : 7;
6855#endif
6856 }
6857}
6858
6859
6860static void set_frame_info(struct VP9Decoder_s *pbi, struct vframe_s *vf)
6861{
6862 unsigned int ar;
6863 vf->duration = pbi->frame_dur;
6864 vf->duration_pulldown = 0;
6865 vf->flag = 0;
6866 vf->prop.master_display_colour = pbi->vf_dp;
6867 vf->signal_type = pbi->video_signal_type;
6868 if (vf->compWidth && vf->compHeight)
6869 pbi->frame_ar = vf->compHeight * 0x100 / vf->compWidth;
6870 ar = min_t(u32, pbi->frame_ar, DISP_RATIO_ASPECT_RATIO_MAX);
6871 vf->ratio_control = (ar << DISP_RATIO_ASPECT_RATIO_BIT);
6872
6873 if (pbi->is_used_v4l && pbi->vf_dp.present_flag) {
6874 struct aml_vdec_hdr_infos hdr;
6875 struct aml_vcodec_ctx *ctx =
6876 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
6877
6878 memset(&hdr, 0, sizeof(hdr));
6879 hdr.signal_type = vf->signal_type;
6880 hdr.color_parms = pbi->vf_dp;
6881 vdec_v4l_set_hdr_infos(ctx, &hdr);
6882 }
6883
6884 if ((pbi->chunk != NULL) && (pbi->chunk->hdr10p_data_buf != NULL)
6885 && (pbi->chunk->hdr10p_data_size != 0)) {
6886 char *new_buf;
6887 int i = 0;
6888 new_buf = vzalloc(pbi->chunk->hdr10p_data_size);
6889
6890 if (new_buf) {
6891 memcpy(new_buf, pbi->chunk->hdr10p_data_buf, pbi->chunk->hdr10p_data_size);
6892 if (debug & VP9_DEBUG_BUFMGR_MORE) {
6893 vp9_print(pbi, VP9_DEBUG_BUFMGR_MORE,
6894 "hdr10p data: (size %d)\n",
6895 pbi->chunk->hdr10p_data_size);
6896 for (i = 0; i < pbi->chunk->hdr10p_data_size; i++) {
6897 vp9_print(pbi, VP9_DEBUG_BUFMGR_MORE,
6898 "%02x ", pbi->chunk->hdr10p_data_buf[i]);
6899 if (((i + 1) & 0xf) == 0)
6900 vp9_print(pbi, VP9_DEBUG_BUFMGR_MORE, "\n");
6901 }
6902 vp9_print(pbi, VP9_DEBUG_BUFMGR_MORE, "\n");
6903 }
6904
6905 vf->hdr10p_data_size = pbi->chunk->hdr10p_data_size;
6906 vf->hdr10p_data_buf = new_buf;
6907 } else {
6908 vp9_print(pbi, 0, "%s:hdr10p data vzalloc size(%d) fail\n",
6909 __func__, pbi->chunk->hdr10p_data_size);
6910 vf->hdr10p_data_size = pbi->chunk->hdr10p_data_size;
6911 vf->hdr10p_data_buf = new_buf;
6912 }
6913
6914 vfree(pbi->chunk->hdr10p_data_buf);
6915 pbi->chunk->hdr10p_data_buf = NULL;
6916 pbi->chunk->hdr10p_data_size = 0;
6917 }
6918
6919 vf->sidebind_type = pbi->sidebind_type;
6920 vf->sidebind_channel_id = pbi->sidebind_channel_id;
6921}
6922
6923static int vvp9_vf_states(struct vframe_states *states, void *op_arg)
6924{
6925 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6926
6927 states->vf_pool_size = VF_POOL_SIZE;
6928 states->buf_free_num = kfifo_len(&pbi->newframe_q);
6929 states->buf_avail_num = kfifo_len(&pbi->display_q);
6930
6931 if (step == 2)
6932 states->buf_avail_num = 0;
6933 return 0;
6934}
6935
6936static struct vframe_s *vvp9_vf_peek(void *op_arg)
6937{
6938 struct vframe_s *vf[2] = {0, 0};
6939 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6940
6941 if (step == 2)
6942 return NULL;
6943
6944 if (kfifo_out_peek(&pbi->display_q, (void *)&vf, 2)) {
6945 if (vf[1]) {
6946 vf[0]->next_vf_pts_valid = true;
6947 vf[0]->next_vf_pts = vf[1]->pts;
6948 } else
6949 vf[0]->next_vf_pts_valid = false;
6950 return vf[0];
6951 }
6952
6953 return NULL;
6954}
6955
6956static struct vframe_s *vvp9_vf_get(void *op_arg)
6957{
6958 struct vframe_s *vf;
6959 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6960
6961 if (step == 2)
6962 return NULL;
6963 else if (step == 1)
6964 step = 2;
6965
6966 if (kfifo_get(&pbi->display_q, &vf)) {
6967 struct vframe_s *next_vf;
6968 uint8_t index = vf->index & 0xff;
6969 if (index < pbi->used_buf_num ||
6970 (vf->type & VIDTYPE_V4L_EOS)) {
6971 vf->index_disp = pbi->vf_get_count;
6972 pbi->vf_get_count++;
6973 if (debug & VP9_DEBUG_BUFMGR)
6974 pr_info("%s type 0x%x w/h %d/%d, pts %d, %lld\n",
6975 __func__, vf->type,
6976 vf->width, vf->height,
6977 vf->pts,
6978 vf->pts_us64);
6979
6980 if (kfifo_peek(&pbi->display_q, &next_vf)) {
6981 vf->next_vf_pts_valid = true;
6982 vf->next_vf_pts = next_vf->pts;
6983 } else
6984 vf->next_vf_pts_valid = false;
6985
6986 return vf;
6987 }
6988 }
6989 return NULL;
6990}
6991
6992static void vvp9_vf_put(struct vframe_s *vf, void *op_arg)
6993{
6994 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6995 uint8_t index = vf->index & 0xff;
6996
6997 if (vf == (&pbi->vframe_dummy))
6998 return;
6999
7000 if (pbi->enable_fence && vf->fence) {
7001 vdec_fence_put(vf->fence);
7002 vf->fence = NULL;
7003 }
7004
7005 if (vf->hdr10p_data_buf) {
7006 vfree(vf->hdr10p_data_buf);
7007 vf->hdr10p_data_buf = NULL;
7008 vf->hdr10p_data_size = 0;
7009 }
7010
7011 kfifo_put(&pbi->newframe_q, (const struct vframe_s *)vf);
7012 pbi->vf_put_count++;
7013 if (index < pbi->used_buf_num) {
7014 struct VP9_Common_s *cm = &pbi->common;
7015 struct BufferPool_s *pool = cm->buffer_pool;
7016 unsigned long flags;
7017
7018 lock_buffer_pool(pool, flags);
7019 if (pool->frame_bufs[index].buf.vf_ref > 0)
7020 pool->frame_bufs[index].buf.vf_ref--;
7021
7022 if (pbi->is_used_v4l)
7023 pool->frame_bufs[index].buf.vframe_bound = true;
7024
7025 if (pbi->wait_buf)
7026 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG,
7027 0x1);
7028 pbi->last_put_idx = index;
7029 pbi->new_frame_displayed++;
7030 unlock_buffer_pool(pool, flags);
7031#ifdef SUPPORT_FB_DECODING
7032 if (pbi->used_stage_buf_num > 0 &&
7033 pbi->back_not_run_ready)
7034 trigger_schedule(pbi);
7035#endif
7036 }
7037
7038}
7039
7040static int vvp9_event_cb(int type, void *data, void *private_data)
7041{
7042 if (type & VFRAME_EVENT_RECEIVER_RESET) {
7043#if 0
7044 unsigned long flags;
7045
7046 amhevc_stop();
7047#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
7048 vf_light_unreg_provider(&vvp9_vf_prov);
7049#endif
7050 spin_lock_irqsave(&pbi->lock, flags);
7051 vvp9_local_init();
7052 vvp9_prot_init();
7053 spin_unlock_irqrestore(&pbi->lock, flags);
7054#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
7055 vf_reg_provider(&vvp9_vf_prov);
7056#endif
7057 amhevc_start();
7058#endif
7059 }
7060
7061 return 0;
7062}
7063
7064void inc_vf_ref(struct VP9Decoder_s *pbi, int index)
7065{
7066 struct VP9_Common_s *cm = &pbi->common;
7067
7068 cm->buffer_pool->frame_bufs[index].buf.vf_ref++;
7069
7070 if (debug & VP9_DEBUG_BUFMGR_MORE)
7071 pr_info("%s index = %d new vf_ref = %d\r\n",
7072 __func__, index,
7073 cm->buffer_pool->frame_bufs[index].buf.vf_ref);
7074}
7075
7076static int frame_duration_adapt(struct VP9Decoder_s *pbi, struct vframe_s *vf, u32 valid)
7077{
7078 u32 old_duration, pts_duration = 0;
7079 u32 pts = vf->pts;
7080
7081 if (pbi->get_frame_dur == true)
7082 return true;
7083
7084 pbi->frame_cnt_window++;
7085 if (!(pbi->vp9_first_pts_ready == 1)) {
7086 if (valid) {
7087 pbi->pts1 = pts;
7088 pbi->frame_cnt_window = 0;
7089 pbi->duration_from_pts_done = 0;
7090 pbi->vp9_first_pts_ready = 1;
7091 } else {
7092 return false;
7093 }
7094 } else {
7095 if (pts < pbi->pts1) {
7096 if (pbi->frame_cnt_window > FRAME_CNT_WINDOW_SIZE) {
7097 pbi->pts1 = pts;
7098 pbi->frame_cnt_window = 0;
7099 }
7100 }
7101
7102 if (valid && (pbi->frame_cnt_window > FRAME_CNT_WINDOW_SIZE) &&
7103 (pts > pbi->pts1) && (pbi->duration_from_pts_done == 0)) {
7104 old_duration = pbi->frame_dur;
7105 pbi->pts2 = pts;
7106 pts_duration = (((pbi->pts2 - pbi->pts1) * 16) /
7107 (pbi->frame_cnt_window * 15));
7108
7109 if (close_to(pts_duration, old_duration, 2000)) {
7110 pbi->frame_dur = pts_duration;
7111 if ((debug & VP9_DEBUG_OUT_PTS) != 0)
7112 pr_info("use calc duration %d\n", pts_duration);
7113 }
7114
7115 if (pbi->duration_from_pts_done == 0) {
7116 if (close_to(pts_duration, old_duration, RATE_CORRECTION_THRESHOLD)) {
7117 pbi->duration_from_pts_done = 1;
7118 } else {
7119 if (!close_to(pts_duration,
7120 old_duration, 1000) &&
7121 !close_to(pts_duration,
7122 pbi->frame_dur, 1000) &&
7123 close_to(pts_duration,
7124 pbi->last_duration, 200)) {
7125 /* frame_dur must
7126 * wrong,recover it.
7127 */
7128 pbi->frame_dur = pts_duration;
7129 }
7130 pbi->pts1 = pbi->pts2;
7131 pbi->frame_cnt_window = 0;
7132 pbi->duration_from_pts_done = 0;
7133 }
7134 }
7135 pbi->last_duration = pts_duration;
7136 }
7137 }
7138 return true;
7139}
7140
7141static void update_vf_memhandle(struct VP9Decoder_s *pbi,
7142 struct vframe_s *vf, struct PIC_BUFFER_CONFIG_s *pic)
7143{
7144 if (pic->index < 0) {
7145 vf->mem_handle = NULL;
7146 vf->mem_head_handle = NULL;
7147 vf->mem_dw_handle = NULL;
7148 } else if (vf->type & VIDTYPE_SCATTER) {
7149 vf->mem_handle =
7150 decoder_mmu_box_get_mem_handle(
7151 pbi->mmu_box, pic->index);
7152 vf->mem_head_handle =
7153 decoder_bmmu_box_get_mem_handle(
7154 pbi->bmmu_box,
7155 HEADER_BUFFER_IDX(pic->BUF_index));
7156 if (pbi->double_write_mode == 3)
7157 vf->mem_dw_handle =
7158 decoder_bmmu_box_get_mem_handle(
7159 pbi->bmmu_box,
7160 VF_BUFFER_IDX(pic->BUF_index));
7161 else
7162 vf->mem_dw_handle = NULL;
7163 } else {
7164 vf->mem_handle =
7165 decoder_bmmu_box_get_mem_handle(
7166 pbi->bmmu_box, VF_BUFFER_IDX(pic->BUF_index));
7167 vf->mem_head_handle = NULL;
7168 vf->mem_dw_handle = NULL;
7169 /*vf->mem_head_handle =
7170 *decoder_bmmu_box_get_mem_handle(
7171 *hevc->bmmu_box, VF_BUFFER_IDX(BUF_index));
7172 */
7173 }
7174}
7175
7176static inline void pbi_update_gvs(struct VP9Decoder_s *pbi)
7177{
7178 if (pbi->gvs->frame_height != frame_height) {
7179 pbi->gvs->frame_width = frame_width;
7180 pbi->gvs->frame_height = frame_height;
7181 }
7182 if (pbi->gvs->frame_dur != pbi->frame_dur) {
7183 pbi->gvs->frame_dur = pbi->frame_dur;
7184 if (pbi->frame_dur != 0)
7185 pbi->gvs->frame_rate = 96000 / pbi->frame_dur;
7186 else
7187 pbi->gvs->frame_rate = -1;
7188 }
7189 pbi->gvs->status = pbi->stat | pbi->fatal_error;
7190}
7191
7192static int prepare_display_buf(struct VP9Decoder_s *pbi,
7193 struct PIC_BUFFER_CONFIG_s *pic_config)
7194{
7195 struct vframe_s *vf = NULL;
7196 struct vdec_s *pvdec = hw_to_vdec(pbi);
7197 int stream_offset = pic_config->stream_offset;
7198 unsigned short slice_type = pic_config->slice_type;
7199 struct aml_vcodec_ctx * v4l2_ctx = pbi->v4l2_ctx;
7200 ulong nv_order = VIDTYPE_VIU_NV21;
7201 u32 pts_valid = 0, pts_us64_valid = 0;
7202 u32 pts_save;
7203 u64 pts_us64_save;
7204 u32 frame_size = 0;
7205 int i = 0;
7206
7207
7208 if (debug & VP9_DEBUG_BUFMGR)
7209 pr_info("%s index = %d\r\n", __func__, pic_config->index);
7210 if (kfifo_get(&pbi->newframe_q, &vf) == 0) {
7211 pr_info("fatal error, no available buffer slot.");
7212 return -1;
7213 }
7214
7215 /* swap uv */
7216 if (pbi->is_used_v4l) {
7217 if ((v4l2_ctx->cap_pix_fmt == V4L2_PIX_FMT_NV12) ||
7218 (v4l2_ctx->cap_pix_fmt == V4L2_PIX_FMT_NV12M))
7219 nv_order = VIDTYPE_VIU_NV12;
7220 }
7221
7222 if (pic_config->double_write_mode)
7223 set_canvas(pbi, pic_config);
7224
7225 display_frame_count[pbi->index]++;
7226 if (vf) {
7227 if (!force_pts_unstable) {
7228 if ((pic_config->pts == 0) || (pic_config->pts <= pbi->last_pts)) {
7229 for (i = (FRAME_BUFFERS - 1); i > 0; i--) {
7230 if ((pbi->last_pts == pbi->frame_mode_pts_save[i]) ||
7231 (pbi->last_pts_us64 == pbi->frame_mode_pts64_save[i])) {
7232 pic_config->pts = pbi->frame_mode_pts_save[i - 1];
7233 pic_config->pts64 = pbi->frame_mode_pts64_save[i - 1];
7234 break;
7235 }
7236 }
7237 if ((i == 0) || (pic_config->pts <= pbi->last_pts)) {
7238 vp9_print(pbi, VP9_DEBUG_OUT_PTS,
7239 "no found pts %d, set 0. %d, %d\n",
7240 i, pic_config->pts, pbi->last_pts);
7241 pic_config->pts = 0;
7242 pic_config->pts64 = 0;
7243 }
7244 }
7245 }
7246
7247 if (pbi->is_used_v4l) {
7248 vf->v4l_mem_handle
7249 = pbi->m_BUF[pic_config->BUF_index].v4l_ref_buf_addr;
7250 if (pbi->mmu_enable) {
7251 vf->mm_box.bmmu_box = pbi->bmmu_box;
7252 vf->mm_box.bmmu_idx = HEADER_BUFFER_IDX(pic_config->BUF_index);
7253 vf->mm_box.mmu_box = pbi->mmu_box;
7254 vf->mm_box.mmu_idx = pic_config->index;
7255 }
7256 }
7257
7258 if (pbi->enable_fence) {
7259 /* fill fence information. */
7260 if (pbi->fence_usage == FENCE_USE_FOR_DRIVER)
7261 vf->fence = pic_config->fence;
7262 }
7263
7264#ifdef MULTI_INSTANCE_SUPPORT
7265 if (vdec_frame_based(pvdec)) {
7266 vf->pts = pic_config->pts;
7267 vf->pts_us64 = pic_config->pts64;
7268 vf->timestamp = pic_config->timestamp;
7269 if (vf->pts != 0 || vf->pts_us64 != 0) {
7270 pts_valid = 1;
7271 pts_us64_valid = 1;
7272 } else {
7273 pts_valid = 0;
7274 pts_us64_valid = 0;
7275 }
7276 } else
7277#endif
7278 /* if (pts_lookup_offset(PTS_TYPE_VIDEO,
7279 * stream_offset, &vf->pts, 0) != 0) {
7280 */
7281 if (pts_lookup_offset_us64
7282 (PTS_TYPE_VIDEO, stream_offset, &vf->pts,
7283 &frame_size, 0,
7284 &vf->pts_us64) != 0) {
7285#ifdef DEBUG_PTS
7286 pbi->pts_missed++;
7287#endif
7288 vf->pts = 0;
7289 vf->pts_us64 = 0;
7290 pts_valid = 0;
7291 pts_us64_valid = 0;
7292 } else {
7293#ifdef DEBUG_PTS
7294 pbi->pts_hit++;
7295#endif
7296 pts_valid = 1;
7297 pts_us64_valid = 1;
7298 }
7299
7300 fill_frame_info(pbi, pic_config, frame_size, vf->pts);
7301
7302 pts_save = vf->pts;
7303 pts_us64_save = vf->pts_us64;
7304 if (pbi->pts_unstable) {
7305 frame_duration_adapt(pbi, vf, pts_valid);
7306 if (pbi->duration_from_pts_done) {
7307 pbi->pts_mode = PTS_NONE_REF_USE_DURATION;
7308 } else {
7309 if (pts_valid || pts_us64_valid)
7310 pbi->pts_mode = PTS_NORMAL;
7311 }
7312 }
7313
7314 if ((pbi->pts_mode == PTS_NORMAL) && (vf->pts != 0)
7315 && pbi->get_frame_dur) {
7316 int pts_diff = (int)vf->pts - pbi->last_lookup_pts;
7317
7318 if (pts_diff < 0) {
7319 pbi->pts_mode_switching_count++;
7320 pbi->pts_mode_recovery_count = 0;
7321
7322 if (pbi->pts_mode_switching_count >=
7323 PTS_MODE_SWITCHING_THRESHOLD) {
7324 pbi->pts_mode =
7325 PTS_NONE_REF_USE_DURATION;
7326 pr_info
7327 ("HEVC: switch to n_d mode.\n");
7328 }
7329
7330 } else {
7331 int p = PTS_MODE_SWITCHING_RECOVERY_THREASHOLD;
7332
7333 pbi->pts_mode_recovery_count++;
7334 if (pbi->pts_mode_recovery_count > p) {
7335 pbi->pts_mode_switching_count = 0;
7336 pbi->pts_mode_recovery_count = 0;
7337 }
7338 }
7339 }
7340
7341 if (vf->pts != 0)
7342 pbi->last_lookup_pts = vf->pts;
7343
7344 if ((pbi->pts_mode == PTS_NONE_REF_USE_DURATION)
7345 && (slice_type != KEY_FRAME))
7346 vf->pts = pbi->last_pts + DUR2PTS(pbi->frame_dur);
7347 pbi->last_pts = vf->pts;
7348
7349 if (vf->pts_us64 != 0)
7350 pbi->last_lookup_pts_us64 = vf->pts_us64;
7351
7352 if ((pbi->pts_mode == PTS_NONE_REF_USE_DURATION)
7353 && (slice_type != KEY_FRAME)) {
7354 vf->pts_us64 =
7355 pbi->last_pts_us64 +
7356 (DUR2PTS(pbi->frame_dur) * 100 / 9);
7357 }
7358 pbi->last_pts_us64 = vf->pts_us64;
7359 if ((debug & VP9_DEBUG_OUT_PTS) != 0) {
7360 pr_info
7361 ("VP9 dec out pts: pts_mode=%d,dur=%d,pts(%d,%lld)(%d,%lld)\n",
7362 pbi->pts_mode, pbi->frame_dur, vf->pts,
7363 vf->pts_us64, pts_save, pts_us64_save);
7364 }
7365
7366 if (pbi->pts_mode == PTS_NONE_REF_USE_DURATION) {
7367 vf->disp_pts = vf->pts;
7368 vf->disp_pts_us64 = vf->pts_us64;
7369 vf->pts = pts_save;
7370 vf->pts_us64 = pts_us64_save;
7371 } else {
7372 vf->disp_pts = 0;
7373 vf->disp_pts_us64 = 0;
7374 }
7375
7376 vf->index = 0xff00 | pic_config->index;
7377
7378 if (pic_config->double_write_mode & 0x10) {
7379 /* double write only */
7380 vf->compBodyAddr = 0;
7381 vf->compHeadAddr = 0;
7382 } else {
7383 if (pbi->mmu_enable) {
7384 vf->compBodyAddr = 0;
7385 vf->compHeadAddr = pic_config->header_adr;
7386 } else {
7387 /*vf->compBodyAddr = pic_config->mc_y_adr;
7388 *vf->compHeadAddr = pic_config->mc_y_adr +
7389 *pic_config->comp_body_size; */
7390 /*head adr*/
7391 }
7392 vf->canvas0Addr = vf->canvas1Addr = 0;
7393 }
7394 if (pic_config->double_write_mode) {
7395 vf->type = VIDTYPE_PROGRESSIVE |
7396 VIDTYPE_VIU_FIELD;
7397 vf->type |= nv_order;
7398 if ((pic_config->double_write_mode == 3) &&
7399 (!IS_8K_SIZE(pic_config->y_crop_width,
7400 pic_config->y_crop_height))) {
7401 vf->type |= VIDTYPE_COMPRESS;
7402 if (pbi->mmu_enable)
7403 vf->type |= VIDTYPE_SCATTER;
7404 }
7405#ifdef MULTI_INSTANCE_SUPPORT
7406 if (pbi->m_ins_flag) {
7407 vf->canvas0Addr = vf->canvas1Addr = -1;
7408 vf->plane_num = 2;
7409 vf->canvas0_config[0] =
7410 pic_config->canvas_config[0];
7411 vf->canvas0_config[1] =
7412 pic_config->canvas_config[1];
7413 vf->canvas1_config[0] =
7414 pic_config->canvas_config[0];
7415 vf->canvas1_config[1] =
7416 pic_config->canvas_config[1];
7417
7418 } else
7419#endif
7420 vf->canvas0Addr = vf->canvas1Addr =
7421 spec2canvas(pic_config);
7422 } else {
7423 vf->canvas0Addr = vf->canvas1Addr = 0;
7424 vf->type = VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
7425 if (pbi->mmu_enable)
7426 vf->type |= VIDTYPE_SCATTER;
7427 }
7428
7429 switch (pic_config->bit_depth) {
7430 case VPX_BITS_8:
7431 vf->bitdepth = BITDEPTH_Y8 |
7432 BITDEPTH_U8 | BITDEPTH_V8;
7433 break;
7434 case VPX_BITS_10:
7435 case VPX_BITS_12:
7436 vf->bitdepth = BITDEPTH_Y10 |
7437 BITDEPTH_U10 | BITDEPTH_V10;
7438 break;
7439 default:
7440 vf->bitdepth = BITDEPTH_Y10 |
7441 BITDEPTH_U10 | BITDEPTH_V10;
7442 break;
7443 }
7444 if ((vf->type & VIDTYPE_COMPRESS) == 0)
7445 vf->bitdepth =
7446 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
7447 if (pic_config->bit_depth == VPX_BITS_8)
7448 vf->bitdepth |= BITDEPTH_SAVING_MODE;
7449
7450 /* if((vf->width!=pic_config->width)|
7451 * (vf->height!=pic_config->height))
7452 */
7453 /* pr_info("aaa: %d/%d, %d/%d\n",
7454 vf->width,vf->height, pic_config->width,
7455 pic_config->height); */
7456 vf->width = pic_config->y_crop_width /
7457 get_double_write_ratio(pbi,
7458 pic_config->double_write_mode);
7459 vf->height = pic_config->y_crop_height /
7460 get_double_write_ratio(pbi,
7461 pic_config->double_write_mode);
7462 if (force_w_h != 0) {
7463 vf->width = (force_w_h >> 16) & 0xffff;
7464 vf->height = force_w_h & 0xffff;
7465 }
7466 vf->compWidth = pic_config->y_crop_width;
7467 vf->compHeight = pic_config->y_crop_height;
7468 set_frame_info(pbi, vf);
7469 if (force_fps & 0x100) {
7470 u32 rate = force_fps & 0xff;
7471
7472 if (rate)
7473 vf->duration = 96000/rate;
7474 else
7475 vf->duration = 0;
7476 }
7477 update_vf_memhandle(pbi, vf, pic_config);
7478
7479 if (!(pic_config->y_crop_width == 196
7480 && pic_config->y_crop_height == 196
7481 && (debug & VP9_DEBUG_NO_TRIGGER_FRAME) == 0
7482 && (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX))) {
7483 struct vdec_info tmp4x;
7484
7485 inc_vf_ref(pbi, pic_config->index);
7486 decoder_do_frame_check(pvdec, vf);
7487 kfifo_put(&pbi->display_q, (const struct vframe_s *)vf);
7488 ATRACE_COUNTER(MODULE_NAME, vf->pts);
7489 pbi->vf_pre_count++;
7490 pbi_update_gvs(pbi);
7491 /*count info*/
7492 vdec_count_info(pbi->gvs, 0, stream_offset);
7493 memcpy(&tmp4x, pbi->gvs, sizeof(struct vdec_info));
7494 tmp4x.bit_depth_luma = pbi->vp9_param.p.bit_depth;
7495 tmp4x.bit_depth_chroma = pbi->vp9_param.p.bit_depth;
7496 tmp4x.double_write_mode = get_double_write_mode(pbi);
7497 vdec_fill_vdec_frame(pvdec, &pbi->vframe_qos, &tmp4x,
7498 vf, pic_config->hw_decode_time);
7499 pvdec->vdec_fps_detec(pvdec->id);
7500 if (without_display_mode == 0) {
7501 vf_notify_receiver(pbi->provider_name,
7502 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
7503 } else
7504 vvp9_vf_put(vvp9_vf_get(pbi), pbi);
7505 } else {
7506 pbi->stat |= VP9_TRIGGER_FRAME_DONE;
7507 hevc_source_changed(VFORMAT_VP9, 196, 196, 30);
7508 pr_debug("[%s %d] drop trigger frame width %d height %d state 0x%x\n",
7509 __func__, __LINE__, vf->width,
7510 vf->height, pbi->stat);
7511 }
7512 }
7513
7514 return 0;
7515}
7516
7517static int notify_v4l_eos(struct vdec_s *vdec)
7518{
7519 struct VP9Decoder_s *hw = (struct VP9Decoder_s *)vdec->private;
7520 struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
7521 struct vframe_s *vf = &hw->vframe_dummy;
7522 struct vdec_v4l2_buffer *fb = NULL;
7523 int index = INVALID_IDX;
7524 ulong expires;
7525
7526 if (hw->eos) {
7527 if (hw->is_used_v4l) {
7528 expires = jiffies + msecs_to_jiffies(2000);
7529 while (INVALID_IDX == (index = v4l_get_free_fb(hw))) {
7530 if (time_after(jiffies, expires) ||
7531 v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx))
7532 break;
7533 }
7534
7535 if (index == INVALID_IDX) {
7536 if (vdec_v4l_get_buffer(hw->v4l2_ctx, &fb) < 0) {
7537 pr_err("[%d] EOS get free buff fail.\n", ctx->id);
7538 return -1;
7539 }
7540 }
7541 }
7542
7543 vf->type |= VIDTYPE_V4L_EOS;
7544 vf->timestamp = ULONG_MAX;
7545 vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L;
7546 vf->v4l_mem_handle = (index == INVALID_IDX) ? (ulong)fb :
7547 hw->m_BUF[index].v4l_ref_buf_addr;
7548
7549 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
7550 vf_notify_receiver(vdec->vf_provider_name,
7551 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
7552
7553 pr_info("[%d] VP9 EOS notify.\n", (hw->is_used_v4l)?ctx->id:vdec->id);
7554 }
7555
7556 return 0;
7557}
7558
7559static void get_rpm_param(union param_u *params)
7560{
7561 int i;
7562 unsigned int data32;
7563
7564 if (debug & VP9_DEBUG_BUFMGR)
7565 pr_info("enter %s\r\n", __func__);
7566 for (i = 0; i < 128; i++) {
7567 do {
7568 data32 = READ_VREG(RPM_CMD_REG);
7569 /*pr_info("%x\n", data32);*/
7570 } while ((data32 & 0x10000) == 0);
7571 params->l.data[i] = data32&0xffff;
7572 /*pr_info("%x\n", data32);*/
7573 WRITE_VREG(RPM_CMD_REG, 0);
7574 }
7575 if (debug & VP9_DEBUG_BUFMGR)
7576 pr_info("leave %s\r\n", __func__);
7577}
7578static void debug_buffer_mgr_more(struct VP9Decoder_s *pbi)
7579{
7580 int i;
7581
7582 if (!(debug & VP9_DEBUG_BUFMGR_MORE))
7583 return;
7584 pr_info("vp9_param: (%d)\n", pbi->slice_idx);
7585 for (i = 0; i < (RPM_END-RPM_BEGIN); i++) {
7586 pr_info("%04x ", pbi->vp9_param.l.data[i]);
7587 if (((i + 1) & 0xf) == 0)
7588 pr_info("\n");
7589 }
7590 pr_info("=============param==========\r\n");
7591 pr_info("profile %x\r\n", pbi->vp9_param.p.profile);
7592 pr_info("show_existing_frame %x\r\n",
7593 pbi->vp9_param.p.show_existing_frame);
7594 pr_info("frame_to_show_idx %x\r\n",
7595 pbi->vp9_param.p.frame_to_show_idx);
7596 pr_info("frame_type %x\r\n", pbi->vp9_param.p.frame_type);
7597 pr_info("show_frame %x\r\n", pbi->vp9_param.p.show_frame);
7598 pr_info("e.r.r.o.r_resilient_mode %x\r\n",
7599 pbi->vp9_param.p.error_resilient_mode);
7600 pr_info("intra_only %x\r\n", pbi->vp9_param.p.intra_only);
7601 pr_info("display_size_present %x\r\n",
7602 pbi->vp9_param.p.display_size_present);
7603 pr_info("reset_frame_context %x\r\n",
7604 pbi->vp9_param.p.reset_frame_context);
7605 pr_info("refresh_frame_flags %x\r\n",
7606 pbi->vp9_param.p.refresh_frame_flags);
7607 pr_info("bit_depth %x\r\n", pbi->vp9_param.p.bit_depth);
7608 pr_info("width %x\r\n", pbi->vp9_param.p.width);
7609 pr_info("height %x\r\n", pbi->vp9_param.p.height);
7610 pr_info("display_width %x\r\n", pbi->vp9_param.p.display_width);
7611 pr_info("display_height %x\r\n", pbi->vp9_param.p.display_height);
7612 pr_info("ref_info %x\r\n", pbi->vp9_param.p.ref_info);
7613 pr_info("same_frame_size %x\r\n", pbi->vp9_param.p.same_frame_size);
7614 if (!(debug & VP9_DEBUG_DBG_LF_PRINT))
7615 return;
7616 pr_info("mode_ref_delta_enabled: 0x%x\r\n",
7617 pbi->vp9_param.p.mode_ref_delta_enabled);
7618 pr_info("sharpness_level: 0x%x\r\n",
7619 pbi->vp9_param.p.sharpness_level);
7620 pr_info("ref_deltas: 0x%x, 0x%x, 0x%x, 0x%x\r\n",
7621 pbi->vp9_param.p.ref_deltas[0], pbi->vp9_param.p.ref_deltas[1],
7622 pbi->vp9_param.p.ref_deltas[2], pbi->vp9_param.p.ref_deltas[3]);
7623 pr_info("mode_deltas: 0x%x, 0x%x\r\n", pbi->vp9_param.p.mode_deltas[0],
7624 pbi->vp9_param.p.mode_deltas[1]);
7625 pr_info("filter_level: 0x%x\r\n", pbi->vp9_param.p.filter_level);
7626 pr_info("seg_enabled: 0x%x\r\n", pbi->vp9_param.p.seg_enabled);
7627 pr_info("seg_abs_delta: 0x%x\r\n", pbi->vp9_param.p.seg_abs_delta);
7628 pr_info("seg_lf_feature_enabled: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\r\n",
7629 (pbi->vp9_param.p.seg_lf_info[0]>>15 & 1),
7630 (pbi->vp9_param.p.seg_lf_info[1]>>15 & 1),
7631 (pbi->vp9_param.p.seg_lf_info[2]>>15 & 1),
7632 (pbi->vp9_param.p.seg_lf_info[3]>>15 & 1),
7633 (pbi->vp9_param.p.seg_lf_info[4]>>15 & 1),
7634 (pbi->vp9_param.p.seg_lf_info[5]>>15 & 1),
7635 (pbi->vp9_param.p.seg_lf_info[6]>>15 & 1),
7636 (pbi->vp9_param.p.seg_lf_info[7]>>15 & 1));
7637 pr_info("seg_lf_feature_data: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\r\n",
7638 (pbi->vp9_param.p.seg_lf_info[0] & 0x13f),
7639 (pbi->vp9_param.p.seg_lf_info[1] & 0x13f),
7640 (pbi->vp9_param.p.seg_lf_info[2] & 0x13f),
7641 (pbi->vp9_param.p.seg_lf_info[3] & 0x13f),
7642 (pbi->vp9_param.p.seg_lf_info[4] & 0x13f),
7643 (pbi->vp9_param.p.seg_lf_info[5] & 0x13f),
7644 (pbi->vp9_param.p.seg_lf_info[6] & 0x13f),
7645 (pbi->vp9_param.p.seg_lf_info[7] & 0x13f));
7646
7647}
7648
7649
7650static void vp9_recycle_mmu_buf_tail(struct VP9Decoder_s *pbi)
7651{
7652 struct VP9_Common_s *const cm = &pbi->common;
7653 if (pbi->double_write_mode & 0x10)
7654 return;
7655 if (cm->cur_fb_idx_mmu != INVALID_IDX) {
7656 if (pbi->used_4k_num == -1) {
7657 pbi->used_4k_num =
7658 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
7659 if (pbi->m_ins_flag)
7660 hevc_mmu_dma_check(hw_to_vdec(pbi));
7661 }
7662 decoder_mmu_box_free_idx_tail(pbi->mmu_box,
7663 cm->cur_fb_idx_mmu, pbi->used_4k_num);
7664 cm->cur_fb_idx_mmu = INVALID_IDX;
7665 pbi->used_4k_num = -1;
7666 }
7667}
7668
7669#ifdef MULTI_INSTANCE_SUPPORT
7670static void vp9_recycle_mmu_buf(struct VP9Decoder_s *pbi)
7671{
7672 struct VP9_Common_s *const cm = &pbi->common;
7673 if (pbi->double_write_mode & 0x10)
7674 return;
7675 if (cm->cur_fb_idx_mmu != INVALID_IDX) {
7676 decoder_mmu_box_free_idx(pbi->mmu_box,
7677 cm->cur_fb_idx_mmu);
7678
7679 cm->cur_fb_idx_mmu = INVALID_IDX;
7680 pbi->used_4k_num = -1;
7681 }
7682}
7683
7684void vp9_recycle_mmu_work(struct work_struct *work)
7685{
7686 struct VP9Decoder_s *pbi = container_of(work,
7687 struct VP9Decoder_s, recycle_mmu_work);
7688
7689 vp9_recycle_mmu_buf(pbi);
7690}
7691#endif
7692
7693
7694static void dec_again_process(struct VP9Decoder_s *pbi)
7695{
7696 amhevc_stop();
7697 pbi->dec_result = DEC_RESULT_AGAIN;
7698 if (pbi->process_state ==
7699 PROC_STATE_DECODESLICE) {
7700 pbi->process_state =
7701 PROC_STATE_SENDAGAIN;
7702 if (pbi->mmu_enable) {
7703 /*
7704 * Because vp9_recycle_mmu_buf has sleep function,we can't
7705 * call it directly. Use a recycle_mmu_work to substitude it.
7706 */
7707 vdec_schedule_work(&pbi->recycle_mmu_work);
7708 }
7709 }
7710 reset_process_time(pbi);
7711 vdec_schedule_work(&pbi->work);
7712}
7713
7714int continue_decoding(struct VP9Decoder_s *pbi)
7715{
7716 int ret;
7717 int i;
7718 struct VP9_Common_s *const cm = &pbi->common;
7719 struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
7720 debug_buffer_mgr_more(pbi);
7721
7722 if (pbi->is_used_v4l && ctx->param_sets_from_ucode)
7723 pbi->res_ch_flag = 0;
7724 bit_depth_luma = pbi->vp9_param.p.bit_depth;
7725 bit_depth_chroma = pbi->vp9_param.p.bit_depth;
7726
7727 if ((pbi->vp9_param.p.bit_depth >= VPX_BITS_10) &&
7728 (get_double_write_mode(pbi) == 0x10)) {
7729 pbi->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
7730 pr_err("fatal err, bit_depth %d, unsupport dw 0x10\n",
7731 pbi->vp9_param.p.bit_depth);
7732 return -1;
7733 }
7734
7735 if (pbi->process_state != PROC_STATE_SENDAGAIN) {
7736 ret = vp9_bufmgr_process(pbi, &pbi->vp9_param);
7737 if (!pbi->m_ins_flag)
7738 pbi->slice_idx++;
7739 } else {
7740 union param_u *params = &pbi->vp9_param;
7741 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
7742 ret = vp9_alloc_mmu(pbi,
7743 cm->new_fb_idx,
7744 params->p.width,
7745 params->p.height,
7746 params->p.bit_depth,
7747 pbi->frame_mmu_map_addr);
7748 if (ret >= 0)
7749 cm->cur_fb_idx_mmu = cm->new_fb_idx;
7750 else
7751 pr_err("can't alloc need mmu1,idx %d ret =%d\n",
7752 cm->new_fb_idx,
7753 ret);
7754 } else {
7755 ret = 0;
7756 }
7757 WRITE_VREG(HEVC_PARSER_PICTURE_SIZE,
7758 (params->p.height << 16) | params->p.width);
7759 }
7760 if (ret < 0) {
7761 pr_info("vp9_bufmgr_process=> %d, VP9_10B_DISCARD_NAL\r\n",
7762 ret);
7763 WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DISCARD_NAL);
7764 cm->show_frame = 0;
7765 if (pbi->mmu_enable)
7766 vp9_recycle_mmu_buf(pbi);
7767#ifdef MULTI_INSTANCE_SUPPORT
7768 if (pbi->m_ins_flag) {
7769 pbi->dec_result = DEC_RESULT_DONE;
7770#ifdef SUPPORT_FB_DECODING
7771 if (pbi->used_stage_buf_num == 0)
7772#endif
7773 amhevc_stop();
7774 vdec_schedule_work(&pbi->work);
7775 }
7776#endif
7777 return ret;
7778 } else if (ret == 0) {
7779 struct PIC_BUFFER_CONFIG_s *cur_pic_config
7780 = &cm->cur_frame->buf;
7781 cur_pic_config->decode_idx = pbi->frame_count;
7782
7783 if (pbi->process_state != PROC_STATE_SENDAGAIN) {
7784 if (!pbi->m_ins_flag) {
7785 pbi->frame_count++;
7786 decode_frame_count[pbi->index]
7787 = pbi->frame_count;
7788 }
7789#ifdef MULTI_INSTANCE_SUPPORT
7790 if (pbi->chunk) {
7791 cur_pic_config->pts = pbi->chunk->pts;
7792 cur_pic_config->pts64 = pbi->chunk->pts64;
7793 cur_pic_config->timestamp = pbi->chunk->timestamp;
7794 }
7795#endif
7796 }
7797 /*pr_info("Decode Frame Data %d\n", pbi->frame_count);*/
7798 config_pic_size(pbi, pbi->vp9_param.p.bit_depth);
7799
7800 if ((pbi->common.frame_type != KEY_FRAME)
7801 && (!pbi->common.intra_only)) {
7802 config_mc_buffer(pbi, pbi->vp9_param.p.bit_depth);
7803#ifdef SUPPORT_FB_DECODING
7804 if (pbi->used_stage_buf_num == 0)
7805#endif
7806 config_mpred_hw(pbi);
7807 } else {
7808#ifdef SUPPORT_FB_DECODING
7809 if (pbi->used_stage_buf_num == 0)
7810#endif
7811 clear_mpred_hw(pbi);
7812 }
7813#ifdef MCRCC_ENABLE
7814 if (mcrcc_cache_alg_flag)
7815 config_mcrcc_axi_hw_new(pbi);
7816 else
7817 config_mcrcc_axi_hw(pbi);
7818#endif
7819 config_sao_hw(pbi, &pbi->vp9_param);
7820
7821#ifdef VP9_LPF_LVL_UPDATE
7822 /*
7823 * Get loop filter related picture level parameters from Parser
7824 */
7825 pbi->lf->mode_ref_delta_enabled = pbi->vp9_param.p.mode_ref_delta_enabled;
7826 pbi->lf->sharpness_level = pbi->vp9_param.p.sharpness_level;
7827 for (i = 0; i < 4; i++)
7828 pbi->lf->ref_deltas[i] = pbi->vp9_param.p.ref_deltas[i];
7829 for (i = 0; i < 2; i++)
7830 pbi->lf->mode_deltas[i] = pbi->vp9_param.p.mode_deltas[i];
7831 pbi->default_filt_lvl = pbi->vp9_param.p.filter_level;
7832 pbi->seg_4lf->enabled = pbi->vp9_param.p.seg_enabled;
7833 pbi->seg_4lf->abs_delta = pbi->vp9_param.p.seg_abs_delta;
7834 for (i = 0; i < MAX_SEGMENTS; i++)
7835 pbi->seg_4lf->feature_mask[i] = (pbi->vp9_param.p.seg_lf_info[i] &
7836 0x8000) ? (1 << SEG_LVL_ALT_LF) : 0;
7837 for (i = 0; i < MAX_SEGMENTS; i++)
7838 pbi->seg_4lf->feature_data[i][SEG_LVL_ALT_LF]
7839 = (pbi->vp9_param.p.seg_lf_info[i]
7840 & 0x100) ? -(pbi->vp9_param.p.seg_lf_info[i]
7841 & 0x3f) : (pbi->vp9_param.p.seg_lf_info[i] & 0x3f);
7842 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
7843 /*Set pipeline mode*/
7844 uint32_t lpf_data32 = READ_VREG(HEVC_DBLK_CFGB);
7845 /*dblk pipeline mode=1 for performance*/
7846 if (pbi->vp9_param.p.width >= 1280)
7847 lpf_data32 |= (0x1 << 4);
7848 else
7849 lpf_data32 &= ~(0x3 << 4);
7850 WRITE_VREG(HEVC_DBLK_CFGB, lpf_data32);
7851 }
7852 /*
7853 * Update loop filter Thr/Lvl table for every frame
7854 */
7855 /*pr_info
7856 ("vp9_loop_filter (run before every frame decoding start)\n");*/
7857 vp9_loop_filter_frame_init(pbi->seg_4lf,
7858 pbi->lfi, pbi->lf, pbi->default_filt_lvl);
7859#endif
7860 /*pr_info("HEVC_DEC_STATUS_REG <= VP9_10B_DECODE_SLICE\n");*/
7861 WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DECODE_SLICE);
7862 } else {
7863 pr_info("Skip search next start code\n");
7864 cm->prev_fb_idx = INVALID_IDX;
7865 /*skip, search next start code*/
7866 WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DECODE_SLICE);
7867 }
7868 pbi->process_state = PROC_STATE_DECODESLICE;
7869 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
7870 if (pbi->last_put_idx < pbi->used_buf_num) {
7871 struct RefCntBuffer_s *frame_bufs =
7872 cm->buffer_pool->frame_bufs;
7873 int i = pbi->last_put_idx;
7874 /*free not used buffers.*/
7875 if ((frame_bufs[i].ref_count == 0) &&
7876 (frame_bufs[i].buf.vf_ref == 0) &&
7877 (frame_bufs[i].buf.index != -1)) {
7878 decoder_mmu_box_free_idx(pbi->mmu_box, i);
7879 }
7880 pbi->last_put_idx = -1;
7881 }
7882 }
7883 return ret;
7884}
7885
7886static void fill_frame_info(struct VP9Decoder_s *pbi,
7887 struct PIC_BUFFER_CONFIG_s *frame,
7888 unsigned int framesize,
7889 unsigned int pts)
7890{
7891 struct vframe_qos_s *vframe_qos = &pbi->vframe_qos;
7892
7893 if (frame->slice_type == KEY_FRAME)
7894 vframe_qos->type = 1;
7895 else if (frame->slice_type == INTER_FRAME)
7896 vframe_qos->type = 2;
7897/*
7898#define SHOW_QOS_INFO
7899*/
7900 if (input_frame_based(hw_to_vdec(pbi)))
7901 vframe_qos->size = frame->frame_size2;
7902 else
7903 vframe_qos->size = framesize;
7904 vframe_qos->pts = pts;
7905#ifdef SHOW_QOS_INFO
7906 vp9_print(pbi, 0, "slice:%d\n", frame->slice_type);
7907#endif
7908 vframe_qos->max_mv = frame->max_mv;
7909 vframe_qos->avg_mv = frame->avg_mv;
7910 vframe_qos->min_mv = frame->min_mv;
7911#ifdef SHOW_QOS_INFO
7912 vp9_print(pbi, 0, "mv: max:%d, avg:%d, min:%d\n",
7913 vframe_qos->max_mv,
7914 vframe_qos->avg_mv,
7915 vframe_qos->min_mv);
7916#endif
7917 vframe_qos->max_qp = frame->max_qp;
7918 vframe_qos->avg_qp = frame->avg_qp;
7919 vframe_qos->min_qp = frame->min_qp;
7920#ifdef SHOW_QOS_INFO
7921 vp9_print(pbi, 0, "qp: max:%d, avg:%d, min:%d\n",
7922 vframe_qos->max_qp,
7923 vframe_qos->avg_qp,
7924 vframe_qos->min_qp);
7925#endif
7926 vframe_qos->max_skip = frame->max_skip;
7927 vframe_qos->avg_skip = frame->avg_skip;
7928 vframe_qos->min_skip = frame->min_skip;
7929#ifdef SHOW_QOS_INFO
7930 vp9_print(pbi, 0, "skip: max:%d, avg:%d, min:%d\n",
7931 vframe_qos->max_skip,
7932 vframe_qos->avg_skip,
7933 vframe_qos->min_skip);
7934#endif
7935 vframe_qos->num++;
7936}
7937
7938/* only when we decoded one field or one frame,
7939we can call this function to get qos info*/
7940static void get_picture_qos_info(struct VP9Decoder_s *pbi)
7941{
7942 struct PIC_BUFFER_CONFIG_s *frame = &pbi->cur_buf->buf;
7943 struct vdec_s *vdec = hw_to_vdec(pbi);
7944
7945 if (!frame)
7946 return;
7947 if (vdec->mvfrm) {
7948 frame->frame_size2 = vdec->mvfrm->frame_size;
7949 frame->hw_decode_time =
7950 local_clock() - vdec->mvfrm->hw_decode_start;
7951 }
7952
7953 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
7954 unsigned char a[3];
7955 unsigned char i, j, t;
7956 unsigned long data;
7957
7958 data = READ_VREG(HEVC_MV_INFO);
7959 if (frame->slice_type == KEY_FRAME)
7960 data = 0;
7961 a[0] = data & 0xff;
7962 a[1] = (data >> 8) & 0xff;
7963 a[2] = (data >> 16) & 0xff;
7964
7965 for (i = 0; i < 3; i++) {
7966 for (j = i+1; j < 3; j++) {
7967 if (a[j] < a[i]) {
7968 t = a[j];
7969 a[j] = a[i];
7970 a[i] = t;
7971 } else if (a[j] == a[i]) {
7972 a[i]++;
7973 t = a[j];
7974 a[j] = a[i];
7975 a[i] = t;
7976 }
7977 }
7978 }
7979 frame->max_mv = a[2];
7980 frame->avg_mv = a[1];
7981 frame->min_mv = a[0];
7982
7983 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7984 "mv data %x a[0]= %x a[1]= %x a[2]= %x\n",
7985 data, a[0], a[1], a[2]);
7986
7987 data = READ_VREG(HEVC_QP_INFO);
7988 a[0] = data & 0x1f;
7989 a[1] = (data >> 8) & 0x3f;
7990 a[2] = (data >> 16) & 0x7f;
7991
7992 for (i = 0; i < 3; i++) {
7993 for (j = i+1; j < 3; j++) {
7994 if (a[j] < a[i]) {
7995 t = a[j];
7996 a[j] = a[i];
7997 a[i] = t;
7998 } else if (a[j] == a[i]) {
7999 a[i]++;
8000 t = a[j];
8001 a[j] = a[i];
8002 a[i] = t;
8003 }
8004 }
8005 }
8006 frame->max_qp = a[2];
8007 frame->avg_qp = a[1];
8008 frame->min_qp = a[0];
8009
8010 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8011 "qp data %x a[0]= %x a[1]= %x a[2]= %x\n",
8012 data, a[0], a[1], a[2]);
8013
8014 data = READ_VREG(HEVC_SKIP_INFO);
8015 a[0] = data & 0x1f;
8016 a[1] = (data >> 8) & 0x3f;
8017 a[2] = (data >> 16) & 0x7f;
8018
8019 for (i = 0; i < 3; i++) {
8020 for (j = i+1; j < 3; j++) {
8021 if (a[j] < a[i]) {
8022 t = a[j];
8023 a[j] = a[i];
8024 a[i] = t;
8025 } else if (a[j] == a[i]) {
8026 a[i]++;
8027 t = a[j];
8028 a[j] = a[i];
8029 a[i] = t;
8030 }
8031 }
8032 }
8033 frame->max_skip = a[2];
8034 frame->avg_skip = a[1];
8035 frame->min_skip = a[0];
8036
8037 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8038 "skip data %x a[0]= %x a[1]= %x a[2]= %x\n",
8039 data, a[0], a[1], a[2]);
8040 } else {
8041 uint32_t blk88_y_count;
8042 uint32_t blk88_c_count;
8043 uint32_t blk22_mv_count;
8044 uint32_t rdata32;
8045 int32_t mv_hi;
8046 int32_t mv_lo;
8047 uint32_t rdata32_l;
8048 uint32_t mvx_L0_hi;
8049 uint32_t mvy_L0_hi;
8050 uint32_t mvx_L1_hi;
8051 uint32_t mvy_L1_hi;
8052 int64_t value;
8053 uint64_t temp_value;
8054 int pic_number = frame->decode_idx;
8055
8056 frame->max_mv = 0;
8057 frame->avg_mv = 0;
8058 frame->min_mv = 0;
8059
8060 frame->max_skip = 0;
8061 frame->avg_skip = 0;
8062 frame->min_skip = 0;
8063
8064 frame->max_qp = 0;
8065 frame->avg_qp = 0;
8066 frame->min_qp = 0;
8067
8068 vp9_print(pbi, VP9_DEBUG_QOS_INFO, "slice_type:%d, poc:%d\n",
8069 frame->slice_type,
8070 pic_number);
8071
8072 /* set rd_idx to 0 */
8073 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, 0);
8074
8075 blk88_y_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
8076 if (blk88_y_count == 0) {
8077
8078 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8079 "[Picture %d Quality] NO Data yet.\n",
8080 pic_number);
8081
8082 /* reset all counts */
8083 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
8084 return;
8085 }
8086 /* qp_y_sum */
8087 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8088
8089 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8090 "[Picture %d Quality] Y QP AVG : %d (%d/%d)\n",
8091 pic_number, rdata32/blk88_y_count,
8092 rdata32, blk88_y_count);
8093
8094 frame->avg_qp = rdata32/blk88_y_count;
8095 /* intra_y_count */
8096 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8097
8098 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8099 "[Picture %d Quality] Y intra rate : %d%c (%d)\n",
8100 pic_number, rdata32*100/blk88_y_count,
8101 '%', rdata32);
8102
8103 /* skipped_y_count */
8104 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8105
8106 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8107 "[Picture %d Quality] Y skipped rate : %d%c (%d)\n",
8108 pic_number, rdata32*100/blk88_y_count,
8109 '%', rdata32);
8110
8111 frame->avg_skip = rdata32*100/blk88_y_count;
8112 /* coeff_non_zero_y_count */
8113 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8114
8115 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8116 "[Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n",
8117 pic_number, (100 - rdata32*100/(blk88_y_count*1)),
8118 '%', rdata32);
8119
8120 /* blk66_c_count */
8121 blk88_c_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
8122 if (blk88_c_count == 0) {
8123 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8124 "[Picture %d Quality] NO Data yet.\n",
8125 pic_number);
8126 /* reset all counts */
8127 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
8128 return;
8129 }
8130 /* qp_c_sum */
8131 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8132
8133 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8134 "[Picture %d Quality] C QP AVG : %d (%d/%d)\n",
8135 pic_number, rdata32/blk88_c_count,
8136 rdata32, blk88_c_count);
8137
8138 /* intra_c_count */
8139 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8140
8141 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8142 "[Picture %d Quality] C intra rate : %d%c (%d)\n",
8143 pic_number, rdata32*100/blk88_c_count,
8144 '%', rdata32);
8145
8146 /* skipped_cu_c_count */
8147 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8148
8149 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8150 "[Picture %d Quality] C skipped rate : %d%c (%d)\n",
8151 pic_number, rdata32*100/blk88_c_count,
8152 '%', rdata32);
8153
8154 /* coeff_non_zero_c_count */
8155 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8156
8157 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8158 "[Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n",
8159 pic_number, (100 - rdata32*100/(blk88_c_count*1)),
8160 '%', rdata32);
8161
8162 /* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0],
8163 1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */
8164 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8165
8166 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8167 "[Picture %d Quality] Y QP min : %d\n",
8168 pic_number, (rdata32>>0)&0xff);
8169
8170 frame->min_qp = (rdata32>>0)&0xff;
8171
8172 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8173 "[Picture %d Quality] Y QP max : %d\n",
8174 pic_number, (rdata32>>8)&0xff);
8175
8176 frame->max_qp = (rdata32>>8)&0xff;
8177
8178 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8179 "[Picture %d Quality] C QP min : %d\n",
8180 pic_number, (rdata32>>16)&0xff);
8181 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8182 "[Picture %d Quality] C QP max : %d\n",
8183 pic_number, (rdata32>>24)&0xff);
8184
8185 /* blk22_mv_count */
8186 blk22_mv_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
8187 if (blk22_mv_count == 0) {
8188 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8189 "[Picture %d Quality] NO MV Data yet.\n",
8190 pic_number);
8191 /* reset all counts */
8192 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
8193 return;
8194 }
8195 /* mvy_L1_count[39:32], mvx_L1_count[39:32],
8196 mvy_L0_count[39:32], mvx_L0_count[39:32] */
8197 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8198 /* should all be 0x00 or 0xff */
8199 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8200 "[Picture %d Quality] MV AVG High Bits: 0x%X\n",
8201 pic_number, rdata32);
8202
8203 mvx_L0_hi = ((rdata32>>0)&0xff);
8204 mvy_L0_hi = ((rdata32>>8)&0xff);
8205 mvx_L1_hi = ((rdata32>>16)&0xff);
8206 mvy_L1_hi = ((rdata32>>24)&0xff);
8207
8208 /* mvx_L0_count[31:0] */
8209 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
8210 temp_value = mvx_L0_hi;
8211 temp_value = (temp_value << 32) | rdata32_l;
8212
8213 if (mvx_L0_hi & 0x80)
8214 value = 0xFFFFFFF000000000 | temp_value;
8215 else
8216 value = temp_value;
8217
8218 value = div_s64(value, blk22_mv_count);
8219
8220 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8221 "[Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n",
8222 pic_number, (int)value,
8223 value, blk22_mv_count);
8224
8225 frame->avg_mv = value;
8226
8227 /* mvy_L0_count[31:0] */
8228 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
8229 temp_value = mvy_L0_hi;
8230 temp_value = (temp_value << 32) | rdata32_l;
8231
8232 if (mvy_L0_hi & 0x80)
8233 value = 0xFFFFFFF000000000 | temp_value;
8234 else
8235 value = temp_value;
8236
8237 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8238 "[Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n",
8239 pic_number, rdata32_l/blk22_mv_count,
8240 value, blk22_mv_count);
8241
8242 /* mvx_L1_count[31:0] */
8243 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
8244 temp_value = mvx_L1_hi;
8245 temp_value = (temp_value << 32) | rdata32_l;
8246 if (mvx_L1_hi & 0x80)
8247 value = 0xFFFFFFF000000000 | temp_value;
8248 else
8249 value = temp_value;
8250
8251 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8252 "[Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n",
8253 pic_number, rdata32_l/blk22_mv_count,
8254 value, blk22_mv_count);
8255
8256 /* mvy_L1_count[31:0] */
8257 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
8258 temp_value = mvy_L1_hi;
8259 temp_value = (temp_value << 32) | rdata32_l;
8260 if (mvy_L1_hi & 0x80)
8261 value = 0xFFFFFFF000000000 | temp_value;
8262 else
8263 value = temp_value;
8264
8265 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8266 "[Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n",
8267 pic_number, rdata32_l/blk22_mv_count,
8268 value, blk22_mv_count);
8269
8270 /* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */
8271 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8272 mv_hi = (rdata32>>16)&0xffff;
8273 if (mv_hi & 0x8000)
8274 mv_hi = 0x8000 - mv_hi;
8275
8276 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8277 "[Picture %d Quality] MVX_L0 MAX : %d\n",
8278 pic_number, mv_hi);
8279
8280 frame->max_mv = mv_hi;
8281
8282 mv_lo = (rdata32>>0)&0xffff;
8283 if (mv_lo & 0x8000)
8284 mv_lo = 0x8000 - mv_lo;
8285
8286 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8287 "[Picture %d Quality] MVX_L0 MIN : %d\n",
8288 pic_number, mv_lo);
8289
8290 frame->min_mv = mv_lo;
8291
8292 /* {mvy_L0_max, mvy_L0_min} */
8293 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8294 mv_hi = (rdata32>>16)&0xffff;
8295 if (mv_hi & 0x8000)
8296 mv_hi = 0x8000 - mv_hi;
8297
8298 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8299 "[Picture %d Quality] MVY_L0 MAX : %d\n",
8300 pic_number, mv_hi);
8301
8302 mv_lo = (rdata32>>0)&0xffff;
8303 if (mv_lo & 0x8000)
8304 mv_lo = 0x8000 - mv_lo;
8305
8306 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8307 "[Picture %d Quality] MVY_L0 MIN : %d\n",
8308 pic_number, mv_lo);
8309
8310 /* {mvx_L1_max, mvx_L1_min} */
8311 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8312 mv_hi = (rdata32>>16)&0xffff;
8313 if (mv_hi & 0x8000)
8314 mv_hi = 0x8000 - mv_hi;
8315
8316 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8317 "[Picture %d Quality] MVX_L1 MAX : %d\n",
8318 pic_number, mv_hi);
8319
8320 mv_lo = (rdata32>>0)&0xffff;
8321 if (mv_lo & 0x8000)
8322 mv_lo = 0x8000 - mv_lo;
8323
8324 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8325 "[Picture %d Quality] MVX_L1 MIN : %d\n",
8326 pic_number, mv_lo);
8327
8328 /* {mvy_L1_max, mvy_L1_min} */
8329 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8330 mv_hi = (rdata32>>16)&0xffff;
8331 if (mv_hi & 0x8000)
8332 mv_hi = 0x8000 - mv_hi;
8333
8334 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8335 "[Picture %d Quality] MVY_L1 MAX : %d\n",
8336 pic_number, mv_hi);
8337
8338 mv_lo = (rdata32>>0)&0xffff;
8339 if (mv_lo & 0x8000)
8340 mv_lo = 0x8000 - mv_lo;
8341
8342 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8343 "[Picture %d Quality] MVY_L1 MIN : %d\n",
8344 pic_number, mv_lo);
8345
8346 rdata32 = READ_VREG(HEVC_PIC_QUALITY_CTRL);
8347
8348 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8349 "[Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n",
8350 pic_number, rdata32);
8351
8352 /* reset all counts */
8353 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
8354 }
8355}
8356
8357static int vvp9_get_ps_info(struct VP9Decoder_s *pbi, struct aml_vdec_ps_infos *ps)
8358{
8359 int dw_mode = v4l_parser_get_double_write_mode(pbi);
8360
8361 ps->visible_width = pbi->frame_width / get_double_write_ratio(pbi, dw_mode);
8362 ps->visible_height = pbi->frame_height / get_double_write_ratio(pbi, dw_mode);
8363 ps->coded_width = ALIGN(pbi->frame_width, 32) / get_double_write_ratio(pbi, dw_mode);
8364 ps->coded_height = ALIGN(pbi->frame_height, 32) / get_double_write_ratio(pbi, dw_mode);
8365 ps->dpb_size = pbi->used_buf_num;
8366
8367 return 0;
8368}
8369
8370
8371static int v4l_res_change(struct VP9Decoder_s *pbi)
8372{
8373 struct aml_vcodec_ctx *ctx =
8374 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
8375 struct VP9_Common_s *const cm = &pbi->common;
8376 int ret = 0;
8377
8378 if (ctx->param_sets_from_ucode &&
8379 pbi->res_ch_flag == 0) {
8380 struct aml_vdec_ps_infos ps;
8381 if ((cm->width != 0 &&
8382 cm->height != 0) &&
8383 (pbi->frame_width != cm->width ||
8384 pbi->frame_height != cm->height)) {
8385
8386 vp9_print(pbi, 0, "%s (%d,%d)=>(%d,%d)\r\n", __func__, cm->width,
8387 cm->height, pbi->frame_width, pbi->frame_height);
8388 vvp9_get_ps_info(pbi, &ps);
8389 vdec_v4l_set_ps_infos(ctx, &ps);
8390 vdec_v4l_res_ch_event(ctx);
8391 pbi->v4l_params_parsed = false;
8392 pbi->res_ch_flag = 1;
8393 pbi->eos = 1;
8394 vp9_bufmgr_postproc(pbi);
8395 //del_timer_sync(&pbi->timer);
8396 notify_v4l_eos(hw_to_vdec(pbi));
8397 ret = 1;
8398 }
8399 }
8400
8401 return ret;
8402}
8403
8404
8405static irqreturn_t vvp9_isr_thread_fn(int irq, void *data)
8406{
8407 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)data;
8408 unsigned int dec_status = pbi->dec_status;
8409 int i;
8410
8411 /*if (pbi->wait_buf)
8412 * pr_info("set wait_buf to 0\r\n");
8413 */
8414 if (pbi->eos)
8415 return IRQ_HANDLED;
8416 pbi->wait_buf = 0;
8417#ifdef MULTI_INSTANCE_SUPPORT
8418#ifdef SUPPORT_FB_DECODING
8419#ifdef FB_DECODING_TEST_SCHEDULE
8420 if (pbi->s1_test_cmd == TEST_SET_PIC_DONE)
8421 dec_status = HEVC_DECPIC_DATA_DONE;
8422 else if (pbi->s1_test_cmd == TEST_SET_S2_DONE
8423 && dec_status == HEVC_DECPIC_DATA_DONE)
8424 dec_status = HEVC_S2_DECODING_DONE;
8425 pbi->s1_test_cmd = TEST_SET_NONE;
8426#else
8427 /*if (irq != VDEC_IRQ_0)
8428 dec_status = HEVC_S2_DECODING_DONE;*/
8429#endif
8430 if (dec_status == HEVC_S2_DECODING_DONE) {
8431 pbi->dec_result = DEC_RESULT_DONE;
8432 vdec_schedule_work(&pbi->work);
8433#ifdef FB_DECODING_TEST_SCHEDULE
8434 amhevc_stop();
8435 pbi->dec_s1_result = DEC_S1_RESULT_DONE;
8436 vdec_schedule_work(&pbi->s1_work);
8437#endif
8438 } else
8439#endif
8440 if ((dec_status == HEVC_NAL_DECODE_DONE) ||
8441 (dec_status == HEVC_SEARCH_BUFEMPTY) ||
8442 (dec_status == HEVC_DECODE_BUFEMPTY)
8443 ) {
8444 if (pbi->m_ins_flag) {
8445 reset_process_time(pbi);
8446 if (!vdec_frame_based(hw_to_vdec(pbi)))
8447 dec_again_process(pbi);
8448 else {
8449 pbi->dec_result = DEC_RESULT_GET_DATA;
8450 vdec_schedule_work(&pbi->work);
8451 }
8452 }
8453 pbi->process_busy = 0;
8454 return IRQ_HANDLED;
8455 } else if (dec_status == HEVC_DECPIC_DATA_DONE) {
8456 if (pbi->m_ins_flag) {
8457 get_picture_qos_info(pbi);
8458#ifdef SUPPORT_FB_DECODING
8459 if (pbi->used_stage_buf_num > 0) {
8460 reset_process_time(pbi);
8461 inc_s1_pos(pbi);
8462 trigger_schedule(pbi);
8463#ifdef FB_DECODING_TEST_SCHEDULE
8464 pbi->s1_test_cmd = TEST_SET_S2_DONE;
8465#else
8466 amhevc_stop();
8467 pbi->dec_s1_result = DEC_S1_RESULT_DONE;
8468 vdec_schedule_work(&pbi->s1_work);
8469#endif
8470 } else
8471#endif
8472 {
8473 reset_process_time(pbi);
8474 if (pbi->vf_pre_count == 0 || pbi->low_latency_flag)
8475 vp9_bufmgr_postproc(pbi);
8476
8477 pbi->dec_result = DEC_RESULT_DONE;
8478 amhevc_stop();
8479 if (mcrcc_cache_alg_flag)
8480 dump_hit_rate(pbi);
8481 vdec_schedule_work(&pbi->work);
8482 }
8483 } else {
8484 if (pbi->low_latency_flag) {
8485 vp9_bufmgr_postproc(pbi);
8486 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
8487#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
8488 vdec_profile(hw_to_vdec(pbi), VDEC_PROFILE_EVENT_CB);
8489 if (debug & PRINT_FLAG_VDEC_DETAIL)
8490 pr_info("%s VP9 frame done \n", __func__);
8491#endif
8492 }
8493 }
8494
8495 pbi->process_busy = 0;
8496 return IRQ_HANDLED;
8497 }
8498#endif
8499
8500 if (dec_status == VP9_EOS) {
8501#ifdef MULTI_INSTANCE_SUPPORT
8502 if (pbi->m_ins_flag)
8503 reset_process_time(pbi);
8504#endif
8505
8506 pr_info("VP9_EOS, flush buffer\r\n");
8507
8508 vp9_bufmgr_postproc(pbi);
8509
8510 pr_info("send VP9_10B_DISCARD_NAL\r\n");
8511 WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DISCARD_NAL);
8512 pbi->process_busy = 0;
8513#ifdef MULTI_INSTANCE_SUPPORT
8514 if (pbi->m_ins_flag) {
8515 pbi->dec_result = DEC_RESULT_DONE;
8516 amhevc_stop();
8517 vdec_schedule_work(&pbi->work);
8518 }
8519#endif
8520 return IRQ_HANDLED;
8521 } else if (dec_status == HEVC_DECODE_OVER_SIZE) {
8522 pr_info("vp9 decode oversize !!\n");
8523 debug |= (VP9_DEBUG_DIS_LOC_ERROR_PROC |
8524 VP9_DEBUG_DIS_SYS_ERROR_PROC);
8525 pbi->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
8526#ifdef MULTI_INSTANCE_SUPPORT
8527 if (pbi->m_ins_flag)
8528 reset_process_time(pbi);
8529#endif
8530 return IRQ_HANDLED;
8531 }
8532
8533 if (dec_status != VP9_HEAD_PARSER_DONE) {
8534 pbi->process_busy = 0;
8535 return IRQ_HANDLED;
8536 }
8537
8538 if (pbi->m_ins_flag &&
8539 !get_free_buf_count(pbi)) {
8540 pbi->run_ready_min_buf_num = pbi->one_package_frame_cnt + 1;
8541 pr_err("need buffer, one package frame count = %d\n", pbi->one_package_frame_cnt + 1);
8542 pbi->dec_result = DEC_RESULT_NEED_MORE_BUFFER;
8543 vdec_schedule_work(&pbi->work);
8544 return IRQ_HANDLED;
8545 }
8546
8547 pbi->one_package_frame_cnt++;
8548
8549#ifdef MULTI_INSTANCE_SUPPORT
8550#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
8551 if (pbi->m_ins_flag ==0 && pbi->low_latency_flag) {
8552 vdec_profile(hw_to_vdec(pbi), VDEC_PROFILE_EVENT_RUN);
8553 if (debug & PRINT_FLAG_VDEC_DETAIL)
8554 pr_info("%s VP9 frame header found \n", __func__);
8555 }
8556#endif
8557 if (pbi->m_ins_flag)
8558 reset_process_time(pbi);
8559#endif
8560 if (pbi->process_state != PROC_STATE_SENDAGAIN
8561#ifdef SUPPORT_FB_DECODING
8562 && pbi->used_stage_buf_num == 0
8563#endif
8564 ) {
8565 if (pbi->mmu_enable)
8566 vp9_recycle_mmu_buf_tail(pbi);
8567
8568
8569 if (pbi->frame_count > 0)
8570 vp9_bufmgr_postproc(pbi);
8571 }
8572
8573 if (debug & VP9_DEBUG_SEND_PARAM_WITH_REG) {
8574 get_rpm_param(&pbi->vp9_param);
8575 } else {
8576#ifdef SUPPORT_FB_DECODING
8577 if (pbi->used_stage_buf_num > 0) {
8578 reset_process_time(pbi);
8579 get_s1_buf(pbi);
8580
8581 if (get_mv_buf(pbi,
8582 &pbi->s1_mv_buf_index,
8583 &pbi->s1_mpred_mv_wr_start_addr
8584 ) < 0) {
8585 vp9_print(pbi, 0,
8586 "%s: Error get_mv_buf fail\n",
8587 __func__);
8588 }
8589
8590 if (pbi->s1_buf == NULL) {
8591 vp9_print(pbi, 0,
8592 "%s: Error get_s1_buf fail\n",
8593 __func__);
8594 pbi->process_busy = 0;
8595 return IRQ_HANDLED;
8596 }
8597
8598 for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
8599 int ii;
8600 for (ii = 0; ii < 4; ii++) {
8601 pbi->s1_buf->rpm[i + 3 - ii] =
8602 pbi->rpm_ptr[i + 3 - ii];
8603 pbi->s1_param.l.data[i + ii] =
8604 pbi->rpm_ptr[i + 3 - ii];
8605 }
8606 }
8607
8608 mpred_process(pbi);
8609#ifdef FB_DECODING_TEST_SCHEDULE
8610 pbi->dec_s1_result =
8611 DEC_S1_RESULT_TEST_TRIGGER_DONE;
8612 vdec_schedule_work(&pbi->s1_work);
8613#else
8614 WRITE_VREG(HEVC_ASSIST_FB_MMU_MAP_ADDR,
8615 pbi->stage_mmu_map_phy_addr +
8616 pbi->s1_buf->index * STAGE_MMU_MAP_SIZE);
8617
8618 start_s1_decoding(pbi);
8619#endif
8620 start_process_time(pbi);
8621 pbi->process_busy = 0;
8622 return IRQ_HANDLED;
8623 } else
8624#endif
8625 {
8626 for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
8627 int ii;
8628 for (ii = 0; ii < 4; ii++)
8629 pbi->vp9_param.l.data[i + ii] =
8630 pbi->rpm_ptr[i + 3 - ii];
8631 }
8632 }
8633 }
8634
8635 if (pbi->is_used_v4l) {
8636 struct aml_vcodec_ctx *ctx =
8637 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
8638
8639 pbi->frame_width = pbi->vp9_param.p.width;
8640 pbi->frame_height = pbi->vp9_param.p.height;
8641
8642 if (!v4l_res_change(pbi)) {
8643 if (ctx->param_sets_from_ucode && !pbi->v4l_params_parsed) {
8644 struct aml_vdec_ps_infos ps;
8645
8646 pr_debug("set ucode parse\n");
8647 vvp9_get_ps_info(pbi, &ps);
8648 /*notice the v4l2 codec.*/
8649 vdec_v4l_set_ps_infos(ctx, &ps);
8650 pbi->v4l_params_parsed = true;
8651 pbi->postproc_done = 0;
8652 pbi->process_busy = 0;
8653 dec_again_process(pbi);
8654 return IRQ_HANDLED;
8655 }
8656 } else {
8657 pbi->postproc_done = 0;
8658 pbi->process_busy = 0;
8659 dec_again_process(pbi);
8660 return IRQ_HANDLED;
8661 }
8662 }
8663
8664 continue_decoding(pbi);
8665 pbi->postproc_done = 0;
8666 pbi->process_busy = 0;
8667
8668#ifdef MULTI_INSTANCE_SUPPORT
8669 if (pbi->m_ins_flag)
8670 start_process_time(pbi);
8671#endif
8672
8673 return IRQ_HANDLED;
8674}
8675
8676static irqreturn_t vvp9_isr(int irq, void *data)
8677{
8678 int i;
8679 unsigned int dec_status;
8680 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)data;
8681 unsigned int adapt_prob_status;
8682 struct VP9_Common_s *const cm = &pbi->common;
8683 uint debug_tag;
8684
8685 WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1);
8686
8687 dec_status = READ_VREG(HEVC_DEC_STATUS_REG);
8688 adapt_prob_status = READ_VREG(VP9_ADAPT_PROB_REG);
8689 if (!pbi)
8690 return IRQ_HANDLED;
8691 if (pbi->init_flag == 0)
8692 return IRQ_HANDLED;
8693 if (pbi->process_busy)/*on process.*/
8694 return IRQ_HANDLED;
8695 pbi->dec_status = dec_status;
8696 pbi->process_busy = 1;
8697 if (debug & VP9_DEBUG_BUFMGR)
8698 pr_info("vp9 isr (%d) dec status = 0x%x, lcu 0x%x shiftbyte 0x%x (%x %x lev %x, wr %x, rd %x)\n",
8699 irq,
8700 dec_status, READ_VREG(HEVC_PARSER_LCU_START),
8701 READ_VREG(HEVC_SHIFT_BYTE_COUNT),
8702 READ_VREG(HEVC_STREAM_START_ADDR),
8703 READ_VREG(HEVC_STREAM_END_ADDR),
8704 READ_VREG(HEVC_STREAM_LEVEL),
8705 READ_VREG(HEVC_STREAM_WR_PTR),
8706 READ_VREG(HEVC_STREAM_RD_PTR)
8707 );
8708#ifdef SUPPORT_FB_DECODING
8709 /*if (irq != VDEC_IRQ_0)
8710 return IRQ_WAKE_THREAD;*/
8711#endif
8712
8713 debug_tag = READ_HREG(DEBUG_REG1);
8714 if (debug_tag & 0x10000) {
8715 pr_info("LMEM<tag %x>:\n", READ_HREG(DEBUG_REG1));
8716 for (i = 0; i < 0x400; i += 4) {
8717 int ii;
8718 if ((i & 0xf) == 0)
8719 pr_info("%03x: ", i);
8720 for (ii = 0; ii < 4; ii++) {
8721 pr_info("%04x ",
8722 pbi->lmem_ptr[i + 3 - ii]);
8723 }
8724 if (((i + ii) & 0xf) == 0)
8725 pr_info("\n");
8726 }
8727
8728 if ((udebug_pause_pos == (debug_tag & 0xffff)) &&
8729 (udebug_pause_decode_idx == 0 ||
8730 udebug_pause_decode_idx == pbi->slice_idx) &&
8731 (udebug_pause_val == 0 ||
8732 udebug_pause_val == READ_HREG(DEBUG_REG2)))
8733 pbi->ucode_pause_pos = udebug_pause_pos;
8734 else if (debug_tag & 0x20000)
8735 pbi->ucode_pause_pos = 0xffffffff;
8736 if (pbi->ucode_pause_pos)
8737 reset_process_time(pbi);
8738 else
8739 WRITE_HREG(DEBUG_REG1, 0);
8740 } else if (debug_tag != 0) {
8741 pr_info(
8742 "dbg%x: %x lcu %x\n", READ_HREG(DEBUG_REG1),
8743 READ_HREG(DEBUG_REG2),
8744 READ_VREG(HEVC_PARSER_LCU_START));
8745 if ((udebug_pause_pos == (debug_tag & 0xffff)) &&
8746 (udebug_pause_decode_idx == 0 ||
8747 udebug_pause_decode_idx == pbi->slice_idx) &&
8748 (udebug_pause_val == 0 ||
8749 udebug_pause_val == READ_HREG(DEBUG_REG2)))
8750 pbi->ucode_pause_pos = udebug_pause_pos;
8751 if (pbi->ucode_pause_pos)
8752 reset_process_time(pbi);
8753 else
8754 WRITE_HREG(DEBUG_REG1, 0);
8755 pbi->process_busy = 0;
8756 return IRQ_HANDLED;
8757 }
8758
8759#ifdef MULTI_INSTANCE_SUPPORT
8760 if (!pbi->m_ins_flag) {
8761#endif
8762 if (pbi->error_flag == 1) {
8763 pbi->error_flag = 2;
8764 pbi->process_busy = 0;
8765 return IRQ_HANDLED;
8766 } else if (pbi->error_flag == 3) {
8767 pbi->process_busy = 0;
8768 return IRQ_HANDLED;
8769 }
8770
8771 if (get_free_buf_count(pbi) <= 0) {
8772 /*
8773 if (pbi->wait_buf == 0)
8774 pr_info("set wait_buf to 1\r\n");
8775 */
8776 pbi->wait_buf = 1;
8777 pbi->process_busy = 0;
8778 return IRQ_HANDLED;
8779 }
8780#ifdef MULTI_INSTANCE_SUPPORT
8781 }
8782#endif
8783 if ((adapt_prob_status & 0xff) == 0xfd) {
8784 /*VP9_REQ_ADAPT_PROB*/
8785 int pre_fc = (cm->frame_type == KEY_FRAME) ? 1 : 0;
8786 uint8_t *prev_prob_b =
8787 ((uint8_t *)pbi->prob_buffer_addr) +
8788 ((adapt_prob_status >> 8) * 0x1000);
8789 uint8_t *cur_prob_b =
8790 ((uint8_t *)pbi->prob_buffer_addr) + 0x4000;
8791 uint8_t *count_b = (uint8_t *)pbi->count_buffer_addr;
8792#ifdef MULTI_INSTANCE_SUPPORT
8793 if (pbi->m_ins_flag)
8794 reset_process_time(pbi);
8795#endif
8796 adapt_coef_probs(pbi->pic_count,
8797 (cm->last_frame_type == KEY_FRAME),
8798 pre_fc, (adapt_prob_status >> 8),
8799 (unsigned int *)prev_prob_b,
8800 (unsigned int *)cur_prob_b, (unsigned int *)count_b);
8801
8802 memcpy(prev_prob_b, cur_prob_b, PROB_SIZE);
8803 WRITE_VREG(VP9_ADAPT_PROB_REG, 0);
8804 pbi->pic_count += 1;
8805#ifdef MULTI_INSTANCE_SUPPORT
8806 if (pbi->m_ins_flag)
8807 start_process_time(pbi);
8808#endif
8809
8810 /*return IRQ_HANDLED;*/
8811 }
8812 return IRQ_WAKE_THREAD;
8813}
8814
8815static void vp9_set_clk(struct work_struct *work)
8816{
8817 struct VP9Decoder_s *pbi = container_of(work,
8818 struct VP9Decoder_s, set_clk_work);
8819 int fps = 96000 / pbi->frame_dur;
8820
8821 if (hevc_source_changed(VFORMAT_VP9,
8822 frame_width, frame_height, fps) > 0)
8823 pbi->saved_resolution = frame_width *
8824 frame_height * fps;
8825}
8826
8827static void vvp9_put_timer_func(unsigned long arg)
8828{
8829 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)arg;
8830 struct timer_list *timer = &pbi->timer;
8831 uint8_t empty_flag;
8832 unsigned int buf_level;
8833
8834 enum receviver_start_e state = RECEIVER_INACTIVE;
8835
8836 if (pbi->m_ins_flag) {
8837 if (hw_to_vdec(pbi)->next_status
8838 == VDEC_STATUS_DISCONNECTED &&
8839 !pbi->is_used_v4l) {
8840#ifdef SUPPORT_FB_DECODING
8841 if (pbi->run2_busy)
8842 return;
8843
8844 pbi->dec_s1_result = DEC_S1_RESULT_FORCE_EXIT;
8845 vdec_schedule_work(&pbi->s1_work);
8846#endif
8847 pbi->dec_result = DEC_RESULT_FORCE_EXIT;
8848 vdec_schedule_work(&pbi->work);
8849 pr_debug(
8850 "vdec requested to be disconnected\n");
8851 return;
8852 }
8853 }
8854 if (pbi->init_flag == 0) {
8855 if (pbi->stat & STAT_TIMER_ARM) {
8856 timer->expires = jiffies + PUT_INTERVAL;
8857 add_timer(&pbi->timer);
8858 }
8859 return;
8860 }
8861 if (pbi->m_ins_flag == 0) {
8862 if (vf_get_receiver(pbi->provider_name)) {
8863 state =
8864 vf_notify_receiver(pbi->provider_name,
8865 VFRAME_EVENT_PROVIDER_QUREY_STATE,
8866 NULL);
8867 if ((state == RECEIVER_STATE_NULL)
8868 || (state == RECEIVER_STATE_NONE))
8869 state = RECEIVER_INACTIVE;
8870 } else
8871 state = RECEIVER_INACTIVE;
8872
8873 empty_flag = (READ_VREG(HEVC_PARSER_INT_STATUS) >> 6) & 0x1;
8874 /* error watchdog */
8875 if (empty_flag == 0) {
8876 /* decoder has input */
8877 if ((debug & VP9_DEBUG_DIS_LOC_ERROR_PROC) == 0) {
8878
8879 buf_level = READ_VREG(HEVC_STREAM_LEVEL);
8880 /* receiver has no buffer to recycle */
8881 if ((state == RECEIVER_INACTIVE) &&
8882 (kfifo_is_empty(&pbi->display_q) &&
8883 buf_level > 0x200)
8884 ) {
8885 WRITE_VREG
8886 (HEVC_ASSIST_MBOX0_IRQ_REG,
8887 0x1);
8888 }
8889 }
8890
8891 if ((debug & VP9_DEBUG_DIS_SYS_ERROR_PROC) == 0) {
8892 /* receiver has no buffer to recycle */
8893 /*if ((state == RECEIVER_INACTIVE) &&
8894 * (kfifo_is_empty(&pbi->display_q))) {
8895 *pr_info("vp9 something error,need reset\n");
8896 *}
8897 */
8898 }
8899 }
8900 }
8901#ifdef MULTI_INSTANCE_SUPPORT
8902 else {
8903 if (
8904 (decode_timeout_val > 0) &&
8905 (pbi->start_process_time > 0) &&
8906 ((1000 * (jiffies - pbi->start_process_time) / HZ)
8907 > decode_timeout_val)
8908 ) {
8909 int current_lcu_idx =
8910 READ_VREG(HEVC_PARSER_LCU_START)
8911 & 0xffffff;
8912 if (pbi->last_lcu_idx == current_lcu_idx) {
8913 if (pbi->decode_timeout_count > 0)
8914 pbi->decode_timeout_count--;
8915 if (pbi->decode_timeout_count == 0) {
8916 if (input_frame_based(
8917 hw_to_vdec(pbi)) ||
8918 (READ_VREG(HEVC_STREAM_LEVEL) > 0x200))
8919 timeout_process(pbi);
8920 else {
8921 vp9_print(pbi, 0,
8922 "timeout & empty, again\n");
8923 dec_again_process(pbi);
8924 }
8925 }
8926 } else {
8927 start_process_time(pbi);
8928 pbi->last_lcu_idx = current_lcu_idx;
8929 }
8930 }
8931 }
8932#endif
8933
8934 if ((pbi->ucode_pause_pos != 0) &&
8935 (pbi->ucode_pause_pos != 0xffffffff) &&
8936 udebug_pause_pos != pbi->ucode_pause_pos) {
8937 pbi->ucode_pause_pos = 0;
8938 WRITE_HREG(DEBUG_REG1, 0);
8939 }
8940#ifdef MULTI_INSTANCE_SUPPORT
8941 if (debug & VP9_DEBUG_FORCE_SEND_AGAIN) {
8942 pr_info(
8943 "Force Send Again\r\n");
8944 debug &= ~VP9_DEBUG_FORCE_SEND_AGAIN;
8945 reset_process_time(pbi);
8946 pbi->dec_result = DEC_RESULT_AGAIN;
8947 if (pbi->process_state ==
8948 PROC_STATE_DECODESLICE) {
8949 if (pbi->mmu_enable)
8950 vp9_recycle_mmu_buf(pbi);
8951 pbi->process_state =
8952 PROC_STATE_SENDAGAIN;
8953 }
8954 amhevc_stop();
8955
8956 vdec_schedule_work(&pbi->work);
8957 }
8958
8959 if (debug & VP9_DEBUG_DUMP_DATA) {
8960 debug &= ~VP9_DEBUG_DUMP_DATA;
8961 vp9_print(pbi, 0,
8962 "%s: chunk size 0x%x off 0x%x sum 0x%x\n",
8963 __func__,
8964 pbi->chunk->size,
8965 pbi->chunk->offset,
8966 get_data_check_sum(pbi, pbi->chunk->size)
8967 );
8968 dump_data(pbi, pbi->chunk->size);
8969 }
8970#endif
8971 if (debug & VP9_DEBUG_DUMP_PIC_LIST) {
8972 dump_pic_list(pbi);
8973 debug &= ~VP9_DEBUG_DUMP_PIC_LIST;
8974 }
8975 if (debug & VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC) {
8976 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1);
8977 debug &= ~VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC;
8978 }
8979 /*if (debug & VP9_DEBUG_HW_RESET) {
8980 }*/
8981
8982 if (radr != 0) {
8983 if (rval != 0) {
8984 WRITE_VREG(radr, rval);
8985 pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
8986 } else
8987 pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
8988 rval = 0;
8989 radr = 0;
8990 }
8991 if (pop_shorts != 0) {
8992 int i;
8993 u32 sum = 0;
8994
8995 pr_info("pop stream 0x%x shorts\r\n", pop_shorts);
8996 for (i = 0; i < pop_shorts; i++) {
8997 u32 data =
8998 (READ_HREG(HEVC_SHIFTED_DATA) >> 16);
8999 WRITE_HREG(HEVC_SHIFT_COMMAND,
9000 (1<<7)|16);
9001 if ((i & 0xf) == 0)
9002 pr_info("%04x:", i);
9003 pr_info("%04x ", data);
9004 if (((i + 1) & 0xf) == 0)
9005 pr_info("\r\n");
9006 sum += data;
9007 }
9008 pr_info("\r\nsum = %x\r\n", sum);
9009 pop_shorts = 0;
9010 }
9011 if (dbg_cmd != 0) {
9012 if (dbg_cmd == 1) {
9013 u32 disp_laddr;
9014
9015 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXBB &&
9016 get_double_write_mode(pbi) == 0) {
9017 disp_laddr =
9018 READ_VCBUS_REG(AFBC_BODY_BADDR) << 4;
9019 } else {
9020 struct canvas_s cur_canvas;
9021
9022 canvas_read((READ_VCBUS_REG(VD1_IF0_CANVAS0)
9023 & 0xff), &cur_canvas);
9024 disp_laddr = cur_canvas.addr;
9025 }
9026 pr_info("current displayed buffer address %x\r\n",
9027 disp_laddr);
9028 }
9029 dbg_cmd = 0;
9030 }
9031 /*don't changed at start.*/
9032 if (pbi->get_frame_dur && pbi->show_frame_num > 60 &&
9033 pbi->frame_dur > 0 && pbi->saved_resolution !=
9034 frame_width * frame_height *
9035 (96000 / pbi->frame_dur))
9036 vdec_schedule_work(&pbi->set_clk_work);
9037
9038 timer->expires = jiffies + PUT_INTERVAL;
9039 add_timer(timer);
9040}
9041
9042
9043int vvp9_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
9044{
9045 struct VP9Decoder_s *vp9 =
9046 (struct VP9Decoder_s *)vdec->private;
9047
9048 if (!vp9)
9049 return -1;
9050
9051 vstatus->frame_width = frame_width;
9052 vstatus->frame_height = frame_height;
9053 if (vp9->frame_dur != 0)
9054 vstatus->frame_rate = 96000 / vp9->frame_dur;
9055 else
9056 vstatus->frame_rate = -1;
9057 vstatus->error_count = 0;
9058 vstatus->status = vp9->stat | vp9->fatal_error;
9059 vstatus->frame_dur = vp9->frame_dur;
9060 vstatus->bit_rate = vp9->gvs->bit_rate;
9061 vstatus->frame_data = vp9->gvs->frame_data;
9062 vstatus->total_data = vp9->gvs->total_data;
9063 vstatus->frame_count = vp9->gvs->frame_count;
9064 vstatus->error_frame_count = vp9->gvs->error_frame_count;
9065 vstatus->drop_frame_count = vp9->gvs->drop_frame_count;
9066 vstatus->total_data = vp9->gvs->total_data;
9067 vstatus->samp_cnt = vp9->gvs->samp_cnt;
9068 vstatus->offset = vp9->gvs->offset;
9069 snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
9070 "%s", DRIVER_NAME);
9071 return 0;
9072}
9073
9074int vvp9_set_isreset(struct vdec_s *vdec, int isreset)
9075{
9076 is_reset = isreset;
9077 return 0;
9078}
9079
9080#if 0
9081static void VP9_DECODE_INIT(void)
9082{
9083 /* enable vp9 clocks */
9084 WRITE_VREG(DOS_GCLK_EN3, 0xffffffff);
9085 /* *************************************************************** */
9086 /* Power ON HEVC */
9087 /* *************************************************************** */
9088 /* Powerup HEVC */
9089 WRITE_VREG(AO_RTI_GEN_PWR_SLEEP0,
9090 READ_VREG(AO_RTI_GEN_PWR_SLEEP0) & (~(0x3 << 6)));
9091 WRITE_VREG(DOS_MEM_PD_HEVC, 0x0);
9092 WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) | (0x3ffff << 2));
9093 WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) & (~(0x3ffff << 2)));
9094 /* remove isolations */
9095 WRITE_VREG(AO_RTI_GEN_PWR_ISO0,
9096 READ_VREG(AO_RTI_GEN_PWR_ISO0) & (~(0x3 << 10)));
9097
9098}
9099#endif
9100
9101static void vvp9_prot_init(struct VP9Decoder_s *pbi, u32 mask)
9102{
9103 unsigned int data32;
9104 /* VP9_DECODE_INIT(); */
9105 vp9_config_work_space_hw(pbi, mask);
9106 if (mask & HW_MASK_BACK)
9107 init_pic_list_hw(pbi);
9108
9109 vp9_init_decoder_hw(pbi, mask);
9110
9111#ifdef VP9_LPF_LVL_UPDATE
9112 if (mask & HW_MASK_BACK)
9113 vp9_loop_filter_init(pbi);
9114#endif
9115
9116 if ((mask & HW_MASK_FRONT) == 0)
9117 return;
9118#if 1
9119 if (debug & VP9_DEBUG_BUFMGR_MORE)
9120 pr_info("%s\n", __func__);
9121 data32 = READ_VREG(HEVC_STREAM_CONTROL);
9122 data32 = data32 |
9123 (1 << 0)/*stream_fetch_enable*/
9124 ;
9125 WRITE_VREG(HEVC_STREAM_CONTROL, data32);
9126
9127 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
9128 if (debug & VP9_DEBUG_BUFMGR)
9129 pr_info("[test.c] Config STREAM_FIFO_CTL\n");
9130 data32 = READ_VREG(HEVC_STREAM_FIFO_CTL);
9131 data32 = data32 |
9132 (1 << 29) // stream_fifo_hole
9133 ;
9134 WRITE_VREG(HEVC_STREAM_FIFO_CTL, data32);
9135 }
9136#if 0
9137 data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
9138 if (data32 != 0x00000100) {
9139 pr_info("vp9 prot init error %d\n", __LINE__);
9140 return;
9141 }
9142 data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
9143 if (data32 != 0x00000300) {
9144 pr_info("vp9 prot init error %d\n", __LINE__);
9145 return;
9146 }
9147 WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x12345678);
9148 WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x9abcdef0);
9149 data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
9150 if (data32 != 0x12345678) {
9151 pr_info("vp9 prot init error %d\n", __LINE__);
9152 return;
9153 }
9154 data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
9155 if (data32 != 0x9abcdef0) {
9156 pr_info("vp9 prot init error %d\n", __LINE__);
9157 return;
9158 }
9159#endif
9160 WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x000000001);
9161 WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x00000300);
9162#endif
9163
9164
9165
9166 WRITE_VREG(HEVC_WAIT_FLAG, 1);
9167
9168 /* WRITE_VREG(HEVC_MPSR, 1); */
9169
9170 /* clear mailbox interrupt */
9171 WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1);
9172
9173 /* enable mailbox interrupt */
9174 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 1);
9175
9176 /* disable PSCALE for hardware sharing */
9177 WRITE_VREG(HEVC_PSCALE_CTRL, 0);
9178
9179 WRITE_VREG(DEBUG_REG1, 0x0);
9180 /*check vps/sps/pps/i-slice in ucode*/
9181 WRITE_VREG(NAL_SEARCH_CTL, 0x8);
9182
9183 WRITE_VREG(DECODE_STOP_POS, udebug_flag);
9184#ifdef SUPPORT_FB_DECODING
9185#ifndef FB_DECODING_TEST_SCHEDULE
9186 if (pbi->used_stage_buf_num > 0) {
9187 if (mask & HW_MASK_FRONT) {
9188 data32 = READ_VREG(
9189 HEVC_ASSIST_HED_FB_W_CTL);
9190 data32 = data32 |
9191 (1 << 0) /*hed_fb_wr_en*/
9192 ;
9193 WRITE_VREG(HEVC_ASSIST_HED_FB_W_CTL,
9194 data32);
9195 }
9196 if (mask & HW_MASK_BACK) {
9197 data32 = READ_VREG(
9198 HEVC_ASSIST_HED_FB_R_CTL);
9199 while (data32 & (1 << 7)) {
9200 /*wait finish*/
9201 data32 = READ_VREG(
9202 HEVC_ASSIST_HED_FB_R_CTL);
9203 }
9204 data32 &= (~(0x1 << 0));
9205 /*hed_fb_rd_addr_auto_rd*/
9206 data32 &= (~(0x1 << 1));
9207 /*rd_id = 0, hed_rd_map_auto_halt_num,
9208 after wr 2 ready, then start reading*/
9209 data32 |= (0x2 << 16);
9210 WRITE_VREG(HEVC_ASSIST_HED_FB_R_CTL,
9211 data32);
9212
9213 data32 |= (0x1 << 11); /*hed_rd_map_auto_halt_en*/
9214 data32 |= (0x1 << 1); /*hed_fb_rd_addr_auto_rd*/
9215 data32 |= (0x1 << 0); /*hed_fb_rd_en*/
9216 WRITE_VREG(HEVC_ASSIST_HED_FB_R_CTL,
9217 data32);
9218 }
9219
9220 }
9221#endif
9222#endif
9223}
9224
9225static int vvp9_local_init(struct VP9Decoder_s *pbi)
9226{
9227 int i;
9228 int ret;
9229 int width, height;
9230 if (alloc_lf_buf(pbi) < 0)
9231 return -1;
9232
9233 pbi->gvs = vzalloc(sizeof(struct vdec_info));
9234 if (NULL == pbi->gvs) {
9235 pr_info("the struct of vdec status malloc failed.\n");
9236 return -1;
9237 }
9238 vdec_set_vframe_comm(hw_to_vdec(pbi), DRIVER_NAME);
9239#ifdef DEBUG_PTS
9240 pbi->pts_missed = 0;
9241 pbi->pts_hit = 0;
9242#endif
9243 pbi->new_frame_displayed = 0;
9244 pbi->last_put_idx = -1;
9245 pbi->saved_resolution = 0;
9246 pbi->get_frame_dur = false;
9247 on_no_keyframe_skiped = 0;
9248 pbi->duration_from_pts_done = 0;
9249 pbi->vp9_first_pts_ready = 0;
9250 pbi->frame_cnt_window = 0;
9251 width = pbi->vvp9_amstream_dec_info.width;
9252 height = pbi->vvp9_amstream_dec_info.height;
9253 pbi->frame_dur =
9254 (pbi->vvp9_amstream_dec_info.rate ==
9255 0) ? 3200 : pbi->vvp9_amstream_dec_info.rate;
9256 if (width && height)
9257 pbi->frame_ar = height * 0x100 / width;
9258/*
9259 *TODO:FOR VERSION
9260 */
9261 pr_info("vp9: ver (%d,%d) decinfo: %dx%d rate=%d\n", vp9_version,
9262 0, width, height, pbi->frame_dur);
9263
9264 if (pbi->frame_dur == 0)
9265 pbi->frame_dur = 96000 / 24;
9266
9267 INIT_KFIFO(pbi->display_q);
9268 INIT_KFIFO(pbi->newframe_q);
9269
9270
9271 for (i = 0; i < VF_POOL_SIZE; i++) {
9272 const struct vframe_s *vf = &pbi->vfpool[i];
9273
9274 pbi->vfpool[i].index = -1;
9275 kfifo_put(&pbi->newframe_q, vf);
9276 }
9277
9278
9279 ret = vp9_local_init(pbi);
9280
9281 if (!pbi->pts_unstable) {
9282 pbi->pts_unstable =
9283 (pbi->vvp9_amstream_dec_info.rate == 0)?1:0;
9284 pr_info("set pts unstable\n");
9285 }
9286
9287 return ret;
9288}
9289
9290
9291#ifdef MULTI_INSTANCE_SUPPORT
9292static s32 vvp9_init(struct vdec_s *vdec)
9293{
9294 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)vdec->private;
9295#else
9296static s32 vvp9_init(struct VP9Decoder_s *pbi)
9297{
9298#endif
9299 int ret;
9300 int fw_size = 0x1000 * 16;
9301 struct firmware_s *fw = NULL;
9302
9303 pbi->stat |= STAT_TIMER_INIT;
9304
9305 if (vvp9_local_init(pbi) < 0)
9306 return -EBUSY;
9307
9308 fw = vmalloc(sizeof(struct firmware_s) + fw_size);
9309 if (IS_ERR_OR_NULL(fw))
9310 return -ENOMEM;
9311
9312 if (get_firmware_data(VIDEO_DEC_VP9_MMU, fw->data) < 0) {
9313 pr_err("get firmware fail.\n");
9314 vfree(fw);
9315 return -1;
9316 }
9317
9318 fw->len = fw_size;
9319
9320 INIT_WORK(&pbi->set_clk_work, vp9_set_clk);
9321 init_timer(&pbi->timer);
9322
9323#ifdef MULTI_INSTANCE_SUPPORT
9324 if (pbi->m_ins_flag) {
9325 pbi->timer.data = (ulong) pbi;
9326 pbi->timer.function = vvp9_put_timer_func;
9327 pbi->timer.expires = jiffies + PUT_INTERVAL;
9328
9329 /*add_timer(&pbi->timer);
9330
9331 pbi->stat |= STAT_TIMER_ARM;
9332 pbi->stat |= STAT_ISR_REG;*/
9333
9334 INIT_WORK(&pbi->work, vp9_work);
9335 INIT_WORK(&pbi->recycle_mmu_work, vp9_recycle_mmu_work);
9336#ifdef SUPPORT_FB_DECODING
9337 if (pbi->used_stage_buf_num > 0)
9338 INIT_WORK(&pbi->s1_work, vp9_s1_work);
9339#endif
9340 pbi->fw = fw;
9341
9342 /* picture list init.*/
9343 pbi->dec_result = DEC_INIT_PICLIST;
9344 vdec_schedule_work(&pbi->work);
9345
9346 return 0;
9347 }
9348#endif
9349 amhevc_enable();
9350
9351 init_pic_list(pbi);
9352
9353 ret = amhevc_loadmc_ex(VFORMAT_VP9, NULL, fw->data);
9354 if (ret < 0) {
9355 amhevc_disable();
9356 vfree(fw);
9357 pr_err("VP9: the %s fw loading failed, err: %x\n",
9358 tee_enabled() ? "TEE" : "local", ret);
9359 return -EBUSY;
9360 }
9361
9362 vfree(fw);
9363
9364 pbi->stat |= STAT_MC_LOAD;
9365
9366 /* enable AMRISC side protocol */
9367 vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
9368
9369 if (vdec_request_threaded_irq(VDEC_IRQ_0,
9370 vvp9_isr,
9371 vvp9_isr_thread_fn,
9372 IRQF_ONESHOT,/*run thread on this irq disabled*/
9373 "vvp9-irq", (void *)pbi)) {
9374 pr_info("vvp9 irq register error.\n");
9375 amhevc_disable();
9376 return -ENOENT;
9377 }
9378
9379 pbi->stat |= STAT_ISR_REG;
9380
9381 pbi->provider_name = PROVIDER_NAME;
9382#ifdef MULTI_INSTANCE_SUPPORT
9383 vf_provider_init(&vvp9_vf_prov, PROVIDER_NAME,
9384 &vvp9_vf_provider, pbi);
9385 vf_reg_provider(&vvp9_vf_prov);
9386 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL);
9387 if (pbi->frame_dur != 0) {
9388 if (!is_reset)
9389 vf_notify_receiver(pbi->provider_name,
9390 VFRAME_EVENT_PROVIDER_FR_HINT,
9391 (void *)
9392 ((unsigned long)pbi->frame_dur));
9393 }
9394#else
9395 vf_provider_init(&vvp9_vf_prov, PROVIDER_NAME, &vvp9_vf_provider,
9396 pbi);
9397 vf_reg_provider(&vvp9_vf_prov);
9398 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL);
9399 if (!is_reset)
9400 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_FR_HINT,
9401 (void *)((unsigned long)pbi->frame_dur));
9402#endif
9403 pbi->stat |= STAT_VF_HOOK;
9404
9405 pbi->timer.data = (ulong)pbi;
9406 pbi->timer.function = vvp9_put_timer_func;
9407 pbi->timer.expires = jiffies + PUT_INTERVAL;
9408
9409 pbi->stat |= STAT_VDEC_RUN;
9410
9411 add_timer(&pbi->timer);
9412
9413 pbi->stat |= STAT_TIMER_ARM;
9414
9415 amhevc_start();
9416
9417 pbi->init_flag = 1;
9418 pbi->process_busy = 0;
9419 pr_info("%d, vvp9_init, RP=0x%x\n",
9420 __LINE__, READ_VREG(HEVC_STREAM_RD_PTR));
9421 return 0;
9422}
9423
9424static int vmvp9_stop(struct VP9Decoder_s *pbi)
9425{
9426 pbi->init_flag = 0;
9427
9428 if (pbi->stat & STAT_VDEC_RUN) {
9429 amhevc_stop();
9430 pbi->stat &= ~STAT_VDEC_RUN;
9431 }
9432 if (pbi->stat & STAT_ISR_REG) {
9433 vdec_free_irq(VDEC_IRQ_0, (void *)pbi);
9434 pbi->stat &= ~STAT_ISR_REG;
9435 }
9436 if (pbi->stat & STAT_TIMER_ARM) {
9437 del_timer_sync(&pbi->timer);
9438 pbi->stat &= ~STAT_TIMER_ARM;
9439 }
9440
9441 if (pbi->stat & STAT_VF_HOOK) {
9442 if (!is_reset)
9443 vf_notify_receiver(pbi->provider_name,
9444 VFRAME_EVENT_PROVIDER_FR_END_HINT,
9445 NULL);
9446
9447 vf_unreg_provider(&vvp9_vf_prov);
9448 pbi->stat &= ~STAT_VF_HOOK;
9449 }
9450 vp9_local_uninit(pbi);
9451 reset_process_time(pbi);
9452 cancel_work_sync(&pbi->work);
9453 cancel_work_sync(&pbi->recycle_mmu_work);
9454#ifdef SUPPORT_FB_DECODING
9455 if (pbi->used_stage_buf_num > 0)
9456 cancel_work_sync(&pbi->s1_work);
9457#endif
9458 cancel_work_sync(&pbi->set_clk_work);
9459 uninit_mmu_buffers(pbi);
9460 if (pbi->fw)
9461 vfree(pbi->fw);
9462 pbi->fw = NULL;
9463 return 0;
9464}
9465
9466static int vvp9_stop(struct VP9Decoder_s *pbi)
9467{
9468
9469 pbi->init_flag = 0;
9470 pbi->first_sc_checked = 0;
9471 if (pbi->stat & STAT_VDEC_RUN) {
9472 amhevc_stop();
9473 pbi->stat &= ~STAT_VDEC_RUN;
9474 }
9475
9476 if (pbi->stat & STAT_ISR_REG) {
9477#ifdef MULTI_INSTANCE_SUPPORT
9478 if (!pbi->m_ins_flag)
9479#endif
9480 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0);
9481 vdec_free_irq(VDEC_IRQ_0, (void *)pbi);
9482 pbi->stat &= ~STAT_ISR_REG;
9483 }
9484
9485 if (pbi->stat & STAT_TIMER_ARM) {
9486 del_timer_sync(&pbi->timer);
9487 pbi->stat &= ~STAT_TIMER_ARM;
9488 }
9489
9490 if (pbi->stat & STAT_VF_HOOK) {
9491 if (!is_reset)
9492 vf_notify_receiver(pbi->provider_name,
9493 VFRAME_EVENT_PROVIDER_FR_END_HINT,
9494 NULL);
9495
9496 vf_unreg_provider(&vvp9_vf_prov);
9497 pbi->stat &= ~STAT_VF_HOOK;
9498 }
9499 vp9_local_uninit(pbi);
9500
9501 cancel_work_sync(&pbi->set_clk_work);
9502#ifdef MULTI_INSTANCE_SUPPORT
9503 if (pbi->m_ins_flag) {
9504#ifdef SUPPORT_FB_DECODING
9505 if (pbi->used_stage_buf_num > 0)
9506 cancel_work_sync(&pbi->s1_work);
9507#endif
9508 cancel_work_sync(&pbi->work);
9509 cancel_work_sync(&pbi->recycle_mmu_work);
9510 } else
9511 amhevc_disable();
9512#else
9513 amhevc_disable();
9514#endif
9515 uninit_mmu_buffers(pbi);
9516
9517 vfree(pbi->fw);
9518 pbi->fw = NULL;
9519 return 0;
9520}
9521static int amvdec_vp9_mmu_init(struct VP9Decoder_s *pbi)
9522{
9523 int tvp_flag = vdec_secure(hw_to_vdec(pbi)) ?
9524 CODEC_MM_FLAGS_TVP : 0;
9525 int buf_size = 48;
9526
9527 if ((pbi->max_pic_w * pbi->max_pic_h > 1280*736) &&
9528 (pbi->max_pic_w * pbi->max_pic_h <= 1920*1088)) {
9529 buf_size = 12;
9530 } else if ((pbi->max_pic_w * pbi->max_pic_h > 0) &&
9531 (pbi->max_pic_w * pbi->max_pic_h <= 1280*736)) {
9532 buf_size = 4;
9533 }
9534 pbi->need_cache_size = buf_size * SZ_1M;
9535 pbi->sc_start_time = get_jiffies_64();
9536 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
9537 pbi->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME,
9538 pbi->index, FRAME_BUFFERS,
9539 pbi->need_cache_size,
9540 tvp_flag
9541 );
9542 if (!pbi->mmu_box) {
9543 pr_err("vp9 alloc mmu box failed!!\n");
9544 return -1;
9545 }
9546 }
9547 pbi->bmmu_box = decoder_bmmu_box_alloc_box(
9548 DRIVER_NAME,
9549 pbi->index,
9550 MAX_BMMU_BUFFER_NUM,
9551 4 + PAGE_SHIFT,
9552 CODEC_MM_FLAGS_CMA_CLEAR |
9553 CODEC_MM_FLAGS_FOR_VDECODER |
9554 tvp_flag);
9555 if (!pbi->bmmu_box) {
9556 pr_err("vp9 alloc bmmu box failed!!\n");
9557 return -1;
9558 }
9559 return 0;
9560}
9561
9562static struct VP9Decoder_s *gHevc;
9563
9564static int amvdec_vp9_probe(struct platform_device *pdev)
9565{
9566 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
9567 struct BUF_s BUF[MAX_BUF_NUM];
9568 struct VP9Decoder_s *pbi;
9569 int ret;
9570#ifndef MULTI_INSTANCE_SUPPORT
9571 int i;
9572#endif
9573 pr_debug("%s\n", __func__);
9574
9575 mutex_lock(&vvp9_mutex);
9576 pbi = vmalloc(sizeof(struct VP9Decoder_s));
9577 if (pbi == NULL) {
9578 pr_info("\namvdec_vp9 device data allocation failed\n");
9579 mutex_unlock(&vvp9_mutex);
9580 return -ENOMEM;
9581 }
9582
9583 gHevc = pbi;
9584 memcpy(&BUF[0], &pbi->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
9585 memset(pbi, 0, sizeof(struct VP9Decoder_s));
9586 memcpy(&pbi->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
9587
9588 pbi->init_flag = 0;
9589 pbi->first_sc_checked= 0;
9590 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
9591 vp9_max_pic_w = 8192;
9592 vp9_max_pic_h = 4608;
9593 }
9594 pbi->max_pic_w = vp9_max_pic_w;
9595 pbi->max_pic_h = vp9_max_pic_h;
9596
9597#ifdef MULTI_INSTANCE_SUPPORT
9598 pbi->eos = 0;
9599 pbi->start_process_time = 0;
9600 pbi->timeout_num = 0;
9601#endif
9602 pbi->fatal_error = 0;
9603 pbi->show_frame_num = 0;
9604 if (pdata == NULL) {
9605 pr_info("\namvdec_vp9 memory resource undefined.\n");
9606 vfree(pbi);
9607 mutex_unlock(&vvp9_mutex);
9608 return -EFAULT;
9609 }
9610 pbi->m_ins_flag = 0;
9611#ifdef MULTI_INSTANCE_SUPPORT
9612 pbi->platform_dev = pdev;
9613 platform_set_drvdata(pdev, pdata);
9614#endif
9615 pbi->double_write_mode = double_write_mode;
9616 pbi->mmu_enable = 1;
9617 if (amvdec_vp9_mmu_init(pbi) < 0) {
9618 vfree(pbi);
9619 mutex_unlock(&vvp9_mutex);
9620 pr_err("vp9 alloc bmmu box failed!!\n");
9621 return -1;
9622 }
9623
9624 ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box, WORK_SPACE_BUF_ID,
9625 work_buf_size, DRIVER_NAME, &pdata->mem_start);
9626 if (ret < 0) {
9627 uninit_mmu_buffers(pbi);
9628 vfree(pbi);
9629 mutex_unlock(&vvp9_mutex);
9630 return ret;
9631 }
9632 pbi->buf_size = work_buf_size;
9633
9634#ifdef MULTI_INSTANCE_SUPPORT
9635 pbi->buf_start = pdata->mem_start;
9636#else
9637 if (!pbi->mmu_enable)
9638 pbi->mc_buf_spec.buf_end = pdata->mem_start + pbi->buf_size;
9639
9640 for (i = 0; i < WORK_BUF_SPEC_NUM; i++)
9641 amvvp9_workbuff_spec[i].start_adr = pdata->mem_start;
9642#endif
9643
9644
9645 if (debug) {
9646 pr_info("===VP9 decoder mem resource 0x%lx size 0x%x\n",
9647 pdata->mem_start, pbi->buf_size);
9648 }
9649
9650 if (pdata->sys_info)
9651 pbi->vvp9_amstream_dec_info = *pdata->sys_info;
9652 else {
9653 pbi->vvp9_amstream_dec_info.width = 0;
9654 pbi->vvp9_amstream_dec_info.height = 0;
9655 pbi->vvp9_amstream_dec_info.rate = 30;
9656 }
9657 pbi->no_head = no_head;
9658#ifdef MULTI_INSTANCE_SUPPORT
9659 pbi->cma_dev = pdata->cma_dev;
9660#else
9661 cma_dev = pdata->cma_dev;
9662#endif
9663
9664#ifdef MULTI_INSTANCE_SUPPORT
9665 pdata->private = pbi;
9666 pdata->dec_status = vvp9_dec_status;
9667 pdata->set_isreset = vvp9_set_isreset;
9668 is_reset = 0;
9669 if (vvp9_init(pdata) < 0) {
9670#else
9671 if (vvp9_init(pbi) < 0) {
9672#endif
9673 pr_info("\namvdec_vp9 init failed.\n");
9674 vp9_local_uninit(pbi);
9675 uninit_mmu_buffers(pbi);
9676 vfree(pbi);
9677 pdata->dec_status = NULL;
9678 mutex_unlock(&vvp9_mutex);
9679 return -ENODEV;
9680 }
9681 /*set the max clk for smooth playing...*/
9682 hevc_source_changed(VFORMAT_VP9,
9683 4096, 2048, 60);
9684 mutex_unlock(&vvp9_mutex);
9685
9686 return 0;
9687}
9688
9689static void vdec_fence_release(struct VP9Decoder_s *pbi,
9690 struct vdec_sync *sync)
9691{
9692 ulong expires;
9693 int i;
9694
9695 /* notify signal to wake up all fences. */
9696 vdec_timeline_increase(sync, VF_POOL_SIZE);
9697
9698 expires = jiffies + msecs_to_jiffies(2000);
9699 while (!check_objs_all_signaled(sync)) {
9700 if (time_after(jiffies, expires)) {
9701 pr_err("wait fence signaled timeout.\n");
9702 break;
9703 }
9704 }
9705
9706 for (i = 0; i < VF_POOL_SIZE; i++) {
9707 struct vframe_s *vf = &pbi->vfpool[i];
9708
9709 if (vf->fence) {
9710 vdec_fence_put(vf->fence);
9711 vf->fence = NULL;
9712 }
9713 }
9714
9715 /* decreases refcnt of timeline. */
9716 vdec_timeline_put(sync);
9717}
9718
9719static int amvdec_vp9_remove(struct platform_device *pdev)
9720{
9721 struct VP9Decoder_s *pbi = gHevc;
9722 struct vdec_s *vdec = hw_to_vdec(pbi);
9723 int i;
9724
9725 if (debug)
9726 pr_info("amvdec_vp9_remove\n");
9727
9728 mutex_lock(&vvp9_mutex);
9729
9730 vvp9_stop(pbi);
9731
9732 hevc_source_changed(VFORMAT_VP9, 0, 0, 0);
9733
9734 if (vdec->parallel_dec == 1) {
9735 for (i = 0; i < FRAME_BUFFERS; i++) {
9736 vdec->free_canvas_ex(pbi->common.buffer_pool->
9737 frame_bufs[i].buf.y_canvas_index, vdec->id);
9738 vdec->free_canvas_ex(pbi->common.buffer_pool->
9739 frame_bufs[i].buf.uv_canvas_index, vdec->id);
9740 }
9741 }
9742
9743#ifdef DEBUG_PTS
9744 pr_info("pts missed %ld, pts hit %ld, duration %d\n",
9745 pbi->pts_missed, pbi->pts_hit, pbi->frame_dur);
9746#endif
9747 mem_map_mode = 0;
9748
9749 if (pbi->enable_fence)
9750 vdec_fence_release(pbi, &vdec->sync);
9751
9752 vfree(pbi);
9753 mutex_unlock(&vvp9_mutex);
9754
9755 return 0;
9756}
9757
9758/****************************************/
9759#ifdef CONFIG_PM
9760static int vp9_suspend(struct device *dev)
9761{
9762 amhevc_suspend(to_platform_device(dev), dev->power.power_state);
9763 return 0;
9764}
9765
9766static int vp9_resume(struct device *dev)
9767{
9768 amhevc_resume(to_platform_device(dev));
9769 return 0;
9770}
9771
9772static const struct dev_pm_ops vp9_pm_ops = {
9773 SET_SYSTEM_SLEEP_PM_OPS(vp9_suspend, vp9_resume)
9774};
9775#endif
9776
9777static struct platform_driver amvdec_vp9_driver = {
9778 .probe = amvdec_vp9_probe,
9779 .remove = amvdec_vp9_remove,
9780 .driver = {
9781 .name = DRIVER_NAME,
9782#ifdef CONFIG_PM
9783 .pm = &vp9_pm_ops,
9784#endif
9785 }
9786};
9787
9788static struct codec_profile_t amvdec_vp9_profile = {
9789 .name = "vp9",
9790 .profile = ""
9791};
9792
9793static struct codec_profile_t amvdec_vp9_profile_mult;
9794
9795static unsigned char get_data_check_sum
9796 (struct VP9Decoder_s *pbi, int size)
9797{
9798 int jj;
9799 int sum = 0;
9800 u8 *data = NULL;
9801
9802 if (!pbi->chunk->block->is_mapped)
9803 data = codec_mm_vmap(pbi->chunk->block->start +
9804 pbi->chunk->offset, size);
9805 else
9806 data = ((u8 *)pbi->chunk->block->start_virt) +
9807 pbi->chunk->offset;
9808
9809 for (jj = 0; jj < size; jj++)
9810 sum += data[jj];
9811
9812 if (!pbi->chunk->block->is_mapped)
9813 codec_mm_unmap_phyaddr(data);
9814 return sum;
9815}
9816
9817static void dump_data(struct VP9Decoder_s *pbi, int size)
9818{
9819 int jj;
9820 u8 *data = NULL;
9821 int padding_size = pbi->chunk->offset &
9822 (VDEC_FIFO_ALIGN - 1);
9823
9824 if (!pbi->chunk->block->is_mapped)
9825 data = codec_mm_vmap(pbi->chunk->block->start +
9826 pbi->chunk->offset, size);
9827 else
9828 data = ((u8 *)pbi->chunk->block->start_virt) +
9829 pbi->chunk->offset;
9830
9831 vp9_print(pbi, 0, "padding: ");
9832 for (jj = padding_size; jj > 0; jj--)
9833 vp9_print_cont(pbi,
9834 0,
9835 "%02x ", *(data - jj));
9836 vp9_print_cont(pbi, 0, "data adr %p\n",
9837 data);
9838
9839 for (jj = 0; jj < size; jj++) {
9840 if ((jj & 0xf) == 0)
9841 vp9_print(pbi,
9842 0,
9843 "%06x:", jj);
9844 vp9_print_cont(pbi,
9845 0,
9846 "%02x ", data[jj]);
9847 if (((jj + 1) & 0xf) == 0)
9848 vp9_print(pbi,
9849 0,
9850 "\n");
9851 }
9852 vp9_print(pbi,
9853 0,
9854 "\n");
9855
9856 if (!pbi->chunk->block->is_mapped)
9857 codec_mm_unmap_phyaddr(data);
9858}
9859
9860static void vp9_work(struct work_struct *work)
9861{
9862 struct VP9Decoder_s *pbi = container_of(work,
9863 struct VP9Decoder_s, work);
9864 struct vdec_s *vdec = hw_to_vdec(pbi);
9865 /* finished decoding one frame or error,
9866 * notify vdec core to switch context
9867 */
9868 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9869 "%s dec_result %d %x %x %x\n",
9870 __func__,
9871 pbi->dec_result,
9872 READ_VREG(HEVC_STREAM_LEVEL),
9873 READ_VREG(HEVC_STREAM_WR_PTR),
9874 READ_VREG(HEVC_STREAM_RD_PTR));
9875
9876 if (pbi->dec_result == DEC_INIT_PICLIST) {
9877 init_pic_list(pbi);
9878 pbi->pic_list_init_done = true;
9879 return;
9880 }
9881
9882 if (pbi->dec_result == DEC_RESULT_NEED_MORE_BUFFER) {
9883 reset_process_time(pbi);
9884 if (!get_free_buf_count(pbi)) {
9885 pbi->dec_result = DEC_RESULT_NEED_MORE_BUFFER;
9886 vdec_schedule_work(&pbi->work);
9887 } else {
9888 int i;
9889
9890 if (pbi->mmu_enable)
9891 vp9_recycle_mmu_buf_tail(pbi);
9892
9893 if (pbi->frame_count > 0)
9894 vp9_bufmgr_postproc(pbi);
9895
9896 for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
9897 int ii;
9898 for (ii = 0; ii < 4; ii++)
9899 pbi->vp9_param.l.data[i + ii] =
9900 pbi->rpm_ptr[i + 3 - ii];
9901 }
9902 continue_decoding(pbi);
9903 pbi->postproc_done = 0;
9904 pbi->process_busy = 0;
9905
9906 start_process_time(pbi);
9907 }
9908 return;
9909 }
9910
9911 if (((pbi->dec_result == DEC_RESULT_GET_DATA) ||
9912 (pbi->dec_result == DEC_RESULT_GET_DATA_RETRY))
9913 && (hw_to_vdec(pbi)->next_status !=
9914 VDEC_STATUS_DISCONNECTED)) {
9915 if (!vdec_has_more_input(vdec)) {
9916 pbi->dec_result = DEC_RESULT_EOS;
9917 vdec_schedule_work(&pbi->work);
9918 return;
9919 }
9920
9921 if (pbi->dec_result == DEC_RESULT_GET_DATA) {
9922 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9923 "%s DEC_RESULT_GET_DATA %x %x %x\n",
9924 __func__,
9925 READ_VREG(HEVC_STREAM_LEVEL),
9926 READ_VREG(HEVC_STREAM_WR_PTR),
9927 READ_VREG(HEVC_STREAM_RD_PTR));
9928 vdec_vframe_dirty(vdec, pbi->chunk);
9929 vdec_clean_input(vdec);
9930 }
9931
9932 if (get_free_buf_count(pbi) >=
9933 pbi->run_ready_min_buf_num) {
9934 int r;
9935 int decode_size;
9936 r = vdec_prepare_input(vdec, &pbi->chunk);
9937 if (r < 0) {
9938 pbi->dec_result = DEC_RESULT_GET_DATA_RETRY;
9939
9940 vp9_print(pbi,
9941 PRINT_FLAG_VDEC_DETAIL,
9942 "amvdec_vh265: Insufficient data\n");
9943
9944 vdec_schedule_work(&pbi->work);
9945 return;
9946 }
9947 pbi->dec_result = DEC_RESULT_NONE;
9948 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9949 "%s: chunk size 0x%x sum 0x%x\n",
9950 __func__, r,
9951 (debug & PRINT_FLAG_VDEC_STATUS) ?
9952 get_data_check_sum(pbi, r) : 0
9953 );
9954
9955 if (debug & PRINT_FLAG_VDEC_DATA)
9956 dump_data(pbi, pbi->chunk->size);
9957
9958 decode_size = pbi->chunk->size +
9959 (pbi->chunk->offset & (VDEC_FIFO_ALIGN - 1));
9960
9961 WRITE_VREG(HEVC_DECODE_SIZE,
9962 READ_VREG(HEVC_DECODE_SIZE) + decode_size);
9963
9964 vdec_enable_input(vdec);
9965
9966 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
9967
9968 start_process_time(pbi);
9969
9970 } else{
9971 pbi->dec_result = DEC_RESULT_GET_DATA_RETRY;
9972
9973 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9974 "amvdec_vh265: Insufficient data\n");
9975
9976 vdec_schedule_work(&pbi->work);
9977 }
9978 return;
9979 } else if (pbi->dec_result == DEC_RESULT_DONE) {
9980#ifdef SUPPORT_FB_DECODING
9981 if (pbi->used_stage_buf_num > 0) {
9982#ifndef FB_DECODING_TEST_SCHEDULE
9983 if (!is_s2_decoding_finished(pbi)) {
9984 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9985 "s2 decoding not done, check again later\n");
9986 vdec_schedule_work(&pbi->work);
9987 }
9988#endif
9989 inc_s2_pos(pbi);
9990 if (mcrcc_cache_alg_flag)
9991 dump_hit_rate(pbi);
9992 }
9993#endif
9994 /* if (!pbi->ctx_valid)
9995 pbi->ctx_valid = 1; */
9996 pbi->slice_idx++;
9997 pbi->frame_count++;
9998 pbi->process_state = PROC_STATE_INIT;
9999 decode_frame_count[pbi->index] = pbi->frame_count;
10000
10001 if (pbi->mmu_enable)
10002 pbi->used_4k_num =
10003 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
10004 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
10005 "%s (===> %d) dec_result %d %x %x %x shiftbytes 0x%x decbytes 0x%x\n",
10006 __func__,
10007 pbi->frame_count,
10008 pbi->dec_result,
10009 READ_VREG(HEVC_STREAM_LEVEL),
10010 READ_VREG(HEVC_STREAM_WR_PTR),
10011 READ_VREG(HEVC_STREAM_RD_PTR),
10012 READ_VREG(HEVC_SHIFT_BYTE_COUNT),
10013 READ_VREG(HEVC_SHIFT_BYTE_COUNT) -
10014 pbi->start_shift_bytes
10015 );
10016 vdec_vframe_dirty(hw_to_vdec(pbi), pbi->chunk);
10017 } else if (pbi->dec_result == DEC_RESULT_AGAIN) {
10018 /*
10019 stream base: stream buf empty or timeout
10020 frame base: vdec_prepare_input fail
10021 */
10022 if (!vdec_has_more_input(vdec)) {
10023 pbi->dec_result = DEC_RESULT_EOS;
10024 vdec_schedule_work(&pbi->work);
10025 return;
10026 }
10027 } else if (pbi->dec_result == DEC_RESULT_EOS) {
10028 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
10029 "%s: end of stream\n",
10030 __func__);
10031 pbi->eos = 1;
10032 vp9_bufmgr_postproc(pbi);
10033
10034 notify_v4l_eos(hw_to_vdec(pbi));
10035
10036 vdec_vframe_dirty(hw_to_vdec(pbi), pbi->chunk);
10037 } else if (pbi->dec_result == DEC_RESULT_FORCE_EXIT) {
10038 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
10039 "%s: force exit\n",
10040 __func__);
10041 if (pbi->stat & STAT_VDEC_RUN) {
10042 amhevc_stop();
10043 pbi->stat &= ~STAT_VDEC_RUN;
10044 }
10045
10046 if (pbi->stat & STAT_ISR_REG) {
10047#ifdef MULTI_INSTANCE_SUPPORT
10048 if (!pbi->m_ins_flag)
10049#endif
10050 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0);
10051 vdec_free_irq(VDEC_IRQ_0, (void *)pbi);
10052 pbi->stat &= ~STAT_ISR_REG;
10053 }
10054 }
10055 if (pbi->stat & STAT_VDEC_RUN) {
10056 amhevc_stop();
10057 pbi->stat &= ~STAT_VDEC_RUN;
10058 }
10059
10060 if (pbi->stat & STAT_TIMER_ARM) {
10061 del_timer_sync(&pbi->timer);
10062 pbi->stat &= ~STAT_TIMER_ARM;
10063 }
10064 /* mark itself has all HW resource released and input released */
10065#ifdef SUPPORT_FB_DECODING
10066 if (pbi->used_stage_buf_num > 0)
10067 vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_HEVC_BACK);
10068 else
10069 vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_VDEC_1
10070 | CORE_MASK_HEVC
10071 | CORE_MASK_HEVC_FRONT
10072 | CORE_MASK_HEVC_BACK
10073 );
10074#else
10075 if (vdec->parallel_dec == 1)
10076 vdec_core_finish_run(vdec, CORE_MASK_HEVC);
10077 else
10078 vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_VDEC_1
10079 | CORE_MASK_HEVC);
10080#endif
10081 trigger_schedule(pbi);
10082}
10083
10084static int vp9_hw_ctx_restore(struct VP9Decoder_s *pbi)
10085{
10086 /* new to do ... */
10087#if (!defined SUPPORT_FB_DECODING)
10088 vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
10089#elif (defined FB_DECODING_TEST_SCHEDULE)
10090 vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
10091#else
10092 if (pbi->used_stage_buf_num > 0)
10093 vvp9_prot_init(pbi, HW_MASK_FRONT);
10094 else
10095 vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
10096#endif
10097 return 0;
10098}
10099static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask)
10100{
10101 struct VP9Decoder_s *pbi =
10102 (struct VP9Decoder_s *)vdec->private;
10103 int tvp = vdec_secure(hw_to_vdec(pbi)) ?
10104 CODEC_MM_FLAGS_TVP : 0;
10105 unsigned long ret = 0;
10106
10107 if (!(pbi->pic_list_init_done && pbi->pic_list_init_done2) || pbi->eos)
10108 return ret;
10109 if (!pbi->first_sc_checked && pbi->mmu_enable) {
10110 int size = decoder_mmu_box_sc_check(pbi->mmu_box, tvp);
10111 pbi->first_sc_checked = 1;
10112 vp9_print(pbi, 0, "vp9 cached=%d need_size=%d speed= %d ms\n",
10113 size, (pbi->need_cache_size >> PAGE_SHIFT),
10114 (int)(get_jiffies_64() - pbi->sc_start_time) * 1000/HZ);
10115 }
10116
10117#ifdef SUPPORT_FB_DECODING
10118 if (pbi->used_stage_buf_num > 0) {
10119 if (mask & CORE_MASK_HEVC_FRONT) {
10120 if (get_free_stage_buf_num(pbi) > 0
10121 && mv_buf_available(pbi))
10122 ret |= CORE_MASK_HEVC_FRONT;
10123 }
10124 if (mask & CORE_MASK_HEVC_BACK) {
10125 if (s2_buf_available(pbi) &&
10126 (get_free_buf_count(pbi) >=
10127 pbi->run_ready_min_buf_num)) {
10128 ret |= CORE_MASK_HEVC_BACK;
10129 pbi->back_not_run_ready = 0;
10130 } else
10131 pbi->back_not_run_ready = 1;
10132#if 0
10133 if (get_free_buf_count(pbi) <
10134 run_ready_min_buf_num)
10135 dump_pic_list(pbi);
10136#endif
10137 }
10138 } else if (get_free_buf_count(pbi) >=
10139 pbi->run_ready_min_buf_num)
10140 ret = CORE_MASK_VDEC_1 | CORE_MASK_HEVC
10141 | CORE_MASK_HEVC_FRONT
10142 | CORE_MASK_HEVC_BACK;
10143
10144 if (ret & CORE_MASK_HEVC_FRONT)
10145 not_run_ready[pbi->index] = 0;
10146 else
10147 not_run_ready[pbi->index]++;
10148
10149 if (ret & CORE_MASK_HEVC_BACK)
10150 not_run2_ready[pbi->index] = 0;
10151 else
10152 not_run2_ready[pbi->index]++;
10153
10154 vp9_print(pbi,
10155 PRINT_FLAG_VDEC_DETAIL, "%s mask %lx=>%lx (%d %d %d %d)\r\n",
10156 __func__, mask, ret,
10157 get_free_stage_buf_num(pbi),
10158 mv_buf_available(pbi),
10159 s2_buf_available(pbi),
10160 get_free_buf_count(pbi)
10161 );
10162
10163 return ret;
10164
10165#else
10166 if (get_free_buf_count(pbi) >=
10167 pbi->run_ready_min_buf_num) {
10168 if (vdec->parallel_dec == 1)
10169 ret = CORE_MASK_HEVC;
10170 else
10171 ret = CORE_MASK_VDEC_1 | CORE_MASK_HEVC;
10172 }
10173
10174 if (pbi->is_used_v4l) {
10175 struct aml_vcodec_ctx *ctx =
10176 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
10177
10178 if (ctx->param_sets_from_ucode) {
10179 if (pbi->v4l_params_parsed) {
10180 if ((ctx->cap_pool.in < pbi->used_buf_num) &&
10181 v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx) <
10182 pbi->run_ready_min_buf_num)
10183 ret = 0;
10184 } else {
10185 if ((pbi->res_ch_flag == 1) &&
10186 ((ctx->state <= AML_STATE_INIT) ||
10187 (ctx->state >= AML_STATE_FLUSHING)))
10188 ret = 0;
10189 }
10190 } else if (ctx->cap_pool.in < ctx->dpb_size) {
10191 if (v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx) <
10192 pbi->run_ready_min_buf_num)
10193 ret = 0;
10194 }
10195 }
10196
10197 if (ret)
10198 not_run_ready[pbi->index] = 0;
10199 else
10200 not_run_ready[pbi->index]++;
10201
10202 vp9_print(pbi,
10203 PRINT_FLAG_VDEC_DETAIL, "%s mask %lx=>%lx\r\n",
10204 __func__, mask, ret);
10205 return ret;
10206#endif
10207}
10208
10209static void vp9_frame_mode_pts_save(struct VP9Decoder_s *pbi)
10210{
10211 int i = 0;
10212
10213 if (pbi->chunk == NULL)
10214 return;
10215 vp9_print(pbi, VP9_DEBUG_OUT_PTS,
10216 "run front: pts %d, pts64 %lld\n", pbi->chunk->pts, pbi->chunk->pts64);
10217 for (i = (FRAME_BUFFERS - 1); i > 0; i--) {
10218 pbi->frame_mode_pts_save[i] = pbi->frame_mode_pts_save[i - 1];
10219 pbi->frame_mode_pts64_save[i] = pbi->frame_mode_pts64_save[i - 1];
10220 }
10221 pbi->frame_mode_pts_save[0] = pbi->chunk->pts;
10222 pbi->frame_mode_pts64_save[0] = pbi->chunk->pts64;
10223}
10224
10225static void run_front(struct vdec_s *vdec)
10226{
10227 struct VP9Decoder_s *pbi =
10228 (struct VP9Decoder_s *)vdec->private;
10229 int ret, size;
10230
10231 run_count[pbi->index]++;
10232 /* pbi->chunk = vdec_prepare_input(vdec); */
10233#if (!defined SUPPORT_FB_DECODING)
10234 hevc_reset_core(vdec);
10235#elif (defined FB_DECODING_TEST_SCHEDULE)
10236 hevc_reset_core(vdec);
10237#else
10238 if (pbi->used_stage_buf_num > 0)
10239 fb_reset_core(vdec, HW_MASK_FRONT);
10240 else
10241 hevc_reset_core(vdec);
10242#endif
10243
10244 size = vdec_prepare_input(vdec, &pbi->chunk);
10245 if (size < 0) {
10246 input_empty[pbi->index]++;
10247
10248 pbi->dec_result = DEC_RESULT_AGAIN;
10249
10250 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
10251 "ammvdec_vh265: Insufficient data\n");
10252
10253 vdec_schedule_work(&pbi->work);
10254 return;
10255 }
10256
10257 input_empty[pbi->index] = 0;
10258 pbi->dec_result = DEC_RESULT_NONE;
10259 pbi->start_shift_bytes = READ_VREG(HEVC_SHIFT_BYTE_COUNT);
10260
10261 vp9_frame_mode_pts_save(pbi);
10262
10263 if (debug & PRINT_FLAG_VDEC_STATUS) {
10264 int ii;
10265 vp9_print(pbi, 0,
10266 "%s (%d): size 0x%x (0x%x 0x%x) sum 0x%x (%x %x %x %x %x) bytes 0x%x",
10267 __func__,
10268 pbi->frame_count, size,
10269 pbi->chunk ? pbi->chunk->size : 0,
10270 pbi->chunk ? pbi->chunk->offset : 0,
10271 pbi->chunk ? ((vdec_frame_based(vdec) &&
10272 (debug & PRINT_FLAG_VDEC_STATUS)) ?
10273 get_data_check_sum(pbi, size) : 0) : 0,
10274 READ_VREG(HEVC_STREAM_START_ADDR),
10275 READ_VREG(HEVC_STREAM_END_ADDR),
10276 READ_VREG(HEVC_STREAM_LEVEL),
10277 READ_VREG(HEVC_STREAM_WR_PTR),
10278 READ_VREG(HEVC_STREAM_RD_PTR),
10279 pbi->start_shift_bytes);
10280 if (vdec_frame_based(vdec) && pbi->chunk) {
10281 u8 *data = NULL;
10282
10283 if (!pbi->chunk->block->is_mapped)
10284 data = codec_mm_vmap(pbi->chunk->block->start +
10285 pbi->chunk->offset, 8);
10286 else
10287 data = ((u8 *)pbi->chunk->block->start_virt) +
10288 pbi->chunk->offset;
10289
10290 vp9_print_cont(pbi, 0, "data adr %p:",
10291 data);
10292 for (ii = 0; ii < 8; ii++)
10293 vp9_print_cont(pbi, 0, "%02x ",
10294 data[ii]);
10295
10296 if (!pbi->chunk->block->is_mapped)
10297 codec_mm_unmap_phyaddr(data);
10298 }
10299 vp9_print_cont(pbi, 0, "\r\n");
10300 }
10301 if (vdec->mc_loaded) {
10302 /*firmware have load before,
10303 and not changes to another.
10304 ignore reload.
10305 */
10306 } else {
10307 ret = amhevc_loadmc_ex(VFORMAT_VP9, NULL, pbi->fw->data);
10308 if (ret < 0) {
10309 amhevc_disable();
10310 vp9_print(pbi, PRINT_FLAG_ERROR,
10311 "VP9: the %s fw loading failed, err: %x\n",
10312 tee_enabled() ? "TEE" : "local", ret);
10313 pbi->dec_result = DEC_RESULT_FORCE_EXIT;
10314 vdec_schedule_work(&pbi->work);
10315 return;
10316 }
10317 vdec->mc_loaded = 1;
10318 vdec->mc_type = VFORMAT_VP9;
10319 }
10320
10321 if (vp9_hw_ctx_restore(pbi) < 0) {
10322 vdec_schedule_work(&pbi->work);
10323 return;
10324 }
10325
10326 vdec_enable_input(vdec);
10327
10328 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
10329
10330 if (vdec_frame_based(vdec)) {
10331 if (debug & PRINT_FLAG_VDEC_DATA)
10332 dump_data(pbi, pbi->chunk->size);
10333
10334 WRITE_VREG(HEVC_SHIFT_BYTE_COUNT, 0);
10335 size = pbi->chunk->size +
10336 (pbi->chunk->offset & (VDEC_FIFO_ALIGN - 1));
10337 if (vdec->mvfrm)
10338 vdec->mvfrm->frame_size = pbi->chunk->size;
10339 }
10340 WRITE_VREG(HEVC_DECODE_SIZE, size);
10341 WRITE_VREG(HEVC_DECODE_COUNT, pbi->slice_idx);
10342 pbi->init_flag = 1;
10343
10344 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
10345 "%s: start hevc (%x %x %x)\n",
10346 __func__,
10347 READ_VREG(HEVC_DEC_STATUS_REG),
10348 READ_VREG(HEVC_MPC_E),
10349 READ_VREG(HEVC_MPSR));
10350
10351 start_process_time(pbi);
10352 mod_timer(&pbi->timer, jiffies);
10353 pbi->stat |= STAT_TIMER_ARM;
10354 pbi->stat |= STAT_ISR_REG;
10355 amhevc_start();
10356 pbi->stat |= STAT_VDEC_RUN;
10357}
10358
10359#ifdef SUPPORT_FB_DECODING
10360static void mpred_process(struct VP9Decoder_s *pbi)
10361{
10362 union param_u *params = &pbi->s1_param;
10363 unsigned char use_prev_frame_mvs =
10364 !params->p.error_resilient_mode &&
10365 params->p.width == pbi->s1_width &&
10366 params->p.height == pbi->s1_height &&
10367 !pbi->s1_intra_only &&
10368 pbi->s1_last_show_frame &&
10369 (pbi->s1_frame_type != KEY_FRAME);
10370 pbi->s1_width = params->p.width;
10371 pbi->s1_height = params->p.height;
10372 pbi->s1_frame_type = params->p.frame_type;
10373 pbi->s1_intra_only =
10374 (params->p.show_frame ||
10375 params->p.show_existing_frame)
10376 ? 0 : params->p.intra_only;
10377 if ((pbi->s1_frame_type != KEY_FRAME)
10378 && (!pbi->s1_intra_only)) {
10379 unsigned int data32;
10380 int mpred_mv_rd_end_addr;
10381
10382 mpred_mv_rd_end_addr =
10383 pbi->s1_mpred_mv_wr_start_addr_pre
10384 + (pbi->lcu_total * MV_MEM_UNIT);
10385
10386 WRITE_VREG(HEVC_MPRED_CTRL3, 0x24122412);
10387 WRITE_VREG(HEVC_MPRED_ABV_START_ADDR,
10388 pbi->work_space_buf->
10389 mpred_above.buf_start);
10390
10391 data32 = READ_VREG(HEVC_MPRED_CTRL4);
10392
10393 data32 &= (~(1 << 6));
10394 data32 |= (use_prev_frame_mvs << 6);
10395 WRITE_VREG(HEVC_MPRED_CTRL4, data32);
10396
10397 WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR,
10398 pbi->s1_mpred_mv_wr_start_addr);
10399 WRITE_VREG(HEVC_MPRED_MV_WPTR,
10400 pbi->s1_mpred_mv_wr_start_addr);
10401
10402 WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR,
10403 pbi->s1_mpred_mv_wr_start_addr_pre);
10404 WRITE_VREG(HEVC_MPRED_MV_RPTR,
10405 pbi->s1_mpred_mv_wr_start_addr_pre);
10406
10407 WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR,
10408 mpred_mv_rd_end_addr);
10409
10410 } else
10411 clear_mpred_hw(pbi);
10412
10413 if (!params->p.show_existing_frame) {
10414 pbi->s1_mpred_mv_wr_start_addr_pre =
10415 pbi->s1_mpred_mv_wr_start_addr;
10416 pbi->s1_last_show_frame =
10417 params->p.show_frame;
10418 if (pbi->s1_mv_buf_index_pre_pre != MV_BUFFER_NUM)
10419 put_mv_buf(pbi, &pbi->s1_mv_buf_index_pre_pre);
10420 pbi->s1_mv_buf_index_pre_pre =
10421 pbi->s1_mv_buf_index_pre;
10422 pbi->s1_mv_buf_index_pre = pbi->s1_mv_buf_index;
10423 } else
10424 put_mv_buf(pbi, &pbi->s1_mv_buf_index);
10425}
10426
10427static void vp9_s1_work(struct work_struct *s1_work)
10428{
10429 struct VP9Decoder_s *pbi = container_of(s1_work,
10430 struct VP9Decoder_s, s1_work);
10431 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
10432 "%s dec_s1_result %d\n",
10433 __func__,
10434 pbi->dec_s1_result);
10435
10436#ifdef FB_DECODING_TEST_SCHEDULE
10437 if (pbi->dec_s1_result ==
10438 DEC_S1_RESULT_TEST_TRIGGER_DONE) {
10439 pbi->s1_test_cmd = TEST_SET_PIC_DONE;
10440 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1);
10441 }
10442#endif
10443 if (pbi->dec_s1_result == DEC_S1_RESULT_DONE ||
10444 pbi->dec_s1_result == DEC_S1_RESULT_FORCE_EXIT) {
10445
10446 vdec_core_finish_run(hw_to_vdec(pbi),
10447 CORE_MASK_HEVC_FRONT);
10448
10449 trigger_schedule(pbi);
10450 /*pbi->dec_s1_result = DEC_S1_RESULT_NONE;*/
10451 }
10452
10453}
10454
10455static void run_back(struct vdec_s *vdec)
10456{
10457 struct VP9Decoder_s *pbi =
10458 (struct VP9Decoder_s *)vdec->private;
10459 int i;
10460 run2_count[pbi->index]++;
10461 if (debug & PRINT_FLAG_VDEC_STATUS) {
10462 vp9_print(pbi, 0,
10463 "%s", __func__);
10464 }
10465 pbi->run2_busy = 1;
10466#ifndef FB_DECODING_TEST_SCHEDULE
10467 fb_reset_core(vdec, HW_MASK_BACK);
10468
10469 vvp9_prot_init(pbi, HW_MASK_BACK);
10470#endif
10471 vp9_recycle_mmu_buf_tail(pbi);
10472
10473 if (pbi->frame_count > 0)
10474 vp9_bufmgr_postproc(pbi);
10475
10476 if (get_s2_buf(pbi) >= 0) {
10477 for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
10478 int ii;
10479 for (ii = 0; ii < 4; ii++)
10480 pbi->vp9_param.l.data[i + ii] =
10481 pbi->s2_buf->rpm[i + 3 - ii];
10482 }
10483#ifndef FB_DECODING_TEST_SCHEDULE
10484 WRITE_VREG(HEVC_ASSIST_FBD_MMU_MAP_ADDR,
10485 pbi->stage_mmu_map_phy_addr +
10486 pbi->s2_buf->index * STAGE_MMU_MAP_SIZE);
10487#endif
10488 continue_decoding(pbi);
10489 }
10490 pbi->run2_busy = 0;
10491}
10492#endif
10493
10494static void run(struct vdec_s *vdec, unsigned long mask,
10495 void (*callback)(struct vdec_s *, void *), void *arg)
10496{
10497 struct VP9Decoder_s *pbi =
10498 (struct VP9Decoder_s *)vdec->private;
10499
10500 vp9_print(pbi,
10501 PRINT_FLAG_VDEC_DETAIL, "%s mask %lx\r\n",
10502 __func__, mask);
10503
10504 if (vdec->mvfrm)
10505 vdec->mvfrm->hw_decode_start = local_clock();
10506 run_count[pbi->index]++;
10507 pbi->vdec_cb_arg = arg;
10508 pbi->vdec_cb = callback;
10509 pbi->one_package_frame_cnt = 0;
10510#ifdef SUPPORT_FB_DECODING
10511 if ((mask & CORE_MASK_HEVC) ||
10512 (mask & CORE_MASK_HEVC_FRONT))
10513 run_front(vdec);
10514
10515 if ((pbi->used_stage_buf_num > 0)
10516 && (mask & CORE_MASK_HEVC_BACK))
10517 run_back(vdec);
10518#else
10519 run_front(vdec);
10520#endif
10521
10522}
10523
10524static void init_frame_bufs(struct VP9Decoder_s *pbi)
10525{
10526 struct vdec_s *vdec = hw_to_vdec(pbi);
10527 struct VP9_Common_s *const cm = &pbi->common;
10528 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
10529 int i;
10530
10531 for (i = 0; i < pbi->used_buf_num; ++i) {
10532 frame_bufs[i].ref_count = 0;
10533 frame_bufs[i].buf.vf_ref = 0;
10534 frame_bufs[i].buf.decode_idx = 0;
10535 frame_bufs[i].buf.cma_alloc_addr = 0;
10536 frame_bufs[i].buf.index = i;
10537 frame_bufs[i].buf.vframe_bound = 0;
10538 }
10539
10540 if (vdec->parallel_dec == 1) {
10541 for (i = 0; i < FRAME_BUFFERS; i++) {
10542 vdec->free_canvas_ex
10543 (pbi->common.buffer_pool->frame_bufs[i].buf.y_canvas_index,
10544 vdec->id);
10545 vdec->free_canvas_ex
10546 (pbi->common.buffer_pool->frame_bufs[i].buf.uv_canvas_index,
10547 vdec->id);
10548 }
10549 }
10550}
10551
10552static void reset(struct vdec_s *vdec)
10553{
10554 struct VP9Decoder_s *pbi =
10555 (struct VP9Decoder_s *)vdec->private;
10556
10557 cancel_work_sync(&pbi->work);
10558 if (pbi->stat & STAT_VDEC_RUN) {
10559 amhevc_stop();
10560 pbi->stat &= ~STAT_VDEC_RUN;
10561 }
10562
10563 if (pbi->stat & STAT_TIMER_ARM) {
10564 del_timer_sync(&pbi->timer);
10565 pbi->stat &= ~STAT_TIMER_ARM;
10566 }
10567 pbi->dec_result = DEC_RESULT_NONE;
10568 reset_process_time(pbi);
10569 vp9_local_uninit(pbi);
10570 if (vvp9_local_init(pbi) < 0)
10571 vp9_print(pbi, 0, "%s local_init failed \r\n", __func__);
10572 init_frame_bufs(pbi);
10573
10574 pbi->eos = 0;
10575
10576 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL, "%s\r\n", __func__);
10577}
10578
10579static irqreturn_t vp9_irq_cb(struct vdec_s *vdec, int irq)
10580{
10581 struct VP9Decoder_s *pbi =
10582 (struct VP9Decoder_s *)vdec->private;
10583 return vvp9_isr(0, pbi);
10584}
10585
10586static irqreturn_t vp9_threaded_irq_cb(struct vdec_s *vdec, int irq)
10587{
10588 struct VP9Decoder_s *pbi =
10589 (struct VP9Decoder_s *)vdec->private;
10590 return vvp9_isr_thread_fn(0, pbi);
10591}
10592
10593static void vp9_dump_state(struct vdec_s *vdec)
10594{
10595 struct VP9Decoder_s *pbi =
10596 (struct VP9Decoder_s *)vdec->private;
10597 struct VP9_Common_s *const cm = &pbi->common;
10598 int i;
10599 vp9_print(pbi, 0, "====== %s\n", __func__);
10600
10601 vp9_print(pbi, 0,
10602 "width/height (%d/%d), used_buf_num %d\n",
10603 cm->width,
10604 cm->height,
10605 pbi->used_buf_num
10606 );
10607
10608 vp9_print(pbi, 0,
10609 "is_framebase(%d), eos %d, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d low_latency %d no_head %d \n",
10610 input_frame_based(vdec),
10611 pbi->eos,
10612 pbi->dec_result,
10613 decode_frame_count[pbi->index],
10614 display_frame_count[pbi->index],
10615 run_count[pbi->index],
10616 not_run_ready[pbi->index],
10617 input_empty[pbi->index],
10618 pbi->low_latency_flag,
10619 pbi->no_head
10620 );
10621
10622 if (vf_get_receiver(vdec->vf_provider_name)) {
10623 enum receviver_start_e state =
10624 vf_notify_receiver(vdec->vf_provider_name,
10625 VFRAME_EVENT_PROVIDER_QUREY_STATE,
10626 NULL);
10627 vp9_print(pbi, 0,
10628 "\nreceiver(%s) state %d\n",
10629 vdec->vf_provider_name,
10630 state);
10631 }
10632
10633 vp9_print(pbi, 0,
10634 "%s, newq(%d/%d), dispq(%d/%d), vf prepare/get/put (%d/%d/%d), free_buf_count %d (min %d for run_ready)\n",
10635 __func__,
10636 kfifo_len(&pbi->newframe_q),
10637 VF_POOL_SIZE,
10638 kfifo_len(&pbi->display_q),
10639 VF_POOL_SIZE,
10640 pbi->vf_pre_count,
10641 pbi->vf_get_count,
10642 pbi->vf_put_count,
10643 get_free_buf_count(pbi),
10644 pbi->run_ready_min_buf_num
10645 );
10646
10647 dump_pic_list(pbi);
10648
10649 for (i = 0; i < MAX_BUF_NUM; i++) {
10650 vp9_print(pbi, 0,
10651 "mv_Buf(%d) start_adr 0x%x size 0x%x used %d\n",
10652 i,
10653 pbi->m_mv_BUF[i].start_adr,
10654 pbi->m_mv_BUF[i].size,
10655 pbi->m_mv_BUF[i].used_flag);
10656 }
10657
10658 vp9_print(pbi, 0,
10659 "HEVC_DEC_STATUS_REG=0x%x\n",
10660 READ_VREG(HEVC_DEC_STATUS_REG));
10661 vp9_print(pbi, 0,
10662 "HEVC_MPC_E=0x%x\n",
10663 READ_VREG(HEVC_MPC_E));
10664 vp9_print(pbi, 0,
10665 "DECODE_MODE=0x%x\n",
10666 READ_VREG(DECODE_MODE));
10667 vp9_print(pbi, 0,
10668 "NAL_SEARCH_CTL=0x%x\n",
10669 READ_VREG(NAL_SEARCH_CTL));
10670 vp9_print(pbi, 0,
10671 "HEVC_PARSER_LCU_START=0x%x\n",
10672 READ_VREG(HEVC_PARSER_LCU_START));
10673 vp9_print(pbi, 0,
10674 "HEVC_DECODE_SIZE=0x%x\n",
10675 READ_VREG(HEVC_DECODE_SIZE));
10676 vp9_print(pbi, 0,
10677 "HEVC_SHIFT_BYTE_COUNT=0x%x\n",
10678 READ_VREG(HEVC_SHIFT_BYTE_COUNT));
10679 vp9_print(pbi, 0,
10680 "HEVC_STREAM_START_ADDR=0x%x\n",
10681 READ_VREG(HEVC_STREAM_START_ADDR));
10682 vp9_print(pbi, 0,
10683 "HEVC_STREAM_END_ADDR=0x%x\n",
10684 READ_VREG(HEVC_STREAM_END_ADDR));
10685 vp9_print(pbi, 0,
10686 "HEVC_STREAM_LEVEL=0x%x\n",
10687 READ_VREG(HEVC_STREAM_LEVEL));
10688 vp9_print(pbi, 0,
10689 "HEVC_STREAM_WR_PTR=0x%x\n",
10690 READ_VREG(HEVC_STREAM_WR_PTR));
10691 vp9_print(pbi, 0,
10692 "HEVC_STREAM_RD_PTR=0x%x\n",
10693 READ_VREG(HEVC_STREAM_RD_PTR));
10694 vp9_print(pbi, 0,
10695 "PARSER_VIDEO_RP=0x%x\n",
10696 STBUF_READ(&vdec->vbuf, get_rp));
10697 vp9_print(pbi, 0,
10698 "PARSER_VIDEO_WP=0x%x\n",
10699 STBUF_READ(&vdec->vbuf, get_wp));
10700
10701 if (input_frame_based(vdec) &&
10702 (debug & PRINT_FLAG_VDEC_DATA)
10703 ) {
10704 int jj;
10705 if (pbi->chunk && pbi->chunk->block &&
10706 pbi->chunk->size > 0) {
10707 u8 *data = NULL;
10708
10709 if (!pbi->chunk->block->is_mapped)
10710 data = codec_mm_vmap(
10711 pbi->chunk->block->start +
10712 pbi->chunk->offset,
10713 pbi->chunk->size);
10714 else
10715 data = ((u8 *)pbi->chunk->block->start_virt)
10716 + pbi->chunk->offset;
10717 vp9_print(pbi, 0,
10718 "frame data size 0x%x\n",
10719 pbi->chunk->size);
10720 for (jj = 0; jj < pbi->chunk->size; jj++) {
10721 if ((jj & 0xf) == 0)
10722 vp9_print(pbi, 0,
10723 "%06x:", jj);
10724 vp9_print_cont(pbi, 0,
10725 "%02x ", data[jj]);
10726 if (((jj + 1) & 0xf) == 0)
10727 vp9_print_cont(pbi, 0,
10728 "\n");
10729 }
10730
10731 if (!pbi->chunk->block->is_mapped)
10732 codec_mm_unmap_phyaddr(data);
10733 }
10734 }
10735
10736}
10737
10738static int ammvdec_vp9_probe(struct platform_device *pdev)
10739{
10740 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
10741 int ret;
10742 int config_val;
10743 struct vframe_content_light_level_s content_light_level;
10744 struct vframe_master_display_colour_s vf_dp;
10745
10746 struct BUF_s BUF[MAX_BUF_NUM];
10747 struct VP9Decoder_s *pbi = NULL;
10748 pr_debug("%s\n", __func__);
10749
10750 if (pdata == NULL) {
10751 pr_info("\nammvdec_vp9 memory resource undefined.\n");
10752 return -EFAULT;
10753 }
10754 /*pbi = (struct VP9Decoder_s *)devm_kzalloc(&pdev->dev,
10755 sizeof(struct VP9Decoder_s), GFP_KERNEL);*/
10756 memset(&vf_dp, 0, sizeof(struct vframe_master_display_colour_s));
10757 pbi = vmalloc(sizeof(struct VP9Decoder_s));
10758 if (pbi == NULL) {
10759 pr_info("\nammvdec_vp9 device data allocation failed\n");
10760 return -ENOMEM;
10761 }
10762 memset(pbi, 0, sizeof(struct VP9Decoder_s));
10763
10764 /* the ctx from v4l2 driver. */
10765 pbi->v4l2_ctx = pdata->private;
10766
10767 pdata->private = pbi;
10768 pdata->dec_status = vvp9_dec_status;
10769 /* pdata->set_trickmode = set_trickmode; */
10770 pdata->run_ready = run_ready;
10771 pdata->run = run;
10772 pdata->reset = reset;
10773 pdata->irq_handler = vp9_irq_cb;
10774 pdata->threaded_irq_handler = vp9_threaded_irq_cb;
10775 pdata->dump_state = vp9_dump_state;
10776
10777 memcpy(&BUF[0], &pbi->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
10778 memcpy(&pbi->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
10779
10780 pbi->index = pdev->id;
10781
10782 if (pdata->use_vfm_path)
10783 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
10784 VFM_DEC_PROVIDER_NAME);
10785 else
10786 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
10787 MULTI_INSTANCE_PROVIDER_NAME ".%02x", pdev->id & 0xff);
10788
10789 vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
10790 &vvp9_vf_provider, pbi);
10791
10792 pbi->provider_name = pdata->vf_provider_name;
10793 platform_set_drvdata(pdev, pdata);
10794
10795 pbi->platform_dev = pdev;
10796 pbi->video_signal_type = 0;
10797 pbi->m_ins_flag = 1;
10798 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX)
10799 pbi->stat |= VP9_TRIGGER_FRAME_ENABLE;
10800
10801 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
10802 pbi->max_pic_w = 8192;
10803 pbi->max_pic_h = 4608;
10804 } else {
10805 pbi->max_pic_w = 4096;
10806 pbi->max_pic_h = 2304;
10807 }
10808#if 1
10809 if ((debug & IGNORE_PARAM_FROM_CONFIG) == 0 &&
10810 pdata->config_len) {
10811#ifdef MULTI_INSTANCE_SUPPORT
10812 int vp9_buf_width = 0;
10813 int vp9_buf_height = 0;
10814 /*use ptr config for doubel_write_mode, etc*/
10815 vp9_print(pbi, 0, "pdata->config=%s\n", pdata->config);
10816 if (get_config_int(pdata->config, "vp9_double_write_mode",
10817 &config_val) == 0)
10818 pbi->double_write_mode = config_val;
10819 else
10820 pbi->double_write_mode = double_write_mode;
10821
10822 if (get_config_int(pdata->config, "save_buffer_mode",
10823 &config_val) == 0)
10824 pbi->save_buffer_mode = config_val;
10825 else
10826 pbi->save_buffer_mode = 0;
10827 if (get_config_int(pdata->config, "vp9_buf_width",
10828 &config_val) == 0) {
10829 vp9_buf_width = config_val;
10830 }
10831 if (get_config_int(pdata->config, "vp9_buf_height",
10832 &config_val) == 0) {
10833 vp9_buf_height = config_val;
10834 }
10835
10836 if (get_config_int(pdata->config, "no_head",
10837 &config_val) == 0)
10838 pbi->no_head = config_val;
10839 else
10840 pbi->no_head = no_head;
10841
10842 /*use ptr config for max_pic_w, etc*/
10843 if (get_config_int(pdata->config, "vp9_max_pic_w",
10844 &config_val) == 0) {
10845 pbi->max_pic_w = config_val;
10846 }
10847 if (get_config_int(pdata->config, "vp9_max_pic_h",
10848 &config_val) == 0) {
10849 pbi->max_pic_h = config_val;
10850 }
10851 if ((pbi->max_pic_w * pbi->max_pic_h)
10852 < (vp9_buf_width * vp9_buf_height)) {
10853 pbi->max_pic_w = vp9_buf_width;
10854 pbi->max_pic_h = vp9_buf_height;
10855 vp9_print(pbi, 0, "use buf resolution\n");
10856 }
10857
10858 if (get_config_int(pdata->config, "sidebind_type",
10859 &config_val) == 0)
10860 pbi->sidebind_type = config_val;
10861
10862 if (get_config_int(pdata->config, "sidebind_channel_id",
10863 &config_val) == 0)
10864 pbi->sidebind_channel_id = config_val;
10865
10866 if (get_config_int(pdata->config,
10867 "parm_v4l_codec_enable",
10868 &config_val) == 0)
10869 pbi->is_used_v4l = config_val;
10870
10871 if (get_config_int(pdata->config,
10872 "parm_v4l_buffer_margin",
10873 &config_val) == 0)
10874 pbi->dynamic_buf_num_margin = config_val;
10875
10876 if (get_config_int(pdata->config,
10877 "parm_v4l_canvas_mem_mode",
10878 &config_val) == 0)
10879 pbi->mem_map_mode = config_val;
10880
10881 if (get_config_int(pdata->config,
10882 "parm_enable_fence",
10883 &config_val) == 0)
10884 pbi->enable_fence = config_val;
10885
10886 if (get_config_int(pdata->config,
10887 "parm_fence_usage",
10888 &config_val) == 0)
10889 pbi->fence_usage = config_val;
10890#endif
10891 if (get_config_int(pdata->config, "HDRStaticInfo",
10892 &vf_dp.present_flag) == 0
10893 && vf_dp.present_flag == 1) {
10894 get_config_int(pdata->config, "mG.x",
10895 &vf_dp.primaries[0][0]);
10896 get_config_int(pdata->config, "mG.y",
10897 &vf_dp.primaries[0][1]);
10898 get_config_int(pdata->config, "mB.x",
10899 &vf_dp.primaries[1][0]);
10900 get_config_int(pdata->config, "mB.y",
10901 &vf_dp.primaries[1][1]);
10902 get_config_int(pdata->config, "mR.x",
10903 &vf_dp.primaries[2][0]);
10904 get_config_int(pdata->config, "mR.y",
10905 &vf_dp.primaries[2][1]);
10906 get_config_int(pdata->config, "mW.x",
10907 &vf_dp.white_point[0]);
10908 get_config_int(pdata->config, "mW.y",
10909 &vf_dp.white_point[1]);
10910 get_config_int(pdata->config, "mMaxDL",
10911 &vf_dp.luminance[0]);
10912 get_config_int(pdata->config, "mMinDL",
10913 &vf_dp.luminance[1]);
10914 vf_dp.content_light_level.present_flag = 1;
10915 get_config_int(pdata->config, "mMaxCLL",
10916 &content_light_level.max_content);
10917 get_config_int(pdata->config, "mMaxFALL",
10918 &content_light_level.max_pic_average);
10919 vf_dp.content_light_level = content_light_level;
10920 pbi->video_signal_type = (1 << 29)
10921 | (5 << 26) /* unspecified */
10922 | (0 << 25) /* limit */
10923 | (1 << 24) /* color available */
10924 | (9 << 16) /* 2020 */
10925 | (16 << 8) /* 2084 */
10926 | (9 << 0); /* 2020 */
10927 }
10928 pbi->vf_dp = vf_dp;
10929 } else
10930#endif
10931 {
10932 /*pbi->vvp9_amstream_dec_info.width = 0;
10933 pbi->vvp9_amstream_dec_info.height = 0;
10934 pbi->vvp9_amstream_dec_info.rate = 30;*/
10935 pbi->double_write_mode = double_write_mode;
10936 }
10937
10938 if (no_head & 0x10) {
10939 pbi->no_head = (no_head & 0xf);
10940 }
10941
10942 if (!pbi->is_used_v4l) {
10943 pbi->mem_map_mode = mem_map_mode;
10944 }
10945 pbi->run_ready_min_buf_num = run_ready_min_buf_num;
10946 if (is_oversize(pbi->max_pic_w, pbi->max_pic_h)) {
10947 pr_err("over size: %dx%d, probe failed\n",
10948 pbi->max_pic_w, pbi->max_pic_h);
10949 return -1;
10950 }
10951
10952 if (force_config_fence) {
10953 pbi->enable_fence = true;
10954 pbi->fence_usage =
10955 (force_config_fence >> 4) & 0xf;
10956 if (force_config_fence & 0x2)
10957 pbi->enable_fence = false;
10958 vp9_print(pbi, 0, "enable fence: %d, fence usage: %d\n",
10959 pbi->enable_fence, pbi->fence_usage);
10960 }
10961
10962 if (pbi->enable_fence)
10963 pdata->sync.usage = pbi->fence_usage;
10964
10965 pbi->mmu_enable = 1;
10966 video_signal_type = pbi->video_signal_type;
10967
10968 if (pdata->sys_info) {
10969 pbi->vvp9_amstream_dec_info = *pdata->sys_info;
10970 } else {
10971 pbi->vvp9_amstream_dec_info.width = 0;
10972 pbi->vvp9_amstream_dec_info.height = 0;
10973 pbi->vvp9_amstream_dec_info.rate = 30;
10974 }
10975 pbi->low_latency_flag = 1;
10976
10977 vp9_print(pbi, 0,
10978 "no_head %d low_latency %d\n",
10979 pbi->no_head, pbi->low_latency_flag);
10980#if 0
10981 pbi->buf_start = pdata->mem_start;
10982 pbi->buf_size = pdata->mem_end - pdata->mem_start + 1;
10983#else
10984 if (amvdec_vp9_mmu_init(pbi) < 0) {
10985 pr_err("vp9 alloc bmmu box failed!!\n");
10986 /* devm_kfree(&pdev->dev, (void *)pbi); */
10987 vfree((void *)pbi);
10988 pdata->dec_status = NULL;
10989 return -1;
10990 }
10991
10992 pbi->cma_alloc_count = PAGE_ALIGN(work_buf_size) / PAGE_SIZE;
10993 ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box, WORK_SPACE_BUF_ID,
10994 pbi->cma_alloc_count * PAGE_SIZE, DRIVER_NAME,
10995 &pbi->cma_alloc_addr);
10996 if (ret < 0) {
10997 uninit_mmu_buffers(pbi);
10998 /* devm_kfree(&pdev->dev, (void *)pbi); */
10999 vfree((void *)pbi);
11000 pdata->dec_status = NULL;
11001 return ret;
11002 }
11003 pbi->buf_start = pbi->cma_alloc_addr;
11004 pbi->buf_size = work_buf_size;
11005#endif
11006
11007 pbi->init_flag = 0;
11008 pbi->first_sc_checked = 0;
11009 pbi->fatal_error = 0;
11010 pbi->show_frame_num = 0;
11011
11012 if (debug) {
11013 pr_info("===VP9 decoder mem resource 0x%lx size 0x%x\n",
11014 pbi->buf_start,
11015 pbi->buf_size);
11016 }
11017
11018 pbi->cma_dev = pdata->cma_dev;
11019 if (vvp9_init(pdata) < 0) {
11020 pr_info("\namvdec_vp9 init failed.\n");
11021 vp9_local_uninit(pbi);
11022 uninit_mmu_buffers(pbi);
11023 /* devm_kfree(&pdev->dev, (void *)pbi); */
11024 vfree((void *)pbi);
11025 pdata->dec_status = NULL;
11026 return -ENODEV;
11027 }
11028 vdec_set_prepare_level(pdata, start_decode_buf_level);
11029 hevc_source_changed(VFORMAT_VP9,
11030 4096, 2048, 60);
11031#ifdef SUPPORT_FB_DECODING
11032 if (pbi->used_stage_buf_num > 0)
11033 vdec_core_request(pdata,
11034 CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK);
11035 else
11036 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
11037 | CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK
11038 | CORE_MASK_COMBINE);
11039#else
11040 if (pdata->parallel_dec == 1)
11041 vdec_core_request(pdata, CORE_MASK_HEVC);
11042 else
11043 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
11044 | CORE_MASK_COMBINE);
11045#endif
11046 pbi->pic_list_init_done2 = true;
11047
11048 if (pbi->enable_fence) {
11049 /* creat timeline. */
11050 vdec_timeline_create(&pdata->sync, DRIVER_NAME);
11051 }
11052
11053 return 0;
11054}
11055
11056static int ammvdec_vp9_remove(struct platform_device *pdev)
11057{
11058 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)
11059 (((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
11060 struct vdec_s *vdec = hw_to_vdec(pbi);
11061 int i;
11062 if (debug)
11063 pr_info("amvdec_vp9_remove\n");
11064
11065 vmvp9_stop(pbi);
11066
11067#ifdef SUPPORT_FB_DECODING
11068 vdec_core_release(hw_to_vdec(pbi), CORE_MASK_VDEC_1 | CORE_MASK_HEVC
11069 | CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK
11070 );
11071#else
11072 if (vdec->parallel_dec == 1)
11073 vdec_core_release(hw_to_vdec(pbi), CORE_MASK_HEVC);
11074 else
11075 vdec_core_release(hw_to_vdec(pbi), CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
11076#endif
11077 vdec_set_status(hw_to_vdec(pbi), VDEC_STATUS_DISCONNECTED);
11078
11079 if (vdec->parallel_dec == 1) {
11080 for (i = 0; i < FRAME_BUFFERS; i++) {
11081 vdec->free_canvas_ex
11082 (pbi->common.buffer_pool->frame_bufs[i].buf.y_canvas_index,
11083 vdec->id);
11084 vdec->free_canvas_ex
11085 (pbi->common.buffer_pool->frame_bufs[i].buf.uv_canvas_index,
11086 vdec->id);
11087 }
11088 }
11089
11090 if (pbi->enable_fence)
11091 vdec_fence_release(pbi, &vdec->sync);
11092
11093#ifdef DEBUG_PTS
11094 pr_info("pts missed %ld, pts hit %ld, duration %d\n",
11095 pbi->pts_missed, pbi->pts_hit, pbi->frame_dur);
11096#endif
11097 mem_map_mode = 0;
11098
11099 /* devm_kfree(&pdev->dev, (void *)pbi); */
11100 vfree((void *)pbi);
11101 return 0;
11102}
11103
11104static struct platform_driver ammvdec_vp9_driver = {
11105 .probe = ammvdec_vp9_probe,
11106 .remove = ammvdec_vp9_remove,
11107 .driver = {
11108 .name = MULTI_DRIVER_NAME,
11109#ifdef CONFIG_PM
11110 .pm = &vp9_pm_ops,
11111#endif
11112 }
11113};
11114#endif
11115static struct mconfig vp9_configs[] = {
11116 MC_PU32("bit_depth_luma", &bit_depth_luma),
11117 MC_PU32("bit_depth_chroma", &bit_depth_chroma),
11118 MC_PU32("frame_width", &frame_width),
11119 MC_PU32("frame_height", &frame_height),
11120 MC_PU32("debug", &debug),
11121 MC_PU32("radr", &radr),
11122 MC_PU32("rval", &rval),
11123 MC_PU32("pop_shorts", &pop_shorts),
11124 MC_PU32("dbg_cmd", &dbg_cmd),
11125 MC_PU32("dbg_skip_decode_index", &dbg_skip_decode_index),
11126 MC_PU32("endian", &endian),
11127 MC_PU32("step", &step),
11128 MC_PU32("udebug_flag", &udebug_flag),
11129 MC_PU32("decode_pic_begin", &decode_pic_begin),
11130 MC_PU32("slice_parse_begin", &slice_parse_begin),
11131 MC_PU32("i_only_flag", &i_only_flag),
11132 MC_PU32("error_handle_policy", &error_handle_policy),
11133 MC_PU32("buf_alloc_width", &buf_alloc_width),
11134 MC_PU32("buf_alloc_height", &buf_alloc_height),
11135 MC_PU32("buf_alloc_depth", &buf_alloc_depth),
11136 MC_PU32("buf_alloc_size", &buf_alloc_size),
11137 MC_PU32("buffer_mode", &buffer_mode),
11138 MC_PU32("buffer_mode_dbg", &buffer_mode_dbg),
11139 MC_PU32("max_buf_num", &max_buf_num),
11140 MC_PU32("dynamic_buf_num_margin", &dynamic_buf_num_margin),
11141 MC_PU32("mem_map_mode", &mem_map_mode),
11142 MC_PU32("double_write_mode", &double_write_mode),
11143 MC_PU32("enable_mem_saving", &enable_mem_saving),
11144 MC_PU32("force_w_h", &force_w_h),
11145 MC_PU32("force_fps", &force_fps),
11146 MC_PU32("max_decoding_time", &max_decoding_time),
11147 MC_PU32("on_no_keyframe_skiped", &on_no_keyframe_skiped),
11148 MC_PU32("start_decode_buf_level", &start_decode_buf_level),
11149 MC_PU32("decode_timeout_val", &decode_timeout_val),
11150 MC_PU32("vp9_max_pic_w", &vp9_max_pic_w),
11151 MC_PU32("vp9_max_pic_h", &vp9_max_pic_h),
11152};
11153static struct mconfig_node vp9_node;
11154
11155static int __init amvdec_vp9_driver_init_module(void)
11156{
11157
11158 struct BuffInfo_s *p_buf_info;
11159
11160 if (vdec_is_support_4k()) {
11161 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
11162 p_buf_info = &amvvp9_workbuff_spec[2];
11163 else
11164 p_buf_info = &amvvp9_workbuff_spec[1];
11165 } else
11166 p_buf_info = &amvvp9_workbuff_spec[0];
11167
11168 init_buff_spec(NULL, p_buf_info);
11169 work_buf_size =
11170 (p_buf_info->end_adr - p_buf_info->start_adr
11171 + 0xffff) & (~0xffff);
11172
11173 pr_debug("amvdec_vp9 module init\n");
11174
11175 error_handle_policy = 0;
11176
11177#ifdef ERROR_HANDLE_DEBUG
11178 dbg_nal_skip_flag = 0;
11179 dbg_nal_skip_count = 0;
11180#endif
11181 udebug_flag = 0;
11182 decode_pic_begin = 0;
11183 slice_parse_begin = 0;
11184 step = 0;
11185 buf_alloc_size = 0;
11186#ifdef MULTI_INSTANCE_SUPPORT
11187 if (platform_driver_register(&ammvdec_vp9_driver))
11188 pr_err("failed to register ammvdec_vp9 driver\n");
11189
11190#endif
11191 if (platform_driver_register(&amvdec_vp9_driver)) {
11192 pr_err("failed to register amvdec_vp9 driver\n");
11193 return -ENODEV;
11194 }
11195
11196 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
11197 amvdec_vp9_profile.profile =
11198 "8k, 10bit, dwrite, compressed";
11199 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXL
11200 /*&& get_cpu_major_id() != MESON_CPU_MAJOR_ID_GXLX*/
11201 && get_cpu_major_id() != AM_MESON_CPU_MAJOR_ID_TXL) {
11202 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX) {
11203 if (vdec_is_support_4k())
11204 amvdec_vp9_profile.profile =
11205 "4k, 10bit, dwrite, compressed";
11206 else
11207 amvdec_vp9_profile.profile =
11208 "10bit, dwrite, compressed";
11209 } else {
11210 if (vdec_is_support_4k())
11211 amvdec_vp9_profile.profile =
11212 "4k, 10bit, dwrite, compressed";
11213 else
11214 amvdec_vp9_profile.profile =
11215 "10bit, dwrite, compressed";
11216 }
11217
11218 } else {
11219 amvdec_vp9_profile.name = "vp9_unsupport";
11220 }
11221
11222 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A)
11223 max_buf_num = MAX_BUF_NUM_LESS;
11224
11225 vcodec_profile_register(&amvdec_vp9_profile);
11226 amvdec_vp9_profile_mult = amvdec_vp9_profile;
11227 amvdec_vp9_profile_mult.name = "mvp9";
11228 vcodec_profile_register(&amvdec_vp9_profile_mult);
11229 INIT_REG_NODE_CONFIGS("media.decoder", &vp9_node,
11230 "vp9", vp9_configs, CONFIG_FOR_RW);
11231
11232 return 0;
11233}
11234
11235static void __exit amvdec_vp9_driver_remove_module(void)
11236{
11237 pr_debug("amvdec_vp9 module remove.\n");
11238#ifdef MULTI_INSTANCE_SUPPORT
11239 platform_driver_unregister(&ammvdec_vp9_driver);
11240#endif
11241 platform_driver_unregister(&amvdec_vp9_driver);
11242}
11243
11244/****************************************/
11245
11246module_param(bit_depth_luma, uint, 0664);
11247MODULE_PARM_DESC(bit_depth_luma, "\n amvdec_vp9 bit_depth_luma\n");
11248
11249module_param(bit_depth_chroma, uint, 0664);
11250MODULE_PARM_DESC(bit_depth_chroma, "\n amvdec_vp9 bit_depth_chroma\n");
11251
11252module_param(frame_width, uint, 0664);
11253MODULE_PARM_DESC(frame_width, "\n amvdec_vp9 frame_width\n");
11254
11255module_param(frame_height, uint, 0664);
11256MODULE_PARM_DESC(frame_height, "\n amvdec_vp9 frame_height\n");
11257
11258module_param(debug, uint, 0664);
11259MODULE_PARM_DESC(debug, "\n amvdec_vp9 debug\n");
11260
11261module_param(radr, uint, 0664);
11262MODULE_PARM_DESC(radr, "\n radr\n");
11263
11264module_param(rval, uint, 0664);
11265MODULE_PARM_DESC(rval, "\n rval\n");
11266
11267module_param(pop_shorts, uint, 0664);
11268MODULE_PARM_DESC(pop_shorts, "\n rval\n");
11269
11270module_param(dbg_cmd, uint, 0664);
11271MODULE_PARM_DESC(dbg_cmd, "\n dbg_cmd\n");
11272
11273module_param(dbg_skip_decode_index, uint, 0664);
11274MODULE_PARM_DESC(dbg_skip_decode_index, "\n dbg_skip_decode_index\n");
11275
11276module_param(endian, uint, 0664);
11277MODULE_PARM_DESC(endian, "\n rval\n");
11278
11279module_param(step, uint, 0664);
11280MODULE_PARM_DESC(step, "\n amvdec_vp9 step\n");
11281
11282module_param(decode_pic_begin, uint, 0664);
11283MODULE_PARM_DESC(decode_pic_begin, "\n amvdec_vp9 decode_pic_begin\n");
11284
11285module_param(slice_parse_begin, uint, 0664);
11286MODULE_PARM_DESC(slice_parse_begin, "\n amvdec_vp9 slice_parse_begin\n");
11287
11288module_param(i_only_flag, uint, 0664);
11289MODULE_PARM_DESC(i_only_flag, "\n amvdec_vp9 i_only_flag\n");
11290
11291module_param(low_latency_flag, uint, 0664);
11292MODULE_PARM_DESC(low_latency_flag, "\n amvdec_vp9 low_latency_flag\n");
11293
11294module_param(no_head, uint, 0664);
11295MODULE_PARM_DESC(no_head, "\n amvdec_vp9 no_head\n");
11296
11297module_param(error_handle_policy, uint, 0664);
11298MODULE_PARM_DESC(error_handle_policy, "\n amvdec_vp9 error_handle_policy\n");
11299
11300module_param(buf_alloc_width, uint, 0664);
11301MODULE_PARM_DESC(buf_alloc_width, "\n buf_alloc_width\n");
11302
11303module_param(buf_alloc_height, uint, 0664);
11304MODULE_PARM_DESC(buf_alloc_height, "\n buf_alloc_height\n");
11305
11306module_param(buf_alloc_depth, uint, 0664);
11307MODULE_PARM_DESC(buf_alloc_depth, "\n buf_alloc_depth\n");
11308
11309module_param(buf_alloc_size, uint, 0664);
11310MODULE_PARM_DESC(buf_alloc_size, "\n buf_alloc_size\n");
11311
11312module_param(buffer_mode, uint, 0664);
11313MODULE_PARM_DESC(buffer_mode, "\n buffer_mode\n");
11314
11315module_param(buffer_mode_dbg, uint, 0664);
11316MODULE_PARM_DESC(buffer_mode_dbg, "\n buffer_mode_dbg\n");
11317/*USE_BUF_BLOCK*/
11318module_param(max_buf_num, uint, 0664);
11319MODULE_PARM_DESC(max_buf_num, "\n max_buf_num\n");
11320
11321module_param(dynamic_buf_num_margin, uint, 0664);
11322MODULE_PARM_DESC(dynamic_buf_num_margin, "\n dynamic_buf_num_margin\n");
11323
11324module_param(mv_buf_margin, uint, 0664);
11325MODULE_PARM_DESC(mv_buf_margin, "\n mv_buf_margin\n");
11326
11327module_param(run_ready_min_buf_num, uint, 0664);
11328MODULE_PARM_DESC(run_ready_min_buf_num, "\n run_ready_min_buf_num\n");
11329
11330/**/
11331
11332module_param(mem_map_mode, uint, 0664);
11333MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n");
11334
11335#ifdef SUPPORT_10BIT
11336module_param(double_write_mode, uint, 0664);
11337MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n");
11338
11339module_param(enable_mem_saving, uint, 0664);
11340MODULE_PARM_DESC(enable_mem_saving, "\n enable_mem_saving\n");
11341
11342module_param(force_w_h, uint, 0664);
11343MODULE_PARM_DESC(force_w_h, "\n force_w_h\n");
11344#endif
11345
11346module_param(force_fps, uint, 0664);
11347MODULE_PARM_DESC(force_fps, "\n force_fps\n");
11348
11349module_param(max_decoding_time, uint, 0664);
11350MODULE_PARM_DESC(max_decoding_time, "\n max_decoding_time\n");
11351
11352module_param(on_no_keyframe_skiped, uint, 0664);
11353MODULE_PARM_DESC(on_no_keyframe_skiped, "\n on_no_keyframe_skiped\n");
11354
11355module_param(mcrcc_cache_alg_flag, uint, 0664);
11356MODULE_PARM_DESC(mcrcc_cache_alg_flag, "\n mcrcc_cache_alg_flag\n");
11357
11358#ifdef MULTI_INSTANCE_SUPPORT
11359module_param(start_decode_buf_level, int, 0664);
11360MODULE_PARM_DESC(start_decode_buf_level,
11361 "\n vp9 start_decode_buf_level\n");
11362
11363module_param(decode_timeout_val, uint, 0664);
11364MODULE_PARM_DESC(decode_timeout_val,
11365 "\n vp9 decode_timeout_val\n");
11366
11367module_param(vp9_max_pic_w, uint, 0664);
11368MODULE_PARM_DESC(vp9_max_pic_w, "\n vp9_max_pic_w\n");
11369
11370module_param(vp9_max_pic_h, uint, 0664);
11371MODULE_PARM_DESC(vp9_max_pic_h, "\n vp9_max_pic_h\n");
11372
11373module_param_array(decode_frame_count, uint,
11374 &max_decode_instance_num, 0664);
11375
11376module_param_array(display_frame_count, uint,
11377 &max_decode_instance_num, 0664);
11378
11379module_param_array(max_process_time, uint,
11380 &max_decode_instance_num, 0664);
11381
11382module_param_array(run_count, uint,
11383 &max_decode_instance_num, 0664);
11384
11385module_param_array(input_empty, uint,
11386 &max_decode_instance_num, 0664);
11387
11388module_param_array(not_run_ready, uint,
11389 &max_decode_instance_num, 0664);
11390#endif
11391
11392#ifdef SUPPORT_FB_DECODING
11393module_param_array(not_run2_ready, uint,
11394 &max_decode_instance_num, 0664);
11395
11396module_param_array(run2_count, uint,
11397 &max_decode_instance_num, 0664);
11398
11399module_param(stage_buf_num, uint, 0664);
11400MODULE_PARM_DESC(stage_buf_num, "\n amvdec_h265 stage_buf_num\n");
11401#endif
11402
11403module_param(udebug_flag, uint, 0664);
11404MODULE_PARM_DESC(udebug_flag, "\n amvdec_h265 udebug_flag\n");
11405
11406module_param(udebug_pause_pos, uint, 0664);
11407MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n");
11408
11409module_param(udebug_pause_val, uint, 0664);
11410MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n");
11411
11412module_param(udebug_pause_decode_idx, uint, 0664);
11413MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n");
11414
11415module_param(without_display_mode, uint, 0664);
11416MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n");
11417
11418module_param(force_config_fence, uint, 0664);
11419MODULE_PARM_DESC(force_config_fence, "\n force enable fence\n");
11420
11421module_param(force_pts_unstable, uint, 0664);
11422MODULE_PARM_DESC(force_pts_unstable, "\n force_pts_unstable\n");
11423
11424module_init(amvdec_vp9_driver_init_module);
11425module_exit(amvdec_vp9_driver_remove_module);
11426
11427MODULE_DESCRIPTION("AMLOGIC vp9 Video Decoder Driver");
11428MODULE_LICENSE("GPL");
11429
11430
generated by cgit at 2024-05-19 16:37:53 (GMT)