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path: root/drivers/frame_provider/decoder/vp9/vvp9.c (plain)
blob: 7a8df628430bc497653929039680609f2ad61ee2
1 /*
2 * drivers/amlogic/amports/vvp9.c
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17#define DEBUG
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/types.h>
21#include <linux/errno.h>
22#include <linux/interrupt.h>
23#include <linux/semaphore.h>
24#include <linux/delay.h>
25#include <linux/timer.h>
26#include <linux/kfifo.h>
27#include <linux/kthread.h>
28#include <linux/spinlock.h>
29#include <linux/platform_device.h>
30#include <linux/amlogic/media/vfm/vframe.h>
31#include <linux/amlogic/media/utils/amstream.h>
32#include <linux/amlogic/media/utils/vformat.h>
33#include <linux/amlogic/media/frame_sync/ptsserv.h>
34#include <linux/amlogic/media/canvas/canvas.h>
35#include <linux/amlogic/media/vfm/vframe_provider.h>
36#include <linux/amlogic/media/vfm/vframe_receiver.h>
37#include <linux/dma-mapping.h>
38#include <linux/dma-contiguous.h>
39#include <linux/slab.h>
40#include <linux/amlogic/tee.h>
41#include "../../../stream_input/amports/amports_priv.h"
42#include <linux/amlogic/media/codec_mm/codec_mm.h>
43#include "../utils/decoder_mmu_box.h"
44#include "../utils/decoder_bmmu_box.h"
45
46#define MEM_NAME "codec_vp9"
47/* #include <mach/am_regs.h> */
48#include <linux/amlogic/media/utils/vdec_reg.h>
49#include "../utils/vdec.h"
50#include "../utils/amvdec.h"
51#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
52#include "../utils/vdec_profile.h"
53#endif
54
55#include <linux/amlogic/media/video_sink/video.h>
56#include <linux/amlogic/media/codec_mm/configs.h>
57#include "../utils/config_parser.h"
58#include "../utils/firmware.h"
59#include "../../../common/chips/decoder_cpu_ver_info.h"
60#include "../utils/vdec_v4l2_buffer_ops.h"
61#include <media/v4l2-mem2mem.h>
62
63#define MIX_STREAM_SUPPORT
64
65#include "vvp9.h"
66
67
68/*#define SUPPORT_FB_DECODING*/
69/*#define FB_DECODING_TEST_SCHEDULE*/
70
71
72#define HW_MASK_FRONT 0x1
73#define HW_MASK_BACK 0x2
74
75#define VP9D_MPP_REFINFO_TBL_ACCCONFIG 0x3442
76#define VP9D_MPP_REFINFO_DATA 0x3443
77#define VP9D_MPP_REF_SCALE_ENBL 0x3441
78#define HEVC_MPRED_CTRL4 0x324c
79#define HEVC_CM_HEADER_START_ADDR 0x3628
80#define HEVC_DBLK_CFGB 0x350b
81#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464
82#define HEVC_SAO_MMU_VH1_ADDR 0x363b
83#define HEVC_SAO_MMU_VH0_ADDR 0x363a
84
85#define HEVC_MV_INFO 0x310d
86#define HEVC_QP_INFO 0x3137
87#define HEVC_SKIP_INFO 0x3136
88
89#define VP9_10B_DEC_IDLE 0
90#define VP9_10B_DEC_FRAME_HEADER 1
91#define VP9_10B_DEC_SLICE_SEGMENT 2
92#define VP9_10B_DECODE_SLICE 5
93#define VP9_10B_DISCARD_NAL 6
94#define VP9_DUMP_LMEM 7
95#define HEVC_DECPIC_DATA_DONE 0xa
96#define HEVC_DECPIC_DATA_ERROR 0xb
97#define HEVC_NAL_DECODE_DONE 0xe
98#define HEVC_DECODE_BUFEMPTY 0x20
99#define HEVC_DECODE_TIMEOUT 0x21
100#define HEVC_SEARCH_BUFEMPTY 0x22
101#define HEVC_DECODE_OVER_SIZE 0x23
102#define HEVC_S2_DECODING_DONE 0x50
103#define VP9_HEAD_PARSER_DONE 0xf0
104#define VP9_HEAD_SEARCH_DONE 0xf1
105#define VP9_EOS 0xf2
106#define HEVC_ACTION_DONE 0xff
107
108#define VF_POOL_SIZE 32
109
110#undef pr_info
111#define pr_info printk
112
113#define DECODE_MODE_SINGLE ((0x80 << 24) | 0)
114#define DECODE_MODE_MULTI_STREAMBASE ((0x80 << 24) | 1)
115#define DECODE_MODE_MULTI_FRAMEBASE ((0x80 << 24) | 2)
116#define DECODE_MODE_SINGLE_LOW_LATENCY ((0x80 << 24) | 3)
117#define DECODE_MODE_MULTI_FRAMEBASE_NOHEAD ((0x80 << 24) | 4)
118
119#define VP9_TRIGGER_FRAME_DONE 0x100
120#define VP9_TRIGGER_FRAME_ENABLE 0x200
121
122#define MV_MEM_UNIT 0x240
123/*---------------------------------------------------
124 * Include "parser_cmd.h"
125 *---------------------------------------------------
126 */
127#define PARSER_CMD_SKIP_CFG_0 0x0000090b
128
129#define PARSER_CMD_SKIP_CFG_1 0x1b14140f
130
131#define PARSER_CMD_SKIP_CFG_2 0x001b1910
132
133#define PARSER_CMD_NUMBER 37
134
135/*#define HEVC_PIC_STRUCT_SUPPORT*/
136/* to remove, fix build error */
137
138/*#define CODEC_MM_FLAGS_FOR_VDECODER 0*/
139
140#define MULTI_INSTANCE_SUPPORT
141#define SUPPORT_10BIT
142/* #define ERROR_HANDLE_DEBUG */
143
144#ifndef STAT_KTHREAD
145#define STAT_KTHREAD 0x40
146#endif
147
148#ifdef MULTI_INSTANCE_SUPPORT
149#define MAX_DECODE_INSTANCE_NUM 9
150#define MULTI_DRIVER_NAME "ammvdec_vp9"
151static unsigned int max_decode_instance_num
152 = MAX_DECODE_INSTANCE_NUM;
153static unsigned int decode_frame_count[MAX_DECODE_INSTANCE_NUM];
154static unsigned int display_frame_count[MAX_DECODE_INSTANCE_NUM];
155static unsigned int max_process_time[MAX_DECODE_INSTANCE_NUM];
156static unsigned int run_count[MAX_DECODE_INSTANCE_NUM];
157static unsigned int input_empty[MAX_DECODE_INSTANCE_NUM];
158static unsigned int not_run_ready[MAX_DECODE_INSTANCE_NUM];
159
160static u32 decode_timeout_val = 200;
161static int start_decode_buf_level = 0x8000;
162static u32 work_buf_size;
163
164static u32 mv_buf_margin;
165
166/* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */
167/* double_write_mode:
168 * 0, no double write;
169 * 1, 1:1 ratio;
170 * 2, (1/4):(1/4) ratio;
171 * 3, (1/4):(1/4) ratio, with both compressed frame included
172 * 4, (1/2):(1/2) ratio;
173 * 0x10, double write only
174 * 0x100, if > 1080p,use mode 4,else use mode 1;
175 * 0x200, if > 1080p,use mode 2,else use mode 1;
176 * 0x300, if > 720p, use mode 4, else use mode 1;
177 */
178static u32 double_write_mode;
179
180#define DRIVER_NAME "amvdec_vp9"
181#define MODULE_NAME "amvdec_vp9"
182#define DRIVER_HEADER_NAME "amvdec_vp9_header"
183
184
185#define PUT_INTERVAL (HZ/100)
186#define ERROR_SYSTEM_RESET_COUNT 200
187
188#define PTS_NORMAL 0
189#define PTS_NONE_REF_USE_DURATION 1
190
191#define PTS_MODE_SWITCHING_THRESHOLD 3
192#define PTS_MODE_SWITCHING_RECOVERY_THREASHOLD 3
193
194#define DUR2PTS(x) ((x)*90/96)
195
196struct VP9Decoder_s;
197static int vvp9_vf_states(struct vframe_states *states, void *);
198static struct vframe_s *vvp9_vf_peek(void *);
199static struct vframe_s *vvp9_vf_get(void *);
200static void vvp9_vf_put(struct vframe_s *, void *);
201static int vvp9_event_cb(int type, void *data, void *private_data);
202
203static int vvp9_stop(struct VP9Decoder_s *pbi);
204#ifdef MULTI_INSTANCE_SUPPORT
205static s32 vvp9_init(struct vdec_s *vdec);
206#else
207static s32 vvp9_init(struct VP9Decoder_s *pbi);
208#endif
209static void vvp9_prot_init(struct VP9Decoder_s *pbi, u32 mask);
210static int vvp9_local_init(struct VP9Decoder_s *pbi);
211static void vvp9_put_timer_func(unsigned long arg);
212static void dump_data(struct VP9Decoder_s *pbi, int size);
213static unsigned char get_data_check_sum
214 (struct VP9Decoder_s *pbi, int size);
215static void dump_pic_list(struct VP9Decoder_s *pbi);
216static int vp9_alloc_mmu(
217 struct VP9Decoder_s *pbi,
218 int cur_buf_idx,
219 int pic_width,
220 int pic_height,
221 unsigned short bit_depth,
222 unsigned int *mmu_index_adr);
223
224
225static const char vvp9_dec_id[] = "vvp9-dev";
226
227#define PROVIDER_NAME "decoder.vp9"
228#define MULTI_INSTANCE_PROVIDER_NAME "vdec.vp9"
229
230static const struct vframe_operations_s vvp9_vf_provider = {
231 .peek = vvp9_vf_peek,
232 .get = vvp9_vf_get,
233 .put = vvp9_vf_put,
234 .event_cb = vvp9_event_cb,
235 .vf_states = vvp9_vf_states,
236};
237
238static struct vframe_provider_s vvp9_vf_prov;
239
240static u32 bit_depth_luma;
241static u32 bit_depth_chroma;
242static u32 frame_width;
243static u32 frame_height;
244static u32 video_signal_type;
245
246static u32 on_no_keyframe_skiped;
247
248#define PROB_SIZE (496 * 2 * 4)
249#define PROB_BUF_SIZE (0x5000)
250#define COUNT_BUF_SIZE (0x300 * 4 * 4)
251/*compute_losless_comp_body_size(4096, 2304, 1) = 18874368(0x1200000)*/
252#define MAX_FRAME_4K_NUM 0x1200
253#define MAX_FRAME_8K_NUM 0x4800
254
255#define HEVC_ASSIST_MMU_MAP_ADDR 0x3009
256
257#ifdef SUPPORT_FB_DECODING
258/* register define */
259#define HEVC_ASSIST_HED_FB_W_CTL 0x3006
260#define HEVC_ASSIST_HED_FB_R_CTL 0x3007
261#define HEVC_ASSIST_HED_FB_ADDR 0x3008
262#define HEVC_ASSIST_FB_MMU_MAP_ADDR 0x300a
263#define HEVC_ASSIST_FBD_MMU_MAP_ADDR 0x300b
264
265
266#define MAX_STAGE_PAGE_NUM 0x1200
267#define STAGE_MMU_MAP_SIZE (MAX_STAGE_PAGE_NUM * 4)
268#endif
269static inline int div_r32(int64_t m, int n)
270{
271/*
272 *return (int)(m/n)
273 */
274#ifndef CONFIG_ARM64
275 int64_t qu = 0;
276 qu = div_s64(m, n);
277 return (int)qu;
278#else
279 return (int)(m/n);
280#endif
281}
282
283/*USE_BUF_BLOCK*/
284struct BUF_s {
285 int index;
286 unsigned int alloc_flag;
287 /*buffer */
288 unsigned int cma_page_count;
289 unsigned long alloc_addr;
290 unsigned long start_adr;
291 unsigned int size;
292
293 unsigned int free_start_adr;
294 ulong v4l_ref_buf_addr;
295 ulong header_addr;
296 u32 header_size;
297 u32 luma_size;
298 ulong chroma_addr;
299 u32 chroma_size;
300} /*BUF_t */;
301
302struct MVBUF_s {
303 unsigned long start_adr;
304 unsigned int size;
305 int used_flag;
306} /*MVBUF_t */;
307
308 /* #undef BUFMGR_ONLY to enable hardware configuration */
309
310/*#define TEST_WR_PTR_INC*/
311/*#define WR_PTR_INC_NUM 128*/
312#define WR_PTR_INC_NUM 1
313
314#define SIMULATION
315#define DOS_PROJECT
316#undef MEMORY_MAP_IN_REAL_CHIP
317
318/*#undef DOS_PROJECT*/
319/*#define MEMORY_MAP_IN_REAL_CHIP*/
320
321/*#define BUFFER_MGR_ONLY*/
322/*#define CONFIG_HEVC_CLK_FORCED_ON*/
323/*#define ENABLE_SWAP_TEST*/
324#define MCRCC_ENABLE
325
326#define VP9_LPF_LVL_UPDATE
327/*#define DBG_LF_PRINT*/
328
329#ifdef VP9_10B_NV21
330#else
331#define LOSLESS_COMPRESS_MODE
332#endif
333
334#define DOUBLE_WRITE_YSTART_TEMP 0x02000000
335#define DOUBLE_WRITE_CSTART_TEMP 0x02900000
336
337
338
339typedef unsigned int u32;
340typedef unsigned short u16;
341
342#define VP9_DEBUG_BUFMGR 0x01
343#define VP9_DEBUG_BUFMGR_MORE 0x02
344#define VP9_DEBUG_BUFMGR_DETAIL 0x04
345#define VP9_DEBUG_OUT_PTS 0x10
346#define VP9_DEBUG_SEND_PARAM_WITH_REG 0x100
347#define VP9_DEBUG_MERGE 0x200
348#define VP9_DEBUG_DBG_LF_PRINT 0x400
349#define VP9_DEBUG_REG 0x800
350#define VP9_DEBUG_2_STAGE 0x1000
351#define VP9_DEBUG_2_STAGE_MORE 0x2000
352#define VP9_DEBUG_QOS_INFO 0x4000
353#define VP9_DEBUG_DIS_LOC_ERROR_PROC 0x10000
354#define VP9_DEBUG_DIS_SYS_ERROR_PROC 0x20000
355#define VP9_DEBUG_DUMP_PIC_LIST 0x40000
356#define VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC 0x80000
357#define VP9_DEBUG_NO_TRIGGER_FRAME 0x100000
358#define VP9_DEBUG_LOAD_UCODE_FROM_FILE 0x200000
359#define VP9_DEBUG_FORCE_SEND_AGAIN 0x400000
360#define VP9_DEBUG_DUMP_DATA 0x800000
361#define VP9_DEBUG_CACHE 0x1000000
362#define VP9_DEBUG_CACHE_HIT_RATE 0x2000000
363#define IGNORE_PARAM_FROM_CONFIG 0x8000000
364#ifdef MULTI_INSTANCE_SUPPORT
365#define PRINT_FLAG_ERROR 0x0
366#define PRINT_FLAG_V4L_DETAIL 0x10000000
367#define PRINT_FLAG_VDEC_STATUS 0x20000000
368#define PRINT_FLAG_VDEC_DETAIL 0x40000000
369#define PRINT_FLAG_VDEC_DATA 0x80000000
370#endif
371
372static u32 debug;
373static bool is_reset;
374/*for debug*/
375/*
376 udebug_flag:
377 bit 0, enable ucode print
378 bit 1, enable ucode detail print
379 bit [31:16] not 0, pos to dump lmem
380 bit 2, pop bits to lmem
381 bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
382*/
383static u32 udebug_flag;
384/*
385 when udebug_flag[1:0] is not 0
386 udebug_pause_pos not 0,
387 pause position
388*/
389static u32 udebug_pause_pos;
390/*
391 when udebug_flag[1:0] is not 0
392 and udebug_pause_pos is not 0,
393 pause only when DEBUG_REG2 is equal to this val
394*/
395static u32 udebug_pause_val;
396
397static u32 udebug_pause_decode_idx;
398
399static u32 without_display_mode;
400
401#define DEBUG_REG
402#ifdef DEBUG_REG
403void WRITE_VREG_DBG2(unsigned int adr, unsigned int val)
404{
405 if (debug & VP9_DEBUG_REG)
406 pr_info("%s(%x, %x)\n", __func__, adr, val);
407 if (adr != 0)
408 WRITE_VREG(adr, val);
409}
410
411#undef WRITE_VREG
412#define WRITE_VREG WRITE_VREG_DBG2
413#endif
414
415#define FRAME_CNT_WINDOW_SIZE 59
416#define RATE_CORRECTION_THRESHOLD 5
417/**************************************************
418
419VP9 buffer management start
420
421***************************************************/
422
423#define MMU_COMPRESS_HEADER_SIZE 0x48000
424#define MMU_COMPRESS_8K_HEADER_SIZE (0x48000*4)
425#define MAX_SIZE_8K (8192 * 4608)
426#define MAX_SIZE_4K (4096 * 2304)
427#define IS_8K_SIZE(w, h) (((w) * (h)) > MAX_SIZE_4K)
428
429#define INVALID_IDX -1 /* Invalid buffer index.*/
430
431#define RPM_BEGIN 0x200
432#define RPM_END 0x280
433
434union param_u {
435 struct {
436 unsigned short data[RPM_END - RPM_BEGIN];
437 } l;
438 struct {
439 /* from ucode lmem, do not change this struct */
440 unsigned short profile;
441 unsigned short show_existing_frame;
442 unsigned short frame_to_show_idx;
443 unsigned short frame_type; /*1 bit*/
444 unsigned short show_frame; /*1 bit*/
445 unsigned short error_resilient_mode; /*1 bit*/
446 unsigned short intra_only; /*1 bit*/
447 unsigned short display_size_present; /*1 bit*/
448 unsigned short reset_frame_context;
449 unsigned short refresh_frame_flags;
450 unsigned short width;
451 unsigned short height;
452 unsigned short display_width;
453 unsigned short display_height;
454 /*
455 *bit[11:8] - ref_frame_info_0 (ref(3-bits), ref_frame_sign_bias(1-bit))
456 *bit[7:4] - ref_frame_info_1 (ref(3-bits), ref_frame_sign_bias(1-bit))
457 *bit[3:0] - ref_frame_info_2 (ref(3-bits), ref_frame_sign_bias(1-bit))
458 */
459 unsigned short ref_info;
460 /*
461 *bit[2]: same_frame_size0
462 *bit[1]: same_frame_size1
463 *bit[0]: same_frame_size2
464 */
465 unsigned short same_frame_size;
466
467 unsigned short mode_ref_delta_enabled;
468 unsigned short ref_deltas[4];
469 unsigned short mode_deltas[2];
470 unsigned short filter_level;
471 unsigned short sharpness_level;
472 unsigned short bit_depth;
473 unsigned short seg_quant_info[8];
474 unsigned short seg_enabled;
475 unsigned short seg_abs_delta;
476 /* bit 15: feature enabled; bit 8, sign; bit[5:0], data */
477 unsigned short seg_lf_info[8];
478 } p;
479};
480
481
482struct vpx_codec_frame_buffer_s {
483 uint8_t *data; /**< Pointer to the data buffer */
484 size_t size; /**< Size of data in bytes */
485 void *priv; /**< Frame's private data */
486};
487
488enum vpx_color_space_t {
489 VPX_CS_UNKNOWN = 0, /**< Unknown */
490 VPX_CS_BT_601 = 1, /**< BT.601 */
491 VPX_CS_BT_709 = 2, /**< BT.709 */
492 VPX_CS_SMPTE_170 = 3, /**< SMPTE.170 */
493 VPX_CS_SMPTE_240 = 4, /**< SMPTE.240 */
494 VPX_CS_BT_2020 = 5, /**< BT.2020 */
495 VPX_CS_RESERVED = 6, /**< Reserved */
496 VPX_CS_SRGB = 7 /**< sRGB */
497}; /**< alias for enum vpx_color_space */
498
499enum vpx_bit_depth_t {
500 VPX_BITS_8 = 8, /**< 8 bits */
501 VPX_BITS_10 = 10, /**< 10 bits */
502 VPX_BITS_12 = 12, /**< 12 bits */
503};
504
505#define MAX_SLICE_NUM 1024
506struct PIC_BUFFER_CONFIG_s {
507 int index;
508 int BUF_index;
509 int mv_buf_index;
510 int comp_body_size;
511 int buf_size;
512 int vf_ref;
513 int y_canvas_index;
514 int uv_canvas_index;
515#ifdef MULTI_INSTANCE_SUPPORT
516 struct canvas_config_s canvas_config[2];
517#endif
518 int decode_idx;
519 int slice_type;
520 int stream_offset;
521 u32 pts;
522 u64 pts64;
523 u64 timestamp;
524 uint8_t error_mark;
525 /**/
526 int slice_idx;
527 /*buffer*/
528 unsigned long header_adr;
529 unsigned long mpred_mv_wr_start_addr;
530 /*unsigned long mc_y_adr;
531 *unsigned long mc_u_v_adr;
532 */
533 unsigned int dw_y_adr;
534 unsigned int dw_u_v_adr;
535 int mc_canvas_y;
536 int mc_canvas_u_v;
537
538 int lcu_total;
539 /**/
540 int y_width;
541 int y_height;
542 int y_crop_width;
543 int y_crop_height;
544 int y_stride;
545
546 int uv_width;
547 int uv_height;
548 int uv_crop_width;
549 int uv_crop_height;
550 int uv_stride;
551
552 int alpha_width;
553 int alpha_height;
554 int alpha_stride;
555
556 uint8_t *y_buffer;
557 uint8_t *u_buffer;
558 uint8_t *v_buffer;
559 uint8_t *alpha_buffer;
560
561 uint8_t *buffer_alloc;
562 int buffer_alloc_sz;
563 int border;
564 int frame_size;
565 int subsampling_x;
566 int subsampling_y;
567 unsigned int bit_depth;
568 enum vpx_color_space_t color_space;
569
570 int corrupted;
571 int flags;
572 unsigned long cma_alloc_addr;
573
574 int double_write_mode;
575
576 /* picture qos infomation*/
577 int max_qp;
578 int avg_qp;
579 int min_qp;
580 int max_skip;
581 int avg_skip;
582 int min_skip;
583 int max_mv;
584 int min_mv;
585 int avg_mv;
586
587 u32 hw_decode_time;
588 u32 frame_size2; // For frame base mode
589 bool vframe_bound;
590} PIC_BUFFER_CONFIG;
591
592enum BITSTREAM_PROFILE {
593 PROFILE_0,
594 PROFILE_1,
595 PROFILE_2,
596 PROFILE_3,
597 MAX_PROFILES
598};
599
600enum FRAME_TYPE {
601 KEY_FRAME = 0,
602 INTER_FRAME = 1,
603 FRAME_TYPES,
604};
605
606enum REFERENCE_MODE {
607 SINGLE_REFERENCE = 0,
608 COMPOUND_REFERENCE = 1,
609 REFERENCE_MODE_SELECT = 2,
610 REFERENCE_MODES = 3,
611};
612
613#define NONE -1
614#define INTRA_FRAME 0
615#define LAST_FRAME 1
616#define GOLDEN_FRAME 2
617#define ALTREF_FRAME 3
618#define MAX_REF_FRAMES 4
619
620#define REFS_PER_FRAME 3
621
622#define REF_FRAMES_LOG2 3
623#define REF_FRAMES (1 << REF_FRAMES_LOG2)
624#define REF_FRAMES_4K (6)
625
626/*4 scratch frames for the new frames to support a maximum of 4 cores decoding
627 *in parallel, 3 for scaled references on the encoder.
628 *TODO(hkuang): Add ondemand frame buffers instead of hardcoding the number
629 * // of framebuffers.
630 *TODO(jkoleszar): These 3 extra references could probably come from the
631 *normal reference pool.
632 */
633#define FRAME_BUFFERS (REF_FRAMES + 16)
634#define HEADER_FRAME_BUFFERS (FRAME_BUFFERS)
635#define MAX_BUF_NUM (FRAME_BUFFERS)
636#define MV_BUFFER_NUM FRAME_BUFFERS
637#ifdef SUPPORT_FB_DECODING
638#define STAGE_MAX_BUFFERS 16
639#else
640#define STAGE_MAX_BUFFERS 0
641#endif
642
643#define FRAME_CONTEXTS_LOG2 2
644#define FRAME_CONTEXTS (1 << FRAME_CONTEXTS_LOG2)
645/*buffer + header buffer + workspace*/
646#ifdef MV_USE_FIXED_BUF
647#define MAX_BMMU_BUFFER_NUM (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + 1)
648#define VF_BUFFER_IDX(n) (n)
649#define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n)
650#define WORK_SPACE_BUF_ID (FRAME_BUFFERS + HEADER_FRAME_BUFFERS)
651#else
652#define MAX_BMMU_BUFFER_NUM \
653 (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + MV_BUFFER_NUM + 1)
654#define VF_BUFFER_IDX(n) (n)
655#define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n)
656#define MV_BUFFER_IDX(n) (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + n)
657#define WORK_SPACE_BUF_ID \
658 (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + MV_BUFFER_NUM)
659#endif
660
661struct RefCntBuffer_s {
662 int ref_count;
663 /*MV_REF *mvs;*/
664 int mi_rows;
665 int mi_cols;
666 struct vpx_codec_frame_buffer_s raw_frame_buffer;
667 struct PIC_BUFFER_CONFIG_s buf;
668
669/*The Following variables will only be used in frame parallel decode.
670 *
671 *frame_worker_owner indicates which FrameWorker owns this buffer. NULL means
672 *that no FrameWorker owns, or is decoding, this buffer.
673 *VP9Worker *frame_worker_owner;
674 *
675 *row and col indicate which position frame has been decoded to in real
676 *pixel unit. They are reset to -1 when decoding begins and set to INT_MAX
677 *when the frame is fully decoded.
678 */
679 int row;
680 int col;
681} RefCntBuffer;
682
683struct RefBuffer_s {
684/*TODO(dkovalev): idx is not really required and should be removed, now it
685 *is used in vp9_onyxd_if.c
686 */
687 int idx;
688 struct PIC_BUFFER_CONFIG_s *buf;
689 /*struct scale_factors sf;*/
690} RefBuffer;
691
692struct InternalFrameBuffer_s {
693 uint8_t *data;
694 size_t size;
695 int in_use;
696} InternalFrameBuffer;
697
698struct InternalFrameBufferList_s {
699 int num_internal_frame_buffers;
700 struct InternalFrameBuffer_s *int_fb;
701} InternalFrameBufferList;
702
703struct BufferPool_s {
704/*Protect BufferPool from being accessed by several FrameWorkers at
705 *the same time during frame parallel decode.
706 *TODO(hkuang): Try to use atomic variable instead of locking the whole pool.
707 *
708 *Private data associated with the frame buffer callbacks.
709 *void *cb_priv;
710 *
711 *vpx_get_frame_buffer_cb_fn_t get_fb_cb;
712 *vpx_release_frame_buffer_cb_fn_t release_fb_cb;
713 */
714
715 struct RefCntBuffer_s frame_bufs[FRAME_BUFFERS];
716
717/*Frame buffers allocated internally by the codec.*/
718 struct InternalFrameBufferList_s int_frame_buffers;
719 unsigned long flags;
720 spinlock_t lock;
721
722} BufferPool;
723
724#define lock_buffer_pool(pool, flags) \
725 spin_lock_irqsave(&pool->lock, flags)
726
727#define unlock_buffer_pool(pool, flags) \
728 spin_unlock_irqrestore(&pool->lock, flags)
729
730struct VP9_Common_s {
731 enum vpx_color_space_t color_space;
732 int width;
733 int height;
734 int display_width;
735 int display_height;
736 int last_width;
737 int last_height;
738
739 int subsampling_x;
740 int subsampling_y;
741
742 int use_highbitdepth;/*Marks if we need to use 16bit frame buffers.*/
743
744 struct PIC_BUFFER_CONFIG_s *frame_to_show;
745 struct RefCntBuffer_s *prev_frame;
746
747 /*TODO(hkuang): Combine this with cur_buf in macroblockd.*/
748 struct RefCntBuffer_s *cur_frame;
749
750 int ref_frame_map[REF_FRAMES]; /* maps fb_idx to reference slot */
751
752 /*Prepare ref_frame_map for the next frame.
753 *Only used in frame parallel decode.
754 */
755 int next_ref_frame_map[REF_FRAMES];
756
757 /* TODO(jkoleszar): could expand active_ref_idx to 4,
758 *with 0 as intra, and roll new_fb_idx into it.
759 */
760
761 /*Each frame can reference REFS_PER_FRAME buffers*/
762 struct RefBuffer_s frame_refs[REFS_PER_FRAME];
763
764 int prev_fb_idx;
765 int new_fb_idx;
766 int cur_fb_idx_mmu;
767 /*last frame's frame type for motion search*/
768 enum FRAME_TYPE last_frame_type;
769 enum FRAME_TYPE frame_type;
770
771 int show_frame;
772 int last_show_frame;
773 int show_existing_frame;
774
775 /*Flag signaling that the frame is encoded using only INTRA modes.*/
776 uint8_t intra_only;
777 uint8_t last_intra_only;
778
779 int allow_high_precision_mv;
780
781 /*Flag signaling that the frame context should be reset to default
782 *values. 0 or 1 implies don't reset, 2 reset just the context
783 *specified in the frame header, 3 reset all contexts.
784 */
785 int reset_frame_context;
786
787 /*MBs, mb_rows/cols is in 16-pixel units; mi_rows/cols is in
788 * MODE_INFO (8-pixel) units.
789 */
790 int MBs;
791 int mb_rows, mi_rows;
792 int mb_cols, mi_cols;
793 int mi_stride;
794
795 /*Whether to use previous frame's motion vectors for prediction.*/
796 int use_prev_frame_mvs;
797
798 int refresh_frame_context; /* Two state 0 = NO, 1 = YES */
799
800 int ref_frame_sign_bias[MAX_REF_FRAMES]; /* Two state 0, 1 */
801
802 /*struct loopfilter lf;*/
803 /*struct segmentation seg;*/
804
805 /*TODO(hkuang):Remove this as it is the same as frame_parallel_decode*/
806 /* in pbi.*/
807 int frame_parallel_decode; /* frame-based threading.*/
808
809 /*Context probabilities for reference frame prediction*/
810 /*MV_REFERENCE_FRAME comp_fixed_ref;*/
811 /*MV_REFERENCE_FRAME comp_var_ref[2];*/
812 enum REFERENCE_MODE reference_mode;
813
814 /*FRAME_CONTEXT *fc; */ /* this frame entropy */
815 /*FRAME_CONTEXT *frame_contexts; */ /*FRAME_CONTEXTS*/
816 /*unsigned int frame_context_idx; *//* Context to use/update */
817 /*FRAME_COUNTS counts;*/
818
819 unsigned int current_video_frame;
820 enum BITSTREAM_PROFILE profile;
821
822 enum vpx_bit_depth_t bit_depth;
823
824 int error_resilient_mode;
825 int frame_parallel_decoding_mode;
826
827 int byte_alignment;
828 int skip_loop_filter;
829
830 /*External BufferPool passed from outside.*/
831 struct BufferPool_s *buffer_pool;
832
833 int above_context_alloc_cols;
834
835};
836
837static void set_canvas(struct VP9Decoder_s *pbi,
838 struct PIC_BUFFER_CONFIG_s *pic_config);
839static int prepare_display_buf(struct VP9Decoder_s *pbi,
840 struct PIC_BUFFER_CONFIG_s *pic_config);
841
842static void fill_frame_info(struct VP9Decoder_s *pbi,
843 struct PIC_BUFFER_CONFIG_s *frame,
844 unsigned int framesize,
845 unsigned int pts);
846
847static struct PIC_BUFFER_CONFIG_s *get_frame_new_buffer(struct VP9_Common_s *cm)
848{
849 return &cm->buffer_pool->frame_bufs[cm->new_fb_idx].buf;
850}
851
852static void ref_cnt_fb(struct RefCntBuffer_s *bufs, int *idx, int new_idx)
853{
854 const int ref_index = *idx;
855
856 if (ref_index >= 0 && bufs[ref_index].ref_count > 0) {
857 bufs[ref_index].ref_count--;
858 /*pr_info("[MMU DEBUG 2] dec ref_count[%d] : %d\r\n",
859 * ref_index, bufs[ref_index].ref_count);
860 */
861 }
862
863 *idx = new_idx;
864
865 bufs[new_idx].ref_count++;
866 /*pr_info("[MMU DEBUG 3] inc ref_count[%d] : %d\r\n",
867 * new_idx, bufs[new_idx].ref_count);
868 */
869}
870
871int vp9_release_frame_buffer(struct vpx_codec_frame_buffer_s *fb)
872{
873 struct InternalFrameBuffer_s *const int_fb =
874 (struct InternalFrameBuffer_s *)fb->priv;
875 if (int_fb)
876 int_fb->in_use = 0;
877 return 0;
878}
879
880static int compute_losless_comp_body_size(int width, int height,
881 uint8_t is_bit_depth_10);
882
883static void setup_display_size(struct VP9_Common_s *cm, union param_u *params,
884 int print_header_info)
885{
886 cm->display_width = cm->width;
887 cm->display_height = cm->height;
888 if (params->p.display_size_present) {
889 if (print_header_info)
890 pr_info(" * 1-bit display_size_present read : 1\n");
891 cm->display_width = params->p.display_width;
892 cm->display_height = params->p.display_height;
893 /*vp9_read_frame_size(rb, &cm->display_width,
894 * &cm->display_height);
895 */
896 } else {
897 if (print_header_info)
898 pr_info(" * 1-bit display_size_present read : 0\n");
899 }
900}
901
902
903uint8_t print_header_info = 0;
904
905struct buff_s {
906 u32 buf_start;
907 u32 buf_size;
908 u32 buf_end;
909} buff_t;
910
911struct BuffInfo_s {
912 u32 max_width;
913 u32 max_height;
914 u32 start_adr;
915 u32 end_adr;
916 struct buff_s ipp;
917 struct buff_s sao_abv;
918 struct buff_s sao_vb;
919 struct buff_s short_term_rps;
920 struct buff_s vps;
921 struct buff_s sps;
922 struct buff_s pps;
923 struct buff_s sao_up;
924 struct buff_s swap_buf;
925 struct buff_s swap_buf2;
926 struct buff_s scalelut;
927 struct buff_s dblk_para;
928 struct buff_s dblk_data;
929 struct buff_s seg_map;
930 struct buff_s mmu_vbh;
931 struct buff_s cm_header;
932 struct buff_s mpred_above;
933#ifdef MV_USE_FIXED_BUF
934 struct buff_s mpred_mv;
935#endif
936 struct buff_s rpm;
937 struct buff_s lmem;
938} BuffInfo_t;
939#ifdef MULTI_INSTANCE_SUPPORT
940#define DEC_RESULT_NONE 0
941#define DEC_RESULT_DONE 1
942#define DEC_RESULT_AGAIN 2
943#define DEC_RESULT_CONFIG_PARAM 3
944#define DEC_RESULT_ERROR 4
945#define DEC_INIT_PICLIST 5
946#define DEC_UNINIT_PICLIST 6
947#define DEC_RESULT_GET_DATA 7
948#define DEC_RESULT_GET_DATA_RETRY 8
949#define DEC_RESULT_EOS 9
950#define DEC_RESULT_FORCE_EXIT 10
951#define DEC_V4L2_CONTINUE_DECODING 18
952
953#define DEC_S1_RESULT_NONE 0
954#define DEC_S1_RESULT_DONE 1
955#define DEC_S1_RESULT_FORCE_EXIT 2
956#define DEC_S1_RESULT_TEST_TRIGGER_DONE 0xf0
957
958#ifdef FB_DECODING_TEST_SCHEDULE
959#define TEST_SET_NONE 0
960#define TEST_SET_PIC_DONE 1
961#define TEST_SET_S2_DONE 2
962#endif
963
964static void vp9_work(struct work_struct *work);
965#endif
966struct loop_filter_info_n;
967struct loopfilter;
968struct segmentation;
969
970#ifdef SUPPORT_FB_DECODING
971static void mpred_process(struct VP9Decoder_s *pbi);
972static void vp9_s1_work(struct work_struct *work);
973
974struct stage_buf_s {
975 int index;
976 unsigned short rpm[RPM_END - RPM_BEGIN];
977};
978
979static unsigned int not_run2_ready[MAX_DECODE_INSTANCE_NUM];
980
981static unsigned int run2_count[MAX_DECODE_INSTANCE_NUM];
982
983#ifdef FB_DECODING_TEST_SCHEDULE
984u32 stage_buf_num; /* = 16;*/
985#else
986u32 stage_buf_num;
987#endif
988#endif
989
990struct VP9Decoder_s {
991#ifdef MULTI_INSTANCE_SUPPORT
992 unsigned char index;
993
994 struct device *cma_dev;
995 struct platform_device *platform_dev;
996 void (*vdec_cb)(struct vdec_s *, void *);
997 void *vdec_cb_arg;
998 struct vframe_chunk_s *chunk;
999 int dec_result;
1000 struct work_struct work;
1001 struct work_struct recycle_mmu_work;
1002 struct work_struct set_clk_work;
1003 u32 start_shift_bytes;
1004
1005 struct BuffInfo_s work_space_buf_store;
1006 unsigned long buf_start;
1007 u32 buf_size;
1008 u32 cma_alloc_count;
1009 unsigned long cma_alloc_addr;
1010 uint8_t eos;
1011 unsigned long int start_process_time;
1012 unsigned last_lcu_idx;
1013 int decode_timeout_count;
1014 unsigned timeout_num;
1015 int save_buffer_mode;
1016
1017 int double_write_mode;
1018#endif
1019 long used_4k_num;
1020
1021 unsigned char m_ins_flag;
1022 char *provider_name;
1023 union param_u param;
1024 int frame_count;
1025 int pic_count;
1026 u32 stat;
1027 struct timer_list timer;
1028 u32 frame_dur;
1029 u32 frame_ar;
1030 int fatal_error;
1031 uint8_t init_flag;
1032 uint8_t first_sc_checked;
1033 uint8_t process_busy;
1034#define PROC_STATE_INIT 0
1035#define PROC_STATE_DECODESLICE 1
1036#define PROC_STATE_SENDAGAIN 2
1037 uint8_t process_state;
1038 u32 ucode_pause_pos;
1039
1040 int show_frame_num;
1041 struct buff_s mc_buf_spec;
1042 struct dec_sysinfo vvp9_amstream_dec_info;
1043 void *rpm_addr;
1044 void *lmem_addr;
1045 dma_addr_t rpm_phy_addr;
1046 dma_addr_t lmem_phy_addr;
1047 unsigned short *lmem_ptr;
1048 unsigned short *debug_ptr;
1049
1050 void *prob_buffer_addr;
1051 void *count_buffer_addr;
1052 dma_addr_t prob_buffer_phy_addr;
1053 dma_addr_t count_buffer_phy_addr;
1054
1055 void *frame_mmu_map_addr;
1056 dma_addr_t frame_mmu_map_phy_addr;
1057
1058 unsigned int use_cma_flag;
1059
1060 struct BUF_s m_BUF[MAX_BUF_NUM];
1061 struct MVBUF_s m_mv_BUF[MV_BUFFER_NUM];
1062 u32 used_buf_num;
1063 DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
1064 DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
1065 DECLARE_KFIFO(pending_q, struct vframe_s *, VF_POOL_SIZE);
1066 struct vframe_s vfpool[VF_POOL_SIZE];
1067 u32 vf_pre_count;
1068 u32 vf_get_count;
1069 u32 vf_put_count;
1070 int buf_num;
1071 int pic_num;
1072 int lcu_size_log2;
1073 unsigned int losless_comp_body_size;
1074
1075 u32 video_signal_type;
1076
1077 int pts_mode;
1078 int last_lookup_pts;
1079 int last_pts;
1080 u64 last_lookup_pts_us64;
1081 u64 last_pts_us64;
1082 u64 shift_byte_count;
1083
1084 u32 pts_unstable;
1085 u32 frame_cnt_window;
1086 u32 pts1, pts2;
1087 u32 last_duration;
1088 u32 duration_from_pts_done;
1089 bool vp9_first_pts_ready;
1090
1091 u32 shift_byte_count_lo;
1092 u32 shift_byte_count_hi;
1093 int pts_mode_switching_count;
1094 int pts_mode_recovery_count;
1095
1096 bool get_frame_dur;
1097 u32 saved_resolution;
1098
1099 /**/
1100 struct VP9_Common_s common;
1101 struct RefCntBuffer_s *cur_buf;
1102 int refresh_frame_flags;
1103 uint8_t need_resync;
1104 uint8_t hold_ref_buf;
1105 uint8_t ready_for_new_data;
1106 struct BufferPool_s vp9_buffer_pool;
1107
1108 struct BuffInfo_s *work_space_buf;
1109
1110 struct buff_s *mc_buf;
1111
1112 unsigned int frame_width;
1113 unsigned int frame_height;
1114
1115 unsigned short *rpm_ptr;
1116 int init_pic_w;
1117 int init_pic_h;
1118 int lcu_total;
1119 int lcu_size;
1120
1121 int slice_type;
1122
1123 int skip_flag;
1124 int decode_idx;
1125 int slice_idx;
1126 uint8_t has_keyframe;
1127 uint8_t wait_buf;
1128 uint8_t error_flag;
1129
1130 /* bit 0, for decoding; bit 1, for displaying */
1131 uint8_t ignore_bufmgr_error;
1132 int PB_skip_mode;
1133 int PB_skip_count_after_decoding;
1134 /*hw*/
1135
1136 /*lf*/
1137 int default_filt_lvl;
1138 struct loop_filter_info_n *lfi;
1139 struct loopfilter *lf;
1140 struct segmentation *seg_4lf;
1141 /**/
1142 struct vdec_info *gvs;
1143
1144 u32 pre_stream_offset;
1145
1146 unsigned int dec_status;
1147 u32 last_put_idx;
1148 int new_frame_displayed;
1149 void *mmu_box;
1150 void *bmmu_box;
1151 int mmu_enable;
1152 struct vframe_master_display_colour_s vf_dp;
1153 struct firmware_s *fw;
1154 int max_pic_w;
1155 int max_pic_h;
1156#ifdef SUPPORT_FB_DECODING
1157 int dec_s1_result;
1158 int s1_test_cmd;
1159 struct work_struct s1_work;
1160 int used_stage_buf_num;
1161 int s1_pos;
1162 int s2_pos;
1163 void *stage_mmu_map_addr;
1164 dma_addr_t stage_mmu_map_phy_addr;
1165 struct stage_buf_s *s1_buf;
1166 struct stage_buf_s *s2_buf;
1167 struct stage_buf_s *stage_bufs
1168 [STAGE_MAX_BUFFERS];
1169 unsigned char run2_busy;
1170
1171 int s1_mv_buf_index;
1172 int s1_mv_buf_index_pre;
1173 int s1_mv_buf_index_pre_pre;
1174 unsigned long s1_mpred_mv_wr_start_addr;
1175 unsigned long s1_mpred_mv_wr_start_addr_pre;
1176 unsigned short s1_intra_only;
1177 unsigned short s1_frame_type;
1178 unsigned short s1_width;
1179 unsigned short s1_height;
1180 unsigned short s1_last_show_frame;
1181 union param_u s1_param;
1182 u8 back_not_run_ready;
1183#endif
1184 int need_cache_size;
1185 u64 sc_start_time;
1186 bool postproc_done;
1187 int low_latency_flag;
1188 bool no_head;
1189 bool pic_list_init_done;
1190 bool pic_list_init_done2;
1191 bool is_used_v4l;
1192 void *v4l2_ctx;
1193 bool v4l_params_parsed;
1194 int frameinfo_enable;
1195 struct vframe_qos_s vframe_qos;
1196 u32 mem_map_mode;
1197 u32 dynamic_buf_num_margin;
1198 struct vframe_s vframe_dummy;
1199 unsigned int res_ch_flag;
1200 /*struct VP9Decoder_s vp9_decoder;*/
1201 union param_u vp9_param;
1202};
1203
1204static int vp9_print(struct VP9Decoder_s *pbi,
1205 int flag, const char *fmt, ...)
1206{
1207#define HEVC_PRINT_BUF 256
1208 unsigned char buf[HEVC_PRINT_BUF];
1209 int len = 0;
1210
1211 if (pbi == NULL ||
1212 (flag == 0) ||
1213 (debug & flag)) {
1214 va_list args;
1215
1216 va_start(args, fmt);
1217 if (pbi)
1218 len = sprintf(buf, "[%d]", pbi->index);
1219 vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
1220 pr_debug("%s", buf);
1221 va_end(args);
1222 }
1223 return 0;
1224}
1225
1226static int is_oversize(int w, int h)
1227{
1228 int max = (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)?
1229 MAX_SIZE_8K : MAX_SIZE_4K;
1230
1231 if (w <= 0 || h <= 0)
1232 return true;
1233
1234 if (h != 0 && (w > max / h))
1235 return true;
1236
1237 return false;
1238}
1239
1240static int v4l_alloc_and_config_pic(struct VP9Decoder_s *pbi,
1241 struct PIC_BUFFER_CONFIG_s *pic);
1242
1243static void resize_context_buffers(struct VP9Decoder_s *pbi,
1244 struct VP9_Common_s *cm, int width, int height)
1245{
1246 if (cm->width != width || cm->height != height) {
1247 /* to do ..*/
1248 if (pbi != NULL) {
1249 pbi->vp9_first_pts_ready = 0;
1250 pbi->duration_from_pts_done = 0;
1251 }
1252 pr_info("%s (%d,%d)=>(%d,%d)\r\n", __func__, cm->width,
1253 cm->height, width, height);
1254 cm->width = width;
1255 cm->height = height;
1256 }
1257 /*
1258 *if (cm->cur_frame->mvs == NULL ||
1259 * cm->mi_rows > cm->cur_frame->mi_rows ||
1260 * cm->mi_cols > cm->cur_frame->mi_cols) {
1261 * resize_mv_buffer(cm);
1262 *}
1263 */
1264}
1265
1266static int valid_ref_frame_size(int ref_width, int ref_height,
1267 int this_width, int this_height) {
1268 return 2 * this_width >= ref_width &&
1269 2 * this_height >= ref_height &&
1270 this_width <= 16 * ref_width &&
1271 this_height <= 16 * ref_height;
1272}
1273
1274/*
1275 *static int valid_ref_frame_img_fmt(enum vpx_bit_depth_t ref_bit_depth,
1276 * int ref_xss, int ref_yss,
1277 * enum vpx_bit_depth_t this_bit_depth,
1278 * int this_xss, int this_yss) {
1279 * return ref_bit_depth == this_bit_depth && ref_xss == this_xss &&
1280 * ref_yss == this_yss;
1281 *}
1282 */
1283
1284
1285static int setup_frame_size(
1286 struct VP9Decoder_s *pbi,
1287 struct VP9_Common_s *cm, union param_u *params,
1288 unsigned int *mmu_index_adr,
1289 int print_header_info) {
1290 int width, height;
1291 struct BufferPool_s * const pool = cm->buffer_pool;
1292 struct PIC_BUFFER_CONFIG_s *ybf;
1293 int ret = 0;
1294
1295 width = params->p.width;
1296 height = params->p.height;
1297 if (is_oversize(width, height)) {
1298 vp9_print(pbi, 0, "%s, Error: Invalid frame size\n", __func__);
1299 return -1;
1300 }
1301
1302 /*vp9_read_frame_size(rb, &width, &height);*/
1303 if (print_header_info)
1304 pr_info(" * 16-bits w read : %d (width : %d)\n", width, height);
1305 if (print_header_info)
1306 pr_info
1307 (" * 16-bits h read : %d (height : %d)\n", width, height);
1308
1309 WRITE_VREG(HEVC_PARSER_PICTURE_SIZE, (height << 16) | width);
1310#ifdef VP9_10B_HED_FB
1311 WRITE_VREG(HEVC_ASSIST_PIC_SIZE_FB_READ, (height << 16) | width);
1312#endif
1313 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
1314 ret = vp9_alloc_mmu(pbi,
1315 cm->new_fb_idx,
1316 params->p.width,
1317 params->p.height,
1318 params->p.bit_depth,
1319 mmu_index_adr);
1320 if (ret != 0) {
1321 pr_err("can't alloc need mmu1,idx %d ret =%d\n",
1322 cm->new_fb_idx,
1323 ret);
1324 return ret;
1325 }
1326 cm->cur_fb_idx_mmu = cm->new_fb_idx;
1327 }
1328
1329 resize_context_buffers(pbi, cm, width, height);
1330 setup_display_size(cm, params, print_header_info);
1331#if 0
1332 lock_buffer_pool(pool);
1333 if (vp9_realloc_frame_buffer(
1334 get_frame_new_buffer(cm), cm->width, cm->height,
1335 cm->subsampling_x, cm->subsampling_y,
1336#if CONFIG_VP9_HIGHBITDEPTH
1337 cm->use_highbitdepth,
1338#endif
1339 VP9_DEC_BORDER_IN_PIXELS,
1340 cm->byte_alignment,
1341 &pool->frame_bufs[cm->new_fb_idx].raw_frame_buffer,
1342 pool->get_fb_cb, pool->cb_priv)) {
1343 unlock_buffer_pool(pool);
1344 vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR,
1345 "Failed to allocate frame buffer");
1346 }
1347 unlock_buffer_pool(pool);
1348#else
1349 /* porting */
1350 ybf = get_frame_new_buffer(cm);
1351 if (!ybf)
1352 return -1;
1353
1354 ybf->y_crop_width = width;
1355 ybf->y_crop_height = height;
1356 ybf->bit_depth = params->p.bit_depth;
1357#endif
1358 pool->frame_bufs[cm->new_fb_idx].buf.subsampling_x = cm->subsampling_x;
1359 pool->frame_bufs[cm->new_fb_idx].buf.subsampling_y = cm->subsampling_y;
1360 pool->frame_bufs[cm->new_fb_idx].buf.bit_depth =
1361 (unsigned int)cm->bit_depth;
1362 pool->frame_bufs[cm->new_fb_idx].buf.color_space = cm->color_space;
1363 return ret;
1364}
1365
1366static int setup_frame_size_with_refs(
1367 struct VP9Decoder_s *pbi,
1368 struct VP9_Common_s *cm,
1369 union param_u *params,
1370 unsigned int *mmu_index_adr,
1371 int print_header_info) {
1372
1373 int width, height;
1374 int found = 0, i;
1375 int has_valid_ref_frame = 0;
1376 struct PIC_BUFFER_CONFIG_s *ybf;
1377 struct BufferPool_s * const pool = cm->buffer_pool;
1378 int ret = 0;
1379
1380 for (i = 0; i < REFS_PER_FRAME; ++i) {
1381 if ((params->p.same_frame_size >>
1382 (REFS_PER_FRAME - i - 1)) & 0x1) {
1383 struct PIC_BUFFER_CONFIG_s *const buf =
1384 cm->frame_refs[i].buf;
1385 /*if (print_header_info)
1386 * pr_info
1387 * ("1-bit same_frame_size[%d] read : 1\n", i);
1388 */
1389 width = buf->y_crop_width;
1390 height = buf->y_crop_height;
1391 /*if (print_header_info)
1392 * pr_info
1393 * (" - same_frame_size width : %d\n", width);
1394 */
1395 /*if (print_header_info)
1396 * pr_info
1397 * (" - same_frame_size height : %d\n", height);
1398 */
1399 found = 1;
1400 break;
1401 } else {
1402 /*if (print_header_info)
1403 * pr_info
1404 * ("1-bit same_frame_size[%d] read : 0\n", i);
1405 */
1406 }
1407 }
1408
1409 if (!found) {
1410 /*vp9_read_frame_size(rb, &width, &height);*/
1411 width = params->p.width;
1412 height = params->p.height;
1413 /*if (print_header_info)
1414 * pr_info
1415 * (" * 16-bits w read : %d (width : %d)\n",
1416 * width, height);
1417 *if (print_header_info)
1418 * pr_info
1419 * (" * 16-bits h read : %d (height : %d)\n",
1420 * width, height);
1421 */
1422 }
1423
1424 if (is_oversize(width, height)) {
1425 vp9_print(pbi, 0, "%s, Error: Invalid frame size\n", __func__);
1426 return -1;
1427 }
1428
1429 params->p.width = width;
1430 params->p.height = height;
1431
1432 WRITE_VREG(HEVC_PARSER_PICTURE_SIZE, (height << 16) | width);
1433 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
1434 /*if(cm->prev_fb_idx >= 0) release_unused_4k(cm->prev_fb_idx);
1435 *cm->prev_fb_idx = cm->new_fb_idx;
1436 */
1437 /* pr_info
1438 * ("[DEBUG DEBUG]Before alloc_mmu,
1439 * prev_fb_idx : %d, new_fb_idx : %d\r\n",
1440 * cm->prev_fb_idx, cm->new_fb_idx);
1441 */
1442 ret = vp9_alloc_mmu(pbi, cm->new_fb_idx,
1443 params->p.width, params->p.height,
1444 params->p.bit_depth, mmu_index_adr);
1445 if (ret != 0) {
1446 pr_err("can't alloc need mmu,idx %d\r\n",
1447 cm->new_fb_idx);
1448 return ret;
1449 }
1450 cm->cur_fb_idx_mmu = cm->new_fb_idx;
1451 }
1452
1453 /*Check to make sure at least one of frames that this frame references
1454 *has valid dimensions.
1455 */
1456 for (i = 0; i < REFS_PER_FRAME; ++i) {
1457 struct RefBuffer_s * const ref_frame = &cm->frame_refs[i];
1458
1459 has_valid_ref_frame |=
1460 valid_ref_frame_size(ref_frame->buf->y_crop_width,
1461 ref_frame->buf->y_crop_height,
1462 width, height);
1463 }
1464 if (!has_valid_ref_frame) {
1465 pr_err("Error: Referenced frame has invalid size\r\n");
1466 return -1;
1467 }
1468#if 0
1469 for (i = 0; i < REFS_PER_FRAME; ++i) {
1470 struct RefBuffer_s * const ref_frame =
1471 &cm->frame_refs[i];
1472 if (!valid_ref_frame_img_fmt(
1473 ref_frame->buf->bit_depth,
1474 ref_frame->buf->subsampling_x,
1475 ref_frame->buf->subsampling_y,
1476 cm->bit_depth,
1477 cm->subsampling_x,
1478 cm->subsampling_y))
1479 pr_err
1480 ("Referenced frame incompatible color fmt\r\n");
1481 return -1;
1482 }
1483#endif
1484 resize_context_buffers(pbi, cm, width, height);
1485 setup_display_size(cm, params, print_header_info);
1486
1487#if 0
1488 lock_buffer_pool(pool);
1489 if (vp9_realloc_frame_buffer(
1490 get_frame_new_buffer(cm), cm->width, cm->height,
1491 cm->subsampling_x, cm->subsampling_y,
1492#if CONFIG_VP9_HIGHBITDEPTH
1493 cm->use_highbitdepth,
1494#endif
1495 VP9_DEC_BORDER_IN_PIXELS,
1496 cm->byte_alignment,
1497 &pool->frame_bufs[cm->new_fb_idx].raw_frame_buffer,
1498 pool->get_fb_cb,
1499 pool->cb_priv)) {
1500 unlock_buffer_pool(pool);
1501 vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR,
1502 "Failed to allocate frame buffer");
1503 }
1504 unlock_buffer_pool(pool);
1505#else
1506 /* porting */
1507 ybf = get_frame_new_buffer(cm);
1508 if (!ybf)
1509 return -1;
1510
1511 ybf->y_crop_width = width;
1512 ybf->y_crop_height = height;
1513 ybf->bit_depth = params->p.bit_depth;
1514#endif
1515 pool->frame_bufs[cm->new_fb_idx].buf.subsampling_x = cm->subsampling_x;
1516 pool->frame_bufs[cm->new_fb_idx].buf.subsampling_y = cm->subsampling_y;
1517 pool->frame_bufs[cm->new_fb_idx].buf.bit_depth =
1518 (unsigned int)cm->bit_depth;
1519 pool->frame_bufs[cm->new_fb_idx].buf.color_space = cm->color_space;
1520 return ret;
1521}
1522
1523static inline bool close_to(int a, int b, int m)
1524{
1525 return (abs(a - b) < m) ? true : false;
1526}
1527
1528#ifdef MULTI_INSTANCE_SUPPORT
1529static int vp9_print_cont(struct VP9Decoder_s *pbi,
1530 int flag, const char *fmt, ...)
1531{
1532 unsigned char buf[HEVC_PRINT_BUF];
1533 int len = 0;
1534
1535 if (pbi == NULL ||
1536 (flag == 0) ||
1537 (debug & flag)) {
1538 va_list args;
1539
1540 va_start(args, fmt);
1541 vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
1542 pr_debug("%s", buf);
1543 va_end(args);
1544 }
1545 return 0;
1546}
1547
1548static void trigger_schedule(struct VP9Decoder_s *pbi)
1549{
1550 if (pbi->is_used_v4l) {
1551 struct aml_vcodec_ctx *ctx =
1552 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
1553
1554 if (ctx->param_sets_from_ucode &&
1555 !pbi->v4l_params_parsed)
1556 vdec_v4l_write_frame_sync(ctx);
1557 }
1558
1559 if (pbi->vdec_cb)
1560 pbi->vdec_cb(hw_to_vdec(pbi), pbi->vdec_cb_arg);
1561}
1562
1563static void reset_process_time(struct VP9Decoder_s *pbi)
1564{
1565 if (pbi->start_process_time) {
1566 unsigned process_time =
1567 1000 * (jiffies - pbi->start_process_time) / HZ;
1568 pbi->start_process_time = 0;
1569 if (process_time > max_process_time[pbi->index])
1570 max_process_time[pbi->index] = process_time;
1571 }
1572}
1573
1574static void start_process_time(struct VP9Decoder_s *pbi)
1575{
1576 pbi->start_process_time = jiffies;
1577 pbi->decode_timeout_count = 0;
1578 pbi->last_lcu_idx = 0;
1579}
1580
1581static void timeout_process(struct VP9Decoder_s *pbi)
1582{
1583 pbi->timeout_num++;
1584 amhevc_stop();
1585 vp9_print(pbi,
1586 0, "%s decoder timeout\n", __func__);
1587
1588 pbi->dec_result = DEC_RESULT_DONE;
1589 reset_process_time(pbi);
1590 vdec_schedule_work(&pbi->work);
1591}
1592
1593static u32 get_valid_double_write_mode(struct VP9Decoder_s *pbi)
1594{
1595 return ((double_write_mode & 0x80000000) == 0) ?
1596 pbi->double_write_mode :
1597 (double_write_mode & 0x7fffffff);
1598}
1599
1600static int v4l_parser_get_double_write_mode(struct VP9Decoder_s *pbi)
1601{
1602 u32 valid_dw_mode = get_valid_double_write_mode(pbi);
1603 u32 dw;
1604 int w, h;
1605
1606 /* mask for supporting double write value bigger than 0x100 */
1607 if (valid_dw_mode & 0xffffff00) {
1608 w = pbi->frame_width;
1609 h = pbi->frame_height;
1610
1611 dw = 0x1; /*1:1*/
1612 switch (valid_dw_mode) {
1613 case 0x100:
1614 if (w > 1920 && h > 1088)
1615 dw = 0x4; /*1:2*/
1616 break;
1617 case 0x200:
1618 if (w > 1920 && h > 1088)
1619 dw = 0x2; /*1:4*/
1620 break;
1621 case 0x300:
1622 if (w > 1280 && h > 720)
1623 dw = 0x4; /*1:2*/
1624 break;
1625 default:
1626 break;
1627 }
1628 return dw;
1629 }
1630
1631 return valid_dw_mode;
1632}
1633
1634
1635static int get_double_write_mode(struct VP9Decoder_s *pbi)
1636{
1637 u32 valid_dw_mode = get_valid_double_write_mode(pbi);
1638 u32 dw;
1639 int w, h;
1640 struct VP9_Common_s *cm = &pbi->common;
1641 struct PIC_BUFFER_CONFIG_s *cur_pic_config;
1642
1643 /* mask for supporting double write value bigger than 0x100 */
1644 if (valid_dw_mode & 0xffffff00) {
1645 if (!cm->cur_frame)
1646 return 1;/*no valid frame,*/
1647 cur_pic_config = &cm->cur_frame->buf;
1648 w = cur_pic_config->y_crop_width;
1649 h = cur_pic_config->y_crop_height;
1650
1651 dw = 0x1; /*1:1*/
1652 switch (valid_dw_mode) {
1653 case 0x100:
1654 if (w > 1920 && h > 1088)
1655 dw = 0x4; /*1:2*/
1656 break;
1657 case 0x200:
1658 if (w > 1920 && h > 1088)
1659 dw = 0x2; /*1:4*/
1660 break;
1661 case 0x300:
1662 if (w > 1280 && h > 720)
1663 dw = 0x4; /*1:2*/
1664 break;
1665 default:
1666 break;
1667 }
1668 return dw;
1669 }
1670
1671 return valid_dw_mode;
1672}
1673
1674/* for double write buf alloc */
1675static int get_double_write_mode_init(struct VP9Decoder_s *pbi)
1676{
1677 u32 valid_dw_mode = get_valid_double_write_mode(pbi);
1678 u32 dw;
1679 int w = pbi->init_pic_w;
1680 int h = pbi->init_pic_h;
1681
1682 dw = 0x1; /*1:1*/
1683 switch (valid_dw_mode) {
1684 case 0x100:
1685 if (w > 1920 && h > 1088)
1686 dw = 0x4; /*1:2*/
1687 break;
1688 case 0x200:
1689 if (w > 1920 && h > 1088)
1690 dw = 0x2; /*1:4*/
1691 break;
1692 case 0x300:
1693 if (w > 1280 && h > 720)
1694 dw = 0x4; /*1:2*/
1695 break;
1696 default:
1697 dw = valid_dw_mode;
1698 break;
1699 }
1700 return dw;
1701}
1702#endif
1703
1704static int get_double_write_ratio(struct VP9Decoder_s *pbi,
1705 int dw_mode)
1706{
1707 int ratio = 1;
1708 if ((dw_mode == 2) ||
1709 (dw_mode == 3))
1710 ratio = 4;
1711 else if (dw_mode == 4)
1712 ratio = 2;
1713 return ratio;
1714}
1715
1716//#define MAX_4K_NUM 0x1200
1717
1718int vp9_alloc_mmu(
1719 struct VP9Decoder_s *pbi,
1720 int cur_buf_idx,
1721 int pic_width,
1722 int pic_height,
1723 unsigned short bit_depth,
1724 unsigned int *mmu_index_adr)
1725{
1726 int bit_depth_10 = (bit_depth == VPX_BITS_10);
1727 int picture_size;
1728 int cur_mmu_4k_number, max_frame_num;
1729 if (!pbi->mmu_box) {
1730 pr_err("error no mmu box!\n");
1731 return -1;
1732 }
1733 if (get_double_write_mode(pbi) == 0x10)
1734 return 0;
1735 if (bit_depth >= VPX_BITS_12) {
1736 pbi->fatal_error = DECODER_FATAL_ERROR_SIZE_OVERFLOW;
1737 pr_err("fatal_error, un support bit depth 12!\n\n");
1738 return -1;
1739 }
1740 picture_size = compute_losless_comp_body_size(pic_width, pic_height,
1741 bit_depth_10);
1742 cur_mmu_4k_number = ((picture_size + (1 << 12) - 1) >> 12);
1743
1744 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
1745 max_frame_num = MAX_FRAME_8K_NUM;
1746 else
1747 max_frame_num = MAX_FRAME_4K_NUM;
1748
1749 if (cur_mmu_4k_number > max_frame_num) {
1750 pr_err("over max !! cur_mmu_4k_number 0x%x width %d height %d\n",
1751 cur_mmu_4k_number, pic_width, pic_height);
1752 return -1;
1753 }
1754 return decoder_mmu_box_alloc_idx(
1755 pbi->mmu_box,
1756 cur_buf_idx,
1757 cur_mmu_4k_number,
1758 mmu_index_adr);
1759}
1760
1761
1762#ifndef MV_USE_FIXED_BUF
1763static void dealloc_mv_bufs(struct VP9Decoder_s *pbi)
1764{
1765 int i;
1766 for (i = 0; i < MV_BUFFER_NUM; i++) {
1767 if (pbi->m_mv_BUF[i].start_adr) {
1768 if (debug)
1769 pr_info(
1770 "dealloc mv buf(%d) adr %ld size 0x%x used_flag %d\n",
1771 i, pbi->m_mv_BUF[i].start_adr,
1772 pbi->m_mv_BUF[i].size,
1773 pbi->m_mv_BUF[i].used_flag);
1774 decoder_bmmu_box_free_idx(
1775 pbi->bmmu_box,
1776 MV_BUFFER_IDX(i));
1777 pbi->m_mv_BUF[i].start_adr = 0;
1778 pbi->m_mv_BUF[i].size = 0;
1779 pbi->m_mv_BUF[i].used_flag = 0;
1780 }
1781 }
1782}
1783
1784static int alloc_mv_buf(struct VP9Decoder_s *pbi,
1785 int i, int size)
1786{
1787 int ret = 0;
1788
1789 if (pbi->m_mv_BUF[i].start_adr &&
1790 size > pbi->m_mv_BUF[i].size) {
1791 dealloc_mv_bufs(pbi);
1792 } else if (pbi->m_mv_BUF[i].start_adr)
1793 return 0;
1794
1795 if (decoder_bmmu_box_alloc_buf_phy
1796 (pbi->bmmu_box,
1797 MV_BUFFER_IDX(i), size,
1798 DRIVER_NAME,
1799 &pbi->m_mv_BUF[i].start_adr) < 0) {
1800 pbi->m_mv_BUF[i].start_adr = 0;
1801 ret = -1;
1802 } else {
1803 pbi->m_mv_BUF[i].size = size;
1804 pbi->m_mv_BUF[i].used_flag = 0;
1805 ret = 0;
1806 if (debug) {
1807 pr_info(
1808 "MV Buffer %d: start_adr %p size %x\n",
1809 i,
1810 (void *)pbi->m_mv_BUF[i].start_adr,
1811 pbi->m_mv_BUF[i].size);
1812 }
1813 }
1814 return ret;
1815}
1816
1817static int init_mv_buf_list(struct VP9Decoder_s *pbi)
1818{
1819 int i;
1820 int ret = 0;
1821 int count = MV_BUFFER_NUM;
1822 int pic_width = pbi->init_pic_w;
1823 int pic_height = pbi->init_pic_h;
1824 int lcu_size = 64; /*fixed 64*/
1825 int pic_width_64 = (pic_width + 63) & (~0x3f);
1826 int pic_height_32 = (pic_height + 31) & (~0x1f);
1827 int pic_width_lcu = (pic_width_64 % lcu_size) ?
1828 pic_width_64 / lcu_size + 1
1829 : pic_width_64 / lcu_size;
1830 int pic_height_lcu = (pic_height_32 % lcu_size) ?
1831 pic_height_32 / lcu_size + 1
1832 : pic_height_32 / lcu_size;
1833 int lcu_total = pic_width_lcu * pic_height_lcu;
1834 int size = ((lcu_total * MV_MEM_UNIT) + 0xffff) &
1835 (~0xffff);
1836 if (mv_buf_margin > 0)
1837 count = REF_FRAMES + mv_buf_margin;
1838
1839 if (pbi->init_pic_w > 2048 && pbi->init_pic_h > 1088)
1840 count = REF_FRAMES_4K + mv_buf_margin;
1841
1842 if (debug) {
1843 pr_info("%s w:%d, h:%d, count: %d\n",
1844 __func__, pbi->init_pic_w, pbi->init_pic_h, count);
1845 }
1846
1847 for (i = 0;
1848 i < count && i < MV_BUFFER_NUM; i++) {
1849 if (alloc_mv_buf(pbi, i, size) < 0) {
1850 ret = -1;
1851 break;
1852 }
1853 }
1854 return ret;
1855}
1856
1857static int get_mv_buf(struct VP9Decoder_s *pbi,
1858 int *mv_buf_index,
1859 unsigned long *mpred_mv_wr_start_addr)
1860{
1861 int i;
1862 int ret = -1;
1863 for (i = 0; i < MV_BUFFER_NUM; i++) {
1864 if (pbi->m_mv_BUF[i].start_adr &&
1865 pbi->m_mv_BUF[i].used_flag == 0) {
1866 pbi->m_mv_BUF[i].used_flag = 1;
1867 ret = i;
1868 break;
1869 }
1870 }
1871
1872 if (ret >= 0) {
1873 *mv_buf_index = ret;
1874 *mpred_mv_wr_start_addr =
1875 (pbi->m_mv_BUF[ret].start_adr + 0xffff) &
1876 (~0xffff);
1877 if (debug & VP9_DEBUG_BUFMGR_MORE)
1878 pr_info(
1879 "%s => %d (%ld) size 0x%x\n",
1880 __func__, ret,
1881 *mpred_mv_wr_start_addr,
1882 pbi->m_mv_BUF[ret].size);
1883 } else {
1884 pr_info(
1885 "%s: Error, mv buf is not enough\n",
1886 __func__);
1887 }
1888 return ret;
1889}
1890
1891static void put_mv_buf(struct VP9Decoder_s *pbi,
1892 int *mv_buf_index)
1893{
1894 int i = *mv_buf_index;
1895 if (i >= MV_BUFFER_NUM) {
1896 if (debug & VP9_DEBUG_BUFMGR_MORE)
1897 pr_info(
1898 "%s: index %d beyond range\n",
1899 __func__, i);
1900 return;
1901 }
1902 if (debug & VP9_DEBUG_BUFMGR_MORE)
1903 pr_info(
1904 "%s(%d): used_flag(%d)\n",
1905 __func__, i,
1906 pbi->m_mv_BUF[i].used_flag);
1907
1908 *mv_buf_index = -1;
1909 if (pbi->m_mv_BUF[i].start_adr &&
1910 pbi->m_mv_BUF[i].used_flag)
1911 pbi->m_mv_BUF[i].used_flag = 0;
1912}
1913
1914static void put_un_used_mv_bufs(struct VP9Decoder_s *pbi)
1915{
1916 struct VP9_Common_s *const cm = &pbi->common;
1917 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
1918 int i;
1919 for (i = 0; i < pbi->used_buf_num; ++i) {
1920 if ((frame_bufs[i].ref_count == 0) &&
1921 (frame_bufs[i].buf.index != -1) &&
1922 (frame_bufs[i].buf.mv_buf_index >= 0)
1923 )
1924 put_mv_buf(pbi, &frame_bufs[i].buf.mv_buf_index);
1925 }
1926}
1927
1928#ifdef SUPPORT_FB_DECODING
1929static bool mv_buf_available(struct VP9Decoder_s *pbi)
1930{
1931 int i;
1932 bool ret = 0;
1933 for (i = 0; i < MV_BUFFER_NUM; i++) {
1934 if (pbi->m_mv_BUF[i].start_adr &&
1935 pbi->m_mv_BUF[i].used_flag == 0) {
1936 ret = 1;
1937 break;
1938 }
1939 }
1940 return ret;
1941}
1942#endif
1943#endif
1944
1945#ifdef SUPPORT_FB_DECODING
1946static void init_stage_buf(struct VP9Decoder_s *pbi)
1947{
1948 uint i;
1949 for (i = 0; i < STAGE_MAX_BUFFERS
1950 && i < stage_buf_num; i++) {
1951 pbi->stage_bufs[i] =
1952 vmalloc(sizeof(struct stage_buf_s));
1953 if (pbi->stage_bufs[i] == NULL) {
1954 vp9_print(pbi,
1955 0, "%s vmalloc fail\n", __func__);
1956 break;
1957 }
1958 pbi->stage_bufs[i]->index = i;
1959 }
1960 pbi->used_stage_buf_num = i;
1961 pbi->s1_pos = 0;
1962 pbi->s2_pos = 0;
1963 pbi->s1_buf = NULL;
1964 pbi->s2_buf = NULL;
1965 pbi->s1_mv_buf_index = FRAME_BUFFERS;
1966 pbi->s1_mv_buf_index_pre = FRAME_BUFFERS;
1967 pbi->s1_mv_buf_index_pre_pre = FRAME_BUFFERS;
1968
1969 if (pbi->used_stage_buf_num > 0)
1970 vp9_print(pbi,
1971 0, "%s 2 stage decoding buf %d\n",
1972 __func__,
1973 pbi->used_stage_buf_num);
1974}
1975
1976static void uninit_stage_buf(struct VP9Decoder_s *pbi)
1977{
1978 int i;
1979 for (i = 0; i < pbi->used_stage_buf_num; i++) {
1980 if (pbi->stage_bufs[i])
1981 vfree(pbi->stage_bufs[i]);
1982 pbi->stage_bufs[i] = NULL;
1983 }
1984 pbi->used_stage_buf_num = 0;
1985 pbi->s1_pos = 0;
1986 pbi->s2_pos = 0;
1987 pbi->s1_buf = NULL;
1988 pbi->s2_buf = NULL;
1989}
1990
1991static int get_s1_buf(
1992 struct VP9Decoder_s *pbi)
1993{
1994 struct stage_buf_s *buf = NULL;
1995 int ret = -1;
1996 int buf_page_num = MAX_STAGE_PAGE_NUM;
1997 int next_s1_pos = pbi->s1_pos + 1;
1998
1999 if (next_s1_pos >= pbi->used_stage_buf_num)
2000 next_s1_pos = 0;
2001 if (next_s1_pos == pbi->s2_pos) {
2002 pbi->s1_buf = NULL;
2003 return ret;
2004 }
2005
2006 buf = pbi->stage_bufs[pbi->s1_pos];
2007 ret = decoder_mmu_box_alloc_idx(
2008 pbi->mmu_box,
2009 buf->index,
2010 buf_page_num,
2011 pbi->stage_mmu_map_addr);
2012 if (ret < 0) {
2013 vp9_print(pbi, 0,
2014 "%s decoder_mmu_box_alloc fail for index %d (s1_pos %d s2_pos %d)\n",
2015 __func__, buf->index,
2016 pbi->s1_pos, pbi->s2_pos);
2017 buf = NULL;
2018 } else {
2019 vp9_print(pbi, VP9_DEBUG_2_STAGE,
2020 "%s decoder_mmu_box_alloc %d page for index %d (s1_pos %d s2_pos %d)\n",
2021 __func__, buf_page_num, buf->index,
2022 pbi->s1_pos, pbi->s2_pos);
2023 }
2024 pbi->s1_buf = buf;
2025 return ret;
2026}
2027
2028static void inc_s1_pos(struct VP9Decoder_s *pbi)
2029{
2030 struct stage_buf_s *buf =
2031 pbi->stage_bufs[pbi->s1_pos];
2032
2033 int used_page_num =
2034#ifdef FB_DECODING_TEST_SCHEDULE
2035 MAX_STAGE_PAGE_NUM/2;
2036#else
2037 (READ_VREG(HEVC_ASSIST_HED_FB_W_CTL) >> 16);
2038#endif
2039 decoder_mmu_box_free_idx_tail(pbi->mmu_box,
2040 FRAME_BUFFERS + buf->index, used_page_num);
2041
2042 pbi->s1_pos++;
2043 if (pbi->s1_pos >= pbi->used_stage_buf_num)
2044 pbi->s1_pos = 0;
2045
2046 vp9_print(pbi, VP9_DEBUG_2_STAGE,
2047 "%s (used_page_num %d) for index %d (s1_pos %d s2_pos %d)\n",
2048 __func__, used_page_num, buf->index,
2049 pbi->s1_pos, pbi->s2_pos);
2050}
2051
2052#define s2_buf_available(pbi) (pbi->s1_pos != pbi->s2_pos)
2053
2054static int get_s2_buf(
2055 struct VP9Decoder_s *pbi)
2056{
2057 int ret = -1;
2058 struct stage_buf_s *buf = NULL;
2059 if (s2_buf_available(pbi)) {
2060 buf = pbi->stage_bufs[pbi->s2_pos];
2061 vp9_print(pbi, VP9_DEBUG_2_STAGE,
2062 "%s for index %d (s1_pos %d s2_pos %d)\n",
2063 __func__, buf->index,
2064 pbi->s1_pos, pbi->s2_pos);
2065 pbi->s2_buf = buf;
2066 ret = 0;
2067 }
2068 return ret;
2069}
2070
2071static void inc_s2_pos(struct VP9Decoder_s *pbi)
2072{
2073 struct stage_buf_s *buf =
2074 pbi->stage_bufs[pbi->s2_pos];
2075 decoder_mmu_box_free_idx(pbi->mmu_box,
2076 FRAME_BUFFERS + buf->index);
2077 pbi->s2_pos++;
2078 if (pbi->s2_pos >= pbi->used_stage_buf_num)
2079 pbi->s2_pos = 0;
2080 vp9_print(pbi, VP9_DEBUG_2_STAGE,
2081 "%s for index %d (s1_pos %d s2_pos %d)\n",
2082 __func__, buf->index,
2083 pbi->s1_pos, pbi->s2_pos);
2084}
2085
2086static int get_free_stage_buf_num(struct VP9Decoder_s *pbi)
2087{
2088 int num;
2089 if (pbi->s1_pos >= pbi->s2_pos)
2090 num = pbi->used_stage_buf_num -
2091 (pbi->s1_pos - pbi->s2_pos) - 1;
2092 else
2093 num = (pbi->s2_pos - pbi->s1_pos) - 1;
2094 return num;
2095}
2096
2097#ifndef FB_DECODING_TEST_SCHEDULE
2098static DEFINE_SPINLOCK(fb_core_spin_lock);
2099
2100static u8 is_s2_decoding_finished(struct VP9Decoder_s *pbi)
2101{
2102 /* to do: VLSI review
2103 completion of last LCU decoding in BACK
2104 */
2105 return 1;
2106}
2107
2108static void start_s1_decoding(struct VP9Decoder_s *pbi)
2109{
2110 /* to do: VLSI review
2111 after parser, how to start LCU decoding in BACK
2112 */
2113}
2114
2115static void fb_reset_core(struct vdec_s *vdec, u32 mask)
2116{
2117 /* to do: VLSI review
2118 1. how to disconnect DMC for FRONT and BACK
2119 2. reset bit 13, 24, FRONT or BACK ??
2120 */
2121
2122 unsigned long flags;
2123 u32 reset_bits = 0;
2124 if (mask & HW_MASK_FRONT)
2125 WRITE_VREG(HEVC_STREAM_CONTROL, 0);
2126 spin_lock_irqsave(&fb_core_spin_lock, flags);
2127 codec_dmcbus_write(DMC_REQ_CTRL,
2128 codec_dmcbus_read(DMC_REQ_CTRL) & (~(1 << 4)));
2129 spin_unlock_irqrestore(&fb_core_spin_lock, flags);
2130
2131 while (!(codec_dmcbus_read(DMC_CHAN_STS)
2132 & (1 << 4)))
2133 ;
2134
2135 if ((mask & HW_MASK_FRONT) &&
2136 input_frame_based(vdec))
2137 WRITE_VREG(HEVC_STREAM_CONTROL, 0);
2138
2139 /*
2140 * 2: assist
2141 * 3: parser
2142 * 4: parser_state
2143 * 8: dblk
2144 * 11:mcpu
2145 * 12:ccpu
2146 * 13:ddr
2147 * 14:iqit
2148 * 15:ipp
2149 * 17:qdct
2150 * 18:mpred
2151 * 19:sao
2152 * 24:hevc_afifo
2153 */
2154 if (mask & HW_MASK_FRONT) {
2155 reset_bits =
2156 (1<<3)|(1<<4)|(1<<11)|
2157 (1<<12)|(1<<18);
2158 }
2159 if (mask & HW_MASK_BACK) {
2160 reset_bits =
2161 (1<<8)|(1<<13)|(1<<14)|(1<<15)|
2162 (1<<17)|(1<<19)|(1<<24);
2163 }
2164 WRITE_VREG(DOS_SW_RESET3, reset_bits);
2165#if 0
2166 (1<<3)|(1<<4)|(1<<8)|(1<<11)|
2167 (1<<12)|(1<<13)|(1<<14)|(1<<15)|
2168 (1<<17)|(1<<18)|(1<<19)|(1<<24);
2169#endif
2170 WRITE_VREG(DOS_SW_RESET3, 0);
2171
2172
2173 spin_lock_irqsave(&fb_core_spin_lock, flags);
2174 codec_dmcbus_write(DMC_REQ_CTRL,
2175 codec_dmcbus_read(DMC_REQ_CTRL) | (1 << 4));
2176 spin_unlock_irqrestore(&fb_core_spin_lock, flags);
2177
2178}
2179#endif
2180
2181#endif
2182
2183static void init_pic_list_hw(struct VP9Decoder_s *pbi);
2184
2185static int get_free_fb(struct VP9Decoder_s *pbi)
2186{
2187 struct VP9_Common_s *const cm = &pbi->common;
2188 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
2189 int i;
2190 unsigned long flags;
2191
2192 lock_buffer_pool(cm->buffer_pool, flags);
2193 if (debug & VP9_DEBUG_BUFMGR_MORE) {
2194 for (i = 0; i < pbi->used_buf_num; ++i) {
2195 pr_info("%s:%d, ref_count %d vf_ref %d index %d\r\n",
2196 __func__, i, frame_bufs[i].ref_count,
2197 frame_bufs[i].buf.vf_ref,
2198 frame_bufs[i].buf.index);
2199 }
2200 }
2201 for (i = 0; i < pbi->used_buf_num; ++i) {
2202 if ((frame_bufs[i].ref_count == 0) &&
2203 (frame_bufs[i].buf.vf_ref == 0) &&
2204 (frame_bufs[i].buf.index != -1)
2205 )
2206 break;
2207 }
2208 if (i != pbi->used_buf_num) {
2209 frame_bufs[i].ref_count = 1;
2210 /*pr_info("[MMU DEBUG 1] set ref_count[%d] : %d\r\n",
2211 i, frame_bufs[i].ref_count);*/
2212 } else {
2213 /* Reset i to be INVALID_IDX to indicate
2214 no free buffer found*/
2215 i = INVALID_IDX;
2216 }
2217
2218 unlock_buffer_pool(cm->buffer_pool, flags);
2219 return i;
2220}
2221
2222static int v4l_get_free_fb(struct VP9Decoder_s *pbi)
2223{
2224 struct VP9_Common_s *const cm = &pbi->common;
2225 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
2226 struct aml_vcodec_ctx * v4l = pbi->v4l2_ctx;
2227 struct v4l_buff_pool *pool = &v4l->cap_pool;
2228 struct PIC_BUFFER_CONFIG_s *pic = NULL;
2229 int i, idx = INVALID_IDX;
2230 ulong flags;
2231
2232 lock_buffer_pool(cm->buffer_pool, flags);
2233
2234 for (i = 0; i < pool->in; ++i) {
2235 u32 state = (pool->seq[i] >> 16);
2236 u32 index = (pool->seq[i] & 0xffff);
2237
2238 switch (state) {
2239 case V4L_CAP_BUFF_IN_DEC:
2240 pic = &frame_bufs[i].buf;
2241 if ((frame_bufs[i].ref_count == 0) &&
2242 (pic->vf_ref == 0) &&
2243 (pic->index != -1) &&
2244 pic->cma_alloc_addr) {
2245 idx = i;
2246 }
2247 break;
2248 case V4L_CAP_BUFF_IN_M2M:
2249 pic = &frame_bufs[index].buf;
2250 pic->y_crop_width = pbi->frame_width;
2251 pic->y_crop_height = pbi->frame_height;
2252 if (!v4l_alloc_and_config_pic(pbi, pic)) {
2253 set_canvas(pbi, pic);
2254 init_pic_list_hw(pbi);
2255 idx = index;
2256 }
2257 break;
2258 default:
2259 pr_err("v4l buffer state err %d.\n", state);
2260 break;
2261 }
2262
2263 if (idx != INVALID_IDX) {
2264 frame_bufs[idx].ref_count = 1;
2265 break;
2266 }
2267 }
2268
2269 unlock_buffer_pool(cm->buffer_pool, flags);
2270
2271 return idx;
2272}
2273
2274static int get_free_buf_count(struct VP9Decoder_s *pbi)
2275{
2276 struct VP9_Common_s *const cm = &pbi->common;
2277 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
2278 int i;
2279 int free_buf_count = 0;
2280 for (i = 0; i < pbi->used_buf_num; ++i)
2281 if ((frame_bufs[i].ref_count == 0) &&
2282 (frame_bufs[i].buf.vf_ref == 0) &&
2283 (frame_bufs[i].buf.index != -1)
2284 )
2285 free_buf_count++;
2286 return free_buf_count;
2287}
2288
2289static void decrease_ref_count(int idx, struct RefCntBuffer_s *const frame_bufs,
2290 struct BufferPool_s *const pool)
2291{
2292 if (idx >= 0) {
2293 --frame_bufs[idx].ref_count;
2294 /*pr_info("[MMU DEBUG 7] dec ref_count[%d] : %d\r\n", idx,
2295 * frame_bufs[idx].ref_count);
2296 */
2297 /*A worker may only get a free framebuffer index when
2298 *calling get_free_fb. But the private buffer is not set up
2299 *until finish decoding header. So any error happens during
2300 *decoding header, the frame_bufs will not have valid priv
2301 *buffer.
2302 */
2303
2304 if (frame_bufs[idx].ref_count == 0 &&
2305 frame_bufs[idx].raw_frame_buffer.priv)
2306 vp9_release_frame_buffer
2307 (&frame_bufs[idx].raw_frame_buffer);
2308 }
2309}
2310
2311static void generate_next_ref_frames(struct VP9Decoder_s *pbi)
2312{
2313 struct VP9_Common_s *const cm = &pbi->common;
2314 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
2315 struct BufferPool_s *const pool = cm->buffer_pool;
2316 int mask, ref_index = 0;
2317 unsigned long flags;
2318
2319 /* Generate next_ref_frame_map.*/
2320 lock_buffer_pool(pool, flags);
2321 for (mask = pbi->refresh_frame_flags; mask; mask >>= 1) {
2322 if (mask & 1) {
2323 cm->next_ref_frame_map[ref_index] = cm->new_fb_idx;
2324 ++frame_bufs[cm->new_fb_idx].ref_count;
2325 /*pr_info("[MMU DEBUG 4] inc ref_count[%d] : %d\r\n",
2326 *cm->new_fb_idx, frame_bufs[cm->new_fb_idx].ref_count);
2327 */
2328 } else
2329 cm->next_ref_frame_map[ref_index] =
2330 cm->ref_frame_map[ref_index];
2331 /* Current thread holds the reference frame.*/
2332 if (cm->ref_frame_map[ref_index] >= 0) {
2333 ++frame_bufs[cm->ref_frame_map[ref_index]].ref_count;
2334 /*pr_info
2335 *("[MMU DEBUG 5] inc ref_count[%d] : %d\r\n",
2336 *cm->ref_frame_map[ref_index],
2337 *frame_bufs[cm->ref_frame_map[ref_index]].ref_count);
2338 */
2339 }
2340 ++ref_index;
2341 }
2342
2343 for (; ref_index < REF_FRAMES; ++ref_index) {
2344 cm->next_ref_frame_map[ref_index] =
2345 cm->ref_frame_map[ref_index];
2346 /* Current thread holds the reference frame.*/
2347 if (cm->ref_frame_map[ref_index] >= 0) {
2348 ++frame_bufs[cm->ref_frame_map[ref_index]].ref_count;
2349 /*pr_info("[MMU DEBUG 6] inc ref_count[%d] : %d\r\n",
2350 *cm->ref_frame_map[ref_index],
2351 *frame_bufs[cm->ref_frame_map[ref_index]].ref_count);
2352 */
2353 }
2354 }
2355 unlock_buffer_pool(pool, flags);
2356 return;
2357}
2358
2359static void refresh_ref_frames(struct VP9Decoder_s *pbi)
2360
2361{
2362 struct VP9_Common_s *const cm = &pbi->common;
2363 struct BufferPool_s *pool = cm->buffer_pool;
2364 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
2365 int mask, ref_index = 0;
2366 unsigned long flags;
2367
2368 lock_buffer_pool(pool, flags);
2369 for (mask = pbi->refresh_frame_flags; mask; mask >>= 1) {
2370 const int old_idx = cm->ref_frame_map[ref_index];
2371 /*Current thread releases the holding of reference frame.*/
2372 decrease_ref_count(old_idx, frame_bufs, pool);
2373
2374 /*Release the reference frame in reference map.*/
2375 if ((mask & 1) && old_idx >= 0)
2376 decrease_ref_count(old_idx, frame_bufs, pool);
2377 cm->ref_frame_map[ref_index] =
2378 cm->next_ref_frame_map[ref_index];
2379 ++ref_index;
2380 }
2381
2382 /*Current thread releases the holding of reference frame.*/
2383 for (; ref_index < REF_FRAMES && !cm->show_existing_frame;
2384 ++ref_index) {
2385 const int old_idx = cm->ref_frame_map[ref_index];
2386
2387 decrease_ref_count(old_idx, frame_bufs, pool);
2388 cm->ref_frame_map[ref_index] =
2389 cm->next_ref_frame_map[ref_index];
2390 }
2391 unlock_buffer_pool(pool, flags);
2392 return;
2393}
2394
2395int vp9_bufmgr_process(struct VP9Decoder_s *pbi, union param_u *params)
2396{
2397 struct VP9_Common_s *const cm = &pbi->common;
2398 struct BufferPool_s *pool = cm->buffer_pool;
2399 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
2400 struct PIC_BUFFER_CONFIG_s *pic = NULL;
2401 int i;
2402 int ret;
2403
2404 pbi->ready_for_new_data = 0;
2405
2406 if (pbi->has_keyframe == 0 &&
2407 params->p.frame_type != KEY_FRAME){
2408 on_no_keyframe_skiped++;
2409 return -2;
2410 }
2411 pbi->has_keyframe = 1;
2412 on_no_keyframe_skiped = 0;
2413#if 0
2414 if (pbi->mmu_enable) {
2415 if (!pbi->m_ins_flag)
2416 pbi->used_4k_num = (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
2417 if (cm->prev_fb_idx >= 0) {
2418 decoder_mmu_box_free_idx_tail(pbi->mmu_box,
2419 cm->prev_fb_idx, pbi->used_4k_num);
2420 }
2421 }
2422#endif
2423 if (cm->new_fb_idx >= 0
2424 && frame_bufs[cm->new_fb_idx].ref_count == 0){
2425 vp9_release_frame_buffer
2426 (&frame_bufs[cm->new_fb_idx].raw_frame_buffer);
2427 }
2428 /*pr_info("Before get_free_fb, prev_fb_idx : %d, new_fb_idx : %d\r\n",
2429 cm->prev_fb_idx, cm->new_fb_idx);*/
2430#ifndef MV_USE_FIXED_BUF
2431 put_un_used_mv_bufs(pbi);
2432 if (debug & VP9_DEBUG_BUFMGR_DETAIL)
2433 dump_pic_list(pbi);
2434#endif
2435 cm->new_fb_idx = pbi->is_used_v4l ?
2436 v4l_get_free_fb(pbi) :
2437 get_free_fb(pbi);
2438 if (cm->new_fb_idx == INVALID_IDX) {
2439 pr_info("get_free_fb error\r\n");
2440 return -1;
2441 }
2442#ifndef MV_USE_FIXED_BUF
2443#ifdef SUPPORT_FB_DECODING
2444 if (pbi->used_stage_buf_num == 0) {
2445#endif
2446 if (get_mv_buf(pbi,
2447 &pool->frame_bufs[cm->new_fb_idx].
2448 buf.mv_buf_index,
2449 &pool->frame_bufs[cm->new_fb_idx].
2450 buf.mpred_mv_wr_start_addr
2451 ) < 0) {
2452 pr_info("get_mv_buf fail\r\n");
2453 return -1;
2454 }
2455 if (debug & VP9_DEBUG_BUFMGR_DETAIL)
2456 dump_pic_list(pbi);
2457#ifdef SUPPORT_FB_DECODING
2458 }
2459#endif
2460#endif
2461 cm->cur_frame = &pool->frame_bufs[cm->new_fb_idx];
2462 /*if (debug & VP9_DEBUG_BUFMGR)
2463 pr_info("[VP9 DEBUG]%s(get_free_fb): %d\r\n", __func__,
2464 cm->new_fb_idx);*/
2465
2466 pbi->cur_buf = &frame_bufs[cm->new_fb_idx];
2467 if (pbi->mmu_enable) {
2468 /* moved to after picture size ready
2469 *alloc_mmu(cm, params->p.width, params->p.height,
2470 *params->p.bit_depth, pbi->frame_mmu_map_addr);
2471 */
2472 cm->prev_fb_idx = cm->new_fb_idx;
2473 }
2474 /*read_uncompressed_header()*/
2475 cm->last_frame_type = cm->frame_type;
2476 cm->last_intra_only = cm->intra_only;
2477 cm->profile = params->p.profile;
2478 if (cm->profile >= MAX_PROFILES) {
2479 pr_err("Error: Unsupported profile %d\r\n", cm->profile);
2480 return -1;
2481 }
2482 cm->show_existing_frame = params->p.show_existing_frame;
2483 if (cm->show_existing_frame) {
2484 /* Show an existing frame directly.*/
2485 int frame_to_show_idx = params->p.frame_to_show_idx;
2486 int frame_to_show;
2487 unsigned long flags;
2488 if (frame_to_show_idx >= REF_FRAMES) {
2489 pr_info("frame_to_show_idx %d exceed max index\r\n",
2490 frame_to_show_idx);
2491 return -1;
2492 }
2493
2494 frame_to_show = cm->ref_frame_map[frame_to_show_idx];
2495 /*pr_info("frame_to_show %d\r\n", frame_to_show);*/
2496 lock_buffer_pool(pool, flags);
2497 if (frame_to_show < 0 ||
2498 frame_bufs[frame_to_show].ref_count < 1) {
2499 unlock_buffer_pool(pool, flags);
2500 pr_err
2501 ("Error:Buffer %d does not contain a decoded frame",
2502 frame_to_show);
2503 return -1;
2504 }
2505
2506 ref_cnt_fb(frame_bufs, &cm->new_fb_idx, frame_to_show);
2507 unlock_buffer_pool(pool, flags);
2508 pbi->refresh_frame_flags = 0;
2509 /*cm->lf.filter_level = 0;*/
2510 cm->show_frame = 1;
2511
2512 /*
2513 *if (pbi->frame_parallel_decode) {
2514 * for (i = 0; i < REF_FRAMES; ++i)
2515 * cm->next_ref_frame_map[i] =
2516 * cm->ref_frame_map[i];
2517 *}
2518 */
2519 /* do not decode, search next start code */
2520 return 1;
2521 }
2522 cm->frame_type = params->p.frame_type;
2523 cm->show_frame = params->p.show_frame;
2524 cm->error_resilient_mode = params->p.error_resilient_mode;
2525
2526
2527 if (cm->frame_type == KEY_FRAME) {
2528 pbi->refresh_frame_flags = (1 << REF_FRAMES) - 1;
2529
2530 for (i = 0; i < REFS_PER_FRAME; ++i) {
2531 cm->frame_refs[i].idx = INVALID_IDX;
2532 cm->frame_refs[i].buf = NULL;
2533 }
2534
2535 ret = setup_frame_size(pbi,
2536 cm, params, pbi->frame_mmu_map_addr,
2537 print_header_info);
2538 if (ret)
2539 return -1;
2540 if (pbi->need_resync) {
2541 memset(&cm->ref_frame_map, -1,
2542 sizeof(cm->ref_frame_map));
2543 pbi->need_resync = 0;
2544 }
2545 } else {
2546 cm->intra_only = cm->show_frame ? 0 : params->p.intra_only;
2547 /*if (print_header_info) {
2548 * if (cm->show_frame)
2549 * pr_info
2550 * ("intra_only set to 0 because of show_frame\n");
2551 * else
2552 * pr_info
2553 * ("1-bit intra_only read: %d\n", cm->intra_only);
2554 *}
2555 */
2556
2557
2558 cm->reset_frame_context = cm->error_resilient_mode ?
2559 0 : params->p.reset_frame_context;
2560 if (print_header_info) {
2561 if (cm->error_resilient_mode)
2562 pr_info
2563 ("reset to 0 error_resilient_mode\n");
2564 else
2565 pr_info
2566 (" * 2-bits reset_frame_context read : %d\n",
2567 cm->reset_frame_context);
2568 }
2569
2570 if (cm->intra_only) {
2571 if (cm->profile > PROFILE_0) {
2572 /*read_bitdepth_colorspace_sampling(cm,
2573 * rb, print_header_info);
2574 */
2575 } else {
2576 /*NOTE: The intra-only frame header
2577 *does not include the specification
2578 *of either the color format or
2579 *color sub-sampling
2580 *in profile 0. VP9 specifies that the default
2581 *color format should be YUV 4:2:0 in this
2582 *case (normative).
2583 */
2584 cm->color_space = VPX_CS_BT_601;
2585 cm->subsampling_y = cm->subsampling_x = 1;
2586 cm->bit_depth = VPX_BITS_8;
2587 cm->use_highbitdepth = 0;
2588 }
2589
2590 pbi->refresh_frame_flags =
2591 params->p.refresh_frame_flags;
2592 /*if (print_header_info)
2593 * pr_info("*%d-bits refresh_frame read:0x%x\n",
2594 * REF_FRAMES, pbi->refresh_frame_flags);
2595 */
2596 ret = setup_frame_size(pbi,
2597 cm,
2598 params,
2599 pbi->frame_mmu_map_addr,
2600 print_header_info);
2601 if (ret)
2602 return -1;
2603 if (pbi->need_resync) {
2604 memset(&cm->ref_frame_map, -1,
2605 sizeof(cm->ref_frame_map));
2606 pbi->need_resync = 0;
2607 }
2608 } else if (pbi->need_resync != 1) { /* Skip if need resync */
2609 pbi->refresh_frame_flags =
2610 params->p.refresh_frame_flags;
2611 if (print_header_info)
2612 pr_info
2613 ("*%d-bits refresh_frame read:0x%x\n",
2614 REF_FRAMES, pbi->refresh_frame_flags);
2615 for (i = 0; i < REFS_PER_FRAME; ++i) {
2616 const int ref =
2617 (params->p.ref_info >>
2618 (((REFS_PER_FRAME-i-1)*4)+1))
2619 & 0x7;
2620 const int idx =
2621 cm->ref_frame_map[ref];
2622 struct RefBuffer_s * const ref_frame =
2623 &cm->frame_refs[i];
2624 if (print_header_info)
2625 pr_info("*%d-bits ref[%d]read:%d\n",
2626 REF_FRAMES_LOG2, i, ref);
2627 ref_frame->idx = idx;
2628 ref_frame->buf = &frame_bufs[idx].buf;
2629 cm->ref_frame_sign_bias[LAST_FRAME + i]
2630 = (params->p.ref_info >>
2631 ((REFS_PER_FRAME-i-1)*4)) & 0x1;
2632 if (print_header_info)
2633 pr_info("1bit ref_frame_sign_bias");
2634 /*pr_info
2635 *("%dread: %d\n",
2636 *LAST_FRAME+i,
2637 *cm->ref_frame_sign_bias
2638 *[LAST_FRAME + i]);
2639 */
2640 /*pr_info
2641 *("[VP9 DEBUG]%s(get ref):%d\r\n",
2642 *__func__, ref_frame->idx);
2643 */
2644
2645 }
2646
2647 ret = setup_frame_size_with_refs(
2648 pbi,
2649 cm,
2650 params,
2651 pbi->frame_mmu_map_addr,
2652 print_header_info);
2653 if (ret)
2654 return -1;
2655 for (i = 0; i < REFS_PER_FRAME; ++i) {
2656 /*struct RefBuffer_s *const ref_buf =
2657 *&cm->frame_refs[i];
2658 */
2659 /* to do:
2660 *vp9_setup_scale_factors_for_frame
2661 */
2662 }
2663 }
2664 }
2665
2666 pic = get_frame_new_buffer(cm);
2667 if (!pic)
2668 return -1;
2669
2670 pic->bit_depth = cm->bit_depth;
2671 pic->color_space = cm->color_space;
2672 pic->slice_type = cm->frame_type;
2673
2674 if (pbi->need_resync) {
2675 pr_err
2676 ("Error: Keyframe/intra-only frame required to reset\r\n");
2677 return -1;
2678 }
2679 generate_next_ref_frames(pbi);
2680 pbi->hold_ref_buf = 1;
2681
2682#if 0
2683 if (frame_is_intra_only(cm) || cm->error_resilient_mode)
2684 vp9_setup_past_independence(cm);
2685 setup_loopfilter(&cm->lf, rb, print_header_info);
2686 setup_quantization(cm, &pbi->mb, rb, print_header_info);
2687 setup_segmentation(&cm->seg, rb, print_header_info);
2688 setup_segmentation_dequant(cm, print_header_info);
2689
2690 setup_tile_info(cm, rb, print_header_info);
2691 sz = vp9_rb_read_literal(rb, 16);
2692 if (print_header_info)
2693 pr_info(" * 16-bits size read : %d (0x%x)\n", sz, sz);
2694
2695 if (sz == 0)
2696 vpx_internal_error(&cm->error, VPX_CODEC_CORRUPT_FRAME,
2697 "Invalid header size");
2698#endif
2699 /*end read_uncompressed_header()*/
2700 cm->use_prev_frame_mvs = !cm->error_resilient_mode &&
2701 cm->width == cm->last_width &&
2702 cm->height == cm->last_height &&
2703 !cm->last_intra_only &&
2704 cm->last_show_frame &&
2705 (cm->last_frame_type != KEY_FRAME);
2706
2707 /*pr_info
2708 *("set use_prev_frame_mvs to %d (last_width %d last_height %d",
2709 *cm->use_prev_frame_mvs, cm->last_width, cm->last_height);
2710 *pr_info
2711 *(" last_intra_only %d last_show_frame %d last_frame_type %d)\n",
2712 *cm->last_intra_only, cm->last_show_frame, cm->last_frame_type);
2713 */
2714 return 0;
2715}
2716
2717
2718void swap_frame_buffers(struct VP9Decoder_s *pbi)
2719{
2720 int ref_index = 0;
2721 struct VP9_Common_s *const cm = &pbi->common;
2722 struct BufferPool_s *const pool = cm->buffer_pool;
2723 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
2724 unsigned long flags;
2725 refresh_ref_frames(pbi);
2726 pbi->hold_ref_buf = 0;
2727 cm->frame_to_show = get_frame_new_buffer(cm);
2728
2729 if (cm->frame_to_show) {
2730 /*if (!pbi->frame_parallel_decode || !cm->show_frame) {*/
2731 lock_buffer_pool(pool, flags);
2732 --frame_bufs[cm->new_fb_idx].ref_count;
2733 /*pr_info("[MMU DEBUG 8] dec ref_count[%d] : %d\r\n", cm->new_fb_idx,
2734 * frame_bufs[cm->new_fb_idx].ref_count);
2735 */
2736 unlock_buffer_pool(pool, flags);
2737 /*}*/
2738 }
2739
2740 /*Invalidate these references until the next frame starts.*/
2741 for (ref_index = 0; ref_index < 3; ref_index++)
2742 cm->frame_refs[ref_index].idx = -1;
2743}
2744
2745#if 0
2746static void check_resync(vpx_codec_alg_priv_t *const ctx,
2747 const struct VP9Decoder_s *const pbi)
2748{
2749 /* Clear resync flag if worker got a key frame or intra only frame.*/
2750 if (ctx->need_resync == 1 && pbi->need_resync == 0 &&
2751 (pbi->common.intra_only || pbi->common.frame_type == KEY_FRAME))
2752 ctx->need_resync = 0;
2753}
2754#endif
2755
2756int vp9_get_raw_frame(struct VP9Decoder_s *pbi, struct PIC_BUFFER_CONFIG_s *sd)
2757{
2758 struct VP9_Common_s *const cm = &pbi->common;
2759 int ret = -1;
2760
2761 if (pbi->ready_for_new_data == 1)
2762 return ret;
2763
2764 pbi->ready_for_new_data = 1;
2765
2766 /* no raw frame to show!!! */
2767 if (!cm->show_frame)
2768 return ret;
2769
2770 /* may not be get buff in v4l2 */
2771 if (!cm->frame_to_show)
2772 return ret;
2773
2774 pbi->ready_for_new_data = 1;
2775
2776 *sd = *cm->frame_to_show;
2777 ret = 0;
2778
2779 return ret;
2780}
2781
2782int vp9_bufmgr_init(struct VP9Decoder_s *pbi, struct BuffInfo_s *buf_spec_i,
2783 struct buff_s *mc_buf_i) {
2784 struct VP9_Common_s *cm = &pbi->common;
2785
2786 /*memset(pbi, 0, sizeof(struct VP9Decoder_s));*/
2787 pbi->frame_count = 0;
2788 pbi->pic_count = 0;
2789 pbi->pre_stream_offset = 0;
2790 cm->buffer_pool = &pbi->vp9_buffer_pool;
2791 spin_lock_init(&cm->buffer_pool->lock);
2792 cm->prev_fb_idx = INVALID_IDX;
2793 cm->new_fb_idx = INVALID_IDX;
2794 pbi->used_4k_num = -1;
2795 cm->cur_fb_idx_mmu = INVALID_IDX;
2796 pr_debug
2797 ("After vp9_bufmgr_init, prev_fb_idx : %d, new_fb_idx : %d\r\n",
2798 cm->prev_fb_idx, cm->new_fb_idx);
2799 pbi->need_resync = 1;
2800 /* Initialize the references to not point to any frame buffers.*/
2801 memset(&cm->ref_frame_map, -1, sizeof(cm->ref_frame_map));
2802 memset(&cm->next_ref_frame_map, -1, sizeof(cm->next_ref_frame_map));
2803 cm->current_video_frame = 0;
2804 pbi->ready_for_new_data = 1;
2805
2806 /* private init */
2807 pbi->work_space_buf = buf_spec_i;
2808 if (!pbi->mmu_enable)
2809 pbi->mc_buf = mc_buf_i;
2810
2811 pbi->rpm_addr = NULL;
2812 pbi->lmem_addr = NULL;
2813
2814 pbi->use_cma_flag = 0;
2815 pbi->decode_idx = 0;
2816 pbi->slice_idx = 0;
2817 /*int m_uiMaxCUWidth = 1<<7;*/
2818 /*int m_uiMaxCUHeight = 1<<7;*/
2819 pbi->has_keyframe = 0;
2820 pbi->skip_flag = 0;
2821 pbi->wait_buf = 0;
2822 pbi->error_flag = 0;
2823
2824 pbi->pts_mode = PTS_NORMAL;
2825 pbi->last_pts = 0;
2826 pbi->last_lookup_pts = 0;
2827 pbi->last_pts_us64 = 0;
2828 pbi->last_lookup_pts_us64 = 0;
2829 pbi->shift_byte_count = 0;
2830 pbi->shift_byte_count_lo = 0;
2831 pbi->shift_byte_count_hi = 0;
2832 pbi->pts_mode_switching_count = 0;
2833 pbi->pts_mode_recovery_count = 0;
2834
2835 pbi->buf_num = 0;
2836 pbi->pic_num = 0;
2837
2838 return 0;
2839}
2840
2841int vp9_bufmgr_postproc(struct VP9Decoder_s *pbi)
2842{
2843 struct VP9_Common_s *cm = &pbi->common;
2844 struct PIC_BUFFER_CONFIG_s sd;
2845
2846 if (pbi->postproc_done)
2847 return 0;
2848 pbi->postproc_done = 1;
2849 swap_frame_buffers(pbi);
2850 if (!cm->show_existing_frame) {
2851 cm->last_show_frame = cm->show_frame;
2852 cm->prev_frame = cm->cur_frame;
2853#if 0
2854 if (cm->seg.enabled && !pbi->frame_parallel_decode)
2855 vp9_swap_current_and_last_seg_map(cm);
2856#endif
2857 }
2858 cm->last_width = cm->width;
2859 cm->last_height = cm->height;
2860 if (cm->show_frame)
2861 cm->current_video_frame++;
2862
2863 if (vp9_get_raw_frame(pbi, &sd) == 0) {
2864 /*pr_info("Display frame index %d\r\n", sd.index);*/
2865 sd.stream_offset = pbi->pre_stream_offset;
2866 prepare_display_buf(pbi, &sd);
2867 pbi->pre_stream_offset = READ_VREG(HEVC_SHIFT_BYTE_COUNT);
2868 }
2869
2870/* else
2871 * pr_info
2872 * ("Not display this frame,ready_for_new_data%d show_frame%d\r\n",
2873 * pbi->ready_for_new_data, cm->show_frame);
2874 */
2875 return 0;
2876}
2877
2878/**************************************************
2879 *
2880 *VP9 buffer management end
2881 *
2882 ***************************************************
2883 */
2884
2885
2886#define HEVC_CM_BODY_START_ADDR 0x3626
2887#define HEVC_CM_BODY_LENGTH 0x3627
2888#define HEVC_CM_HEADER_LENGTH 0x3629
2889#define HEVC_CM_HEADER_OFFSET 0x362b
2890
2891#define LOSLESS_COMPRESS_MODE
2892
2893/*#define DECOMP_HEADR_SURGENT*/
2894#ifdef VP9_10B_NV21
2895static u32 mem_map_mode = 2 /* 0:linear 1:32x32 2:64x32*/
2896#else
2897static u32 mem_map_mode; /* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */
2898#endif
2899static u32 enable_mem_saving = 1;
2900static u32 force_w_h;
2901
2902static u32 force_fps;
2903
2904
2905const u32 vp9_version = 201602101;
2906static u32 debug;
2907static u32 radr;
2908static u32 rval;
2909static u32 pop_shorts;
2910static u32 dbg_cmd;
2911static u32 dbg_skip_decode_index;
2912static u32 endian = 0xff0;
2913#ifdef ERROR_HANDLE_DEBUG
2914static u32 dbg_nal_skip_flag;
2915 /* bit[0], skip vps; bit[1], skip sps; bit[2], skip pps */
2916static u32 dbg_nal_skip_count;
2917#endif
2918/*for debug*/
2919static u32 decode_pic_begin;
2920static uint slice_parse_begin;
2921static u32 step;
2922#ifdef MIX_STREAM_SUPPORT
2923static u32 buf_alloc_width = 4096;
2924static u32 buf_alloc_height = 2304;
2925static u32 vp9_max_pic_w = 4096;
2926static u32 vp9_max_pic_h = 2304;
2927
2928static u32 dynamic_buf_num_margin;
2929#else
2930static u32 buf_alloc_width;
2931static u32 buf_alloc_height;
2932static u32 dynamic_buf_num_margin = 7;
2933#endif
2934static u32 buf_alloc_depth = 10;
2935static u32 buf_alloc_size;
2936/*
2937 *bit[0]: 0,
2938 * bit[1]: 0, always release cma buffer when stop
2939 * bit[1]: 1, never release cma buffer when stop
2940 *bit[0]: 1, when stop, release cma buffer if blackout is 1;
2941 *do not release cma buffer is blackout is not 1
2942 *
2943 *bit[2]: 0, when start decoding, check current displayed buffer
2944 * (only for buffer decoded by vp9) if blackout is 0
2945 * 1, do not check current displayed buffer
2946 *
2947 *bit[3]: 1, if blackout is not 1, do not release current
2948 * displayed cma buffer always.
2949 */
2950/* set to 1 for fast play;
2951 * set to 8 for other case of "keep last frame"
2952 */
2953static u32 buffer_mode = 1;
2954/* buffer_mode_dbg: debug only*/
2955static u32 buffer_mode_dbg = 0xffff0000;
2956/**/
2957
2958/*
2959 *bit 0, 1: only display I picture;
2960 *bit 1, 1: only decode I picture;
2961 */
2962static u32 i_only_flag;
2963
2964static u32 low_latency_flag;
2965
2966static u32 no_head;
2967
2968static u32 max_decoding_time;
2969/*
2970 *error handling
2971 */
2972/*error_handle_policy:
2973 *bit 0: 0, auto skip error_skip_nal_count nals before error recovery;
2974 *1, skip error_skip_nal_count nals before error recovery;
2975 *bit 1 (valid only when bit0 == 1):
2976 *1, wait vps/sps/pps after error recovery;
2977 *bit 2 (valid only when bit0 == 0):
2978 *0, auto search after error recovery (vp9_recover() called);
2979 *1, manual search after error recovery
2980 *(change to auto search after get IDR: WRITE_VREG(NAL_SEARCH_CTL, 0x2))
2981 *
2982 *bit 4: 0, set error_mark after reset/recover
2983 * 1, do not set error_mark after reset/recover
2984 *bit 5: 0, check total lcu for every picture
2985 * 1, do not check total lcu
2986 *
2987 */
2988
2989static u32 error_handle_policy;
2990/*static u32 parser_sei_enable = 1;*/
2991#define MAX_BUF_NUM_NORMAL 12
2992#define MAX_BUF_NUM_LESS 10
2993static u32 max_buf_num = MAX_BUF_NUM_NORMAL;
2994#define MAX_BUF_NUM_SAVE_BUF 8
2995
2996static u32 run_ready_min_buf_num = 2;
2997
2998
2999static DEFINE_MUTEX(vvp9_mutex);
3000#ifndef MULTI_INSTANCE_SUPPORT
3001static struct device *cma_dev;
3002#endif
3003
3004#define HEVC_DEC_STATUS_REG HEVC_ASSIST_SCRATCH_0
3005#define HEVC_RPM_BUFFER HEVC_ASSIST_SCRATCH_1
3006#define HEVC_SHORT_TERM_RPS HEVC_ASSIST_SCRATCH_2
3007#define VP9_ADAPT_PROB_REG HEVC_ASSIST_SCRATCH_3
3008#define VP9_MMU_MAP_BUFFER HEVC_ASSIST_SCRATCH_4
3009#define HEVC_PPS_BUFFER HEVC_ASSIST_SCRATCH_5
3010#define HEVC_SAO_UP HEVC_ASSIST_SCRATCH_6
3011#define HEVC_STREAM_SWAP_BUFFER HEVC_ASSIST_SCRATCH_7
3012#define HEVC_STREAM_SWAP_BUFFER2 HEVC_ASSIST_SCRATCH_8
3013#define VP9_PROB_SWAP_BUFFER HEVC_ASSIST_SCRATCH_9
3014#define VP9_COUNT_SWAP_BUFFER HEVC_ASSIST_SCRATCH_A
3015#define VP9_SEG_MAP_BUFFER HEVC_ASSIST_SCRATCH_B
3016#define HEVC_SCALELUT HEVC_ASSIST_SCRATCH_D
3017#define HEVC_WAIT_FLAG HEVC_ASSIST_SCRATCH_E
3018#define RPM_CMD_REG HEVC_ASSIST_SCRATCH_F
3019#define LMEM_DUMP_ADR HEVC_ASSIST_SCRATCH_F
3020#define HEVC_STREAM_SWAP_TEST HEVC_ASSIST_SCRATCH_L
3021#ifdef MULTI_INSTANCE_SUPPORT
3022#define HEVC_DECODE_COUNT HEVC_ASSIST_SCRATCH_M
3023#define HEVC_DECODE_SIZE HEVC_ASSIST_SCRATCH_N
3024#else
3025#define HEVC_DECODE_PIC_BEGIN_REG HEVC_ASSIST_SCRATCH_M
3026#define HEVC_DECODE_PIC_NUM_REG HEVC_ASSIST_SCRATCH_N
3027#endif
3028#define DEBUG_REG1 HEVC_ASSIST_SCRATCH_G
3029#define DEBUG_REG2 HEVC_ASSIST_SCRATCH_H
3030
3031
3032/*
3033 *ucode parser/search control
3034 *bit 0: 0, header auto parse; 1, header manual parse
3035 *bit 1: 0, auto skip for noneseamless stream; 1, no skip
3036 *bit [3:2]: valid when bit1==0;
3037 *0, auto skip nal before first vps/sps/pps/idr;
3038 *1, auto skip nal before first vps/sps/pps
3039 *2, auto skip nal before first vps/sps/pps,
3040 * and not decode until the first I slice (with slice address of 0)
3041 *
3042 *3, auto skip before first I slice (nal_type >=16 && nal_type<=21)
3043 *bit [15:4] nal skip count (valid when bit0 == 1 (manual mode) )
3044 *bit [16]: for NAL_UNIT_EOS when bit0 is 0:
3045 * 0, send SEARCH_DONE to arm ; 1, do not send SEARCH_DONE to arm
3046 *bit [17]: for NAL_SEI when bit0 is 0:
3047 * 0, do not parse SEI in ucode; 1, parse SEI in ucode
3048 *bit [31:20]: used by ucode for debug purpose
3049 */
3050#define NAL_SEARCH_CTL HEVC_ASSIST_SCRATCH_I
3051 /*[31:24] chip feature
3052 31: 0, use MBOX1; 1, use MBOX0
3053 */
3054#define DECODE_MODE HEVC_ASSIST_SCRATCH_J
3055#define DECODE_STOP_POS HEVC_ASSIST_SCRATCH_K
3056
3057#ifdef MULTI_INSTANCE_SUPPORT
3058#define RPM_BUF_SIZE (0x400 * 2)
3059#else
3060#define RPM_BUF_SIZE (0x80*2)
3061#endif
3062#define LMEM_BUF_SIZE (0x400 * 2)
3063
3064#define WORK_BUF_SPEC_NUM 3
3065static struct BuffInfo_s amvvp9_workbuff_spec[WORK_BUF_SPEC_NUM] = {
3066 {
3067 /* 8M bytes */
3068 .max_width = 1920,
3069 .max_height = 1088,
3070 .ipp = {
3071 /* IPP work space calculation :
3072 * 4096 * (Y+CbCr+Flags) = 12k, round to 16k
3073 */
3074 .buf_size = 0x4000,
3075 },
3076 .sao_abv = {
3077 .buf_size = 0x30000,
3078 },
3079 .sao_vb = {
3080 .buf_size = 0x30000,
3081 },
3082 .short_term_rps = {
3083 /* SHORT_TERM_RPS - Max 64 set, 16 entry every set,
3084 * total 64x16x2 = 2048 bytes (0x800)
3085 */
3086 .buf_size = 0x800,
3087 },
3088 .vps = {
3089 /* VPS STORE AREA - Max 16 VPS, each has 0x80 bytes,
3090 * total 0x0800 bytes
3091 */
3092 .buf_size = 0x800,
3093 },
3094 .sps = {
3095 /* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes,
3096 * total 0x0800 bytes
3097 */
3098 .buf_size = 0x800,
3099 },
3100 .pps = {
3101 /* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes,
3102 * total 0x2000 bytes
3103 */
3104 .buf_size = 0x2000,
3105 },
3106 .sao_up = {
3107 /* SAO UP STORE AREA - Max 640(10240/16) LCU,
3108 * each has 16 bytes total 0x2800 bytes
3109 */
3110 .buf_size = 0x2800,
3111 },
3112 .swap_buf = {
3113 /* 256cyclex64bit = 2K bytes 0x800
3114 * (only 144 cycles valid)
3115 */
3116 .buf_size = 0x800,
3117 },
3118 .swap_buf2 = {
3119 .buf_size = 0x800,
3120 },
3121 .scalelut = {
3122 /* support up to 32 SCALELUT 1024x32 =
3123 * 32Kbytes (0x8000)
3124 */
3125 .buf_size = 0x8000,
3126 },
3127 .dblk_para = {
3128 /* DBLK -> Max 256(4096/16) LCU,
3129 *each para 1024bytes(total:0x40000),
3130 *data 1024bytes(total:0x40000)
3131 */
3132 .buf_size = 0x80000,
3133 },
3134 .dblk_data = {
3135 .buf_size = 0x80000,
3136 },
3137 .seg_map = {
3138 /*4096x2304/64/64 *24 = 0xd800 Bytes*/
3139 .buf_size = 0xd800,
3140 },
3141 .mmu_vbh = {
3142 .buf_size = 0x5000, /*2*16*(more than 2304)/4, 4K*/
3143 },
3144#if 0
3145 .cm_header = {
3146 /*add one for keeper.*/
3147 .buf_size = MMU_COMPRESS_HEADER_SIZE *
3148 (FRAME_BUFFERS + 1),
3149 /* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) */
3150 },
3151#endif
3152 .mpred_above = {
3153 .buf_size = 0x10000, /* 2 * size of hevc*/
3154 },
3155#ifdef MV_USE_FIXED_BUF
3156 .mpred_mv = {/* 1080p, 0x40000 per buffer */
3157 .buf_size = 0x40000 * FRAME_BUFFERS,
3158 },
3159#endif
3160 .rpm = {
3161 .buf_size = RPM_BUF_SIZE,
3162 },
3163 .lmem = {
3164 .buf_size = 0x400 * 2,
3165 }
3166 },
3167 {
3168 .max_width = 4096,
3169 .max_height = 2304,
3170 .ipp = {
3171 /* IPP work space calculation :
3172 * 4096 * (Y+CbCr+Flags) = 12k, round to 16k
3173 */
3174 .buf_size = 0x4000,
3175 },
3176 .sao_abv = {
3177 .buf_size = 0x30000,
3178 },
3179 .sao_vb = {
3180 .buf_size = 0x30000,
3181 },
3182 .short_term_rps = {
3183 /* SHORT_TERM_RPS - Max 64 set, 16 entry every set,
3184 * total 64x16x2 = 2048 bytes (0x800)
3185 */
3186 .buf_size = 0x800,
3187 },
3188 .vps = {
3189 /* VPS STORE AREA - Max 16 VPS, each has 0x80 bytes,
3190 * total 0x0800 bytes
3191 */
3192 .buf_size = 0x800,
3193 },
3194 .sps = {
3195 /* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes,
3196 * total 0x0800 bytes
3197 */
3198 .buf_size = 0x800,
3199 },
3200 .pps = {
3201 /* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes,
3202 * total 0x2000 bytes
3203 */
3204 .buf_size = 0x2000,
3205 },
3206 .sao_up = {
3207 /* SAO UP STORE AREA - Max 640(10240/16) LCU,
3208 * each has 16 bytes total 0x2800 bytes
3209 */
3210 .buf_size = 0x2800,
3211 },
3212 .swap_buf = {
3213 /* 256cyclex64bit = 2K bytes 0x800
3214 * (only 144 cycles valid)
3215 */
3216 .buf_size = 0x800,
3217 },
3218 .swap_buf2 = {
3219 .buf_size = 0x800,
3220 },
3221 .scalelut = {
3222 /* support up to 32 SCALELUT 1024x32 = 32Kbytes
3223 * (0x8000)
3224 */
3225 .buf_size = 0x8000,
3226 },
3227 .dblk_para = {
3228 /* DBLK -> Max 256(4096/16) LCU,
3229 *each para 1024bytes(total:0x40000),
3230 *data 1024bytes(total:0x40000)
3231 */
3232 .buf_size = 0x80000,
3233 },
3234 .dblk_data = {
3235 .buf_size = 0x80000,
3236 },
3237 .seg_map = {
3238 /*4096x2304/64/64 *24 = 0xd800 Bytes*/
3239 .buf_size = 0xd800,
3240 },
3241 .mmu_vbh = {
3242 .buf_size = 0x5000,/*2*16*(more than 2304)/4, 4K*/
3243 },
3244#if 0
3245 .cm_header = {
3246 /*add one for keeper.*/
3247 .buf_size = MMU_COMPRESS_HEADER_SIZE *
3248 (FRAME_BUFFERS + 1),
3249 /* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) */
3250 },
3251#endif
3252 .mpred_above = {
3253 .buf_size = 0x10000, /* 2 * size of hevc*/
3254 },
3255#ifdef MV_USE_FIXED_BUF
3256 .mpred_mv = {
3257 /* .buf_size = 0x100000*16,
3258 * //4k2k , 0x100000 per buffer
3259 */
3260 /* 4096x2304 , 0x120000 per buffer */
3261 .buf_size = 0x120000 * FRAME_BUFFERS,
3262 },
3263#endif
3264 .rpm = {
3265 .buf_size = RPM_BUF_SIZE,
3266 },
3267 .lmem = {
3268 .buf_size = 0x400 * 2,
3269 }
3270 },
3271 {
3272 .max_width = 4096*2,
3273 .max_height = 2304*2,
3274 .ipp = {
3275 // IPP work space calculation : 4096 * (Y+CbCr+Flags) = 12k, round to 16k
3276 .buf_size = 0x4000*2,
3277 },
3278 .sao_abv = {
3279 .buf_size = 0x30000*2,
3280 },
3281 .sao_vb = {
3282 .buf_size = 0x30000*2,
3283 },
3284 .short_term_rps = {
3285 // SHORT_TERM_RPS - Max 64 set, 16 entry every set, total 64x16x2 = 2048 bytes (0x800)
3286 .buf_size = 0x800,
3287 },
3288 .vps = {
3289 // VPS STORE AREA - Max 16 VPS, each has 0x80 bytes, total 0x0800 bytes
3290 .buf_size = 0x800,
3291 },
3292 .sps = {
3293 // SPS STORE AREA - Max 16 SPS, each has 0x80 bytes, total 0x0800 bytes
3294 .buf_size = 0x800,
3295 },
3296 .pps = {
3297 // PPS STORE AREA - Max 64 PPS, each has 0x80 bytes, total 0x2000 bytes
3298 .buf_size = 0x2000,
3299 },
3300 .sao_up = {
3301 // SAO UP STORE AREA - Max 640(10240/16) LCU, each has 16 bytes total 0x2800 bytes
3302 .buf_size = 0x2800*2,
3303 },
3304 .swap_buf = {
3305 // 256cyclex64bit = 2K bytes 0x800 (only 144 cycles valid)
3306 .buf_size = 0x800,
3307 },
3308 .swap_buf2 = {
3309 .buf_size = 0x800,
3310 },
3311 .scalelut = {
3312 // support up to 32 SCALELUT 1024x32 = 32Kbytes (0x8000)
3313 .buf_size = 0x8000*2,
3314 },
3315 .dblk_para = {
3316 // DBLK -> Max 256(4096/16) LCU, each para 1024bytes(total:0x40000), data 1024bytes(total:0x40000)
3317 .buf_size = 0x80000*2,
3318 },
3319 .dblk_data = {
3320 .buf_size = 0x80000*2,
3321 },
3322 .seg_map = {
3323 /*4096x2304/64/64 *24 = 0xd800 Bytes*/
3324 .buf_size = 0xd800*4,
3325 },
3326 .mmu_vbh = {
3327 .buf_size = 0x5000*2, //2*16*(more than 2304)/4, 4K
3328 },
3329#if 0
3330 .cm_header = {
3331 //.buf_size = MMU_COMPRESS_HEADER_SIZE*8, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
3332 .buf_size = MMU_COMPRESS_HEADER_SIZE*16, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
3333 },
3334#endif
3335 .mpred_above = {
3336 .buf_size = 0x10000*2, /* 2 * size of hevc*/
3337 },
3338#ifdef MV_USE_FIXED_BUF
3339 .mpred_mv = {
3340 //4k2k , 0x100000 per buffer */
3341 /* 4096x2304 , 0x120000 per buffer */
3342 .buf_size = 0x120000 * FRAME_BUFFERS * 4,
3343 },
3344#endif
3345 .rpm = {
3346 .buf_size = RPM_BUF_SIZE,
3347 },
3348 .lmem = {
3349 .buf_size = 0x400 * 2,
3350 }
3351 }
3352};
3353
3354
3355/*Losless compression body buffer size 4K per 64x32 (jt)*/
3356int compute_losless_comp_body_size(int width, int height,
3357 uint8_t is_bit_depth_10)
3358{
3359 int width_x64;
3360 int height_x32;
3361 int bsize;
3362
3363 width_x64 = width + 63;
3364 width_x64 >>= 6;
3365 height_x32 = height + 31;
3366 height_x32 >>= 5;
3367 bsize = (is_bit_depth_10?4096:3200)*width_x64*height_x32;
3368 if (debug & VP9_DEBUG_BUFMGR_MORE)
3369 pr_info("%s(%d,%d,%d)=>%d\n",
3370 __func__, width, height,
3371 is_bit_depth_10, bsize);
3372
3373 return bsize;
3374}
3375
3376/* Losless compression header buffer size 32bytes per 128x64 (jt)*/
3377static int compute_losless_comp_header_size(int width, int height)
3378{
3379 int width_x128;
3380 int height_x64;
3381 int hsize;
3382
3383 width_x128 = width + 127;
3384 width_x128 >>= 7;
3385 height_x64 = height + 63;
3386 height_x64 >>= 6;
3387
3388 hsize = 32 * width_x128 * height_x64;
3389 if (debug & VP9_DEBUG_BUFMGR_MORE)
3390 pr_info("%s(%d,%d)=>%d\n",
3391 __func__, width, height,
3392 hsize);
3393
3394 return hsize;
3395}
3396
3397static void init_buff_spec(struct VP9Decoder_s *pbi,
3398 struct BuffInfo_s *buf_spec)
3399{
3400 void *mem_start_virt;
3401
3402 buf_spec->ipp.buf_start = buf_spec->start_adr;
3403 buf_spec->sao_abv.buf_start =
3404 buf_spec->ipp.buf_start + buf_spec->ipp.buf_size;
3405
3406 buf_spec->sao_vb.buf_start =
3407 buf_spec->sao_abv.buf_start + buf_spec->sao_abv.buf_size;
3408 buf_spec->short_term_rps.buf_start =
3409 buf_spec->sao_vb.buf_start + buf_spec->sao_vb.buf_size;
3410 buf_spec->vps.buf_start =
3411 buf_spec->short_term_rps.buf_start +
3412 buf_spec->short_term_rps.buf_size;
3413 buf_spec->sps.buf_start =
3414 buf_spec->vps.buf_start + buf_spec->vps.buf_size;
3415 buf_spec->pps.buf_start =
3416 buf_spec->sps.buf_start + buf_spec->sps.buf_size;
3417 buf_spec->sao_up.buf_start =
3418 buf_spec->pps.buf_start + buf_spec->pps.buf_size;
3419 buf_spec->swap_buf.buf_start =
3420 buf_spec->sao_up.buf_start + buf_spec->sao_up.buf_size;
3421 buf_spec->swap_buf2.buf_start =
3422 buf_spec->swap_buf.buf_start + buf_spec->swap_buf.buf_size;
3423 buf_spec->scalelut.buf_start =
3424 buf_spec->swap_buf2.buf_start + buf_spec->swap_buf2.buf_size;
3425 buf_spec->dblk_para.buf_start =
3426 buf_spec->scalelut.buf_start + buf_spec->scalelut.buf_size;
3427 buf_spec->dblk_data.buf_start =
3428 buf_spec->dblk_para.buf_start + buf_spec->dblk_para.buf_size;
3429 buf_spec->seg_map.buf_start =
3430 buf_spec->dblk_data.buf_start + buf_spec->dblk_data.buf_size;
3431 if (pbi == NULL || pbi->mmu_enable) {
3432 buf_spec->mmu_vbh.buf_start =
3433 buf_spec->seg_map.buf_start +
3434 buf_spec->seg_map.buf_size;
3435 buf_spec->mpred_above.buf_start =
3436 buf_spec->mmu_vbh.buf_start +
3437 buf_spec->mmu_vbh.buf_size;
3438 } else {
3439 buf_spec->mpred_above.buf_start =
3440 buf_spec->seg_map.buf_start + buf_spec->seg_map.buf_size;
3441 }
3442#ifdef MV_USE_FIXED_BUF
3443 buf_spec->mpred_mv.buf_start =
3444 buf_spec->mpred_above.buf_start +
3445 buf_spec->mpred_above.buf_size;
3446
3447 buf_spec->rpm.buf_start =
3448 buf_spec->mpred_mv.buf_start +
3449 buf_spec->mpred_mv.buf_size;
3450#else
3451 buf_spec->rpm.buf_start =
3452 buf_spec->mpred_above.buf_start +
3453 buf_spec->mpred_above.buf_size;
3454
3455#endif
3456 buf_spec->lmem.buf_start =
3457 buf_spec->rpm.buf_start +
3458 buf_spec->rpm.buf_size;
3459 buf_spec->end_adr =
3460 buf_spec->lmem.buf_start +
3461 buf_spec->lmem.buf_size;
3462
3463 if (!pbi)
3464 return;
3465
3466 if (!vdec_secure(hw_to_vdec(pbi))) {
3467 mem_start_virt =
3468 codec_mm_phys_to_virt(buf_spec->dblk_para.buf_start);
3469 if (mem_start_virt) {
3470 memset(mem_start_virt, 0,
3471 buf_spec->dblk_para.buf_size);
3472 codec_mm_dma_flush(mem_start_virt,
3473 buf_spec->dblk_para.buf_size,
3474 DMA_TO_DEVICE);
3475 } else {
3476 mem_start_virt = codec_mm_vmap(
3477 buf_spec->dblk_para.buf_start,
3478 buf_spec->dblk_para.buf_size);
3479 if (mem_start_virt) {
3480 memset(mem_start_virt, 0,
3481 buf_spec->dblk_para.buf_size);
3482 codec_mm_dma_flush(mem_start_virt,
3483 buf_spec->dblk_para.buf_size,
3484 DMA_TO_DEVICE);
3485 codec_mm_unmap_phyaddr(mem_start_virt);
3486 } else {
3487 /*not virt for tvp playing,
3488 may need clear on ucode.*/
3489 pr_err("mem_start_virt failed\n");
3490 }
3491 }
3492 }
3493
3494 if (debug) {
3495 pr_info("%s workspace (%x %x) size = %x\n", __func__,
3496 buf_spec->start_adr, buf_spec->end_adr,
3497 buf_spec->end_adr - buf_spec->start_adr);
3498 }
3499
3500 if (debug) {
3501 pr_info("ipp.buf_start :%x\n",
3502 buf_spec->ipp.buf_start);
3503 pr_info("sao_abv.buf_start :%x\n",
3504 buf_spec->sao_abv.buf_start);
3505 pr_info("sao_vb.buf_start :%x\n",
3506 buf_spec->sao_vb.buf_start);
3507 pr_info("short_term_rps.buf_start :%x\n",
3508 buf_spec->short_term_rps.buf_start);
3509 pr_info("vps.buf_start :%x\n",
3510 buf_spec->vps.buf_start);
3511 pr_info("sps.buf_start :%x\n",
3512 buf_spec->sps.buf_start);
3513 pr_info("pps.buf_start :%x\n",
3514 buf_spec->pps.buf_start);
3515 pr_info("sao_up.buf_start :%x\n",
3516 buf_spec->sao_up.buf_start);
3517 pr_info("swap_buf.buf_start :%x\n",
3518 buf_spec->swap_buf.buf_start);
3519 pr_info("swap_buf2.buf_start :%x\n",
3520 buf_spec->swap_buf2.buf_start);
3521 pr_info("scalelut.buf_start :%x\n",
3522 buf_spec->scalelut.buf_start);
3523 pr_info("dblk_para.buf_start :%x\n",
3524 buf_spec->dblk_para.buf_start);
3525 pr_info("dblk_data.buf_start :%x\n",
3526 buf_spec->dblk_data.buf_start);
3527 pr_info("seg_map.buf_start :%x\n",
3528 buf_spec->seg_map.buf_start);
3529 if (pbi->mmu_enable) {
3530 pr_info("mmu_vbh.buf_start :%x\n",
3531 buf_spec->mmu_vbh.buf_start);
3532 }
3533 pr_info("mpred_above.buf_start :%x\n",
3534 buf_spec->mpred_above.buf_start);
3535#ifdef MV_USE_FIXED_BUF
3536 pr_info("mpred_mv.buf_start :%x\n",
3537 buf_spec->mpred_mv.buf_start);
3538#endif
3539 if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0) {
3540 pr_info("rpm.buf_start :%x\n",
3541 buf_spec->rpm.buf_start);
3542 }
3543 }
3544}
3545
3546/* cache_util.c */
3547#define THODIYIL_MCRCC_CANVAS_ALGX 4
3548
3549static u32 mcrcc_cache_alg_flag = THODIYIL_MCRCC_CANVAS_ALGX;
3550
3551static void mcrcc_perfcount_reset(void)
3552{
3553 if (debug & VP9_DEBUG_CACHE)
3554 pr_info("[cache_util.c] Entered mcrcc_perfcount_reset...\n");
3555 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x1);
3556 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x0);
3557 return;
3558}
3559
3560static unsigned raw_mcr_cnt_total_prev;
3561static unsigned hit_mcr_0_cnt_total_prev;
3562static unsigned hit_mcr_1_cnt_total_prev;
3563static unsigned byp_mcr_cnt_nchcanv_total_prev;
3564static unsigned byp_mcr_cnt_nchoutwin_total_prev;
3565
3566static void mcrcc_get_hitrate(unsigned reset_pre)
3567{
3568 unsigned delta_hit_mcr_0_cnt;
3569 unsigned delta_hit_mcr_1_cnt;
3570 unsigned delta_raw_mcr_cnt;
3571 unsigned delta_mcr_cnt_nchcanv;
3572 unsigned delta_mcr_cnt_nchoutwin;
3573
3574 unsigned tmp;
3575 unsigned raw_mcr_cnt;
3576 unsigned hit_mcr_cnt;
3577 unsigned byp_mcr_cnt_nchoutwin;
3578 unsigned byp_mcr_cnt_nchcanv;
3579 int hitrate;
3580 if (reset_pre) {
3581 raw_mcr_cnt_total_prev = 0;
3582 hit_mcr_0_cnt_total_prev = 0;
3583 hit_mcr_1_cnt_total_prev = 0;
3584 byp_mcr_cnt_nchcanv_total_prev = 0;
3585 byp_mcr_cnt_nchoutwin_total_prev = 0;
3586 }
3587 if (debug & VP9_DEBUG_CACHE)
3588 pr_info("[cache_util.c] Entered mcrcc_get_hitrate...\n");
3589 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x0<<1));
3590 raw_mcr_cnt = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3591 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x1<<1));
3592 hit_mcr_cnt = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3593 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x2<<1));
3594 byp_mcr_cnt_nchoutwin = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3595 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x3<<1));
3596 byp_mcr_cnt_nchcanv = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3597
3598 if (debug & VP9_DEBUG_CACHE)
3599 pr_info("raw_mcr_cnt_total: %d\n",
3600 raw_mcr_cnt);
3601 if (debug & VP9_DEBUG_CACHE)
3602 pr_info("hit_mcr_cnt_total: %d\n",
3603 hit_mcr_cnt);
3604 if (debug & VP9_DEBUG_CACHE)
3605 pr_info("byp_mcr_cnt_nchoutwin_total: %d\n",
3606 byp_mcr_cnt_nchoutwin);
3607 if (debug & VP9_DEBUG_CACHE)
3608 pr_info("byp_mcr_cnt_nchcanv_total: %d\n",
3609 byp_mcr_cnt_nchcanv);
3610
3611 delta_raw_mcr_cnt = raw_mcr_cnt -
3612 raw_mcr_cnt_total_prev;
3613 delta_mcr_cnt_nchcanv = byp_mcr_cnt_nchcanv -
3614 byp_mcr_cnt_nchcanv_total_prev;
3615 delta_mcr_cnt_nchoutwin = byp_mcr_cnt_nchoutwin -
3616 byp_mcr_cnt_nchoutwin_total_prev;
3617 raw_mcr_cnt_total_prev = raw_mcr_cnt;
3618 byp_mcr_cnt_nchcanv_total_prev = byp_mcr_cnt_nchcanv;
3619 byp_mcr_cnt_nchoutwin_total_prev = byp_mcr_cnt_nchoutwin;
3620
3621 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x4<<1));
3622 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3623 if (debug & VP9_DEBUG_CACHE)
3624 pr_info("miss_mcr_0_cnt_total: %d\n", tmp);
3625 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x5<<1));
3626 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3627 if (debug & VP9_DEBUG_CACHE)
3628 pr_info("miss_mcr_1_cnt_total: %d\n", tmp);
3629 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x6<<1));
3630 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3631 if (debug & VP9_DEBUG_CACHE)
3632 pr_info("hit_mcr_0_cnt_total: %d\n", tmp);
3633 delta_hit_mcr_0_cnt = tmp - hit_mcr_0_cnt_total_prev;
3634 hit_mcr_0_cnt_total_prev = tmp;
3635 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x7<<1));
3636 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3637 if (debug & VP9_DEBUG_CACHE)
3638 pr_info("hit_mcr_1_cnt_total: %d\n", tmp);
3639 delta_hit_mcr_1_cnt = tmp - hit_mcr_1_cnt_total_prev;
3640 hit_mcr_1_cnt_total_prev = tmp;
3641
3642 if (delta_raw_mcr_cnt != 0) {
3643 hitrate = 100 * delta_hit_mcr_0_cnt
3644 / delta_raw_mcr_cnt;
3645 if (debug & VP9_DEBUG_CACHE)
3646 pr_info("CANV0_HIT_RATE : %d\n", hitrate);
3647 hitrate = 100 * delta_hit_mcr_1_cnt
3648 / delta_raw_mcr_cnt;
3649 if (debug & VP9_DEBUG_CACHE)
3650 pr_info("CANV1_HIT_RATE : %d\n", hitrate);
3651 hitrate = 100 * delta_mcr_cnt_nchcanv
3652 / delta_raw_mcr_cnt;
3653 if (debug & VP9_DEBUG_CACHE)
3654 pr_info("NONCACH_CANV_BYP_RATE : %d\n", hitrate);
3655 hitrate = 100 * delta_mcr_cnt_nchoutwin
3656 / delta_raw_mcr_cnt;
3657 if (debug & VP9_DEBUG_CACHE)
3658 pr_info("CACHE_OUTWIN_BYP_RATE : %d\n", hitrate);
3659 }
3660
3661
3662 if (raw_mcr_cnt != 0) {
3663 hitrate = 100 * hit_mcr_cnt / raw_mcr_cnt;
3664 if (debug & VP9_DEBUG_CACHE)
3665 pr_info("MCRCC_HIT_RATE : %d\n", hitrate);
3666 hitrate = 100 * (byp_mcr_cnt_nchoutwin + byp_mcr_cnt_nchcanv)
3667 / raw_mcr_cnt;
3668 if (debug & VP9_DEBUG_CACHE)
3669 pr_info("MCRCC_BYP_RATE : %d\n", hitrate);
3670 } else {
3671 if (debug & VP9_DEBUG_CACHE)
3672 pr_info("MCRCC_HIT_RATE : na\n");
3673 if (debug & VP9_DEBUG_CACHE)
3674 pr_info("MCRCC_BYP_RATE : na\n");
3675 }
3676 return;
3677}
3678
3679
3680static void decomp_perfcount_reset(void)
3681{
3682 if (debug & VP9_DEBUG_CACHE)
3683 pr_info("[cache_util.c] Entered decomp_perfcount_reset...\n");
3684 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x1);
3685 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x0);
3686 return;
3687}
3688
3689static void decomp_get_hitrate(void)
3690{
3691 unsigned raw_mcr_cnt;
3692 unsigned hit_mcr_cnt;
3693 int hitrate;
3694 if (debug & VP9_DEBUG_CACHE)
3695 pr_info("[cache_util.c] Entered decomp_get_hitrate...\n");
3696 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x0<<1));
3697 raw_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3698 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x1<<1));
3699 hit_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3700
3701 if (debug & VP9_DEBUG_CACHE)
3702 pr_info("hcache_raw_cnt_total: %d\n", raw_mcr_cnt);
3703 if (debug & VP9_DEBUG_CACHE)
3704 pr_info("hcache_hit_cnt_total: %d\n", hit_mcr_cnt);
3705
3706 if (raw_mcr_cnt != 0) {
3707 hitrate = hit_mcr_cnt * 100 / raw_mcr_cnt;
3708 if (debug & VP9_DEBUG_CACHE)
3709 pr_info("DECOMP_HCACHE_HIT_RATE : %d\n", hitrate);
3710 } else {
3711 if (debug & VP9_DEBUG_CACHE)
3712 pr_info("DECOMP_HCACHE_HIT_RATE : na\n");
3713 }
3714 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x2<<1));
3715 raw_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3716 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x3<<1));
3717 hit_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3718
3719 if (debug & VP9_DEBUG_CACHE)
3720 pr_info("dcache_raw_cnt_total: %d\n", raw_mcr_cnt);
3721 if (debug & VP9_DEBUG_CACHE)
3722 pr_info("dcache_hit_cnt_total: %d\n", hit_mcr_cnt);
3723
3724 if (raw_mcr_cnt != 0) {
3725 hitrate = hit_mcr_cnt * 100 / raw_mcr_cnt;
3726 if (debug & VP9_DEBUG_CACHE)
3727 pr_info("DECOMP_DCACHE_HIT_RATE : %d\n", hitrate);
3728 } else {
3729 if (debug & VP9_DEBUG_CACHE)
3730 pr_info("DECOMP_DCACHE_HIT_RATE : na\n");
3731 }
3732 return;
3733}
3734
3735static void decomp_get_comprate(void)
3736{
3737 unsigned raw_ucomp_cnt;
3738 unsigned fast_comp_cnt;
3739 unsigned slow_comp_cnt;
3740 int comprate;
3741
3742 if (debug & VP9_DEBUG_CACHE)
3743 pr_info("[cache_util.c] Entered decomp_get_comprate...\n");
3744 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x4<<1));
3745 fast_comp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3746 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x5<<1));
3747 slow_comp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3748 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x6<<1));
3749 raw_ucomp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3750
3751 if (debug & VP9_DEBUG_CACHE)
3752 pr_info("decomp_fast_comp_total: %d\n", fast_comp_cnt);
3753 if (debug & VP9_DEBUG_CACHE)
3754 pr_info("decomp_slow_comp_total: %d\n", slow_comp_cnt);
3755 if (debug & VP9_DEBUG_CACHE)
3756 pr_info("decomp_raw_uncomp_total: %d\n", raw_ucomp_cnt);
3757
3758 if (raw_ucomp_cnt != 0) {
3759 comprate = (fast_comp_cnt + slow_comp_cnt)
3760 * 100 / raw_ucomp_cnt;
3761 if (debug & VP9_DEBUG_CACHE)
3762 pr_info("DECOMP_COMP_RATIO : %d\n", comprate);
3763 } else {
3764 if (debug & VP9_DEBUG_CACHE)
3765 pr_info("DECOMP_COMP_RATIO : na\n");
3766 }
3767 return;
3768}
3769/* cache_util.c end */
3770
3771/*====================================================
3772 *========================================================================
3773 *vp9_prob define
3774 *========================================================================
3775 */
3776#define VP9_PARTITION_START 0
3777#define VP9_PARTITION_SIZE_STEP (3 * 4)
3778#define VP9_PARTITION_ONE_SIZE (4 * VP9_PARTITION_SIZE_STEP)
3779#define VP9_PARTITION_KEY_START 0
3780#define VP9_PARTITION_P_START VP9_PARTITION_ONE_SIZE
3781#define VP9_PARTITION_SIZE (2 * VP9_PARTITION_ONE_SIZE)
3782#define VP9_SKIP_START (VP9_PARTITION_START + VP9_PARTITION_SIZE)
3783#define VP9_SKIP_SIZE 4 /* only use 3*/
3784#define VP9_TX_MODE_START (VP9_SKIP_START+VP9_SKIP_SIZE)
3785#define VP9_TX_MODE_8_0_OFFSET 0
3786#define VP9_TX_MODE_8_1_OFFSET 1
3787#define VP9_TX_MODE_16_0_OFFSET 2
3788#define VP9_TX_MODE_16_1_OFFSET 4
3789#define VP9_TX_MODE_32_0_OFFSET 6
3790#define VP9_TX_MODE_32_1_OFFSET 9
3791#define VP9_TX_MODE_SIZE 12
3792#define VP9_COEF_START (VP9_TX_MODE_START+VP9_TX_MODE_SIZE)
3793#define VP9_COEF_BAND_0_OFFSET 0
3794#define VP9_COEF_BAND_1_OFFSET (VP9_COEF_BAND_0_OFFSET + 3 * 3 + 1)
3795#define VP9_COEF_BAND_2_OFFSET (VP9_COEF_BAND_1_OFFSET + 6 * 3)
3796#define VP9_COEF_BAND_3_OFFSET (VP9_COEF_BAND_2_OFFSET + 6 * 3)
3797#define VP9_COEF_BAND_4_OFFSET (VP9_COEF_BAND_3_OFFSET + 6 * 3)
3798#define VP9_COEF_BAND_5_OFFSET (VP9_COEF_BAND_4_OFFSET + 6 * 3)
3799#define VP9_COEF_SIZE_ONE_SET 100 /* ((3 +5*6)*3 + 1 padding)*/
3800#define VP9_COEF_4X4_START (VP9_COEF_START + 0 * VP9_COEF_SIZE_ONE_SET)
3801#define VP9_COEF_8X8_START (VP9_COEF_START + 4 * VP9_COEF_SIZE_ONE_SET)
3802#define VP9_COEF_16X16_START (VP9_COEF_START + 8 * VP9_COEF_SIZE_ONE_SET)
3803#define VP9_COEF_32X32_START (VP9_COEF_START + 12 * VP9_COEF_SIZE_ONE_SET)
3804#define VP9_COEF_SIZE_PLANE (2 * VP9_COEF_SIZE_ONE_SET)
3805#define VP9_COEF_SIZE (4 * 2 * 2 * VP9_COEF_SIZE_ONE_SET)
3806#define VP9_INTER_MODE_START (VP9_COEF_START+VP9_COEF_SIZE)
3807#define VP9_INTER_MODE_SIZE 24 /* only use 21 ( #*7)*/
3808#define VP9_INTERP_START (VP9_INTER_MODE_START+VP9_INTER_MODE_SIZE)
3809#define VP9_INTERP_SIZE 8
3810#define VP9_INTRA_INTER_START (VP9_INTERP_START+VP9_INTERP_SIZE)
3811#define VP9_INTRA_INTER_SIZE 4
3812#define VP9_INTERP_INTRA_INTER_START VP9_INTERP_START
3813#define VP9_INTERP_INTRA_INTER_SIZE (VP9_INTERP_SIZE + VP9_INTRA_INTER_SIZE)
3814#define VP9_COMP_INTER_START \
3815 (VP9_INTERP_INTRA_INTER_START+VP9_INTERP_INTRA_INTER_SIZE)
3816#define VP9_COMP_INTER_SIZE 5
3817#define VP9_COMP_REF_START (VP9_COMP_INTER_START+VP9_COMP_INTER_SIZE)
3818#define VP9_COMP_REF_SIZE 5
3819#define VP9_SINGLE_REF_START (VP9_COMP_REF_START+VP9_COMP_REF_SIZE)
3820#define VP9_SINGLE_REF_SIZE 10
3821#define VP9_REF_MODE_START VP9_COMP_INTER_START
3822#define VP9_REF_MODE_SIZE \
3823 (VP9_COMP_INTER_SIZE+VP9_COMP_REF_SIZE+VP9_SINGLE_REF_SIZE)
3824#define VP9_IF_Y_MODE_START (VP9_REF_MODE_START+VP9_REF_MODE_SIZE)
3825#define VP9_IF_Y_MODE_SIZE 36
3826#define VP9_IF_UV_MODE_START (VP9_IF_Y_MODE_START+VP9_IF_Y_MODE_SIZE)
3827#define VP9_IF_UV_MODE_SIZE 92 /* only use 90*/
3828#define VP9_MV_JOINTS_START (VP9_IF_UV_MODE_START+VP9_IF_UV_MODE_SIZE)
3829#define VP9_MV_JOINTS_SIZE 3
3830#define VP9_MV_SIGN_0_START (VP9_MV_JOINTS_START+VP9_MV_JOINTS_SIZE)
3831#define VP9_MV_SIGN_0_SIZE 1
3832#define VP9_MV_CLASSES_0_START (VP9_MV_SIGN_0_START+VP9_MV_SIGN_0_SIZE)
3833#define VP9_MV_CLASSES_0_SIZE 10
3834#define VP9_MV_CLASS0_0_START (VP9_MV_CLASSES_0_START+VP9_MV_CLASSES_0_SIZE)
3835#define VP9_MV_CLASS0_0_SIZE 1
3836#define VP9_MV_BITS_0_START (VP9_MV_CLASS0_0_START+VP9_MV_CLASS0_0_SIZE)
3837#define VP9_MV_BITS_0_SIZE 10
3838#define VP9_MV_SIGN_1_START (VP9_MV_BITS_0_START+VP9_MV_BITS_0_SIZE)
3839#define VP9_MV_SIGN_1_SIZE 1
3840#define VP9_MV_CLASSES_1_START \
3841 (VP9_MV_SIGN_1_START+VP9_MV_SIGN_1_SIZE)
3842#define VP9_MV_CLASSES_1_SIZE 10
3843#define VP9_MV_CLASS0_1_START \
3844 (VP9_MV_CLASSES_1_START+VP9_MV_CLASSES_1_SIZE)
3845#define VP9_MV_CLASS0_1_SIZE 1
3846#define VP9_MV_BITS_1_START \
3847 (VP9_MV_CLASS0_1_START+VP9_MV_CLASS0_1_SIZE)
3848#define VP9_MV_BITS_1_SIZE 10
3849#define VP9_MV_CLASS0_FP_0_START \
3850 (VP9_MV_BITS_1_START+VP9_MV_BITS_1_SIZE)
3851#define VP9_MV_CLASS0_FP_0_SIZE 9
3852#define VP9_MV_CLASS0_FP_1_START \
3853 (VP9_MV_CLASS0_FP_0_START+VP9_MV_CLASS0_FP_0_SIZE)
3854#define VP9_MV_CLASS0_FP_1_SIZE 9
3855#define VP9_MV_CLASS0_HP_0_START \
3856 (VP9_MV_CLASS0_FP_1_START+VP9_MV_CLASS0_FP_1_SIZE)
3857#define VP9_MV_CLASS0_HP_0_SIZE 2
3858#define VP9_MV_CLASS0_HP_1_START \
3859 (VP9_MV_CLASS0_HP_0_START+VP9_MV_CLASS0_HP_0_SIZE)
3860#define VP9_MV_CLASS0_HP_1_SIZE 2
3861#define VP9_MV_START VP9_MV_JOINTS_START
3862#define VP9_MV_SIZE 72 /*only use 69*/
3863
3864#define VP9_TOTAL_SIZE (VP9_MV_START + VP9_MV_SIZE)
3865
3866
3867/*========================================================================
3868 * vp9_count_mem define
3869 *========================================================================
3870 */
3871#define VP9_COEF_COUNT_START 0
3872#define VP9_COEF_COUNT_BAND_0_OFFSET 0
3873#define VP9_COEF_COUNT_BAND_1_OFFSET \
3874 (VP9_COEF_COUNT_BAND_0_OFFSET + 3*5)
3875#define VP9_COEF_COUNT_BAND_2_OFFSET \
3876 (VP9_COEF_COUNT_BAND_1_OFFSET + 6*5)
3877#define VP9_COEF_COUNT_BAND_3_OFFSET \
3878 (VP9_COEF_COUNT_BAND_2_OFFSET + 6*5)
3879#define VP9_COEF_COUNT_BAND_4_OFFSET \
3880 (VP9_COEF_COUNT_BAND_3_OFFSET + 6*5)
3881#define VP9_COEF_COUNT_BAND_5_OFFSET \
3882 (VP9_COEF_COUNT_BAND_4_OFFSET + 6*5)
3883#define VP9_COEF_COUNT_SIZE_ONE_SET 165 /* ((3 +5*6)*5 */
3884#define VP9_COEF_COUNT_4X4_START \
3885 (VP9_COEF_COUNT_START + 0*VP9_COEF_COUNT_SIZE_ONE_SET)
3886#define VP9_COEF_COUNT_8X8_START \
3887 (VP9_COEF_COUNT_START + 4*VP9_COEF_COUNT_SIZE_ONE_SET)
3888#define VP9_COEF_COUNT_16X16_START \
3889 (VP9_COEF_COUNT_START + 8*VP9_COEF_COUNT_SIZE_ONE_SET)
3890#define VP9_COEF_COUNT_32X32_START \
3891 (VP9_COEF_COUNT_START + 12*VP9_COEF_COUNT_SIZE_ONE_SET)
3892#define VP9_COEF_COUNT_SIZE_PLANE (2 * VP9_COEF_COUNT_SIZE_ONE_SET)
3893#define VP9_COEF_COUNT_SIZE (4 * 2 * 2 * VP9_COEF_COUNT_SIZE_ONE_SET)
3894
3895#define VP9_INTRA_INTER_COUNT_START \
3896 (VP9_COEF_COUNT_START+VP9_COEF_COUNT_SIZE)
3897#define VP9_INTRA_INTER_COUNT_SIZE (4*2)
3898#define VP9_COMP_INTER_COUNT_START \
3899 (VP9_INTRA_INTER_COUNT_START+VP9_INTRA_INTER_COUNT_SIZE)
3900#define VP9_COMP_INTER_COUNT_SIZE (5*2)
3901#define VP9_COMP_REF_COUNT_START \
3902 (VP9_COMP_INTER_COUNT_START+VP9_COMP_INTER_COUNT_SIZE)
3903#define VP9_COMP_REF_COUNT_SIZE (5*2)
3904#define VP9_SINGLE_REF_COUNT_START \
3905 (VP9_COMP_REF_COUNT_START+VP9_COMP_REF_COUNT_SIZE)
3906#define VP9_SINGLE_REF_COUNT_SIZE (10*2)
3907#define VP9_TX_MODE_COUNT_START \
3908 (VP9_SINGLE_REF_COUNT_START+VP9_SINGLE_REF_COUNT_SIZE)
3909#define VP9_TX_MODE_COUNT_SIZE (12*2)
3910#define VP9_SKIP_COUNT_START \
3911 (VP9_TX_MODE_COUNT_START+VP9_TX_MODE_COUNT_SIZE)
3912#define VP9_SKIP_COUNT_SIZE (3*2)
3913#define VP9_MV_SIGN_0_COUNT_START \
3914 (VP9_SKIP_COUNT_START+VP9_SKIP_COUNT_SIZE)
3915#define VP9_MV_SIGN_0_COUNT_SIZE (1*2)
3916#define VP9_MV_SIGN_1_COUNT_START \
3917 (VP9_MV_SIGN_0_COUNT_START+VP9_MV_SIGN_0_COUNT_SIZE)
3918#define VP9_MV_SIGN_1_COUNT_SIZE (1*2)
3919#define VP9_MV_BITS_0_COUNT_START \
3920 (VP9_MV_SIGN_1_COUNT_START+VP9_MV_SIGN_1_COUNT_SIZE)
3921#define VP9_MV_BITS_0_COUNT_SIZE (10*2)
3922#define VP9_MV_BITS_1_COUNT_START \
3923 (VP9_MV_BITS_0_COUNT_START+VP9_MV_BITS_0_COUNT_SIZE)
3924#define VP9_MV_BITS_1_COUNT_SIZE (10*2)
3925#define VP9_MV_CLASS0_HP_0_COUNT_START \
3926 (VP9_MV_BITS_1_COUNT_START+VP9_MV_BITS_1_COUNT_SIZE)
3927#define VP9_MV_CLASS0_HP_0_COUNT_SIZE (2*2)
3928#define VP9_MV_CLASS0_HP_1_COUNT_START \
3929 (VP9_MV_CLASS0_HP_0_COUNT_START+VP9_MV_CLASS0_HP_0_COUNT_SIZE)
3930#define VP9_MV_CLASS0_HP_1_COUNT_SIZE (2*2)
3931/* Start merge_tree*/
3932#define VP9_INTER_MODE_COUNT_START \
3933 (VP9_MV_CLASS0_HP_1_COUNT_START+VP9_MV_CLASS0_HP_1_COUNT_SIZE)
3934#define VP9_INTER_MODE_COUNT_SIZE (7*4)
3935#define VP9_IF_Y_MODE_COUNT_START \
3936 (VP9_INTER_MODE_COUNT_START+VP9_INTER_MODE_COUNT_SIZE)
3937#define VP9_IF_Y_MODE_COUNT_SIZE (10*4)
3938#define VP9_IF_UV_MODE_COUNT_START \
3939 (VP9_IF_Y_MODE_COUNT_START+VP9_IF_Y_MODE_COUNT_SIZE)
3940#define VP9_IF_UV_MODE_COUNT_SIZE (10*10)
3941#define VP9_PARTITION_P_COUNT_START \
3942 (VP9_IF_UV_MODE_COUNT_START+VP9_IF_UV_MODE_COUNT_SIZE)
3943#define VP9_PARTITION_P_COUNT_SIZE (4*4*4)
3944#define VP9_INTERP_COUNT_START \
3945 (VP9_PARTITION_P_COUNT_START+VP9_PARTITION_P_COUNT_SIZE)
3946#define VP9_INTERP_COUNT_SIZE (4*3)
3947#define VP9_MV_JOINTS_COUNT_START \
3948 (VP9_INTERP_COUNT_START+VP9_INTERP_COUNT_SIZE)
3949#define VP9_MV_JOINTS_COUNT_SIZE (1 * 4)
3950#define VP9_MV_CLASSES_0_COUNT_START \
3951 (VP9_MV_JOINTS_COUNT_START+VP9_MV_JOINTS_COUNT_SIZE)
3952#define VP9_MV_CLASSES_0_COUNT_SIZE (1*11)
3953#define VP9_MV_CLASS0_0_COUNT_START \
3954 (VP9_MV_CLASSES_0_COUNT_START+VP9_MV_CLASSES_0_COUNT_SIZE)
3955#define VP9_MV_CLASS0_0_COUNT_SIZE (1*2)
3956#define VP9_MV_CLASSES_1_COUNT_START \
3957 (VP9_MV_CLASS0_0_COUNT_START+VP9_MV_CLASS0_0_COUNT_SIZE)
3958#define VP9_MV_CLASSES_1_COUNT_SIZE (1*11)
3959#define VP9_MV_CLASS0_1_COUNT_START \
3960 (VP9_MV_CLASSES_1_COUNT_START+VP9_MV_CLASSES_1_COUNT_SIZE)
3961#define VP9_MV_CLASS0_1_COUNT_SIZE (1*2)
3962#define VP9_MV_CLASS0_FP_0_COUNT_START \
3963 (VP9_MV_CLASS0_1_COUNT_START+VP9_MV_CLASS0_1_COUNT_SIZE)
3964#define VP9_MV_CLASS0_FP_0_COUNT_SIZE (3*4)
3965#define VP9_MV_CLASS0_FP_1_COUNT_START \
3966 (VP9_MV_CLASS0_FP_0_COUNT_START+VP9_MV_CLASS0_FP_0_COUNT_SIZE)
3967#define VP9_MV_CLASS0_FP_1_COUNT_SIZE (3*4)
3968
3969
3970#define DC_PRED 0 /* Average of above and left pixels*/
3971#define V_PRED 1 /* Vertical*/
3972#define H_PRED 2 /* Horizontal*/
3973#define D45_PRED 3 /*Directional 45 deg = round(arctan(1/1) * 180/pi)*/
3974#define D135_PRED 4 /* Directional 135 deg = 180 - 45*/
3975#define D117_PRED 5 /* Directional 117 deg = 180 - 63*/
3976#define D153_PRED 6 /* Directional 153 deg = 180 - 27*/
3977#define D207_PRED 7 /* Directional 207 deg = 180 + 27*/
3978#define D63_PRED 8 /*Directional 63 deg = round(arctan(2/1) * 180/pi)*/
3979#define TM_PRED 9 /*True-motion*/
3980
3981int clip_prob(int p)
3982{
3983 return (p > 255) ? 255 : (p < 1) ? 1 : p;
3984}
3985
3986#define ROUND_POWER_OF_TWO(value, n) \
3987 (((value) + (1 << ((n) - 1))) >> (n))
3988
3989#define MODE_MV_COUNT_SAT 20
3990static const int count_to_update_factor[MODE_MV_COUNT_SAT + 1] = {
3991 0, 6, 12, 19, 25, 32, 38, 44, 51, 57, 64,
3992 70, 76, 83, 89, 96, 102, 108, 115, 121, 128
3993};
3994
3995void vp9_tree_merge_probs(unsigned int *prev_prob, unsigned int *cur_prob,
3996 int coef_node_start, int tree_left, int tree_right, int tree_i,
3997 int node) {
3998
3999 int prob_32, prob_res, prob_shift;
4000 int pre_prob, new_prob;
4001 int den, m_count, get_prob, factor;
4002
4003 prob_32 = prev_prob[coef_node_start / 4 * 2];
4004 prob_res = coef_node_start & 3;
4005 prob_shift = prob_res * 8;
4006 pre_prob = (prob_32 >> prob_shift) & 0xff;
4007
4008 den = tree_left + tree_right;
4009
4010 if (den == 0)
4011 new_prob = pre_prob;
4012 else {
4013 m_count = (den < MODE_MV_COUNT_SAT) ?
4014 den : MODE_MV_COUNT_SAT;
4015 get_prob = clip_prob(
4016 div_r32(((int64_t)tree_left * 256 + (den >> 1)),
4017 den));
4018 /*weighted_prob*/
4019 factor = count_to_update_factor[m_count];
4020 new_prob = ROUND_POWER_OF_TWO(pre_prob * (256 - factor)
4021 + get_prob * factor, 8);
4022 }
4023 cur_prob[coef_node_start / 4 * 2] = (cur_prob[coef_node_start / 4 * 2]
4024 & (~(0xff << prob_shift))) | (new_prob << prob_shift);
4025
4026 /*pr_info(" - [%d][%d] 0x%02X --> 0x%02X (0x%X 0x%X) (%X)\n",
4027 *tree_i, node, pre_prob, new_prob, tree_left, tree_right,
4028 *cur_prob[coef_node_start/4*2]);
4029 */
4030}
4031
4032
4033/*void adapt_coef_probs(void)*/
4034void adapt_coef_probs(int pic_count, int prev_kf, int cur_kf, int pre_fc,
4035 unsigned int *prev_prob, unsigned int *cur_prob, unsigned int *count)
4036{
4037 /* 80 * 64bits = 0xF00 ( use 0x1000 4K bytes)
4038 *unsigned int prev_prob[496*2];
4039 *unsigned int cur_prob[496*2];
4040 *0x300 * 128bits = 0x3000 (32K Bytes)
4041 *unsigned int count[0x300*4];
4042 */
4043
4044 int tx_size, coef_tx_size_start, coef_count_tx_size_start;
4045 int plane, coef_plane_start, coef_count_plane_start;
4046 int type, coef_type_start, coef_count_type_start;
4047 int band, coef_band_start, coef_count_band_start;
4048 int cxt_num;
4049 int cxt, coef_cxt_start, coef_count_cxt_start;
4050 int node, coef_node_start, coef_count_node_start;
4051
4052 int tree_i, tree_left, tree_right;
4053 int mvd_i;
4054
4055 int count_sat = 24;
4056 /*int update_factor = 112;*/ /*If COEF_MAX_UPDATE_FACTOR_AFTER_KEY,
4057 *use 128
4058 */
4059 /* If COEF_MAX_UPDATE_FACTOR_AFTER_KEY, use 128*/
4060 /*int update_factor = (pic_count == 1) ? 128 : 112;*/
4061 int update_factor = cur_kf ? 112 :
4062 prev_kf ? 128 : 112;
4063
4064 int prob_32;
4065 int prob_res;
4066 int prob_shift;
4067 int pre_prob;
4068
4069 int num, den;
4070 int get_prob;
4071 int m_count;
4072 int factor;
4073
4074 int new_prob;
4075
4076 if (debug & VP9_DEBUG_MERGE)
4077 pr_info
4078 ("\n ##adapt_coef_probs (pre_fc : %d ,prev_kf : %d,cur_kf : %d)##\n\n",
4079 pre_fc, prev_kf, cur_kf);
4080
4081 /*adapt_coef_probs*/
4082 for (tx_size = 0; tx_size < 4; tx_size++) {
4083 coef_tx_size_start = VP9_COEF_START
4084 + tx_size * 4 * VP9_COEF_SIZE_ONE_SET;
4085 coef_count_tx_size_start = VP9_COEF_COUNT_START
4086 + tx_size * 4 * VP9_COEF_COUNT_SIZE_ONE_SET;
4087 coef_plane_start = coef_tx_size_start;
4088 coef_count_plane_start = coef_count_tx_size_start;
4089 for (plane = 0; plane < 2; plane++) {
4090 coef_type_start = coef_plane_start;
4091 coef_count_type_start = coef_count_plane_start;
4092 for (type = 0; type < 2; type++) {
4093 coef_band_start = coef_type_start;
4094 coef_count_band_start = coef_count_type_start;
4095 for (band = 0; band < 6; band++) {
4096 if (band == 0)
4097 cxt_num = 3;
4098 else
4099 cxt_num = 6;
4100 coef_cxt_start = coef_band_start;
4101 coef_count_cxt_start =
4102 coef_count_band_start;
4103 for (cxt = 0; cxt < cxt_num; cxt++) {
4104 const int n0 =
4105 count[coef_count_cxt_start];
4106 const int n1 =
4107 count[coef_count_cxt_start + 1];
4108 const int n2 =
4109 count[coef_count_cxt_start + 2];
4110 const int neob =
4111 count[coef_count_cxt_start + 3];
4112 const int nneob =
4113 count[coef_count_cxt_start + 4];
4114 const unsigned int
4115 branch_ct[3][2] = {
4116 { neob, nneob },
4117 { n0, n1 + n2 },
4118 { n1, n2 }
4119 };
4120 coef_node_start =
4121 coef_cxt_start;
4122 for
4123 (node = 0; node < 3; node++) {
4124 prob_32 =
4125 prev_prob[
4126 coef_node_start
4127 / 4 * 2];
4128 prob_res =
4129 coef_node_start & 3;
4130 prob_shift =
4131 prob_res * 8;
4132 pre_prob =
4133 (prob_32 >> prob_shift)
4134 & 0xff;
4135
4136 /*get_binary_prob*/
4137 num =
4138 branch_ct[node][0];
4139 den =
4140 branch_ct[node][0] +
4141 branch_ct[node][1];
4142 m_count = (den <
4143 count_sat)
4144 ? den : count_sat;
4145
4146 get_prob =
4147 (den == 0) ? 128u :
4148 clip_prob(
4149 div_r32(((int64_t)
4150 num * 256
4151 + (den >> 1)),
4152 den));
4153
4154 factor =
4155 update_factor * m_count
4156 / count_sat;
4157 new_prob =
4158 ROUND_POWER_OF_TWO
4159 (pre_prob *
4160 (256 - factor) +
4161 get_prob * factor, 8);
4162
4163 cur_prob[coef_node_start
4164 / 4 * 2] =
4165 (cur_prob
4166 [coef_node_start
4167 / 4 * 2] & (~(0xff <<
4168 prob_shift))) |
4169 (new_prob <<
4170 prob_shift);
4171
4172 coef_node_start += 1;
4173 }
4174
4175 coef_cxt_start =
4176 coef_cxt_start + 3;
4177 coef_count_cxt_start =
4178 coef_count_cxt_start
4179 + 5;
4180 }
4181 if (band == 0) {
4182 coef_band_start += 10;
4183 coef_count_band_start += 15;
4184 } else {
4185 coef_band_start += 18;
4186 coef_count_band_start += 30;
4187 }
4188 }
4189 coef_type_start += VP9_COEF_SIZE_ONE_SET;
4190 coef_count_type_start +=
4191 VP9_COEF_COUNT_SIZE_ONE_SET;
4192 }
4193 coef_plane_start += 2 * VP9_COEF_SIZE_ONE_SET;
4194 coef_count_plane_start +=
4195 2 * VP9_COEF_COUNT_SIZE_ONE_SET;
4196 }
4197 }
4198
4199 if (cur_kf == 0) {
4200 /*mode_mv_merge_probs - merge_intra_inter_prob*/
4201 for (coef_count_node_start = VP9_INTRA_INTER_COUNT_START;
4202 coef_count_node_start < (VP9_MV_CLASS0_HP_1_COUNT_START +
4203 VP9_MV_CLASS0_HP_1_COUNT_SIZE); coef_count_node_start += 2) {
4204
4205 if (coef_count_node_start ==
4206 VP9_INTRA_INTER_COUNT_START) {
4207 if (debug & VP9_DEBUG_MERGE)
4208 pr_info(" # merge_intra_inter_prob\n");
4209 coef_node_start = VP9_INTRA_INTER_START;
4210 } else if (coef_count_node_start ==
4211 VP9_COMP_INTER_COUNT_START) {
4212 if (debug & VP9_DEBUG_MERGE)
4213 pr_info(" # merge_comp_inter_prob\n");
4214 coef_node_start = VP9_COMP_INTER_START;
4215 }
4216 /*
4217 *else if (coef_count_node_start ==
4218 * VP9_COMP_REF_COUNT_START) {
4219 * pr_info(" # merge_comp_inter_prob\n");
4220 * coef_node_start = VP9_COMP_REF_START;
4221 *}
4222 *else if (coef_count_node_start ==
4223 * VP9_SINGLE_REF_COUNT_START) {
4224 * pr_info(" # merge_comp_inter_prob\n");
4225 * coef_node_start = VP9_SINGLE_REF_START;
4226 *}
4227 */
4228 else if (coef_count_node_start ==
4229 VP9_TX_MODE_COUNT_START) {
4230 if (debug & VP9_DEBUG_MERGE)
4231 pr_info(" # merge_tx_mode_probs\n");
4232 coef_node_start = VP9_TX_MODE_START;
4233 } else if (coef_count_node_start ==
4234 VP9_SKIP_COUNT_START) {
4235 if (debug & VP9_DEBUG_MERGE)
4236 pr_info(" # merge_skip_probs\n");
4237 coef_node_start = VP9_SKIP_START;
4238 } else if (coef_count_node_start ==
4239 VP9_MV_SIGN_0_COUNT_START) {
4240 if (debug & VP9_DEBUG_MERGE)
4241 pr_info(" # merge_sign_0\n");
4242 coef_node_start = VP9_MV_SIGN_0_START;
4243 } else if (coef_count_node_start ==
4244 VP9_MV_SIGN_1_COUNT_START) {
4245 if (debug & VP9_DEBUG_MERGE)
4246 pr_info(" # merge_sign_1\n");
4247 coef_node_start = VP9_MV_SIGN_1_START;
4248 } else if (coef_count_node_start ==
4249 VP9_MV_BITS_0_COUNT_START) {
4250 if (debug & VP9_DEBUG_MERGE)
4251 pr_info(" # merge_bits_0\n");
4252 coef_node_start = VP9_MV_BITS_0_START;
4253 } else if (coef_count_node_start ==
4254 VP9_MV_BITS_1_COUNT_START) {
4255 if (debug & VP9_DEBUG_MERGE)
4256 pr_info(" # merge_bits_1\n");
4257 coef_node_start = VP9_MV_BITS_1_START;
4258 } else if (coef_count_node_start ==
4259 VP9_MV_CLASS0_HP_0_COUNT_START) {
4260 if (debug & VP9_DEBUG_MERGE)
4261 pr_info(" # merge_class0_hp\n");
4262 coef_node_start = VP9_MV_CLASS0_HP_0_START;
4263 }
4264
4265
4266 den = count[coef_count_node_start] +
4267 count[coef_count_node_start + 1];
4268
4269 prob_32 = prev_prob[coef_node_start / 4 * 2];
4270 prob_res = coef_node_start & 3;
4271 prob_shift = prob_res * 8;
4272 pre_prob = (prob_32 >> prob_shift) & 0xff;
4273
4274 if (den == 0)
4275 new_prob = pre_prob;
4276 else {
4277 m_count = (den < MODE_MV_COUNT_SAT) ?
4278 den : MODE_MV_COUNT_SAT;
4279 get_prob =
4280 clip_prob(
4281 div_r32(((int64_t)count[coef_count_node_start]
4282 * 256 + (den >> 1)),
4283 den));
4284 /*weighted_prob*/
4285 factor = count_to_update_factor[m_count];
4286 new_prob =
4287 ROUND_POWER_OF_TWO(pre_prob * (256 - factor)
4288 + get_prob * factor, 8);
4289 }
4290 cur_prob[coef_node_start / 4 * 2] =
4291 (cur_prob[coef_node_start / 4 * 2] &
4292 (~(0xff << prob_shift)))
4293 | (new_prob << prob_shift);
4294
4295 coef_node_start = coef_node_start + 1;
4296 }
4297 if (debug & VP9_DEBUG_MERGE)
4298 pr_info(" # merge_vp9_inter_mode_tree\n");
4299 coef_node_start = VP9_INTER_MODE_START;
4300 coef_count_node_start = VP9_INTER_MODE_COUNT_START;
4301 for (tree_i = 0; tree_i < 7; tree_i++) {
4302 for (node = 0; node < 3; node++) {
4303 switch (node) {
4304 case 2:
4305 tree_left =
4306 count[coef_count_node_start + 1];
4307 tree_right =
4308 count[coef_count_node_start + 3];
4309 break;
4310 case 1:
4311 tree_left =
4312 count[coef_count_node_start + 0];
4313 tree_right =
4314 count[coef_count_node_start + 1]
4315 + count[coef_count_node_start + 3];
4316 break;
4317 default:
4318 tree_left =
4319 count[coef_count_node_start + 2];
4320 tree_right =
4321 count[coef_count_node_start + 0]
4322 + count[coef_count_node_start + 1]
4323 + count[coef_count_node_start + 3];
4324 break;
4325
4326 }
4327
4328 vp9_tree_merge_probs(prev_prob, cur_prob,
4329 coef_node_start, tree_left, tree_right,
4330 tree_i, node);
4331
4332 coef_node_start = coef_node_start + 1;
4333 }
4334 coef_count_node_start = coef_count_node_start + 4;
4335 }
4336 if (debug & VP9_DEBUG_MERGE)
4337 pr_info(" # merge_vp9_intra_mode_tree\n");
4338 coef_node_start = VP9_IF_Y_MODE_START;
4339 coef_count_node_start = VP9_IF_Y_MODE_COUNT_START;
4340 for (tree_i = 0; tree_i < 14; tree_i++) {
4341 for (node = 0; node < 9; node++) {
4342 switch (node) {
4343 case 8:
4344 tree_left =
4345 count[coef_count_node_start+D153_PRED];
4346 tree_right =
4347 count[coef_count_node_start+D207_PRED];
4348 break;
4349 case 7:
4350 tree_left =
4351 count[coef_count_node_start+D63_PRED];
4352 tree_right =
4353 count[coef_count_node_start+D207_PRED] +
4354 count[coef_count_node_start+D153_PRED];
4355 break;
4356 case 6:
4357 tree_left =
4358 count[coef_count_node_start + D45_PRED];
4359 tree_right =
4360 count[coef_count_node_start+D207_PRED] +
4361 count[coef_count_node_start+D153_PRED] +
4362 count[coef_count_node_start+D63_PRED];
4363 break;
4364 case 5:
4365 tree_left =
4366 count[coef_count_node_start+D135_PRED];
4367 tree_right =
4368 count[coef_count_node_start+D117_PRED];
4369 break;
4370 case 4:
4371 tree_left =
4372 count[coef_count_node_start+H_PRED];
4373 tree_right =
4374 count[coef_count_node_start+D117_PRED] +
4375 count[coef_count_node_start+D135_PRED];
4376 break;
4377 case 3:
4378 tree_left =
4379 count[coef_count_node_start+H_PRED] +
4380 count[coef_count_node_start+D117_PRED] +
4381 count[coef_count_node_start+D135_PRED];
4382 tree_right =
4383 count[coef_count_node_start+D45_PRED] +
4384 count[coef_count_node_start+D207_PRED] +
4385 count[coef_count_node_start+D153_PRED] +
4386 count[coef_count_node_start+D63_PRED];
4387 break;
4388 case 2:
4389 tree_left =
4390 count[coef_count_node_start+V_PRED];
4391 tree_right =
4392 count[coef_count_node_start+H_PRED] +
4393 count[coef_count_node_start+D117_PRED] +
4394 count[coef_count_node_start+D135_PRED] +
4395 count[coef_count_node_start+D45_PRED] +
4396 count[coef_count_node_start+D207_PRED] +
4397 count[coef_count_node_start+D153_PRED] +
4398 count[coef_count_node_start+D63_PRED];
4399 break;
4400 case 1:
4401 tree_left =
4402 count[coef_count_node_start+TM_PRED];
4403 tree_right =
4404 count[coef_count_node_start+V_PRED] +
4405 count[coef_count_node_start+H_PRED] +
4406 count[coef_count_node_start+D117_PRED] +
4407 count[coef_count_node_start+D135_PRED] +
4408 count[coef_count_node_start+D45_PRED] +
4409 count[coef_count_node_start+D207_PRED] +
4410 count[coef_count_node_start+D153_PRED] +
4411 count[coef_count_node_start+D63_PRED];
4412 break;
4413 default:
4414 tree_left =
4415 count[coef_count_node_start+DC_PRED];
4416 tree_right =
4417 count[coef_count_node_start+TM_PRED] +
4418 count[coef_count_node_start+V_PRED] +
4419 count[coef_count_node_start+H_PRED] +
4420 count[coef_count_node_start+D117_PRED] +
4421 count[coef_count_node_start+D135_PRED] +
4422 count[coef_count_node_start+D45_PRED] +
4423 count[coef_count_node_start+D207_PRED] +
4424 count[coef_count_node_start+D153_PRED] +
4425 count[coef_count_node_start+D63_PRED];
4426 break;
4427
4428 }
4429
4430 vp9_tree_merge_probs(prev_prob, cur_prob,
4431 coef_node_start, tree_left, tree_right,
4432 tree_i, node);
4433
4434 coef_node_start = coef_node_start + 1;
4435 }
4436 coef_count_node_start = coef_count_node_start + 10;
4437 }
4438
4439 if (debug & VP9_DEBUG_MERGE)
4440 pr_info(" # merge_vp9_partition_tree\n");
4441 coef_node_start = VP9_PARTITION_P_START;
4442 coef_count_node_start = VP9_PARTITION_P_COUNT_START;
4443 for (tree_i = 0; tree_i < 16; tree_i++) {
4444 for (node = 0; node < 3; node++) {
4445 switch (node) {
4446 case 2:
4447 tree_left =
4448 count[coef_count_node_start + 2];
4449 tree_right =
4450 count[coef_count_node_start + 3];
4451 break;
4452 case 1:
4453 tree_left =
4454 count[coef_count_node_start + 1];
4455 tree_right =
4456 count[coef_count_node_start + 2] +
4457 count[coef_count_node_start + 3];
4458 break;
4459 default:
4460 tree_left =
4461 count[coef_count_node_start + 0];
4462 tree_right =
4463 count[coef_count_node_start + 1] +
4464 count[coef_count_node_start + 2] +
4465 count[coef_count_node_start + 3];
4466 break;
4467
4468 }
4469
4470 vp9_tree_merge_probs(prev_prob, cur_prob,
4471 coef_node_start,
4472 tree_left, tree_right, tree_i, node);
4473
4474 coef_node_start = coef_node_start + 1;
4475 }
4476 coef_count_node_start = coef_count_node_start + 4;
4477 }
4478
4479 if (debug & VP9_DEBUG_MERGE)
4480 pr_info(" # merge_vp9_switchable_interp_tree\n");
4481 coef_node_start = VP9_INTERP_START;
4482 coef_count_node_start = VP9_INTERP_COUNT_START;
4483 for (tree_i = 0; tree_i < 4; tree_i++) {
4484 for (node = 0; node < 2; node++) {
4485 switch (node) {
4486 case 1:
4487 tree_left =
4488 count[coef_count_node_start + 1];
4489 tree_right =
4490 count[coef_count_node_start + 2];
4491 break;
4492 default:
4493 tree_left =
4494 count[coef_count_node_start + 0];
4495 tree_right =
4496 count[coef_count_node_start + 1] +
4497 count[coef_count_node_start + 2];
4498 break;
4499
4500 }
4501
4502 vp9_tree_merge_probs(prev_prob, cur_prob,
4503 coef_node_start,
4504 tree_left, tree_right, tree_i, node);
4505
4506 coef_node_start = coef_node_start + 1;
4507 }
4508 coef_count_node_start = coef_count_node_start + 3;
4509 }
4510
4511 if (debug & VP9_DEBUG_MERGE)
4512 pr_info("# merge_vp9_mv_joint_tree\n");
4513 coef_node_start = VP9_MV_JOINTS_START;
4514 coef_count_node_start = VP9_MV_JOINTS_COUNT_START;
4515 for (tree_i = 0; tree_i < 1; tree_i++) {
4516 for (node = 0; node < 3; node++) {
4517 switch (node) {
4518 case 2:
4519 tree_left =
4520 count[coef_count_node_start + 2];
4521 tree_right =
4522 count[coef_count_node_start + 3];
4523 break;
4524 case 1:
4525 tree_left =
4526 count[coef_count_node_start + 1];
4527 tree_right =
4528 count[coef_count_node_start + 2] +
4529 count[coef_count_node_start + 3];
4530 break;
4531 default:
4532 tree_left =
4533 count[coef_count_node_start + 0];
4534 tree_right =
4535 count[coef_count_node_start + 1] +
4536 count[coef_count_node_start + 2] +
4537 count[coef_count_node_start + 3];
4538 break;
4539 }
4540
4541 vp9_tree_merge_probs(prev_prob, cur_prob,
4542 coef_node_start,
4543 tree_left, tree_right, tree_i, node);
4544
4545 coef_node_start = coef_node_start + 1;
4546 }
4547 coef_count_node_start = coef_count_node_start + 4;
4548 }
4549
4550 for (mvd_i = 0; mvd_i < 2; mvd_i++) {
4551 if (debug & VP9_DEBUG_MERGE)
4552 pr_info(" # merge_vp9_mv_class_tree [%d] -\n", mvd_i);
4553 coef_node_start =
4554 mvd_i ? VP9_MV_CLASSES_1_START : VP9_MV_CLASSES_0_START;
4555 coef_count_node_start =
4556 mvd_i ? VP9_MV_CLASSES_1_COUNT_START
4557 : VP9_MV_CLASSES_0_COUNT_START;
4558 tree_i = 0;
4559 for (node = 0; node < 10; node++) {
4560 switch (node) {
4561 case 9:
4562 tree_left =
4563 count[coef_count_node_start + 9];
4564 tree_right =
4565 count[coef_count_node_start + 10];
4566 break;
4567 case 8:
4568 tree_left =
4569 count[coef_count_node_start + 7];
4570 tree_right =
4571 count[coef_count_node_start + 8];
4572 break;
4573 case 7:
4574 tree_left =
4575 count[coef_count_node_start + 7] +
4576 count[coef_count_node_start + 8];
4577 tree_right =
4578 count[coef_count_node_start + 9] +
4579 count[coef_count_node_start + 10];
4580 break;
4581 case 6:
4582 tree_left =
4583 count[coef_count_node_start + 6];
4584 tree_right =
4585 count[coef_count_node_start + 7] +
4586 count[coef_count_node_start + 8] +
4587 count[coef_count_node_start + 9] +
4588 count[coef_count_node_start + 10];
4589 break;
4590 case 5:
4591 tree_left =
4592 count[coef_count_node_start + 4];
4593 tree_right =
4594 count[coef_count_node_start + 5];
4595 break;
4596 case 4:
4597 tree_left =
4598 count[coef_count_node_start + 4] +
4599 count[coef_count_node_start + 5];
4600 tree_right =
4601 count[coef_count_node_start + 6] +
4602 count[coef_count_node_start + 7] +
4603 count[coef_count_node_start + 8] +
4604 count[coef_count_node_start + 9] +
4605 count[coef_count_node_start + 10];
4606 break;
4607 case 3:
4608 tree_left =
4609 count[coef_count_node_start + 2];
4610 tree_right =
4611 count[coef_count_node_start + 3];
4612 break;
4613 case 2:
4614 tree_left =
4615 count[coef_count_node_start + 2] +
4616 count[coef_count_node_start + 3];
4617 tree_right =
4618 count[coef_count_node_start + 4] +
4619 count[coef_count_node_start + 5] +
4620 count[coef_count_node_start + 6] +
4621 count[coef_count_node_start + 7] +
4622 count[coef_count_node_start + 8] +
4623 count[coef_count_node_start + 9] +
4624 count[coef_count_node_start + 10];
4625 break;
4626 case 1:
4627 tree_left =
4628 count[coef_count_node_start + 1];
4629 tree_right =
4630 count[coef_count_node_start + 2] +
4631 count[coef_count_node_start + 3] +
4632 count[coef_count_node_start + 4] +
4633 count[coef_count_node_start + 5] +
4634 count[coef_count_node_start + 6] +
4635 count[coef_count_node_start + 7] +
4636 count[coef_count_node_start + 8] +
4637 count[coef_count_node_start + 9] +
4638 count[coef_count_node_start + 10];
4639 break;
4640 default:
4641 tree_left =
4642 count[coef_count_node_start + 0];
4643 tree_right =
4644 count[coef_count_node_start + 1] +
4645 count[coef_count_node_start + 2] +
4646 count[coef_count_node_start + 3] +
4647 count[coef_count_node_start + 4] +
4648 count[coef_count_node_start + 5] +
4649 count[coef_count_node_start + 6] +
4650 count[coef_count_node_start + 7] +
4651 count[coef_count_node_start + 8] +
4652 count[coef_count_node_start + 9] +
4653 count[coef_count_node_start + 10];
4654 break;
4655
4656 }
4657
4658 vp9_tree_merge_probs(prev_prob, cur_prob,
4659 coef_node_start, tree_left, tree_right,
4660 tree_i, node);
4661
4662 coef_node_start = coef_node_start + 1;
4663 }
4664
4665 if (debug & VP9_DEBUG_MERGE)
4666 pr_info(" # merge_vp9_mv_class0_tree [%d] -\n", mvd_i);
4667 coef_node_start =
4668 mvd_i ? VP9_MV_CLASS0_1_START : VP9_MV_CLASS0_0_START;
4669 coef_count_node_start =
4670 mvd_i ? VP9_MV_CLASS0_1_COUNT_START :
4671 VP9_MV_CLASS0_0_COUNT_START;
4672 tree_i = 0;
4673 node = 0;
4674 tree_left = count[coef_count_node_start + 0];
4675 tree_right = count[coef_count_node_start + 1];
4676
4677 vp9_tree_merge_probs(prev_prob, cur_prob, coef_node_start,
4678 tree_left, tree_right, tree_i, node);
4679 if (debug & VP9_DEBUG_MERGE)
4680 pr_info(" # merge_vp9_mv_fp_tree_class0_fp [%d] -\n",
4681 mvd_i);
4682 coef_node_start =
4683 mvd_i ? VP9_MV_CLASS0_FP_1_START :
4684 VP9_MV_CLASS0_FP_0_START;
4685 coef_count_node_start =
4686 mvd_i ? VP9_MV_CLASS0_FP_1_COUNT_START :
4687 VP9_MV_CLASS0_FP_0_COUNT_START;
4688 for (tree_i = 0; tree_i < 3; tree_i++) {
4689 for (node = 0; node < 3; node++) {
4690 switch (node) {
4691 case 2:
4692 tree_left =
4693 count[coef_count_node_start + 2];
4694 tree_right =
4695 count[coef_count_node_start + 3];
4696 break;
4697 case 1:
4698 tree_left =
4699 count[coef_count_node_start + 1];
4700 tree_right =
4701 count[coef_count_node_start + 2]
4702 + count[coef_count_node_start + 3];
4703 break;
4704 default:
4705 tree_left =
4706 count[coef_count_node_start + 0];
4707 tree_right =
4708 count[coef_count_node_start + 1]
4709 + count[coef_count_node_start + 2]
4710 + count[coef_count_node_start + 3];
4711 break;
4712
4713 }
4714
4715 vp9_tree_merge_probs(prev_prob, cur_prob,
4716 coef_node_start, tree_left, tree_right,
4717 tree_i, node);
4718
4719 coef_node_start = coef_node_start + 1;
4720 }
4721 coef_count_node_start = coef_count_node_start + 4;
4722 }
4723
4724 } /* for mvd_i (mvd_y or mvd_x)*/
4725}
4726
4727}
4728
4729static bool v4l_is_there_vframe_bound(struct VP9Decoder_s *pbi)
4730{
4731 int i;
4732 struct VP9_Common_s *const cm = &pbi->common;
4733 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
4734
4735 for (i = 0; i < pbi->used_buf_num; ++i) {
4736 if (frame_bufs[i].buf.vframe_bound)
4737 return true;
4738 }
4739
4740 return false;
4741}
4742
4743static void v4l_mmu_buffer_release(struct VP9Decoder_s *pbi)
4744{
4745 struct VP9_Common_s *const cm = &pbi->common;
4746 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
4747 int i;
4748
4749 /* release workspace */
4750 if (pbi->bmmu_box)
4751 decoder_bmmu_box_free_idx(pbi->bmmu_box,
4752 WORK_SPACE_BUF_ID);
4753 /*
4754 * it's only when vframe get back to driver, right now we can be sure
4755 * that vframe and fd are related. if the playback exits, the capture
4756 * requires the upper app to release when the fd is closed, and others
4757 * buffers drivers are released by driver.
4758 */
4759 for (i = 0; i < pbi->used_buf_num; ++i) {
4760 if (!frame_bufs[i].buf.vframe_bound) {
4761 if (pbi->bmmu_box)
4762 decoder_bmmu_box_free_idx(pbi->bmmu_box,
4763 HEADER_BUFFER_IDX(i));
4764 if (pbi->mmu_box)
4765 decoder_mmu_box_free_idx(pbi->mmu_box, i);
4766
4767 vp9_print(pbi, PRINT_FLAG_V4L_DETAIL,
4768 "%s free buffer[%d], bmmu_box: %p, mmu_box: %p\n",
4769 __func__, i, pbi->bmmu_box, pbi->mmu_box);
4770 }
4771 }
4772}
4773
4774static void uninit_mmu_buffers(struct VP9Decoder_s *pbi)
4775{
4776#ifndef MV_USE_FIXED_BUF
4777 dealloc_mv_bufs(pbi);
4778#endif
4779 if (pbi->is_used_v4l &&
4780 v4l_is_there_vframe_bound(pbi)) {
4781 if (get_double_write_mode(pbi) != 0x10) {
4782 v4l_mmu_buffer_release(pbi);
4783 return;
4784 }
4785 }
4786
4787 if (pbi->mmu_box)
4788 decoder_mmu_box_free(pbi->mmu_box);
4789 pbi->mmu_box = NULL;
4790
4791 if (pbi->bmmu_box)
4792 decoder_bmmu_box_free(pbi->bmmu_box);
4793 pbi->bmmu_box = NULL;
4794}
4795
4796static int calc_luc_quantity(u32 w, u32 h)
4797{
4798 int lcu_size = 64; /*fixed 64*/
4799 int pic_width_64 = (w + 63) & (~0x3f);
4800 int pic_height_32 = (h + 31) & (~0x1f);
4801 int pic_width_lcu = (pic_width_64 % lcu_size) ?
4802 pic_width_64 / lcu_size + 1 : pic_width_64 / lcu_size;
4803 int pic_height_lcu = (pic_height_32 % lcu_size) ?
4804 pic_height_32 / lcu_size + 1 : pic_height_32 / lcu_size;
4805
4806 return pic_width_lcu * pic_height_lcu;
4807}
4808
4809static int v4l_alloc_and_config_pic(struct VP9Decoder_s *pbi,
4810 struct PIC_BUFFER_CONFIG_s *pic)
4811{
4812 int ret = -1;
4813 int i = pic->index;
4814 int dw_mode = get_double_write_mode_init(pbi);
4815 int lcu_total = calc_luc_quantity(pbi->frame_width, pbi->frame_height);
4816#ifdef MV_USE_FIXED_BUF
4817 u32 mpred_mv_end = pbi->work_space_buf->mpred_mv.buf_start +
4818 pbi->work_space_buf->mpred_mv.buf_size;
4819#endif
4820 struct vdec_v4l2_buffer *fb = NULL;
4821
4822 if (i < 0)
4823 return ret;
4824
4825 ret = vdec_v4l_get_buffer(pbi->v4l2_ctx, &fb);
4826 if (ret < 0) {
4827 vp9_print(pbi, 0, "[%d] VP9 get buffer fail.\n",
4828 ((struct aml_vcodec_ctx *) (pbi->v4l2_ctx))->id);
4829 return ret;
4830 }
4831
4832 if (pbi->mmu_enable) {
4833 pbi->m_BUF[i].header_addr = decoder_bmmu_box_get_phy_addr(
4834 pbi->bmmu_box, HEADER_BUFFER_IDX(i));
4835 if (debug & VP9_DEBUG_BUFMGR_MORE) {
4836 pr_info("MMU header_adr %d: %ld\n",
4837 i, pbi->m_BUF[i].header_addr);
4838 }
4839 }
4840
4841#ifdef MV_USE_FIXED_BUF
4842 if ((pbi->work_space_buf->mpred_mv.buf_start +
4843 (((i + 1) * lcu_total) * MV_MEM_UNIT))
4844 <= mpred_mv_end) {
4845#endif
4846 pbi->m_BUF[i].v4l_ref_buf_addr = (ulong)fb;
4847 pic->cma_alloc_addr = fb->m.mem[0].addr;
4848 if (fb->num_planes == 1) {
4849 pbi->m_BUF[i].start_adr = fb->m.mem[0].addr;
4850 pbi->m_BUF[i].luma_size = fb->m.mem[0].offset;
4851 pbi->m_BUF[i].size = fb->m.mem[0].size;
4852 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
4853 pic->dw_y_adr = pbi->m_BUF[i].start_adr;
4854 pic->dw_u_v_adr = pic->dw_y_adr + pbi->m_BUF[i].luma_size;
4855 } else if (fb->num_planes == 2) {
4856 pbi->m_BUF[i].start_adr = fb->m.mem[0].addr;
4857 pbi->m_BUF[i].size = fb->m.mem[0].size;
4858 pbi->m_BUF[i].chroma_addr = fb->m.mem[1].addr;
4859 pbi->m_BUF[i].chroma_size = fb->m.mem[1].size;
4860 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
4861 fb->m.mem[1].bytes_used = fb->m.mem[1].size;
4862 pic->dw_y_adr = pbi->m_BUF[i].start_adr;
4863 pic->dw_u_v_adr = pbi->m_BUF[i].chroma_addr;
4864 }
4865
4866 /* config frame buffer */
4867 if (pbi->mmu_enable)
4868 pic->header_adr = pbi->m_BUF[i].header_addr;
4869
4870 pic->BUF_index = i;
4871 pic->lcu_total = lcu_total;
4872 pic->mc_canvas_y = pic->index;
4873 pic->mc_canvas_u_v = pic->index;
4874
4875 if (dw_mode & 0x10) {
4876 pic->mc_canvas_y = (pic->index << 1);
4877 pic->mc_canvas_u_v = (pic->index << 1) + 1;
4878 }
4879
4880#ifdef MV_USE_FIXED_BUF
4881 pic->mpred_mv_wr_start_addr =
4882 pbi->work_space_buf->mpred_mv.buf_start +
4883 ((pic->index * lcu_total) * MV_MEM_UNIT);
4884#endif
4885 if (debug) {
4886 pr_info("%s index %d BUF_index %d ",
4887 __func__, pic->index,
4888 pic->BUF_index);
4889 pr_info("comp_body_size %x comp_buf_size %x ",
4890 pic->comp_body_size,
4891 pic->buf_size);
4892 pr_info("mpred_mv_wr_start_adr %ld\n",
4893 pic->mpred_mv_wr_start_addr);
4894 pr_info("dw_y_adr %d, pic_config->dw_u_v_adr =%d\n",
4895 pic->dw_y_adr,
4896 pic->dw_u_v_adr);
4897 }
4898#ifdef MV_USE_FIXED_BUF
4899 }
4900#endif
4901 return ret;
4902}
4903
4904static int config_pic(struct VP9Decoder_s *pbi,
4905 struct PIC_BUFFER_CONFIG_s *pic_config)
4906{
4907 int ret = -1;
4908 int i;
4909 int pic_width = pbi->init_pic_w;
4910 int pic_height = pbi->init_pic_h;
4911 int lcu_size = 64; /*fixed 64*/
4912 int pic_width_64 = (pic_width + 63) & (~0x3f);
4913 int pic_height_32 = (pic_height + 31) & (~0x1f);
4914 int pic_width_lcu = (pic_width_64 % lcu_size) ?
4915 pic_width_64 / lcu_size + 1
4916 : pic_width_64 / lcu_size;
4917 int pic_height_lcu = (pic_height_32 % lcu_size) ?
4918 pic_height_32 / lcu_size + 1
4919 : pic_height_32 / lcu_size;
4920 int lcu_total = pic_width_lcu * pic_height_lcu;
4921#ifdef MV_USE_FIXED_BUF
4922 u32 mpred_mv_end = pbi->work_space_buf->mpred_mv.buf_start +
4923 pbi->work_space_buf->mpred_mv.buf_size;
4924#endif
4925 u32 y_adr = 0;
4926 int buf_size = 0;
4927
4928 int losless_comp_header_size =
4929 compute_losless_comp_header_size(pic_width,
4930 pic_height);
4931 int losless_comp_body_size = compute_losless_comp_body_size(pic_width,
4932 pic_height, buf_alloc_depth == 10);
4933 int mc_buffer_size = losless_comp_header_size + losless_comp_body_size;
4934 int mc_buffer_size_h = (mc_buffer_size + 0xffff) >> 16;
4935 int mc_buffer_size_u_v = 0;
4936 int mc_buffer_size_u_v_h = 0;
4937 int dw_mode = get_double_write_mode_init(pbi);
4938
4939 pbi->lcu_total = lcu_total;
4940
4941 if (dw_mode) {
4942 int pic_width_dw = pic_width /
4943 get_double_write_ratio(pbi, dw_mode);
4944 int pic_height_dw = pic_height /
4945 get_double_write_ratio(pbi, dw_mode);
4946
4947 int pic_width_64_dw = (pic_width_dw + 63) & (~0x3f);
4948 int pic_height_32_dw = (pic_height_dw + 31) & (~0x1f);
4949 int pic_width_lcu_dw = (pic_width_64_dw % lcu_size) ?
4950 pic_width_64_dw / lcu_size + 1
4951 : pic_width_64_dw / lcu_size;
4952 int pic_height_lcu_dw = (pic_height_32_dw % lcu_size) ?
4953 pic_height_32_dw / lcu_size + 1
4954 : pic_height_32_dw / lcu_size;
4955 int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw;
4956 mc_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2;
4957 mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff) >> 16;
4958 /*64k alignment*/
4959 buf_size = ((mc_buffer_size_u_v_h << 16) * 3);
4960 buf_size = ((buf_size + 0xffff) >> 16) << 16;
4961 }
4962
4963 if (mc_buffer_size & 0xffff) /*64k alignment*/
4964 mc_buffer_size_h += 1;
4965 if ((!pbi->mmu_enable) && ((dw_mode & 0x10) == 0))
4966 buf_size += (mc_buffer_size_h << 16);
4967
4968 if (pbi->mmu_enable) {
4969 pic_config->header_adr = decoder_bmmu_box_get_phy_addr(
4970 pbi->bmmu_box, HEADER_BUFFER_IDX(pic_config->index));
4971
4972 if (debug & VP9_DEBUG_BUFMGR_MORE) {
4973 pr_info("MMU header_adr %d: %ld\n",
4974 pic_config->index, pic_config->header_adr);
4975 }
4976 }
4977
4978 i = pic_config->index;
4979#ifdef MV_USE_FIXED_BUF
4980 if ((pbi->work_space_buf->mpred_mv.buf_start +
4981 (((i + 1) * lcu_total) * MV_MEM_UNIT))
4982 <= mpred_mv_end
4983 ) {
4984#endif
4985 if (buf_size > 0) {
4986 ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box,
4987 VF_BUFFER_IDX(i),
4988 buf_size, DRIVER_NAME,
4989 &pic_config->cma_alloc_addr);
4990 if (ret < 0) {
4991 pr_info(
4992 "decoder_bmmu_box_alloc_buf_phy idx %d size %d fail\n",
4993 VF_BUFFER_IDX(i),
4994 buf_size
4995 );
4996 return ret;
4997 }
4998
4999 if (pic_config->cma_alloc_addr)
5000 y_adr = pic_config->cma_alloc_addr;
5001 else {
5002 pr_info(
5003 "decoder_bmmu_box_alloc_buf_phy idx %d size %d return null\n",
5004 VF_BUFFER_IDX(i),
5005 buf_size
5006 );
5007 return -1;
5008 }
5009 }
5010 {
5011 /*ensure get_pic_by_POC()
5012 not get the buffer not decoded*/
5013 pic_config->BUF_index = i;
5014 pic_config->lcu_total = lcu_total;
5015
5016 pic_config->comp_body_size = losless_comp_body_size;
5017 pic_config->buf_size = buf_size;
5018
5019 pic_config->mc_canvas_y = pic_config->index;
5020 pic_config->mc_canvas_u_v = pic_config->index;
5021 if (dw_mode & 0x10) {
5022 pic_config->dw_y_adr = y_adr;
5023 pic_config->dw_u_v_adr = y_adr +
5024 ((mc_buffer_size_u_v_h << 16) << 1);
5025
5026 pic_config->mc_canvas_y =
5027 (pic_config->index << 1);
5028 pic_config->mc_canvas_u_v =
5029 (pic_config->index << 1) + 1;
5030 } else if (dw_mode) {
5031 pic_config->dw_y_adr = y_adr;
5032 pic_config->dw_u_v_adr = pic_config->dw_y_adr +
5033 ((mc_buffer_size_u_v_h << 16) << 1);
5034 }
5035#ifdef MV_USE_FIXED_BUF
5036 pic_config->mpred_mv_wr_start_addr =
5037 pbi->work_space_buf->mpred_mv.buf_start +
5038 ((pic_config->index * lcu_total)
5039 * MV_MEM_UNIT);
5040#endif
5041 if (debug) {
5042 pr_info
5043 ("%s index %d BUF_index %d ",
5044 __func__, pic_config->index,
5045 pic_config->BUF_index);
5046 pr_info
5047 ("comp_body_size %x comp_buf_size %x ",
5048 pic_config->comp_body_size,
5049 pic_config->buf_size);
5050 pr_info
5051 ("mpred_mv_wr_start_adr %ld\n",
5052 pic_config->mpred_mv_wr_start_addr);
5053 pr_info("dw_y_adr %d, pic_config->dw_u_v_adr =%d\n",
5054 pic_config->dw_y_adr,
5055 pic_config->dw_u_v_adr);
5056 }
5057 ret = 0;
5058 }
5059#ifdef MV_USE_FIXED_BUF
5060 }
5061#endif
5062 return ret;
5063}
5064
5065static int vvp9_mmu_compress_header_size(struct VP9Decoder_s *pbi)
5066{
5067 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
5068 IS_8K_SIZE(pbi->max_pic_w, pbi->max_pic_h))
5069 return (MMU_COMPRESS_8K_HEADER_SIZE);
5070
5071 return (MMU_COMPRESS_HEADER_SIZE);
5072}
5073
5074/*#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)*/
5075static int vvp9_frame_mmu_map_size(struct VP9Decoder_s *pbi)
5076{
5077 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
5078 IS_8K_SIZE(pbi->max_pic_w, pbi->max_pic_h))
5079 return (MAX_FRAME_8K_NUM * 4);
5080
5081 return (MAX_FRAME_4K_NUM * 4);
5082}
5083
5084static void init_pic_list(struct VP9Decoder_s *pbi)
5085{
5086 int i;
5087 struct VP9_Common_s *cm = &pbi->common;
5088 struct PIC_BUFFER_CONFIG_s *pic_config;
5089 u32 header_size;
5090 struct vdec_s *vdec = hw_to_vdec(pbi);
5091
5092 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
5093 header_size = vvp9_mmu_compress_header_size(pbi);
5094 /*alloc VP9 compress header first*/
5095 for (i = 0; i < pbi->used_buf_num; i++) {
5096 unsigned long buf_addr;
5097 if (decoder_bmmu_box_alloc_buf_phy
5098 (pbi->bmmu_box,
5099 HEADER_BUFFER_IDX(i), header_size,
5100 DRIVER_HEADER_NAME,
5101 &buf_addr) < 0) {
5102 pr_info("%s malloc compress header failed %d\n",
5103 DRIVER_HEADER_NAME, i);
5104 pbi->fatal_error |= DECODER_FATAL_ERROR_NO_MEM;
5105 return;
5106 }
5107 }
5108 }
5109 for (i = 0; i < pbi->used_buf_num; i++) {
5110 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
5111 pic_config->index = i;
5112 pic_config->BUF_index = -1;
5113 pic_config->mv_buf_index = -1;
5114 if (vdec->parallel_dec == 1) {
5115 pic_config->y_canvas_index = -1;
5116 pic_config->uv_canvas_index = -1;
5117 }
5118 pic_config->y_crop_width = pbi->init_pic_w;
5119 pic_config->y_crop_height = pbi->init_pic_h;
5120 pic_config->double_write_mode = get_double_write_mode(pbi);
5121
5122 if (!pbi->is_used_v4l) {
5123 if (config_pic(pbi, pic_config) < 0) {
5124 if (debug)
5125 pr_info("Config_pic %d fail\n",
5126 pic_config->index);
5127 pic_config->index = -1;
5128 break;
5129 }
5130
5131 if (pic_config->double_write_mode) {
5132 set_canvas(pbi, pic_config);
5133 }
5134 }
5135 }
5136 for (; i < pbi->used_buf_num; i++) {
5137 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
5138 pic_config->index = -1;
5139 pic_config->BUF_index = -1;
5140 pic_config->mv_buf_index = -1;
5141 if (vdec->parallel_dec == 1) {
5142 pic_config->y_canvas_index = -1;
5143 pic_config->uv_canvas_index = -1;
5144 }
5145 }
5146 pr_info("%s ok, used_buf_num = %d\n",
5147 __func__, pbi->used_buf_num);
5148}
5149
5150static void init_pic_list_hw(struct VP9Decoder_s *pbi)
5151{
5152 int i;
5153 struct VP9_Common_s *cm = &pbi->common;
5154 struct PIC_BUFFER_CONFIG_s *pic_config;
5155 /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x0);*/
5156 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
5157 (0x1 << 1) | (0x1 << 2));
5158
5159
5160 for (i = 0; i < pbi->used_buf_num; i++) {
5161 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
5162 if (pic_config->index < 0)
5163 break;
5164
5165 if (pbi->mmu_enable && ((pic_config->double_write_mode & 0x10) == 0)) {
5166
5167 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
5168 pic_config->header_adr >> 5);
5169 } else {
5170 /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
5171 * pic_config->mc_y_adr
5172 * | (pic_config->mc_canvas_y << 8) | 0x1);
5173 */
5174 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
5175 pic_config->dw_y_adr >> 5);
5176 }
5177#ifndef LOSLESS_COMPRESS_MODE
5178 /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
5179 * pic_config->mc_u_v_adr
5180 * | (pic_config->mc_canvas_u_v << 8)| 0x1);
5181 */
5182 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
5183 pic_config->header_adr >> 5);
5184#else
5185 if (pic_config->double_write_mode & 0x10) {
5186 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
5187 pic_config->dw_u_v_adr >> 5);
5188 }
5189#endif
5190 }
5191 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
5192
5193 /*Zero out canvas registers in IPP -- avoid simulation X*/
5194 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
5195 (0 << 8) | (0 << 1) | 1);
5196 for (i = 0; i < 32; i++)
5197 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
5198}
5199
5200
5201static void dump_pic_list(struct VP9Decoder_s *pbi)
5202{
5203 struct VP9_Common_s *const cm = &pbi->common;
5204 struct PIC_BUFFER_CONFIG_s *pic_config;
5205 int i;
5206 for (i = 0; i < FRAME_BUFFERS; i++) {
5207 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
5208 vp9_print(pbi, 0,
5209 "Buf(%d) index %d mv_buf_index %d ref_count %d vf_ref %d dec_idx %d slice_type %d w/h %d/%d adr%ld\n",
5210 i,
5211 pic_config->index,
5212#ifndef MV_USE_FIXED_BUF
5213 pic_config->mv_buf_index,
5214#else
5215 -1,
5216#endif
5217 cm->buffer_pool->
5218 frame_bufs[i].ref_count,
5219 pic_config->vf_ref,
5220 pic_config->decode_idx,
5221 pic_config->slice_type,
5222 pic_config->y_crop_width,
5223 pic_config->y_crop_height,
5224 pic_config->cma_alloc_addr
5225 );
5226 }
5227 return;
5228}
5229
5230static int config_pic_size(struct VP9Decoder_s *pbi, unsigned short bit_depth)
5231{
5232#ifdef LOSLESS_COMPRESS_MODE
5233 unsigned int data32;
5234#endif
5235 int losless_comp_header_size, losless_comp_body_size;
5236 struct VP9_Common_s *cm = &pbi->common;
5237 struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf;
5238
5239 frame_width = cur_pic_config->y_crop_width;
5240 frame_height = cur_pic_config->y_crop_height;
5241 cur_pic_config->bit_depth = bit_depth;
5242 cur_pic_config->double_write_mode = get_double_write_mode(pbi);
5243 losless_comp_header_size =
5244 compute_losless_comp_header_size(cur_pic_config->y_crop_width,
5245 cur_pic_config->y_crop_height);
5246 losless_comp_body_size =
5247 compute_losless_comp_body_size(cur_pic_config->y_crop_width,
5248 cur_pic_config->y_crop_height, (bit_depth == VPX_BITS_10));
5249 cur_pic_config->comp_body_size = losless_comp_body_size;
5250#ifdef LOSLESS_COMPRESS_MODE
5251 data32 = READ_VREG(HEVC_SAO_CTRL5);
5252 if (bit_depth == VPX_BITS_10)
5253 data32 &= ~(1 << 9);
5254 else
5255 data32 |= (1 << 9);
5256
5257 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5258
5259 if (pbi->mmu_enable) {
5260 /*bit[4] : paged_mem_mode*/
5261 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
5262 } else {
5263 /*bit[3] smem mdoe*/
5264 if (bit_depth == VPX_BITS_10)
5265 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0 << 3));
5266 else
5267 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (1 << 3));
5268 }
5269 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_SM1)
5270 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, (losless_comp_body_size >> 5));
5271 /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,(0xff<<20) | (0xff<<10) | 0xff);*/
5272 WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size);
5273 WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size);
5274 WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size);
5275 if (get_double_write_mode(pbi) & 0x10)
5276 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5277#else
5278 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5279#endif
5280 return 0;
5281}
5282
5283static int config_mc_buffer(struct VP9Decoder_s *pbi, unsigned short bit_depth)
5284{
5285 int i;
5286 struct VP9_Common_s *cm = &pbi->common;
5287 struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf;
5288 uint8_t scale_enable = 0;
5289
5290 if (debug&VP9_DEBUG_BUFMGR_MORE)
5291 pr_info("config_mc_buffer entered .....\n");
5292
5293 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
5294 (0 << 8) | (0 << 1) | 1);
5295 for (i = 0; i < REFS_PER_FRAME; ++i) {
5296 struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf;
5297 if (!pic_config)
5298 continue;
5299 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
5300 (pic_config->mc_canvas_u_v << 16)
5301 | (pic_config->mc_canvas_u_v << 8)
5302 | pic_config->mc_canvas_y);
5303 if (debug & VP9_DEBUG_BUFMGR_MORE)
5304 pr_info("refid %x mc_canvas_u_v %x mc_canvas_y %x\n",
5305 i, pic_config->mc_canvas_u_v,
5306 pic_config->mc_canvas_y);
5307 }
5308 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
5309 (16 << 8) | (0 << 1) | 1);
5310 for (i = 0; i < REFS_PER_FRAME; ++i) {
5311 struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf;
5312 if (!pic_config)
5313 continue;
5314 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
5315 (pic_config->mc_canvas_u_v << 16)
5316 | (pic_config->mc_canvas_u_v << 8)
5317 | pic_config->mc_canvas_y);
5318 }
5319
5320 /*auto_inc start index:0 field:0*/
5321 WRITE_VREG(VP9D_MPP_REFINFO_TBL_ACCCONFIG, 0x1 << 2);
5322 /*index 0:last 1:golden 2:altref*/
5323 for (i = 0; i < REFS_PER_FRAME; i++) {
5324 int ref_pic_body_size;
5325 struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf;
5326 if (!pic_config)
5327 continue;
5328 WRITE_VREG(VP9D_MPP_REFINFO_DATA, pic_config->y_crop_width);
5329 WRITE_VREG(VP9D_MPP_REFINFO_DATA, pic_config->y_crop_height);
5330
5331 if (pic_config->y_crop_width != cur_pic_config->y_crop_width ||
5332 pic_config->y_crop_height != cur_pic_config->y_crop_height) {
5333 scale_enable |= (1 << i);
5334 }
5335 ref_pic_body_size =
5336 compute_losless_comp_body_size(pic_config->y_crop_width,
5337 pic_config->y_crop_height, (bit_depth == VPX_BITS_10));
5338 WRITE_VREG(VP9D_MPP_REFINFO_DATA,
5339 (pic_config->y_crop_width << 14)
5340 / cur_pic_config->y_crop_width);
5341 WRITE_VREG(VP9D_MPP_REFINFO_DATA,
5342 (pic_config->y_crop_height << 14)
5343 / cur_pic_config->y_crop_height);
5344 if (pbi->mmu_enable)
5345 WRITE_VREG(VP9D_MPP_REFINFO_DATA, 0);
5346 else
5347 WRITE_VREG(VP9D_MPP_REFINFO_DATA, ref_pic_body_size >> 5);
5348 }
5349 WRITE_VREG(VP9D_MPP_REF_SCALE_ENBL, scale_enable);
5350 return 0;
5351}
5352
5353static void clear_mpred_hw(struct VP9Decoder_s *pbi)
5354{
5355 unsigned int data32;
5356
5357 data32 = READ_VREG(HEVC_MPRED_CTRL4);
5358 data32 &= (~(1 << 6));
5359 WRITE_VREG(HEVC_MPRED_CTRL4, data32);
5360}
5361
5362static void config_mpred_hw(struct VP9Decoder_s *pbi)
5363{
5364 struct VP9_Common_s *cm = &pbi->common;
5365 struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf;
5366 struct PIC_BUFFER_CONFIG_s *last_frame_pic_config =
5367 &cm->prev_frame->buf;
5368
5369 unsigned int data32;
5370 int mpred_curr_lcu_x;
5371 int mpred_curr_lcu_y;
5372 int mpred_mv_rd_end_addr;
5373
5374
5375 mpred_mv_rd_end_addr = last_frame_pic_config->mpred_mv_wr_start_addr
5376 + (last_frame_pic_config->lcu_total * MV_MEM_UNIT);
5377
5378 data32 = READ_VREG(HEVC_MPRED_CURR_LCU);
5379 mpred_curr_lcu_x = data32 & 0xffff;
5380 mpred_curr_lcu_y = (data32 >> 16) & 0xffff;
5381
5382 if (debug & VP9_DEBUG_BUFMGR)
5383 pr_info("cur pic_config index %d col pic_config index %d\n",
5384 cur_pic_config->index, last_frame_pic_config->index);
5385 WRITE_VREG(HEVC_MPRED_CTRL3, 0x24122412);
5386 WRITE_VREG(HEVC_MPRED_ABV_START_ADDR,
5387 pbi->work_space_buf->mpred_above.buf_start);
5388
5389 data32 = READ_VREG(HEVC_MPRED_CTRL4);
5390
5391 data32 &= (~(1 << 6));
5392 data32 |= (cm->use_prev_frame_mvs << 6);
5393 WRITE_VREG(HEVC_MPRED_CTRL4, data32);
5394
5395 WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR,
5396 cur_pic_config->mpred_mv_wr_start_addr);
5397 WRITE_VREG(HEVC_MPRED_MV_WPTR, cur_pic_config->mpred_mv_wr_start_addr);
5398
5399 WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR,
5400 last_frame_pic_config->mpred_mv_wr_start_addr);
5401 WRITE_VREG(HEVC_MPRED_MV_RPTR,
5402 last_frame_pic_config->mpred_mv_wr_start_addr);
5403 /*data32 = ((pbi->lcu_x_num - pbi->tile_width_lcu)*MV_MEM_UNIT);*/
5404 /*WRITE_VREG(HEVC_MPRED_MV_WR_ROW_JUMP,data32);*/
5405 /*WRITE_VREG(HEVC_MPRED_MV_RD_ROW_JUMP,data32);*/
5406 WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR, mpred_mv_rd_end_addr);
5407
5408}
5409
5410static void config_sao_hw(struct VP9Decoder_s *pbi, union param_u *params)
5411{
5412 struct VP9_Common_s *cm = &pbi->common;
5413 struct PIC_BUFFER_CONFIG_s *pic_config = &cm->cur_frame->buf;
5414
5415 unsigned int data32;
5416 int lcu_size = 64;
5417 int mc_buffer_size_u_v =
5418 pic_config->lcu_total * lcu_size*lcu_size/2;
5419 int mc_buffer_size_u_v_h =
5420 (mc_buffer_size_u_v + 0xffff) >> 16;/*64k alignment*/
5421 struct aml_vcodec_ctx * v4l2_ctx = pbi->v4l2_ctx;
5422
5423 if (get_double_write_mode(pbi)) {
5424 WRITE_VREG(HEVC_SAO_Y_START_ADDR, pic_config->dw_y_adr);
5425 WRITE_VREG(HEVC_SAO_C_START_ADDR, pic_config->dw_u_v_adr);
5426 WRITE_VREG(HEVC_SAO_Y_WPTR, pic_config->dw_y_adr);
5427 WRITE_VREG(HEVC_SAO_C_WPTR, pic_config->dw_u_v_adr);
5428 } else {
5429 WRITE_VREG(HEVC_SAO_Y_START_ADDR, 0xffffffff);
5430 WRITE_VREG(HEVC_SAO_C_START_ADDR, 0xffffffff);
5431 }
5432 if (pbi->mmu_enable)
5433 WRITE_VREG(HEVC_CM_HEADER_START_ADDR, pic_config->header_adr);
5434
5435 data32 = (mc_buffer_size_u_v_h << 16) << 1;
5436 /*pr_info("data32=%x,mc_buffer_size_u_v_h=%x,lcu_total=%x\n",
5437 * data32, mc_buffer_size_u_v_h, pic_config->lcu_total);
5438 */
5439 WRITE_VREG(HEVC_SAO_Y_LENGTH, data32);
5440
5441 data32 = (mc_buffer_size_u_v_h << 16);
5442 WRITE_VREG(HEVC_SAO_C_LENGTH, data32);
5443
5444#ifdef VP9_10B_NV21
5445#ifdef DOS_PROJECT
5446 data32 = READ_VREG(HEVC_SAO_CTRL1);
5447 data32 &= (~0x3000);
5448 /*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/
5449 data32 |= (pbi->mem_map_mode << 12);
5450 data32 &= (~0x3);
5451 data32 |= 0x1; /* [1]:dw_disable [0]:cm_disable*/
5452 WRITE_VREG(HEVC_SAO_CTRL1, data32);
5453 /*[23:22] dw_v1_ctrl [21:20] dw_v0_ctrl [19:18] dw_h1_ctrl
5454 * [17:16] dw_h0_ctrl
5455 */
5456 data32 = READ_VREG(HEVC_SAO_CTRL5);
5457 /*set them all 0 for H265_NV21 (no down-scale)*/
5458 data32 &= ~(0xff << 16);
5459 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5460 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
5461 data32 &= (~0x30);
5462 /*[5:4] address_format 00:linear 01:32x32 10:64x32*/
5463 data32 |= (pbi->mem_map_mode << 4);
5464 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
5465#else
5466 /*m8baby test1902*/
5467 data32 = READ_VREG(HEVC_SAO_CTRL1);
5468 data32 &= (~0x3000);
5469 /*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/
5470 data32 |= (pbi->mem_map_mode << 12);
5471 data32 &= (~0xff0);
5472 /*data32 |= 0x670;*/ /*Big-Endian per 64-bit*/
5473 data32 |= 0x880; /*.Big-Endian per 64-bit */
5474 data32 &= (~0x3);
5475 data32 |= 0x1; /*[1]:dw_disable [0]:cm_disable*/
5476 WRITE_VREG(HEVC_SAO_CTRL1, data32);
5477 /* [23:22] dw_v1_ctrl [21:20] dw_v0_ctrl
5478 *[19:18] dw_h1_ctrl [17:16] dw_h0_ctrl
5479 */
5480 data32 = READ_VREG(HEVC_SAO_CTRL5);
5481 /* set them all 0 for H265_NV21 (no down-scale)*/
5482 data32 &= ~(0xff << 16);
5483 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5484
5485 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
5486 data32 &= (~0x30);
5487 /*[5:4] address_format 00:linear 01:32x32 10:64x32*/
5488 data32 |= (pbi->mem_map_mode << 4);
5489 data32 &= (~0xF);
5490 data32 |= 0x8; /*Big-Endian per 64-bit*/
5491 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
5492#endif
5493#else
5494 data32 = READ_VREG(HEVC_SAO_CTRL1);
5495 data32 &= (~0x3000);
5496 data32 |= (pbi->mem_map_mode <<
5497 12);
5498
5499/* [13:12] axi_aformat, 0-Linear,
5500 * 1-32x32, 2-64x32
5501 */
5502 data32 &= (~0xff0);
5503 /* data32 |= 0x670; // Big-Endian per 64-bit */
5504 data32 |= endian; /* Big-Endian per 64-bit */
5505 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
5506 data32 &= (~0x3); /*[1]:dw_disable [0]:cm_disable*/
5507 if (get_double_write_mode(pbi) == 0)
5508 data32 |= 0x2; /*disable double write*/
5509 else if (get_double_write_mode(pbi) & 0x10)
5510 data32 |= 0x1; /*disable cm*/
5511 } else { /* >= G12A dw write control */
5512 unsigned int data;
5513 data = READ_VREG(HEVC_DBLK_CFGB);
5514 data &= (~0x300); /*[8]:first write enable (compress) [9]:double write enable (uncompress)*/
5515 if (get_double_write_mode(pbi) == 0)
5516 data |= (0x1 << 8); /*enable first write*/
5517 else if (get_double_write_mode(pbi) & 0x10)
5518 data |= (0x1 << 9); /*double write only*/
5519 else
5520 data |= ((0x1 << 8) |(0x1 << 9));
5521 WRITE_VREG(HEVC_DBLK_CFGB, data);
5522 }
5523
5524 /* swap uv */
5525 if (pbi->is_used_v4l) {
5526 if ((v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21) ||
5527 (v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
5528 data32 &= ~(1 << 8); /* NV21 */
5529 else
5530 data32 |= (1 << 8); /* NV12 */
5531 }
5532
5533 /*
5534 * [31:24] ar_fifo1_axi_thred
5535 * [23:16] ar_fifo0_axi_thred
5536 * [15:14] axi_linealign, 0-16bytes, 1-32bytes, 2-64bytes
5537 * [13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32
5538 * [11:08] axi_lendian_C
5539 * [07:04] axi_lendian_Y
5540 * [3] reserved
5541 * [2] clk_forceon
5542 * [1] dw_disable:disable double write output
5543 * [0] cm_disable:disable compress output
5544 */
5545 WRITE_VREG(HEVC_SAO_CTRL1, data32);
5546
5547 if (get_double_write_mode(pbi) & 0x10) {
5548 /* [23:22] dw_v1_ctrl
5549 *[21:20] dw_v0_ctrl
5550 *[19:18] dw_h1_ctrl
5551 *[17:16] dw_h0_ctrl
5552 */
5553 data32 = READ_VREG(HEVC_SAO_CTRL5);
5554 /*set them all 0 for H265_NV21 (no down-scale)*/
5555 data32 &= ~(0xff << 16);
5556 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5557 } else {
5558 data32 = READ_VREG(HEVC_SAO_CTRL5);
5559 data32 &= (~(0xff << 16));
5560 if (get_double_write_mode(pbi) == 2 ||
5561 get_double_write_mode(pbi) == 3)
5562 data32 |= (0xff<<16);
5563 else if (get_double_write_mode(pbi) == 4)
5564 data32 |= (0x33<<16);
5565 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5566 }
5567
5568 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
5569 data32 &= (~0x30);
5570 /* [5:4] -- address_format 00:linear 01:32x32 10:64x32 */
5571 data32 |= (pbi->mem_map_mode <<
5572 4);
5573 data32 &= (~0xF);
5574 data32 |= 0xf; /* valid only when double write only */
5575 /*data32 |= 0x8;*/ /* Big-Endian per 64-bit */
5576
5577 /* swap uv */
5578 if (pbi->is_used_v4l) {
5579 if ((v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21) ||
5580 (v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
5581 data32 |= (1 << 12); /* NV21 */
5582 else
5583 data32 &= ~(1 << 12); /* NV12 */
5584 }
5585
5586 /*
5587 * [3:0] little_endian
5588 * [5:4] address_format 00:linear 01:32x32 10:64x32
5589 * [7:6] reserved
5590 * [9:8] Linear_LineAlignment 00:16byte 01:32byte 10:64byte
5591 * [11:10] reserved
5592 * [12] CbCr_byte_swap
5593 * [31:13] reserved
5594 */
5595 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
5596#endif
5597}
5598
5599static void vp9_config_work_space_hw(struct VP9Decoder_s *pbi, u32 mask)
5600{
5601 struct BuffInfo_s *buf_spec = pbi->work_space_buf;
5602 unsigned int data32;
5603
5604 if (debug && pbi->init_flag == 0)
5605 pr_info("%s %x %x %x %x %x %x %x %x %x %x %x %x\n",
5606 __func__,
5607 buf_spec->ipp.buf_start,
5608 buf_spec->start_adr,
5609 buf_spec->short_term_rps.buf_start,
5610 buf_spec->vps.buf_start,
5611 buf_spec->sps.buf_start,
5612 buf_spec->pps.buf_start,
5613 buf_spec->sao_up.buf_start,
5614 buf_spec->swap_buf.buf_start,
5615 buf_spec->swap_buf2.buf_start,
5616 buf_spec->scalelut.buf_start,
5617 buf_spec->dblk_para.buf_start,
5618 buf_spec->dblk_data.buf_start);
5619
5620 if (mask & HW_MASK_FRONT) {
5621 if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0)
5622 WRITE_VREG(HEVC_RPM_BUFFER, (u32)pbi->rpm_phy_addr);
5623
5624 WRITE_VREG(HEVC_SHORT_TERM_RPS,
5625 buf_spec->short_term_rps.buf_start);
5626 /*WRITE_VREG(HEVC_VPS_BUFFER, buf_spec->vps.buf_start);*/
5627 /*WRITE_VREG(HEVC_SPS_BUFFER, buf_spec->sps.buf_start);*/
5628 WRITE_VREG(HEVC_PPS_BUFFER, buf_spec->pps.buf_start);
5629 WRITE_VREG(HEVC_STREAM_SWAP_BUFFER,
5630 buf_spec->swap_buf.buf_start);
5631 WRITE_VREG(HEVC_STREAM_SWAP_BUFFER2,
5632 buf_spec->swap_buf2.buf_start);
5633 WRITE_VREG(LMEM_DUMP_ADR, (u32)pbi->lmem_phy_addr);
5634
5635 }
5636
5637 if (mask & HW_MASK_BACK) {
5638#ifdef LOSLESS_COMPRESS_MODE
5639 int losless_comp_header_size =
5640 compute_losless_comp_header_size(pbi->init_pic_w,
5641 pbi->init_pic_h);
5642 int losless_comp_body_size =
5643 compute_losless_comp_body_size(pbi->init_pic_w,
5644 pbi->init_pic_h, buf_alloc_depth == 10);
5645#endif
5646 WRITE_VREG(HEVCD_IPP_LINEBUFF_BASE,
5647 buf_spec->ipp.buf_start);
5648 WRITE_VREG(HEVC_SAO_UP, buf_spec->sao_up.buf_start);
5649 WRITE_VREG(HEVC_SCALELUT, buf_spec->scalelut.buf_start);
5650 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
5651 /* cfg_addr_adp*/
5652 WRITE_VREG(HEVC_DBLK_CFGE, buf_spec->dblk_para.buf_start);
5653 if (debug & VP9_DEBUG_BUFMGR_MORE)
5654 pr_info("Write HEVC_DBLK_CFGE\n");
5655 }
5656 /* cfg_p_addr */
5657 WRITE_VREG(HEVC_DBLK_CFG4, buf_spec->dblk_para.buf_start);
5658 /* cfg_d_addr */
5659 WRITE_VREG(HEVC_DBLK_CFG5, buf_spec->dblk_data.buf_start);
5660
5661 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
5662 /*
5663 * data32 = (READ_VREG(P_HEVC_DBLK_CFG3)>>8) & 0xff; // xio left offset, default is 0x40
5664 * data32 = data32 * 2;
5665 * data32 = (READ_VREG(P_HEVC_DBLK_CFG3)>>16) & 0xff; // adp left offset, default is 0x040
5666 * data32 = data32 * 2;
5667 */
5668 WRITE_VREG(HEVC_DBLK_CFG3, 0x808010); // make left storage 2 x 4k]
5669 }
5670#ifdef LOSLESS_COMPRESS_MODE
5671 if (pbi->mmu_enable) {
5672 /*bit[4] : paged_mem_mode*/
5673 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
5674 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_SM1)
5675 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0);
5676 } else {
5677 /*if(cur_pic_config->bit_depth == VPX_BITS_10)
5678 * WRITE_VREG(P_HEVCD_MPP_DECOMP_CTL1, (0<<3));
5679 */
5680 /*bit[3] smem mdoe*/
5681 /*else WRITE_VREG(P_HEVCD_MPP_DECOMP_CTL1, (1<<3));*/
5682 /*bit[3] smem mdoe*/
5683 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2,
5684 (losless_comp_body_size >> 5));
5685 }
5686 /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL2,
5687 (losless_comp_body_size >> 5));*/
5688 /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,
5689 (0xff<<20) | (0xff<<10) | 0xff);*/
5690 /*8-bit mode */
5691 WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size);
5692 WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size);
5693 WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size);
5694 if (get_double_write_mode(pbi) & 0x10)
5695 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5696#else
5697 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5698#endif
5699
5700 if (pbi->mmu_enable) {
5701 WRITE_VREG(HEVC_SAO_MMU_VH0_ADDR, buf_spec->mmu_vbh.buf_start);
5702 WRITE_VREG(HEVC_SAO_MMU_VH1_ADDR, buf_spec->mmu_vbh.buf_start
5703 + buf_spec->mmu_vbh.buf_size/2);
5704 /*data32 = READ_VREG(P_HEVC_SAO_CTRL9);*/
5705 /*data32 |= 0x1;*/
5706 /*WRITE_VREG(P_HEVC_SAO_CTRL9, data32);*/
5707
5708 /* use HEVC_CM_HEADER_START_ADDR */
5709 data32 = READ_VREG(HEVC_SAO_CTRL5);
5710 data32 |= (1<<10);
5711 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5712 }
5713
5714 WRITE_VREG(VP9_SEG_MAP_BUFFER, buf_spec->seg_map.buf_start);
5715
5716 WRITE_VREG(LMEM_DUMP_ADR, (u32)pbi->lmem_phy_addr);
5717 /**/
5718 WRITE_VREG(VP9_PROB_SWAP_BUFFER, pbi->prob_buffer_phy_addr);
5719 WRITE_VREG(VP9_COUNT_SWAP_BUFFER, pbi->count_buffer_phy_addr);
5720 if (pbi->mmu_enable) {
5721 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A)
5722 WRITE_VREG(HEVC_ASSIST_MMU_MAP_ADDR, pbi->frame_mmu_map_phy_addr);
5723 else
5724 WRITE_VREG(VP9_MMU_MAP_BUFFER, pbi->frame_mmu_map_phy_addr);
5725 }
5726 }
5727}
5728
5729
5730#ifdef VP9_LPF_LVL_UPDATE
5731/*
5732 * Defines, declarations, sub-functions for vp9 de-block loop
5733 filter Thr/Lvl table update
5734 * - struct segmentation is for loop filter only (removed something)
5735 * - function "vp9_loop_filter_init" and "vp9_loop_filter_frame_init" will
5736 be instantiated in C_Entry
5737 * - vp9_loop_filter_init run once before decoding start
5738 * - vp9_loop_filter_frame_init run before every frame decoding start
5739 * - set video format to VP9 is in vp9_loop_filter_init
5740 */
5741#define MAX_LOOP_FILTER 63
5742#define MAX_REF_LF_DELTAS 4
5743#define MAX_MODE_LF_DELTAS 2
5744/*#define INTRA_FRAME 0*/
5745/*#define LAST_FRAME 1*/
5746/*#define MAX_REF_FRAMES 4*/
5747#define SEGMENT_DELTADATA 0
5748#define SEGMENT_ABSDATA 1
5749#define MAX_SEGMENTS 8
5750/*.#define SEG_TREE_PROBS (MAX_SEGMENTS-1)*/
5751/*no use for loop filter, if this struct for common use, pls add it back*/
5752/*#define PREDICTION_PROBS 3*/
5753/* no use for loop filter, if this struct for common use, pls add it back*/
5754
5755enum SEG_LVL_FEATURES {
5756 SEG_LVL_ALT_Q = 0, /*Use alternate Quantizer ....*/
5757 SEG_LVL_ALT_LF = 1, /*Use alternate loop filter value...*/
5758 SEG_LVL_REF_FRAME = 2, /*Optional Segment reference frame*/
5759 SEG_LVL_SKIP = 3, /*Optional Segment (0,0) + skip mode*/
5760 SEG_LVL_MAX = 4 /*Number of features supported*/
5761};
5762
5763struct segmentation {
5764 uint8_t enabled;
5765 uint8_t update_map;
5766 uint8_t update_data;
5767 uint8_t abs_delta;
5768 uint8_t temporal_update;
5769
5770 /*no use for loop filter, if this struct
5771 *for common use, pls add it back
5772 */
5773 /*vp9_prob tree_probs[SEG_TREE_PROBS]; */
5774 /* no use for loop filter, if this struct
5775 * for common use, pls add it back
5776 */
5777 /*vp9_prob pred_probs[PREDICTION_PROBS];*/
5778
5779 int16_t feature_data[MAX_SEGMENTS][SEG_LVL_MAX];
5780 unsigned int feature_mask[MAX_SEGMENTS];
5781};
5782
5783struct loop_filter_thresh {
5784 uint8_t mblim;
5785 uint8_t lim;
5786 uint8_t hev_thr;
5787};
5788
5789struct loop_filter_info_n {
5790 struct loop_filter_thresh lfthr[MAX_LOOP_FILTER + 1];
5791 uint8_t lvl[MAX_SEGMENTS][MAX_REF_FRAMES][MAX_MODE_LF_DELTAS];
5792};
5793
5794struct loopfilter {
5795 int filter_level;
5796
5797 int sharpness_level;
5798 int last_sharpness_level;
5799
5800 uint8_t mode_ref_delta_enabled;
5801 uint8_t mode_ref_delta_update;
5802
5803 /*0 = Intra, Last, GF, ARF*/
5804 signed char ref_deltas[MAX_REF_LF_DELTAS];
5805 signed char last_ref_deltas[MAX_REF_LF_DELTAS];
5806
5807 /*0 = ZERO_MV, MV*/
5808 signed char mode_deltas[MAX_MODE_LF_DELTAS];
5809 signed char last_mode_deltas[MAX_MODE_LF_DELTAS];
5810};
5811
5812static int vp9_clamp(int value, int low, int high)
5813{
5814 return value < low ? low : (value > high ? high : value);
5815}
5816
5817int segfeature_active(struct segmentation *seg,
5818 int segment_id,
5819 enum SEG_LVL_FEATURES feature_id) {
5820 return seg->enabled &&
5821 (seg->feature_mask[segment_id] & (1 << feature_id));
5822}
5823
5824int get_segdata(struct segmentation *seg, int segment_id,
5825 enum SEG_LVL_FEATURES feature_id) {
5826 return seg->feature_data[segment_id][feature_id];
5827}
5828
5829static void vp9_update_sharpness(struct loop_filter_info_n *lfi,
5830 int sharpness_lvl)
5831{
5832 int lvl;
5833 /*For each possible value for the loop filter fill out limits*/
5834 for (lvl = 0; lvl <= MAX_LOOP_FILTER; lvl++) {
5835 /*Set loop filter parameters that control sharpness.*/
5836 int block_inside_limit = lvl >> ((sharpness_lvl > 0) +
5837 (sharpness_lvl > 4));
5838
5839 if (sharpness_lvl > 0) {
5840 if (block_inside_limit > (9 - sharpness_lvl))
5841 block_inside_limit = (9 - sharpness_lvl);
5842 }
5843
5844 if (block_inside_limit < 1)
5845 block_inside_limit = 1;
5846
5847 lfi->lfthr[lvl].lim = (uint8_t)block_inside_limit;
5848 lfi->lfthr[lvl].mblim = (uint8_t)(2 * (lvl + 2) +
5849 block_inside_limit);
5850 }
5851}
5852
5853/*instantiate this function once when decode is started*/
5854void vp9_loop_filter_init(struct VP9Decoder_s *pbi)
5855{
5856 struct loop_filter_info_n *lfi = pbi->lfi;
5857 struct loopfilter *lf = pbi->lf;
5858 struct segmentation *seg_4lf = pbi->seg_4lf;
5859 int i;
5860 unsigned int data32;
5861
5862 memset(lfi, 0, sizeof(struct loop_filter_info_n));
5863 memset(lf, 0, sizeof(struct loopfilter));
5864 memset(seg_4lf, 0, sizeof(struct segmentation));
5865 lf->sharpness_level = 0; /*init to 0 */
5866 /*init limits for given sharpness*/
5867 vp9_update_sharpness(lfi, lf->sharpness_level);
5868 lf->last_sharpness_level = lf->sharpness_level;
5869 /*init hev threshold const vectors (actually no use)
5870 *for (i = 0; i <= MAX_LOOP_FILTER; i++)
5871 * lfi->lfthr[i].hev_thr = (uint8_t)(i >> 4);
5872 */
5873
5874 /*Write to register*/
5875 for (i = 0; i < 32; i++) {
5876 unsigned int thr;
5877
5878 thr = ((lfi->lfthr[i * 2 + 1].lim & 0x3f)<<8) |
5879 (lfi->lfthr[i * 2 + 1].mblim & 0xff);
5880 thr = (thr<<16) | ((lfi->lfthr[i*2].lim & 0x3f)<<8) |
5881 (lfi->lfthr[i * 2].mblim & 0xff);
5882 WRITE_VREG(HEVC_DBLK_CFG9, thr);
5883 }
5884
5885 /*video format is VP9*/
5886 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
5887 data32 = (0x3 << 14) | // (dw fifo thres r and b)
5888 (0x3 << 12) | // (dw fifo thres r or b)
5889 (0x3 << 10) | // (dw fifo thres not r/b)
5890 (0x3 << 8) | // 1st/2nd write both enable
5891 (0x1 << 0); // vp9 video format
5892 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
5893 data32 = (0x57 << 8) | /*1st/2nd write both enable*/
5894 (0x1 << 0); /*vp9 video format*/
5895 } else
5896 data32 = 0x40400001;
5897
5898 WRITE_VREG(HEVC_DBLK_CFGB, data32);
5899 if (debug & VP9_DEBUG_BUFMGR_MORE)
5900 pr_info("[DBLK DEBUG] CFGB : 0x%x\n", data32);
5901}
5902 /* perform this function per frame*/
5903void vp9_loop_filter_frame_init(struct segmentation *seg,
5904 struct loop_filter_info_n *lfi, struct loopfilter *lf,
5905 int default_filt_lvl) {
5906 int i;
5907 int seg_id;
5908 /*n_shift is the multiplier for lf_deltas
5909 *the multiplier is 1 for when filter_lvl is between 0 and 31;
5910 *2 when filter_lvl is between 32 and 63
5911 */
5912 const int scale = 1 << (default_filt_lvl >> 5);
5913
5914 /*update limits if sharpness has changed*/
5915 if (lf->last_sharpness_level != lf->sharpness_level) {
5916 vp9_update_sharpness(lfi, lf->sharpness_level);
5917 lf->last_sharpness_level = lf->sharpness_level;
5918
5919 /*Write to register*/
5920 for (i = 0; i < 32; i++) {
5921 unsigned int thr;
5922
5923 thr = ((lfi->lfthr[i * 2 + 1].lim & 0x3f) << 8)
5924 | (lfi->lfthr[i * 2 + 1].mblim & 0xff);
5925 thr = (thr << 16) | ((lfi->lfthr[i * 2].lim & 0x3f) << 8)
5926 | (lfi->lfthr[i * 2].mblim & 0xff);
5927 WRITE_VREG(HEVC_DBLK_CFG9, thr);
5928 }
5929 }
5930
5931 for (seg_id = 0; seg_id < MAX_SEGMENTS; seg_id++) {/*MAX_SEGMENTS = 8*/
5932 int lvl_seg = default_filt_lvl;
5933
5934 if (segfeature_active(seg, seg_id, SEG_LVL_ALT_LF)) {
5935 const int data = get_segdata(seg, seg_id,
5936 SEG_LVL_ALT_LF);
5937 lvl_seg = vp9_clamp(seg->abs_delta == SEGMENT_ABSDATA ?
5938 data : default_filt_lvl + data,
5939 0, MAX_LOOP_FILTER);
5940#ifdef DBG_LF_PRINT
5941 pr_info("segfeature_active!!!seg_id=%d,lvl_seg=%d\n", seg_id, lvl_seg);
5942#endif
5943 }
5944
5945 if (!lf->mode_ref_delta_enabled) {
5946 /*we could get rid of this if we assume that deltas are set to
5947 *zero when not in use; encoder always uses deltas
5948 */
5949 memset(lfi->lvl[seg_id], lvl_seg, sizeof(lfi->lvl[seg_id]));
5950 } else {
5951 int ref, mode;
5952 const int intra_lvl = lvl_seg + lf->ref_deltas[INTRA_FRAME]
5953 * scale;
5954#ifdef DBG_LF_PRINT
5955 pr_info("LF_PRINT:vp9_loop_filter_frame_init,seg_id=%d\n", seg_id);
5956 pr_info("ref_deltas[INTRA_FRAME]=%d\n", lf->ref_deltas[INTRA_FRAME]);
5957#endif
5958 lfi->lvl[seg_id][INTRA_FRAME][0] =
5959 vp9_clamp(intra_lvl, 0, MAX_LOOP_FILTER);
5960
5961 for (ref = LAST_FRAME; ref < MAX_REF_FRAMES; ++ref) {
5962 /* LAST_FRAME = 1, MAX_REF_FRAMES = 4*/
5963 for (mode = 0; mode < MAX_MODE_LF_DELTAS; ++mode) {
5964 /*MAX_MODE_LF_DELTAS = 2*/
5965 const int inter_lvl =
5966 lvl_seg + lf->ref_deltas[ref] * scale
5967 + lf->mode_deltas[mode] * scale;
5968#ifdef DBG_LF_PRINT
5969#endif
5970 lfi->lvl[seg_id][ref][mode] =
5971 vp9_clamp(inter_lvl, 0,
5972 MAX_LOOP_FILTER);
5973 }
5974 }
5975 }
5976 }
5977
5978#ifdef DBG_LF_PRINT
5979 /*print out thr/lvl table per frame*/
5980 for (i = 0; i <= MAX_LOOP_FILTER; i++) {
5981 pr_info("LF_PRINT:(%d)thr=%d,blim=%d,lim=%d\n",
5982 i, lfi->lfthr[i].hev_thr, lfi->lfthr[i].mblim,
5983 lfi->lfthr[i].lim);
5984 }
5985 for (seg_id = 0; seg_id < MAX_SEGMENTS; seg_id++) {
5986 pr_info("LF_PRINT:lvl(seg_id=%d)(mode=0,%d,%d,%d,%d)\n",
5987 seg_id, lfi->lvl[seg_id][0][0],
5988 lfi->lvl[seg_id][1][0], lfi->lvl[seg_id][2][0],
5989 lfi->lvl[seg_id][3][0]);
5990 pr_info("i(mode=1,%d,%d,%d,%d)\n", lfi->lvl[seg_id][0][1],
5991 lfi->lvl[seg_id][1][1], lfi->lvl[seg_id][2][1],
5992 lfi->lvl[seg_id][3][1]);
5993 }
5994#endif
5995
5996 /*Write to register */
5997 for (i = 0; i < 16; i++) {
5998 unsigned int level;
5999
6000 level = ((lfi->lvl[i >> 1][3][i & 1] & 0x3f) << 24) |
6001 ((lfi->lvl[i >> 1][2][i & 1] & 0x3f) << 16) |
6002 ((lfi->lvl[i >> 1][1][i & 1] & 0x3f) << 8) |
6003 (lfi->lvl[i >> 1][0][i & 1] & 0x3f);
6004 if (!default_filt_lvl)
6005 level = 0;
6006 WRITE_VREG(HEVC_DBLK_CFGA, level);
6007 }
6008}
6009/* VP9_LPF_LVL_UPDATE */
6010#endif
6011
6012static void vp9_init_decoder_hw(struct VP9Decoder_s *pbi, u32 mask)
6013{
6014 unsigned int data32;
6015 int i;
6016 const unsigned short parser_cmd[PARSER_CMD_NUMBER] = {
6017 0x0401, 0x8401, 0x0800, 0x0402, 0x9002, 0x1423,
6018 0x8CC3, 0x1423, 0x8804, 0x9825, 0x0800, 0x04FE,
6019 0x8406, 0x8411, 0x1800, 0x8408, 0x8409, 0x8C2A,
6020 0x9C2B, 0x1C00, 0x840F, 0x8407, 0x8000, 0x8408,
6021 0x2000, 0xA800, 0x8410, 0x04DE, 0x840C, 0x840D,
6022 0xAC00, 0xA000, 0x08C0, 0x08E0, 0xA40E, 0xFC00,
6023 0x7C00
6024 };
6025#if 0
6026 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
6027 /* Set MCR fetch priorities*/
6028 data32 = 0x1 | (0x1 << 2) | (0x1 <<3) |
6029 (24 << 4) | (32 << 11) | (24 << 18) | (32 << 25);
6030 WRITE_VREG(HEVCD_MPP_DECOMP_AXIURG_CTL, data32);
6031 }
6032#endif
6033 /*if (debug & VP9_DEBUG_BUFMGR_MORE)
6034 pr_info("%s\n", __func__);*/
6035 if (mask & HW_MASK_FRONT) {
6036 data32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
6037#if 1
6038 /* set bit 31~29 to 3 if HEVC_STREAM_FIFO_CTL[29] is 1 */
6039 data32 &= ~(7 << 29);
6040 data32 |= (3 << 29);
6041#endif
6042 data32 = data32 |
6043 (1 << 24) |/*stream_buffer_empty_int_amrisc_enable*/
6044 (1 << 22) |/*stream_fifo_empty_int_amrisc_enable*/
6045 (1 << 7) |/*dec_done_int_cpu_enable*/
6046 (1 << 4) |/*startcode_found_int_cpu_enable*/
6047 (0 << 3) |/*startcode_found_int_amrisc_enable*/
6048 (1 << 0) /*parser_int_enable*/
6049 ;
6050#ifdef SUPPORT_FB_DECODING
6051#ifndef FB_DECODING_TEST_SCHEDULE
6052 /*fed_fb_slice_done_int_cpu_enable*/
6053 if (pbi->used_stage_buf_num > 0)
6054 data32 |= (1 << 10);
6055#endif
6056#endif
6057 WRITE_VREG(HEVC_PARSER_INT_CONTROL, data32);
6058
6059 data32 = READ_VREG(HEVC_SHIFT_STATUS);
6060 data32 = data32 |
6061 (0 << 1) |/*emulation_check_off VP9
6062 do not have emulation*/
6063 (1 << 0)/*startcode_check_on*/
6064 ;
6065 WRITE_VREG(HEVC_SHIFT_STATUS, data32);
6066 WRITE_VREG(HEVC_SHIFT_CONTROL,
6067 (0 << 14) | /*disable_start_code_protect*/
6068 (1 << 10) | /*length_zero_startcode_en for VP9*/
6069 (1 << 9) | /*length_valid_startcode_en for VP9*/
6070 (3 << 6) | /*sft_valid_wr_position*/
6071 (2 << 4) | /*emulate_code_length_sub_1*/
6072 (3 << 1) | /*start_code_length_sub_1
6073 VP9 use 0x00000001 as startcode (4 Bytes)*/
6074 (1 << 0) /*stream_shift_enable*/
6075 );
6076
6077 WRITE_VREG(HEVC_CABAC_CONTROL,
6078 (1 << 0)/*cabac_enable*/
6079 );
6080
6081 WRITE_VREG(HEVC_PARSER_CORE_CONTROL,
6082 (1 << 0)/* hevc_parser_core_clk_en*/
6083 );
6084
6085
6086 WRITE_VREG(HEVC_DEC_STATUS_REG, 0);
6087
6088 }
6089
6090 if (mask & HW_MASK_BACK) {
6091 /*Initial IQIT_SCALELUT memory
6092 -- just to avoid X in simulation*/
6093
6094 WRITE_VREG(HEVC_IQIT_SCALELUT_WR_ADDR, 0);/*cfg_p_addr*/
6095 for (i = 0; i < 1024; i++)
6096 WRITE_VREG(HEVC_IQIT_SCALELUT_DATA, 0);
6097 }
6098
6099 if (mask & HW_MASK_FRONT) {
6100 u32 decode_mode;
6101#ifdef ENABLE_SWAP_TEST
6102 WRITE_VREG(HEVC_STREAM_SWAP_TEST, 100);
6103#else
6104 WRITE_VREG(HEVC_STREAM_SWAP_TEST, 0);
6105#endif
6106#ifdef MULTI_INSTANCE_SUPPORT
6107 if (!pbi->m_ins_flag) {
6108 if (pbi->low_latency_flag)
6109 decode_mode = DECODE_MODE_SINGLE_LOW_LATENCY;
6110 else
6111 decode_mode = DECODE_MODE_SINGLE;
6112 } else if (vdec_frame_based(hw_to_vdec(pbi)))
6113 decode_mode = pbi->no_head ?
6114 DECODE_MODE_MULTI_FRAMEBASE_NOHEAD :
6115 DECODE_MODE_MULTI_FRAMEBASE;
6116 else
6117 decode_mode = DECODE_MODE_MULTI_STREAMBASE;
6118#ifdef SUPPORT_FB_DECODING
6119#ifndef FB_DECODING_TEST_SCHEDULE
6120 if (pbi->used_stage_buf_num > 0)
6121 decode_mode |= (0x01 << 24);
6122#endif
6123#endif
6124 WRITE_VREG(DECODE_MODE, decode_mode);
6125 WRITE_VREG(HEVC_DECODE_SIZE, 0);
6126 WRITE_VREG(HEVC_DECODE_COUNT, 0);
6127#else
6128 WRITE_VREG(DECODE_MODE, DECODE_MODE_SINGLE);
6129 WRITE_VREG(HEVC_DECODE_PIC_BEGIN_REG, 0);
6130 WRITE_VREG(HEVC_DECODE_PIC_NUM_REG, 0x7fffffff); /*to remove*/
6131#endif
6132 /*Send parser_cmd*/
6133 WRITE_VREG(HEVC_PARSER_CMD_WRITE, (1 << 16) | (0 << 0));
6134 for (i = 0; i < PARSER_CMD_NUMBER; i++)
6135 WRITE_VREG(HEVC_PARSER_CMD_WRITE, parser_cmd[i]);
6136 WRITE_VREG(HEVC_PARSER_CMD_SKIP_0, PARSER_CMD_SKIP_CFG_0);
6137 WRITE_VREG(HEVC_PARSER_CMD_SKIP_1, PARSER_CMD_SKIP_CFG_1);
6138 WRITE_VREG(HEVC_PARSER_CMD_SKIP_2, PARSER_CMD_SKIP_CFG_2);
6139
6140
6141 WRITE_VREG(HEVC_PARSER_IF_CONTROL,
6142 /* (1 << 8) |*/ /*sao_sw_pred_enable*/
6143 (1 << 5) | /*parser_sao_if_en*/
6144 (1 << 2) | /*parser_mpred_if_en*/
6145 (1 << 0) /*parser_scaler_if_en*/
6146 );
6147 }
6148
6149 if (mask & HW_MASK_BACK) {
6150 /*Changed to Start MPRED in microcode*/
6151 /*
6152 pr_info("[test.c] Start MPRED\n");
6153 WRITE_VREG(HEVC_MPRED_INT_STATUS,
6154 (1<<31)
6155 );
6156 */
6157 WRITE_VREG(HEVCD_IPP_TOP_CNTL,
6158 (0 << 1) | /*enable ipp*/
6159 (1 << 0) /*software reset ipp and mpp*/
6160 );
6161 WRITE_VREG(HEVCD_IPP_TOP_CNTL,
6162 (1 << 1) | /*enable ipp*/
6163 (0 << 0) /*software reset ipp and mpp*/
6164 );
6165 if (get_double_write_mode(pbi) & 0x10) {
6166 /*Enable NV21 reference read mode for MC*/
6167 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
6168 }
6169
6170 /*Initialize mcrcc and decomp perf counters*/
6171 if (mcrcc_cache_alg_flag &&
6172 pbi->init_flag == 0) {
6173 mcrcc_perfcount_reset();
6174 decomp_perfcount_reset();
6175 }
6176 }
6177 return;
6178}
6179
6180
6181#ifdef CONFIG_HEVC_CLK_FORCED_ON
6182static void config_vp9_clk_forced_on(void)
6183{
6184 unsigned int rdata32;
6185 /*IQIT*/
6186 rdata32 = READ_VREG(HEVC_IQIT_CLK_RST_CTRL);
6187 WRITE_VREG(HEVC_IQIT_CLK_RST_CTRL, rdata32 | (0x1 << 2));
6188
6189 /* DBLK*/
6190 rdata32 = READ_VREG(HEVC_DBLK_CFG0);
6191 WRITE_VREG(HEVC_DBLK_CFG0, rdata32 | (0x1 << 2));
6192
6193 /* SAO*/
6194 rdata32 = READ_VREG(HEVC_SAO_CTRL1);
6195 WRITE_VREG(HEVC_SAO_CTRL1, rdata32 | (0x1 << 2));
6196
6197 /*MPRED*/
6198 rdata32 = READ_VREG(HEVC_MPRED_CTRL1);
6199 WRITE_VREG(HEVC_MPRED_CTRL1, rdata32 | (0x1 << 24));
6200
6201 /* PARSER*/
6202 rdata32 = READ_VREG(HEVC_STREAM_CONTROL);
6203 WRITE_VREG(HEVC_STREAM_CONTROL, rdata32 | (0x1 << 15));
6204 rdata32 = READ_VREG(HEVC_SHIFT_CONTROL);
6205 WRITE_VREG(HEVC_SHIFT_CONTROL, rdata32 | (0x1 << 15));
6206 rdata32 = READ_VREG(HEVC_CABAC_CONTROL);
6207 WRITE_VREG(HEVC_CABAC_CONTROL, rdata32 | (0x1 << 13));
6208 rdata32 = READ_VREG(HEVC_PARSER_CORE_CONTROL);
6209 WRITE_VREG(HEVC_PARSER_CORE_CONTROL, rdata32 | (0x1 << 15));
6210 rdata32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
6211 WRITE_VREG(HEVC_PARSER_INT_CONTROL, rdata32 | (0x1 << 15));
6212 rdata32 = READ_VREG(HEVC_PARSER_IF_CONTROL);
6213 WRITE_VREG(HEVC_PARSER_IF_CONTROL,
6214 rdata32 | (0x1 << 6) | (0x1 << 3) | (0x1 << 1));
6215
6216 /*IPP*/
6217 rdata32 = READ_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG);
6218 WRITE_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG, rdata32 | 0xffffffff);
6219
6220 /* MCRCC*/
6221 rdata32 = READ_VREG(HEVCD_MCRCC_CTL1);
6222 WRITE_VREG(HEVCD_MCRCC_CTL1, rdata32 | (0x1 << 3));
6223}
6224#endif
6225
6226
6227#ifdef MCRCC_ENABLE
6228static void dump_hit_rate(struct VP9Decoder_s *pbi)
6229{
6230 if (debug & VP9_DEBUG_CACHE_HIT_RATE) {
6231 mcrcc_get_hitrate(pbi->m_ins_flag);
6232 decomp_get_hitrate();
6233 decomp_get_comprate();
6234 }
6235}
6236
6237static void config_mcrcc_axi_hw(struct VP9Decoder_s *pbi)
6238{
6239 unsigned int rdata32;
6240 unsigned short is_inter;
6241 /*pr_info("Entered config_mcrcc_axi_hw...\n");*/
6242 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2);/* reset mcrcc*/
6243 is_inter = ((pbi->common.frame_type != KEY_FRAME) &&
6244 (!pbi->common.intra_only)) ? 1 : 0;
6245 if (!is_inter) { /* I-PIC*/
6246 /*remove reset -- disables clock*/
6247 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
6248 return;
6249 }
6250
6251 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
6252 mcrcc_get_hitrate(pbi->m_ins_flag);
6253 decomp_get_hitrate();
6254 decomp_get_comprate();
6255 }
6256
6257 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
6258 (0 << 8) | (1 << 1) | 0);
6259 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6260 rdata32 = rdata32 & 0xffff;
6261 rdata32 = rdata32 | (rdata32 << 16);
6262 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
6263 /*Programme canvas1 */
6264 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6265 rdata32 = rdata32 & 0xffff;
6266 rdata32 = rdata32 | (rdata32 << 16);
6267 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
6268 /*enable mcrcc progressive-mode*/
6269 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0);
6270}
6271
6272static void config_mcrcc_axi_hw_new(struct VP9Decoder_s *pbi)
6273{
6274 u32 curr_picnum = -1;
6275 u32 lastref_picnum = -1;
6276 u32 goldenref_picnum = -1;
6277 u32 altref_picnum = -1;
6278
6279 u32 lastref_delta_picnum;
6280 u32 goldenref_delta_picnum;
6281 u32 altref_delta_picnum;
6282
6283 u32 rdata32;
6284
6285 u32 lastcanvas;
6286 u32 goldencanvas;
6287 u32 altrefcanvas;
6288
6289 u16 is_inter;
6290 u16 lastref_inref;
6291 u16 goldenref_inref;
6292 u16 altref_inref;
6293
6294 u32 refcanvas_array[3], utmp;
6295 int deltapicnum_array[3], tmp;
6296
6297 struct VP9_Common_s *cm = &pbi->common;
6298 struct PIC_BUFFER_CONFIG_s *cur_pic_config
6299 = &cm->cur_frame->buf;
6300 curr_picnum = cur_pic_config->decode_idx;
6301 if (cm->frame_refs[0].buf)
6302 lastref_picnum = cm->frame_refs[0].buf->decode_idx;
6303 if (cm->frame_refs[1].buf)
6304 goldenref_picnum = cm->frame_refs[1].buf->decode_idx;
6305 if (cm->frame_refs[2].buf)
6306 altref_picnum = cm->frame_refs[2].buf->decode_idx;
6307
6308 lastref_delta_picnum = (lastref_picnum >= curr_picnum) ?
6309 (lastref_picnum - curr_picnum) : (curr_picnum - lastref_picnum);
6310 goldenref_delta_picnum = (goldenref_picnum >= curr_picnum) ?
6311 (goldenref_picnum - curr_picnum) :
6312 (curr_picnum - goldenref_picnum);
6313 altref_delta_picnum =
6314 (altref_picnum >= curr_picnum) ?
6315 (altref_picnum - curr_picnum) : (curr_picnum - altref_picnum);
6316
6317 lastref_inref = (cm->frame_refs[0].idx != INVALID_IDX) ? 1 : 0;
6318 goldenref_inref = (cm->frame_refs[1].idx != INVALID_IDX) ? 1 : 0;
6319 altref_inref = (cm->frame_refs[2].idx != INVALID_IDX) ? 1 : 0;
6320
6321 if (debug & VP9_DEBUG_CACHE)
6322 pr_info("%s--0--lastref_inref:%d goldenref_inref:%d altref_inref:%d\n",
6323 __func__, lastref_inref, goldenref_inref, altref_inref);
6324
6325 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2); /* reset mcrcc */
6326
6327 is_inter = ((pbi->common.frame_type != KEY_FRAME)
6328 && (!pbi->common.intra_only)) ? 1 : 0;
6329
6330 if (!is_inter) { /* I-PIC */
6331 /* remove reset -- disables clock */
6332 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
6333 return;
6334 }
6335
6336 if (!pbi->m_ins_flag)
6337 dump_hit_rate(pbi);
6338
6339 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (0 << 8) | (1<<1) | 0);
6340 lastcanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6341 goldencanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6342 altrefcanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6343
6344 if (debug & VP9_DEBUG_CACHE)
6345 pr_info("[test.c] lastref_canv:%x goldenref_canv:%x altref_canv:%x\n",
6346 lastcanvas, goldencanvas, altrefcanvas);
6347
6348 altref_inref = ((altref_inref == 1) &&
6349 (altrefcanvas != (goldenref_inref
6350 ? goldencanvas : 0xffffffff)) &&
6351 (altrefcanvas != (lastref_inref ?
6352 lastcanvas : 0xffffffff))) ? 1 : 0;
6353 goldenref_inref = ((goldenref_inref == 1) &&
6354 (goldencanvas != (lastref_inref ?
6355 lastcanvas : 0xffffffff))) ? 1 : 0;
6356 if (debug & VP9_DEBUG_CACHE)
6357 pr_info("[test.c]--1--lastref_inref:%d goldenref_inref:%d altref_inref:%d\n",
6358 lastref_inref, goldenref_inref, altref_inref);
6359
6360 altref_delta_picnum = altref_inref ? altref_delta_picnum : 0x7fffffff;
6361 goldenref_delta_picnum = goldenref_inref ?
6362 goldenref_delta_picnum : 0x7fffffff;
6363 lastref_delta_picnum = lastref_inref ?
6364 lastref_delta_picnum : 0x7fffffff;
6365 if (debug & VP9_DEBUG_CACHE)
6366 pr_info("[test.c]--1--lastref_delta_picnum:%d goldenref_delta_picnum:%d altref_delta_picnum:%d\n",
6367 lastref_delta_picnum, goldenref_delta_picnum,
6368 altref_delta_picnum);
6369 /*ARRAY SORT HERE DELTA/CANVAS ARRAY SORT -- use DELTA*/
6370
6371 refcanvas_array[0] = lastcanvas;
6372 refcanvas_array[1] = goldencanvas;
6373 refcanvas_array[2] = altrefcanvas;
6374
6375 deltapicnum_array[0] = lastref_delta_picnum;
6376 deltapicnum_array[1] = goldenref_delta_picnum;
6377 deltapicnum_array[2] = altref_delta_picnum;
6378
6379 /* sort0 : 2-to-1 */
6380 if (deltapicnum_array[2] < deltapicnum_array[1]) {
6381 utmp = refcanvas_array[2];
6382 refcanvas_array[2] = refcanvas_array[1];
6383 refcanvas_array[1] = utmp;
6384 tmp = deltapicnum_array[2];
6385 deltapicnum_array[2] = deltapicnum_array[1];
6386 deltapicnum_array[1] = tmp;
6387 }
6388 /* sort1 : 1-to-0 */
6389 if (deltapicnum_array[1] < deltapicnum_array[0]) {
6390 utmp = refcanvas_array[1];
6391 refcanvas_array[1] = refcanvas_array[0];
6392 refcanvas_array[0] = utmp;
6393 tmp = deltapicnum_array[1];
6394 deltapicnum_array[1] = deltapicnum_array[0];
6395 deltapicnum_array[0] = tmp;
6396 }
6397 /* sort2 : 2-to-1 */
6398 if (deltapicnum_array[2] < deltapicnum_array[1]) {
6399 utmp = refcanvas_array[2]; refcanvas_array[2] =
6400 refcanvas_array[1]; refcanvas_array[1] = utmp;
6401 tmp = deltapicnum_array[2]; deltapicnum_array[2] =
6402 deltapicnum_array[1]; deltapicnum_array[1] = tmp;
6403 }
6404 if (mcrcc_cache_alg_flag ==
6405 THODIYIL_MCRCC_CANVAS_ALGX) { /*09/15/2017*/
6406 /* lowest delta_picnum */
6407 rdata32 = refcanvas_array[0];
6408 rdata32 = rdata32 & 0xffff;
6409 rdata32 = rdata32 | (rdata32 << 16);
6410 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
6411
6412 /* 2nd-lowest delta_picnum */
6413 rdata32 = refcanvas_array[1];
6414 rdata32 = rdata32 & 0xffff;
6415 rdata32 = rdata32 | (rdata32 << 16);
6416 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
6417 } else {
6418 /* previous version -- LAST/GOLDEN ALWAYS -- before 09/13/2017*/
6419 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
6420 (0 << 8) | (1<<1) | 0);
6421 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6422 rdata32 = rdata32 & 0xffff;
6423 rdata32 = rdata32 | (rdata32 << 16);
6424 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
6425
6426 /* Programme canvas1 */
6427 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6428 rdata32 = rdata32 & 0xffff;
6429 rdata32 = rdata32 | (rdata32 << 16);
6430 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
6431 }
6432
6433 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0); /* enable mcrcc progressive-mode */
6434 return;
6435}
6436
6437#endif
6438
6439
6440static void free_lf_buf(struct VP9Decoder_s *pbi)
6441{
6442 if (pbi->lfi)
6443 vfree(pbi->lfi);
6444 if (pbi->lf)
6445 vfree(pbi->lf);
6446 if (pbi->seg_4lf)
6447 vfree(pbi->seg_4lf);
6448 pbi->lfi = NULL;
6449 pbi->lf = NULL;
6450 pbi->seg_4lf = NULL;
6451}
6452
6453static int alloc_lf_buf(struct VP9Decoder_s *pbi)
6454{
6455 pbi->lfi = vmalloc(sizeof(struct loop_filter_info_n));
6456 pbi->lf = vmalloc(sizeof(struct loopfilter));
6457 pbi->seg_4lf = vmalloc(sizeof(struct segmentation));
6458 if (pbi->lfi == NULL || pbi->lf == NULL || pbi->seg_4lf == NULL) {
6459 free_lf_buf(pbi);
6460 pr_err("[test.c] vp9_loop_filter init malloc error!!!\n");
6461 return -1;
6462 }
6463 return 0;
6464}
6465
6466static void vp9_local_uninit(struct VP9Decoder_s *pbi)
6467{
6468 pbi->rpm_ptr = NULL;
6469 pbi->lmem_ptr = NULL;
6470 if (pbi->rpm_addr) {
6471 dma_free_coherent(amports_get_dma_device(),
6472 RPM_BUF_SIZE,
6473 pbi->rpm_addr,
6474 pbi->rpm_phy_addr);
6475 pbi->rpm_addr = NULL;
6476 }
6477 if (pbi->lmem_addr) {
6478 if (pbi->lmem_phy_addr)
6479 dma_free_coherent(amports_get_dma_device(),
6480 LMEM_BUF_SIZE, pbi->lmem_addr,
6481 pbi->lmem_phy_addr);
6482 pbi->lmem_addr = NULL;
6483 }
6484 if (pbi->prob_buffer_addr) {
6485 if (pbi->prob_buffer_phy_addr)
6486 dma_free_coherent(amports_get_dma_device(),
6487 PROB_BUF_SIZE, pbi->prob_buffer_addr,
6488 pbi->prob_buffer_phy_addr);
6489
6490 pbi->prob_buffer_addr = NULL;
6491 }
6492 if (pbi->count_buffer_addr) {
6493 if (pbi->count_buffer_phy_addr)
6494 dma_free_coherent(amports_get_dma_device(),
6495 COUNT_BUF_SIZE, pbi->count_buffer_addr,
6496 pbi->count_buffer_phy_addr);
6497
6498 pbi->count_buffer_addr = NULL;
6499 }
6500 if (pbi->mmu_enable) {
6501 u32 mmu_map_size = vvp9_frame_mmu_map_size(pbi);
6502 if (pbi->frame_mmu_map_addr) {
6503 if (pbi->frame_mmu_map_phy_addr)
6504 dma_free_coherent(amports_get_dma_device(),
6505 mmu_map_size,
6506 pbi->frame_mmu_map_addr,
6507 pbi->frame_mmu_map_phy_addr);
6508 pbi->frame_mmu_map_addr = NULL;
6509 }
6510 }
6511#ifdef SUPPORT_FB_DECODING
6512 if (pbi->stage_mmu_map_addr) {
6513 if (pbi->stage_mmu_map_phy_addr)
6514 dma_free_coherent(amports_get_dma_device(),
6515 STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS,
6516 pbi->stage_mmu_map_addr,
6517 pbi->stage_mmu_map_phy_addr);
6518 pbi->stage_mmu_map_addr = NULL;
6519 }
6520
6521 uninit_stage_buf(pbi);
6522#endif
6523
6524#ifdef VP9_LPF_LVL_UPDATE
6525 free_lf_buf(pbi);
6526#endif
6527 if (pbi->gvs)
6528 vfree(pbi->gvs);
6529 pbi->gvs = NULL;
6530}
6531
6532static int vp9_local_init(struct VP9Decoder_s *pbi)
6533{
6534 int ret = -1;
6535 /*int losless_comp_header_size, losless_comp_body_size;*/
6536
6537 struct BuffInfo_s *cur_buf_info = NULL;
6538
6539 memset(&pbi->param, 0, sizeof(union param_u));
6540 memset(&pbi->common, 0, sizeof(struct VP9_Common_s));
6541#ifdef MULTI_INSTANCE_SUPPORT
6542 cur_buf_info = &pbi->work_space_buf_store;
6543
6544 if (vdec_is_support_4k()) {
6545 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
6546 memcpy(cur_buf_info, &amvvp9_workbuff_spec[2], /* 8k */
6547 sizeof(struct BuffInfo_s));
6548 } else
6549 memcpy(cur_buf_info, &amvvp9_workbuff_spec[1], /* 4k */
6550 sizeof(struct BuffInfo_s));
6551 } else
6552 memcpy(cur_buf_info, &amvvp9_workbuff_spec[0],/* 1080p */
6553 sizeof(struct BuffInfo_s));
6554
6555 cur_buf_info->start_adr = pbi->buf_start;
6556 if (!pbi->mmu_enable)
6557 pbi->mc_buf_spec.buf_end = pbi->buf_start + pbi->buf_size;
6558
6559#else
6560/*! MULTI_INSTANCE_SUPPORT*/
6561 if (vdec_is_support_4k()) {
6562 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
6563 cur_buf_info = &amvvp9_workbuff_spec[2];/* 8k work space */
6564 else
6565 cur_buf_info = &amvvp9_workbuff_spec[1];/* 4k2k work space */
6566 } else
6567 cur_buf_info = &amvvp9_workbuff_spec[0];/* 1080p work space */
6568
6569#endif
6570
6571 init_buff_spec(pbi, cur_buf_info);
6572 vp9_bufmgr_init(pbi, cur_buf_info, NULL);
6573
6574 if (!vdec_is_support_4k()
6575 && (buf_alloc_width > 1920 && buf_alloc_height > 1088)) {
6576 buf_alloc_width = 1920;
6577 buf_alloc_height = 1088;
6578 if (pbi->max_pic_w > 1920 && pbi->max_pic_h > 1088) {
6579 pbi->max_pic_w = 1920;
6580 pbi->max_pic_h = 1088;
6581 }
6582 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
6583 buf_alloc_width = 8192;
6584 buf_alloc_height = 4608;
6585 }
6586 pbi->init_pic_w = pbi->max_pic_w ? pbi->max_pic_w :
6587 (buf_alloc_width ? buf_alloc_width :
6588 (pbi->vvp9_amstream_dec_info.width ?
6589 pbi->vvp9_amstream_dec_info.width :
6590 pbi->work_space_buf->max_width));
6591 pbi->init_pic_h = pbi->max_pic_h ? pbi->max_pic_h :
6592 (buf_alloc_height ? buf_alloc_height :
6593 (pbi->vvp9_amstream_dec_info.height ?
6594 pbi->vvp9_amstream_dec_info.height :
6595 pbi->work_space_buf->max_height));
6596
6597 /* video is not support unaligned with 64 in tl1
6598 ** vdec canvas mode will be linear when dump yuv is set
6599 */
6600 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) &&
6601 (pbi->double_write_mode != 0) &&
6602 (((pbi->max_pic_w % 64) != 0) ||
6603 (pbi->vvp9_amstream_dec_info.width % 64) != 0)) {
6604 if (hw_to_vdec(pbi)->canvas_mode !=
6605 CANVAS_BLKMODE_LINEAR)
6606 pbi->mem_map_mode = 2;
6607 else {
6608 pbi->mem_map_mode = 0;
6609 pr_info("vdec blkmod linear, force mem_map_mode 0\n");
6610 }
6611 }
6612
6613#ifndef MV_USE_FIXED_BUF
6614 if (init_mv_buf_list(pbi) < 0) {
6615 pr_err("%s: init_mv_buf_list fail\n", __func__);
6616 return -1;
6617 }
6618#endif
6619 if (pbi->save_buffer_mode)
6620 pbi->used_buf_num = MAX_BUF_NUM_SAVE_BUF;
6621 else {
6622 if (pbi->is_used_v4l)
6623 pbi->used_buf_num = 5 + pbi->dynamic_buf_num_margin;
6624 else
6625 pbi->used_buf_num = max_buf_num;
6626 }
6627
6628 if (pbi->used_buf_num > MAX_BUF_NUM)
6629 pbi->used_buf_num = MAX_BUF_NUM;
6630 if (pbi->used_buf_num > FRAME_BUFFERS)
6631 pbi->used_buf_num = FRAME_BUFFERS;
6632
6633 pbi->pts_unstable = ((unsigned long)(pbi->vvp9_amstream_dec_info.param)
6634 & 0x40) >> 6;
6635
6636 if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0) {
6637 pbi->rpm_addr = dma_alloc_coherent(amports_get_dma_device(),
6638 RPM_BUF_SIZE,
6639 &pbi->rpm_phy_addr, GFP_KERNEL);
6640 if (pbi->rpm_addr == NULL) {
6641 pr_err("%s: failed to alloc rpm buffer\n", __func__);
6642 return -1;
6643 }
6644
6645 pbi->rpm_ptr = pbi->rpm_addr;
6646 }
6647
6648 pbi->lmem_addr = dma_alloc_coherent(amports_get_dma_device(),
6649 LMEM_BUF_SIZE,
6650 &pbi->lmem_phy_addr, GFP_KERNEL);
6651 if (pbi->lmem_addr == NULL) {
6652 pr_err("%s: failed to alloc lmem buffer\n", __func__);
6653 return -1;
6654 }
6655 pbi->lmem_ptr = pbi->lmem_addr;
6656
6657 pbi->prob_buffer_addr = dma_alloc_coherent(amports_get_dma_device(),
6658 PROB_BUF_SIZE,
6659 &pbi->prob_buffer_phy_addr, GFP_KERNEL);
6660 if (pbi->prob_buffer_addr == NULL) {
6661 pr_err("%s: failed to alloc prob_buffer\n", __func__);
6662 return -1;
6663 }
6664 memset(pbi->prob_buffer_addr, 0, PROB_BUF_SIZE);
6665 pbi->count_buffer_addr = dma_alloc_coherent(amports_get_dma_device(),
6666 COUNT_BUF_SIZE,
6667 &pbi->count_buffer_phy_addr, GFP_KERNEL);
6668 if (pbi->count_buffer_addr == NULL) {
6669 pr_err("%s: failed to alloc count_buffer\n", __func__);
6670 return -1;
6671 }
6672 memset(pbi->count_buffer_addr, 0, COUNT_BUF_SIZE);
6673
6674 if (pbi->mmu_enable) {
6675 u32 mmu_map_size = vvp9_frame_mmu_map_size(pbi);
6676 pbi->frame_mmu_map_addr =
6677 dma_alloc_coherent(amports_get_dma_device(),
6678 mmu_map_size,
6679 &pbi->frame_mmu_map_phy_addr, GFP_KERNEL);
6680 if (pbi->frame_mmu_map_addr == NULL) {
6681 pr_err("%s: failed to alloc count_buffer\n", __func__);
6682 return -1;
6683 }
6684 memset(pbi->frame_mmu_map_addr, 0, COUNT_BUF_SIZE);
6685 }
6686#ifdef SUPPORT_FB_DECODING
6687 if (pbi->m_ins_flag && stage_buf_num > 0) {
6688 pbi->stage_mmu_map_addr =
6689 dma_alloc_coherent(amports_get_dma_device(),
6690 STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS,
6691 &pbi->stage_mmu_map_phy_addr, GFP_KERNEL);
6692 if (pbi->stage_mmu_map_addr == NULL) {
6693 pr_err("%s: failed to alloc count_buffer\n", __func__);
6694 return -1;
6695 }
6696 memset(pbi->stage_mmu_map_addr,
6697 0, STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS);
6698
6699 init_stage_buf(pbi);
6700 }
6701#endif
6702
6703 ret = 0;
6704 return ret;
6705}
6706
6707/********************************************
6708 * Mailbox command
6709 ********************************************/
6710#define CMD_FINISHED 0
6711#define CMD_ALLOC_VIEW 1
6712#define CMD_FRAME_DISPLAY 3
6713#define CMD_DEBUG 10
6714
6715
6716#define DECODE_BUFFER_NUM_MAX 32
6717#define DISPLAY_BUFFER_NUM 6
6718
6719#define video_domain_addr(adr) (adr&0x7fffffff)
6720#define DECODER_WORK_SPACE_SIZE 0x800000
6721
6722#define spec2canvas(x) \
6723 (((x)->uv_canvas_index << 16) | \
6724 ((x)->uv_canvas_index << 8) | \
6725 ((x)->y_canvas_index << 0))
6726
6727
6728static void set_canvas(struct VP9Decoder_s *pbi,
6729 struct PIC_BUFFER_CONFIG_s *pic_config)
6730{
6731 struct vdec_s *vdec = hw_to_vdec(pbi);
6732 int canvas_w = ALIGN(pic_config->y_crop_width, 64)/4;
6733 int canvas_h = ALIGN(pic_config->y_crop_height, 32)/4;
6734 int blkmode = pbi->mem_map_mode;
6735 /*CANVAS_BLKMODE_64X32*/
6736 if (pic_config->double_write_mode) {
6737 canvas_w = pic_config->y_crop_width /
6738 get_double_write_ratio(pbi,
6739 pic_config->double_write_mode);
6740 canvas_h = pic_config->y_crop_height /
6741 get_double_write_ratio(pbi,
6742 pic_config->double_write_mode);
6743
6744 if (pbi->mem_map_mode == 0)
6745 canvas_w = ALIGN(canvas_w, 32);
6746 else
6747 canvas_w = ALIGN(canvas_w, 64);
6748 canvas_h = ALIGN(canvas_h, 32);
6749
6750 if (vdec->parallel_dec == 1) {
6751 if (pic_config->y_canvas_index == -1)
6752 pic_config->y_canvas_index =
6753 vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
6754 if (pic_config->uv_canvas_index == -1)
6755 pic_config->uv_canvas_index =
6756 vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
6757 } else {
6758 pic_config->y_canvas_index = 128 + pic_config->index * 2;
6759 pic_config->uv_canvas_index = 128 + pic_config->index * 2 + 1;
6760 }
6761
6762 canvas_config_ex(pic_config->y_canvas_index,
6763 pic_config->dw_y_adr, canvas_w, canvas_h,
6764 CANVAS_ADDR_NOWRAP, blkmode, pbi->is_used_v4l ? 0 : 7);
6765 canvas_config_ex(pic_config->uv_canvas_index,
6766 pic_config->dw_u_v_adr, canvas_w, canvas_h,
6767 CANVAS_ADDR_NOWRAP, blkmode, pbi->is_used_v4l ? 0 : 7);
6768
6769#ifdef MULTI_INSTANCE_SUPPORT
6770 pic_config->canvas_config[0].phy_addr =
6771 pic_config->dw_y_adr;
6772 pic_config->canvas_config[0].width =
6773 canvas_w;
6774 pic_config->canvas_config[0].height =
6775 canvas_h;
6776 pic_config->canvas_config[0].block_mode =
6777 blkmode;
6778 pic_config->canvas_config[0].endian = pbi->is_used_v4l ? 0 : 7;
6779
6780 pic_config->canvas_config[1].phy_addr =
6781 pic_config->dw_u_v_adr;
6782 pic_config->canvas_config[1].width =
6783 canvas_w;
6784 pic_config->canvas_config[1].height =
6785 canvas_h;
6786 pic_config->canvas_config[1].block_mode =
6787 blkmode;
6788 pic_config->canvas_config[1].endian = pbi->is_used_v4l ? 0 : 7;
6789#endif
6790 }
6791}
6792
6793
6794static void set_frame_info(struct VP9Decoder_s *pbi, struct vframe_s *vf)
6795{
6796 unsigned int ar;
6797 vf->duration = pbi->frame_dur;
6798 vf->duration_pulldown = 0;
6799 vf->flag = 0;
6800 vf->prop.master_display_colour = pbi->vf_dp;
6801 vf->signal_type = pbi->video_signal_type;
6802 if (vf->compWidth && vf->compHeight)
6803 pbi->frame_ar = vf->compHeight * 0x100 / vf->compWidth;
6804 ar = min_t(u32, pbi->frame_ar, DISP_RATIO_ASPECT_RATIO_MAX);
6805 vf->ratio_control = (ar << DISP_RATIO_ASPECT_RATIO_BIT);
6806
6807 if (pbi->is_used_v4l && pbi->vf_dp.present_flag) {
6808 struct aml_vdec_hdr_infos hdr;
6809 struct aml_vcodec_ctx *ctx =
6810 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
6811
6812 memset(&hdr, 0, sizeof(hdr));
6813 hdr.signal_type = vf->signal_type;
6814 hdr.color_parms = pbi->vf_dp;
6815 vdec_v4l_set_hdr_infos(ctx, &hdr);
6816 }
6817}
6818
6819static int vvp9_vf_states(struct vframe_states *states, void *op_arg)
6820{
6821 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6822
6823 states->vf_pool_size = VF_POOL_SIZE;
6824 states->buf_free_num = kfifo_len(&pbi->newframe_q);
6825 states->buf_avail_num = kfifo_len(&pbi->display_q);
6826
6827 if (step == 2)
6828 states->buf_avail_num = 0;
6829 return 0;
6830}
6831
6832static struct vframe_s *vvp9_vf_peek(void *op_arg)
6833{
6834 struct vframe_s *vf[2] = {0, 0};
6835 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6836
6837 if (step == 2)
6838 return NULL;
6839
6840 if (kfifo_out_peek(&pbi->display_q, (void *)&vf, 2)) {
6841 if (vf[1]) {
6842 vf[0]->next_vf_pts_valid = true;
6843 vf[0]->next_vf_pts = vf[1]->pts;
6844 } else
6845 vf[0]->next_vf_pts_valid = false;
6846 return vf[0];
6847 }
6848
6849 return NULL;
6850}
6851
6852static struct vframe_s *vvp9_vf_get(void *op_arg)
6853{
6854 struct vframe_s *vf;
6855 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6856
6857 if (step == 2)
6858 return NULL;
6859 else if (step == 1)
6860 step = 2;
6861
6862 if (kfifo_get(&pbi->display_q, &vf)) {
6863 struct vframe_s *next_vf;
6864 uint8_t index = vf->index & 0xff;
6865 if (index < pbi->used_buf_num ||
6866 (vf->type & VIDTYPE_V4L_EOS)) {
6867 vf->index_disp = pbi->vf_get_count;
6868 pbi->vf_get_count++;
6869 if (debug & VP9_DEBUG_BUFMGR)
6870 pr_info("%s type 0x%x w/h %d/%d, pts %d, %lld\n",
6871 __func__, vf->type,
6872 vf->width, vf->height,
6873 vf->pts,
6874 vf->pts_us64);
6875
6876 if (kfifo_peek(&pbi->display_q, &next_vf)) {
6877 vf->next_vf_pts_valid = true;
6878 vf->next_vf_pts = next_vf->pts;
6879 } else
6880 vf->next_vf_pts_valid = false;
6881
6882 return vf;
6883 }
6884 }
6885 return NULL;
6886}
6887
6888static void vvp9_vf_put(struct vframe_s *vf, void *op_arg)
6889{
6890 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6891 uint8_t index = vf->index & 0xff;
6892
6893 if (vf == (&pbi->vframe_dummy))
6894 return;
6895
6896 kfifo_put(&pbi->newframe_q, (const struct vframe_s *)vf);
6897 pbi->vf_put_count++;
6898 if (index < pbi->used_buf_num) {
6899 struct VP9_Common_s *cm = &pbi->common;
6900 struct BufferPool_s *pool = cm->buffer_pool;
6901 unsigned long flags;
6902
6903 lock_buffer_pool(pool, flags);
6904 if (pool->frame_bufs[index].buf.vf_ref > 0)
6905 pool->frame_bufs[index].buf.vf_ref--;
6906
6907 if (pbi->is_used_v4l)
6908 pool->frame_bufs[index].buf.vframe_bound = true;
6909
6910 if (pbi->wait_buf)
6911 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG,
6912 0x1);
6913 pbi->last_put_idx = index;
6914 pbi->new_frame_displayed++;
6915 unlock_buffer_pool(pool, flags);
6916#ifdef SUPPORT_FB_DECODING
6917 if (pbi->used_stage_buf_num > 0 &&
6918 pbi->back_not_run_ready)
6919 trigger_schedule(pbi);
6920#endif
6921 }
6922
6923}
6924
6925static int vvp9_event_cb(int type, void *data, void *private_data)
6926{
6927 if (type & VFRAME_EVENT_RECEIVER_RESET) {
6928#if 0
6929 unsigned long flags;
6930
6931 amhevc_stop();
6932#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
6933 vf_light_unreg_provider(&vvp9_vf_prov);
6934#endif
6935 spin_lock_irqsave(&pbi->lock, flags);
6936 vvp9_local_init();
6937 vvp9_prot_init();
6938 spin_unlock_irqrestore(&pbi->lock, flags);
6939#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
6940 vf_reg_provider(&vvp9_vf_prov);
6941#endif
6942 amhevc_start();
6943#endif
6944 }
6945
6946 return 0;
6947}
6948
6949void inc_vf_ref(struct VP9Decoder_s *pbi, int index)
6950{
6951 struct VP9_Common_s *cm = &pbi->common;
6952
6953 cm->buffer_pool->frame_bufs[index].buf.vf_ref++;
6954
6955 if (debug & VP9_DEBUG_BUFMGR_MORE)
6956 pr_info("%s index = %d new vf_ref = %d\r\n",
6957 __func__, index,
6958 cm->buffer_pool->frame_bufs[index].buf.vf_ref);
6959}
6960
6961static int frame_duration_adapt(struct VP9Decoder_s *pbi, struct vframe_s *vf, u32 valid)
6962{
6963 u32 old_duration, pts_duration = 0;
6964 u32 pts = vf->pts;
6965
6966 if (pbi->get_frame_dur == true)
6967 return true;
6968
6969 pbi->frame_cnt_window++;
6970 if (!(pbi->vp9_first_pts_ready == 1)) {
6971 if (valid) {
6972 pbi->pts1 = pts;
6973 pbi->frame_cnt_window = 0;
6974 pbi->duration_from_pts_done = 0;
6975 pbi->vp9_first_pts_ready = 1;
6976 } else {
6977 return false;
6978 }
6979 } else {
6980 if (pts < pbi->pts1) {
6981 if (pbi->frame_cnt_window > FRAME_CNT_WINDOW_SIZE) {
6982 pbi->pts1 = pts;
6983 pbi->frame_cnt_window = 0;
6984 }
6985 }
6986
6987 if (valid && (pbi->frame_cnt_window > FRAME_CNT_WINDOW_SIZE) &&
6988 (pts > pbi->pts1) && (pbi->duration_from_pts_done == 0)) {
6989 old_duration = pbi->frame_dur;
6990 pbi->pts2 = pts;
6991 pts_duration = (((pbi->pts2 - pbi->pts1) * 16) /
6992 (pbi->frame_cnt_window * 15));
6993
6994 if (close_to(pts_duration, old_duration, 2000)) {
6995 pbi->frame_dur = pts_duration;
6996 if ((debug & VP9_DEBUG_OUT_PTS) != 0)
6997 pr_info("use calc duration %d\n", pts_duration);
6998 }
6999
7000 if (pbi->duration_from_pts_done == 0) {
7001 if (close_to(pts_duration, old_duration, RATE_CORRECTION_THRESHOLD)) {
7002 pbi->duration_from_pts_done = 1;
7003 } else {
7004 if (!close_to(pts_duration,
7005 old_duration, 1000) &&
7006 !close_to(pts_duration,
7007 pbi->frame_dur, 1000) &&
7008 close_to(pts_duration,
7009 pbi->last_duration, 200)) {
7010 /* frame_dur must
7011 * wrong,recover it.
7012 */
7013 pbi->frame_dur = pts_duration;
7014 }
7015 pbi->pts1 = pbi->pts2;
7016 pbi->frame_cnt_window = 0;
7017 pbi->duration_from_pts_done = 0;
7018 }
7019 }
7020 pbi->last_duration = pts_duration;
7021 }
7022 }
7023 return true;
7024}
7025
7026static void update_vf_memhandle(struct VP9Decoder_s *pbi,
7027 struct vframe_s *vf, struct PIC_BUFFER_CONFIG_s *pic)
7028{
7029 if (pic->index < 0) {
7030 vf->mem_handle = NULL;
7031 vf->mem_head_handle = NULL;
7032 } else if (vf->type & VIDTYPE_SCATTER) {
7033 vf->mem_handle =
7034 decoder_mmu_box_get_mem_handle(
7035 pbi->mmu_box, pic->index);
7036 vf->mem_head_handle =
7037 decoder_bmmu_box_get_mem_handle(
7038 pbi->bmmu_box,
7039 HEADER_BUFFER_IDX(pic->BUF_index));
7040 } else {
7041 vf->mem_handle =
7042 decoder_bmmu_box_get_mem_handle(
7043 pbi->bmmu_box, VF_BUFFER_IDX(pic->BUF_index));
7044 vf->mem_head_handle = NULL;
7045 /*vf->mem_head_handle =
7046 *decoder_bmmu_box_get_mem_handle(
7047 *hevc->bmmu_box, VF_BUFFER_IDX(BUF_index));
7048 */
7049 }
7050}
7051
7052static inline void pbi_update_gvs(struct VP9Decoder_s *pbi)
7053{
7054 if (pbi->gvs->frame_height != frame_height) {
7055 pbi->gvs->frame_width = frame_width;
7056 pbi->gvs->frame_height = frame_height;
7057 }
7058 if (pbi->gvs->frame_dur != pbi->frame_dur) {
7059 pbi->gvs->frame_dur = pbi->frame_dur;
7060 if (pbi->frame_dur != 0)
7061 pbi->gvs->frame_rate = 96000 / pbi->frame_dur;
7062 else
7063 pbi->gvs->frame_rate = -1;
7064 }
7065 pbi->gvs->status = pbi->stat | pbi->fatal_error;
7066}
7067
7068static int prepare_display_buf(struct VP9Decoder_s *pbi,
7069 struct PIC_BUFFER_CONFIG_s *pic_config)
7070{
7071 struct vframe_s *vf = NULL;
7072 struct vdec_s *pvdec = hw_to_vdec(pbi);
7073 int stream_offset = pic_config->stream_offset;
7074 unsigned short slice_type = pic_config->slice_type;
7075 struct aml_vcodec_ctx * v4l2_ctx = pbi->v4l2_ctx;
7076 ulong nv_order = VIDTYPE_VIU_NV21;
7077 u32 pts_valid = 0, pts_us64_valid = 0;
7078 u32 pts_save;
7079 u64 pts_us64_save;
7080 u32 frame_size = 0;
7081
7082
7083 if (debug & VP9_DEBUG_BUFMGR)
7084 pr_info("%s index = %d\r\n", __func__, pic_config->index);
7085 if (kfifo_get(&pbi->newframe_q, &vf) == 0) {
7086 pr_info("fatal error, no available buffer slot.");
7087 return -1;
7088 }
7089
7090 /* swap uv */
7091 if (pbi->is_used_v4l) {
7092 if ((v4l2_ctx->cap_pix_fmt == V4L2_PIX_FMT_NV12) ||
7093 (v4l2_ctx->cap_pix_fmt == V4L2_PIX_FMT_NV12M))
7094 nv_order = VIDTYPE_VIU_NV12;
7095 }
7096
7097 if (pic_config->double_write_mode)
7098 set_canvas(pbi, pic_config);
7099
7100 display_frame_count[pbi->index]++;
7101 if (vf) {
7102 if (pbi->is_used_v4l) {
7103 vf->v4l_mem_handle
7104 = pbi->m_BUF[pic_config->BUF_index].v4l_ref_buf_addr;
7105 if (pbi->mmu_enable) {
7106 vf->mm_box.bmmu_box = pbi->bmmu_box;
7107 vf->mm_box.bmmu_idx = HEADER_BUFFER_IDX(pic_config->BUF_index);
7108 vf->mm_box.mmu_box = pbi->mmu_box;
7109 vf->mm_box.mmu_idx = pic_config->index;
7110 }
7111 }
7112
7113#ifdef MULTI_INSTANCE_SUPPORT
7114 if (vdec_frame_based(pvdec)) {
7115 vf->pts = pic_config->pts;
7116 vf->pts_us64 = pic_config->pts64;
7117 vf->timestamp = pic_config->timestamp;
7118 if (vf->pts != 0 || vf->pts_us64 != 0) {
7119 pts_valid = 1;
7120 pts_us64_valid = 1;
7121 } else {
7122 pts_valid = 0;
7123 pts_us64_valid = 0;
7124 }
7125 } else
7126#endif
7127 /* if (pts_lookup_offset(PTS_TYPE_VIDEO,
7128 * stream_offset, &vf->pts, 0) != 0) {
7129 */
7130 if (pts_lookup_offset_us64
7131 (PTS_TYPE_VIDEO, stream_offset, &vf->pts,
7132 &frame_size, 0,
7133 &vf->pts_us64) != 0) {
7134#ifdef DEBUG_PTS
7135 pbi->pts_missed++;
7136#endif
7137 vf->pts = 0;
7138 vf->pts_us64 = 0;
7139 pts_valid = 0;
7140 pts_us64_valid = 0;
7141 } else {
7142#ifdef DEBUG_PTS
7143 pbi->pts_hit++;
7144#endif
7145 pts_valid = 1;
7146 pts_us64_valid = 1;
7147 }
7148
7149 fill_frame_info(pbi, pic_config, frame_size, vf->pts);
7150
7151 pts_save = vf->pts;
7152 pts_us64_save = vf->pts_us64;
7153 if (pbi->pts_unstable) {
7154 frame_duration_adapt(pbi, vf, pts_valid);
7155 if (pbi->duration_from_pts_done) {
7156 pbi->pts_mode = PTS_NONE_REF_USE_DURATION;
7157 } else {
7158 if (pts_valid || pts_us64_valid)
7159 pbi->pts_mode = PTS_NORMAL;
7160 }
7161 }
7162
7163 if ((pbi->pts_mode == PTS_NORMAL) && (vf->pts != 0)
7164 && pbi->get_frame_dur) {
7165 int pts_diff = (int)vf->pts - pbi->last_lookup_pts;
7166
7167 if (pts_diff < 0) {
7168 pbi->pts_mode_switching_count++;
7169 pbi->pts_mode_recovery_count = 0;
7170
7171 if (pbi->pts_mode_switching_count >=
7172 PTS_MODE_SWITCHING_THRESHOLD) {
7173 pbi->pts_mode =
7174 PTS_NONE_REF_USE_DURATION;
7175 pr_info
7176 ("HEVC: switch to n_d mode.\n");
7177 }
7178
7179 } else {
7180 int p = PTS_MODE_SWITCHING_RECOVERY_THREASHOLD;
7181
7182 pbi->pts_mode_recovery_count++;
7183 if (pbi->pts_mode_recovery_count > p) {
7184 pbi->pts_mode_switching_count = 0;
7185 pbi->pts_mode_recovery_count = 0;
7186 }
7187 }
7188 }
7189
7190 if (vf->pts != 0)
7191 pbi->last_lookup_pts = vf->pts;
7192
7193 if ((pbi->pts_mode == PTS_NONE_REF_USE_DURATION)
7194 && (slice_type != KEY_FRAME))
7195 vf->pts = pbi->last_pts + DUR2PTS(pbi->frame_dur);
7196 pbi->last_pts = vf->pts;
7197
7198 if (vf->pts_us64 != 0)
7199 pbi->last_lookup_pts_us64 = vf->pts_us64;
7200
7201 if ((pbi->pts_mode == PTS_NONE_REF_USE_DURATION)
7202 && (slice_type != KEY_FRAME)) {
7203 vf->pts_us64 =
7204 pbi->last_pts_us64 +
7205 (DUR2PTS(pbi->frame_dur) * 100 / 9);
7206 }
7207 pbi->last_pts_us64 = vf->pts_us64;
7208 if ((debug & VP9_DEBUG_OUT_PTS) != 0) {
7209 pr_info
7210 ("VP9 dec out pts: pts_mode=%d,dur=%d,pts(%d,%lld)(%d,%lld)\n",
7211 pbi->pts_mode, pbi->frame_dur, vf->pts,
7212 vf->pts_us64, pts_save, pts_us64_save);
7213 }
7214
7215 if (pbi->pts_mode == PTS_NONE_REF_USE_DURATION) {
7216 vf->disp_pts = vf->pts;
7217 vf->disp_pts_us64 = vf->pts_us64;
7218 vf->pts = pts_save;
7219 vf->pts_us64 = pts_us64_save;
7220 } else {
7221 vf->disp_pts = 0;
7222 vf->disp_pts_us64 = 0;
7223 }
7224
7225 vf->index = 0xff00 | pic_config->index;
7226
7227 if (pic_config->double_write_mode & 0x10) {
7228 /* double write only */
7229 vf->compBodyAddr = 0;
7230 vf->compHeadAddr = 0;
7231 } else {
7232 if (pbi->mmu_enable) {
7233 vf->compBodyAddr = 0;
7234 vf->compHeadAddr = pic_config->header_adr;
7235 } else {
7236 /*vf->compBodyAddr = pic_config->mc_y_adr;
7237 *vf->compHeadAddr = pic_config->mc_y_adr +
7238 *pic_config->comp_body_size; */
7239 /*head adr*/
7240 }
7241 vf->canvas0Addr = vf->canvas1Addr = 0;
7242 }
7243 if (pic_config->double_write_mode) {
7244 vf->type = VIDTYPE_PROGRESSIVE |
7245 VIDTYPE_VIU_FIELD;
7246 vf->type |= nv_order;
7247 if ((pic_config->double_write_mode == 3) &&
7248 (!IS_8K_SIZE(pic_config->y_crop_width,
7249 pic_config->y_crop_height))) {
7250 vf->type |= VIDTYPE_COMPRESS;
7251 if (pbi->mmu_enable)
7252 vf->type |= VIDTYPE_SCATTER;
7253 }
7254#ifdef MULTI_INSTANCE_SUPPORT
7255 if (pbi->m_ins_flag) {
7256 vf->canvas0Addr = vf->canvas1Addr = -1;
7257 vf->plane_num = 2;
7258 vf->canvas0_config[0] =
7259 pic_config->canvas_config[0];
7260 vf->canvas0_config[1] =
7261 pic_config->canvas_config[1];
7262 vf->canvas1_config[0] =
7263 pic_config->canvas_config[0];
7264 vf->canvas1_config[1] =
7265 pic_config->canvas_config[1];
7266
7267 } else
7268#endif
7269 vf->canvas0Addr = vf->canvas1Addr =
7270 spec2canvas(pic_config);
7271 } else {
7272 vf->canvas0Addr = vf->canvas1Addr = 0;
7273 vf->type = VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
7274 if (pbi->mmu_enable)
7275 vf->type |= VIDTYPE_SCATTER;
7276 }
7277
7278 switch (pic_config->bit_depth) {
7279 case VPX_BITS_8:
7280 vf->bitdepth = BITDEPTH_Y8 |
7281 BITDEPTH_U8 | BITDEPTH_V8;
7282 break;
7283 case VPX_BITS_10:
7284 case VPX_BITS_12:
7285 vf->bitdepth = BITDEPTH_Y10 |
7286 BITDEPTH_U10 | BITDEPTH_V10;
7287 break;
7288 default:
7289 vf->bitdepth = BITDEPTH_Y10 |
7290 BITDEPTH_U10 | BITDEPTH_V10;
7291 break;
7292 }
7293 if ((vf->type & VIDTYPE_COMPRESS) == 0)
7294 vf->bitdepth =
7295 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
7296 if (pic_config->bit_depth == VPX_BITS_8)
7297 vf->bitdepth |= BITDEPTH_SAVING_MODE;
7298
7299 /* if((vf->width!=pic_config->width)|
7300 * (vf->height!=pic_config->height))
7301 */
7302 /* pr_info("aaa: %d/%d, %d/%d\n",
7303 vf->width,vf->height, pic_config->width,
7304 pic_config->height); */
7305 vf->width = pic_config->y_crop_width /
7306 get_double_write_ratio(pbi,
7307 pic_config->double_write_mode);
7308 vf->height = pic_config->y_crop_height /
7309 get_double_write_ratio(pbi,
7310 pic_config->double_write_mode);
7311 if (force_w_h != 0) {
7312 vf->width = (force_w_h >> 16) & 0xffff;
7313 vf->height = force_w_h & 0xffff;
7314 }
7315 vf->compWidth = pic_config->y_crop_width;
7316 vf->compHeight = pic_config->y_crop_height;
7317 set_frame_info(pbi, vf);
7318 if (force_fps & 0x100) {
7319 u32 rate = force_fps & 0xff;
7320
7321 if (rate)
7322 vf->duration = 96000/rate;
7323 else
7324 vf->duration = 0;
7325 }
7326 update_vf_memhandle(pbi, vf, pic_config);
7327 if (!(pic_config->y_crop_width == 196
7328 && pic_config->y_crop_height == 196
7329 && (debug & VP9_DEBUG_NO_TRIGGER_FRAME) == 0
7330 && (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX))) {
7331 struct vdec_info tmp4x;
7332
7333 inc_vf_ref(pbi, pic_config->index);
7334 decoder_do_frame_check(pvdec, vf);
7335 kfifo_put(&pbi->display_q, (const struct vframe_s *)vf);
7336 ATRACE_COUNTER(MODULE_NAME, vf->pts);
7337 pbi->vf_pre_count++;
7338 pbi_update_gvs(pbi);
7339 /*count info*/
7340 vdec_count_info(pbi->gvs, 0, stream_offset);
7341 memcpy(&tmp4x, pbi->gvs, sizeof(struct vdec_info));
7342 tmp4x.bit_depth_luma = pbi->vp9_param.p.bit_depth;
7343 tmp4x.bit_depth_chroma = pbi->vp9_param.p.bit_depth;
7344 tmp4x.double_write_mode = get_double_write_mode(pbi);
7345 vdec_fill_vdec_frame(pvdec, &pbi->vframe_qos, &tmp4x,
7346 vf, pic_config->hw_decode_time);
7347 pvdec->vdec_fps_detec(pvdec->id);
7348 if (without_display_mode == 0) {
7349 vf_notify_receiver(pbi->provider_name,
7350 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
7351 } else
7352 vvp9_vf_put(vvp9_vf_get(pbi), pbi);
7353 } else {
7354 pbi->stat |= VP9_TRIGGER_FRAME_DONE;
7355 hevc_source_changed(VFORMAT_VP9, 196, 196, 30);
7356 pr_debug("[%s %d] drop trigger frame width %d height %d state 0x%x\n",
7357 __func__, __LINE__, vf->width,
7358 vf->height, pbi->stat);
7359 }
7360 }
7361
7362 return 0;
7363}
7364
7365static int notify_v4l_eos(struct vdec_s *vdec)
7366{
7367 struct VP9Decoder_s *hw = (struct VP9Decoder_s *)vdec->private;
7368 struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
7369 struct vframe_s *vf = &hw->vframe_dummy;
7370 struct vdec_v4l2_buffer *fb = NULL;
7371 int index = INVALID_IDX;
7372 ulong expires;
7373
7374 if (hw->is_used_v4l && hw->eos) {
7375 expires = jiffies + msecs_to_jiffies(2000);
7376 while (INVALID_IDX == (index = v4l_get_free_fb(hw))) {
7377 if (time_after(jiffies, expires) ||
7378 v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx))
7379 break;
7380 }
7381
7382 if (index == INVALID_IDX) {
7383 if (vdec_v4l_get_buffer(hw->v4l2_ctx, &fb) < 0) {
7384 pr_err("[%d] EOS get free buff fail.\n", ctx->id);
7385 return -1;
7386 }
7387 }
7388
7389 vf->type |= VIDTYPE_V4L_EOS;
7390 vf->timestamp = ULONG_MAX;
7391 vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L;
7392 vf->v4l_mem_handle = (index == INVALID_IDX) ? (ulong)fb :
7393 hw->m_BUF[index].v4l_ref_buf_addr;
7394
7395 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
7396 vf_notify_receiver(vdec->vf_provider_name,
7397 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
7398
7399 pr_info("[%d] VP9 EOS notify.\n", ctx->id);
7400 }
7401
7402 return 0;
7403}
7404
7405static void get_rpm_param(union param_u *params)
7406{
7407 int i;
7408 unsigned int data32;
7409
7410 if (debug & VP9_DEBUG_BUFMGR)
7411 pr_info("enter %s\r\n", __func__);
7412 for (i = 0; i < 128; i++) {
7413 do {
7414 data32 = READ_VREG(RPM_CMD_REG);
7415 /*pr_info("%x\n", data32);*/
7416 } while ((data32 & 0x10000) == 0);
7417 params->l.data[i] = data32&0xffff;
7418 /*pr_info("%x\n", data32);*/
7419 WRITE_VREG(RPM_CMD_REG, 0);
7420 }
7421 if (debug & VP9_DEBUG_BUFMGR)
7422 pr_info("leave %s\r\n", __func__);
7423}
7424static void debug_buffer_mgr_more(struct VP9Decoder_s *pbi)
7425{
7426 int i;
7427
7428 if (!(debug & VP9_DEBUG_BUFMGR_MORE))
7429 return;
7430 pr_info("vp9_param: (%d)\n", pbi->slice_idx);
7431 for (i = 0; i < (RPM_END-RPM_BEGIN); i++) {
7432 pr_info("%04x ", pbi->vp9_param.l.data[i]);
7433 if (((i + 1) & 0xf) == 0)
7434 pr_info("\n");
7435 }
7436 pr_info("=============param==========\r\n");
7437 pr_info("profile %x\r\n", pbi->vp9_param.p.profile);
7438 pr_info("show_existing_frame %x\r\n",
7439 pbi->vp9_param.p.show_existing_frame);
7440 pr_info("frame_to_show_idx %x\r\n",
7441 pbi->vp9_param.p.frame_to_show_idx);
7442 pr_info("frame_type %x\r\n", pbi->vp9_param.p.frame_type);
7443 pr_info("show_frame %x\r\n", pbi->vp9_param.p.show_frame);
7444 pr_info("e.r.r.o.r_resilient_mode %x\r\n",
7445 pbi->vp9_param.p.error_resilient_mode);
7446 pr_info("intra_only %x\r\n", pbi->vp9_param.p.intra_only);
7447 pr_info("display_size_present %x\r\n",
7448 pbi->vp9_param.p.display_size_present);
7449 pr_info("reset_frame_context %x\r\n",
7450 pbi->vp9_param.p.reset_frame_context);
7451 pr_info("refresh_frame_flags %x\r\n",
7452 pbi->vp9_param.p.refresh_frame_flags);
7453 pr_info("bit_depth %x\r\n", pbi->vp9_param.p.bit_depth);
7454 pr_info("width %x\r\n", pbi->vp9_param.p.width);
7455 pr_info("height %x\r\n", pbi->vp9_param.p.height);
7456 pr_info("display_width %x\r\n", pbi->vp9_param.p.display_width);
7457 pr_info("display_height %x\r\n", pbi->vp9_param.p.display_height);
7458 pr_info("ref_info %x\r\n", pbi->vp9_param.p.ref_info);
7459 pr_info("same_frame_size %x\r\n", pbi->vp9_param.p.same_frame_size);
7460 if (!(debug & VP9_DEBUG_DBG_LF_PRINT))
7461 return;
7462 pr_info("mode_ref_delta_enabled: 0x%x\r\n",
7463 pbi->vp9_param.p.mode_ref_delta_enabled);
7464 pr_info("sharpness_level: 0x%x\r\n",
7465 pbi->vp9_param.p.sharpness_level);
7466 pr_info("ref_deltas: 0x%x, 0x%x, 0x%x, 0x%x\r\n",
7467 pbi->vp9_param.p.ref_deltas[0], pbi->vp9_param.p.ref_deltas[1],
7468 pbi->vp9_param.p.ref_deltas[2], pbi->vp9_param.p.ref_deltas[3]);
7469 pr_info("mode_deltas: 0x%x, 0x%x\r\n", pbi->vp9_param.p.mode_deltas[0],
7470 pbi->vp9_param.p.mode_deltas[1]);
7471 pr_info("filter_level: 0x%x\r\n", pbi->vp9_param.p.filter_level);
7472 pr_info("seg_enabled: 0x%x\r\n", pbi->vp9_param.p.seg_enabled);
7473 pr_info("seg_abs_delta: 0x%x\r\n", pbi->vp9_param.p.seg_abs_delta);
7474 pr_info("seg_lf_feature_enabled: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\r\n",
7475 (pbi->vp9_param.p.seg_lf_info[0]>>15 & 1),
7476 (pbi->vp9_param.p.seg_lf_info[1]>>15 & 1),
7477 (pbi->vp9_param.p.seg_lf_info[2]>>15 & 1),
7478 (pbi->vp9_param.p.seg_lf_info[3]>>15 & 1),
7479 (pbi->vp9_param.p.seg_lf_info[4]>>15 & 1),
7480 (pbi->vp9_param.p.seg_lf_info[5]>>15 & 1),
7481 (pbi->vp9_param.p.seg_lf_info[6]>>15 & 1),
7482 (pbi->vp9_param.p.seg_lf_info[7]>>15 & 1));
7483 pr_info("seg_lf_feature_data: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\r\n",
7484 (pbi->vp9_param.p.seg_lf_info[0] & 0x13f),
7485 (pbi->vp9_param.p.seg_lf_info[1] & 0x13f),
7486 (pbi->vp9_param.p.seg_lf_info[2] & 0x13f),
7487 (pbi->vp9_param.p.seg_lf_info[3] & 0x13f),
7488 (pbi->vp9_param.p.seg_lf_info[4] & 0x13f),
7489 (pbi->vp9_param.p.seg_lf_info[5] & 0x13f),
7490 (pbi->vp9_param.p.seg_lf_info[6] & 0x13f),
7491 (pbi->vp9_param.p.seg_lf_info[7] & 0x13f));
7492
7493}
7494
7495
7496static void vp9_recycle_mmu_buf_tail(struct VP9Decoder_s *pbi)
7497{
7498 struct VP9_Common_s *const cm = &pbi->common;
7499 if (pbi->double_write_mode & 0x10)
7500 return;
7501 if (cm->cur_fb_idx_mmu != INVALID_IDX) {
7502 if (pbi->used_4k_num == -1) {
7503 pbi->used_4k_num =
7504 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
7505 if (pbi->m_ins_flag)
7506 hevc_mmu_dma_check(hw_to_vdec(pbi));
7507 }
7508 decoder_mmu_box_free_idx_tail(pbi->mmu_box,
7509 cm->cur_fb_idx_mmu, pbi->used_4k_num);
7510 cm->cur_fb_idx_mmu = INVALID_IDX;
7511 pbi->used_4k_num = -1;
7512 }
7513}
7514
7515#ifdef MULTI_INSTANCE_SUPPORT
7516static void vp9_recycle_mmu_buf(struct VP9Decoder_s *pbi)
7517{
7518 struct VP9_Common_s *const cm = &pbi->common;
7519 if (pbi->double_write_mode & 0x10)
7520 return;
7521 if (cm->cur_fb_idx_mmu != INVALID_IDX) {
7522 decoder_mmu_box_free_idx(pbi->mmu_box,
7523 cm->cur_fb_idx_mmu);
7524
7525 cm->cur_fb_idx_mmu = INVALID_IDX;
7526 pbi->used_4k_num = -1;
7527 }
7528}
7529
7530void vp9_recycle_mmu_work(struct work_struct *work)
7531{
7532 struct VP9Decoder_s *pbi = container_of(work,
7533 struct VP9Decoder_s, recycle_mmu_work);
7534
7535 vp9_recycle_mmu_buf(pbi);
7536}
7537#endif
7538
7539
7540static void dec_again_process(struct VP9Decoder_s *pbi)
7541{
7542 amhevc_stop();
7543 pbi->dec_result = DEC_RESULT_AGAIN;
7544 if (pbi->process_state ==
7545 PROC_STATE_DECODESLICE) {
7546 pbi->process_state =
7547 PROC_STATE_SENDAGAIN;
7548 if (pbi->mmu_enable) {
7549 /*
7550 * Because vp9_recycle_mmu_buf has sleep function,we can't
7551 * call it directly. Use a recycle_mmu_work to substitude it.
7552 */
7553 vdec_schedule_work(&pbi->recycle_mmu_work);
7554 }
7555 }
7556 reset_process_time(pbi);
7557 vdec_schedule_work(&pbi->work);
7558}
7559
7560int continue_decoding(struct VP9Decoder_s *pbi)
7561{
7562 int ret;
7563 int i;
7564 struct VP9_Common_s *const cm = &pbi->common;
7565 struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
7566 debug_buffer_mgr_more(pbi);
7567
7568 if (pbi->is_used_v4l && ctx->param_sets_from_ucode)
7569 pbi->res_ch_flag = 0;
7570 bit_depth_luma = pbi->vp9_param.p.bit_depth;
7571 bit_depth_chroma = pbi->vp9_param.p.bit_depth;
7572
7573 if ((pbi->vp9_param.p.bit_depth >= VPX_BITS_10) &&
7574 (get_double_write_mode(pbi) == 0x10)) {
7575 pbi->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
7576 pr_err("fatal err, bit_depth %d, unsupport dw 0x10\n",
7577 pbi->vp9_param.p.bit_depth);
7578 return -1;
7579 }
7580
7581 if (pbi->process_state != PROC_STATE_SENDAGAIN) {
7582 ret = vp9_bufmgr_process(pbi, &pbi->vp9_param);
7583 if (!pbi->m_ins_flag)
7584 pbi->slice_idx++;
7585 } else {
7586 union param_u *params = &pbi->vp9_param;
7587 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
7588 ret = vp9_alloc_mmu(pbi,
7589 cm->new_fb_idx,
7590 params->p.width,
7591 params->p.height,
7592 params->p.bit_depth,
7593 pbi->frame_mmu_map_addr);
7594 if (ret >= 0)
7595 cm->cur_fb_idx_mmu = cm->new_fb_idx;
7596 else
7597 pr_err("can't alloc need mmu1,idx %d ret =%d\n",
7598 cm->new_fb_idx,
7599 ret);
7600 } else {
7601 ret = 0;
7602 }
7603 WRITE_VREG(HEVC_PARSER_PICTURE_SIZE,
7604 (params->p.height << 16) | params->p.width);
7605 }
7606 if (ret < 0) {
7607 pr_info("vp9_bufmgr_process=> %d, VP9_10B_DISCARD_NAL\r\n",
7608 ret);
7609 WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DISCARD_NAL);
7610 cm->show_frame = 0;
7611 if (pbi->mmu_enable)
7612 vp9_recycle_mmu_buf(pbi);
7613#ifdef MULTI_INSTANCE_SUPPORT
7614 if (pbi->m_ins_flag) {
7615 pbi->dec_result = DEC_RESULT_DONE;
7616#ifdef SUPPORT_FB_DECODING
7617 if (pbi->used_stage_buf_num == 0)
7618#endif
7619 amhevc_stop();
7620 vdec_schedule_work(&pbi->work);
7621 }
7622#endif
7623 return ret;
7624 } else if (ret == 0) {
7625 struct PIC_BUFFER_CONFIG_s *cur_pic_config
7626 = &cm->cur_frame->buf;
7627 cur_pic_config->decode_idx = pbi->frame_count;
7628
7629 if (pbi->process_state != PROC_STATE_SENDAGAIN) {
7630 if (!pbi->m_ins_flag) {
7631 pbi->frame_count++;
7632 decode_frame_count[pbi->index]
7633 = pbi->frame_count;
7634 }
7635#ifdef MULTI_INSTANCE_SUPPORT
7636 if (pbi->chunk) {
7637 cur_pic_config->pts = pbi->chunk->pts;
7638 cur_pic_config->pts64 = pbi->chunk->pts64;
7639 cur_pic_config->timestamp = pbi->chunk->timestamp;
7640 }
7641#endif
7642 }
7643 /*pr_info("Decode Frame Data %d\n", pbi->frame_count);*/
7644 config_pic_size(pbi, pbi->vp9_param.p.bit_depth);
7645
7646 if ((pbi->common.frame_type != KEY_FRAME)
7647 && (!pbi->common.intra_only)) {
7648 config_mc_buffer(pbi, pbi->vp9_param.p.bit_depth);
7649#ifdef SUPPORT_FB_DECODING
7650 if (pbi->used_stage_buf_num == 0)
7651#endif
7652 config_mpred_hw(pbi);
7653 } else {
7654#ifdef SUPPORT_FB_DECODING
7655 if (pbi->used_stage_buf_num == 0)
7656#endif
7657 clear_mpred_hw(pbi);
7658 }
7659#ifdef MCRCC_ENABLE
7660 if (mcrcc_cache_alg_flag)
7661 config_mcrcc_axi_hw_new(pbi);
7662 else
7663 config_mcrcc_axi_hw(pbi);
7664#endif
7665 config_sao_hw(pbi, &pbi->vp9_param);
7666
7667#ifdef VP9_LPF_LVL_UPDATE
7668 /*
7669 * Get loop filter related picture level parameters from Parser
7670 */
7671 pbi->lf->mode_ref_delta_enabled = pbi->vp9_param.p.mode_ref_delta_enabled;
7672 pbi->lf->sharpness_level = pbi->vp9_param.p.sharpness_level;
7673 for (i = 0; i < 4; i++)
7674 pbi->lf->ref_deltas[i] = pbi->vp9_param.p.ref_deltas[i];
7675 for (i = 0; i < 2; i++)
7676 pbi->lf->mode_deltas[i] = pbi->vp9_param.p.mode_deltas[i];
7677 pbi->default_filt_lvl = pbi->vp9_param.p.filter_level;
7678 pbi->seg_4lf->enabled = pbi->vp9_param.p.seg_enabled;
7679 pbi->seg_4lf->abs_delta = pbi->vp9_param.p.seg_abs_delta;
7680 for (i = 0; i < MAX_SEGMENTS; i++)
7681 pbi->seg_4lf->feature_mask[i] = (pbi->vp9_param.p.seg_lf_info[i] &
7682 0x8000) ? (1 << SEG_LVL_ALT_LF) : 0;
7683 for (i = 0; i < MAX_SEGMENTS; i++)
7684 pbi->seg_4lf->feature_data[i][SEG_LVL_ALT_LF]
7685 = (pbi->vp9_param.p.seg_lf_info[i]
7686 & 0x100) ? -(pbi->vp9_param.p.seg_lf_info[i]
7687 & 0x3f) : (pbi->vp9_param.p.seg_lf_info[i] & 0x3f);
7688 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
7689 /*Set pipeline mode*/
7690 uint32_t lpf_data32 = READ_VREG(HEVC_DBLK_CFGB);
7691 /*dblk pipeline mode=1 for performance*/
7692 if (pbi->vp9_param.p.width >= 1280)
7693 lpf_data32 |= (0x1 << 4);
7694 else
7695 lpf_data32 &= ~(0x3 << 4);
7696 WRITE_VREG(HEVC_DBLK_CFGB, lpf_data32);
7697 }
7698 /*
7699 * Update loop filter Thr/Lvl table for every frame
7700 */
7701 /*pr_info
7702 ("vp9_loop_filter (run before every frame decoding start)\n");*/
7703 vp9_loop_filter_frame_init(pbi->seg_4lf,
7704 pbi->lfi, pbi->lf, pbi->default_filt_lvl);
7705#endif
7706 /*pr_info("HEVC_DEC_STATUS_REG <= VP9_10B_DECODE_SLICE\n");*/
7707 WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DECODE_SLICE);
7708 } else {
7709 pr_info("Skip search next start code\n");
7710 cm->prev_fb_idx = INVALID_IDX;
7711 /*skip, search next start code*/
7712 WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DECODE_SLICE);
7713 }
7714 pbi->process_state = PROC_STATE_DECODESLICE;
7715 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
7716 if (pbi->last_put_idx < pbi->used_buf_num) {
7717 struct RefCntBuffer_s *frame_bufs =
7718 cm->buffer_pool->frame_bufs;
7719 int i = pbi->last_put_idx;
7720 /*free not used buffers.*/
7721 if ((frame_bufs[i].ref_count == 0) &&
7722 (frame_bufs[i].buf.vf_ref == 0) &&
7723 (frame_bufs[i].buf.index != -1)) {
7724 decoder_mmu_box_free_idx(pbi->mmu_box, i);
7725 }
7726 pbi->last_put_idx = -1;
7727 }
7728 }
7729 return ret;
7730}
7731
7732static void fill_frame_info(struct VP9Decoder_s *pbi,
7733 struct PIC_BUFFER_CONFIG_s *frame,
7734 unsigned int framesize,
7735 unsigned int pts)
7736{
7737 struct vframe_qos_s *vframe_qos = &pbi->vframe_qos;
7738
7739 if (frame->slice_type == KEY_FRAME)
7740 vframe_qos->type = 1;
7741 else if (frame->slice_type == INTER_FRAME)
7742 vframe_qos->type = 2;
7743/*
7744#define SHOW_QOS_INFO
7745*/
7746 if (input_frame_based(hw_to_vdec(pbi)))
7747 vframe_qos->size = frame->frame_size2;
7748 else
7749 vframe_qos->size = framesize;
7750 vframe_qos->pts = pts;
7751#ifdef SHOW_QOS_INFO
7752 vp9_print(pbi, 0, "slice:%d\n", frame->slice_type);
7753#endif
7754 vframe_qos->max_mv = frame->max_mv;
7755 vframe_qos->avg_mv = frame->avg_mv;
7756 vframe_qos->min_mv = frame->min_mv;
7757#ifdef SHOW_QOS_INFO
7758 vp9_print(pbi, 0, "mv: max:%d, avg:%d, min:%d\n",
7759 vframe_qos->max_mv,
7760 vframe_qos->avg_mv,
7761 vframe_qos->min_mv);
7762#endif
7763 vframe_qos->max_qp = frame->max_qp;
7764 vframe_qos->avg_qp = frame->avg_qp;
7765 vframe_qos->min_qp = frame->min_qp;
7766#ifdef SHOW_QOS_INFO
7767 vp9_print(pbi, 0, "qp: max:%d, avg:%d, min:%d\n",
7768 vframe_qos->max_qp,
7769 vframe_qos->avg_qp,
7770 vframe_qos->min_qp);
7771#endif
7772 vframe_qos->max_skip = frame->max_skip;
7773 vframe_qos->avg_skip = frame->avg_skip;
7774 vframe_qos->min_skip = frame->min_skip;
7775#ifdef SHOW_QOS_INFO
7776 vp9_print(pbi, 0, "skip: max:%d, avg:%d, min:%d\n",
7777 vframe_qos->max_skip,
7778 vframe_qos->avg_skip,
7779 vframe_qos->min_skip);
7780#endif
7781 vframe_qos->num++;
7782}
7783
7784/* only when we decoded one field or one frame,
7785we can call this function to get qos info*/
7786static void get_picture_qos_info(struct VP9Decoder_s *pbi)
7787{
7788 struct PIC_BUFFER_CONFIG_s *frame = &pbi->cur_buf->buf;
7789 struct vdec_s *vdec = hw_to_vdec(pbi);
7790
7791 if (!frame)
7792 return;
7793 if (vdec->mvfrm) {
7794 frame->frame_size2 = vdec->mvfrm->frame_size;
7795 frame->hw_decode_time =
7796 local_clock() - vdec->mvfrm->hw_decode_start;
7797 }
7798
7799 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
7800 unsigned char a[3];
7801 unsigned char i, j, t;
7802 unsigned long data;
7803
7804 data = READ_VREG(HEVC_MV_INFO);
7805 if (frame->slice_type == KEY_FRAME)
7806 data = 0;
7807 a[0] = data & 0xff;
7808 a[1] = (data >> 8) & 0xff;
7809 a[2] = (data >> 16) & 0xff;
7810
7811 for (i = 0; i < 3; i++) {
7812 for (j = i+1; j < 3; j++) {
7813 if (a[j] < a[i]) {
7814 t = a[j];
7815 a[j] = a[i];
7816 a[i] = t;
7817 } else if (a[j] == a[i]) {
7818 a[i]++;
7819 t = a[j];
7820 a[j] = a[i];
7821 a[i] = t;
7822 }
7823 }
7824 }
7825 frame->max_mv = a[2];
7826 frame->avg_mv = a[1];
7827 frame->min_mv = a[0];
7828
7829 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7830 "mv data %x a[0]= %x a[1]= %x a[2]= %x\n",
7831 data, a[0], a[1], a[2]);
7832
7833 data = READ_VREG(HEVC_QP_INFO);
7834 a[0] = data & 0x1f;
7835 a[1] = (data >> 8) & 0x3f;
7836 a[2] = (data >> 16) & 0x7f;
7837
7838 for (i = 0; i < 3; i++) {
7839 for (j = i+1; j < 3; j++) {
7840 if (a[j] < a[i]) {
7841 t = a[j];
7842 a[j] = a[i];
7843 a[i] = t;
7844 } else if (a[j] == a[i]) {
7845 a[i]++;
7846 t = a[j];
7847 a[j] = a[i];
7848 a[i] = t;
7849 }
7850 }
7851 }
7852 frame->max_qp = a[2];
7853 frame->avg_qp = a[1];
7854 frame->min_qp = a[0];
7855
7856 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7857 "qp data %x a[0]= %x a[1]= %x a[2]= %x\n",
7858 data, a[0], a[1], a[2]);
7859
7860 data = READ_VREG(HEVC_SKIP_INFO);
7861 a[0] = data & 0x1f;
7862 a[1] = (data >> 8) & 0x3f;
7863 a[2] = (data >> 16) & 0x7f;
7864
7865 for (i = 0; i < 3; i++) {
7866 for (j = i+1; j < 3; j++) {
7867 if (a[j] < a[i]) {
7868 t = a[j];
7869 a[j] = a[i];
7870 a[i] = t;
7871 } else if (a[j] == a[i]) {
7872 a[i]++;
7873 t = a[j];
7874 a[j] = a[i];
7875 a[i] = t;
7876 }
7877 }
7878 }
7879 frame->max_skip = a[2];
7880 frame->avg_skip = a[1];
7881 frame->min_skip = a[0];
7882
7883 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7884 "skip data %x a[0]= %x a[1]= %x a[2]= %x\n",
7885 data, a[0], a[1], a[2]);
7886 } else {
7887 uint32_t blk88_y_count;
7888 uint32_t blk88_c_count;
7889 uint32_t blk22_mv_count;
7890 uint32_t rdata32;
7891 int32_t mv_hi;
7892 int32_t mv_lo;
7893 uint32_t rdata32_l;
7894 uint32_t mvx_L0_hi;
7895 uint32_t mvy_L0_hi;
7896 uint32_t mvx_L1_hi;
7897 uint32_t mvy_L1_hi;
7898 int64_t value;
7899 uint64_t temp_value;
7900 int pic_number = frame->decode_idx;
7901
7902 frame->max_mv = 0;
7903 frame->avg_mv = 0;
7904 frame->min_mv = 0;
7905
7906 frame->max_skip = 0;
7907 frame->avg_skip = 0;
7908 frame->min_skip = 0;
7909
7910 frame->max_qp = 0;
7911 frame->avg_qp = 0;
7912 frame->min_qp = 0;
7913
7914 vp9_print(pbi, VP9_DEBUG_QOS_INFO, "slice_type:%d, poc:%d\n",
7915 frame->slice_type,
7916 pic_number);
7917
7918 /* set rd_idx to 0 */
7919 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, 0);
7920
7921 blk88_y_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
7922 if (blk88_y_count == 0) {
7923
7924 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7925 "[Picture %d Quality] NO Data yet.\n",
7926 pic_number);
7927
7928 /* reset all counts */
7929 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
7930 return;
7931 }
7932 /* qp_y_sum */
7933 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7934
7935 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7936 "[Picture %d Quality] Y QP AVG : %d (%d/%d)\n",
7937 pic_number, rdata32/blk88_y_count,
7938 rdata32, blk88_y_count);
7939
7940 frame->avg_qp = rdata32/blk88_y_count;
7941 /* intra_y_count */
7942 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7943
7944 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7945 "[Picture %d Quality] Y intra rate : %d%c (%d)\n",
7946 pic_number, rdata32*100/blk88_y_count,
7947 '%', rdata32);
7948
7949 /* skipped_y_count */
7950 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7951
7952 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7953 "[Picture %d Quality] Y skipped rate : %d%c (%d)\n",
7954 pic_number, rdata32*100/blk88_y_count,
7955 '%', rdata32);
7956
7957 frame->avg_skip = rdata32*100/blk88_y_count;
7958 /* coeff_non_zero_y_count */
7959 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7960
7961 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7962 "[Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n",
7963 pic_number, (100 - rdata32*100/(blk88_y_count*1)),
7964 '%', rdata32);
7965
7966 /* blk66_c_count */
7967 blk88_c_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
7968 if (blk88_c_count == 0) {
7969 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7970 "[Picture %d Quality] NO Data yet.\n",
7971 pic_number);
7972 /* reset all counts */
7973 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
7974 return;
7975 }
7976 /* qp_c_sum */
7977 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7978
7979 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7980 "[Picture %d Quality] C QP AVG : %d (%d/%d)\n",
7981 pic_number, rdata32/blk88_c_count,
7982 rdata32, blk88_c_count);
7983
7984 /* intra_c_count */
7985 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7986
7987 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7988 "[Picture %d Quality] C intra rate : %d%c (%d)\n",
7989 pic_number, rdata32*100/blk88_c_count,
7990 '%', rdata32);
7991
7992 /* skipped_cu_c_count */
7993 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7994
7995 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7996 "[Picture %d Quality] C skipped rate : %d%c (%d)\n",
7997 pic_number, rdata32*100/blk88_c_count,
7998 '%', rdata32);
7999
8000 /* coeff_non_zero_c_count */
8001 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8002
8003 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8004 "[Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n",
8005 pic_number, (100 - rdata32*100/(blk88_c_count*1)),
8006 '%', rdata32);
8007
8008 /* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0],
8009 1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */
8010 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8011
8012 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8013 "[Picture %d Quality] Y QP min : %d\n",
8014 pic_number, (rdata32>>0)&0xff);
8015
8016 frame->min_qp = (rdata32>>0)&0xff;
8017
8018 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8019 "[Picture %d Quality] Y QP max : %d\n",
8020 pic_number, (rdata32>>8)&0xff);
8021
8022 frame->max_qp = (rdata32>>8)&0xff;
8023
8024 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8025 "[Picture %d Quality] C QP min : %d\n",
8026 pic_number, (rdata32>>16)&0xff);
8027 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8028 "[Picture %d Quality] C QP max : %d\n",
8029 pic_number, (rdata32>>24)&0xff);
8030
8031 /* blk22_mv_count */
8032 blk22_mv_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
8033 if (blk22_mv_count == 0) {
8034 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8035 "[Picture %d Quality] NO MV Data yet.\n",
8036 pic_number);
8037 /* reset all counts */
8038 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
8039 return;
8040 }
8041 /* mvy_L1_count[39:32], mvx_L1_count[39:32],
8042 mvy_L0_count[39:32], mvx_L0_count[39:32] */
8043 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8044 /* should all be 0x00 or 0xff */
8045 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8046 "[Picture %d Quality] MV AVG High Bits: 0x%X\n",
8047 pic_number, rdata32);
8048
8049 mvx_L0_hi = ((rdata32>>0)&0xff);
8050 mvy_L0_hi = ((rdata32>>8)&0xff);
8051 mvx_L1_hi = ((rdata32>>16)&0xff);
8052 mvy_L1_hi = ((rdata32>>24)&0xff);
8053
8054 /* mvx_L0_count[31:0] */
8055 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
8056 temp_value = mvx_L0_hi;
8057 temp_value = (temp_value << 32) | rdata32_l;
8058
8059 if (mvx_L0_hi & 0x80)
8060 value = 0xFFFFFFF000000000 | temp_value;
8061 else
8062 value = temp_value;
8063
8064 value = div_s64(value, blk22_mv_count);
8065
8066 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8067 "[Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n",
8068 pic_number, (int)value,
8069 value, blk22_mv_count);
8070
8071 frame->avg_mv = value;
8072
8073 /* mvy_L0_count[31:0] */
8074 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
8075 temp_value = mvy_L0_hi;
8076 temp_value = (temp_value << 32) | rdata32_l;
8077
8078 if (mvy_L0_hi & 0x80)
8079 value = 0xFFFFFFF000000000 | temp_value;
8080 else
8081 value = temp_value;
8082
8083 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8084 "[Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n",
8085 pic_number, rdata32_l/blk22_mv_count,
8086 value, blk22_mv_count);
8087
8088 /* mvx_L1_count[31:0] */
8089 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
8090 temp_value = mvx_L1_hi;
8091 temp_value = (temp_value << 32) | rdata32_l;
8092 if (mvx_L1_hi & 0x80)
8093 value = 0xFFFFFFF000000000 | temp_value;
8094 else
8095 value = temp_value;
8096
8097 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8098 "[Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n",
8099 pic_number, rdata32_l/blk22_mv_count,
8100 value, blk22_mv_count);
8101
8102 /* mvy_L1_count[31:0] */
8103 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
8104 temp_value = mvy_L1_hi;
8105 temp_value = (temp_value << 32) | rdata32_l;
8106 if (mvy_L1_hi & 0x80)
8107 value = 0xFFFFFFF000000000 | temp_value;
8108 else
8109 value = temp_value;
8110
8111 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8112 "[Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n",
8113 pic_number, rdata32_l/blk22_mv_count,
8114 value, blk22_mv_count);
8115
8116 /* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */
8117 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8118 mv_hi = (rdata32>>16)&0xffff;
8119 if (mv_hi & 0x8000)
8120 mv_hi = 0x8000 - mv_hi;
8121
8122 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8123 "[Picture %d Quality] MVX_L0 MAX : %d\n",
8124 pic_number, mv_hi);
8125
8126 frame->max_mv = mv_hi;
8127
8128 mv_lo = (rdata32>>0)&0xffff;
8129 if (mv_lo & 0x8000)
8130 mv_lo = 0x8000 - mv_lo;
8131
8132 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8133 "[Picture %d Quality] MVX_L0 MIN : %d\n",
8134 pic_number, mv_lo);
8135
8136 frame->min_mv = mv_lo;
8137
8138 /* {mvy_L0_max, mvy_L0_min} */
8139 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8140 mv_hi = (rdata32>>16)&0xffff;
8141 if (mv_hi & 0x8000)
8142 mv_hi = 0x8000 - mv_hi;
8143
8144 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8145 "[Picture %d Quality] MVY_L0 MAX : %d\n",
8146 pic_number, mv_hi);
8147
8148 mv_lo = (rdata32>>0)&0xffff;
8149 if (mv_lo & 0x8000)
8150 mv_lo = 0x8000 - mv_lo;
8151
8152 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8153 "[Picture %d Quality] MVY_L0 MIN : %d\n",
8154 pic_number, mv_lo);
8155
8156 /* {mvx_L1_max, mvx_L1_min} */
8157 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8158 mv_hi = (rdata32>>16)&0xffff;
8159 if (mv_hi & 0x8000)
8160 mv_hi = 0x8000 - mv_hi;
8161
8162 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8163 "[Picture %d Quality] MVX_L1 MAX : %d\n",
8164 pic_number, mv_hi);
8165
8166 mv_lo = (rdata32>>0)&0xffff;
8167 if (mv_lo & 0x8000)
8168 mv_lo = 0x8000 - mv_lo;
8169
8170 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8171 "[Picture %d Quality] MVX_L1 MIN : %d\n",
8172 pic_number, mv_lo);
8173
8174 /* {mvy_L1_max, mvy_L1_min} */
8175 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8176 mv_hi = (rdata32>>16)&0xffff;
8177 if (mv_hi & 0x8000)
8178 mv_hi = 0x8000 - mv_hi;
8179
8180 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8181 "[Picture %d Quality] MVY_L1 MAX : %d\n",
8182 pic_number, mv_hi);
8183
8184 mv_lo = (rdata32>>0)&0xffff;
8185 if (mv_lo & 0x8000)
8186 mv_lo = 0x8000 - mv_lo;
8187
8188 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8189 "[Picture %d Quality] MVY_L1 MIN : %d\n",
8190 pic_number, mv_lo);
8191
8192 rdata32 = READ_VREG(HEVC_PIC_QUALITY_CTRL);
8193
8194 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8195 "[Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n",
8196 pic_number, rdata32);
8197
8198 /* reset all counts */
8199 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
8200 }
8201}
8202
8203static int vvp9_get_ps_info(struct VP9Decoder_s *pbi, struct aml_vdec_ps_infos *ps)
8204{
8205 int dw_mode = v4l_parser_get_double_write_mode(pbi);
8206
8207 ps->visible_width = pbi->frame_width / get_double_write_ratio(pbi, dw_mode);
8208 ps->visible_height = pbi->frame_height / get_double_write_ratio(pbi, dw_mode);
8209 ps->coded_width = ALIGN(pbi->frame_width, 32) / get_double_write_ratio(pbi, dw_mode);
8210 ps->coded_height = ALIGN(pbi->frame_height, 32) / get_double_write_ratio(pbi, dw_mode);
8211 ps->dpb_size = pbi->used_buf_num;
8212
8213 return 0;
8214}
8215
8216
8217static int v4l_res_change(struct VP9Decoder_s *pbi)
8218{
8219 struct aml_vcodec_ctx *ctx =
8220 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
8221 struct VP9_Common_s *const cm = &pbi->common;
8222 int ret = 0;
8223
8224 if (ctx->param_sets_from_ucode &&
8225 pbi->res_ch_flag == 0) {
8226 struct aml_vdec_ps_infos ps;
8227 if ((cm->width != 0 &&
8228 cm->height != 0) &&
8229 (pbi->frame_width != cm->width ||
8230 pbi->frame_height != cm->height)) {
8231
8232 vp9_print(pbi, 0, "%s (%d,%d)=>(%d,%d)\r\n", __func__, cm->width,
8233 cm->height, pbi->frame_width, pbi->frame_height);
8234 vvp9_get_ps_info(pbi, &ps);
8235 vdec_v4l_set_ps_infos(ctx, &ps);
8236 vdec_v4l_res_ch_event(ctx);
8237 pbi->v4l_params_parsed = false;
8238 pbi->res_ch_flag = 1;
8239 pbi->eos = 1;
8240 vp9_bufmgr_postproc(pbi);
8241 //del_timer_sync(&pbi->timer);
8242 notify_v4l_eos(hw_to_vdec(pbi));
8243 ret = 1;
8244 }
8245 }
8246
8247 return ret;
8248}
8249
8250
8251static irqreturn_t vvp9_isr_thread_fn(int irq, void *data)
8252{
8253 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)data;
8254 unsigned int dec_status = pbi->dec_status;
8255 int i;
8256
8257 /*if (pbi->wait_buf)
8258 * pr_info("set wait_buf to 0\r\n");
8259 */
8260 if (pbi->eos)
8261 return IRQ_HANDLED;
8262 pbi->wait_buf = 0;
8263#ifdef MULTI_INSTANCE_SUPPORT
8264#ifdef SUPPORT_FB_DECODING
8265#ifdef FB_DECODING_TEST_SCHEDULE
8266 if (pbi->s1_test_cmd == TEST_SET_PIC_DONE)
8267 dec_status = HEVC_DECPIC_DATA_DONE;
8268 else if (pbi->s1_test_cmd == TEST_SET_S2_DONE
8269 && dec_status == HEVC_DECPIC_DATA_DONE)
8270 dec_status = HEVC_S2_DECODING_DONE;
8271 pbi->s1_test_cmd = TEST_SET_NONE;
8272#else
8273 /*if (irq != VDEC_IRQ_0)
8274 dec_status = HEVC_S2_DECODING_DONE;*/
8275#endif
8276 if (dec_status == HEVC_S2_DECODING_DONE) {
8277 pbi->dec_result = DEC_RESULT_DONE;
8278 vdec_schedule_work(&pbi->work);
8279#ifdef FB_DECODING_TEST_SCHEDULE
8280 amhevc_stop();
8281 pbi->dec_s1_result = DEC_S1_RESULT_DONE;
8282 vdec_schedule_work(&pbi->s1_work);
8283#endif
8284 } else
8285#endif
8286 if ((dec_status == HEVC_NAL_DECODE_DONE) ||
8287 (dec_status == HEVC_SEARCH_BUFEMPTY) ||
8288 (dec_status == HEVC_DECODE_BUFEMPTY)
8289 ) {
8290 if (pbi->m_ins_flag) {
8291 reset_process_time(pbi);
8292 if (!vdec_frame_based(hw_to_vdec(pbi)))
8293 dec_again_process(pbi);
8294 else {
8295 pbi->dec_result = DEC_RESULT_GET_DATA;
8296 vdec_schedule_work(&pbi->work);
8297 }
8298 }
8299 pbi->process_busy = 0;
8300 return IRQ_HANDLED;
8301 } else if (dec_status == HEVC_DECPIC_DATA_DONE) {
8302 if (pbi->m_ins_flag) {
8303 get_picture_qos_info(pbi);
8304#ifdef SUPPORT_FB_DECODING
8305 if (pbi->used_stage_buf_num > 0) {
8306 reset_process_time(pbi);
8307 inc_s1_pos(pbi);
8308 trigger_schedule(pbi);
8309#ifdef FB_DECODING_TEST_SCHEDULE
8310 pbi->s1_test_cmd = TEST_SET_S2_DONE;
8311#else
8312 amhevc_stop();
8313 pbi->dec_s1_result = DEC_S1_RESULT_DONE;
8314 vdec_schedule_work(&pbi->s1_work);
8315#endif
8316 } else
8317#endif
8318 {
8319 reset_process_time(pbi);
8320 if (pbi->vf_pre_count == 0 || pbi->low_latency_flag)
8321 vp9_bufmgr_postproc(pbi);
8322
8323 pbi->dec_result = DEC_RESULT_DONE;
8324 amhevc_stop();
8325 if (mcrcc_cache_alg_flag)
8326 dump_hit_rate(pbi);
8327 vdec_schedule_work(&pbi->work);
8328 }
8329 } else {
8330 if (pbi->low_latency_flag) {
8331 vp9_bufmgr_postproc(pbi);
8332 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
8333#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
8334 vdec_profile(hw_to_vdec(pbi), VDEC_PROFILE_EVENT_CB);
8335 if (debug & PRINT_FLAG_VDEC_DETAIL)
8336 pr_info("%s VP9 frame done \n", __func__);
8337#endif
8338 }
8339 }
8340
8341 pbi->process_busy = 0;
8342 return IRQ_HANDLED;
8343 }
8344#endif
8345
8346 if (dec_status == VP9_EOS) {
8347#ifdef MULTI_INSTANCE_SUPPORT
8348 if (pbi->m_ins_flag)
8349 reset_process_time(pbi);
8350#endif
8351
8352 pr_info("VP9_EOS, flush buffer\r\n");
8353
8354 vp9_bufmgr_postproc(pbi);
8355
8356 pr_info("send VP9_10B_DISCARD_NAL\r\n");
8357 WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DISCARD_NAL);
8358 pbi->process_busy = 0;
8359#ifdef MULTI_INSTANCE_SUPPORT
8360 if (pbi->m_ins_flag) {
8361 pbi->dec_result = DEC_RESULT_DONE;
8362 amhevc_stop();
8363 vdec_schedule_work(&pbi->work);
8364 }
8365#endif
8366 return IRQ_HANDLED;
8367 } else if (dec_status == HEVC_DECODE_OVER_SIZE) {
8368 pr_info("vp9 decode oversize !!\n");
8369 debug |= (VP9_DEBUG_DIS_LOC_ERROR_PROC |
8370 VP9_DEBUG_DIS_SYS_ERROR_PROC);
8371 pbi->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
8372#ifdef MULTI_INSTANCE_SUPPORT
8373 if (pbi->m_ins_flag)
8374 reset_process_time(pbi);
8375#endif
8376 return IRQ_HANDLED;
8377 }
8378
8379 if (dec_status != VP9_HEAD_PARSER_DONE) {
8380 pbi->process_busy = 0;
8381 return IRQ_HANDLED;
8382 }
8383
8384
8385#ifdef MULTI_INSTANCE_SUPPORT
8386#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
8387 if (pbi->m_ins_flag ==0 && pbi->low_latency_flag) {
8388 vdec_profile(hw_to_vdec(pbi), VDEC_PROFILE_EVENT_RUN);
8389 if (debug & PRINT_FLAG_VDEC_DETAIL)
8390 pr_info("%s VP9 frame header found \n", __func__);
8391 }
8392#endif
8393 if (pbi->m_ins_flag)
8394 reset_process_time(pbi);
8395#endif
8396 if (pbi->process_state != PROC_STATE_SENDAGAIN
8397#ifdef SUPPORT_FB_DECODING
8398 && pbi->used_stage_buf_num == 0
8399#endif
8400 ) {
8401 if (pbi->mmu_enable)
8402 vp9_recycle_mmu_buf_tail(pbi);
8403
8404
8405 if (pbi->frame_count > 0)
8406 vp9_bufmgr_postproc(pbi);
8407 }
8408
8409 if (debug & VP9_DEBUG_SEND_PARAM_WITH_REG) {
8410 get_rpm_param(&pbi->vp9_param);
8411 } else {
8412#ifdef SUPPORT_FB_DECODING
8413 if (pbi->used_stage_buf_num > 0) {
8414 reset_process_time(pbi);
8415 get_s1_buf(pbi);
8416
8417 if (get_mv_buf(pbi,
8418 &pbi->s1_mv_buf_index,
8419 &pbi->s1_mpred_mv_wr_start_addr
8420 ) < 0) {
8421 vp9_print(pbi, 0,
8422 "%s: Error get_mv_buf fail\n",
8423 __func__);
8424 }
8425
8426 if (pbi->s1_buf == NULL) {
8427 vp9_print(pbi, 0,
8428 "%s: Error get_s1_buf fail\n",
8429 __func__);
8430 pbi->process_busy = 0;
8431 return IRQ_HANDLED;
8432 }
8433
8434 for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
8435 int ii;
8436 for (ii = 0; ii < 4; ii++) {
8437 pbi->s1_buf->rpm[i + 3 - ii] =
8438 pbi->rpm_ptr[i + 3 - ii];
8439 pbi->s1_param.l.data[i + ii] =
8440 pbi->rpm_ptr[i + 3 - ii];
8441 }
8442 }
8443
8444 mpred_process(pbi);
8445#ifdef FB_DECODING_TEST_SCHEDULE
8446 pbi->dec_s1_result =
8447 DEC_S1_RESULT_TEST_TRIGGER_DONE;
8448 vdec_schedule_work(&pbi->s1_work);
8449#else
8450 WRITE_VREG(HEVC_ASSIST_FB_MMU_MAP_ADDR,
8451 pbi->stage_mmu_map_phy_addr +
8452 pbi->s1_buf->index * STAGE_MMU_MAP_SIZE);
8453
8454 start_s1_decoding(pbi);
8455#endif
8456 start_process_time(pbi);
8457 pbi->process_busy = 0;
8458 return IRQ_HANDLED;
8459 } else
8460#endif
8461 {
8462 for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
8463 int ii;
8464 for (ii = 0; ii < 4; ii++)
8465 pbi->vp9_param.l.data[i + ii] =
8466 pbi->rpm_ptr[i + 3 - ii];
8467 }
8468 }
8469 }
8470
8471 if (pbi->is_used_v4l) {
8472 struct aml_vcodec_ctx *ctx =
8473 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
8474
8475 pbi->frame_width = pbi->vp9_param.p.width;
8476 pbi->frame_height = pbi->vp9_param.p.height;
8477
8478 if (!v4l_res_change(pbi)) {
8479 if (ctx->param_sets_from_ucode && !pbi->v4l_params_parsed) {
8480 struct aml_vdec_ps_infos ps;
8481
8482 pr_debug("set ucode parse\n");
8483 vvp9_get_ps_info(pbi, &ps);
8484 /*notice the v4l2 codec.*/
8485 vdec_v4l_set_ps_infos(ctx, &ps);
8486 pbi->v4l_params_parsed = true;
8487 pbi->postproc_done = 0;
8488 pbi->process_busy = 0;
8489 dec_again_process(pbi);
8490 return IRQ_HANDLED;
8491 }
8492 } else {
8493 pbi->postproc_done = 0;
8494 pbi->process_busy = 0;
8495 dec_again_process(pbi);
8496 return IRQ_HANDLED;
8497 }
8498 }
8499
8500 continue_decoding(pbi);
8501 pbi->postproc_done = 0;
8502 pbi->process_busy = 0;
8503
8504#ifdef MULTI_INSTANCE_SUPPORT
8505 if (pbi->m_ins_flag)
8506 start_process_time(pbi);
8507#endif
8508
8509 return IRQ_HANDLED;
8510}
8511
8512static irqreturn_t vvp9_isr(int irq, void *data)
8513{
8514 int i;
8515 unsigned int dec_status;
8516 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)data;
8517 unsigned int adapt_prob_status;
8518 struct VP9_Common_s *const cm = &pbi->common;
8519 uint debug_tag;
8520
8521 WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1);
8522
8523 dec_status = READ_VREG(HEVC_DEC_STATUS_REG);
8524 adapt_prob_status = READ_VREG(VP9_ADAPT_PROB_REG);
8525 if (!pbi)
8526 return IRQ_HANDLED;
8527 if (pbi->init_flag == 0)
8528 return IRQ_HANDLED;
8529 if (pbi->process_busy)/*on process.*/
8530 return IRQ_HANDLED;
8531 pbi->dec_status = dec_status;
8532 pbi->process_busy = 1;
8533 if (debug & VP9_DEBUG_BUFMGR)
8534 pr_info("vp9 isr (%d) dec status = 0x%x, lcu 0x%x shiftbyte 0x%x (%x %x lev %x, wr %x, rd %x)\n",
8535 irq,
8536 dec_status, READ_VREG(HEVC_PARSER_LCU_START),
8537 READ_VREG(HEVC_SHIFT_BYTE_COUNT),
8538 READ_VREG(HEVC_STREAM_START_ADDR),
8539 READ_VREG(HEVC_STREAM_END_ADDR),
8540 READ_VREG(HEVC_STREAM_LEVEL),
8541 READ_VREG(HEVC_STREAM_WR_PTR),
8542 READ_VREG(HEVC_STREAM_RD_PTR)
8543 );
8544#ifdef SUPPORT_FB_DECODING
8545 /*if (irq != VDEC_IRQ_0)
8546 return IRQ_WAKE_THREAD;*/
8547#endif
8548
8549 debug_tag = READ_HREG(DEBUG_REG1);
8550 if (debug_tag & 0x10000) {
8551 pr_info("LMEM<tag %x>:\n", READ_HREG(DEBUG_REG1));
8552 for (i = 0; i < 0x400; i += 4) {
8553 int ii;
8554 if ((i & 0xf) == 0)
8555 pr_info("%03x: ", i);
8556 for (ii = 0; ii < 4; ii++) {
8557 pr_info("%04x ",
8558 pbi->lmem_ptr[i + 3 - ii]);
8559 }
8560 if (((i + ii) & 0xf) == 0)
8561 pr_info("\n");
8562 }
8563
8564 if ((udebug_pause_pos == (debug_tag & 0xffff)) &&
8565 (udebug_pause_decode_idx == 0 ||
8566 udebug_pause_decode_idx == pbi->slice_idx) &&
8567 (udebug_pause_val == 0 ||
8568 udebug_pause_val == READ_HREG(DEBUG_REG2)))
8569 pbi->ucode_pause_pos = udebug_pause_pos;
8570 else if (debug_tag & 0x20000)
8571 pbi->ucode_pause_pos = 0xffffffff;
8572 if (pbi->ucode_pause_pos)
8573 reset_process_time(pbi);
8574 else
8575 WRITE_HREG(DEBUG_REG1, 0);
8576 } else if (debug_tag != 0) {
8577 pr_info(
8578 "dbg%x: %x lcu %x\n", READ_HREG(DEBUG_REG1),
8579 READ_HREG(DEBUG_REG2),
8580 READ_VREG(HEVC_PARSER_LCU_START));
8581 if ((udebug_pause_pos == (debug_tag & 0xffff)) &&
8582 (udebug_pause_decode_idx == 0 ||
8583 udebug_pause_decode_idx == pbi->slice_idx) &&
8584 (udebug_pause_val == 0 ||
8585 udebug_pause_val == READ_HREG(DEBUG_REG2)))
8586 pbi->ucode_pause_pos = udebug_pause_pos;
8587 if (pbi->ucode_pause_pos)
8588 reset_process_time(pbi);
8589 else
8590 WRITE_HREG(DEBUG_REG1, 0);
8591 pbi->process_busy = 0;
8592 return IRQ_HANDLED;
8593 }
8594
8595#ifdef MULTI_INSTANCE_SUPPORT
8596 if (!pbi->m_ins_flag) {
8597#endif
8598 if (pbi->error_flag == 1) {
8599 pbi->error_flag = 2;
8600 pbi->process_busy = 0;
8601 return IRQ_HANDLED;
8602 } else if (pbi->error_flag == 3) {
8603 pbi->process_busy = 0;
8604 return IRQ_HANDLED;
8605 }
8606
8607 if (get_free_buf_count(pbi) <= 0) {
8608 /*
8609 if (pbi->wait_buf == 0)
8610 pr_info("set wait_buf to 1\r\n");
8611 */
8612 pbi->wait_buf = 1;
8613 pbi->process_busy = 0;
8614 return IRQ_HANDLED;
8615 }
8616#ifdef MULTI_INSTANCE_SUPPORT
8617 }
8618#endif
8619 if ((adapt_prob_status & 0xff) == 0xfd) {
8620 /*VP9_REQ_ADAPT_PROB*/
8621 int pre_fc = (cm->frame_type == KEY_FRAME) ? 1 : 0;
8622 uint8_t *prev_prob_b =
8623 ((uint8_t *)pbi->prob_buffer_addr) +
8624 ((adapt_prob_status >> 8) * 0x1000);
8625 uint8_t *cur_prob_b =
8626 ((uint8_t *)pbi->prob_buffer_addr) + 0x4000;
8627 uint8_t *count_b = (uint8_t *)pbi->count_buffer_addr;
8628#ifdef MULTI_INSTANCE_SUPPORT
8629 if (pbi->m_ins_flag)
8630 reset_process_time(pbi);
8631#endif
8632 adapt_coef_probs(pbi->pic_count,
8633 (cm->last_frame_type == KEY_FRAME),
8634 pre_fc, (adapt_prob_status >> 8),
8635 (unsigned int *)prev_prob_b,
8636 (unsigned int *)cur_prob_b, (unsigned int *)count_b);
8637
8638 memcpy(prev_prob_b, cur_prob_b, PROB_SIZE);
8639 WRITE_VREG(VP9_ADAPT_PROB_REG, 0);
8640 pbi->pic_count += 1;
8641#ifdef MULTI_INSTANCE_SUPPORT
8642 if (pbi->m_ins_flag)
8643 start_process_time(pbi);
8644#endif
8645
8646 /*return IRQ_HANDLED;*/
8647 }
8648 return IRQ_WAKE_THREAD;
8649}
8650
8651static void vp9_set_clk(struct work_struct *work)
8652{
8653 struct VP9Decoder_s *pbi = container_of(work,
8654 struct VP9Decoder_s, set_clk_work);
8655 int fps = 96000 / pbi->frame_dur;
8656
8657 if (hevc_source_changed(VFORMAT_VP9,
8658 frame_width, frame_height, fps) > 0)
8659 pbi->saved_resolution = frame_width *
8660 frame_height * fps;
8661}
8662
8663static void vvp9_put_timer_func(unsigned long arg)
8664{
8665 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)arg;
8666 struct timer_list *timer = &pbi->timer;
8667 uint8_t empty_flag;
8668 unsigned int buf_level;
8669
8670 enum receviver_start_e state = RECEIVER_INACTIVE;
8671
8672 if (pbi->m_ins_flag) {
8673 if (hw_to_vdec(pbi)->next_status
8674 == VDEC_STATUS_DISCONNECTED &&
8675 !pbi->is_used_v4l) {
8676#ifdef SUPPORT_FB_DECODING
8677 if (pbi->run2_busy)
8678 return;
8679
8680 pbi->dec_s1_result = DEC_S1_RESULT_FORCE_EXIT;
8681 vdec_schedule_work(&pbi->s1_work);
8682#endif
8683 pbi->dec_result = DEC_RESULT_FORCE_EXIT;
8684 vdec_schedule_work(&pbi->work);
8685 pr_debug(
8686 "vdec requested to be disconnected\n");
8687 return;
8688 }
8689 }
8690 if (pbi->init_flag == 0) {
8691 if (pbi->stat & STAT_TIMER_ARM) {
8692 timer->expires = jiffies + PUT_INTERVAL;
8693 add_timer(&pbi->timer);
8694 }
8695 return;
8696 }
8697 if (pbi->m_ins_flag == 0) {
8698 if (vf_get_receiver(pbi->provider_name)) {
8699 state =
8700 vf_notify_receiver(pbi->provider_name,
8701 VFRAME_EVENT_PROVIDER_QUREY_STATE,
8702 NULL);
8703 if ((state == RECEIVER_STATE_NULL)
8704 || (state == RECEIVER_STATE_NONE))
8705 state = RECEIVER_INACTIVE;
8706 } else
8707 state = RECEIVER_INACTIVE;
8708
8709 empty_flag = (READ_VREG(HEVC_PARSER_INT_STATUS) >> 6) & 0x1;
8710 /* error watchdog */
8711 if (empty_flag == 0) {
8712 /* decoder has input */
8713 if ((debug & VP9_DEBUG_DIS_LOC_ERROR_PROC) == 0) {
8714
8715 buf_level = READ_VREG(HEVC_STREAM_LEVEL);
8716 /* receiver has no buffer to recycle */
8717 if ((state == RECEIVER_INACTIVE) &&
8718 (kfifo_is_empty(&pbi->display_q) &&
8719 buf_level > 0x200)
8720 ) {
8721 WRITE_VREG
8722 (HEVC_ASSIST_MBOX0_IRQ_REG,
8723 0x1);
8724 }
8725 }
8726
8727 if ((debug & VP9_DEBUG_DIS_SYS_ERROR_PROC) == 0) {
8728 /* receiver has no buffer to recycle */
8729 /*if ((state == RECEIVER_INACTIVE) &&
8730 * (kfifo_is_empty(&pbi->display_q))) {
8731 *pr_info("vp9 something error,need reset\n");
8732 *}
8733 */
8734 }
8735 }
8736 }
8737#ifdef MULTI_INSTANCE_SUPPORT
8738 else {
8739 if (
8740 (decode_timeout_val > 0) &&
8741 (pbi->start_process_time > 0) &&
8742 ((1000 * (jiffies - pbi->start_process_time) / HZ)
8743 > decode_timeout_val)
8744 ) {
8745 int current_lcu_idx =
8746 READ_VREG(HEVC_PARSER_LCU_START)
8747 & 0xffffff;
8748 if (pbi->last_lcu_idx == current_lcu_idx) {
8749 if (pbi->decode_timeout_count > 0)
8750 pbi->decode_timeout_count--;
8751 if (pbi->decode_timeout_count == 0) {
8752 if (input_frame_based(
8753 hw_to_vdec(pbi)) ||
8754 (READ_VREG(HEVC_STREAM_LEVEL) > 0x200))
8755 timeout_process(pbi);
8756 else {
8757 vp9_print(pbi, 0,
8758 "timeout & empty, again\n");
8759 dec_again_process(pbi);
8760 }
8761 }
8762 } else {
8763 start_process_time(pbi);
8764 pbi->last_lcu_idx = current_lcu_idx;
8765 }
8766 }
8767 }
8768#endif
8769
8770 if ((pbi->ucode_pause_pos != 0) &&
8771 (pbi->ucode_pause_pos != 0xffffffff) &&
8772 udebug_pause_pos != pbi->ucode_pause_pos) {
8773 pbi->ucode_pause_pos = 0;
8774 WRITE_HREG(DEBUG_REG1, 0);
8775 }
8776#ifdef MULTI_INSTANCE_SUPPORT
8777 if (debug & VP9_DEBUG_FORCE_SEND_AGAIN) {
8778 pr_info(
8779 "Force Send Again\r\n");
8780 debug &= ~VP9_DEBUG_FORCE_SEND_AGAIN;
8781 reset_process_time(pbi);
8782 pbi->dec_result = DEC_RESULT_AGAIN;
8783 if (pbi->process_state ==
8784 PROC_STATE_DECODESLICE) {
8785 if (pbi->mmu_enable)
8786 vp9_recycle_mmu_buf(pbi);
8787 pbi->process_state =
8788 PROC_STATE_SENDAGAIN;
8789 }
8790 amhevc_stop();
8791
8792 vdec_schedule_work(&pbi->work);
8793 }
8794
8795 if (debug & VP9_DEBUG_DUMP_DATA) {
8796 debug &= ~VP9_DEBUG_DUMP_DATA;
8797 vp9_print(pbi, 0,
8798 "%s: chunk size 0x%x off 0x%x sum 0x%x\n",
8799 __func__,
8800 pbi->chunk->size,
8801 pbi->chunk->offset,
8802 get_data_check_sum(pbi, pbi->chunk->size)
8803 );
8804 dump_data(pbi, pbi->chunk->size);
8805 }
8806#endif
8807 if (debug & VP9_DEBUG_DUMP_PIC_LIST) {
8808 dump_pic_list(pbi);
8809 debug &= ~VP9_DEBUG_DUMP_PIC_LIST;
8810 }
8811 if (debug & VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC) {
8812 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1);
8813 debug &= ~VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC;
8814 }
8815 /*if (debug & VP9_DEBUG_HW_RESET) {
8816 }*/
8817
8818 if (radr != 0) {
8819 if (rval != 0) {
8820 WRITE_VREG(radr, rval);
8821 pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
8822 } else
8823 pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
8824 rval = 0;
8825 radr = 0;
8826 }
8827 if (pop_shorts != 0) {
8828 int i;
8829 u32 sum = 0;
8830
8831 pr_info("pop stream 0x%x shorts\r\n", pop_shorts);
8832 for (i = 0; i < pop_shorts; i++) {
8833 u32 data =
8834 (READ_HREG(HEVC_SHIFTED_DATA) >> 16);
8835 WRITE_HREG(HEVC_SHIFT_COMMAND,
8836 (1<<7)|16);
8837 if ((i & 0xf) == 0)
8838 pr_info("%04x:", i);
8839 pr_info("%04x ", data);
8840 if (((i + 1) & 0xf) == 0)
8841 pr_info("\r\n");
8842 sum += data;
8843 }
8844 pr_info("\r\nsum = %x\r\n", sum);
8845 pop_shorts = 0;
8846 }
8847 if (dbg_cmd != 0) {
8848 if (dbg_cmd == 1) {
8849 u32 disp_laddr;
8850
8851 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXBB &&
8852 get_double_write_mode(pbi) == 0) {
8853 disp_laddr =
8854 READ_VCBUS_REG(AFBC_BODY_BADDR) << 4;
8855 } else {
8856 struct canvas_s cur_canvas;
8857
8858 canvas_read((READ_VCBUS_REG(VD1_IF0_CANVAS0)
8859 & 0xff), &cur_canvas);
8860 disp_laddr = cur_canvas.addr;
8861 }
8862 pr_info("current displayed buffer address %x\r\n",
8863 disp_laddr);
8864 }
8865 dbg_cmd = 0;
8866 }
8867 /*don't changed at start.*/
8868 if (pbi->get_frame_dur && pbi->show_frame_num > 60 &&
8869 pbi->frame_dur > 0 && pbi->saved_resolution !=
8870 frame_width * frame_height *
8871 (96000 / pbi->frame_dur))
8872 vdec_schedule_work(&pbi->set_clk_work);
8873
8874 timer->expires = jiffies + PUT_INTERVAL;
8875 add_timer(timer);
8876}
8877
8878
8879int vvp9_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
8880{
8881 struct VP9Decoder_s *vp9 =
8882 (struct VP9Decoder_s *)vdec->private;
8883
8884 if (!vp9)
8885 return -1;
8886
8887 vstatus->frame_width = frame_width;
8888 vstatus->frame_height = frame_height;
8889 if (vp9->frame_dur != 0)
8890 vstatus->frame_rate = 96000 / vp9->frame_dur;
8891 else
8892 vstatus->frame_rate = -1;
8893 vstatus->error_count = 0;
8894 vstatus->status = vp9->stat | vp9->fatal_error;
8895 vstatus->frame_dur = vp9->frame_dur;
8896 vstatus->bit_rate = vp9->gvs->bit_rate;
8897 vstatus->frame_data = vp9->gvs->frame_data;
8898 vstatus->total_data = vp9->gvs->total_data;
8899 vstatus->frame_count = vp9->gvs->frame_count;
8900 vstatus->error_frame_count = vp9->gvs->error_frame_count;
8901 vstatus->drop_frame_count = vp9->gvs->drop_frame_count;
8902 vstatus->total_data = vp9->gvs->total_data;
8903 vstatus->samp_cnt = vp9->gvs->samp_cnt;
8904 vstatus->offset = vp9->gvs->offset;
8905 snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
8906 "%s", DRIVER_NAME);
8907 return 0;
8908}
8909
8910int vvp9_set_isreset(struct vdec_s *vdec, int isreset)
8911{
8912 is_reset = isreset;
8913 return 0;
8914}
8915
8916#if 0
8917static void VP9_DECODE_INIT(void)
8918{
8919 /* enable vp9 clocks */
8920 WRITE_VREG(DOS_GCLK_EN3, 0xffffffff);
8921 /* *************************************************************** */
8922 /* Power ON HEVC */
8923 /* *************************************************************** */
8924 /* Powerup HEVC */
8925 WRITE_VREG(AO_RTI_GEN_PWR_SLEEP0,
8926 READ_VREG(AO_RTI_GEN_PWR_SLEEP0) & (~(0x3 << 6)));
8927 WRITE_VREG(DOS_MEM_PD_HEVC, 0x0);
8928 WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) | (0x3ffff << 2));
8929 WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) & (~(0x3ffff << 2)));
8930 /* remove isolations */
8931 WRITE_VREG(AO_RTI_GEN_PWR_ISO0,
8932 READ_VREG(AO_RTI_GEN_PWR_ISO0) & (~(0x3 << 10)));
8933
8934}
8935#endif
8936
8937static void vvp9_prot_init(struct VP9Decoder_s *pbi, u32 mask)
8938{
8939 unsigned int data32;
8940 /* VP9_DECODE_INIT(); */
8941 vp9_config_work_space_hw(pbi, mask);
8942 if (mask & HW_MASK_BACK)
8943 init_pic_list_hw(pbi);
8944
8945 vp9_init_decoder_hw(pbi, mask);
8946
8947#ifdef VP9_LPF_LVL_UPDATE
8948 if (mask & HW_MASK_BACK)
8949 vp9_loop_filter_init(pbi);
8950#endif
8951
8952 if ((mask & HW_MASK_FRONT) == 0)
8953 return;
8954#if 1
8955 if (debug & VP9_DEBUG_BUFMGR_MORE)
8956 pr_info("%s\n", __func__);
8957 data32 = READ_VREG(HEVC_STREAM_CONTROL);
8958 data32 = data32 |
8959 (1 << 0)/*stream_fetch_enable*/
8960 ;
8961 WRITE_VREG(HEVC_STREAM_CONTROL, data32);
8962
8963 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
8964 if (debug & VP9_DEBUG_BUFMGR)
8965 pr_info("[test.c] Config STREAM_FIFO_CTL\n");
8966 data32 = READ_VREG(HEVC_STREAM_FIFO_CTL);
8967 data32 = data32 |
8968 (1 << 29) // stream_fifo_hole
8969 ;
8970 WRITE_VREG(HEVC_STREAM_FIFO_CTL, data32);
8971 }
8972#if 0
8973 data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
8974 if (data32 != 0x00000100) {
8975 pr_info("vp9 prot init error %d\n", __LINE__);
8976 return;
8977 }
8978 data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
8979 if (data32 != 0x00000300) {
8980 pr_info("vp9 prot init error %d\n", __LINE__);
8981 return;
8982 }
8983 WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x12345678);
8984 WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x9abcdef0);
8985 data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
8986 if (data32 != 0x12345678) {
8987 pr_info("vp9 prot init error %d\n", __LINE__);
8988 return;
8989 }
8990 data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
8991 if (data32 != 0x9abcdef0) {
8992 pr_info("vp9 prot init error %d\n", __LINE__);
8993 return;
8994 }
8995#endif
8996 WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x000000001);
8997 WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x00000300);
8998#endif
8999
9000
9001
9002 WRITE_VREG(HEVC_WAIT_FLAG, 1);
9003
9004 /* WRITE_VREG(HEVC_MPSR, 1); */
9005
9006 /* clear mailbox interrupt */
9007 WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1);
9008
9009 /* enable mailbox interrupt */
9010 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 1);
9011
9012 /* disable PSCALE for hardware sharing */
9013 WRITE_VREG(HEVC_PSCALE_CTRL, 0);
9014
9015 WRITE_VREG(DEBUG_REG1, 0x0);
9016 /*check vps/sps/pps/i-slice in ucode*/
9017 WRITE_VREG(NAL_SEARCH_CTL, 0x8);
9018
9019 WRITE_VREG(DECODE_STOP_POS, udebug_flag);
9020#ifdef SUPPORT_FB_DECODING
9021#ifndef FB_DECODING_TEST_SCHEDULE
9022 if (pbi->used_stage_buf_num > 0) {
9023 if (mask & HW_MASK_FRONT) {
9024 data32 = READ_VREG(
9025 HEVC_ASSIST_HED_FB_W_CTL);
9026 data32 = data32 |
9027 (1 << 0) /*hed_fb_wr_en*/
9028 ;
9029 WRITE_VREG(HEVC_ASSIST_HED_FB_W_CTL,
9030 data32);
9031 }
9032 if (mask & HW_MASK_BACK) {
9033 data32 = READ_VREG(
9034 HEVC_ASSIST_HED_FB_R_CTL);
9035 while (data32 & (1 << 7)) {
9036 /*wait finish*/
9037 data32 = READ_VREG(
9038 HEVC_ASSIST_HED_FB_R_CTL);
9039 }
9040 data32 &= (~(0x1 << 0));
9041 /*hed_fb_rd_addr_auto_rd*/
9042 data32 &= (~(0x1 << 1));
9043 /*rd_id = 0, hed_rd_map_auto_halt_num,
9044 after wr 2 ready, then start reading*/
9045 data32 |= (0x2 << 16);
9046 WRITE_VREG(HEVC_ASSIST_HED_FB_R_CTL,
9047 data32);
9048
9049 data32 |= (0x1 << 11); /*hed_rd_map_auto_halt_en*/
9050 data32 |= (0x1 << 1); /*hed_fb_rd_addr_auto_rd*/
9051 data32 |= (0x1 << 0); /*hed_fb_rd_en*/
9052 WRITE_VREG(HEVC_ASSIST_HED_FB_R_CTL,
9053 data32);
9054 }
9055
9056 }
9057#endif
9058#endif
9059}
9060
9061static int vvp9_local_init(struct VP9Decoder_s *pbi)
9062{
9063 int i;
9064 int ret;
9065 int width, height;
9066 if (alloc_lf_buf(pbi) < 0)
9067 return -1;
9068
9069 pbi->gvs = vzalloc(sizeof(struct vdec_info));
9070 if (NULL == pbi->gvs) {
9071 pr_info("the struct of vdec status malloc failed.\n");
9072 return -1;
9073 }
9074 vdec_set_vframe_comm(hw_to_vdec(pbi), DRIVER_NAME);
9075#ifdef DEBUG_PTS
9076 pbi->pts_missed = 0;
9077 pbi->pts_hit = 0;
9078#endif
9079 pbi->new_frame_displayed = 0;
9080 pbi->last_put_idx = -1;
9081 pbi->saved_resolution = 0;
9082 pbi->get_frame_dur = false;
9083 on_no_keyframe_skiped = 0;
9084 pbi->duration_from_pts_done = 0;
9085 pbi->vp9_first_pts_ready = 0;
9086 pbi->frame_cnt_window = 0;
9087 width = pbi->vvp9_amstream_dec_info.width;
9088 height = pbi->vvp9_amstream_dec_info.height;
9089 pbi->frame_dur =
9090 (pbi->vvp9_amstream_dec_info.rate ==
9091 0) ? 3200 : pbi->vvp9_amstream_dec_info.rate;
9092 if (width && height)
9093 pbi->frame_ar = height * 0x100 / width;
9094/*
9095 *TODO:FOR VERSION
9096 */
9097 pr_info("vp9: ver (%d,%d) decinfo: %dx%d rate=%d\n", vp9_version,
9098 0, width, height, pbi->frame_dur);
9099
9100 if (pbi->frame_dur == 0)
9101 pbi->frame_dur = 96000 / 24;
9102
9103 INIT_KFIFO(pbi->display_q);
9104 INIT_KFIFO(pbi->newframe_q);
9105
9106
9107 for (i = 0; i < VF_POOL_SIZE; i++) {
9108 const struct vframe_s *vf = &pbi->vfpool[i];
9109
9110 pbi->vfpool[i].index = -1;
9111 kfifo_put(&pbi->newframe_q, vf);
9112 }
9113
9114
9115 ret = vp9_local_init(pbi);
9116
9117 if (!pbi->pts_unstable) {
9118 pbi->pts_unstable =
9119 (pbi->vvp9_amstream_dec_info.rate == 0)?1:0;
9120 pr_info("set pts unstable\n");
9121 }
9122
9123 return ret;
9124}
9125
9126
9127#ifdef MULTI_INSTANCE_SUPPORT
9128static s32 vvp9_init(struct vdec_s *vdec)
9129{
9130 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)vdec->private;
9131#else
9132static s32 vvp9_init(struct VP9Decoder_s *pbi)
9133{
9134#endif
9135 int ret;
9136 int fw_size = 0x1000 * 16;
9137 struct firmware_s *fw = NULL;
9138
9139 pbi->stat |= STAT_TIMER_INIT;
9140
9141 if (vvp9_local_init(pbi) < 0)
9142 return -EBUSY;
9143
9144 fw = vmalloc(sizeof(struct firmware_s) + fw_size);
9145 if (IS_ERR_OR_NULL(fw))
9146 return -ENOMEM;
9147
9148 if (get_firmware_data(VIDEO_DEC_VP9_MMU, fw->data) < 0) {
9149 pr_err("get firmware fail.\n");
9150 vfree(fw);
9151 return -1;
9152 }
9153
9154 fw->len = fw_size;
9155
9156 INIT_WORK(&pbi->set_clk_work, vp9_set_clk);
9157 init_timer(&pbi->timer);
9158
9159#ifdef MULTI_INSTANCE_SUPPORT
9160 if (pbi->m_ins_flag) {
9161 pbi->timer.data = (ulong) pbi;
9162 pbi->timer.function = vvp9_put_timer_func;
9163 pbi->timer.expires = jiffies + PUT_INTERVAL;
9164
9165 /*add_timer(&pbi->timer);
9166
9167 pbi->stat |= STAT_TIMER_ARM;
9168 pbi->stat |= STAT_ISR_REG;*/
9169
9170 INIT_WORK(&pbi->work, vp9_work);
9171 INIT_WORK(&pbi->recycle_mmu_work, vp9_recycle_mmu_work);
9172#ifdef SUPPORT_FB_DECODING
9173 if (pbi->used_stage_buf_num > 0)
9174 INIT_WORK(&pbi->s1_work, vp9_s1_work);
9175#endif
9176 pbi->fw = fw;
9177
9178 /* picture list init.*/
9179 pbi->dec_result = DEC_INIT_PICLIST;
9180 vdec_schedule_work(&pbi->work);
9181
9182 return 0;
9183 }
9184#endif
9185 amhevc_enable();
9186
9187 init_pic_list(pbi);
9188
9189 ret = amhevc_loadmc_ex(VFORMAT_VP9, NULL, fw->data);
9190 if (ret < 0) {
9191 amhevc_disable();
9192 vfree(fw);
9193 pr_err("VP9: the %s fw loading failed, err: %x\n",
9194 tee_enabled() ? "TEE" : "local", ret);
9195 return -EBUSY;
9196 }
9197
9198 vfree(fw);
9199
9200 pbi->stat |= STAT_MC_LOAD;
9201
9202 /* enable AMRISC side protocol */
9203 vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
9204
9205 if (vdec_request_threaded_irq(VDEC_IRQ_0,
9206 vvp9_isr,
9207 vvp9_isr_thread_fn,
9208 IRQF_ONESHOT,/*run thread on this irq disabled*/
9209 "vvp9-irq", (void *)pbi)) {
9210 pr_info("vvp9 irq register error.\n");
9211 amhevc_disable();
9212 return -ENOENT;
9213 }
9214
9215 pbi->stat |= STAT_ISR_REG;
9216
9217 pbi->provider_name = PROVIDER_NAME;
9218#ifdef MULTI_INSTANCE_SUPPORT
9219 vf_provider_init(&vvp9_vf_prov, PROVIDER_NAME,
9220 &vvp9_vf_provider, pbi);
9221 vf_reg_provider(&vvp9_vf_prov);
9222 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL);
9223 if (pbi->frame_dur != 0) {
9224 if (!is_reset)
9225 vf_notify_receiver(pbi->provider_name,
9226 VFRAME_EVENT_PROVIDER_FR_HINT,
9227 (void *)
9228 ((unsigned long)pbi->frame_dur));
9229 }
9230#else
9231 vf_provider_init(&vvp9_vf_prov, PROVIDER_NAME, &vvp9_vf_provider,
9232 pbi);
9233 vf_reg_provider(&vvp9_vf_prov);
9234 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL);
9235 if (!is_reset)
9236 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_FR_HINT,
9237 (void *)((unsigned long)pbi->frame_dur));
9238#endif
9239 pbi->stat |= STAT_VF_HOOK;
9240
9241 pbi->timer.data = (ulong)pbi;
9242 pbi->timer.function = vvp9_put_timer_func;
9243 pbi->timer.expires = jiffies + PUT_INTERVAL;
9244
9245 pbi->stat |= STAT_VDEC_RUN;
9246
9247 add_timer(&pbi->timer);
9248
9249 pbi->stat |= STAT_TIMER_ARM;
9250
9251 amhevc_start();
9252
9253 pbi->init_flag = 1;
9254 pbi->process_busy = 0;
9255 pr_info("%d, vvp9_init, RP=0x%x\n",
9256 __LINE__, READ_VREG(HEVC_STREAM_RD_PTR));
9257 return 0;
9258}
9259
9260static int vmvp9_stop(struct VP9Decoder_s *pbi)
9261{
9262 pbi->init_flag = 0;
9263
9264 if (pbi->stat & STAT_VDEC_RUN) {
9265 amhevc_stop();
9266 pbi->stat &= ~STAT_VDEC_RUN;
9267 }
9268 if (pbi->stat & STAT_ISR_REG) {
9269 vdec_free_irq(VDEC_IRQ_0, (void *)pbi);
9270 pbi->stat &= ~STAT_ISR_REG;
9271 }
9272 if (pbi->stat & STAT_TIMER_ARM) {
9273 del_timer_sync(&pbi->timer);
9274 pbi->stat &= ~STAT_TIMER_ARM;
9275 }
9276
9277 if (pbi->stat & STAT_VF_HOOK) {
9278 if (!is_reset)
9279 vf_notify_receiver(pbi->provider_name,
9280 VFRAME_EVENT_PROVIDER_FR_END_HINT,
9281 NULL);
9282
9283 vf_unreg_provider(&vvp9_vf_prov);
9284 pbi->stat &= ~STAT_VF_HOOK;
9285 }
9286 vp9_local_uninit(pbi);
9287 reset_process_time(pbi);
9288 cancel_work_sync(&pbi->work);
9289 cancel_work_sync(&pbi->recycle_mmu_work);
9290#ifdef SUPPORT_FB_DECODING
9291 if (pbi->used_stage_buf_num > 0)
9292 cancel_work_sync(&pbi->s1_work);
9293#endif
9294 cancel_work_sync(&pbi->set_clk_work);
9295 uninit_mmu_buffers(pbi);
9296 if (pbi->fw)
9297 vfree(pbi->fw);
9298 pbi->fw = NULL;
9299 return 0;
9300}
9301
9302static int vvp9_stop(struct VP9Decoder_s *pbi)
9303{
9304
9305 pbi->init_flag = 0;
9306 pbi->first_sc_checked = 0;
9307 if (pbi->stat & STAT_VDEC_RUN) {
9308 amhevc_stop();
9309 pbi->stat &= ~STAT_VDEC_RUN;
9310 }
9311
9312 if (pbi->stat & STAT_ISR_REG) {
9313#ifdef MULTI_INSTANCE_SUPPORT
9314 if (!pbi->m_ins_flag)
9315#endif
9316 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0);
9317 vdec_free_irq(VDEC_IRQ_0, (void *)pbi);
9318 pbi->stat &= ~STAT_ISR_REG;
9319 }
9320
9321 if (pbi->stat & STAT_TIMER_ARM) {
9322 del_timer_sync(&pbi->timer);
9323 pbi->stat &= ~STAT_TIMER_ARM;
9324 }
9325
9326 if (pbi->stat & STAT_VF_HOOK) {
9327 if (!is_reset)
9328 vf_notify_receiver(pbi->provider_name,
9329 VFRAME_EVENT_PROVIDER_FR_END_HINT,
9330 NULL);
9331
9332 vf_unreg_provider(&vvp9_vf_prov);
9333 pbi->stat &= ~STAT_VF_HOOK;
9334 }
9335 vp9_local_uninit(pbi);
9336
9337 cancel_work_sync(&pbi->set_clk_work);
9338#ifdef MULTI_INSTANCE_SUPPORT
9339 if (pbi->m_ins_flag) {
9340#ifdef SUPPORT_FB_DECODING
9341 if (pbi->used_stage_buf_num > 0)
9342 cancel_work_sync(&pbi->s1_work);
9343#endif
9344 cancel_work_sync(&pbi->work);
9345 cancel_work_sync(&pbi->recycle_mmu_work);
9346 } else
9347 amhevc_disable();
9348#else
9349 amhevc_disable();
9350#endif
9351 uninit_mmu_buffers(pbi);
9352
9353 vfree(pbi->fw);
9354 pbi->fw = NULL;
9355 return 0;
9356}
9357static int amvdec_vp9_mmu_init(struct VP9Decoder_s *pbi)
9358{
9359 int tvp_flag = vdec_secure(hw_to_vdec(pbi)) ?
9360 CODEC_MM_FLAGS_TVP : 0;
9361 int buf_size = 48;
9362
9363 if ((pbi->max_pic_w * pbi->max_pic_h > 1280*736) &&
9364 (pbi->max_pic_w * pbi->max_pic_h <= 1920*1088)) {
9365 buf_size = 12;
9366 } else if ((pbi->max_pic_w * pbi->max_pic_h > 0) &&
9367 (pbi->max_pic_w * pbi->max_pic_h <= 1280*736)) {
9368 buf_size = 4;
9369 }
9370 pbi->need_cache_size = buf_size * SZ_1M;
9371 pbi->sc_start_time = get_jiffies_64();
9372 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
9373 pbi->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME,
9374 pbi->index, FRAME_BUFFERS,
9375 pbi->need_cache_size,
9376 tvp_flag
9377 );
9378 if (!pbi->mmu_box) {
9379 pr_err("vp9 alloc mmu box failed!!\n");
9380 return -1;
9381 }
9382 }
9383 pbi->bmmu_box = decoder_bmmu_box_alloc_box(
9384 DRIVER_NAME,
9385 pbi->index,
9386 MAX_BMMU_BUFFER_NUM,
9387 4 + PAGE_SHIFT,
9388 CODEC_MM_FLAGS_CMA_CLEAR |
9389 CODEC_MM_FLAGS_FOR_VDECODER |
9390 tvp_flag);
9391 if (!pbi->bmmu_box) {
9392 pr_err("vp9 alloc bmmu box failed!!\n");
9393 return -1;
9394 }
9395 return 0;
9396}
9397
9398static struct VP9Decoder_s *gHevc;
9399
9400static int amvdec_vp9_probe(struct platform_device *pdev)
9401{
9402 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
9403 struct BUF_s BUF[MAX_BUF_NUM];
9404 struct VP9Decoder_s *pbi;
9405 int ret;
9406#ifndef MULTI_INSTANCE_SUPPORT
9407 int i;
9408#endif
9409 pr_debug("%s\n", __func__);
9410
9411 mutex_lock(&vvp9_mutex);
9412 pbi = vmalloc(sizeof(struct VP9Decoder_s));
9413 if (pbi == NULL) {
9414 pr_info("\namvdec_vp9 device data allocation failed\n");
9415 mutex_unlock(&vvp9_mutex);
9416 return -ENOMEM;
9417 }
9418
9419 gHevc = pbi;
9420 memcpy(&BUF[0], &pbi->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
9421 memset(pbi, 0, sizeof(struct VP9Decoder_s));
9422 memcpy(&pbi->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
9423
9424 pbi->init_flag = 0;
9425 pbi->first_sc_checked= 0;
9426 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
9427 vp9_max_pic_w = 8192;
9428 vp9_max_pic_h = 4608;
9429 }
9430 pbi->max_pic_w = vp9_max_pic_w;
9431 pbi->max_pic_h = vp9_max_pic_h;
9432
9433#ifdef MULTI_INSTANCE_SUPPORT
9434 pbi->eos = 0;
9435 pbi->start_process_time = 0;
9436 pbi->timeout_num = 0;
9437#endif
9438 pbi->fatal_error = 0;
9439 pbi->show_frame_num = 0;
9440 if (pdata == NULL) {
9441 pr_info("\namvdec_vp9 memory resource undefined.\n");
9442 vfree(pbi);
9443 mutex_unlock(&vvp9_mutex);
9444 return -EFAULT;
9445 }
9446 pbi->m_ins_flag = 0;
9447#ifdef MULTI_INSTANCE_SUPPORT
9448 pbi->platform_dev = pdev;
9449 platform_set_drvdata(pdev, pdata);
9450#endif
9451 pbi->double_write_mode = double_write_mode;
9452 pbi->mmu_enable = 1;
9453 if (amvdec_vp9_mmu_init(pbi) < 0) {
9454 vfree(pbi);
9455 mutex_unlock(&vvp9_mutex);
9456 pr_err("vp9 alloc bmmu box failed!!\n");
9457 return -1;
9458 }
9459
9460 ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box, WORK_SPACE_BUF_ID,
9461 work_buf_size, DRIVER_NAME, &pdata->mem_start);
9462 if (ret < 0) {
9463 uninit_mmu_buffers(pbi);
9464 vfree(pbi);
9465 mutex_unlock(&vvp9_mutex);
9466 return ret;
9467 }
9468 pbi->buf_size = work_buf_size;
9469
9470#ifdef MULTI_INSTANCE_SUPPORT
9471 pbi->buf_start = pdata->mem_start;
9472#else
9473 if (!pbi->mmu_enable)
9474 pbi->mc_buf_spec.buf_end = pdata->mem_start + pbi->buf_size;
9475
9476 for (i = 0; i < WORK_BUF_SPEC_NUM; i++)
9477 amvvp9_workbuff_spec[i].start_adr = pdata->mem_start;
9478#endif
9479
9480
9481 if (debug) {
9482 pr_info("===VP9 decoder mem resource 0x%lx size 0x%x\n",
9483 pdata->mem_start, pbi->buf_size);
9484 }
9485
9486 if (pdata->sys_info)
9487 pbi->vvp9_amstream_dec_info = *pdata->sys_info;
9488 else {
9489 pbi->vvp9_amstream_dec_info.width = 0;
9490 pbi->vvp9_amstream_dec_info.height = 0;
9491 pbi->vvp9_amstream_dec_info.rate = 30;
9492 }
9493 pbi->no_head = no_head;
9494#ifdef MULTI_INSTANCE_SUPPORT
9495 pbi->cma_dev = pdata->cma_dev;
9496#else
9497 cma_dev = pdata->cma_dev;
9498#endif
9499
9500#ifdef MULTI_INSTANCE_SUPPORT
9501 pdata->private = pbi;
9502 pdata->dec_status = vvp9_dec_status;
9503 pdata->set_isreset = vvp9_set_isreset;
9504 is_reset = 0;
9505 if (vvp9_init(pdata) < 0) {
9506#else
9507 if (vvp9_init(pbi) < 0) {
9508#endif
9509 pr_info("\namvdec_vp9 init failed.\n");
9510 vp9_local_uninit(pbi);
9511 uninit_mmu_buffers(pbi);
9512 vfree(pbi);
9513 pdata->dec_status = NULL;
9514 mutex_unlock(&vvp9_mutex);
9515 return -ENODEV;
9516 }
9517 /*set the max clk for smooth playing...*/
9518 hevc_source_changed(VFORMAT_VP9,
9519 4096, 2048, 60);
9520 mutex_unlock(&vvp9_mutex);
9521
9522 return 0;
9523}
9524
9525static int amvdec_vp9_remove(struct platform_device *pdev)
9526{
9527 struct VP9Decoder_s *pbi = gHevc;
9528 struct vdec_s *vdec = hw_to_vdec(pbi);
9529 int i;
9530
9531 if (debug)
9532 pr_info("amvdec_vp9_remove\n");
9533
9534 mutex_lock(&vvp9_mutex);
9535
9536 vvp9_stop(pbi);
9537
9538 hevc_source_changed(VFORMAT_VP9, 0, 0, 0);
9539
9540 if (vdec->parallel_dec == 1) {
9541 for (i = 0; i < FRAME_BUFFERS; i++) {
9542 vdec->free_canvas_ex(pbi->common.buffer_pool->
9543 frame_bufs[i].buf.y_canvas_index, vdec->id);
9544 vdec->free_canvas_ex(pbi->common.buffer_pool->
9545 frame_bufs[i].buf.uv_canvas_index, vdec->id);
9546 }
9547 }
9548
9549#ifdef DEBUG_PTS
9550 pr_info("pts missed %ld, pts hit %ld, duration %d\n",
9551 pbi->pts_missed, pbi->pts_hit, pbi->frame_dur);
9552#endif
9553 mem_map_mode = 0;
9554
9555 vfree(pbi);
9556 mutex_unlock(&vvp9_mutex);
9557
9558 return 0;
9559}
9560
9561/****************************************/
9562#ifdef CONFIG_PM
9563static int vp9_suspend(struct device *dev)
9564{
9565 amhevc_suspend(to_platform_device(dev), dev->power.power_state);
9566 return 0;
9567}
9568
9569static int vp9_resume(struct device *dev)
9570{
9571 amhevc_resume(to_platform_device(dev));
9572 return 0;
9573}
9574
9575static const struct dev_pm_ops vp9_pm_ops = {
9576 SET_SYSTEM_SLEEP_PM_OPS(vp9_suspend, vp9_resume)
9577};
9578#endif
9579
9580static struct platform_driver amvdec_vp9_driver = {
9581 .probe = amvdec_vp9_probe,
9582 .remove = amvdec_vp9_remove,
9583 .driver = {
9584 .name = DRIVER_NAME,
9585#ifdef CONFIG_PM
9586 .pm = &vp9_pm_ops,
9587#endif
9588 }
9589};
9590
9591static struct codec_profile_t amvdec_vp9_profile = {
9592 .name = "vp9",
9593 .profile = ""
9594};
9595
9596static struct codec_profile_t amvdec_vp9_profile_mult;
9597
9598static unsigned char get_data_check_sum
9599 (struct VP9Decoder_s *pbi, int size)
9600{
9601 int jj;
9602 int sum = 0;
9603 u8 *data = NULL;
9604
9605 if (!pbi->chunk->block->is_mapped)
9606 data = codec_mm_vmap(pbi->chunk->block->start +
9607 pbi->chunk->offset, size);
9608 else
9609 data = ((u8 *)pbi->chunk->block->start_virt) +
9610 pbi->chunk->offset;
9611
9612 for (jj = 0; jj < size; jj++)
9613 sum += data[jj];
9614
9615 if (!pbi->chunk->block->is_mapped)
9616 codec_mm_unmap_phyaddr(data);
9617 return sum;
9618}
9619
9620static void dump_data(struct VP9Decoder_s *pbi, int size)
9621{
9622 int jj;
9623 u8 *data = NULL;
9624 int padding_size = pbi->chunk->offset &
9625 (VDEC_FIFO_ALIGN - 1);
9626
9627 if (!pbi->chunk->block->is_mapped)
9628 data = codec_mm_vmap(pbi->chunk->block->start +
9629 pbi->chunk->offset, size);
9630 else
9631 data = ((u8 *)pbi->chunk->block->start_virt) +
9632 pbi->chunk->offset;
9633
9634 vp9_print(pbi, 0, "padding: ");
9635 for (jj = padding_size; jj > 0; jj--)
9636 vp9_print_cont(pbi,
9637 0,
9638 "%02x ", *(data - jj));
9639 vp9_print_cont(pbi, 0, "data adr %p\n",
9640 data);
9641
9642 for (jj = 0; jj < size; jj++) {
9643 if ((jj & 0xf) == 0)
9644 vp9_print(pbi,
9645 0,
9646 "%06x:", jj);
9647 vp9_print_cont(pbi,
9648 0,
9649 "%02x ", data[jj]);
9650 if (((jj + 1) & 0xf) == 0)
9651 vp9_print(pbi,
9652 0,
9653 "\n");
9654 }
9655 vp9_print(pbi,
9656 0,
9657 "\n");
9658
9659 if (!pbi->chunk->block->is_mapped)
9660 codec_mm_unmap_phyaddr(data);
9661}
9662
9663static void vp9_work(struct work_struct *work)
9664{
9665 struct VP9Decoder_s *pbi = container_of(work,
9666 struct VP9Decoder_s, work);
9667 struct vdec_s *vdec = hw_to_vdec(pbi);
9668 /* finished decoding one frame or error,
9669 * notify vdec core to switch context
9670 */
9671 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9672 "%s dec_result %d %x %x %x\n",
9673 __func__,
9674 pbi->dec_result,
9675 READ_VREG(HEVC_STREAM_LEVEL),
9676 READ_VREG(HEVC_STREAM_WR_PTR),
9677 READ_VREG(HEVC_STREAM_RD_PTR));
9678
9679 if (pbi->dec_result == DEC_INIT_PICLIST) {
9680 init_pic_list(pbi);
9681 pbi->pic_list_init_done = true;
9682 return;
9683 }
9684
9685 if (((pbi->dec_result == DEC_RESULT_GET_DATA) ||
9686 (pbi->dec_result == DEC_RESULT_GET_DATA_RETRY))
9687 && (hw_to_vdec(pbi)->next_status !=
9688 VDEC_STATUS_DISCONNECTED)) {
9689 if (!vdec_has_more_input(vdec)) {
9690 pbi->dec_result = DEC_RESULT_EOS;
9691 vdec_schedule_work(&pbi->work);
9692 return;
9693 }
9694
9695 if (pbi->dec_result == DEC_RESULT_GET_DATA) {
9696 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9697 "%s DEC_RESULT_GET_DATA %x %x %x\n",
9698 __func__,
9699 READ_VREG(HEVC_STREAM_LEVEL),
9700 READ_VREG(HEVC_STREAM_WR_PTR),
9701 READ_VREG(HEVC_STREAM_RD_PTR));
9702 vdec_vframe_dirty(vdec, pbi->chunk);
9703 vdec_clean_input(vdec);
9704 }
9705
9706 if (get_free_buf_count(pbi) >=
9707 run_ready_min_buf_num) {
9708 int r;
9709 int decode_size;
9710 r = vdec_prepare_input(vdec, &pbi->chunk);
9711 if (r < 0) {
9712 pbi->dec_result = DEC_RESULT_GET_DATA_RETRY;
9713
9714 vp9_print(pbi,
9715 PRINT_FLAG_VDEC_DETAIL,
9716 "amvdec_vh265: Insufficient data\n");
9717
9718 vdec_schedule_work(&pbi->work);
9719 return;
9720 }
9721 pbi->dec_result = DEC_RESULT_NONE;
9722 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9723 "%s: chunk size 0x%x sum 0x%x\n",
9724 __func__, r,
9725 (debug & PRINT_FLAG_VDEC_STATUS) ?
9726 get_data_check_sum(pbi, r) : 0
9727 );
9728
9729 if (debug & PRINT_FLAG_VDEC_DATA)
9730 dump_data(pbi, pbi->chunk->size);
9731
9732 decode_size = pbi->chunk->size +
9733 (pbi->chunk->offset & (VDEC_FIFO_ALIGN - 1));
9734
9735 WRITE_VREG(HEVC_DECODE_SIZE,
9736 READ_VREG(HEVC_DECODE_SIZE) + decode_size);
9737
9738 vdec_enable_input(vdec);
9739
9740 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
9741
9742 start_process_time(pbi);
9743
9744 } else{
9745 pbi->dec_result = DEC_RESULT_GET_DATA_RETRY;
9746
9747 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9748 "amvdec_vh265: Insufficient data\n");
9749
9750 vdec_schedule_work(&pbi->work);
9751 }
9752 return;
9753 } else if (pbi->dec_result == DEC_RESULT_DONE) {
9754#ifdef SUPPORT_FB_DECODING
9755 if (pbi->used_stage_buf_num > 0) {
9756#ifndef FB_DECODING_TEST_SCHEDULE
9757 if (!is_s2_decoding_finished(pbi)) {
9758 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9759 "s2 decoding not done, check again later\n");
9760 vdec_schedule_work(&pbi->work);
9761 }
9762#endif
9763 inc_s2_pos(pbi);
9764 if (mcrcc_cache_alg_flag)
9765 dump_hit_rate(pbi);
9766 }
9767#endif
9768 /* if (!pbi->ctx_valid)
9769 pbi->ctx_valid = 1; */
9770 pbi->slice_idx++;
9771 pbi->frame_count++;
9772 pbi->process_state = PROC_STATE_INIT;
9773 decode_frame_count[pbi->index] = pbi->frame_count;
9774
9775 if (pbi->mmu_enable)
9776 pbi->used_4k_num =
9777 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
9778 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9779 "%s (===> %d) dec_result %d %x %x %x shiftbytes 0x%x decbytes 0x%x\n",
9780 __func__,
9781 pbi->frame_count,
9782 pbi->dec_result,
9783 READ_VREG(HEVC_STREAM_LEVEL),
9784 READ_VREG(HEVC_STREAM_WR_PTR),
9785 READ_VREG(HEVC_STREAM_RD_PTR),
9786 READ_VREG(HEVC_SHIFT_BYTE_COUNT),
9787 READ_VREG(HEVC_SHIFT_BYTE_COUNT) -
9788 pbi->start_shift_bytes
9789 );
9790 vdec_vframe_dirty(hw_to_vdec(pbi), pbi->chunk);
9791 } else if (pbi->dec_result == DEC_RESULT_AGAIN) {
9792 /*
9793 stream base: stream buf empty or timeout
9794 frame base: vdec_prepare_input fail
9795 */
9796 if (!vdec_has_more_input(vdec)) {
9797 pbi->dec_result = DEC_RESULT_EOS;
9798 vdec_schedule_work(&pbi->work);
9799 return;
9800 }
9801 } else if (pbi->dec_result == DEC_RESULT_EOS) {
9802 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9803 "%s: end of stream\n",
9804 __func__);
9805 pbi->eos = 1;
9806 vp9_bufmgr_postproc(pbi);
9807
9808 if (pbi->is_used_v4l)
9809 notify_v4l_eos(hw_to_vdec(pbi));
9810
9811 vdec_vframe_dirty(hw_to_vdec(pbi), pbi->chunk);
9812 } else if (pbi->dec_result == DEC_RESULT_FORCE_EXIT) {
9813 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9814 "%s: force exit\n",
9815 __func__);
9816 if (pbi->stat & STAT_VDEC_RUN) {
9817 amhevc_stop();
9818 pbi->stat &= ~STAT_VDEC_RUN;
9819 }
9820
9821 if (pbi->stat & STAT_ISR_REG) {
9822#ifdef MULTI_INSTANCE_SUPPORT
9823 if (!pbi->m_ins_flag)
9824#endif
9825 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0);
9826 vdec_free_irq(VDEC_IRQ_0, (void *)pbi);
9827 pbi->stat &= ~STAT_ISR_REG;
9828 }
9829 }
9830 if (pbi->stat & STAT_VDEC_RUN) {
9831 amhevc_stop();
9832 pbi->stat &= ~STAT_VDEC_RUN;
9833 }
9834
9835 if (pbi->stat & STAT_TIMER_ARM) {
9836 del_timer_sync(&pbi->timer);
9837 pbi->stat &= ~STAT_TIMER_ARM;
9838 }
9839 /* mark itself has all HW resource released and input released */
9840#ifdef SUPPORT_FB_DECODING
9841 if (pbi->used_stage_buf_num > 0)
9842 vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_HEVC_BACK);
9843 else
9844 vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_VDEC_1
9845 | CORE_MASK_HEVC
9846 | CORE_MASK_HEVC_FRONT
9847 | CORE_MASK_HEVC_BACK
9848 );
9849#else
9850 if (vdec->parallel_dec == 1)
9851 vdec_core_finish_run(vdec, CORE_MASK_HEVC);
9852 else
9853 vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_VDEC_1
9854 | CORE_MASK_HEVC);
9855#endif
9856 trigger_schedule(pbi);
9857}
9858
9859static int vp9_hw_ctx_restore(struct VP9Decoder_s *pbi)
9860{
9861 /* new to do ... */
9862#if (!defined SUPPORT_FB_DECODING)
9863 vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
9864#elif (defined FB_DECODING_TEST_SCHEDULE)
9865 vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
9866#else
9867 if (pbi->used_stage_buf_num > 0)
9868 vvp9_prot_init(pbi, HW_MASK_FRONT);
9869 else
9870 vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
9871#endif
9872 return 0;
9873}
9874static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask)
9875{
9876 struct VP9Decoder_s *pbi =
9877 (struct VP9Decoder_s *)vdec->private;
9878 int tvp = vdec_secure(hw_to_vdec(pbi)) ?
9879 CODEC_MM_FLAGS_TVP : 0;
9880 unsigned long ret = 0;
9881
9882 if (!(pbi->pic_list_init_done && pbi->pic_list_init_done2) || pbi->eos)
9883 return ret;
9884 if (!pbi->first_sc_checked && pbi->mmu_enable) {
9885 int size = decoder_mmu_box_sc_check(pbi->mmu_box, tvp);
9886 pbi->first_sc_checked = 1;
9887 vp9_print(pbi, 0, "vp9 cached=%d need_size=%d speed= %d ms\n",
9888 size, (pbi->need_cache_size >> PAGE_SHIFT),
9889 (int)(get_jiffies_64() - pbi->sc_start_time) * 1000/HZ);
9890 }
9891
9892#ifdef SUPPORT_FB_DECODING
9893 if (pbi->used_stage_buf_num > 0) {
9894 if (mask & CORE_MASK_HEVC_FRONT) {
9895 if (get_free_stage_buf_num(pbi) > 0
9896 && mv_buf_available(pbi))
9897 ret |= CORE_MASK_HEVC_FRONT;
9898 }
9899 if (mask & CORE_MASK_HEVC_BACK) {
9900 if (s2_buf_available(pbi) &&
9901 (get_free_buf_count(pbi) >=
9902 run_ready_min_buf_num)) {
9903 ret |= CORE_MASK_HEVC_BACK;
9904 pbi->back_not_run_ready = 0;
9905 } else
9906 pbi->back_not_run_ready = 1;
9907#if 0
9908 if (get_free_buf_count(pbi) <
9909 run_ready_min_buf_num)
9910 dump_pic_list(pbi);
9911#endif
9912 }
9913 } else if (get_free_buf_count(pbi) >=
9914 run_ready_min_buf_num)
9915 ret = CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9916 | CORE_MASK_HEVC_FRONT
9917 | CORE_MASK_HEVC_BACK;
9918
9919 if (ret & CORE_MASK_HEVC_FRONT)
9920 not_run_ready[pbi->index] = 0;
9921 else
9922 not_run_ready[pbi->index]++;
9923
9924 if (ret & CORE_MASK_HEVC_BACK)
9925 not_run2_ready[pbi->index] = 0;
9926 else
9927 not_run2_ready[pbi->index]++;
9928
9929 vp9_print(pbi,
9930 PRINT_FLAG_VDEC_DETAIL, "%s mask %lx=>%lx (%d %d %d %d)\r\n",
9931 __func__, mask, ret,
9932 get_free_stage_buf_num(pbi),
9933 mv_buf_available(pbi),
9934 s2_buf_available(pbi),
9935 get_free_buf_count(pbi)
9936 );
9937
9938 return ret;
9939
9940#else
9941 if (get_free_buf_count(pbi) >=
9942 run_ready_min_buf_num) {
9943 if (vdec->parallel_dec == 1)
9944 ret = CORE_MASK_HEVC;
9945 else
9946 ret = CORE_MASK_VDEC_1 | CORE_MASK_HEVC;
9947 }
9948
9949 if (pbi->is_used_v4l) {
9950 struct aml_vcodec_ctx *ctx =
9951 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
9952
9953 if (ctx->param_sets_from_ucode) {
9954 if (pbi->v4l_params_parsed) {
9955 if ((ctx->cap_pool.in < ctx->dpb_size) &&
9956 v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx) <
9957 run_ready_min_buf_num)
9958 ret = 0;
9959 } else {
9960 if ((pbi->res_ch_flag == 1) &&
9961 ((ctx->state <= AML_STATE_INIT) ||
9962 (ctx->state >= AML_STATE_FLUSHING)))
9963 ret = 0;
9964 }
9965 } else if (ctx->cap_pool.in < ctx->dpb_size) {
9966 if (v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx) <
9967 run_ready_min_buf_num)
9968 ret = 0;
9969 }
9970 }
9971
9972 if (ret)
9973 not_run_ready[pbi->index] = 0;
9974 else
9975 not_run_ready[pbi->index]++;
9976
9977 vp9_print(pbi,
9978 PRINT_FLAG_VDEC_DETAIL, "%s mask %lx=>%lx\r\n",
9979 __func__, mask, ret);
9980 return ret;
9981#endif
9982}
9983
9984static void run_front(struct vdec_s *vdec)
9985{
9986 struct VP9Decoder_s *pbi =
9987 (struct VP9Decoder_s *)vdec->private;
9988 int ret, size;
9989
9990 run_count[pbi->index]++;
9991 /* pbi->chunk = vdec_prepare_input(vdec); */
9992#if (!defined SUPPORT_FB_DECODING)
9993 hevc_reset_core(vdec);
9994#elif (defined FB_DECODING_TEST_SCHEDULE)
9995 hevc_reset_core(vdec);
9996#else
9997 if (pbi->used_stage_buf_num > 0)
9998 fb_reset_core(vdec, HW_MASK_FRONT);
9999 else
10000 hevc_reset_core(vdec);
10001#endif
10002
10003 size = vdec_prepare_input(vdec, &pbi->chunk);
10004 if (size < 0) {
10005 input_empty[pbi->index]++;
10006
10007 pbi->dec_result = DEC_RESULT_AGAIN;
10008
10009 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
10010 "ammvdec_vh265: Insufficient data\n");
10011
10012 vdec_schedule_work(&pbi->work);
10013 return;
10014 }
10015
10016 input_empty[pbi->index] = 0;
10017 pbi->dec_result = DEC_RESULT_NONE;
10018 pbi->start_shift_bytes = READ_VREG(HEVC_SHIFT_BYTE_COUNT);
10019
10020 if (debug & PRINT_FLAG_VDEC_STATUS) {
10021 int ii;
10022 vp9_print(pbi, 0,
10023 "%s (%d): size 0x%x (0x%x 0x%x) sum 0x%x (%x %x %x %x %x) bytes 0x%x",
10024 __func__,
10025 pbi->frame_count, size,
10026 pbi->chunk ? pbi->chunk->size : 0,
10027 pbi->chunk ? pbi->chunk->offset : 0,
10028 pbi->chunk ? ((vdec_frame_based(vdec) &&
10029 (debug & PRINT_FLAG_VDEC_STATUS)) ?
10030 get_data_check_sum(pbi, size) : 0) : 0,
10031 READ_VREG(HEVC_STREAM_START_ADDR),
10032 READ_VREG(HEVC_STREAM_END_ADDR),
10033 READ_VREG(HEVC_STREAM_LEVEL),
10034 READ_VREG(HEVC_STREAM_WR_PTR),
10035 READ_VREG(HEVC_STREAM_RD_PTR),
10036 pbi->start_shift_bytes);
10037 if (vdec_frame_based(vdec) && pbi->chunk) {
10038 u8 *data = NULL;
10039
10040 if (!pbi->chunk->block->is_mapped)
10041 data = codec_mm_vmap(pbi->chunk->block->start +
10042 pbi->chunk->offset, 8);
10043 else
10044 data = ((u8 *)pbi->chunk->block->start_virt) +
10045 pbi->chunk->offset;
10046
10047 vp9_print_cont(pbi, 0, "data adr %p:",
10048 data);
10049 for (ii = 0; ii < 8; ii++)
10050 vp9_print_cont(pbi, 0, "%02x ",
10051 data[ii]);
10052
10053 if (!pbi->chunk->block->is_mapped)
10054 codec_mm_unmap_phyaddr(data);
10055 }
10056 vp9_print_cont(pbi, 0, "\r\n");
10057 }
10058 if (vdec->mc_loaded) {
10059 /*firmware have load before,
10060 and not changes to another.
10061 ignore reload.
10062 */
10063 } else {
10064 ret = amhevc_loadmc_ex(VFORMAT_VP9, NULL, pbi->fw->data);
10065 if (ret < 0) {
10066 amhevc_disable();
10067 vp9_print(pbi, PRINT_FLAG_ERROR,
10068 "VP9: the %s fw loading failed, err: %x\n",
10069 tee_enabled() ? "TEE" : "local", ret);
10070 pbi->dec_result = DEC_RESULT_FORCE_EXIT;
10071 vdec_schedule_work(&pbi->work);
10072 return;
10073 }
10074 vdec->mc_loaded = 1;
10075 vdec->mc_type = VFORMAT_VP9;
10076 }
10077
10078 if (vp9_hw_ctx_restore(pbi) < 0) {
10079 vdec_schedule_work(&pbi->work);
10080 return;
10081 }
10082
10083 vdec_enable_input(vdec);
10084
10085 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
10086
10087 if (vdec_frame_based(vdec)) {
10088 if (debug & PRINT_FLAG_VDEC_DATA)
10089 dump_data(pbi, pbi->chunk->size);
10090
10091 WRITE_VREG(HEVC_SHIFT_BYTE_COUNT, 0);
10092 size = pbi->chunk->size +
10093 (pbi->chunk->offset & (VDEC_FIFO_ALIGN - 1));
10094 if (vdec->mvfrm)
10095 vdec->mvfrm->frame_size = pbi->chunk->size;
10096 }
10097 WRITE_VREG(HEVC_DECODE_SIZE, size);
10098 WRITE_VREG(HEVC_DECODE_COUNT, pbi->slice_idx);
10099 pbi->init_flag = 1;
10100
10101 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
10102 "%s: start hevc (%x %x %x)\n",
10103 __func__,
10104 READ_VREG(HEVC_DEC_STATUS_REG),
10105 READ_VREG(HEVC_MPC_E),
10106 READ_VREG(HEVC_MPSR));
10107
10108 start_process_time(pbi);
10109 mod_timer(&pbi->timer, jiffies);
10110 pbi->stat |= STAT_TIMER_ARM;
10111 pbi->stat |= STAT_ISR_REG;
10112 amhevc_start();
10113 pbi->stat |= STAT_VDEC_RUN;
10114}
10115
10116#ifdef SUPPORT_FB_DECODING
10117static void mpred_process(struct VP9Decoder_s *pbi)
10118{
10119 union param_u *params = &pbi->s1_param;
10120 unsigned char use_prev_frame_mvs =
10121 !params->p.error_resilient_mode &&
10122 params->p.width == pbi->s1_width &&
10123 params->p.height == pbi->s1_height &&
10124 !pbi->s1_intra_only &&
10125 pbi->s1_last_show_frame &&
10126 (pbi->s1_frame_type != KEY_FRAME);
10127 pbi->s1_width = params->p.width;
10128 pbi->s1_height = params->p.height;
10129 pbi->s1_frame_type = params->p.frame_type;
10130 pbi->s1_intra_only =
10131 (params->p.show_frame ||
10132 params->p.show_existing_frame)
10133 ? 0 : params->p.intra_only;
10134 if ((pbi->s1_frame_type != KEY_FRAME)
10135 && (!pbi->s1_intra_only)) {
10136 unsigned int data32;
10137 int mpred_mv_rd_end_addr;
10138
10139 mpred_mv_rd_end_addr =
10140 pbi->s1_mpred_mv_wr_start_addr_pre
10141 + (pbi->lcu_total * MV_MEM_UNIT);
10142
10143 WRITE_VREG(HEVC_MPRED_CTRL3, 0x24122412);
10144 WRITE_VREG(HEVC_MPRED_ABV_START_ADDR,
10145 pbi->work_space_buf->
10146 mpred_above.buf_start);
10147
10148 data32 = READ_VREG(HEVC_MPRED_CTRL4);
10149
10150 data32 &= (~(1 << 6));
10151 data32 |= (use_prev_frame_mvs << 6);
10152 WRITE_VREG(HEVC_MPRED_CTRL4, data32);
10153
10154 WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR,
10155 pbi->s1_mpred_mv_wr_start_addr);
10156 WRITE_VREG(HEVC_MPRED_MV_WPTR,
10157 pbi->s1_mpred_mv_wr_start_addr);
10158
10159 WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR,
10160 pbi->s1_mpred_mv_wr_start_addr_pre);
10161 WRITE_VREG(HEVC_MPRED_MV_RPTR,
10162 pbi->s1_mpred_mv_wr_start_addr_pre);
10163
10164 WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR,
10165 mpred_mv_rd_end_addr);
10166
10167 } else
10168 clear_mpred_hw(pbi);
10169
10170 if (!params->p.show_existing_frame) {
10171 pbi->s1_mpred_mv_wr_start_addr_pre =
10172 pbi->s1_mpred_mv_wr_start_addr;
10173 pbi->s1_last_show_frame =
10174 params->p.show_frame;
10175 if (pbi->s1_mv_buf_index_pre_pre != MV_BUFFER_NUM)
10176 put_mv_buf(pbi, &pbi->s1_mv_buf_index_pre_pre);
10177 pbi->s1_mv_buf_index_pre_pre =
10178 pbi->s1_mv_buf_index_pre;
10179 pbi->s1_mv_buf_index_pre = pbi->s1_mv_buf_index;
10180 } else
10181 put_mv_buf(pbi, &pbi->s1_mv_buf_index);
10182}
10183
10184static void vp9_s1_work(struct work_struct *s1_work)
10185{
10186 struct VP9Decoder_s *pbi = container_of(s1_work,
10187 struct VP9Decoder_s, s1_work);
10188 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
10189 "%s dec_s1_result %d\n",
10190 __func__,
10191 pbi->dec_s1_result);
10192
10193#ifdef FB_DECODING_TEST_SCHEDULE
10194 if (pbi->dec_s1_result ==
10195 DEC_S1_RESULT_TEST_TRIGGER_DONE) {
10196 pbi->s1_test_cmd = TEST_SET_PIC_DONE;
10197 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1);
10198 }
10199#endif
10200 if (pbi->dec_s1_result == DEC_S1_RESULT_DONE ||
10201 pbi->dec_s1_result == DEC_S1_RESULT_FORCE_EXIT) {
10202
10203 vdec_core_finish_run(hw_to_vdec(pbi),
10204 CORE_MASK_HEVC_FRONT);
10205
10206 trigger_schedule(pbi);
10207 /*pbi->dec_s1_result = DEC_S1_RESULT_NONE;*/
10208 }
10209
10210}
10211
10212static void run_back(struct vdec_s *vdec)
10213{
10214 struct VP9Decoder_s *pbi =
10215 (struct VP9Decoder_s *)vdec->private;
10216 int i;
10217 run2_count[pbi->index]++;
10218 if (debug & PRINT_FLAG_VDEC_STATUS) {
10219 vp9_print(pbi, 0,
10220 "%s", __func__);
10221 }
10222 pbi->run2_busy = 1;
10223#ifndef FB_DECODING_TEST_SCHEDULE
10224 fb_reset_core(vdec, HW_MASK_BACK);
10225
10226 vvp9_prot_init(pbi, HW_MASK_BACK);
10227#endif
10228 vp9_recycle_mmu_buf_tail(pbi);
10229
10230 if (pbi->frame_count > 0)
10231 vp9_bufmgr_postproc(pbi);
10232
10233 if (get_s2_buf(pbi) >= 0) {
10234 for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
10235 int ii;
10236 for (ii = 0; ii < 4; ii++)
10237 pbi->vp9_param.l.data[i + ii] =
10238 pbi->s2_buf->rpm[i + 3 - ii];
10239 }
10240#ifndef FB_DECODING_TEST_SCHEDULE
10241 WRITE_VREG(HEVC_ASSIST_FBD_MMU_MAP_ADDR,
10242 pbi->stage_mmu_map_phy_addr +
10243 pbi->s2_buf->index * STAGE_MMU_MAP_SIZE);
10244#endif
10245 continue_decoding(pbi);
10246 }
10247 pbi->run2_busy = 0;
10248}
10249#endif
10250
10251static void run(struct vdec_s *vdec, unsigned long mask,
10252 void (*callback)(struct vdec_s *, void *), void *arg)
10253{
10254 struct VP9Decoder_s *pbi =
10255 (struct VP9Decoder_s *)vdec->private;
10256
10257 vp9_print(pbi,
10258 PRINT_FLAG_VDEC_DETAIL, "%s mask %lx\r\n",
10259 __func__, mask);
10260
10261 if (vdec->mvfrm)
10262 vdec->mvfrm->hw_decode_start = local_clock();
10263 run_count[pbi->index]++;
10264 pbi->vdec_cb_arg = arg;
10265 pbi->vdec_cb = callback;
10266#ifdef SUPPORT_FB_DECODING
10267 if ((mask & CORE_MASK_HEVC) ||
10268 (mask & CORE_MASK_HEVC_FRONT))
10269 run_front(vdec);
10270
10271 if ((pbi->used_stage_buf_num > 0)
10272 && (mask & CORE_MASK_HEVC_BACK))
10273 run_back(vdec);
10274#else
10275 run_front(vdec);
10276#endif
10277
10278}
10279
10280static void init_frame_bufs(struct VP9Decoder_s *pbi)
10281{
10282 struct vdec_s *vdec = hw_to_vdec(pbi);
10283 struct VP9_Common_s *const cm = &pbi->common;
10284 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
10285 int i;
10286
10287 for (i = 0; i < pbi->used_buf_num; ++i) {
10288 frame_bufs[i].ref_count = 0;
10289 frame_bufs[i].buf.vf_ref = 0;
10290 frame_bufs[i].buf.decode_idx = 0;
10291 frame_bufs[i].buf.cma_alloc_addr = 0;
10292 frame_bufs[i].buf.index = i;
10293 frame_bufs[i].buf.vframe_bound = 0;
10294 }
10295
10296 if (vdec->parallel_dec == 1) {
10297 for (i = 0; i < FRAME_BUFFERS; i++) {
10298 vdec->free_canvas_ex
10299 (pbi->common.buffer_pool->frame_bufs[i].buf.y_canvas_index,
10300 vdec->id);
10301 vdec->free_canvas_ex
10302 (pbi->common.buffer_pool->frame_bufs[i].buf.uv_canvas_index,
10303 vdec->id);
10304 }
10305 }
10306}
10307
10308static void reset(struct vdec_s *vdec)
10309{
10310 struct VP9Decoder_s *pbi =
10311 (struct VP9Decoder_s *)vdec->private;
10312
10313 cancel_work_sync(&pbi->work);
10314 if (pbi->stat & STAT_VDEC_RUN) {
10315 amhevc_stop();
10316 pbi->stat &= ~STAT_VDEC_RUN;
10317 }
10318
10319 if (pbi->stat & STAT_TIMER_ARM) {
10320 del_timer_sync(&pbi->timer);
10321 pbi->stat &= ~STAT_TIMER_ARM;
10322 }
10323 pbi->dec_result = DEC_RESULT_NONE;
10324 reset_process_time(pbi);
10325 vp9_local_uninit(pbi);
10326 if (vvp9_local_init(pbi) < 0)
10327 vp9_print(pbi, 0, "%s local_init failed \r\n", __func__);
10328 init_frame_bufs(pbi);
10329
10330 pbi->eos = 0;
10331
10332 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL, "%s\r\n", __func__);
10333}
10334
10335static irqreturn_t vp9_irq_cb(struct vdec_s *vdec, int irq)
10336{
10337 struct VP9Decoder_s *pbi =
10338 (struct VP9Decoder_s *)vdec->private;
10339 return vvp9_isr(0, pbi);
10340}
10341
10342static irqreturn_t vp9_threaded_irq_cb(struct vdec_s *vdec, int irq)
10343{
10344 struct VP9Decoder_s *pbi =
10345 (struct VP9Decoder_s *)vdec->private;
10346 return vvp9_isr_thread_fn(0, pbi);
10347}
10348
10349static void vp9_dump_state(struct vdec_s *vdec)
10350{
10351 struct VP9Decoder_s *pbi =
10352 (struct VP9Decoder_s *)vdec->private;
10353 struct VP9_Common_s *const cm = &pbi->common;
10354 int i;
10355 vp9_print(pbi, 0, "====== %s\n", __func__);
10356
10357 vp9_print(pbi, 0,
10358 "width/height (%d/%d), used_buf_num %d\n",
10359 cm->width,
10360 cm->height,
10361 pbi->used_buf_num
10362 );
10363
10364 vp9_print(pbi, 0,
10365 "is_framebase(%d), eos %d, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d low_latency %d no_head %d \n",
10366 input_frame_based(vdec),
10367 pbi->eos,
10368 pbi->dec_result,
10369 decode_frame_count[pbi->index],
10370 display_frame_count[pbi->index],
10371 run_count[pbi->index],
10372 not_run_ready[pbi->index],
10373 input_empty[pbi->index],
10374 pbi->low_latency_flag,
10375 pbi->no_head
10376 );
10377
10378 if (vf_get_receiver(vdec->vf_provider_name)) {
10379 enum receviver_start_e state =
10380 vf_notify_receiver(vdec->vf_provider_name,
10381 VFRAME_EVENT_PROVIDER_QUREY_STATE,
10382 NULL);
10383 vp9_print(pbi, 0,
10384 "\nreceiver(%s) state %d\n",
10385 vdec->vf_provider_name,
10386 state);
10387 }
10388
10389 vp9_print(pbi, 0,
10390 "%s, newq(%d/%d), dispq(%d/%d), vf prepare/get/put (%d/%d/%d), free_buf_count %d (min %d for run_ready)\n",
10391 __func__,
10392 kfifo_len(&pbi->newframe_q),
10393 VF_POOL_SIZE,
10394 kfifo_len(&pbi->display_q),
10395 VF_POOL_SIZE,
10396 pbi->vf_pre_count,
10397 pbi->vf_get_count,
10398 pbi->vf_put_count,
10399 get_free_buf_count(pbi),
10400 run_ready_min_buf_num
10401 );
10402
10403 dump_pic_list(pbi);
10404
10405 for (i = 0; i < MAX_BUF_NUM; i++) {
10406 vp9_print(pbi, 0,
10407 "mv_Buf(%d) start_adr 0x%x size 0x%x used %d\n",
10408 i,
10409 pbi->m_mv_BUF[i].start_adr,
10410 pbi->m_mv_BUF[i].size,
10411 pbi->m_mv_BUF[i].used_flag);
10412 }
10413
10414 vp9_print(pbi, 0,
10415 "HEVC_DEC_STATUS_REG=0x%x\n",
10416 READ_VREG(HEVC_DEC_STATUS_REG));
10417 vp9_print(pbi, 0,
10418 "HEVC_MPC_E=0x%x\n",
10419 READ_VREG(HEVC_MPC_E));
10420 vp9_print(pbi, 0,
10421 "DECODE_MODE=0x%x\n",
10422 READ_VREG(DECODE_MODE));
10423 vp9_print(pbi, 0,
10424 "NAL_SEARCH_CTL=0x%x\n",
10425 READ_VREG(NAL_SEARCH_CTL));
10426 vp9_print(pbi, 0,
10427 "HEVC_PARSER_LCU_START=0x%x\n",
10428 READ_VREG(HEVC_PARSER_LCU_START));
10429 vp9_print(pbi, 0,
10430 "HEVC_DECODE_SIZE=0x%x\n",
10431 READ_VREG(HEVC_DECODE_SIZE));
10432 vp9_print(pbi, 0,
10433 "HEVC_SHIFT_BYTE_COUNT=0x%x\n",
10434 READ_VREG(HEVC_SHIFT_BYTE_COUNT));
10435 vp9_print(pbi, 0,
10436 "HEVC_STREAM_START_ADDR=0x%x\n",
10437 READ_VREG(HEVC_STREAM_START_ADDR));
10438 vp9_print(pbi, 0,
10439 "HEVC_STREAM_END_ADDR=0x%x\n",
10440 READ_VREG(HEVC_STREAM_END_ADDR));
10441 vp9_print(pbi, 0,
10442 "HEVC_STREAM_LEVEL=0x%x\n",
10443 READ_VREG(HEVC_STREAM_LEVEL));
10444 vp9_print(pbi, 0,
10445 "HEVC_STREAM_WR_PTR=0x%x\n",
10446 READ_VREG(HEVC_STREAM_WR_PTR));
10447 vp9_print(pbi, 0,
10448 "HEVC_STREAM_RD_PTR=0x%x\n",
10449 READ_VREG(HEVC_STREAM_RD_PTR));
10450 vp9_print(pbi, 0,
10451 "PARSER_VIDEO_RP=0x%x\n",
10452 READ_PARSER_REG(PARSER_VIDEO_RP));
10453 vp9_print(pbi, 0,
10454 "PARSER_VIDEO_WP=0x%x\n",
10455 READ_PARSER_REG(PARSER_VIDEO_WP));
10456
10457 if (input_frame_based(vdec) &&
10458 (debug & PRINT_FLAG_VDEC_DATA)
10459 ) {
10460 int jj;
10461 if (pbi->chunk && pbi->chunk->block &&
10462 pbi->chunk->size > 0) {
10463 u8 *data = NULL;
10464
10465 if (!pbi->chunk->block->is_mapped)
10466 data = codec_mm_vmap(
10467 pbi->chunk->block->start +
10468 pbi->chunk->offset,
10469 pbi->chunk->size);
10470 else
10471 data = ((u8 *)pbi->chunk->block->start_virt)
10472 + pbi->chunk->offset;
10473 vp9_print(pbi, 0,
10474 "frame data size 0x%x\n",
10475 pbi->chunk->size);
10476 for (jj = 0; jj < pbi->chunk->size; jj++) {
10477 if ((jj & 0xf) == 0)
10478 vp9_print(pbi, 0,
10479 "%06x:", jj);
10480 vp9_print_cont(pbi, 0,
10481 "%02x ", data[jj]);
10482 if (((jj + 1) & 0xf) == 0)
10483 vp9_print_cont(pbi, 0,
10484 "\n");
10485 }
10486
10487 if (!pbi->chunk->block->is_mapped)
10488 codec_mm_unmap_phyaddr(data);
10489 }
10490 }
10491
10492}
10493
10494static int ammvdec_vp9_probe(struct platform_device *pdev)
10495{
10496 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
10497 int ret;
10498 int config_val;
10499 struct vframe_content_light_level_s content_light_level;
10500 struct vframe_master_display_colour_s vf_dp;
10501
10502 struct BUF_s BUF[MAX_BUF_NUM];
10503 struct VP9Decoder_s *pbi = NULL;
10504 pr_debug("%s\n", __func__);
10505
10506 if (pdata == NULL) {
10507 pr_info("\nammvdec_vp9 memory resource undefined.\n");
10508 return -EFAULT;
10509 }
10510 /*pbi = (struct VP9Decoder_s *)devm_kzalloc(&pdev->dev,
10511 sizeof(struct VP9Decoder_s), GFP_KERNEL);*/
10512 memset(&vf_dp, 0, sizeof(struct vframe_master_display_colour_s));
10513 pbi = vmalloc(sizeof(struct VP9Decoder_s));
10514 if (pbi == NULL) {
10515 pr_info("\nammvdec_vp9 device data allocation failed\n");
10516 return -ENOMEM;
10517 }
10518 memset(pbi, 0, sizeof(struct VP9Decoder_s));
10519
10520 /* the ctx from v4l2 driver. */
10521 pbi->v4l2_ctx = pdata->private;
10522
10523 pdata->private = pbi;
10524 pdata->dec_status = vvp9_dec_status;
10525 /* pdata->set_trickmode = set_trickmode; */
10526 pdata->run_ready = run_ready;
10527 pdata->run = run;
10528 pdata->reset = reset;
10529 pdata->irq_handler = vp9_irq_cb;
10530 pdata->threaded_irq_handler = vp9_threaded_irq_cb;
10531 pdata->dump_state = vp9_dump_state;
10532
10533 memcpy(&BUF[0], &pbi->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
10534 memcpy(&pbi->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
10535
10536 pbi->index = pdev->id;
10537
10538 if (pdata->use_vfm_path)
10539 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
10540 VFM_DEC_PROVIDER_NAME);
10541 else
10542 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
10543 MULTI_INSTANCE_PROVIDER_NAME ".%02x", pdev->id & 0xff);
10544
10545 vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
10546 &vvp9_vf_provider, pbi);
10547
10548 pbi->provider_name = pdata->vf_provider_name;
10549 platform_set_drvdata(pdev, pdata);
10550
10551 pbi->platform_dev = pdev;
10552 pbi->video_signal_type = 0;
10553 pbi->m_ins_flag = 1;
10554 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX)
10555 pbi->stat |= VP9_TRIGGER_FRAME_ENABLE;
10556
10557 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
10558 pbi->max_pic_w = 8192;
10559 pbi->max_pic_h = 4608;
10560 } else {
10561 pbi->max_pic_w = 4096;
10562 pbi->max_pic_h = 2304;
10563 }
10564#if 1
10565 if ((debug & IGNORE_PARAM_FROM_CONFIG) == 0 &&
10566 pdata->config_len) {
10567#ifdef MULTI_INSTANCE_SUPPORT
10568 int vp9_buf_width = 0;
10569 int vp9_buf_height = 0;
10570 /*use ptr config for doubel_write_mode, etc*/
10571 vp9_print(pbi, 0, "pdata->config=%s\n", pdata->config);
10572 if (get_config_int(pdata->config, "vp9_double_write_mode",
10573 &config_val) == 0)
10574 pbi->double_write_mode = config_val;
10575 else
10576 pbi->double_write_mode = double_write_mode;
10577
10578 if (get_config_int(pdata->config, "save_buffer_mode",
10579 &config_val) == 0)
10580 pbi->save_buffer_mode = config_val;
10581 else
10582 pbi->save_buffer_mode = 0;
10583 if (get_config_int(pdata->config, "vp9_buf_width",
10584 &config_val) == 0) {
10585 vp9_buf_width = config_val;
10586 }
10587 if (get_config_int(pdata->config, "vp9_buf_height",
10588 &config_val) == 0) {
10589 vp9_buf_height = config_val;
10590 }
10591
10592 if (get_config_int(pdata->config, "no_head",
10593 &config_val) == 0)
10594 pbi->no_head = config_val;
10595 else
10596 pbi->no_head = no_head;
10597
10598 /*use ptr config for max_pic_w, etc*/
10599 if (get_config_int(pdata->config, "vp9_max_pic_w",
10600 &config_val) == 0) {
10601 pbi->max_pic_w = config_val;
10602 }
10603 if (get_config_int(pdata->config, "vp9_max_pic_h",
10604 &config_val) == 0) {
10605 pbi->max_pic_h = config_val;
10606 }
10607 if ((pbi->max_pic_w * pbi->max_pic_h)
10608 < (vp9_buf_width * vp9_buf_height)) {
10609 pbi->max_pic_w = vp9_buf_width;
10610 pbi->max_pic_h = vp9_buf_height;
10611 vp9_print(pbi, 0, "use buf resolution\n");
10612 }
10613
10614 if (get_config_int(pdata->config,
10615 "parm_v4l_codec_enable",
10616 &config_val) == 0)
10617 pbi->is_used_v4l = config_val;
10618
10619 if (get_config_int(pdata->config,
10620 "parm_v4l_buffer_margin",
10621 &config_val) == 0)
10622 pbi->dynamic_buf_num_margin = config_val;
10623
10624 if (get_config_int(pdata->config,
10625 "parm_v4l_canvas_mem_mode",
10626 &config_val) == 0)
10627 pbi->mem_map_mode = config_val;
10628#endif
10629 if (get_config_int(pdata->config, "HDRStaticInfo",
10630 &vf_dp.present_flag) == 0
10631 && vf_dp.present_flag == 1) {
10632 get_config_int(pdata->config, "mG.x",
10633 &vf_dp.primaries[0][0]);
10634 get_config_int(pdata->config, "mG.y",
10635 &vf_dp.primaries[0][1]);
10636 get_config_int(pdata->config, "mB.x",
10637 &vf_dp.primaries[1][0]);
10638 get_config_int(pdata->config, "mB.y",
10639 &vf_dp.primaries[1][1]);
10640 get_config_int(pdata->config, "mR.x",
10641 &vf_dp.primaries[2][0]);
10642 get_config_int(pdata->config, "mR.y",
10643 &vf_dp.primaries[2][1]);
10644 get_config_int(pdata->config, "mW.x",
10645 &vf_dp.white_point[0]);
10646 get_config_int(pdata->config, "mW.y",
10647 &vf_dp.white_point[1]);
10648 get_config_int(pdata->config, "mMaxDL",
10649 &vf_dp.luminance[0]);
10650 get_config_int(pdata->config, "mMinDL",
10651 &vf_dp.luminance[1]);
10652 vf_dp.content_light_level.present_flag = 1;
10653 get_config_int(pdata->config, "mMaxCLL",
10654 &content_light_level.max_content);
10655 get_config_int(pdata->config, "mMaxFALL",
10656 &content_light_level.max_pic_average);
10657 vf_dp.content_light_level = content_light_level;
10658 pbi->video_signal_type = (1 << 29)
10659 | (5 << 26) /* unspecified */
10660 | (0 << 25) /* limit */
10661 | (1 << 24) /* color available */
10662 | (9 << 16) /* 2020 */
10663 | (16 << 8) /* 2084 */
10664 | (9 << 0); /* 2020 */
10665 }
10666 pbi->vf_dp = vf_dp;
10667 } else
10668#endif
10669 {
10670 /*pbi->vvp9_amstream_dec_info.width = 0;
10671 pbi->vvp9_amstream_dec_info.height = 0;
10672 pbi->vvp9_amstream_dec_info.rate = 30;*/
10673 pbi->double_write_mode = double_write_mode;
10674 }
10675
10676 if (!pbi->is_used_v4l) {
10677 pbi->mem_map_mode = mem_map_mode;
10678 }
10679
10680 if (is_oversize(pbi->max_pic_w, pbi->max_pic_h)) {
10681 pr_err("over size: %dx%d, probe failed\n",
10682 pbi->max_pic_w, pbi->max_pic_h);
10683 return -1;
10684 }
10685 pbi->mmu_enable = 1;
10686 video_signal_type = pbi->video_signal_type;
10687
10688 if (pdata->sys_info) {
10689 pbi->vvp9_amstream_dec_info = *pdata->sys_info;
10690 } else {
10691 pbi->vvp9_amstream_dec_info.width = 0;
10692 pbi->vvp9_amstream_dec_info.height = 0;
10693 pbi->vvp9_amstream_dec_info.rate = 30;
10694 }
10695 pbi->low_latency_flag = 1;
10696
10697 vp9_print(pbi, 0,
10698 "no_head %d low_latency %d\n",
10699 pbi->no_head, pbi->low_latency_flag);
10700#if 0
10701 pbi->buf_start = pdata->mem_start;
10702 pbi->buf_size = pdata->mem_end - pdata->mem_start + 1;
10703#else
10704 if (amvdec_vp9_mmu_init(pbi) < 0) {
10705 pr_err("vp9 alloc bmmu box failed!!\n");
10706 /* devm_kfree(&pdev->dev, (void *)pbi); */
10707 vfree((void *)pbi);
10708 pdata->dec_status = NULL;
10709 return -1;
10710 }
10711
10712 pbi->cma_alloc_count = PAGE_ALIGN(work_buf_size) / PAGE_SIZE;
10713 ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box, WORK_SPACE_BUF_ID,
10714 pbi->cma_alloc_count * PAGE_SIZE, DRIVER_NAME,
10715 &pbi->cma_alloc_addr);
10716 if (ret < 0) {
10717 uninit_mmu_buffers(pbi);
10718 /* devm_kfree(&pdev->dev, (void *)pbi); */
10719 vfree((void *)pbi);
10720 pdata->dec_status = NULL;
10721 return ret;
10722 }
10723 pbi->buf_start = pbi->cma_alloc_addr;
10724 pbi->buf_size = work_buf_size;
10725#endif
10726
10727 pbi->init_flag = 0;
10728 pbi->first_sc_checked = 0;
10729 pbi->fatal_error = 0;
10730 pbi->show_frame_num = 0;
10731
10732 if (debug) {
10733 pr_info("===VP9 decoder mem resource 0x%lx size 0x%x\n",
10734 pbi->buf_start,
10735 pbi->buf_size);
10736 }
10737
10738 pbi->cma_dev = pdata->cma_dev;
10739 if (vvp9_init(pdata) < 0) {
10740 pr_info("\namvdec_vp9 init failed.\n");
10741 vp9_local_uninit(pbi);
10742 uninit_mmu_buffers(pbi);
10743 /* devm_kfree(&pdev->dev, (void *)pbi); */
10744 vfree((void *)pbi);
10745 pdata->dec_status = NULL;
10746 return -ENODEV;
10747 }
10748 vdec_set_prepare_level(pdata, start_decode_buf_level);
10749 hevc_source_changed(VFORMAT_VP9,
10750 4096, 2048, 60);
10751#ifdef SUPPORT_FB_DECODING
10752 if (pbi->used_stage_buf_num > 0)
10753 vdec_core_request(pdata,
10754 CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK);
10755 else
10756 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
10757 | CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK
10758 | CORE_MASK_COMBINE);
10759#else
10760 if (pdata->parallel_dec == 1)
10761 vdec_core_request(pdata, CORE_MASK_HEVC);
10762 else
10763 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
10764 | CORE_MASK_COMBINE);
10765#endif
10766 pbi->pic_list_init_done2 = true;
10767 return 0;
10768}
10769
10770static int ammvdec_vp9_remove(struct platform_device *pdev)
10771{
10772 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)
10773 (((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
10774 struct vdec_s *vdec = hw_to_vdec(pbi);
10775 int i;
10776 if (debug)
10777 pr_info("amvdec_vp9_remove\n");
10778
10779 vmvp9_stop(pbi);
10780
10781#ifdef SUPPORT_FB_DECODING
10782 vdec_core_release(hw_to_vdec(pbi), CORE_MASK_VDEC_1 | CORE_MASK_HEVC
10783 | CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK
10784 );
10785#else
10786 if (vdec->parallel_dec == 1)
10787 vdec_core_release(hw_to_vdec(pbi), CORE_MASK_HEVC);
10788 else
10789 vdec_core_release(hw_to_vdec(pbi), CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
10790#endif
10791 vdec_set_status(hw_to_vdec(pbi), VDEC_STATUS_DISCONNECTED);
10792
10793 if (vdec->parallel_dec == 1) {
10794 for (i = 0; i < FRAME_BUFFERS; i++) {
10795 vdec->free_canvas_ex
10796 (pbi->common.buffer_pool->frame_bufs[i].buf.y_canvas_index,
10797 vdec->id);
10798 vdec->free_canvas_ex
10799 (pbi->common.buffer_pool->frame_bufs[i].buf.uv_canvas_index,
10800 vdec->id);
10801 }
10802 }
10803
10804
10805#ifdef DEBUG_PTS
10806 pr_info("pts missed %ld, pts hit %ld, duration %d\n",
10807 pbi->pts_missed, pbi->pts_hit, pbi->frame_dur);
10808#endif
10809 mem_map_mode = 0;
10810
10811 /* devm_kfree(&pdev->dev, (void *)pbi); */
10812 vfree((void *)pbi);
10813 return 0;
10814}
10815
10816static struct platform_driver ammvdec_vp9_driver = {
10817 .probe = ammvdec_vp9_probe,
10818 .remove = ammvdec_vp9_remove,
10819 .driver = {
10820 .name = MULTI_DRIVER_NAME,
10821#ifdef CONFIG_PM
10822 .pm = &vp9_pm_ops,
10823#endif
10824 }
10825};
10826#endif
10827static struct mconfig vp9_configs[] = {
10828 MC_PU32("bit_depth_luma", &bit_depth_luma),
10829 MC_PU32("bit_depth_chroma", &bit_depth_chroma),
10830 MC_PU32("frame_width", &frame_width),
10831 MC_PU32("frame_height", &frame_height),
10832 MC_PU32("debug", &debug),
10833 MC_PU32("radr", &radr),
10834 MC_PU32("rval", &rval),
10835 MC_PU32("pop_shorts", &pop_shorts),
10836 MC_PU32("dbg_cmd", &dbg_cmd),
10837 MC_PU32("dbg_skip_decode_index", &dbg_skip_decode_index),
10838 MC_PU32("endian", &endian),
10839 MC_PU32("step", &step),
10840 MC_PU32("udebug_flag", &udebug_flag),
10841 MC_PU32("decode_pic_begin", &decode_pic_begin),
10842 MC_PU32("slice_parse_begin", &slice_parse_begin),
10843 MC_PU32("i_only_flag", &i_only_flag),
10844 MC_PU32("error_handle_policy", &error_handle_policy),
10845 MC_PU32("buf_alloc_width", &buf_alloc_width),
10846 MC_PU32("buf_alloc_height", &buf_alloc_height),
10847 MC_PU32("buf_alloc_depth", &buf_alloc_depth),
10848 MC_PU32("buf_alloc_size", &buf_alloc_size),
10849 MC_PU32("buffer_mode", &buffer_mode),
10850 MC_PU32("buffer_mode_dbg", &buffer_mode_dbg),
10851 MC_PU32("max_buf_num", &max_buf_num),
10852 MC_PU32("dynamic_buf_num_margin", &dynamic_buf_num_margin),
10853 MC_PU32("mem_map_mode", &mem_map_mode),
10854 MC_PU32("double_write_mode", &double_write_mode),
10855 MC_PU32("enable_mem_saving", &enable_mem_saving),
10856 MC_PU32("force_w_h", &force_w_h),
10857 MC_PU32("force_fps", &force_fps),
10858 MC_PU32("max_decoding_time", &max_decoding_time),
10859 MC_PU32("on_no_keyframe_skiped", &on_no_keyframe_skiped),
10860 MC_PU32("start_decode_buf_level", &start_decode_buf_level),
10861 MC_PU32("decode_timeout_val", &decode_timeout_val),
10862 MC_PU32("vp9_max_pic_w", &vp9_max_pic_w),
10863 MC_PU32("vp9_max_pic_h", &vp9_max_pic_h),
10864};
10865static struct mconfig_node vp9_node;
10866
10867static int __init amvdec_vp9_driver_init_module(void)
10868{
10869
10870 struct BuffInfo_s *p_buf_info;
10871
10872 if (vdec_is_support_4k()) {
10873 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
10874 p_buf_info = &amvvp9_workbuff_spec[2];
10875 else
10876 p_buf_info = &amvvp9_workbuff_spec[1];
10877 } else
10878 p_buf_info = &amvvp9_workbuff_spec[0];
10879
10880 init_buff_spec(NULL, p_buf_info);
10881 work_buf_size =
10882 (p_buf_info->end_adr - p_buf_info->start_adr
10883 + 0xffff) & (~0xffff);
10884
10885 pr_debug("amvdec_vp9 module init\n");
10886
10887 error_handle_policy = 0;
10888
10889#ifdef ERROR_HANDLE_DEBUG
10890 dbg_nal_skip_flag = 0;
10891 dbg_nal_skip_count = 0;
10892#endif
10893 udebug_flag = 0;
10894 decode_pic_begin = 0;
10895 slice_parse_begin = 0;
10896 step = 0;
10897 buf_alloc_size = 0;
10898#ifdef MULTI_INSTANCE_SUPPORT
10899 if (platform_driver_register(&ammvdec_vp9_driver))
10900 pr_err("failed to register ammvdec_vp9 driver\n");
10901
10902#endif
10903 if (platform_driver_register(&amvdec_vp9_driver)) {
10904 pr_err("failed to register amvdec_vp9 driver\n");
10905 return -ENODEV;
10906 }
10907
10908 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
10909 amvdec_vp9_profile.profile =
10910 "8k, 10bit, dwrite, compressed, no_head";
10911 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXL
10912 /*&& get_cpu_major_id() != MESON_CPU_MAJOR_ID_GXLX*/
10913 && get_cpu_major_id() != AM_MESON_CPU_MAJOR_ID_TXL) {
10914 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX) {
10915 if (vdec_is_support_4k())
10916 amvdec_vp9_profile.profile =
10917 "4k, 10bit, dwrite, compressed";
10918 else
10919 amvdec_vp9_profile.profile =
10920 "10bit, dwrite, compressed";
10921 } else {
10922 if (vdec_is_support_4k())
10923 amvdec_vp9_profile.profile =
10924 "4k, 10bit, dwrite, compressed, no_head";
10925 else
10926 amvdec_vp9_profile.profile =
10927 "10bit, dwrite, compressed, no_head";
10928 }
10929
10930 } else {
10931 amvdec_vp9_profile.name = "vp9_unsupport";
10932 }
10933
10934 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A)
10935 max_buf_num = MAX_BUF_NUM_LESS;
10936
10937 vcodec_profile_register(&amvdec_vp9_profile);
10938 amvdec_vp9_profile_mult = amvdec_vp9_profile;
10939 amvdec_vp9_profile_mult.name = "mvp9";
10940 vcodec_profile_register(&amvdec_vp9_profile_mult);
10941 INIT_REG_NODE_CONFIGS("media.decoder", &vp9_node,
10942 "vp9", vp9_configs, CONFIG_FOR_RW);
10943
10944 return 0;
10945}
10946
10947static void __exit amvdec_vp9_driver_remove_module(void)
10948{
10949 pr_debug("amvdec_vp9 module remove.\n");
10950#ifdef MULTI_INSTANCE_SUPPORT
10951 platform_driver_unregister(&ammvdec_vp9_driver);
10952#endif
10953 platform_driver_unregister(&amvdec_vp9_driver);
10954}
10955
10956/****************************************/
10957
10958module_param(bit_depth_luma, uint, 0664);
10959MODULE_PARM_DESC(bit_depth_luma, "\n amvdec_vp9 bit_depth_luma\n");
10960
10961module_param(bit_depth_chroma, uint, 0664);
10962MODULE_PARM_DESC(bit_depth_chroma, "\n amvdec_vp9 bit_depth_chroma\n");
10963
10964module_param(frame_width, uint, 0664);
10965MODULE_PARM_DESC(frame_width, "\n amvdec_vp9 frame_width\n");
10966
10967module_param(frame_height, uint, 0664);
10968MODULE_PARM_DESC(frame_height, "\n amvdec_vp9 frame_height\n");
10969
10970module_param(debug, uint, 0664);
10971MODULE_PARM_DESC(debug, "\n amvdec_vp9 debug\n");
10972
10973module_param(radr, uint, 0664);
10974MODULE_PARM_DESC(radr, "\n radr\n");
10975
10976module_param(rval, uint, 0664);
10977MODULE_PARM_DESC(rval, "\n rval\n");
10978
10979module_param(pop_shorts, uint, 0664);
10980MODULE_PARM_DESC(pop_shorts, "\n rval\n");
10981
10982module_param(dbg_cmd, uint, 0664);
10983MODULE_PARM_DESC(dbg_cmd, "\n dbg_cmd\n");
10984
10985module_param(dbg_skip_decode_index, uint, 0664);
10986MODULE_PARM_DESC(dbg_skip_decode_index, "\n dbg_skip_decode_index\n");
10987
10988module_param(endian, uint, 0664);
10989MODULE_PARM_DESC(endian, "\n rval\n");
10990
10991module_param(step, uint, 0664);
10992MODULE_PARM_DESC(step, "\n amvdec_vp9 step\n");
10993
10994module_param(decode_pic_begin, uint, 0664);
10995MODULE_PARM_DESC(decode_pic_begin, "\n amvdec_vp9 decode_pic_begin\n");
10996
10997module_param(slice_parse_begin, uint, 0664);
10998MODULE_PARM_DESC(slice_parse_begin, "\n amvdec_vp9 slice_parse_begin\n");
10999
11000module_param(i_only_flag, uint, 0664);
11001MODULE_PARM_DESC(i_only_flag, "\n amvdec_vp9 i_only_flag\n");
11002
11003module_param(low_latency_flag, uint, 0664);
11004MODULE_PARM_DESC(low_latency_flag, "\n amvdec_vp9 low_latency_flag\n");
11005
11006module_param(no_head, uint, 0664);
11007MODULE_PARM_DESC(no_head, "\n amvdec_vp9 no_head\n");
11008
11009module_param(error_handle_policy, uint, 0664);
11010MODULE_PARM_DESC(error_handle_policy, "\n amvdec_vp9 error_handle_policy\n");
11011
11012module_param(buf_alloc_width, uint, 0664);
11013MODULE_PARM_DESC(buf_alloc_width, "\n buf_alloc_width\n");
11014
11015module_param(buf_alloc_height, uint, 0664);
11016MODULE_PARM_DESC(buf_alloc_height, "\n buf_alloc_height\n");
11017
11018module_param(buf_alloc_depth, uint, 0664);
11019MODULE_PARM_DESC(buf_alloc_depth, "\n buf_alloc_depth\n");
11020
11021module_param(buf_alloc_size, uint, 0664);
11022MODULE_PARM_DESC(buf_alloc_size, "\n buf_alloc_size\n");
11023
11024module_param(buffer_mode, uint, 0664);
11025MODULE_PARM_DESC(buffer_mode, "\n buffer_mode\n");
11026
11027module_param(buffer_mode_dbg, uint, 0664);
11028MODULE_PARM_DESC(buffer_mode_dbg, "\n buffer_mode_dbg\n");
11029/*USE_BUF_BLOCK*/
11030module_param(max_buf_num, uint, 0664);
11031MODULE_PARM_DESC(max_buf_num, "\n max_buf_num\n");
11032
11033module_param(dynamic_buf_num_margin, uint, 0664);
11034MODULE_PARM_DESC(dynamic_buf_num_margin, "\n dynamic_buf_num_margin\n");
11035
11036module_param(mv_buf_margin, uint, 0664);
11037MODULE_PARM_DESC(mv_buf_margin, "\n mv_buf_margin\n");
11038
11039module_param(run_ready_min_buf_num, uint, 0664);
11040MODULE_PARM_DESC(run_ready_min_buf_num, "\n run_ready_min_buf_num\n");
11041
11042/**/
11043
11044module_param(mem_map_mode, uint, 0664);
11045MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n");
11046
11047#ifdef SUPPORT_10BIT
11048module_param(double_write_mode, uint, 0664);
11049MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n");
11050
11051module_param(enable_mem_saving, uint, 0664);
11052MODULE_PARM_DESC(enable_mem_saving, "\n enable_mem_saving\n");
11053
11054module_param(force_w_h, uint, 0664);
11055MODULE_PARM_DESC(force_w_h, "\n force_w_h\n");
11056#endif
11057
11058module_param(force_fps, uint, 0664);
11059MODULE_PARM_DESC(force_fps, "\n force_fps\n");
11060
11061module_param(max_decoding_time, uint, 0664);
11062MODULE_PARM_DESC(max_decoding_time, "\n max_decoding_time\n");
11063
11064module_param(on_no_keyframe_skiped, uint, 0664);
11065MODULE_PARM_DESC(on_no_keyframe_skiped, "\n on_no_keyframe_skiped\n");
11066
11067module_param(mcrcc_cache_alg_flag, uint, 0664);
11068MODULE_PARM_DESC(mcrcc_cache_alg_flag, "\n mcrcc_cache_alg_flag\n");
11069
11070#ifdef MULTI_INSTANCE_SUPPORT
11071module_param(start_decode_buf_level, int, 0664);
11072MODULE_PARM_DESC(start_decode_buf_level,
11073 "\n vp9 start_decode_buf_level\n");
11074
11075module_param(decode_timeout_val, uint, 0664);
11076MODULE_PARM_DESC(decode_timeout_val,
11077 "\n vp9 decode_timeout_val\n");
11078
11079module_param(vp9_max_pic_w, uint, 0664);
11080MODULE_PARM_DESC(vp9_max_pic_w, "\n vp9_max_pic_w\n");
11081
11082module_param(vp9_max_pic_h, uint, 0664);
11083MODULE_PARM_DESC(vp9_max_pic_h, "\n vp9_max_pic_h\n");
11084
11085module_param_array(decode_frame_count, uint,
11086 &max_decode_instance_num, 0664);
11087
11088module_param_array(display_frame_count, uint,
11089 &max_decode_instance_num, 0664);
11090
11091module_param_array(max_process_time, uint,
11092 &max_decode_instance_num, 0664);
11093
11094module_param_array(run_count, uint,
11095 &max_decode_instance_num, 0664);
11096
11097module_param_array(input_empty, uint,
11098 &max_decode_instance_num, 0664);
11099
11100module_param_array(not_run_ready, uint,
11101 &max_decode_instance_num, 0664);
11102#endif
11103
11104#ifdef SUPPORT_FB_DECODING
11105module_param_array(not_run2_ready, uint,
11106 &max_decode_instance_num, 0664);
11107
11108module_param_array(run2_count, uint,
11109 &max_decode_instance_num, 0664);
11110
11111module_param(stage_buf_num, uint, 0664);
11112MODULE_PARM_DESC(stage_buf_num, "\n amvdec_h265 stage_buf_num\n");
11113#endif
11114
11115module_param(udebug_flag, uint, 0664);
11116MODULE_PARM_DESC(udebug_flag, "\n amvdec_h265 udebug_flag\n");
11117
11118module_param(udebug_pause_pos, uint, 0664);
11119MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n");
11120
11121module_param(udebug_pause_val, uint, 0664);
11122MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n");
11123
11124module_param(udebug_pause_decode_idx, uint, 0664);
11125MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n");
11126
11127module_param(without_display_mode, uint, 0664);
11128MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n");
11129
11130module_init(amvdec_vp9_driver_init_module);
11131module_exit(amvdec_vp9_driver_remove_module);
11132
11133MODULE_DESCRIPTION("AMLOGIC vp9 Video Decoder Driver");
11134MODULE_LICENSE("GPL");
11135
11136
generated by cgit at 2024-05-19 17:00:28 (GMT)