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path: root/drivers/stream_input/tv_frontend/dtv_demod/demod_func.c (plain)
blob: a54d82cadddc84e62697a9b16891d90799aee9d1
1/*
2* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
3*
4* This program is free software; you can redistribute it and/or modify
5* it under the terms of the GNU General Public License as published by
6* the Free Software Foundation; either version 2 of the License, or
7* (at your option) any later version.
8*
9* This program is distributed in the hope that it will be useful, but WITHOUT
10* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12* more details.
13*
14* You should have received a copy of the GNU General Public License along
15* with this program; if not, write to the Free Software Foundation, Inc.,
16* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17*
18* Description:
19*/
20/*#include "register.h"*/
21/*#include "c_arc_pointer_reg.h"*/
22/*#include "a9_func.h"*/
23/*#include "clk_util.h"*/
24/*#include "c_stimulus.h"*/
25/*#include "a9_l2_func.h"*/
26
27#include "demod_func.h"
28#include <linux/dvb/aml_demod.h>
29#include <linux/string.h>
30#include <linux/kernel.h>
31#include "acf_filter_coefficient.h"
32#include <linux/mutex.h>
33
34#define M6D
35
36/* static void __iomem * demod_meson_reg_map[4]; */
37
38#define pr_dbg(fmt, args ...) \
39 do { \
40 if (debug_demod) \
41 pr_info("FE: " fmt, ## args); \
42 } while (0)
43#define pr_error(fmt, args ...) pr_info("FE: " fmt, ## args)
44
45MODULE_PARM_DESC(debug_demod, "\n\t\t Enable frontend debug information");
46static int debug_demod;
47module_param(debug_demod, int, 0644);
48
49MODULE_PARM_DESC(demod_timeout, "\n\t\t timeout debug information");
50static int demod_timeout = 120;
51module_param(demod_timeout, int, 0644);
52
53MODULE_PARM_DESC(demod_sync_count, "\n\t\t timeout debug information");
54static int demod_sync_count = 60;
55module_param(demod_sync_count, int, 0644);
56
57MODULE_PARM_DESC(demod_sync_delay_time, "\n\t\t timeout debug information");
58static int demod_sync_delay_time = 8;
59module_param(demod_sync_delay_time, int, 0644);
60
61
62
63MODULE_PARM_DESC(demod_mobile_power, "\n\t\t demod_mobile_power debug information");
64static int demod_mobile_power = 100;
65module_param(demod_mobile_power, int, 0644);
66
67MODULE_PARM_DESC(demod_enable_performance, "\n\t\t demod_enable_performance information");
68static int demod_enable_performance = 1;
69module_param(demod_enable_performance, int, 0644);
70
71
72static struct mutex mp;
73static struct mutex dtvpll_init_lock;
74static int dtvpll_init;
75static int dtmb_spectrum = 2;
76
77
78/* 8vsb */
79static struct atsc_cfg list_8vsb[22] = {
80 {0x0733, 0x00, 0},
81 {0x0734, 0xff, 0},
82 {0x0716, 0x02, 0}, /* F06[7] invert spectrum 0x02 0x06 */
83 {0x05e7, 0x00, 0},
84 {0x05e8, 0x00, 0},
85 {0x0f06, 0x80, 0},
86 {0x0f09, 0x04, 0},
87 {0x070c, 0x18, 0},
88 {0x070d, 0x9d, 0},
89 {0x070e, 0x89, 0},
90 {0x070f, 0x6a, 0},
91 {0x0710, 0x75, 0},
92 {0x0711, 0x6f, 0},
93 {0x072a, 0x02, 0},
94 {0x072c, 0x02, 0},
95 {0x090d, 0x03, 0},
96 {0x090e, 0x02, 0},
97 {0x090f, 0x00, 0},
98 {0x0900, 0x01, 0},
99 {0x0900, 0x00, 0},
100 {0x0f00, 0x01, 0},
101 {0x0000, 0x00, 1}
102};
103
104/* 64qam */
105static struct atsc_cfg list_qam64[111] = {
106 {0x0900, 0x01, 0},
107 {0x0f04, 0x08, 0},
108 {0x0f06, 0x80, 0},
109 {0x0f07, 0x00, 0},
110 {0x0f00, 0xe0, 0},
111 {0x0f00, 0xec, 0},
112 {0x0001, 0x05, 0},
113 {0x0002, 0x61, 0}, /* /0x61 invert spectrum */
114 {0x0003, 0x3e, 0},
115 {0x0004, 0xed, 0}, /* 0x9d */
116 {0x0005, 0x10, 0},
117 {0x0006, 0xc0, 0},
118 {0x0007, 0x5c, 0},
119 {0x0008, 0x0f, 0},
120 {0x0009, 0x4f, 0},
121 {0x000a, 0xfc, 0},
122 {0x000b, 0x0c, 0},
123 {0x000c, 0x6c, 0},
124 {0x000d, 0x3a, 0},
125 {0x000e, 0x10, 0},
126 {0x000f, 0x02, 0},
127 {0x0011, 0x00, 0},
128 {0x0012, 0xf5, 0},
129 {0x0013, 0x74, 0},
130 {0x0014, 0xb9, 0},
131 {0x0015, 0x1f, 0},
132 {0x0016, 0x80, 0},
133 {0x0017, 0x1f, 0},
134 {0x0018, 0x0f, 0},
135 {0x001e, 0x00, 0},
136 {0x001f, 0x00, 0},
137 {0x0023, 0x03, 0},
138 {0x0025, 0x20, 0},
139 {0x0026, 0xff, 0},
140 {0x0027, 0xff, 0},
141 {0x0028, 0xf8, 0},
142 {0x0200, 0x20, 0},
143 {0x0201, 0x62, 0},
144 {0x0202, 0x23, 0},
145 {0x0204, 0x19, 0},
146 {0x0205, 0x74, 0},
147 {0x0206, 0xab, 0},
148 {0x0207, 0xff, 0},
149 {0x0208, 0xc0, 0},
150 {0x0209, 0xff, 0},
151 {0x0211, 0xc0, 0},
152 {0x0212, 0xb0, 0},
153 {0x0213, 0x05, 0},
154 {0x0215, 0x08, 0},
155 {0x0222, 0xe0, 0},
156 {0x0223, 0xf0, 0},
157 {0x0226, 0x40, 0},
158 {0x0229, 0x23, 0},
159 {0x022a, 0x02, 0},
160 {0x022c, 0x01, 0},
161 {0x022e, 0x01, 0},
162 {0x022f, 0x25, 0},
163 {0x0230, 0x40, 0},
164 {0x0231, 0x01, 0},
165 {0x0734, 0xff, 0},
166 {0x073a, 0xff, 0},
167 {0x073b, 0x04, 0},
168 {0x073c, 0x08, 0},
169 {0x073d, 0x08, 0},
170 {0x073e, 0x01, 0},
171 {0x073f, 0xf8, 0},
172 {0x0740, 0xf1, 0},
173 {0x0741, 0xf3, 0},
174 {0x0742, 0xff, 0},
175 {0x0743, 0x0f, 0},
176 {0x0744, 0x1a, 0},
177 {0x0745, 0x16, 0},
178 {0x0746, 0x00, 0},
179 {0x0747, 0xe3, 0},
180 {0x0748, 0xce, 0},
181 {0x0749, 0xd4, 0},
182 {0x074a, 0x00, 0},
183 {0x074b, 0x4b, 0},
184 {0x074c, 0x00, 0},
185 {0x074d, 0xa2, 0},
186 {0x074e, 0x00, 0},
187 {0x074f, 0xe6, 0},
188 {0x0750, 0x00, 0},
189 {0x0751, 0x00, 0},
190 {0x0752, 0x01, 0},
191 {0x0753, 0x03, 0},
192 {0x0400, 0x00, 0},
193 {0x0408, 0x04, 0},
194 {0x040e, 0xe0, 0},
195 {0x0500, 0x02, 0},
196 {0x05e7, 0x00, 0},
197 {0x05e8, 0x00, 0},
198 {0x0f09, 0x18, 0},
199 {0x070c, 0x20, 0},
200 {0x070d, 0x41, 0}, /* 0x49 */
201 {0x070e, 0x04, 0}, /* 0x37 */
202 {0x070f, 0x00, 0},
203 {0x0710, 0x00, 0},
204 {0x0711, 0x00, 0},
205 {0x0716, 0xf0, 0},
206 {0x090f, 0x00, 0},
207 {0x0900, 0x01, 1},
208 {0x0900, 0x00, 0},
209 {0x0001, 0xf5, 0},
210 {0x0001, 0xf5, 1},
211 {0x0001, 0xf5, 1},
212 {0x0001, 0xf5, 1},
213 {0x0001, 0xf5, 1},
214 {0x0001, 0x05, 0},
215 {0x0001, 0x05, 1},
216 {0x0000, 0x00, 1}
217};
218
219/* 256qam */
220static struct atsc_cfg list_qam256[113] = {
221 {0x0900, 0x01, 0},
222 {0x0f04, 0x08, 0},
223 {0x0f06, 0x80, 0},
224 {0x0f00, 0xe0, 0},
225 {0x0f00, 0xec, 0},
226 {0x0001, 0x05, 0},
227 {0x0002, 0x01, 0}, /* 0x09 */
228 {0x0003, 0x2c, 0},
229 {0x0004, 0x91, 0},
230 {0x0005, 0x10, 0},
231 {0x0006, 0xc0, 0},
232 {0x0007, 0x5c, 0},
233 {0x0008, 0x0f, 0},
234 {0x0009, 0x4f, 0},
235 {0x000a, 0xfc, 0},
236 {0x000b, 0x0c, 0},
237 {0x000c, 0x6c, 0},
238 {0x000d, 0x3a, 0},
239 {0x000e, 0x10, 0},
240 {0x000f, 0x02, 0},
241 {0x0011, 0x80, 0},
242 {0x0012, 0xf5, 0}, /* a5 */
243 {0x0013, 0x74, 0},
244 {0x0014, 0xb9, 0},
245 {0x0015, 0x1f, 0},
246 {0x0016, 0x80, 0},
247 {0x0017, 0x1f, 0},
248 {0x0018, 0x0f, 0},
249 {0x001e, 0x00, 0},
250 {0x001f, 0x00, 0},
251 {0x0023, 0x03, 0},
252 {0x0025, 0x20, 0},
253 {0x0026, 0xff, 0},
254 {0x0027, 0xff, 0},
255 {0x0028, 0xf8, 0},
256 {0x0200, 0x20, 0},
257 {0x0201, 0x62, 0},
258 {0x0202, 0x23, 0},
259 {0x0204, 0x19, 0},
260 {0x0205, 0x76, 0},
261 {0x0206, 0xd2, 0},
262 {0x0207, 0xff, 0},
263 {0x0208, 0xc0, 0},
264 {0x0209, 0xff, 0},
265 {0x0211, 0xc0, 0},
266 {0x0212, 0xb0, 0},
267 {0x0213, 0x05, 0},
268 {0x0215, 0x08, 0},
269 {0x0222, 0xf0, 0},
270 {0x0223, 0xff, 0},
271 {0x0226, 0x40, 0},
272 {0x0229, 0x23, 0},
273 {0x022a, 0x02, 0},
274 {0x022c, 0x01, 0},
275 {0x022e, 0x01, 0},
276 {0x022f, 0x05, 0},
277 {0x0230, 0x40, 0},
278 {0x0231, 0x01, 0},
279 {0x0400, 0x02, 0},
280 {0x0401, 0x30, 0},
281 {0x0402, 0x13, 0},
282 {0x0406, 0x06, 0},
283 {0x0408, 0x04, 0},
284 {0x040e, 0xe0, 0},
285 {0x0411, 0x02, 0},
286 {0x073a, 0x02, 0},
287 {0x073b, 0x09, 0},
288 {0x073c, 0x0c, 0},
289 {0x073d, 0x08, 0},
290 {0x073e, 0xfd, 0},
291 {0x073f, 0xf2, 0},
292 {0x0740, 0xed, 0},
293 {0x0741, 0xf4, 0},
294 {0x0742, 0x03, 0},
295 {0x0743, 0x15, 0},
296 {0x0744, 0x1d, 0},
297 {0x0745, 0x15, 0},
298 {0x0746, 0xfc, 0},
299 {0x0747, 0xde, 0},
300 {0x0748, 0xcc, 0},
301 {0x0749, 0xd6, 0},
302 {0x074a, 0x04, 0},
303 {0x074b, 0x4f, 0},
304 {0x074c, 0x00, 0},
305 {0x074d, 0xa2, 0},
306 {0x074e, 0x00, 0},
307 {0x074f, 0xe3, 0},
308 {0x0750, 0x00, 0},
309 {0x0751, 0xfc, 0},
310 {0x0752, 0x00, 0},
311 {0x0753, 0x03, 0},
312 {0x0500, 0x02, 0},
313 {0x05e7, 0x00, 0},
314 {0x05e8, 0x00, 0},
315 {0x0f09, 0x18, 0},
316 {0x070c, 0x20, 0},
317 {0x070d, 0x49, 0},
318 {0x070e, 0x37, 0},
319 {0x070f, 0x00, 0},
320 {0x0710, 0x00, 0},
321 {0x0711, 0x00, 0},
322 {0x0716, 0xf0, 0},
323 {0x090f, 0x00, 0},
324 {0x0900, 0x01, 1},
325 {0x0900, 0x00, 0},
326 {0x0001, 0xf5, 0},
327 {0x0001, 0xf5, 1},
328 {0x0001, 0xf5, 1},
329 {0x0001, 0xf5, 1},
330 {0x0001, 0xf5, 1},
331 {0x0001, 0x05, 0},
332 {0x0001, 0x05, 1},
333 {0x0000, 0x00, 1}
334};
335
336void dtvpll_lock_init(void)
337{
338 mutex_init(&dtvpll_init_lock);
339}
340
341void dtvpll_init_flag(int on)
342{
343 mutex_lock(&dtvpll_init_lock);
344 dtvpll_init = on;
345 mutex_unlock(&dtvpll_init_lock);
346 pr_err("%s %d\n", __func__, on);
347}
348
349int get_dtvpll_init_flag(void)
350{
351 int val;
352
353 mutex_lock(&dtvpll_init_lock);
354 val = dtvpll_init;
355 mutex_unlock(&dtvpll_init_lock);
356 if (!val)
357 pr_err("%s: %d\n", __func__, val);
358 return val;
359}
360
361void adc_dpll_setup(int clk_a, int clk_b, int clk_sys)
362{
363 int unit, found, ena, enb, div2;
364 int pll_m, pll_n, pll_od_a, pll_od_b, pll_xd_a, pll_xd_b;
365 long freq_osc, freq_dco, freq_b, freq_a, freq_sys;
366 long freq_b_act, freq_a_act, freq_sys_act, err_tmp, best_err;
367 union adc_pll_cntl adc_pll_cntl;
368 union adc_pll_cntl2 adc_pll_cntl2;
369 union adc_pll_cntl3 adc_pll_cntl3;
370 union adc_pll_cntl4 adc_pll_cntl4;
371 union demod_dig_clk dig_clk_cfg;
372
373 adc_pll_cntl.d32 = 0;
374 adc_pll_cntl2.d32 = 0;
375 adc_pll_cntl3.d32 = 0;
376 adc_pll_cntl4.d32 = 0;
377
378 pr_dbg("target clk_a %d clk_b %d\n", clk_a, clk_b);
379
380 unit = 10000; /* 10000 as 1 MHz, 0.1 kHz resolution. */
381 freq_osc = 24 * unit;
382
383 if (clk_a < 1000)
384 freq_a = clk_a * unit;
385 else
386 freq_a = clk_a * (unit / 1000);
387
388 if (clk_b < 1000)
389 freq_b = clk_b * unit;
390 else
391 freq_b = clk_b * (unit / 1000);
392
393 ena = clk_a > 0 ? 1 : 0;
394 enb = clk_b > 0 ? 1 : 0;
395
396 if (ena || enb)
397 adc_pll_cntl3.b.enable = 1;
398 adc_pll_cntl3.b.reset = 1;
399
400 found = 0;
401 best_err = 100 * unit;
402 pll_od_a = 1;
403 pll_od_b = 1;
404 pll_n = 1;
405 for (pll_m = 1; pll_m < 512; pll_m++) {
406 /* for (pll_n=1; pll_n<=5; pll_n++) { */
407 if (is_meson_txl_cpu()) {
408 freq_dco = freq_osc * pll_m / pll_n / 2;/*txl add div2*/
409 if (freq_dco < 700 * unit || freq_dco > 1000 * unit)
410 continue;
411 } else {
412 freq_dco = freq_osc * pll_m / pll_n;
413 if (freq_dco < 750 * unit || freq_dco > 1550 * unit)
414 continue;
415 }
416 pll_xd_a = freq_dco / (1 << pll_od_a) / freq_a;
417 pll_xd_b = freq_dco / (1 << pll_od_b) / freq_b;
418
419 freq_a_act = freq_dco / (1 << pll_od_a) / pll_xd_a;
420 freq_b_act = freq_dco / (1 << pll_od_b) / pll_xd_b;
421
422 err_tmp = (freq_a_act - freq_a) * ena + (freq_b_act - freq_b) *
423 enb;
424
425 if (err_tmp >= best_err)
426 continue;
427
428 adc_pll_cntl.b.pll_m = pll_m;
429 adc_pll_cntl.b.pll_n = pll_n;
430 adc_pll_cntl.b.pll_od0 = pll_od_b;
431 adc_pll_cntl.b.pll_od1 = pll_od_a;
432 adc_pll_cntl.b.pll_xd0 = pll_xd_b;
433 adc_pll_cntl.b.pll_xd1 = pll_xd_a;
434 if (is_meson_txl_cpu()) {
435 adc_pll_cntl4.b.pll_od3 = 0;
436 adc_pll_cntl.b.pll_od2 = 0;
437 } else {
438 adc_pll_cntl2.b.div2_ctrl =
439 freq_dco > 1000 * unit ? 1 : 0;
440 }
441 found = 1;
442 best_err = err_tmp;
443 /* } */
444 }
445
446 pll_m = adc_pll_cntl.b.pll_m;
447 pll_n = adc_pll_cntl.b.pll_n;
448 pll_od_b = adc_pll_cntl.b.pll_od0;
449 pll_od_a = adc_pll_cntl.b.pll_od1;
450 pll_xd_b = adc_pll_cntl.b.pll_xd0;
451 pll_xd_a = adc_pll_cntl.b.pll_xd1;
452
453 if (is_meson_txl_cpu())
454 div2 = 1;
455 else
456 div2 = adc_pll_cntl2.b.div2_ctrl;
457 /*
458 * p_adc_pll_cntl = adc_pll_cntl.d32;
459 * p_adc_pll_cntl2 = adc_pll_cntl2.d32;
460 * p_adc_pll_cntl3 = adc_pll_cntl3.d32;
461 * p_adc_pll_cntl4 = adc_pll_cntl4.d32;
462 */
463 adc_pll_cntl3.b.reset = 0;
464 /* *p_adc_pll_cntl3 = adc_pll_cntl3.d32; */
465 if (!found) {
466 pr_dbg(" ERROR can't setup %7ld kHz %7ld kHz\n",
467 freq_b / (unit / 1000), freq_a / (unit / 1000));
468 } else {
469 if (is_meson_txl_cpu())
470 freq_dco = freq_osc * pll_m / pll_n / 2;
471 else
472 freq_dco = freq_osc * pll_m / pll_n;
473 pr_dbg(" ADC PLL M %3d N %3d\n", pll_m, pll_n);
474 pr_dbg(" ADC PLL DCO %ld kHz\n", freq_dco / (unit / 1000));
475
476 pr_dbg(" ADC PLL XD %3d OD %3d\n", pll_xd_b, pll_od_b);
477 pr_dbg(" ADC PLL XD %3d OD %3d\n", pll_xd_a, pll_od_a);
478
479 freq_a_act = freq_dco / (1 << pll_od_a) / pll_xd_a;
480 freq_b_act = freq_dco / (1 << pll_od_b) / pll_xd_b;
481
482 pr_dbg(" B %7ld kHz %7ld kHz\n",
483 freq_b / (unit / 1000), freq_b_act / (unit / 1000));
484 pr_dbg(" A %7ld kHz %7ld kHz\n",
485 freq_a / (unit / 1000), freq_a_act / (unit / 1000));
486
487 if (clk_sys > 0) {
488 dig_clk_cfg.b.demod_clk_en = 1;
489 dig_clk_cfg.b.demod_clk_sel = 3;
490 if (clk_sys < 1000)
491 freq_sys = clk_sys * unit;
492 else
493 freq_sys = clk_sys * (unit / 1000);
494
495 dig_clk_cfg.b.demod_clk_div = freq_dco / (1 + div2) /
496 freq_sys - 1;
497 freq_sys_act = freq_dco / (1 + div2) /
498 (dig_clk_cfg.b.demod_clk_div + 1);
499 pr_dbg(" SYS %7ld kHz div %d+1 %7ld kHz\n",
500 freq_sys / (unit / 1000),
501 dig_clk_cfg.b.demod_clk_div,
502 freq_sys_act / (unit / 1000));
503 } else {
504 dig_clk_cfg.b.demod_clk_en = 0;
505 }
506
507 /* *p_demod_dig_clk = dig_clk_cfg.d32; */
508 }
509 if (is_meson_txl_cpu()) {
510 demod_set_demod_reg(TXLTV_ADC_RESET_VALUE, ADC_REG3);
511 demod_set_demod_reg(adc_pll_cntl.d32, ADC_REG1);
512 demod_set_demod_reg(dig_clk_cfg.d32, ADC_REG6);
513 demod_set_demod_reg(TXLTV_ADC_REG3_VALUE, ADC_REG3);
514 /* debug */
515 pr_dbg("[adc][%x]%x\n", ADC_REG1,
516 demod_read_demod_reg(ADC_REG1));
517 pr_dbg("[adc][%x]%x\n", ADC_REG2,
518 demod_read_demod_reg(ADC_REG2));
519 pr_dbg("[adc][%x]%x\n", ADC_REG3,
520 demod_read_demod_reg(ADC_REG3));
521 pr_dbg("[adc][%x]%x\n", ADC_REG4,
522 demod_read_demod_reg(ADC_REG4));
523 pr_dbg("[adc][%x]%x\n", ADC_REG5,
524 demod_read_demod_reg(ADC_REG5));
525 pr_dbg("[adc][%x]%x\n", ADC_REG6,
526 demod_read_demod_reg(ADC_REG6));
527 pr_dbg("[adc][%x]%x\n", ADC_REG7,
528 demod_read_demod_reg(ADC_REG7));
529 pr_dbg("[adc][%x]%x\n", ADC_REG8,
530 demod_read_demod_reg(ADC_REG8));
531 pr_dbg("[adc][%x]%x\n", ADC_REG9,
532 demod_read_demod_reg(ADC_REG9));
533 pr_dbg("[adc][%x]%x\n", ADC_REGB,
534 demod_read_demod_reg(ADC_REGB));
535 pr_dbg("[adc][%x]%x\n", ADC_REGC,
536 demod_read_demod_reg(ADC_REGC));
537 pr_dbg("[adc][%x]%x\n", ADC_REGD,
538 demod_read_demod_reg(ADC_REGD));
539 pr_dbg("[adc][%x]%x\n", ADC_REGE,
540 demod_read_demod_reg(ADC_REGE));
541 pr_dbg("[demod][%x]%x\n", DEMOD_REG1,
542 demod_read_demod_reg(DEMOD_REG1));
543 pr_dbg("[demod][%x]%x\n", DEMOD_REG2,
544 demod_read_demod_reg(DEMOD_REG2));
545 pr_dbg("[demod][%x]%x\n", DEMOD_REG3,
546 demod_read_demod_reg(DEMOD_REG3));
547 } else {
548 demod_set_demod_reg(ADC_RESET_VALUE, ADC_REG3); /* adc reset */
549 demod_set_demod_reg(adc_pll_cntl.d32, ADC_REG1);
550 demod_set_demod_reg(dig_clk_cfg.d32, ADC_REG6);
551 demod_set_demod_reg(ADC_REG3_VALUE, ADC_REG3);
552 /* debug */
553 pr_dbg("[adc][%x]%x\n", ADC_REG1,
554 demod_read_demod_reg(ADC_REG1));
555 pr_dbg("[adc][%x]%x\n", ADC_REG2,
556 demod_read_demod_reg(ADC_REG2));
557 pr_dbg("[adc][%x]%x\n", ADC_REG3,
558 demod_read_demod_reg(ADC_REG3));
559 pr_dbg("[adc][%x]%x\n", ADC_REG4,
560 demod_read_demod_reg(ADC_REG4));
561 pr_dbg("[adc][%x]%x\n", ADC_REG6,
562 demod_read_demod_reg(ADC_REG6));
563 pr_dbg("[demod][%x]%x\n", DEMOD_REG1,
564 demod_read_demod_reg(DEMOD_REG1));
565 pr_dbg("[demod][%x]%x\n", DEMOD_REG2,
566 demod_read_demod_reg(DEMOD_REG2));
567 pr_dbg("[demod][%x]%x\n", DEMOD_REG3,
568 demod_read_demod_reg(DEMOD_REG3));
569 }
570 dtvpll_init_flag(1);
571}
572
573void demod_set_adc_core_clk(int adc_clk, int sys_clk, int dvb_mode)
574{
575 adc_dpll_setup(25, adc_clk, sys_clk);
576}
577
578void demod_set_cbus_reg(unsigned int data, unsigned int addr)
579{
580 void __iomem *vaddr;
581
582 pr_dbg("[cbus][write]%x\n", (IO_CBUS_PHY_BASE + (addr << 2)));
583 vaddr = ioremap((IO_CBUS_PHY_BASE + (addr << 2)), 0x4);
584 writel(data, vaddr);
585 iounmap(vaddr);
586}
587
588unsigned int demod_read_cbus_reg(unsigned int addr)
589{
590/* return __raw_readl(CBUS_REG_ADDR(addr)); */
591 unsigned int tmp;
592 void __iomem *vaddr;
593
594 vaddr = ioremap((IO_CBUS_PHY_BASE + (addr << 2)), 0x4);
595 tmp = readl(vaddr);
596 iounmap(vaddr);
597/* tmp = aml_read_cbus(addr); */
598 pr_dbg("[cbus][read]%x,data is %x\n",
599 (IO_CBUS_PHY_BASE + (addr << 2)), tmp);
600 return tmp;
601}
602
603void demod_set_ao_reg(unsigned int data, unsigned int addr)
604{
605 void __iomem *vaddr;
606
607/* pr_dbg("[ao][write]%x,data is %x\n",(IO_AOBUS_BASE+addr),data); */
608 vaddr = ioremap((IO_AOBUS_BASE + addr), 0x4);
609 writel(data, vaddr);
610 iounmap(vaddr);
611}
612
613unsigned int demod_read_ao_reg(unsigned int addr)
614{
615 unsigned int tmp;
616 void __iomem *vaddr;
617
618/* pr_dbg("[ao][read]%x\n",(IO_AOBUS_BASE+addr)); */
619 vaddr = ioremap((IO_AOBUS_BASE + addr), 0x4);
620 tmp = readl(vaddr);
621/* pr_dbg("[ao][read]%x,data is %x\n",(IO_AOBUS_BASE+addr),tmp); */
622 iounmap(vaddr);
623 return tmp;
624}
625
626void demod_set_demod_reg(unsigned int data, unsigned int addr)
627{
628 void __iomem *vaddr;
629
630 mutex_lock(&mp);
631/* printk("[demod][write]%x,data is %x\n",(addr),data); */
632 vaddr = ioremap((addr), 0x4);
633 writel(data, vaddr);
634 iounmap(vaddr);
635 mutex_unlock(&mp);
636}
637
638unsigned int demod_read_demod_reg(unsigned int addr)
639{
640 unsigned int tmp;
641 void __iomem *vaddr;
642
643 mutex_lock(&mp);
644 vaddr = ioremap((addr), 0x4);
645 tmp = readl(vaddr);
646 iounmap(vaddr);
647 mutex_unlock(&mp);
648/* printk("[demod][read]%x,data is %x\n",(addr),tmp); */
649 return tmp;
650}
651
652void demod_power_switch(int pwr_cntl)
653{
654 int reg_data;
655#if 1
656 if (pwr_cntl == PWR_ON) {
657 pr_dbg("[PWR]: Power on demod_comp %x,%x\n",
658 AO_RTI_GEN_PWR_SLEEP0, AO_RTI_GEN_PWR_ISO0);
659 /* Powerup demod_comb */
660 reg_data = demod_read_ao_reg(AO_RTI_GEN_PWR_SLEEP0);
661 demod_set_ao_reg((reg_data & (~(0x1 << 10))),
662 AO_RTI_GEN_PWR_SLEEP0);
663 /* [10] power on */
664 pr_dbg("[PWR]: Power on demod_comp %x,%x\n",
665 HHI_DEMOD_MEM_PD_REG, RESET0_LEVEL);
666 /* Power up memory */
667 demod_set_demod_reg((demod_read_demod_reg(HHI_DEMOD_MEM_PD_REG)
668 & (~0x2fff)), HHI_DEMOD_MEM_PD_REG);
669 /* reset */
670 demod_set_demod_reg((demod_read_demod_reg(RESET0_LEVEL) &
671 (~(0x1 << 8))), RESET0_LEVEL);
672 /* msleep(20);*/
673
674 /* remove isolation */
675 demod_set_ao_reg(
676 (demod_read_ao_reg(AO_RTI_GEN_PWR_ISO0) &
677 (~(0x3 << 14))), AO_RTI_GEN_PWR_ISO0);
678 /* pull up reset */
679 demod_set_demod_reg((demod_read_demod_reg(RESET0_LEVEL) |
680 (0x1 << 8)), RESET0_LEVEL);
681/* *P_RESET0_LEVEL |= (0x1<<8); */
682 } else {
683 pr_dbg("[PWR]: Power off demod_comp\n");
684 /* add isolation */
685
686 demod_set_ao_reg(
687 (demod_read_ao_reg(AO_RTI_GEN_PWR_ISO0) |
688 (0x3 << 14)), AO_RTI_GEN_PWR_ISO0);
689
690 /* power down memory */
691 demod_set_demod_reg((demod_read_demod_reg(HHI_DEMOD_MEM_PD_REG)
692 | 0x2fff), HHI_DEMOD_MEM_PD_REG);
693 /* power down demod_comb */
694 reg_data = demod_read_ao_reg(AO_RTI_GEN_PWR_SLEEP0);
695 demod_set_ao_reg((reg_data | (0x1 << 10)),
696 AO_RTI_GEN_PWR_SLEEP0);
697 /* [10] power on */
698 }
699#endif
700}
701
702static void clocks_set_sys_defaults(unsigned char dvb_mode)
703{
704 union demod_cfg0 cfg0;
705 union demod_cfg2 cfg2;
706
707 demod_power_switch(PWR_ON);
708
709 if (is_meson_gxtvbb_cpu()) {
710 pr_dbg("GX_TV config\n");
711 demod_set_demod_reg(ADC_RESET_VALUE, ADC_REG3);
712 demod_set_demod_reg(ADC_REG1_VALUE, ADC_REG1);
713 demod_set_demod_reg(ADC_REG2_VALUE, ADC_REG2);
714 demod_set_demod_reg(ADC_REG4_VALUE, ADC_REG4);
715 demod_set_demod_reg(ADC_REG3_VALUE, ADC_REG3);
716 /* dadc */
717 demod_set_demod_reg(ADC_REG7_VALUE, ADC_REG7);
718 demod_set_demod_reg(ADC_REG8_VALUE, ADC_REG8);
719 demod_set_demod_reg(ADC_REG9_VALUE, ADC_REG9);
720 demod_set_demod_reg(ADC_REGA_VALUE, ADC_REGA);
721 } else if (is_meson_txl_cpu()) {
722 pr_dbg("TXL_TV config\n");
723 demod_set_demod_reg(TXLTV_ADC_REG3_VALUE, ADC_REG3);
724 demod_set_demod_reg(TXLTV_ADC_REG1_VALUE, ADC_REG1);
725 demod_set_demod_reg(TXLTV_ADC_REGB_VALUE, ADC_REGB);
726 demod_set_demod_reg(TXLTV_ADC_REG2_VALUE, ADC_REG2);
727 demod_set_demod_reg(TXLTV_ADC_REG3_VALUE, ADC_REG3);
728 demod_set_demod_reg(TXLTV_ADC_REG4_VALUE, ADC_REG4);
729 demod_set_demod_reg(TXLTV_ADC_REGC_VALUE, ADC_REGC);
730 demod_set_demod_reg(TXLTV_ADC_REGD_VALUE, ADC_REGD);
731 demod_set_demod_reg(TXLTV_ADC_RESET_VALUE, ADC_REG3);
732 demod_set_demod_reg(TXLTV_ADC_REG3_VALUE, ADC_REG3);
733
734 /* dadc */
735 demod_set_demod_reg(TXLTV_ADC_REG7_VALUE, ADC_REG7);
736 demod_set_demod_reg(TXLTV_ADC_REG8_VALUE, ADC_REG8);
737 demod_set_demod_reg(TXLTV_ADC_REG9_VALUE, ADC_REG9);
738 demod_set_demod_reg(TXLTV_ADC_REGE_VALUE, ADC_REGE);
739 }
740
741 demod_set_demod_reg(DEMOD_REG1_VALUE, DEMOD_REG1);
742 demod_set_demod_reg(DEMOD_REG2_VALUE, DEMOD_REG2);
743 demod_set_demod_reg(DEMOD_REG3_VALUE, DEMOD_REG3);
744 cfg0.b.mode = 7;
745 cfg0.b.adc_format = 1;
746 if (dvb_mode == Gxtv_Dvbc) { /* // 0 -DVBC, 1-DVBT, ISDBT, 2-ATSC */
747 cfg0.b.ts_sel = 2;
748 } else if ((dvb_mode == Gxtv_Dvbt_Isdbt) || (dvb_mode == Gxtv_Dtmb)) {
749 cfg0.b.ts_sel = 1;
750 cfg0.b.adc_regout = 1;
751 } else if (dvb_mode == Gxtv_Atsc) {
752 cfg0.b.ts_sel = 4;
753 }
754 demod_set_demod_reg(cfg0.d32, DEMOD_REG1);
755 cfg2.b.biasgen_en = 1;
756 cfg2.b.en_adc = 1;
757 demod_set_demod_reg(cfg2.d32, DEMOD_REG3);
758 pr_dbg("0xc8020c00 is %x,dvb_mode is %d\n",
759 demod_read_demod_reg(DEMOD_REG1), dvb_mode);
760}
761
762void dtmb_write_reg(int reg_addr, int reg_data)
763{
764 if (!get_dtvpll_init_flag())
765 return;
766 demod_set_demod_reg(reg_data, reg_addr);
767/* apb_write_reg(reg_addr,reg_data); */
768}
769
770int dtmb_read_reg(int reg_addr)
771{
772 if (!get_dtvpll_init_flag())
773 return 0;
774 return demod_read_demod_reg(reg_addr); /* apb_read_reg(reg_addr); */
775}
776
777void atsc_write_reg(int reg_addr, int reg_data)
778{
779 if (!get_dtvpll_init_flag())
780 return;
781 apb_write_reg(ATSC_BASE, (reg_addr & 0xffff) << 8 | (reg_data & 0xff));
782}
783
784unsigned long atsc_read_reg(int reg_addr)
785{
786 unsigned long tmp;
787
788 if (!get_dtvpll_init_flag())
789 return 0;
790 apb_write_reg(ATSC_BASE + 4, (reg_addr & 0xffff) << 8);
791 tmp = apb_read_reg(ATSC_BASE);
792
793 return tmp & 0xff;
794}
795
796unsigned long atsc_read_iqr_reg(void)
797{
798 unsigned long tmp;
799
800 tmp = apb_read_reg(ATSC_BASE + 8);
801 pr_dbg("[atsc irq] is %lx\n", tmp);
802 return tmp & 0xffffffff;
803}
804
805int atsc_qam_set(fe_modulation_t mode)
806{
807 int i, j;
808
809 if (mode == VSB_8) { /* 5-8vsb, 2-64qam, 4-256qam */
810 for (i = 0; list_8vsb[i].adr != 0; i++) {
811 if (list_8vsb[i].rw)
812 atsc_read_reg(list_8vsb[i].adr);
813 /* msleep(20); */
814 else
815 atsc_write_reg(list_8vsb[i].adr,
816 list_8vsb[i].dat);
817 /* msleep(20); */
818 }
819 j = 15589;
820 pr_dbg("8-vsb mode\n");
821 } else if (mode == QAM_64) {
822 for (i = 0; list_qam64[i].adr != 0; i++) {
823 if (list_qam64[i].rw) {
824 atsc_read_reg(list_qam64[i].adr);
825 msleep(20);
826 } else {
827 atsc_write_reg(list_qam64[i].adr,
828 list_qam64[i].dat);
829 msleep(20);
830 }
831 }
832 j = 16588; /* 33177; */
833 pr_dbg("64qam mode\n");
834 } else if (mode == QAM_256) {
835 for (i = 0; list_qam256[i].adr != 0; i++) {
836 if (list_qam256[i].rw) {
837 atsc_read_reg(list_qam256[i].adr);
838 msleep(20);
839 } else {
840 atsc_write_reg(list_qam256[i].adr,
841 list_qam256[i].dat);
842 msleep(20);
843 }
844 }
845 j = 15649; /* 31298; */
846 pr_dbg("256qam mode\n");
847 } else {
848 for (i = 0; list_qam256[i].adr != 0; i++) {
849 if (list_qam256[i].rw) {
850 atsc_read_reg(list_qam256[i].adr);
851 msleep(20);
852 } else {
853 atsc_write_reg(list_qam256[i].adr,
854 list_qam256[i].dat);
855 msleep(20);
856 }
857 }
858 j = 15649; /* 31298; */
859 pr_dbg("256qam mode\n");
860 }
861 return j;
862}
863
864void atsc_initial(struct aml_demod_sta *demod_sta)
865{
866 int fc, fs, cr, ck, j;
867 fe_modulation_t mode;
868
869 mode = demod_sta->ch_mode;
870
871 j = atsc_qam_set(mode); /* set mode */
872
873 fs = demod_sta->adc_freq; /* KHZ 25200 */
874 fc = demod_sta->ch_if; /* KHZ 6350 */
875
876 cr = (fc * (1 << 17) / fs) * (1 << 6);
877 ck = fs * j / 10 - (1 << 25);
878 /* ck_rate = (f_samp / f_vsb /2 -1)*(1<<25);
879 *double f_vsb = 10.76238;// double f_64q = 5.056941;
880 * // double f_256q = 5.360537;
881 */
882
883 atsc_write_reg(0x070e, cr & 0xff);
884 atsc_write_reg(0x070d, (cr >> 8) & 0xff);
885 atsc_write_reg(0x070c, (cr >> 16) & 0xff);
886
887 if (demod_sta->ch_mode == VSB_8) {
888 atsc_write_reg(0x0711, ck & 0xff);
889 atsc_write_reg(0x0710, (ck >> 8) & 0xff);
890 atsc_write_reg(0x070f, (ck >> 16) & 0xff);
891 }
892 pr_dbg("0x70e is %x, 0x70d is %x, 0x70c is %x\n", cr & 0xff,
893 (cr >> 8) & 0xff, (cr >> 16) & 0xff);
894 pr_dbg("fs is %d(SR),fc is %d(IF),cr is %x,ck is %x\n", fs, fc, cr, ck);
895}
896
897int atsc_set_ch(struct aml_demod_sta *demod_sta,
898 struct aml_demod_i2c *demod_i2c,
899 struct aml_demod_atsc *demod_atsc)
900{
901 int ret = 0;
902 u8 demod_mode;
903 u8 bw, sr, ifreq, agc_mode;
904 u32 ch_freq;
905
906 bw = demod_atsc->bw;
907 sr = demod_atsc->sr;
908 ifreq = demod_atsc->ifreq;
909 agc_mode = demod_atsc->agc_mode;
910 ch_freq = demod_atsc->ch_freq;
911 demod_mode = demod_atsc->dat0;
912 demod_sta->ch_mode = demod_atsc->mode; /* TODO */
913 demod_sta->agc_mode = agc_mode;
914 demod_sta->ch_freq = ch_freq;
915 demod_sta->dvb_mode = demod_mode;
916 demod_sta->ch_bw = (8 - bw) * 1000;
917 atsc_initial(demod_sta);
918 pr_dbg("ATSC mode\n");
919 return ret;
920}
921
922#if 0
923static dtmb_cfg_t list_dtmb_v1[99] = {
924 {0x00000000, 0x01, 0},
925 {0x00001000, 0x02, 0},
926 {0x00000000, 0x03, 0},
927 {0x00000000, 0x04, 0},
928 {0x00000000, 0x05, 0},
929 {0x00000000, 0x06, 0},
930 {0x007fffff, 0x07, 0},
931 {0x0000000f, 0x08, 0},
932 {0x00003000, 0x09, 0},
933 {0x00000001, 0x0a, 0},
934 {0x0c403006, 0x0b, 0},
935 {0x44444400, 0x0c, 0},
936 {0x1412c320, 0x0d, 0},
937 {0x00000152, 0x10, 0},
938 {0x47080137, 0x11, 0},
939 {0x02200a16, 0x12, 0},
940 {0x42190190, 0x13, 0},
941 {0x7f807f80, 0x14, 0},
942 {0x0000199a, 0x15, 0},
943 {0x000a1466, 0x18, 0},
944 {0x00274217, 0x1a, 0},
945 {0x00131036, 0x1b, 1},
946 {0x00000396, 0x1c, 0},
947 {0x0037f3cc, 0x1d, 0},
948 {0x00000029, 0x1e, 0},
949 {0x0004f031, 0x1f, 0},
950 {0x00f3cbd4, 0x20, 0},
951 {0x0000007e, 0x21, 0},
952 {0x23270b6a, 0x22, 0},
953 {0x5f700c1b, 0x23, 0},
954 {0x00133c2b, 0x24, 0},
955 {0x2d3e0f12, 0x25, 0},
956 {0x06363038, 0x26, 0},
957 {0x060e0a3e, 0x27, 0},
958 {0x0015161f, 0x28, 0},
959 {0x0809031b, 0x29, 0},
960 {0x181c0307, 0x2a, 0},
961 {0x051f1a1b, 0x2b, 0},
962 {0x00451dce, 0x2c, 0},
963 {0x242fde12, 0x2d, 0},
964 {0x0034e8fa, 0x2e, 0},
965 {0x00000007, 0x30, 0},
966 {0x16000d0c, 0x31, 0},
967 {0x0000011f, 0x32, 0},
968 {0x01000200, 0x33, 0},
969 {0x10bbf376, 0x34, 0},
970 {0x00000044, 0x35, 0},
971 {0x00000000, 0x36, 0},
972 {0x00000000, 0x37, 0},
973 {0x00000000, 0x38, 0},
974 {0x00000000, 0x39, 0},
975 {0x00000031, 0x3a, 0},
976 {0x4d6b0a58, 0x3b, 0},
977 {0x00000c04, 0x3c, 0},
978 {0x0d3b0a50, 0x3d, 0},
979 {0x03140480, 0x3e, 0},
980 {0x05e60452, 0x3f, 0},
981 {0x05780400, 0x40, 0},
982 {0x0063c025, 0x41, 0},
983 {0x05050202, 0x42, 0},
984 {0x5e4a0a14, 0x43, 0},
985 {0x00003b42, 0x44, 0},
986 {0xa53080ff, 0x45, 0},
987 {0x00000000, 0x46, 0},
988 {0x00133202, 0x47, 0},
989 {0x01f00000, 0x48, 0},
990 {0x00000000, 0x49, 0},
991 {0x00000000, 0x4a, 0},
992 {0x00000000, 0x4b, 0},
993 {0x00000000, 0x4c, 0},
994 {0x20405dc8, 0x4d, 0},
995 {0x00000000, 0x4e, 0},
996 {0x1f0205df, 0x4f, 0},
997 {0x00001120, 0x50, 0},
998 {0x4f190803, 0x51, 0},
999 {0x00000000, 0x52, 0},
1000 {0x00000040, 0x53, 0},
1001 {0x00100050, 0x54, 0},
1002 {0x00cd1000, 0x55, 0},
1003 {0x00010fab, 0x56, 0},
1004 {0x03f0fc3f, 0x58, 0},
1005 {0x02005014, 0x59, 0},
1006 {0x01405014, 0x5a, 0},
1007 {0x00014284, 0x5b, 0},
1008 {0x00000320, 0x5c, 0},
1009 {0x14130e05, 0x5d, 0},
1010 {0x4321c963, 0x5f, 0},
1011 {0x624668f8, 0x60, 0},
1012 {0xccc08888, 0x61, 0},
1013 {0x13212111, 0x62, 0},
1014 {0x21100000, 0x63, 0},
1015 {0x624668f8, 0x64, 0},
1016 {0xccc08888, 0x65, 0},
1017 {0x13212111, 0x66, 0},
1018 {0x21100000, 0x67, 0},
1019 {0x624668f8, 0x68, 0},
1020 {0xccc08888, 0x69, 0},
1021 {0x0, 0x0, 0}
1022};
1023#endif
1024
1025void dtmb_all_reset(void)
1026{
1027 int temp_data = 0;
1028
1029 if (is_meson_txl_cpu()) {
1030 dtmb_write_reg(DTMB_FRONT_AFIFO_ADC, 0x1f);
1031 /*modified bu xiaotong*/
1032 dtmb_write_reg(DTMB_CHE_TPS_CONFIG, 0xc00000);
1033 dtmb_write_reg(DTMB_CHE_EQ_CONFIG, 0x1a027719);
1034 dtmb_write_reg(DTMB_FRONT_AGC_CONFIG1, 0x101a7);
1035 dtmb_write_reg(DTMB_FRONT_47_CONFIG, 0x131a31);
1036 /*detect 64qam 420 595 problems*/
1037 dtmb_write_reg(DTMB_FRONT_19_CONFIG, 0x300);
1038 dtmb_write_reg(DTMB_FRONT_4d_CONFIG, 0x12ffbe0);
1039 /*fix fsm b bug*/
1040 dtmb_write_reg(DTMB_FRONT_DEBUG_CFG, 0x5680000);
1041 /*fix agc problem,skip warm_up status*/
1042 dtmb_write_reg(DTMB_FRONT_46_CONFIG, 0x1a000f0f);
1043 dtmb_write_reg(DTMB_FRONT_ST_FREQ, 0xf2400000);
1044 } else {
1045 dtmb_write_reg(DTMB_FRONT_AGC_CONFIG1, 0x10127);
1046 dtmb_write_reg(DTMB_CHE_IBDFE_CONFIG6, 0x943228cc);
1047 dtmb_write_reg(DTMB_CHE_IBDFE_CONFIG7, 0xc09aa8cd);
1048 dtmb_write_reg(DTMB_CHE_FD_TD_COEFF, 0x0);
1049 dtmb_write_reg(DTMB_CHE_EQ_CONFIG, 0x9dc59);
1050 /*0x2 is auto,0x406 is invert spectrum*/
1051 if (dtmb_spectrum == 0)
1052 dtmb_write_reg(DTMB_TOP_CTRL_TPS, 0x406);
1053 else if (dtmb_spectrum == 1)
1054 dtmb_write_reg(DTMB_TOP_CTRL_TPS, 0x402);
1055 else
1056 dtmb_write_reg(DTMB_TOP_CTRL_TPS, 0x2);
1057
1058 pr_dbg("dtmb_spectrum is %d\n", dtmb_spectrum);
1059 dtmb_write_reg(DTMB_TOP_CTRL_FEC, 0x41444400);
1060 dtmb_write_reg(DTMB_TOP_CTRL_INTLV_TIME, 0x180300);
1061 dtmb_write_reg(DTMB_FRONT_DDC_BYPASS, 0x662ca0);
1062 dtmb_write_reg(DTMB_FRONT_AFIFO_ADC, 0x29);
1063 dtmb_write_reg(DTMB_FRONT_DC_HOLD, 0xa1066);
1064 /*cci para*/
1065 dtmb_write_reg(DTMB_CHE_M_CCI_THR_CONFIG3, 0x80201f6);
1066 dtmb_write_reg(DTMB_CHE_M_CCI_THR_CONFIG2, 0x3f20080);
1067 dtmb_write_reg(DTMB_CHE_TPS_CONFIG, 0xc00000);
1068 dtmb_write_reg(DTMB_TOP_CTRL_AGC, 0x3);
1069 dtmb_write_reg(DTMB_TOP_CTRL_TS_SFO_CFO, 0x20403006);
1070 dtmb_write_reg(DTMB_FRONT_AGC_CONFIG2, 0x7200a16);
1071 dtmb_write_reg(DTMB_FRONT_DEBUG_CFG, 0x1e00000);
1072 dtmb_write_reg(DTMB_TOP_CTRL_ENABLE, 0x7fffff);
1073 /*close ts3 timing loop*/
1074 dtmb_write_reg(DTMB_TOP_CTRL_DAGC_CCI, 0x305);
1075 /*dektec card issue,close f case snr drop*/
1076 dtmb_write_reg(DTMB_CHE_MC_SC_TIMING_POWTHR, 0xc06100a);
1077 if (demod_enable_performance) {
1078 dtmb_write_reg(DTMB_CHE_IBDFE_CONFIG1, 0x4040002);
1079 temp_data = dtmb_read_reg(DTMB_CHE_FD_TD_COEFF);
1080 temp_data = (temp_data & ~0x3fff)|(0x241f & 0x3fff);
1081 temp_data = temp_data | (1<<21);
1082 /*Set freeze_mode and reset coeff*/
1083 dtmb_write_reg(DTMB_CHE_FD_TD_COEFF, temp_data);
1084 temp_data = temp_data & ~(1<<21);
1085 /*Set freeze_mode and reset coeff*/
1086 dtmb_write_reg(DTMB_CHE_FD_TD_COEFF, temp_data);
1087 }
1088 }
1089}
1090
1091void dtmb_initial(struct aml_demod_sta *demod_sta)
1092{
1093/* dtmb_write_reg(0x049, memstart); //only for init */
1094 dtmb_spectrum = 1;
1095 dtmb_spectrum = demod_sta->spectrum;
1096 dtmb_register_reset();
1097 dtmb_all_reset();
1098#if 0
1099 int i;
1100
1101 for (i = 0; list_dtmb_v1[i].adr != 0; i++) {
1102 if (list_dtmb_v1[i].rw)
1103 apb_read_reg(DTMB_BASE + ((list_dtmb_v1[i].adr) << 2));
1104 /* msleep(20); */
1105 else
1106 apb_write_reg(DTMB_BASE + ((list_dtmb_v1[i].adr) << 2),
1107 list_dtmb_v1[i].dat);
1108 /* msleep(20); */
1109 }
1110#endif
1111}
1112
1113int check_dtmb_fec_lock(void)
1114{
1115 int fec_lock, snr, status;
1116
1117 fec_lock = (dtmb_read_reg(DTMB_TOP_FEC_LOCK_SNR) >> 14) & 0x1;
1118 snr = dtmb_read_reg(DTMB_TOP_FEC_LOCK_SNR) & 0x3fff;
1119 if (fec_lock && (snr > 4))
1120 status = 1;
1121 else
1122 status = 0;
1123 return status;
1124}
1125
1126int check_dtmb_mobile_det(void)
1127{
1128 int mobile_det = 0;
1129
1130 mobile_det = (dtmb_read_reg(DTMB_TOP_CTRL_SYS_OFDM_CNT) >> 8) & 0x7ffff;
1131 return mobile_det;
1132
1133}
1134
1135
1136int dtmb_information(void)
1137{
1138 int tps, snr, fec_lock, fec_bch_add, fec_ldpc_unc_acc, fec_ldpc_it_avg,
1139 tmp, che_snr;
1140 struct aml_fe_dev *dev;
1141
1142 dev = NULL;
1143 tps = dtmb_read_reg(DTMB_TOP_CTRL_CHE_WORKCNT);
1144 tmp = dtmb_read_reg(DTMB_TOP_FEC_LOCK_SNR);
1145 if (is_meson_txl_cpu())
1146 che_snr = tmp & 0x3fff;
1147 else
1148 che_snr = tmp & 0xfff;
1149 snr = che_snr;
1150 snr = convert_snr(snr);
1151 /* if (che_snr >= 8192) */
1152 /* che_snr = che_snr - 16384;*/
1153 /* snr = che_snr / 32;*/
1154 /* snr = 10*log10(snr)-6; */
1155 fec_lock = (dtmb_read_reg(DTMB_TOP_FEC_LOCK_SNR) >> 14) & 0x1;
1156 fec_bch_add = dtmb_read_reg(DTMB_TOP_FEC_BCH_ACC);
1157 fec_ldpc_unc_acc = dtmb_read_reg(DTMB_TOP_FEC_LDPC_UNC_ACC);
1158 fec_ldpc_it_avg = dtmb_read_reg(DTMB_TOP_FEC_LDPC_IT_AVG);
1159 pr_dbg("¡¾FSM ¡¿: %x %x %x %x\n",
1160 dtmb_read_reg(DTMB_TOP_CTRL_FSM_STATE0),
1161 dtmb_read_reg(DTMB_TOP_CTRL_FSM_STATE1),
1162 dtmb_read_reg(DTMB_TOP_CTRL_FSM_STATE2),
1163 dtmb_read_reg(DTMB_TOP_CTRL_FSM_STATE3));
1164 pr_dbg
1165 ("¡¾AGC ¡¿: agc_power %d,agc_if_gain %d,agc_rf_gain %d,",
1166 (-(((dtmb_read_reg(DTMB_TOP_FRONT_AGC) >> 22) & 0x3ff) / 16)),
1167 ((dtmb_read_reg(DTMB_TOP_FRONT_AGC)) & 0x3ff),
1168 ((dtmb_read_reg(DTMB_TOP_FRONT_AGC) >> 11) & 0x7ff));
1169 pr_dbg
1170 ("dagc_power %3d,dagc_gain %3d mobi_det_power %d\n",
1171 ((dtmb_read_reg(DTMB_TOP_FRONT_DAGC) >> 0) & 0xff),
1172 ((dtmb_read_reg(DTMB_TOP_FRONT_DAGC) >> 8) & 0xfff),
1173 (dtmb_read_reg(DTMB_TOP_CTRL_SYS_OFDM_CNT) >> 8) & 0x7ffff);
1174 pr_dbg
1175 ("¡¾TPS ¡¿ SC or MC %2d,f_r %2d qam_nr %2d ",
1176 (dtmb_read_reg(DTMB_TOP_CHE_OBS_STATE1) >> 1) & 0x1,
1177 (tps >> 22) & 0x1, (tps >> 21) & 0x1);
1178 pr_dbg
1179 ("intlv %2d,cr %2d constl %2d\n",
1180 (tps >> 20) & 0x1,
1181 (tps >> 18) & 0x3, (tps >> 16) & 0x3);
1182
1183 pr_dbg
1184 ("[dtmb] snr is %d,fec_lock is %d,fec_bch_add is %d,",
1185 snr, fec_lock, fec_bch_add);
1186 pr_dbg
1187 ("fec_ldpc_unc_acc is %d ,fec_ldpc_it_avg is %d\n",
1188 fec_ldpc_unc_acc,
1189 fec_ldpc_it_avg / 256);
1190 pr_dbg
1191 ("------------------------------------------------------------\n");
1192
1193 tuner_get_ch_power(dev);
1194
1195 return 0;
1196}
1197
1198int dtmb_check_cci(void)
1199{
1200 int cci_det = 0;
1201
1202 cci_det =
1203 ((dtmb_read_reg(DTMB_TOP_SYNC_CCI_NF2_POSITION) >> 22)
1204 & 0x3);
1205 if (cci_det > 0) {
1206 pr_dbg("find cci\n");
1207 dtmb_write_reg(DTMB_CHE_CCIDET_CONFIG, 0x20210290);
1208 dtmb_write_reg(DTMB_CHE_M_CCI_THR_CONFIG3, 0x20081f6);
1209 dtmb_write_reg(DTMB_CHE_M_CCI_THR_CONFIG2, 0x3f08020);
1210 }
1211 return cci_det;
1212}
1213
1214int dtmb_bch_check(void)
1215{
1216 int fec_bch_add, i;
1217
1218 fec_bch_add = dtmb_read_reg(DTMB_TOP_FEC_BCH_ACC);
1219 pr_dbg("[debug]fec lock,fec_bch_add is %d\n", fec_bch_add);
1220 msleep(100);
1221 if (((dtmb_read_reg(DTMB_TOP_FEC_BCH_ACC))-fec_bch_add) >= 50) {
1222 pr_dbg("[debug]fec lock,but bch add ,need reset,wait not to reset\n");
1223 dtmb_reset();
1224 for (i = 0; i < 30; i++) {
1225 msleep(100);
1226 if (check_dtmb_fec_lock() == 1) {
1227 pr_dbg("[debug]fec lock,but bch add ,need reset,now is lock\n");
1228 return 0;
1229 }
1230 }
1231 }
1232 return 0;
1233}
1234
1235int dtmb_constell_check(void)
1236{
1237 int constell;
1238
1239 constell = dtmb_read_reg(DTMB_TOP_CTRL_CHE_WORKCNT)>>16 & 0x3;
1240 if (constell == 0)/*4qam*/
1241 dtmb_write_reg(DTMB_FRONT_47_CONFIG, 0x133221);
1242 else if (constell == 1)/*16qam*/
1243 dtmb_write_reg(DTMB_FRONT_47_CONFIG, 0x132821);
1244 else if (constell == 2)/*32qam*/
1245 dtmb_write_reg(DTMB_FRONT_47_CONFIG, 0x131e21);
1246 else if (constell == 3)/*64qam*/
1247 dtmb_write_reg(DTMB_FRONT_47_CONFIG, 0x131a31);
1248
1249 return 0;
1250}
1251
1252
1253int dtmb_check_fsm(void)
1254{
1255 int tmp, fsm_status, i, has_singnal;
1256
1257 tmp = dtmb_read_reg(DTMB_TOP_CTRL_FSM_STATE0);
1258 fsm_status = tmp&0xffffffff;
1259 has_singnal = 0;
1260 pr_dbg("[rsj1] fsm_status is %x\n", fsm_status);
1261 for (i = 0 ; i < 8 ; i++) {
1262 if (((fsm_status >> (i*4)) & 0xf) > 3) {
1263 /*has signal*/
1264 /* pr_dbg("has signal\n");*/
1265 has_singnal = 1;
1266 }
1267 }
1268 return has_singnal;
1269
1270}
1271
1272int patch_ts3(int delay1_us, int delay2_us)
1273{
1274 if (((dtmb_read_reg(DTMB_TOP_CTRL_FSM_STATE0)&0xf) == 0x7)&1) {
1275 dtmb_write_reg(DTMB_TOP_CTRL_FSM, 0x300f);
1276 dtmb_write_reg(DTMB_TOP_CTRL_FSM, 0x310f);
1277 msleep(delay1_us);
1278 dtmb_write_reg(DTMB_TOP_CTRL_ENABLE, 0xffdfff);
1279 dtmb_write_reg(DTMB_TOP_CTRL_ENABLE, 0xffffff);
1280 dtmb_write_reg(DTMB_TOP_CTRL_FSM, 0x3110);
1281 dtmb_write_reg(DTMB_TOP_CTRL_FSM, 0x3010);
1282 dtmb_write_reg(DTMB_TOP_CTRL_FSM, 0x3000);
1283 return 1;
1284 } else
1285 return 0;
1286}
1287
1288
1289int read_cfo_all(void)
1290{
1291 int icfo_all, fcfo_all;
1292
1293 icfo_all = dtmb_read_reg(DTMB_TOP_CTRL_ICFO_ALL) & 0xfffff;
1294 fcfo_all = dtmb_read_reg(DTMB_TOP_CTRL_FCFO_ALL) & 0x3fff;
1295 if (icfo_all > (1 << 19))
1296 icfo_all = icfo_all - (1 << 20);
1297 if (fcfo_all > (1 << 13))
1298 fcfo_all = fcfo_all - (1 << 14);
1299
1300 return (int)(icfo_all*4+fcfo_all);
1301
1302}
1303
1304
1305int dtmb_v3_soft_sync(int cfo_init)
1306{
1307
1308/* int cfo_all;*/
1309/* int cfo_setting;*/
1310
1311 if (cfo_init == 0) {
1312 cfo_init = patch_ts3(11, 0);
1313 #if 0
1314 if (cfo_init == 1) {
1315 cfo_all = read_cfo_all();
1316 cfo_setting = dtmb_read_reg(DTMB_FRONT_DDC_BYPASS);
1317 dtmb_write_reg(DTMB_FRONT_DDC_BYPASS,
1318 cfo_setting+cfo_all);
1319 dtmb_write_reg(DTMB_TOP_CTRL_LOOP, 0x3);
1320 dtmb_reset();
1321 }
1322 #endif
1323 }
1324 return cfo_init;
1325
1326}
1327
1328int dtmb_check_status_gxtv(struct dvb_frontend *fe)
1329{
1330 int local_state;
1331 int time_cnt;/* cci_det, src_config;*/
1332 int cfo_init, count;
1333
1334 dtmb_information();
1335 time_cnt = 0;
1336 local_state = 0;
1337 cfo_init = 0;
1338 if (check_dtmb_fec_lock() != 1) {
1339 dtmb_register_reset();
1340 dtmb_all_reset();
1341 count = 15;
1342 while ((count) &&
1343 ((dtmb_read_reg(DTMB_TOP_CTRL_FSM_STATE0)&0xf) < 0x6)) {
1344 msleep(20);
1345 count--;
1346 }
1347
1348 count = demod_sync_count;
1349 while ((count) && (cfo_init == 0)) {
1350
1351 cfo_init = dtmb_v3_soft_sync(cfo_init);
1352
1353 msleep(demod_sync_delay_time);
1354 count--;
1355 }
1356 if ((cfo_init == 0) &&
1357 ((dtmb_read_reg(DTMB_TOP_CTRL_FSM_STATE0)&0xf) <= 7)) {
1358 pr_dbg("over 400ms,status is %x, need reset\n",
1359 (dtmb_read_reg(DTMB_TOP_CTRL_FSM_STATE0)&0xf));
1360 return 0;
1361 }
1362 while ((time_cnt < 10) && (check_dtmb_fec_lock() != 1)) {
1363 msleep(demod_timeout);
1364 time_cnt++;
1365 local_state = AMLOGIC_DTMB_STEP3;
1366 dtmb_information();
1367 dtmb_check_cci();
1368 if (time_cnt > 8)
1369 pr_dbg
1370 ("* local_state = %d\n", local_state);
1371 }
1372 if (time_cnt >= 10 && (check_dtmb_fec_lock() != 1)) {
1373 local_state = AMLOGIC_DTMB_STEP4;
1374 time_cnt = 0;
1375 pr_dbg
1376 ("*all reset,timeout is %d\n", demod_timeout);
1377 }
1378 } else {
1379 dtmb_check_cci();
1380 dtmb_bch_check();
1381 #if 0
1382 cci_det = dtmb_check_cci();
1383 if ((check_dtmb_mobile_det() <= demod_mobile_power)
1384 && (cci_det == 0)) {
1385 /* open */
1386 src_config = (dtmb_read_reg(DTMB_FRONT_SRC_CONFIG1));
1387 dtmb_write_reg(DTMB_FRONT_SRC_CONFIG1,
1388 src_config & (~(0x1 << 28)));
1389 } else {
1390 /* close */
1391 src_config = (dtmb_read_reg(DTMB_FRONT_SRC_CONFIG1));
1392 dtmb_write_reg(DTMB_FRONT_SRC_CONFIG1,
1393 src_config | (0x1 << 28));
1394 }
1395 #endif
1396 }
1397 if (check_dtmb_fec_lock() == 1)
1398 dtmb_write_reg(DTMB_TOP_CTRL_LOOP, 0xf);
1399 return 0;
1400}
1401
1402
1403int dtmb_check_status_txl(struct dvb_frontend *fe)
1404{
1405 int time_cnt;
1406
1407 time_cnt = 0;
1408 dtmb_information();
1409 if (check_dtmb_fec_lock() != 1) {
1410 while ((time_cnt < 10) && (check_dtmb_fec_lock() != 1)) {
1411 msleep(demod_timeout);
1412 time_cnt++;
1413 dtmb_information();
1414 if (((dtmb_read_reg(DTMB_TOP_CTRL_CHE_WORKCNT)
1415 >> 21) & 0x1) == 0x1) {
1416 pr_dbg("4qam-nr,need set spectrum\n");
1417 if (dtmb_spectrum == 1) {
1418 dtmb_write_reg
1419 (DTMB_TOP_CTRL_TPS, 0x1010406);
1420 } else if (dtmb_spectrum == 0) {
1421 dtmb_write_reg
1422 (DTMB_TOP_CTRL_TPS, 0x1010402);
1423 } else {
1424 dtmb_write_reg
1425 (DTMB_TOP_CTRL_TPS, 0x1010002);
1426 }
1427 }
1428 if (time_cnt > 8)
1429 pr_dbg
1430 ("* time_cnt = %d\n", time_cnt);
1431 }
1432 if (time_cnt >= 10 && (check_dtmb_fec_lock() != 1)) {
1433 time_cnt = 0;
1434 dtmb_register_reset();
1435 dtmb_all_reset();
1436 if (dtmb_spectrum == 0)
1437 dtmb_spectrum = 1;
1438 else
1439 dtmb_spectrum = 0;
1440 pr_dbg
1441 ("*all reset,timeout is %d\n", demod_timeout);
1442 }
1443 } else {
1444 dtmb_bch_check();
1445 dtmb_constell_check();
1446 }
1447 return 0;
1448}
1449
1450
1451void dtmb_reset(void)
1452{
1453 union DTMB_TOP_CTRL_SW_RST_BITS sw_rst;
1454
1455 sw_rst.b.ctrl_sw_rst = 1;
1456 sw_rst.b.ctrl_sw_rst_noreg = 1;
1457 dtmb_write_reg(DTMB_TOP_CTRL_SW_RST, sw_rst.d32);
1458 sw_rst.b.ctrl_sw_rst = 0;
1459 sw_rst.b.ctrl_sw_rst_noreg = 0;
1460 dtmb_write_reg(DTMB_TOP_CTRL_SW_RST, sw_rst.d32);
1461}
1462
1463void dtmb_register_reset(void)
1464{
1465 union DTMB_TOP_CTRL_SW_RST_BITS sw_rst;
1466
1467 sw_rst.b.ctrl_sw_rst = 1;
1468 dtmb_write_reg(DTMB_TOP_CTRL_SW_RST, sw_rst.d32);
1469 sw_rst.b.ctrl_sw_rst = 0;
1470 dtmb_write_reg(DTMB_TOP_CTRL_SW_RST, sw_rst.d32);
1471}
1472
1473int dtmb_set_ch(struct aml_demod_sta *demod_sta,
1474 struct aml_demod_i2c *demod_i2c,
1475 struct aml_demod_dtmb *demod_dtmb)
1476{
1477 int ret = 0;
1478 u8 demod_mode;
1479 u8 bw, sr, ifreq, agc_mode;
1480 u32 ch_freq;
1481
1482 bw = demod_dtmb->bw;
1483 sr = demod_dtmb->sr;
1484 ifreq = demod_dtmb->ifreq;
1485 agc_mode = demod_dtmb->agc_mode;
1486 ch_freq = demod_dtmb->ch_freq;
1487 demod_mode = demod_dtmb->dat0;
1488 demod_sta->ch_mode = demod_dtmb->mode; /* TODO */
1489 demod_sta->agc_mode = agc_mode;
1490 demod_sta->ch_freq = ch_freq;
1491 demod_sta->dvb_mode = demod_mode;
1492 demod_sta->ch_bw = (8 - bw) * 1000;
1493 dtmb_initial(demod_sta);
1494 pr_dbg("DTMB mode\n");
1495 return ret;
1496}
1497
1498int dvbt_set_ch(struct aml_demod_sta *demod_sta,
1499 struct aml_demod_i2c *demod_i2c,
1500 struct aml_demod_dvbt *demod_dvbt)
1501{
1502 int ret = 0;
1503 u8_t demod_mode = 1;
1504 u8_t bw, sr, ifreq, agc_mode;
1505 u32_t ch_freq;
1506
1507 bw = demod_dvbt->bw;
1508 sr = demod_dvbt->sr;
1509 ifreq = demod_dvbt->ifreq;
1510 agc_mode = demod_dvbt->agc_mode;
1511 ch_freq = demod_dvbt->ch_freq;
1512 demod_mode = demod_dvbt->dat0;
1513 if (ch_freq < 1000 || ch_freq > 900000000) {
1514 /* pr_dbg("Error: Invalid Channel Freq option %d\n",
1515 *ch_freq);
1516 */
1517 ch_freq = 474000;
1518 ret = -1;
1519 }
1520
1521 if (demod_mode < 0 || demod_mode > 4) {
1522 /* pr_dbg("Error: Invalid demod mode option %d\n",
1523 *demod_mode);
1524 */
1525 demod_mode = 1;
1526 ret = -1;
1527 }
1528
1529 /* demod_sta->dvb_mode = 1; */
1530 demod_sta->ch_mode = 0; /* TODO */
1531 demod_sta->agc_mode = agc_mode;
1532 demod_sta->ch_freq = ch_freq;
1533 demod_sta->dvb_mode = demod_mode;
1534 /* if (demod_i2c->tuner == 1)
1535 * demod_sta->ch_if = 36130;
1536 * else if (demod_i2c->tuner == 2)
1537 * demod_sta->ch_if = 4570;
1538 * else if (demod_i2c->tuner == 3)
1539 * demod_sta->ch_if = 4000;// It is nouse.(alan)
1540 * else if (demod_i2c->tuner == 7)
1541 * demod_sta->ch_if = 5000;//silab 5000kHz IF
1542 */
1543
1544 demod_sta->ch_bw = (8 - bw) * 1000;
1545 demod_sta->symb_rate = 0; /* TODO */
1546
1547/* bw=0; */
1548 demod_mode = 1;
1549 /* for si2176 IF:5M sr 28.57 */
1550 sr = 4;
1551 ifreq = 4;
1552 if (bw == BANDWIDTH_AUTO)
1553 demod_mode = 2;
1554 ofdm_initial(bw,
1555 /* 00:8M 01:7M 10:6M 11:5M */
1556 sr,
1557 /* 00:45M 01:20.8333M 10:20.7M 11:28.57 100:24m */
1558 ifreq,
1559 /* 000:36.13M 001:-5.5M 010:4.57M 011:4M 100:5M */
1560 demod_mode - 1,
1561 /* 00:DVBT,01:ISDBT */
1562 1
1563 /* 0: Unsigned, 1:TC */
1564 );
1565 pr_dbg("DVBT/ISDBT mode\n");
1566
1567 return ret;
1568}
1569
1570int demod_set_sys(struct aml_demod_sta *demod_sta,
1571 struct aml_demod_i2c *demod_i2c,
1572 struct aml_demod_sys *demod_sys)
1573{
1574/* int adc_clk; */
1575/* demod_sta->tmp=Adc_mode; */
1576 unsigned char dvb_mode;
1577 int clk_adc, clk_dem;
1578 int gpioDV_2;
1579 int gpiW_2;
1580
1581 dvb_mode = demod_sta->dvb_mode;
1582 clk_adc = demod_sys->adc_clk;
1583 clk_dem = demod_sys->demod_clk;
1584 pr_dbg
1585 ("demod_set_sys,clk_adc is %d,clk_demod is %d\n",
1586 clk_adc, clk_dem);
1587 mutex_init(&mp);
1588 clocks_set_sys_defaults(dvb_mode);
1589 /* open dtv adc pinmux */
1590 if (is_meson_txl_cpu()) {
1591 gpioDV_2 = demod_read_demod_reg(0xc8834400 + (0x2e << 2));
1592 pr_dbg("[R840]set adc pinmux,gpioDV_2 %x\n", gpioDV_2);
1593 gpioDV_2 = gpioDV_2 | (0x1 << 22);
1594 gpioDV_2 = gpioDV_2 & ~(0x3 << 19);
1595 gpioDV_2 = gpioDV_2 & ~(0x1 << 23);
1596 gpioDV_2 = gpioDV_2 & ~(0x1 << 31);
1597 demod_set_demod_reg(gpioDV_2, 0xc8834400 + (0x2e << 2));
1598 pr_dbg("[R840]set adc pinmux,gpioDV_2 %x\n", gpioDV_2);
1599 } else {
1600 gpiW_2 = demod_read_demod_reg(0xc88344c4);
1601 gpiW_2 = gpiW_2 | (0x1 << 25);
1602 gpiW_2 = gpiW_2 & ~(0xd << 24);
1603 demod_set_demod_reg(gpiW_2, 0xc88344c4);
1604 pr_dbg("[R840]set adc pinmux,gpiW_2 %x\n", gpiW_2);
1605 }
1606 /* set adc clk */
1607 demod_set_adc_core_clk(clk_adc, clk_dem, dvb_mode);
1608 /* init for dtmb */
1609 if (dvb_mode == Gxtv_Dtmb) {
1610 /* open arbit */
1611 /* demod_set_demod_reg(0x8, DEMOD_REG4);*/
1612 }
1613 demod_sta->adc_freq = clk_adc;
1614 demod_sta->clk_freq = clk_dem;
1615 return 0;
1616}
1617
1618void demod_set_reg(struct aml_demod_reg *demod_reg)
1619{
1620 switch (demod_reg->mode) {
1621 case 0:
1622 demod_reg->addr = demod_reg->addr + QAM_BASE;
1623 break;
1624 case 1:
1625 case 2:
1626 demod_reg->addr = DTMB_TOP_ADDR(demod_reg->addr);
1627 break;
1628 case 3:
1629 /* demod_reg->addr=ATSC_BASE; */
1630 break;
1631 case 4:
1632 demod_reg->addr = demod_reg->addr * 4 + DEMOD_CFG_BASE;
1633 break;
1634 case 5:
1635 demod_reg->addr = demod_reg->addr + DEMOD_BASE;
1636 break;
1637 case 6:
1638 /* demod_reg->addr=demod_reg->addr*4+DEMOD_CFG_BASE; */
1639 break;
1640 case 11:
1641 demod_reg->addr = demod_reg->addr;
1642 break;
1643 case 10:
1644 /* demod_reg->addr=(u32_t)phys_to_virt(demod_reg->addr); */
1645 break;
1646 }
1647
1648 if (demod_reg->mode == 3)
1649 atsc_write_reg(demod_reg->addr, demod_reg->val);
1650 else if (demod_reg->mode == 11)
1651 demod_set_cbus_reg(demod_reg->val, demod_reg->addr);
1652 else if (demod_reg->mode == 10)
1653 apb_write_reg_collect(demod_reg->addr, demod_reg->val);
1654 /* demod_reg->val_high = apb_read_reg_high(demod_reg->addr); */
1655 else
1656 demod_set_demod_reg(demod_reg->val, demod_reg->addr);
1657}
1658
1659void demod_get_reg(struct aml_demod_reg *demod_reg)
1660{
1661 if (demod_reg->mode == 0) {
1662 demod_reg->addr = demod_reg->addr + QAM_BASE;
1663 } else if ((demod_reg->mode == 1) || (demod_reg->mode == 2)) {
1664 demod_reg->addr = DTMB_TOP_ADDR(demod_reg->addr);
1665 } else if (demod_reg->mode == 3) {
1666 /* demod_reg->addr=demod_reg->addr+ATSC_BASE; */
1667 } else if (demod_reg->mode == 4) {
1668 demod_reg->addr = demod_reg->addr * 4 + DEMOD_CFG_BASE;
1669 } else if (demod_reg->mode == 5) {
1670 demod_reg->addr = demod_reg->addr + DEMOD_BASE;
1671 } else if (demod_reg->mode == 6) {
1672 /* demod_reg->addr=demod_reg->addr*4+DEMOD_CFG_BASE; */
1673 } else if (demod_reg->mode == 11) {
1674 demod_reg->addr = demod_reg->addr;
1675 } else if (demod_reg->mode == 10) {
1676 /* printk("demod_reg->addr is %x\n",demod_reg->addr); */
1677 /* test=(unsigned long)phys_to_virt(test); */
1678/* demod_reg->addr=(unsigned long)phys_to_virt(demod_reg->addr); */
1679/* printk("demod_reg->addr is %lx %x\n",test,demod_reg->addr); */
1680 }
1681
1682 if (demod_reg->mode == 3) {
1683 demod_reg->val = atsc_read_reg(demod_reg->addr);
1684 /* apb_write_reg(ATSC_BASE+4, (demod_reg->addr&0xffff)<<8); */
1685 /* demod_reg->val = apb_read_reg(ATSC_BASE)&0xff; */
1686 } else if (demod_reg->mode == 6) {
1687 demod_reg->val = atsc_read_iqr_reg();
1688 /* apb_write_reg(ATSC_BASE+4, (demod_reg->addr&0xffff)<<8); */
1689 /* demod_reg->val = apb_read_reg(ATSC_BASE)&0xff; */
1690 } else if (demod_reg->mode == 11) {
1691 demod_reg->val = demod_read_cbus_reg(demod_reg->addr);
1692 } else if (demod_reg->mode == 10) {
1693 demod_reg->val = apb_read_reg_collect(demod_reg->addr);
1694 /* demod_reg->val_high = apb_read_reg_high(demod_reg->addr);*/
1695 } else {
1696 demod_reg->val = demod_read_demod_reg(demod_reg->addr);
1697 }
1698}
1699
1700void apb_write_reg_collect(unsigned int addr, unsigned int data)
1701{
1702 writel(data, ((void __iomem *)(phys_to_virt(addr))));
1703/* *(volatile unsigned int*)addr = data; */
1704}
1705
1706unsigned long apb_read_reg_collect(unsigned long addr)
1707{
1708 unsigned long tmp;
1709/* void __iomem *vaddr;
1710 * vaddr = ioremap(((unsigned long)phys_to_virt(addr)), 0x4);
1711 * tmp = readl(vaddr);
1712 * iounmap(vaddr);
1713 */
1714 tmp = readl((void __iomem *)(phys_to_virt(addr)));
1715/*tmp = *(volatile unsigned long *)((unsigned long)phys_to_virt(addr));*/
1716/* printk("[all][read]%lx,data is %lx\n",addr,tmp); */
1717 return tmp & 0xffffffff;
1718}
1719
1720
1721
1722void apb_write_reg(unsigned int addr, unsigned int data)
1723{
1724 demod_set_demod_reg(data, addr);
1725}
1726
1727unsigned long apb_read_reg_high(unsigned long addr)
1728{
1729 unsigned long tmp;
1730
1731 tmp = 0;
1732 return (tmp >> 32) & 0xffffffff;
1733}
1734
1735unsigned long apb_read_reg(unsigned long addr)
1736{
1737 return demod_read_demod_reg(addr);
1738}
1739
1740void apb_write_regb(unsigned long addr, int index, unsigned long data)
1741{
1742 /*to achieve write func*/
1743}
1744
1745void enable_qam_int(int idx)
1746{
1747 unsigned long mask;
1748
1749 mask = apb_read_reg(QAM_BASE + 0xd0);
1750 mask |= (1 << idx);
1751 apb_write_reg(QAM_BASE + 0xd0, mask);
1752}
1753
1754void disable_qam_int(int idx)
1755{
1756 unsigned long mask;
1757
1758 mask = apb_read_reg(QAM_BASE + 0xd0);
1759 mask &= ~(1 << idx);
1760 apb_write_reg(QAM_BASE + 0xd0, mask);
1761}
1762
1763char *qam_int_name[] = { " ADC",
1764 " Symbol",
1765 " RS",
1766 " In_Sync0",
1767 " In_Sync1",
1768 " In_Sync2",
1769 " In_Sync3",
1770 " In_Sync4",
1771 "Out_Sync0",
1772 "Out_Sync1",
1773 "Out_Sync2",
1774 "Out_Sync3",
1775 "Out_Sync4",
1776 "In_SyncCo",
1777 "OutSyncCo",
1778 " In_Dagc",
1779 " Out_Dagc",
1780 " Eq_Mode",
1781 "RS_Uncorr"
1782};
1783
1784#define OFDM_INT_STS 0
1785#define OFDM_INT_EN 0
1786
1787void enable_ofdm_int(int ofdm_irq)
1788{
1789
1790}
1791
1792void disable_ofdm_int(int ofdm_irq)
1793{
1794
1795}
1796
1797char *ofdm_int_name[] = { "PFS_FCFO",
1798 "PFS_ICFO",
1799 " CS_FCFO",
1800 " PFS_SFO",
1801 " PFS_TPS",
1802 " SP",
1803 " CCI",
1804 " Symbol",
1805 " In_Sync",
1806 "Out_Sync",
1807 "FSM Stat"
1808};
1809
1810unsigned long read_ofdm_int(void)
1811{
1812
1813 return 0;
1814}
1815
1816#define PHS_LOOP_OPEN
1817
1818void qam_read_all_regs(void)
1819{
1820
1821}
1822
1823void ini_icfo_pn_index(int mode)
1824{ /* 00:DVBT,01:ISDBT */
1825 if (mode == 0) {
1826 apb_write_reg(DVBT_BASE + 0x3f8, 0x00000031);
1827 apb_write_reg(DVBT_BASE + 0x3fc, 0x00030000);
1828 apb_write_reg(DVBT_BASE + 0x3f8, 0x00000032);
1829 apb_write_reg(DVBT_BASE + 0x3fc, 0x00057036);
1830 apb_write_reg(DVBT_BASE + 0x3f8, 0x00000033);
1831 apb_write_reg(DVBT_BASE + 0x3fc, 0x0009c08d);
1832 apb_write_reg(DVBT_BASE + 0x3f8, 0x00000034);
1833 apb_write_reg(DVBT_BASE + 0x3fc, 0x000c90c0);
1834 apb_write_reg(DVBT_BASE + 0x3f8, 0x00000035);
1835 apb_write_reg(DVBT_BASE + 0x3fc, 0x001170ff);
1836 apb_write_reg(DVBT_BASE + 0x3f8, 0x00000036);
1837 apb_write_reg(DVBT_BASE + 0x3fc, 0x0014d11a);
1838 } else if (mode == 1) {
1839 apb_write_reg(DVBT_BASE + 0x3f8, 0x00000031);
1840 apb_write_reg(DVBT_BASE + 0x3fc, 0x00085046);
1841 apb_write_reg(DVBT_BASE + 0x3f8, 0x00000032);
1842 apb_write_reg(DVBT_BASE + 0x3fc, 0x0019a0e9);
1843 apb_write_reg(DVBT_BASE + 0x3f8, 0x00000033);
1844 apb_write_reg(DVBT_BASE + 0x3fc, 0x0024b1dc);
1845 apb_write_reg(DVBT_BASE + 0x3f8, 0x00000034);
1846 apb_write_reg(DVBT_BASE + 0x3fc, 0x003b3313);
1847 apb_write_reg(DVBT_BASE + 0x3f8, 0x00000035);
1848 apb_write_reg(DVBT_BASE + 0x3fc, 0x0048d409);
1849 apb_write_reg(DVBT_BASE + 0x3f8, 0x00000036);
1850 apb_write_reg(DVBT_BASE + 0x3fc, 0x00527509);
1851 }
1852}
1853
1854static int coef[] = {
1855 0xf900, 0xfe00, 0x0000, 0x0000, 0x0100, 0x0100, 0x0000, 0x0000,
1856 0xfd00, 0xf700, 0x0000, 0x0000, 0x4c00, 0x0000, 0x0000, 0x0000,
1857 0x2200, 0x0c00, 0x0000, 0x0000, 0xf700, 0xf700, 0x0000, 0x0000,
1858 0x0300, 0x0900, 0x0000, 0x0000, 0x0600, 0x0600, 0x0000, 0x0000,
1859 0xfc00, 0xf300, 0x0000, 0x0000, 0x2e00, 0x0000, 0x0000, 0x0000,
1860 0x3900, 0x1300, 0x0000, 0x0000, 0xfa00, 0xfa00, 0x0000, 0x0000,
1861 0x0100, 0x0200, 0x0000, 0x0000, 0xf600, 0x0000, 0x0000, 0x0000,
1862 0x0700, 0x0700, 0x0000, 0x0000, 0xfe00, 0xfb00, 0x0000, 0x0000,
1863 0x0900, 0x0000, 0x0000, 0x0000, 0x3200, 0x1100, 0x0000, 0x0000,
1864 0x0400, 0x0400, 0x0000, 0x0000, 0xfe00, 0xfb00, 0x0000, 0x0000,
1865 0x0e00, 0x0000, 0x0000, 0x0000, 0xfb00, 0xfb00, 0x0000, 0x0000,
1866 0x0100, 0x0200, 0x0000, 0x0000, 0xf400, 0x0000, 0x0000, 0x0000,
1867 0x3900, 0x1300, 0x0000, 0x0000, 0x1700, 0x1700, 0x0000, 0x0000,
1868 0xfc00, 0xf300, 0x0000, 0x0000, 0x0c00, 0x0000, 0x0000, 0x0000,
1869 0x0300, 0x0900, 0x0000, 0x0000, 0xee00, 0x0000, 0x0000, 0x0000,
1870 0x2200, 0x0c00, 0x0000, 0x0000, 0x2600, 0x2600, 0x0000, 0x0000,
1871 0xfd00, 0xf700, 0x0000, 0x0000, 0x0200, 0x0000, 0x0000, 0x0000,
1872 0xf900, 0xfe00, 0x0000, 0x0000, 0x0400, 0x0b00, 0x0000, 0x0000,
1873 0xf900, 0x0000, 0x0000, 0x0000, 0x0700, 0x0200, 0x0000, 0x0000,
1874 0x2100, 0x2100, 0x0000, 0x0000, 0x0200, 0x0700, 0x0000, 0x0000,
1875 0xf900, 0x0000, 0x0000, 0x0000, 0x0b00, 0x0400, 0x0000, 0x0000,
1876 0xfe00, 0xf900, 0x0000, 0x0000, 0x0200, 0x0000, 0x0000, 0x0000,
1877 0xf700, 0xfd00, 0x0000, 0x0000, 0x2600, 0x2600, 0x0000, 0x0000,
1878 0x0c00, 0x2200, 0x0000, 0x0000, 0xee00, 0x0000, 0x0000, 0x0000,
1879 0x0900, 0x0300, 0x0000, 0x0000, 0x0c00, 0x0000, 0x0000, 0x0000,
1880 0xf300, 0xfc00, 0x0000, 0x0000, 0x1700, 0x1700, 0x0000, 0x0000,
1881 0x1300, 0x3900, 0x0000, 0x0000, 0xf400, 0x0000, 0x0000, 0x0000,
1882 0x0200, 0x0100, 0x0000, 0x0000, 0xfb00, 0xfb00, 0x0000, 0x0000,
1883 0x0e00, 0x0000, 0x0000, 0x0000, 0xfb00, 0xfe00, 0x0000, 0x0000,
1884 0x0400, 0x0400, 0x0000, 0x0000, 0x1100, 0x3200, 0x0000, 0x0000,
1885 0x0900, 0x0000, 0x0000, 0x0000, 0xfb00, 0xfe00, 0x0000, 0x0000,
1886 0x0700, 0x0700, 0x0000, 0x0000, 0xf600, 0x0000, 0x0000, 0x0000,
1887 0x0200, 0x0100, 0x0000, 0x0000, 0xfa00, 0xfa00, 0x0000, 0x0000,
1888 0x1300, 0x3900, 0x0000, 0x0000, 0x2e00, 0x0000, 0x0000, 0x0000,
1889 0xf300, 0xfc00, 0x0000, 0x0000, 0x0600, 0x0600, 0x0000, 0x0000,
1890 0x0900, 0x0300, 0x0000, 0x0000, 0xf700, 0xf700, 0x0000, 0x0000,
1891 0x0c00, 0x2200, 0x0000, 0x0000, 0x4c00, 0x0000, 0x0000, 0x0000,
1892 0xf700, 0xfd00, 0x0000, 0x0000, 0x0100, 0x0100, 0x0000, 0x0000,
1893 0xfe00, 0xf900, 0x0000, 0x0000, 0x0b00, 0x0400, 0x0000, 0x0000,
1894 0xfc00, 0xfc00, 0x0000, 0x0000, 0x0200, 0x0700, 0x0000, 0x0000,
1895 0x4200, 0x0000, 0x0000, 0x0000, 0x0700, 0x0200, 0x0000, 0x0000,
1896 0xfc00, 0xfc00, 0x0000, 0x0000, 0x0400, 0x0b00, 0x0000, 0x0000
1897};
1898
1899void tfd_filter_coff_ini(void)
1900{
1901 int i = 0;
1902
1903 for (i = 0; i < 336; i++) {
1904 apb_write_reg(DVBT_BASE + 0x99 * 4, (i << 16) | coef[i]);
1905 apb_write_reg(DVBT_BASE + 0x03 * 4, (1 << 12));
1906 }
1907}
1908
1909void ofdm_initial(int bandwidth,
1910 /* 00:8M 01:7M 10:6M 11:5M */
1911 int samplerate,
1912 /* 00:45M 01:20.8333M 10:20.7M 11:28.57 100: 24.00 */
1913 int IF,
1914 /* 000:36.13M 001:-5.5M 010:4.57M 011:4M 100:5M */
1915 int mode,
1916 /* 00:DVBT,01:ISDBT */
1917 int tc_mode
1918 /* 0: Unsigned, 1:TC */
1919 )
1920{
1921#if 0
1922 int tmp;
1923 int ch_if;
1924 int adc_freq;
1925
1926 pr_dbg
1927 ("[ofdm_initial]bandwidth is %d,samplerate is %d",
1928 bandwidth, samplerate);
1929 pr_dbg
1930 ("IF is %d, mode is %d,tc_mode is %d\n",
1931 IF, mode, tc_mode);
1932 switch (IF) {
1933 case 0:
1934 ch_if = 36130;
1935 break;
1936 case 1:
1937 ch_if = -5500;
1938 break;
1939 case 2:
1940 ch_if = 4570;
1941 break;
1942 case 3:
1943 ch_if = 4000;
1944 break;
1945 case 4:
1946 ch_if = 5000;
1947 break;
1948 default:
1949 ch_if = 4000;
1950 break;
1951 }
1952 switch (samplerate) {
1953 case 0:
1954 adc_freq = 45000;
1955 break;
1956 case 1:
1957 adc_freq = 20833;
1958 break;
1959 case 2:
1960 adc_freq = 20700;
1961 break;
1962 case 3:
1963 adc_freq = 28571;
1964 break;
1965 case 4:
1966 adc_freq = 24000;
1967 break;
1968 default:
1969 adc_freq = 28571;
1970 break;
1971 }
1972
1973 apb_write_reg(DVBT_BASE + (0x02 << 2), 0x00800000);
1974 /* SW reset bit[23] ; write anything to zero */
1975 apb_write_reg(DVBT_BASE + (0x00 << 2), 0x00000000);
1976
1977 apb_write_reg(DVBT_BASE + (0xe << 2), 0xffff);
1978 /* enable interrupt */
1979
1980 if (mode == 0) { /* DVBT */
1981 switch (samplerate) {
1982 case 0:
1983 apb_write_reg(DVBT_BASE + (0x08 << 2), 0x00005a00);
1984 break; /* 45MHz */
1985 case 1:
1986 apb_write_reg(DVBT_BASE + (0x08 << 2), 0x000029aa);
1987 break; /* 20.833 */
1988 case 2:
1989 apb_write_reg(DVBT_BASE + (0x08 << 2), 0x00002966);
1990 break; /* 20.7 SAMPLERATE*512 */
1991 case 3:
1992 apb_write_reg(DVBT_BASE + (0x08 << 2), 0x00003924);
1993 break; /* 28.571 */
1994 case 4:
1995 apb_write_reg(DVBT_BASE + (0x08 << 2), 0x00003000);
1996 break; /* 24 */
1997 default:
1998 apb_write_reg(DVBT_BASE + (0x08 << 2), 0x00003924);
1999 break; /* 28.571 */
2000 }
2001 } else { /* ISDBT */
2002 switch (samplerate) {
2003 case 0:
2004 apb_write_reg(DVBT_BASE + (0x08 << 2), 0x0000580d);
2005 break; /* 45MHz */
2006 case 1:
2007 apb_write_reg(DVBT_BASE + (0x08 << 2), 0x0000290d);
2008 break; /* 20.833 = 56/7 * 20.8333 / (512/63)*512 */
2009 case 2:
2010 apb_write_reg(DVBT_BASE + (0x08 << 2), 0x000028da);
2011 break; /* 20.7 */
2012 case 3:
2013 apb_write_reg(DVBT_BASE + (0x08 << 2), 0x0000383F);
2014 break; /* 28.571 3863 */
2015 case 4:
2016 apb_write_reg(DVBT_BASE + (0x08 << 2), 0x00002F40);
2017 break; /* 24 */
2018 default:
2019 apb_write_reg(DVBT_BASE + (0x08 << 2), 0x00003863);
2020 break; /* 28.571 */
2021 }
2022 }
2023/* memstart=0x93900000; */
2024 pr_dbg("memstart is %x\n", memstart);
2025 apb_write_reg(DVBT_BASE + (0x10 << 2), memstart);
2026 /* 0x8f300000 */
2027
2028 apb_write_reg(DVBT_BASE + (0x14 << 2), 0xe81c4ff6);
2029 /* AGC_TARGET 0xf0121385 */
2030
2031 switch (samplerate) {
2032 case 0:
2033 apb_write_reg(DVBT_BASE + (0x15 << 2), 0x018c2df2);
2034 break;
2035 case 1:
2036 apb_write_reg(DVBT_BASE + (0x15 << 2), 0x0185bdf2);
2037 break;
2038 case 2:
2039 apb_write_reg(DVBT_BASE + (0x15 << 2), 0x0185bdf2);
2040 break;
2041 case 3:
2042 apb_write_reg(DVBT_BASE + (0x15 << 2), 0x0187bdf2);
2043 break;
2044 case 4:
2045 apb_write_reg(DVBT_BASE + (0x15 << 2), 0x0187bdf2);
2046 break;
2047 default:
2048 apb_write_reg(DVBT_BASE + (0x15 << 2), 0x0187bdf2);
2049 break;
2050 }
2051 if (tc_mode == 1)
2052 apb_write_regb(DVBT_BASE + (0x15 << 2), 11, 0);
2053 /* For TC mode. Notice, For ADC input is Unsigned,
2054 *For Capture Data, It is TC.
2055 */
2056 apb_write_regb(DVBT_BASE + (0x15 << 2), 26, 1);
2057 /* [19:0] = [I , Q], I is high, Q is low. This bit is swap I/Q. */
2058
2059 apb_write_reg(DVBT_BASE + (0x16 << 2), 0x00047f80);
2060 /* AGC_IFGAIN_CTRL */
2061 apb_write_reg(DVBT_BASE + (0x17 << 2), 0x00027f80);
2062 /* AGC_RFGAIN_CTRL */
2063 apb_write_reg(DVBT_BASE + (0x18 << 2), 0x00000190);
2064 /* AGC_IFGAIN_ACCUM */
2065 apb_write_reg(DVBT_BASE + (0x19 << 2), 0x00000190);
2066 /* AGC_RFGAIN_ACCUM */
2067 if (ch_if < 0)
2068 ch_if += adc_freq;
2069 if (ch_if > adc_freq)
2070 ch_if -= adc_freq;
2071
2072 tmp = ch_if * (1 << 15) / adc_freq;
2073 apb_write_reg(DVBT_BASE + (0x20 << 2), tmp);
2074
2075 apb_write_reg(DVBT_BASE + (0x21 << 2), 0x001ff000);
2076 /* DDC CS_FCFO_ADJ_CTRL */
2077 apb_write_reg(DVBT_BASE + (0x22 << 2), 0x00000000);
2078 /* DDC ICFO_ADJ_CTRL */
2079 apb_write_reg(DVBT_BASE + (0x23 << 2), 0x00004000);
2080 /* DDC TRACK_FCFO_ADJ_CTRL */
2081
2082 apb_write_reg(DVBT_BASE + (0x27 << 2), (1 << 23)
2083 | (3 << 19) | (3 << 15) | (1000 << 4) | 9);
2084 /* {8'd0,1'd1,4'd3,4'd3,11'd50,4'd9});//FSM_1 */
2085 apb_write_reg(DVBT_BASE + (0x28 << 2), (100 << 13) | 1000);
2086 /* {8'd0,11'd40,13'd50});//FSM_2 */
2087 apb_write_reg(DVBT_BASE + (0x29 << 2), (31 << 20) | (1 << 16) |
2088 (24 << 9) | (3 << 6) | 20);
2089 /* {5'd0,7'd127,1'd0,3'd0,7'd24,3'd5,6'd20}); */
2090
2091 if (mode == 0) { /* DVBT */
2092 if (bandwidth == 0) { /* 8M */
2093 switch (samplerate) {
2094 case 0:
2095 ini_acf_iireq_src_45m_8m();
2096 apb_write_reg(DVBT_BASE + (0x44 << 2),
2097 0x004ebf2e);
2098 break; /* 45M */
2099 case 1:
2100 ini_acf_iireq_src_207m_8m();
2101 apb_write_reg(DVBT_BASE + (0x44 << 2),
2102 0x00247551);
2103 break; /* 20.833M */
2104 case 2:
2105 ini_acf_iireq_src_207m_8m();
2106 apb_write_reg(DVBT_BASE + (0x44 << 2),
2107 0x00243999);
2108 break; /* 20.7M */
2109 case 3:
2110 ini_acf_iireq_src_2857m_8m();
2111 apb_write_reg(DVBT_BASE + (0x44 << 2),
2112 0x0031ffcd);
2113 break; /* 28.57M */
2114 case 4:
2115 ini_acf_iireq_src_24m_8m();
2116 apb_write_reg(DVBT_BASE + (0x44 << 2),
2117 0x002A0000);
2118 break; /* 24M */
2119 default:
2120 ini_acf_iireq_src_2857m_8m();
2121 apb_write_reg(DVBT_BASE + (0x44 << 2),
2122 0x0031ffcd);
2123 break; /* 28.57M */
2124 }
2125 } else if (bandwidth == 1) { /* 7M */
2126 switch (samplerate) {
2127 case 0:
2128 ini_acf_iireq_src_45m_7m();
2129 apb_write_reg(DVBT_BASE + (0x44 << 2),
2130 0x0059ff10);
2131 break; /* 45M */
2132 case 1:
2133 ini_acf_iireq_src_207m_7m();
2134 apb_write_reg(DVBT_BASE + (0x44 << 2),
2135 0x0029aaa6);
2136 break; /* 20.833M */
2137 case 2:
2138 ini_acf_iireq_src_207m_7m();
2139 apb_write_reg(DVBT_BASE + (0x44 << 2),
2140 0x00296665);
2141 break; /* 20.7M */
2142 case 3:
2143 ini_acf_iireq_src_2857m_7m();
2144 apb_write_reg(DVBT_BASE + (0x44 << 2),
2145 0x00392491);
2146 break; /* 28.57M */
2147 case 4:
2148 ini_acf_iireq_src_24m_7m();
2149 apb_write_reg(DVBT_BASE + (0x44 << 2),
2150 0x00300000);
2151 break; /* 24M */
2152 default:
2153 ini_acf_iireq_src_2857m_7m();
2154 apb_write_reg(DVBT_BASE + (0x44 << 2),
2155 0x00392491);
2156 break; /* 28.57M */
2157 }
2158 } else if (bandwidth == 2) { /* 6M */
2159 switch (samplerate) {
2160 case 0:
2161 ini_acf_iireq_src_45m_6m();
2162 apb_write_reg(DVBT_BASE + (0x44 << 2),
2163 0x00690000);
2164 break; /* 45M */
2165 case 1:
2166 ini_acf_iireq_src_207m_6m();
2167 apb_write_reg(DVBT_BASE + (0x44 << 2),
2168 0x00309c3e);
2169 break; /* 20.833M */
2170 case 2:
2171 ini_acf_iireq_src_207m_6m();
2172 apb_write_reg(DVBT_BASE + (0x44 << 2),
2173 0x002eaaaa);
2174 break; /* 20.7M */
2175 case 3:
2176 ini_acf_iireq_src_2857m_6m();
2177 apb_write_reg(DVBT_BASE + (0x44 << 2),
2178 0x0042AA69);
2179 break; /* 28.57M */
2180 case 4:
2181 ini_acf_iireq_src_24m_6m();
2182 apb_write_reg(DVBT_BASE + (0x44 << 2),
2183 0x00380000);
2184 break; /* 24M */
2185 default:
2186 ini_acf_iireq_src_2857m_6m();
2187 apb_write_reg(DVBT_BASE + (0x44 << 2),
2188 0x0042AA69);
2189 break; /* 28.57M */
2190 }
2191 } else { /* 5M */
2192 switch (samplerate) {
2193 case 0:
2194 ini_acf_iireq_src_45m_5m();
2195 apb_write_reg(DVBT_BASE + (0x44 << 2),
2196 0x007dfbe0);
2197 break; /* 45M */
2198 case 1:
2199 ini_acf_iireq_src_207m_5m();
2200 apb_write_reg(DVBT_BASE + (0x44 << 2),
2201 0x003a554f);
2202 break; /* 20.833M */
2203 case 2:
2204 ini_acf_iireq_src_207m_5m();
2205 apb_write_reg(DVBT_BASE + (0x44 << 2),
2206 0x0039f5c0);
2207 break; /* 20.7M */
2208 case 3:
2209 ini_acf_iireq_src_2857m_5m();
2210 apb_write_reg(DVBT_BASE + (0x44 << 2),
2211 0x004FFFFE);
2212 break; /* 28.57M */
2213 case 4:
2214 ini_acf_iireq_src_24m_5m();
2215 apb_write_reg(DVBT_BASE + (0x44 << 2),
2216 0x00433333);
2217 break; /* 24M */
2218 default:
2219 ini_acf_iireq_src_2857m_5m();
2220 apb_write_reg(DVBT_BASE + (0x44 << 2),
2221 0x004FFFFE);
2222 break; /* 28.57M */
2223 }
2224 }
2225 } else { /* ISDBT */
2226 switch (samplerate) {
2227 case 0:
2228 ini_acf_iireq_src_45m_6m();
2229 apb_write_reg(DVBT_BASE + (0x44 << 2), 0x00589800);
2230 break;
2231
2232/* 45M
2233 * SampleRate/(symbolRate)*2^20,
2234 * symbolRate = 512/63 for isdbt
2235 */
2236 case 1:
2237 ini_acf_iireq_src_207m_6m();
2238 apb_write_reg(DVBT_BASE + (0x44 << 2), 0x002903d4);
2239 break; /* 20.833M */
2240 case 2:
2241 ini_acf_iireq_src_207m_6m();
2242 apb_write_reg(DVBT_BASE + (0x44 << 2), 0x00280ccc);
2243 break; /* 20.7M */
2244 case 3:
2245 ini_acf_iireq_src_2857m_6m();
2246 apb_write_reg(DVBT_BASE + (0x44 << 2), 0x00383fc8);
2247 break; /* 28.57M */
2248 case 4:
2249 ini_acf_iireq_src_24m_6m();
2250 apb_write_reg(DVBT_BASE + (0x44 << 2), 0x002F4000);
2251 break; /* 24M */
2252 default:
2253 ini_acf_iireq_src_2857m_6m();
2254 apb_write_reg(DVBT_BASE + (0x44 << 2), 0x00383fc8);
2255 break; /* 28.57M */
2256 }
2257 }
2258
2259 if (mode == 0) /* DVBT */
2260 apb_write_reg(DVBT_BASE + (0x02 << 2),
2261 (bandwidth << 20) | 0x10002);
2262 else /* ISDBT */
2263 apb_write_reg(DVBT_BASE + (0x02 << 2), (1 << 20) | 0x1001a);
2264 /* {0x000,2'h1,20'h1_001a}); // For ISDBT , bandwidth should be 1, */
2265
2266 apb_write_reg(DVBT_BASE + (0x45 << 2), 0x00000000);
2267 /* SRC SFO_ADJ_CTRL */
2268 apb_write_reg(DVBT_BASE + (0x46 << 2), 0x02004000);
2269 /* SRC SFO_ADJ_CTRL */
2270 apb_write_reg(DVBT_BASE + (0x48 << 2), 0x000c0287);
2271 /* DAGC_CTRL1 */
2272 apb_write_reg(DVBT_BASE + (0x49 << 2), 0x00000005);
2273 /* DAGC_CTRL2 */
2274 apb_write_reg(DVBT_BASE + (0x4c << 2), 0x00000bbf);
2275 /* CCI_RP */
2276 apb_write_reg(DVBT_BASE + (0x4d << 2), 0x00000376);
2277 /* CCI_RPSQ */
2278 apb_write_reg(DVBT_BASE + (0x4e << 2), 0x0f0f1d09);
2279 /* CCI_CTRL */
2280 apb_write_reg(DVBT_BASE + (0x4f << 2), 0x00000000);
2281 /* CCI DET_INDX1 */
2282 apb_write_reg(DVBT_BASE + (0x50 << 2), 0x00000000);
2283 /* CCI DET_INDX2 */
2284 apb_write_reg(DVBT_BASE + (0x51 << 2), 0x00000000);
2285 /* CCI_NOTCH1_A1 */
2286 apb_write_reg(DVBT_BASE + (0x52 << 2), 0x00000000);
2287 /* CCI_NOTCH1_A2 */
2288 apb_write_reg(DVBT_BASE + (0x53 << 2), 0x00000000);
2289 /* CCI_NOTCH1_B1 */
2290 apb_write_reg(DVBT_BASE + (0x54 << 2), 0x00000000);
2291 /* CCI_NOTCH2_A1 */
2292 apb_write_reg(DVBT_BASE + (0x55 << 2), 0x00000000);
2293 /* CCI_NOTCH2_A2 */
2294 apb_write_reg(DVBT_BASE + (0x56 << 2), 0x00000000);
2295 /* CCI_NOTCH2_B1 */
2296 apb_write_reg(DVBT_BASE + (0x58 << 2), 0x00000885);
2297 /* MODE_DETECT_CTRL // 582 */
2298 if (mode == 0) /* DVBT */
2299 apb_write_reg(DVBT_BASE + (0x5c << 2), 0x00001011); /* */
2300 else
2301 apb_write_reg(DVBT_BASE + (0x5c << 2), 0x00000753);
2302 /* ICFO_EST_CTRL ISDBT ICFO thres = 2 */
2303
2304 apb_write_reg(DVBT_BASE + (0x5f << 2), 0x0ffffe10);
2305 /* TPS_FCFO_CTRL */
2306 apb_write_reg(DVBT_BASE + (0x61 << 2), 0x0000006c);
2307 /* FWDT ctrl */
2308 apb_write_reg(DVBT_BASE + (0x68 << 2), 0x128c3929);
2309 apb_write_reg(DVBT_BASE + (0x69 << 2), 0x91017f2d);
2310 /* 0x1a8 */
2311 apb_write_reg(DVBT_BASE + (0x6b << 2), 0x00442211);
2312 /* 0x1a8 */
2313 apb_write_reg(DVBT_BASE + (0x6c << 2), 0x01fc400a);
2314 /* 0x */
2315 apb_write_reg(DVBT_BASE + (0x6d << 2), 0x0030303f);
2316 /* 0x */
2317 apb_write_reg(DVBT_BASE + (0x73 << 2), 0xffffffff);
2318 /* CCI0_PILOT_UPDATE_CTRL */
2319 apb_write_reg(DVBT_BASE + (0x74 << 2), 0xffffffff);
2320 /* CCI0_DATA_UPDATE_CTRL */
2321 apb_write_reg(DVBT_BASE + (0x75 << 2), 0xffffffff);
2322 /* CCI1_PILOT_UPDATE_CTRL */
2323 apb_write_reg(DVBT_BASE + (0x76 << 2), 0xffffffff);
2324 /* CCI1_DATA_UPDATE_CTRL */
2325
2326 tmp = mode == 0 ? 0x000001a2 : 0x00000da2;
2327 apb_write_reg(DVBT_BASE + (0x78 << 2), tmp); /* FEC_CTR */
2328
2329 apb_write_reg(DVBT_BASE + (0x7d << 2), 0x0000009d);
2330 apb_write_reg(DVBT_BASE + (0x7e << 2), 0x00004000);
2331 apb_write_reg(DVBT_BASE + (0x7f << 2), 0x00008000);
2332
2333 apb_write_reg(DVBT_BASE + ((0x8b + 0) << 2), 0x20002000);
2334 apb_write_reg(DVBT_BASE + ((0x8b + 1) << 2), 0x20002000);
2335 apb_write_reg(DVBT_BASE + ((0x8b + 2) << 2), 0x20002000);
2336 apb_write_reg(DVBT_BASE + ((0x8b + 3) << 2), 0x20002000);
2337 apb_write_reg(DVBT_BASE + ((0x8b + 4) << 2), 0x20002000);
2338 apb_write_reg(DVBT_BASE + ((0x8b + 5) << 2), 0x20002000);
2339 apb_write_reg(DVBT_BASE + ((0x8b + 6) << 2), 0x20002000);
2340 apb_write_reg(DVBT_BASE + ((0x8b + 7) << 2), 0x20002000);
2341
2342 apb_write_reg(DVBT_BASE + (0x93 << 2), 0x31);
2343 apb_write_reg(DVBT_BASE + (0x94 << 2), 0x00);
2344 apb_write_reg(DVBT_BASE + (0x95 << 2), 0x7f1);
2345 apb_write_reg(DVBT_BASE + (0x96 << 2), 0x20);
2346
2347 apb_write_reg(DVBT_BASE + (0x98 << 2), 0x03f9115a);
2348 apb_write_reg(DVBT_BASE + (0x9b << 2), 0x000005df);
2349
2350 apb_write_reg(DVBT_BASE + (0x9c << 2), 0x00100000);
2351 /* TestBus write valid, 0 is system clk valid */
2352 apb_write_reg(DVBT_BASE + (0x9d << 2), 0x01000000);
2353 /* DDR Start address */
2354 apb_write_reg(DVBT_BASE + (0x9e << 2), 0x02000000);
2355 /* DDR End address */
2356
2357 apb_write_regb(DVBT_BASE + (0x9b << 2), 7, 0);
2358 /* Enable Testbus dump to DDR */
2359 apb_write_regb(DVBT_BASE + (0x9b << 2), 8, 0);
2360 /* Run Testbus dump to DDR */
2361
2362 apb_write_reg(DVBT_BASE + (0xd6 << 2), 0x00000003);
2363 /* apb_write_reg(DVBT_BASE+(0xd7<<2), 0x00000008); */
2364 apb_write_reg(DVBT_BASE + (0xd8 << 2), 0x00000120);
2365 apb_write_reg(DVBT_BASE + (0xd9 << 2), 0x01010101);
2366
2367 ini_icfo_pn_index(mode);
2368 tfd_filter_coff_ini();
2369
2370 calculate_cordic_para();
2371 msleep(20);
2372 /* delay_us(1); */
2373
2374 apb_write_reg(DVBT_BASE + (0x02 << 2),
2375 apb_read_reg(DVBT_BASE + (0x02 << 2)) | (1 << 0));
2376 apb_write_reg(DVBT_BASE + (0x02 << 2),
2377 apb_read_reg(DVBT_BASE + (0x02 << 2)) | (1 << 24));
2378#endif
2379/* dvbt_check_status(); */
2380}
2381
2382void calculate_cordic_para(void)
2383{
2384 apb_write_reg(DVBT_BASE + 0x0c, 0x00000040);
2385}
2386
2387char *ofdm_fsm_name[] = { " IDLE",
2388 " AGC",
2389 " CCI",
2390 " ACQ",
2391 " SYNC",
2392 "TRACKING",
2393 " TIMING",
2394 " SP_SYNC",
2395 " TPS_DEC",
2396 "FEC_LOCK",
2397 "FEC_LOST"
2398};
2399
2400void check_fsm_state(void)
2401{
2402 unsigned long tmp;
2403
2404 tmp = apb_read_reg(DVBT_BASE + 0xa8);
2405 /* printk(">>>>>>>>>>>>>>>>>>>>>>>>> OFDM FSM From %d
2406 *to %d\n", tmp>>4&0xf, tmp&0xf);
2407 */
2408
2409 if ((tmp & 0xf) == 3) {
2410 apb_write_regb(DVBT_BASE + (0x9b << 2), 8, 1);
2411 /* Stop dump testbus; */
2412 apb_write_regb(DVBT_BASE + (0x0f << 2), 0, 1);
2413 tmp = apb_read_reg(DVBT_BASE + (0x9f << 2));
2414 /* printk(">>>>>>>>>>>>>>>>>>>>>>>>> STOP DUMP DATA To DDR :
2415 *End Addr %d,Is it overflow?%d\n", tmp>>1, tmp&0x1);
2416 */
2417 }
2418}
2419
2420void ofdm_read_all_regs(void)
2421{
2422 int i;
2423 unsigned long tmp;
2424
2425 for (i = 0; i < 0xff; i++)
2426 tmp = apb_read_reg(DVBT_BASE + 0x00 + i * 4);
2427 /* printk("OFDM Reg (0x%x) is 0x%x\n", i, tmp); */
2428
2429}
2430
2431static int dvbt_get_status(struct aml_demod_sta *demod_sta,
2432 struct aml_demod_i2c *demod_i2c)
2433{
2434 return apb_read_reg(DVBT_BASE + 0x0) >> 12 & 1;
2435}
2436
2437static int dvbt_get_ber(struct aml_demod_sta *demod_sta,
2438 struct aml_demod_i2c *demod_i2c)
2439{
2440/* pr_dbg("[RSJ]per is %u\n",apb_read_reg(DVBT_BASE+(0xbf<<2))); */
2441 return apb_read_reg(DVBT_BASE + (0xbf << 2));
2442}
2443
2444static int dvbt_get_snr(struct aml_demod_sta *demod_sta,
2445 struct aml_demod_i2c *demod_i2c)
2446{
2447/* pr_dbg("2snr is %u\n",((apb_read_reg(DVBT_BASE+(0x0a<<2)))>>20)&0x3ff); */
2448 return ((apb_read_reg(DVBT_BASE + (0x0a << 2))) >> 20) & 0x3ff;
2449 /*dBm: bit0~bit2=decimal */
2450}
2451
2452static int dvbt_get_strength(struct aml_demod_sta *demod_sta,
2453 struct aml_demod_i2c *demod_i2c)
2454{
2455/* int dbm = dvbt_get_ch_power(demod_sta, demod_i2c); */
2456/* return dbm; */
2457 return 0;
2458}
2459
2460static int dvbt_get_ucblocks(struct aml_demod_sta *demod_sta,
2461 struct aml_demod_i2c *demod_i2c)
2462{
2463 return 0;
2464/* return dvbt_get_per(); */
2465}
2466
2467struct demod_status_ops *dvbt_get_status_ops(void)
2468{
2469 static struct demod_status_ops ops = {
2470 .get_status = dvbt_get_status,
2471 .get_ber = dvbt_get_ber,
2472 .get_snr = dvbt_get_snr,
2473 .get_strength = dvbt_get_strength,
2474 .get_ucblocks = dvbt_get_ucblocks,
2475 };
2476
2477 return &ops;
2478}
2479
2480int app_apb_read_reg(int addr)
2481{
2482 addr = DTMB_TOP_ADDR(addr);
2483 return (int)demod_read_demod_reg(addr);
2484}
2485
2486int app_apb_write_reg(int addr, int data)
2487{
2488 addr = DTMB_TOP_ADDR(addr);
2489 demod_set_demod_reg(data, addr);
2490 return 0;
2491}
2492
2493void monitor_isdbt(void)
2494{
2495 int SNR;
2496 int SNR_SP = 500;
2497 int SNR_TPS = 0;
2498 int SNR_CP = 0;
2499 int timeStamp = 0;
2500 int SFO_residual = 0;
2501 int SFO_esti = 0;
2502 int FCFO_esti = 0;
2503 int FCFO_residual = 0;
2504 int AGC_Gain = 0;
2505 int RF_AGC = 0;
2506 int Signal_power = 0;
2507 int FECFlag = 0;
2508 int EQ_seg_ratio = 0;
2509 int tps_0 = 0;
2510 int tps_1 = 0;
2511 int tps_2 = 0;
2512
2513 int time_stamp;
2514 int SFO;
2515 int FCFO;
2516 int timing_adj;
2517 int RS_CorrectNum;
2518
2519 int cnt;
2520 int tmpAGCGain;
2521
2522 tmpAGCGain = 0;
2523 cnt = 0;
2524
2525/* app_apb_write_reg(0x8, app_apb_read_reg(0x8) & ~(1 << 17));
2526 * // TPS symbol index update : active high
2527 */
2528 time_stamp = app_apb_read_reg(0x07) & 0xffff;
2529 SNR = app_apb_read_reg(0x0a);
2530 FECFlag = (app_apb_read_reg(0x00) >> 11) & 0x3;
2531 SFO = app_apb_read_reg(0x47) & 0xfff;
2532 SFO_esti = app_apb_read_reg(0x60) & 0xfff;
2533 FCFO_esti = (app_apb_read_reg(0x60) >> 11) & 0xfff;
2534 FCFO = (app_apb_read_reg(0x26)) & 0xffffff;
2535 RF_AGC = app_apb_read_reg(0x0c) & 0x1fff;
2536 timing_adj = app_apb_read_reg(0x6f) & 0x1fff;
2537 RS_CorrectNum = app_apb_read_reg(0xc1) & 0xfffff;
2538 Signal_power = (app_apb_read_reg(0x1b)) & 0x1ff;
2539 EQ_seg_ratio = app_apb_read_reg(0x6e) & 0x3ffff;
2540 tps_0 = app_apb_read_reg(0x64);
2541 tps_1 = app_apb_read_reg(0x65);
2542 tps_2 = app_apb_read_reg(0x66) & 0xf;
2543
2544 timeStamp = (time_stamp >> 8) * 68 + (time_stamp & 0x7f);
2545 SFO_residual = (SFO > 0x7ff) ? (SFO - 0x1000) : SFO;
2546 FCFO_residual = (FCFO > 0x7fffff) ? (FCFO - 0x1000000) : FCFO;
2547 /* RF_AGC = (RF_AGC>0x3ff)? (RF_AGC - 0x800): RF_AGC; */
2548 FCFO_esti = (FCFO_esti > 0x7ff) ? (FCFO_esti - 0x1000) : FCFO_esti;
2549 SNR_CP = (SNR) & 0x3ff;
2550 SNR_TPS = (SNR >> 10) & 0x3ff;
2551 SNR_SP = (SNR >> 20) & 0x3ff;
2552 SNR_SP = (SNR_SP > 0x1ff) ? SNR_SP - 0x400 : SNR_SP;
2553 SNR_TPS = (SNR_TPS > 0x1ff) ? SNR_TPS - 0x400 : SNR_TPS;
2554 SNR_CP = (SNR_CP > 0x1ff) ? SNR_CP - 0x400 : SNR_CP;
2555 AGC_Gain = tmpAGCGain >> 4;
2556 tmpAGCGain = (AGC_Gain > 0x3ff) ? AGC_Gain - 0x800 : AGC_Gain;
2557 timing_adj = (timing_adj > 0xfff) ? timing_adj - 0x2000 : timing_adj;
2558 EQ_seg_ratio =
2559 (EQ_seg_ratio > 0x1ffff) ? EQ_seg_ratio - 0x40000 : EQ_seg_ratio;
2560
2561 pr_dbg
2562 ("T %4x SP %3d TPS %3d CP %3d EQS %8x RSC %4d",
2563 app_apb_read_reg(0xbf)
2564 , SNR_SP, SNR_TPS, SNR_CP
2565/* ,EQ_seg_ratio */
2566 , app_apb_read_reg(0x62)
2567 , RS_CorrectNum);
2568 pr_dbg
2569 ("SFO %4d FCFO %4d Vit %4x Timing %3d SigP %3x",
2570 SFO_residual, FCFO_residual, RF_AGC, timing_adj,
2571 Signal_power);
2572 pr_dbg
2573 ("FEC %x RSErr %8x ReSyn %x tps %03x%08x",
2574 FECFlag, app_apb_read_reg(0x0b)
2575 , (app_apb_read_reg(0xc0) >> 20) & 0xff,
2576 app_apb_read_reg(0x05) & 0xfff, app_apb_read_reg(0x04)
2577 );
2578 pr_dbg("\n");
2579}
2580
2581int find_2(int data, int *table, int len)
2582{
2583 int end;
2584 int index;
2585 int start;
2586 int cnt = 0;
2587
2588 start = 0;
2589 end = len;
2590 /* printf("data is %d\n",data); */
2591 while ((len > 1) && (cnt < 10)) {
2592 cnt++;
2593 index = (len / 2);
2594 if (data > table[start + index]) {
2595 start = start + index;
2596 len = len - index - 1;
2597 }
2598 if (data < table[start + index]) {
2599 len = index + 1;
2600 } else if (data == table[start + index]) {
2601 start = start + index;
2602 break;
2603 }
2604 }
2605 return start;
2606}
2607
2608int read_atsc_all_reg(void)
2609{
2610 return 0;
2611#if 0
2612 int i, j, k;
2613
2614 j = 4;
2615 unsigned long data;
2616
2617 pr_dbg("system agc is:"); /* system agc */
2618 for (i = 0xc00; i <= 0xc0c; i++) {
2619 data = atsc_read_reg(i);
2620 if (j == 4) {
2621 pr_dbg("\n[addr:0x%x]", i);
2622 j = 0;
2623 }
2624 pr_dbg("%02x ", data);
2625 j++;
2626 }
2627 j = 4;
2628 for (i = 0xc80; i <= 0xc87; i++) {
2629 data = atsc_read_reg(i);
2630 if (j == 4) {
2631 pr_dbg("\n[addr:0x%x]", i);
2632 j = 0;
2633 }
2634 pr_dbg("%02x ", data);
2635 j++;
2636 }
2637 pr_dbg("\n vsb control is:"); /*vsb control */
2638 j = 4;
2639 for (i = 0x900; i <= 0x905; i++) {
2640 data = atsc_read_reg(i);
2641 if (j == 4) {
2642 pr_dbg("\n[addr:0x%x]", i);
2643 j = 0;
2644 }
2645 pr_dbg("%02x ", data);
2646 j++;
2647 }
2648 j = 4;
2649 for (i = 0x908; i <= 0x912; i++) {
2650 data = atsc_read_reg(i);
2651 if (j == 4) {
2652 pr_dbg("\n[addr:0x%x]", i);
2653 j = 0;
2654 }
2655 pr_dbg("%02x ", data);
2656 j++;
2657 }
2658 j = 4;
2659 for (i = 0x917; i <= 0x91b; i++) {
2660 data = atsc_read_reg(i);
2661 if (j == 4) {
2662 pr_dbg("\n[addr:0x%x]", i);
2663 j = 0;
2664 }
2665 pr_dbg("%02x ", data);
2666 j++;
2667 }
2668 j = 4;
2669 for (i = 0x980; i <= 0x992; i++) {
2670 data = atsc_read_reg(i);
2671 if (j == 4) {
2672 pr_dbg("\n[addr:0x%x]", i);
2673 j = 0;
2674 }
2675 pr_dbg("%02x ", data);
2676 j++;
2677 }
2678 pr_dbg("\n vsb demod is:"); /*vsb demod */
2679 j = 4;
2680 for (i = 0x700; i <= 0x711; i++) {
2681 data = atsc_read_reg(i);
2682 if (j == 4) {
2683 pr_dbg("\n[addr:0x%x]", i);
2684 j = 0;
2685 }
2686 pr_dbg("%02x ", data);
2687 j++;
2688 }
2689 j = 4;
2690 for (i = 0x716; i <= 0x720; i++) {
2691 data = atsc_read_reg(i);
2692 if (j == 4) {
2693 pr_dbg("\n[addr:0x%x]", i);
2694 j = 0;
2695 }
2696 pr_dbg("%02x ", data);
2697 j++;
2698 }
2699 j = 4;
2700 for (i = 0x722; i <= 0x724; i++) {
2701 data = atsc_read_reg(i);
2702 if (j == 4) {
2703 pr_dbg("\n[addr:0x%x]", i);
2704 j = 0;
2705 }
2706 pr_dbg("%02x ", data);
2707 j++;
2708 }
2709 j = 4;
2710 for (i = 0x726; i <= 0x72c; i++) {
2711 data = atsc_read_reg(i);
2712 if (j == 4) {
2713 pr_dbg("\n[addr:0x%x]", i);
2714 j = 0;
2715 }
2716 pr_dbg("%02x ", data);
2717 j++;
2718 }
2719 j = 4;
2720 for (i = 0x730; i <= 0x732; i++) {
2721 data = atsc_read_reg(i);
2722 if (j == 4) {
2723 pr_dbg("\n[addr:0x%x]", i);
2724 j = 0;
2725 }
2726 pr_dbg("%02x ", data);
2727 j++;
2728 }
2729 j = 4;
2730 for (i = 0x735; i <= 0x751; i++) {
2731 data = atsc_read_reg(i);
2732 if (j == 4) {
2733 pr_dbg("\n[addr:0x%x]", i);
2734 j = 0;
2735 }
2736 pr_dbg("%02x ", data);
2737 j++;
2738 }
2739 j = 4;
2740 for (i = 0x780; i <= 0x795; i++) {
2741 data = atsc_read_reg(i);
2742 if (j == 4) {
2743 pr_dbg("\n[addr:0x%x]", i);
2744 j = 0;
2745 }
2746 pr_dbg("%02x ", data);
2747 j++;
2748 }
2749 j = 4;
2750 for (i = 0x752; i <= 0x755; i++) {
2751 data = atsc_read_reg(i);
2752 if (j == 4) {
2753 pr_dbg("\n[addr:0x%x]", i);
2754 j = 0;
2755 }
2756 pr_dbg("%02x ", data);
2757 j++;
2758 }
2759 pr_dbg("\n vsb equalizer is:"); /*vsb equalizer */
2760 j = 4;
2761 for (i = 0x501; i <= 0x5ff; i++) {
2762 data = atsc_read_reg(i);
2763 if (j == 4) {
2764 pr_dbg("\n[addr:0x%x]", i);
2765 j = 0;
2766 }
2767 pr_dbg("%02x ", data);
2768 j++;
2769 }
2770 pr_dbg("\n vsb fec is:"); /*vsb fec */
2771 j = 4;
2772 for (i = 0x601; i <= 0x601; i++) {
2773 data = atsc_read_reg(i);
2774 if (j == 4) {
2775 pr_dbg("\n[addr:0x%x]", i);
2776 j = 0;
2777 }
2778 pr_dbg("%02x ", data);
2779 j++;
2780 }
2781 j = 4;
2782 for (i = 0x682; i <= 0x685; i++) {
2783 data = atsc_read_reg(i);
2784 if (j == 4) {
2785 pr_dbg("\n[addr:0x%x]", i);
2786 j = 0;
2787 }
2788 pr_dbg("%02x ", data);
2789 j++;
2790 }
2791 pr_dbg("\n qam demod is:"); /*qam demod */
2792 j = 4;
2793 for (i = 0x1; i <= 0x1a; i++) {
2794 data = atsc_read_reg(i);
2795 if (j == 4) {
2796 pr_dbg("\n[addr:0x%x]", i);
2797 j = 0;
2798 }
2799 pr_dbg("%02x ", data);
2800 j++;
2801 }
2802 j = 4;
2803 for (i = 0x25; i <= 0x28; i++) {
2804 data = atsc_read_reg(i);
2805 if (j == 4) {
2806 pr_dbg("\n[addr:0x%x]", i);
2807 j = 0;
2808 }
2809 pr_dbg("%02x ", data);
2810 j++;
2811 }
2812 j = 4;
2813 for (i = 0x101; i <= 0x10b; i++) {
2814 data = atsc_read_reg(i);
2815 if (j == 4) {
2816 pr_dbg("\n[addr:0x%x]", i);
2817 j = 0;
2818 }
2819 pr_dbg("%02x ", data);
2820 j++;
2821 }
2822 j = 4;
2823 for (i = 0x206; i <= 0x207; i++) {
2824 data = atsc_read_reg(i);
2825 if (j == 4) {
2826 pr_dbg("\n[addr:0x%x]", i);
2827 j = 0;
2828 }
2829 pr_dbg("%02x ", data);
2830 j++;
2831 }
2832 pr_dbg("\n qam equalize is:"); /*qam equalize */
2833 j = 4;
2834 for (i = 0x200; i <= 0x23d; i++) {
2835 data = atsc_read_reg(i);
2836 if (j == 4) {
2837 pr_dbg("\n[addr:0x%x]", i);
2838 j = 0;
2839 }
2840 pr_dbg("%02x ", data);
2841 j++;
2842 }
2843 j = 4;
2844 for (i = 0x260; i <= 0x275; i++) {
2845 data = atsc_read_reg(i);
2846 if (j == 4) {
2847 pr_dbg("\n[addr:0x%x]", i);
2848 j = 0;
2849 }
2850 pr_dbg("%02x ", data);
2851 j++;
2852 }
2853 pr_dbg("\n qam fec is:"); /*qam fec */
2854 j = 4;
2855 for (i = 0x400; i <= 0x418; i++) {
2856 data = atsc_read_reg(i);
2857 if (j == 4) {
2858 pr_dbg("\n[addr:0x%x]", i);
2859 j = 0;
2860 }
2861 pr_dbg("%02x ", data);
2862 j++;
2863 }
2864 pr_dbg("\n system mpeg formatter is:"); /*system mpeg formatter */
2865 j = 4;
2866 for (i = 0xf00; i <= 0xf09; i++) {
2867 data = atsc_read_reg(i);
2868 if (j == 4) {
2869 pr_dbg("\n[addr:0x%x]", i);
2870 j = 0;
2871 }
2872 pr_dbg("%02x ", data);
2873 j++;
2874 }
2875 pr_dbg("\n\n");
2876 return 0;
2877#endif
2878}
2879
2880int check_atsc_fsm_status(void)
2881{
2882 int SNR;
2883 int atsc_snr = 0;
2884 int SNR_dB;
2885 int SNR_table[56] = { 0, 7, 9, 11, 14,
2886 17,
2887 22,
2888 27, 34, 43, 54,
2889 68, 86, 108, 136, 171,
2890 215,
2891 271, 341,
2892 429, 540,
2893 566, 592, 620, 649, 680,
2894 712,
2895 746, 781,
2896 818, 856,
2897 896, 939, 983, 1029, 1078,
2898 1182,
2899 1237,
2900 1237, 1296, 1357,
2901 1708, 2150, 2707, 3408, 4291,
2902 5402,
2903 6800,
2904 8561, 10778, 13568,
2905 16312, 17081, 18081, 19081, 65536
2906 };
2907 int SNR_dB_table[56] = { 360, 350, 340, 330, 320, 310, 300,
2908 290,
2909 280,
2910 270, 260,
2911 250, 240, 230, 220, 210, 200, 190,
2912 180,
2913 170,
2914 160,
2915 158, 156, 154, 152, 150, 148, 146,
2916 144,
2917 142,
2918 140,
2919 138, 136, 134, 132, 130, 128, 126,
2920 124,
2921 122,
2922 120,
2923 110, 100, 90, 80, 70, 60, 50,
2924 40,
2925 30,
2926 20,
2927 12, 10, 4, 2, 0
2928 };
2929
2930 int tmp[3];
2931 int cr;
2932 int ck;
2933 int SM;
2934 int tni;
2935 int ber;
2936 int per;
2937
2938 int cnt;
2939
2940 cnt = 0;
2941 ber = 0;
2942 per = 0;
2943
2944/* g_demod_mode = 2; */
2945 tni = atsc_read_reg((0x08) >> 16);
2946/* g_demod_mode = 4; */
2947 tmp[0] = atsc_read_reg(0x0511);
2948 tmp[1] = atsc_read_reg(0x0512);
2949 SNR = (tmp[0] << 8) + tmp[1];
2950 SNR_dB = SNR_dB_table[find_2(SNR, SNR_table, 56)];
2951
2952 tmp[0] = atsc_read_reg(0x0780);
2953 tmp[1] = atsc_read_reg(0x0781);
2954 tmp[2] = atsc_read_reg(0x0782);
2955 cr = tmp[0] + (tmp[1] << 8) + (tmp[2] << 16);
2956 tmp[0] = atsc_read_reg(0x0786);
2957 tmp[1] = atsc_read_reg(0x0787);
2958 tmp[2] = atsc_read_reg(0x0788);
2959 ck = (tmp[0] << 16) + (tmp[1] << 8) + tmp[2];
2960 ck = (ck > 8388608) ? ck - 16777216 : ck;
2961 SM = atsc_read_reg(0x0980);
2962/* ber per */
2963 atsc_write_reg(0x0601, atsc_read_reg(0x0601) & (~(1 << 3)));
2964 atsc_write_reg(0x0601, atsc_read_reg(0x0601) | (1 << 3));
2965 ber = atsc_read_reg(0x0683) + (atsc_read_reg(0x0682) << 8);
2966 per = atsc_read_reg(0x0685) + (atsc_read_reg(0x0684) << 8);
2967
2968/* read_atsc_all_reg(); */
2969
2970 pr_dbg
2971 ("INT %x SNR %x SNRdB %d.%d FSM %x cr %d ck %d",
2972 tni, SNR, (SNR_dB / 10)
2973 , (SNR_dB - (SNR_dB / 10) * 10)
2974 , SM, cr, ck);
2975 pr_dbg
2976 ("ber is %d, per is %d\n",
2977 ber, per);
2978
2979 atsc_snr = (SNR_dB / 10);
2980 return atsc_snr;
2981
2982 /* unsigned long sm,snr1,snr2,snr;
2983 * static int fec_lock_cnt = 0;
2984 *
2985 * delay_us(10000);
2986 * sm = atsc_read_reg(0x0980);
2987 * snr1 = atsc_read_reg(0x0511)&0xff;
2988 * snr2 = atsc_read_reg(0x0512)&0xff;
2989 * snr = (snr1 << 8) + snr2;
2990 *
2991 * printk(">>>>>>>>>>>>>>>>>>>>>>>>>
2992 OFDM FSM %x SNR %x\n", sm&0xff, snr);
2993 *
2994 * if (sm == 0x79) stimulus_finish_pass();
2995 */
2996}
2997
generated by cgit at 2024-05-19 17:09:05 (GMT)