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path: root/drivers/stream_input/tv_frontend/dtv_demod/dvbt_func.c (plain)
blob: 7654aaef160765ae9167bd54b7980a702721bd55
1/*
2* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
3*
4* This program is free software; you can redistribute it and/or modify
5* it under the terms of the GNU General Public License as published by
6* the Free Software Foundation; either version 2 of the License, or
7* (at your option) any later version.
8*
9* This program is distributed in the hope that it will be useful, but WITHOUT
10* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12* more details.
13*
14* You should have received a copy of the GNU General Public License along
15* with this program; if not, write to the Free Software Foundation, Inc.,
16* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17*
18* Description:
19*/
20#include <linux/kernel.h>
21#include <linux/i2c.h>
22#include <linux/delay.h>
23#include <linux/dvb/aml_demod.h>
24#include "demod_func.h"
25
26static int debug_amldvbt;
27
28module_param(debug_amldvbt, int, 0644);
29MODULE_PARM_DESC(debug_amldvbt, "turn on debugging (default: 0)");
30#define dprintk(args ...) do { if (debug_amldvbt) printk(args); } while (0)
31
32static int tuner_type = 3;
33
34static void set_ACF_coef(int ADsample, int bandwidth)
35{
36 if (ADsample == 45) {
37 /* Set ACF and IIREQ */
38 if (bandwidth == 0) {
39 /*8M Hz */
40 apb_write_reg(2, 0x2c, 0x255); /* ACF_STAGE1_A1 */
41 apb_write_reg(2, 0x2d, 0x0B5); /* ACF_STAGE1_A2 */
42 apb_write_reg(2, 0x2e, 0x091); /* ACF_STAGE1_B1 */
43 apb_write_reg(2, 0x2f, 0x02E); /* ACF_STAGE1_GAIN */
44 apb_write_reg(2, 0x30, 0x253); /* ACF_STAGE2_A1 */
45 apb_write_reg(2, 0x31, 0x0CB); /* ACF_STAGE2_A2 */
46 apb_write_reg(2, 0x32, 0x2CD); /* ACF_STAGE2_B1 */
47 apb_write_reg(2, 0x33, 0x07C); /* ACF_STAGE2_GAIN */
48 apb_write_reg(2, 0x34, 0x250); /* ACF_STAGE3_A1 */
49 apb_write_reg(2, 0x35, 0x0E4); /* ACF_STAGE3_A2 */
50 apb_write_reg(2, 0x36, 0x276); /* ACF_STAGE3_B1 */
51 apb_write_reg(2, 0x37, 0x05D); /* ACF_STAGE3_GAIN */
52 apb_write_reg(2, 0x38, 0x24D); /* ACF_STAGE4_A1 */
53 apb_write_reg(2, 0x39, 0x0F3); /* ACF_STAGE4_A2 */
54 apb_write_reg(2, 0x3a, 0x25E); /* ACF_STAGE4_B1 */
55 apb_write_reg(2, 0x3b, 0x05A); /* ACF_STAGE4_GAIN */
56 apb_write_reg(2, 0x3c, 0x24A); /* ACF_STAGE5_A1 */
57 apb_write_reg(2, 0x3d, 0x0FD); /* ACF_STAGE5_A2 */
58 apb_write_reg(2, 0x3e, 0x256); /* ACF_STAGE5_B1 */
59 apb_write_reg(2, 0x3f, 0x04B); /* ACF_STAGE5_GAIN */
60
61 apb_write_reg(2, 0xfe, 0x000);
62 apb_write_reg(2, 0xff, 0x003effff);
63 apb_write_reg(2, 0xfe, 0x001);
64 apb_write_reg(2, 0xff, 0x003cefbe);
65 apb_write_reg(2, 0xfe, 0x002);
66 apb_write_reg(2, 0xff, 0x003adf7c);
67 apb_write_reg(2, 0xfe, 0x003);
68 apb_write_reg(2, 0xff, 0x0038bf39);
69 apb_write_reg(2, 0xfe, 0x004);
70 apb_write_reg(2, 0xff, 0x003696f5);
71 apb_write_reg(2, 0xfe, 0x005);
72 apb_write_reg(2, 0xff, 0x003466b0);
73 apb_write_reg(2, 0xfe, 0x006);
74 apb_write_reg(2, 0xff, 0x00322e69);
75 apb_write_reg(2, 0xfe, 0x007);
76 apb_write_reg(2, 0xff, 0x002fee21);
77 apb_write_reg(2, 0xfe, 0x008);
78 apb_write_reg(2, 0xff, 0x002dadd9);
79 apb_write_reg(2, 0xfe, 0x009);
80 apb_write_reg(2, 0xff, 0x002b6d91);
81 apb_write_reg(2, 0xfe, 0x00a);
82 apb_write_reg(2, 0xff, 0x00291d48);
83 apb_write_reg(2, 0xfe, 0x00b);
84 apb_write_reg(2, 0xff, 0x0026ccfe);
85 apb_write_reg(2, 0xfe, 0x00c);
86 apb_write_reg(2, 0xff, 0x00245cb2);
87 apb_write_reg(2, 0xfe, 0x00d);
88 apb_write_reg(2, 0xff, 0x0021d463);
89 apb_write_reg(2, 0xfe, 0x00e);
90 apb_write_reg(2, 0xff, 0x001f2410);
91 apb_write_reg(2, 0xfe, 0x00f);
92 apb_write_reg(2, 0xff, 0x001c3bb6);
93 apb_write_reg(2, 0xfe, 0x010);
94 apb_write_reg(2, 0xff, 0x00192b57);
95 apb_write_reg(2, 0xfe, 0x011);
96 apb_write_reg(2, 0xff, 0x0015e2f1);
97 apb_write_reg(2, 0xfe, 0x012);
98 apb_write_reg(2, 0xff, 0x00127285);
99 apb_write_reg(2, 0xfe, 0x013);
100 apb_write_reg(2, 0xff, 0x000eca14);
101 apb_write_reg(2, 0xfe, 0x014);
102 apb_write_reg(2, 0xff, 0x000ac99b);
103 apb_write_reg(2, 0xfe, 0x015);
104 apb_write_reg(2, 0xff, 0x00063913);
105 apb_write_reg(2, 0xfe, 0x016);
106 apb_write_reg(2, 0xff, 0x0000c073);
107 apb_write_reg(2, 0xfe, 0x017);
108 apb_write_reg(2, 0xff, 0x003a3fb4);
109 apb_write_reg(2, 0xfe, 0x018);
110 apb_write_reg(2, 0xff, 0x00347ecf);
111 apb_write_reg(2, 0xfe, 0x019);
112 apb_write_reg(2, 0xff, 0x002ff649);
113 apb_write_reg(2, 0xfe, 0x01a);
114 apb_write_reg(2, 0xff, 0x002a8dab);
115 apb_write_reg(2, 0xfe, 0x01b);
116 apb_write_reg(2, 0xff, 0x002444f0);
117 apb_write_reg(2, 0xfe, 0x01c);
118 apb_write_reg(2, 0xff, 0x001d0c1b);
119 apb_write_reg(2, 0xfe, 0x01d);
120 apb_write_reg(2, 0xff, 0x000fc300);
121 apb_write_reg(2, 0xfe, 0x01e);
122 apb_write_reg(2, 0xff, 0x000118ce);
123 apb_write_reg(2, 0xfe, 0x01f);
124 apb_write_reg(2, 0xff, 0x003c17c3);
125 apb_write_reg(2, 0xfe, 0x020);
126 apb_write_reg(2, 0xff, 0x00000751);
127 } else if (bandwidth == 1) {
128 /* 7Mhz */
129 apb_write_reg(2, 0x2c, 0x24B); /* ACF_STAGE1_A1 */
130 apb_write_reg(2, 0x2d, 0x0BD); /* ACF_STAGE1_A2 */
131 apb_write_reg(2, 0x2e, 0x04B); /* ACF_STAGE1_B1 */
132 apb_write_reg(2, 0x2f, 0x03E); /* ACF_STAGE1_GAIN */
133 apb_write_reg(2, 0x30, 0x246); /* ACF_STAGE2_A1 */
134 apb_write_reg(2, 0x31, 0x0D1); /* ACF_STAGE2_A2 */
135 apb_write_reg(2, 0x32, 0x2A2); /* ACF_STAGE2_B1 */
136 apb_write_reg(2, 0x33, 0x07C); /* ACF_STAGE2_GAIN */
137 apb_write_reg(2, 0x34, 0x241); /* ACF_STAGE3_A1 */
138 apb_write_reg(2, 0x35, 0x0E7); /* ACF_STAGE3_A2 */
139 apb_write_reg(2, 0x36, 0x25B); /* ACF_STAGE3_B1 */
140 apb_write_reg(2, 0x37, 0x05D); /* ACF_STAGE3_GAIN */
141 apb_write_reg(2, 0x38, 0x23D); /* ACF_STAGE4_A1 */
142 apb_write_reg(2, 0x39, 0x0F5); /* ACF_STAGE4_A2 */
143 apb_write_reg(2, 0x3a, 0x248); /* ACF_STAGE4_B1 */
144 apb_write_reg(2, 0x3b, 0x05A); /* ACF_STAGE4_GAIN */
145 apb_write_reg(2, 0x3c, 0x23A); /* ACF_STAGE5_A1 */
146 apb_write_reg(2, 0x3d, 0x0FD); /* ACF_STAGE5_A2 */
147 apb_write_reg(2, 0x3e, 0x242); /* ACF_STAGE5_B1 */
148 apb_write_reg(2, 0x3f, 0x04B); /* ACF_STAGE5_GAIN */
149 apb_write_reg(2, 0xfe, 0x000);
150 apb_write_reg(2, 0xff, 0x003f07ff);
151 apb_write_reg(2, 0xfe, 0x001);
152 apb_write_reg(2, 0xff, 0x003cffbf);
153 apb_write_reg(2, 0xfe, 0x002);
154 apb_write_reg(2, 0xff, 0x003aef7e);
155 apb_write_reg(2, 0xfe, 0x003);
156 apb_write_reg(2, 0xff, 0x0038d73c);
157 apb_write_reg(2, 0xfe, 0x004);
158 apb_write_reg(2, 0xff, 0x0036b6f9);
159 apb_write_reg(2, 0xfe, 0x005);
160 apb_write_reg(2, 0xff, 0x003486b3);
161 apb_write_reg(2, 0xfe, 0x006);
162 apb_write_reg(2, 0xff, 0x00324e6d);
163 apb_write_reg(2, 0xfe, 0x007);
164 apb_write_reg(2, 0xff, 0x00300e25);
165 apb_write_reg(2, 0xfe, 0x008);
166 apb_write_reg(2, 0xff, 0x002dcddd);
167 apb_write_reg(2, 0xfe, 0x009);
168 apb_write_reg(2, 0xff, 0x002b8594);
169 apb_write_reg(2, 0xfe, 0x00a);
170 apb_write_reg(2, 0xff, 0x00292d4b);
171 apb_write_reg(2, 0xfe, 0x00b);
172 apb_write_reg(2, 0xff, 0x0026d500);
173 apb_write_reg(2, 0xfe, 0x00c);
174 apb_write_reg(2, 0xff, 0x00245cb3);
175 apb_write_reg(2, 0xfe, 0x00d);
176 apb_write_reg(2, 0xff, 0x0021cc62);
177 apb_write_reg(2, 0xfe, 0x00e);
178 apb_write_reg(2, 0xff, 0x001f0c0d);
179 apb_write_reg(2, 0xfe, 0x00f);
180 apb_write_reg(2, 0xff, 0x001c1bb3);
181 apb_write_reg(2, 0xfe, 0x010);
182 apb_write_reg(2, 0xff, 0x0018fb52);
183 apb_write_reg(2, 0xfe, 0x011);
184 apb_write_reg(2, 0xff, 0x0015b2eb);
185 apb_write_reg(2, 0xfe, 0x012);
186 apb_write_reg(2, 0xff, 0x00123a7f);
187 apb_write_reg(2, 0xfe, 0x013);
188 apb_write_reg(2, 0xff, 0x000e9a0e);
189 apb_write_reg(2, 0xfe, 0x014);
190 apb_write_reg(2, 0xff, 0x000a9995);
191 apb_write_reg(2, 0xfe, 0x015);
192 apb_write_reg(2, 0xff, 0x0006090d);
193 apb_write_reg(2, 0xfe, 0x016);
194 apb_write_reg(2, 0xff, 0x0000a06e);
195 apb_write_reg(2, 0xfe, 0x017);
196 apb_write_reg(2, 0xff, 0x003a57b3);
197 apb_write_reg(2, 0xfe, 0x018);
198 apb_write_reg(2, 0xff, 0x0034ded8);
199 apb_write_reg(2, 0xfe, 0x019);
200 apb_write_reg(2, 0xff, 0x00309659);
201 apb_write_reg(2, 0xfe, 0x01a);
202 apb_write_reg(2, 0xff, 0x002b75c4);
203 apb_write_reg(2, 0xfe, 0x01b);
204 apb_write_reg(2, 0xff, 0x0025350e);
205 apb_write_reg(2, 0xfe, 0x01c);
206 apb_write_reg(2, 0xff, 0x001dec37);
207 apb_write_reg(2, 0xfe, 0x01d);
208 apb_write_reg(2, 0xff, 0x00126b28);
209 apb_write_reg(2, 0xfe, 0x01e);
210 apb_write_reg(2, 0xff, 0x00031130);
211 apb_write_reg(2, 0xfe, 0x01f);
212 apb_write_reg(2, 0xff, 0x003cffec);
213 apb_write_reg(2, 0xfe, 0x020);
214 apb_write_reg(2, 0xff, 0x00000767);
215 } else if (bandwidth == 2) {
216 /* 6MHz */
217 apb_write_reg(2, 0x2c, 0x240); /* ACF_STAGE1_A1 */
218 apb_write_reg(2, 0x2d, 0x0C6); /* ACF_STAGE1_A2 */
219 apb_write_reg(2, 0x2e, 0x3F9); /* ACF_STAGE1_B1 */
220 apb_write_reg(2, 0x2f, 0x03E); /* ACF_STAGE1_GAIN */
221 apb_write_reg(2, 0x30, 0x23A); /* ACF_STAGE2_A1 */
222 apb_write_reg(2, 0x31, 0x0D7); /* ACF_STAGE2_A2 */
223 apb_write_reg(2, 0x32, 0x27B); /* ACF_STAGE2_B1 */
224 apb_write_reg(2, 0x33, 0x07C); /* ACF_STAGE2_GAIN */
225 apb_write_reg(2, 0x34, 0x233); /* ACF_STAGE3_A1 */
226 apb_write_reg(2, 0x35, 0x0EA); /* ACF_STAGE3_A2 */
227 apb_write_reg(2, 0x36, 0x244); /* ACF_STAGE3_B1 */
228 apb_write_reg(2, 0x37, 0x05D); /* ACF_STAGE3_GAIN */
229 apb_write_reg(2, 0x38, 0x22F); /* ACF_STAGE4_A1 */
230 apb_write_reg(2, 0x39, 0x0F6); /* ACF_STAGE4_A2 */
231 apb_write_reg(2, 0x3a, 0x235); /* ACF_STAGE4_B1 */
232 apb_write_reg(2, 0x3b, 0x05A); /* ACF_STAGE4_GAIN */
233 apb_write_reg(2, 0x3c, 0x22B); /* ACF_STAGE5_A1 */
234 apb_write_reg(2, 0x3d, 0x0FD); /* ACF_STAGE5_A2 */
235 apb_write_reg(2, 0x3e, 0x231); /* ACF_STAGE5_B1 */
236 apb_write_reg(2, 0x3f, 0x04B); /* ACF_STAGE5_GAIN */
237 apb_write_reg(2, 0xfe, 0x000);
238 apb_write_reg(2, 0xff, 0x003f07ff);
239 apb_write_reg(2, 0xfe, 0x001);
240 apb_write_reg(2, 0xff, 0x003cffbf);
241 apb_write_reg(2, 0xfe, 0x002);
242 apb_write_reg(2, 0xff, 0x003aef7e);
243 apb_write_reg(2, 0xfe, 0x003);
244 apb_write_reg(2, 0xff, 0x0038d73c);
245 apb_write_reg(2, 0xfe, 0x004);
246 apb_write_reg(2, 0xff, 0x0036b6f8);
247 apb_write_reg(2, 0xfe, 0x005);
248 apb_write_reg(2, 0xff, 0x003486b3);
249 apb_write_reg(2, 0xfe, 0x006);
250 apb_write_reg(2, 0xff, 0x0032466c);
251 apb_write_reg(2, 0xfe, 0x007);
252 apb_write_reg(2, 0xff, 0x002ffe24);
253 apb_write_reg(2, 0xfe, 0x008);
254 apb_write_reg(2, 0xff, 0x002dadda);
255 apb_write_reg(2, 0xfe, 0x009);
256 apb_write_reg(2, 0xff, 0x002b5d90);
257 apb_write_reg(2, 0xfe, 0x00a);
258 apb_write_reg(2, 0xff, 0x0028fd45);
259 apb_write_reg(2, 0xfe, 0x00b);
260 apb_write_reg(2, 0xff, 0x002694f9);
261 apb_write_reg(2, 0xfe, 0x00c);
262 apb_write_reg(2, 0xff, 0x002414ab);
263 apb_write_reg(2, 0xfe, 0x00d);
264 apb_write_reg(2, 0xff, 0x00217458);
265 apb_write_reg(2, 0xfe, 0x00e);
266 apb_write_reg(2, 0xff, 0x001ea402);
267 apb_write_reg(2, 0xfe, 0x00f);
268 apb_write_reg(2, 0xff, 0x001ba3a5);
269 apb_write_reg(2, 0xfe, 0x010);
270 apb_write_reg(2, 0xff, 0x00187342);
271 apb_write_reg(2, 0xfe, 0x011);
272 apb_write_reg(2, 0xff, 0x00151ad9);
273 apb_write_reg(2, 0xfe, 0x012);
274 apb_write_reg(2, 0xff, 0x0011926b);
275 apb_write_reg(2, 0xfe, 0x013);
276 apb_write_reg(2, 0xff, 0x000dc9f6);
277 apb_write_reg(2, 0xfe, 0x014);
278 apb_write_reg(2, 0xff, 0x0009a178);
279 apb_write_reg(2, 0xfe, 0x015);
280 apb_write_reg(2, 0xff, 0x0004d8eb);
281 apb_write_reg(2, 0xfe, 0x016);
282 apb_write_reg(2, 0xff, 0x003f4045);
283 apb_write_reg(2, 0xfe, 0x017);
284 apb_write_reg(2, 0xff, 0x0038e785);
285 apb_write_reg(2, 0xfe, 0x018);
286 apb_write_reg(2, 0xff, 0x00337eab);
287 apb_write_reg(2, 0xfe, 0x019);
288 apb_write_reg(2, 0xff, 0x002f3e2d);
289 apb_write_reg(2, 0xfe, 0x01a);
290 apb_write_reg(2, 0xff, 0x002a1599);
291 apb_write_reg(2, 0xfe, 0x01b);
292 apb_write_reg(2, 0xff, 0x0023ace1);
293 apb_write_reg(2, 0xfe, 0x01c);
294 apb_write_reg(2, 0xff, 0x001b33fb);
295 apb_write_reg(2, 0xfe, 0x01d);
296 apb_write_reg(2, 0xff, 0x000cd29c);
297 apb_write_reg(2, 0xfe, 0x01e);
298 apb_write_reg(2, 0xff, 0x0001c0c1);
299 apb_write_reg(2, 0xfe, 0x01f);
300 apb_write_reg(2, 0xff, 0x003cefde);
301 apb_write_reg(2, 0xfe, 0x020);
302 apb_write_reg(2, 0xff, 0x0000076a);
303 } else {
304 /* 5MHz */
305 apb_write_reg(2, 0x2c, 0x236); /* ACF_STAGE1_A1 */
306 apb_write_reg(2, 0x2d, 0x0CE); /* ACF_STAGE1_A2 */
307 apb_write_reg(2, 0x2e, 0x39A); /* ACF_STAGE1_B1 */
308 apb_write_reg(2, 0x2f, 0x03E); /* ACF_STAGE1_GAIN */
309 apb_write_reg(2, 0x30, 0x22F); /* ACF_STAGE2_A1 */
310 apb_write_reg(2, 0x31, 0x0DE); /* ACF_STAGE2_A2 */
311 apb_write_reg(2, 0x32, 0x257); /* ACF_STAGE2_B1 */
312 apb_write_reg(2, 0x33, 0x07C); /* ACF_STAGE2_GAIN */
313 apb_write_reg(2, 0x34, 0x227); /* ACF_STAGE3_A1 */
314 apb_write_reg(2, 0x35, 0x0EE); /* ACF_STAGE3_A2 */
315 apb_write_reg(2, 0x36, 0x230); /* ACF_STAGE3_B1 */
316 apb_write_reg(2, 0x37, 0x05D); /* ACF_STAGE3_GAIN */
317 apb_write_reg(2, 0x38, 0x222); /* ACF_STAGE4_A1 */
318 apb_write_reg(2, 0x39, 0x0F8); /* ACF_STAGE4_A2 */
319 apb_write_reg(2, 0x3a, 0x225); /* ACF_STAGE4_B1 */
320 apb_write_reg(2, 0x3b, 0x05A); /* ACF_STAGE4_GAIN */
321 apb_write_reg(2, 0x3c, 0x21E); /* ACF_STAGE5_A1 */
322 apb_write_reg(2, 0x3d, 0x0FE); /* ACF_STAGE5_A2 */
323 apb_write_reg(2, 0x3e, 0x222); /* ACF_STAGE5_B1 */
324 apb_write_reg(2, 0x3f, 0x04B); /* ACF_STAGE5_GAIN */
325 apb_write_reg(2, 0xfe, 0x000);
326 apb_write_reg(2, 0xff, 0x003effff);
327 apb_write_reg(2, 0xfe, 0x001);
328 apb_write_reg(2, 0xff, 0x003ce7bd);
329 apb_write_reg(2, 0xfe, 0x002);
330 apb_write_reg(2, 0xff, 0x003ac77a);
331 apb_write_reg(2, 0xfe, 0x003);
332 apb_write_reg(2, 0xff, 0x0038a737);
333 apb_write_reg(2, 0xfe, 0x004);
334 apb_write_reg(2, 0xff, 0x00367ef2);
335 apb_write_reg(2, 0xfe, 0x005);
336 apb_write_reg(2, 0xff, 0x00344eac);
337 apb_write_reg(2, 0xfe, 0x006);
338 apb_write_reg(2, 0xff, 0x00321e66);
339 apb_write_reg(2, 0xfe, 0x007);
340 apb_write_reg(2, 0xff, 0x002fee20);
341 apb_write_reg(2, 0xfe, 0x008);
342 apb_write_reg(2, 0xff, 0x002dbdda);
343 apb_write_reg(2, 0xfe, 0x009);
344 apb_write_reg(2, 0xff, 0x002b8d94);
345 apb_write_reg(2, 0xfe, 0x00a);
346 apb_write_reg(2, 0xff, 0x00295d4e);
347 apb_write_reg(2, 0xfe, 0x00b);
348 apb_write_reg(2, 0xff, 0x00272508);
349 apb_write_reg(2, 0xfe, 0x00c);
350 apb_write_reg(2, 0xff, 0x0024dcc0);
351 apb_write_reg(2, 0xfe, 0x00d);
352 apb_write_reg(2, 0xff, 0x00227475);
353 apb_write_reg(2, 0xfe, 0x00e);
354 apb_write_reg(2, 0xff, 0x001fe426);
355 apb_write_reg(2, 0xfe, 0x00f);
356 apb_write_reg(2, 0xff, 0x001d1bd1);
357 apb_write_reg(2, 0xfe, 0x010);
358 apb_write_reg(2, 0xff, 0x001a2374);
359 apb_write_reg(2, 0xfe, 0x011);
360 apb_write_reg(2, 0xff, 0x0016e311);
361 apb_write_reg(2, 0xfe, 0x012);
362 apb_write_reg(2, 0xff, 0x00136aa6);
363 apb_write_reg(2, 0xfe, 0x013);
364 apb_write_reg(2, 0xff, 0x000fba33);
365 apb_write_reg(2, 0xfe, 0x014);
366 apb_write_reg(2, 0xff, 0x000ba9b8);
367 apb_write_reg(2, 0xfe, 0x015);
368 apb_write_reg(2, 0xff, 0x0007092e);
369 apb_write_reg(2, 0xfe, 0x016);
370 apb_write_reg(2, 0xff, 0x0001988e);
371 apb_write_reg(2, 0xfe, 0x017);
372 apb_write_reg(2, 0xff, 0x003b37d0);
373 apb_write_reg(2, 0xfe, 0x018);
374 apb_write_reg(2, 0xff, 0x0035aef3);
375 apb_write_reg(2, 0xfe, 0x019);
376 apb_write_reg(2, 0xff, 0x00316673);
377 apb_write_reg(2, 0xfe, 0x01a);
378 apb_write_reg(2, 0xff, 0x002c45de);
379 apb_write_reg(2, 0xfe, 0x01b);
380 apb_write_reg(2, 0xff, 0x0025e527);
381 apb_write_reg(2, 0xfe, 0x01c);
382 apb_write_reg(2, 0xff, 0x001da444);
383 apb_write_reg(2, 0xfe, 0x01d);
384 apb_write_reg(2, 0xff, 0x000deaea);
385 apb_write_reg(2, 0xfe, 0x01e);
386 apb_write_reg(2, 0xff, 0x000178bf);
387 apb_write_reg(2, 0xfe, 0x01f);
388 apb_write_reg(2, 0xff, 0x003cb7d6);
389 apb_write_reg(2, 0xfe, 0x020);
390 apb_write_reg(2, 0xff, 0x00000765);
391 }
392 } else if (ADsample == 28) {
393 /* 28.5714 MHz Set ACF */
394 if (bandwidth == 0) {
395 /*8M Hz */
396 apb_write_reg(2, 0x2c, 0x2DB); /* ACF_STAGE1_A1 */
397 apb_write_reg(2, 0x2d, 0x05B); /* ACF_STAGE1_A2 */
398 apb_write_reg(2, 0x2e, 0x163); /* ACF_STAGE1_B1 */
399 apb_write_reg(2, 0x2f, 0x00E); /* ACF_STAGE1_GAIN */
400 apb_write_reg(2, 0x30, 0x2D5); /* ACF_STAGE2_A1 */
401 apb_write_reg(2, 0x31, 0x08B); /* ACF_STAGE2_A2 */
402 apb_write_reg(2, 0x32, 0x3BC); /* ACF_STAGE2_B1 */
403 apb_write_reg(2, 0x33, 0x06D); /* ACF_STAGE2_GAIN */
404 apb_write_reg(2, 0x34, 0x2CF); /* ACF_STAGE3_A1 */
405 apb_write_reg(2, 0x35, 0x0BF); /* ACF_STAGE3_A2 */
406 apb_write_reg(2, 0x36, 0x321); /* ACF_STAGE3_B1 */
407 apb_write_reg(2, 0x37, 0x008); /* ACF_STAGE3_GAIN */
408 apb_write_reg(2, 0x38, 0x2C9); /* ACF_STAGE4_A1 */
409 apb_write_reg(2, 0x39, 0x0E3); /* ACF_STAGE4_A2 */
410 apb_write_reg(2, 0x3a, 0x2EE); /* ACF_STAGE4_B1 */
411 apb_write_reg(2, 0x3b, 0x058); /* ACF_STAGE4_GAIN */
412 apb_write_reg(2, 0x3c, 0x2C3); /* ACF_STAGE5_A1 */
413 apb_write_reg(2, 0x3d, 0x0F8); /* ACF_STAGE5_A2 */
414 apb_write_reg(2, 0x3e, 0x2DD); /* ACF_STAGE5_B1 */
415 apb_write_reg(2, 0x3f, 0x04D); /* ACF_STAGE5_GAIN */
416
417 apb_write_reg(2, 0xfe, 0x000);
418 apb_write_reg(2, 0xff, 0x003ef7ff);
419 apb_write_reg(2, 0xfe, 0x001);
420 apb_write_reg(2, 0xff, 0x003d37c0);
421 apb_write_reg(2, 0xfe, 0x002);
422 apb_write_reg(2, 0xff, 0x003c3f94);
423 apb_write_reg(2, 0xfe, 0x003);
424 apb_write_reg(2, 0xff, 0x003b0f78);
425 apb_write_reg(2, 0xfe, 0x004);
426 apb_write_reg(2, 0xff, 0x0038c73f);
427 apb_write_reg(2, 0xfe, 0x005);
428 apb_write_reg(2, 0xff, 0x00369ef1);
429 apb_write_reg(2, 0xfe, 0x006);
430 apb_write_reg(2, 0xff, 0x003576be);
431 apb_write_reg(2, 0xfe, 0x007);
432 apb_write_reg(2, 0xff, 0x0033b698);
433 apb_write_reg(2, 0xfe, 0x008);
434 apb_write_reg(2, 0xff, 0x0031164d);
435 apb_write_reg(2, 0xfe, 0x009);
436 apb_write_reg(2, 0xff, 0x002f1dfd);
437 apb_write_reg(2, 0xfe, 0x00a);
438 apb_write_reg(2, 0xff, 0x002de5cf);
439 apb_write_reg(2, 0xfe, 0x00b);
440 apb_write_reg(2, 0xff, 0x002c15a2);
441 apb_write_reg(2, 0xfe, 0x00c);
442 apb_write_reg(2, 0xff, 0x0029f560);
443 apb_write_reg(2, 0xfe, 0x00d);
444 apb_write_reg(2, 0xff, 0x0027bd1b);
445 apb_write_reg(2, 0xfe, 0x00e);
446 apb_write_reg(2, 0xff, 0x00252ccf);
447 apb_write_reg(2, 0xfe, 0x00f);
448 apb_write_reg(2, 0xff, 0x0022bc7c);
449 apb_write_reg(2, 0xfe, 0x010);
450 apb_write_reg(2, 0xff, 0x00207c34);
451 apb_write_reg(2, 0xfe, 0x011);
452 apb_write_reg(2, 0xff, 0x001da3e5);
453 apb_write_reg(2, 0xfe, 0x012);
454 apb_write_reg(2, 0xff, 0x001a9b83);
455 apb_write_reg(2, 0xfe, 0x013);
456 apb_write_reg(2, 0xff, 0x0017db27);
457 apb_write_reg(2, 0xfe, 0x014);
458 apb_write_reg(2, 0xff, 0x001432c6);
459 apb_write_reg(2, 0xfe, 0x015);
460 apb_write_reg(2, 0xff, 0x000fa23e);
461 apb_write_reg(2, 0xfe, 0x016);
462 apb_write_reg(2, 0xff, 0x000b91af);
463 apb_write_reg(2, 0xfe, 0x017);
464 apb_write_reg(2, 0xff, 0x00077136);
465 apb_write_reg(2, 0xfe, 0x018);
466 apb_write_reg(2, 0xff, 0x0002c090);
467 apb_write_reg(2, 0xfe, 0x019);
468 apb_write_reg(2, 0xff, 0x003ec01a);
469 apb_write_reg(2, 0xfe, 0x01a);
470 apb_write_reg(2, 0xff, 0x003a3f92);
471 apb_write_reg(2, 0xfe, 0x01b);
472 apb_write_reg(2, 0xff, 0x00354efa);
473 apb_write_reg(2, 0xfe, 0x01c);
474 apb_write_reg(2, 0xff, 0x002fee54);
475 apb_write_reg(2, 0xfe, 0x01d);
476 apb_write_reg(2, 0xff, 0x002a35a3);
477 apb_write_reg(2, 0xfe, 0x01e);
478 apb_write_reg(2, 0xff, 0x0023f4e4);
479 apb_write_reg(2, 0xfe, 0x01f);
480 apb_write_reg(2, 0xff, 0x001cdc12);
481 apb_write_reg(2, 0xfe, 0x020);
482 apb_write_reg(2, 0xff, 0x00000316);
483 } else if (bandwidth == 1) {
484 apb_write_reg(2, 0x2c, 0x2C2); /* ACF_STAGE1_A1 */
485 apb_write_reg(2, 0x2d, 0x069); /* ACF_STAGE1_A2 */
486 apb_write_reg(2, 0x2e, 0x134); /* ACF_STAGE1_B1 */
487 apb_write_reg(2, 0x2f, 0x00E); /* ACF_STAGE1_GAIN */
488 apb_write_reg(2, 0x30, 0x2B7); /* ACF_STAGE2_A1 */
489 apb_write_reg(2, 0x31, 0x095); /* ACF_STAGE2_A2 */
490 apb_write_reg(2, 0x32, 0x36F); /* ACF_STAGE2_B1 */
491 apb_write_reg(2, 0x33, 0x06D); /* ACF_STAGE2_GAIN */
492 apb_write_reg(2, 0x34, 0x2AA); /* ACF_STAGE3_A1 */
493 apb_write_reg(2, 0x35, 0x0C6); /* ACF_STAGE3_A2 */
494 apb_write_reg(2, 0x36, 0x2E5); /* ACF_STAGE3_B1 */
495 apb_write_reg(2, 0x37, 0x008); /* ACF_STAGE3_GAIN */
496 apb_write_reg(2, 0x38, 0x2A1); /* ACF_STAGE4_A1 */
497 apb_write_reg(2, 0x39, 0x0E6); /* ACF_STAGE4_A2 */
498 apb_write_reg(2, 0x3a, 0x2BA); /* ACF_STAGE4_B1 */
499 apb_write_reg(2, 0x3b, 0x058); /* ACF_STAGE4_GAIN */
500 apb_write_reg(2, 0x3c, 0x299); /* ACF_STAGE5_A1 */
501 apb_write_reg(2, 0x3d, 0x0F9); /* ACF_STAGE5_A2 */
502 apb_write_reg(2, 0x3e, 0x2AC); /* ACF_STAGE5_B1 */
503 apb_write_reg(2, 0x3f, 0x04D); /* ACF_STAGE5_GAIN */
504
505 apb_write_reg(2, 0xfe, 0x000);
506 apb_write_reg(2, 0xff, 0x003ee7ff);
507 apb_write_reg(2, 0xfe, 0x001);
508 apb_write_reg(2, 0xff, 0x003d1fbc);
509 apb_write_reg(2, 0xfe, 0x002);
510 apb_write_reg(2, 0xff, 0x003bf790);
511 apb_write_reg(2, 0xfe, 0x003);
512 apb_write_reg(2, 0xff, 0x003a876a);
513 apb_write_reg(2, 0xfe, 0x004);
514 apb_write_reg(2, 0xff, 0x00388f31);
515 apb_write_reg(2, 0xfe, 0x005);
516 apb_write_reg(2, 0xff, 0x0036c6f3);
517 apb_write_reg(2, 0xfe, 0x006);
518 apb_write_reg(2, 0xff, 0x003536bf);
519 apb_write_reg(2, 0xfe, 0x007);
520 apb_write_reg(2, 0xff, 0x00334689);
521 apb_write_reg(2, 0xfe, 0x008);
522 apb_write_reg(2, 0xff, 0x00310644);
523 apb_write_reg(2, 0xfe, 0x009);
524 apb_write_reg(2, 0xff, 0x002ef5fd);
525 apb_write_reg(2, 0xfe, 0x00a);
526 apb_write_reg(2, 0xff, 0x002d45c2);
527 apb_write_reg(2, 0xfe, 0x00b);
528 apb_write_reg(2, 0xff, 0x002b7d8c);
529 apb_write_reg(2, 0xfe, 0x00c);
530 apb_write_reg(2, 0xff, 0x00298550);
531 apb_write_reg(2, 0xfe, 0x00d);
532 apb_write_reg(2, 0xff, 0x00278510);
533 apb_write_reg(2, 0xfe, 0x00e);
534 apb_write_reg(2, 0xff, 0x00252ccc);
535 apb_write_reg(2, 0xfe, 0x00f);
536 apb_write_reg(2, 0xff, 0x0022847c);
537 apb_write_reg(2, 0xfe, 0x010);
538 apb_write_reg(2, 0xff, 0x00201427);
539 apb_write_reg(2, 0xfe, 0x011);
540 apb_write_reg(2, 0xff, 0x001e03e0);
541 apb_write_reg(2, 0xfe, 0x012);
542 apb_write_reg(2, 0xff, 0x001b6b9b);
543 apb_write_reg(2, 0xfe, 0x013);
544 apb_write_reg(2, 0xff, 0x0017c336);
545 apb_write_reg(2, 0xfe, 0x014);
546 apb_write_reg(2, 0xff, 0x0013e2b8);
547 apb_write_reg(2, 0xfe, 0x015);
548 apb_write_reg(2, 0xff, 0x0010b246);
549 apb_write_reg(2, 0xfe, 0x016);
550 apb_write_reg(2, 0xff, 0x000d81e8);
551 apb_write_reg(2, 0xfe, 0x017);
552 apb_write_reg(2, 0xff, 0x00084966);
553 apb_write_reg(2, 0xfe, 0x018);
554 apb_write_reg(2, 0xff, 0x0003089c);
555 apb_write_reg(2, 0xfe, 0x019);
556 apb_write_reg(2, 0xff, 0x003f0022);
557 apb_write_reg(2, 0xfe, 0x01a);
558 apb_write_reg(2, 0xff, 0x003aaf9c);
559 apb_write_reg(2, 0xfe, 0x01b);
560 apb_write_reg(2, 0xff, 0x00360f0c);
561 apb_write_reg(2, 0xfe, 0x01c);
562 apb_write_reg(2, 0xff, 0x00312e74);
563 apb_write_reg(2, 0xfe, 0x01d);
564 apb_write_reg(2, 0xff, 0x002c05d3);
565 apb_write_reg(2, 0xfe, 0x01e);
566 apb_write_reg(2, 0xff, 0x00268d2a);
567 apb_write_reg(2, 0xfe, 0x01f);
568 apb_write_reg(2, 0xff, 0x0020bc76);
569 apb_write_reg(2, 0xfe, 0x020);
570 apb_write_reg(2, 0xff, 0x000003b3);
571 } else if (bandwidth == 2) {
572 /* 6MHz */
573 apb_write_reg(2, 0x2c, 0x2A9); /* ACF_STAGE1_A1 */
574 apb_write_reg(2, 0x2d, 0x078); /* ACF_STAGE1_A2 */
575 apb_write_reg(2, 0x2e, 0x0F4); /* ACF_STAGE1_B1 */
576 apb_write_reg(2, 0x2f, 0x01E); /* ACF_STAGE1_GAIN */
577 apb_write_reg(2, 0x30, 0x299); /* ACF_STAGE2_A1 */
578 apb_write_reg(2, 0x31, 0x0A1); /* ACF_STAGE2_A2 */
579 apb_write_reg(2, 0x32, 0x321); /* ACF_STAGE2_B1 */
580 apb_write_reg(2, 0x33, 0x078); /* ACF_STAGE2_GAIN */
581 apb_write_reg(2, 0x34, 0x288); /* ACF_STAGE3_A1 */
582 apb_write_reg(2, 0x35, 0x0CD); /* ACF_STAGE3_A2 */
583 apb_write_reg(2, 0x36, 0x2AE); /* ACF_STAGE3_B1 */
584 apb_write_reg(2, 0x37, 0x05F); /* ACF_STAGE3_GAIN */
585 apb_write_reg(2, 0x38, 0x27C); /* ACF_STAGE4_A1 */
586 apb_write_reg(2, 0x39, 0x0E9); /* ACF_STAGE4_A2 */
587 apb_write_reg(2, 0x3a, 0x28B); /* ACF_STAGE4_B1 */
588 apb_write_reg(2, 0x3b, 0x058); /* ACF_STAGE4_GAIN */
589 apb_write_reg(2, 0x3c, 0x273); /* ACF_STAGE5_A1 */
590 apb_write_reg(2, 0x3d, 0x0FA); /* ACF_STAGE5_A2 */
591 apb_write_reg(2, 0x3e, 0x281); /* ACF_STAGE5_B1 */
592 apb_write_reg(2, 0x3f, 0x04D); /* ACF_STAGE5_GAIN */
593
594 apb_write_reg(2, 0xfe, 0x000);
595 apb_write_reg(2, 0xff, 0x003f17ff);
596 apb_write_reg(2, 0xfe, 0x001);
597 apb_write_reg(2, 0xff, 0x003d3fc4);
598 apb_write_reg(2, 0xfe, 0x002);
599 apb_write_reg(2, 0xff, 0x003b7f8a);
600 apb_write_reg(2, 0xfe, 0x003);
601 apb_write_reg(2, 0xff, 0x0039df55);
602 apb_write_reg(2, 0xfe, 0x004);
603 apb_write_reg(2, 0xff, 0x00381720);
604 apb_write_reg(2, 0xfe, 0x005);
605 apb_write_reg(2, 0xff, 0x00360ee2);
606 apb_write_reg(2, 0xfe, 0x006);
607 apb_write_reg(2, 0xff, 0x00342ea1);
608 apb_write_reg(2, 0xfe, 0x007);
609 apb_write_reg(2, 0xff, 0x0032ee6e);
610 apb_write_reg(2, 0xfe, 0x008);
611 apb_write_reg(2, 0xff, 0x0031e64e);
612 apb_write_reg(2, 0xfe, 0x009);
613 apb_write_reg(2, 0xff, 0x00300e22);
614 apb_write_reg(2, 0xfe, 0x00a);
615 apb_write_reg(2, 0xff, 0x002daddc);
616 apb_write_reg(2, 0xfe, 0x00b);
617 apb_write_reg(2, 0xff, 0x002b758f);
618 apb_write_reg(2, 0xfe, 0x00c);
619 apb_write_reg(2, 0xff, 0x0029ad51);
620 apb_write_reg(2, 0xfe, 0x00d);
621 apb_write_reg(2, 0xff, 0x0027ad18);
622 apb_write_reg(2, 0xfe, 0x00e);
623 apb_write_reg(2, 0xff, 0x00250ccd);
624 apb_write_reg(2, 0xfe, 0x00f);
625 apb_write_reg(2, 0xff, 0x00227476);
626 apb_write_reg(2, 0xfe, 0x010);
627 apb_write_reg(2, 0xff, 0x00204c2a);
628 apb_write_reg(2, 0xfe, 0x011);
629 apb_write_reg(2, 0xff, 0x001de3e6);
630 apb_write_reg(2, 0xfe, 0x012);
631 apb_write_reg(2, 0xff, 0x001a838a);
632 apb_write_reg(2, 0xfe, 0x013);
633 apb_write_reg(2, 0xff, 0x0016ab12);
634 apb_write_reg(2, 0xfe, 0x014);
635 apb_write_reg(2, 0xff, 0x00137a9d);
636 apb_write_reg(2, 0xfe, 0x015);
637 apb_write_reg(2, 0xff, 0x00113a4a);
638 apb_write_reg(2, 0xfe, 0x016);
639 apb_write_reg(2, 0xff, 0x000db1f8);
640 apb_write_reg(2, 0xfe, 0x017);
641 apb_write_reg(2, 0xff, 0x0007c15f);
642 apb_write_reg(2, 0xfe, 0x018);
643 apb_write_reg(2, 0xff, 0x00022883);
644 apb_write_reg(2, 0xfe, 0x019);
645 apb_write_reg(2, 0xff, 0x003df803);
646 apb_write_reg(2, 0xfe, 0x01a);
647 apb_write_reg(2, 0xff, 0x00398f79);
648 apb_write_reg(2, 0xfe, 0x01b);
649 apb_write_reg(2, 0xff, 0x0034d6e6);
650 apb_write_reg(2, 0xfe, 0x01c);
651 apb_write_reg(2, 0xff, 0x002fd64b);
652 apb_write_reg(2, 0xfe, 0x01d);
653 apb_write_reg(2, 0xff, 0x002a8da7);
654 apb_write_reg(2, 0xfe, 0x01e);
655 apb_write_reg(2, 0xff, 0x002504fa);
656 apb_write_reg(2, 0xfe, 0x01f);
657 apb_write_reg(2, 0xff, 0x001f2443);
658 apb_write_reg(2, 0xfe, 0x020);
659 apb_write_reg(2, 0xff, 0x00000382);
660 } else {
661 apb_write_reg(2, 0x2c, 0x28F); /* ACF_STAGE1_A1 */
662 apb_write_reg(2, 0x2d, 0x088); /* ACF_STAGE1_A2 */
663 apb_write_reg(2, 0x2e, 0x09E); /* ACF_STAGE1_B1 */
664 apb_write_reg(2, 0x2f, 0x01E); /* ACF_STAGE1_GAIN */
665 apb_write_reg(2, 0x30, 0x27C); /* ACF_STAGE2_A1 */
666 apb_write_reg(2, 0x31, 0x0AD); /* ACF_STAGE2_A2 */
667 apb_write_reg(2, 0x32, 0x2D6); /* ACF_STAGE2_B1 */
668 apb_write_reg(2, 0x33, 0x078); /* ACF_STAGE2_GAIN */
669 apb_write_reg(2, 0x34, 0x268); /* ACF_STAGE3_A1 */
670 apb_write_reg(2, 0x35, 0x0D4); /* ACF_STAGE3_A2 */
671 apb_write_reg(2, 0x36, 0x27C); /* ACF_STAGE3_B1 */
672 apb_write_reg(2, 0x37, 0x05F); /* ACF_STAGE3_GAIN */
673 apb_write_reg(2, 0x38, 0x25B); /* ACF_STAGE4_A1 */
674 apb_write_reg(2, 0x39, 0x0ED); /* ACF_STAGE4_A2 */
675 apb_write_reg(2, 0x3a, 0x262); /* ACF_STAGE4_B1 */
676 apb_write_reg(2, 0x3b, 0x058); /* ACF_STAGE4_GAIN */
677 apb_write_reg(2, 0x3c, 0x252); /* ACF_STAGE5_A1 */
678 apb_write_reg(2, 0x3d, 0x0FB); /* ACF_STAGE5_A2 */
679 apb_write_reg(2, 0x3e, 0x25A); /* ACF_STAGE5_B1 */
680 apb_write_reg(2, 0x3f, 0x04D); /* ACF_STAGE5_GAIN */
681
682 apb_write_reg(2, 0xfe, 0x000);
683 apb_write_reg(2, 0xff, 0x003f17ff);
684 apb_write_reg(2, 0xfe, 0x001);
685 apb_write_reg(2, 0xff, 0x003d4fc5);
686 apb_write_reg(2, 0xfe, 0x002);
687 apb_write_reg(2, 0xff, 0x003baf8e);
688 apb_write_reg(2, 0xfe, 0x003);
689 apb_write_reg(2, 0xff, 0x003a3f5d);
690 apb_write_reg(2, 0xfe, 0x004);
691 apb_write_reg(2, 0xff, 0x0038df32);
692 apb_write_reg(2, 0xfe, 0x005);
693 apb_write_reg(2, 0xff, 0x00374703);
694 apb_write_reg(2, 0xfe, 0x006);
695 apb_write_reg(2, 0xff, 0x00354ec9);
696 apb_write_reg(2, 0xfe, 0x007);
697 apb_write_reg(2, 0xff, 0x00333e88);
698 apb_write_reg(2, 0xfe, 0x008);
699 apb_write_reg(2, 0xff, 0x00314e47);
700 apb_write_reg(2, 0xfe, 0x009);
701 apb_write_reg(2, 0xff, 0x002f860c);
702 apb_write_reg(2, 0xfe, 0x00a);
703 apb_write_reg(2, 0xff, 0x002d9dd2);
704 apb_write_reg(2, 0xfe, 0x00b);
705 apb_write_reg(2, 0xff, 0x002b5590);
706 apb_write_reg(2, 0xfe, 0x00c);
707 apb_write_reg(2, 0xff, 0x0028cd42);
708 apb_write_reg(2, 0xfe, 0x00d);
709 apb_write_reg(2, 0xff, 0x00266cf2);
710 apb_write_reg(2, 0xfe, 0x00e);
711 apb_write_reg(2, 0xff, 0x00245cab);
712 apb_write_reg(2, 0xfe, 0x00f);
713 apb_write_reg(2, 0xff, 0x00225c6b);
714 apb_write_reg(2, 0xfe, 0x010);
715 apb_write_reg(2, 0xff, 0x00200427);
716 apb_write_reg(2, 0xfe, 0x011);
717 apb_write_reg(2, 0xff, 0x001d4bd5);
718 apb_write_reg(2, 0xfe, 0x012);
719 apb_write_reg(2, 0xff, 0x001a9b7d);
720 apb_write_reg(2, 0xfe, 0x013);
721 apb_write_reg(2, 0xff, 0x00183b2b);
722 apb_write_reg(2, 0xfe, 0x014);
723 apb_write_reg(2, 0xff, 0x0015b2e1);
724 apb_write_reg(2, 0xfe, 0x015);
725 apb_write_reg(2, 0xff, 0x00122a83);
726 apb_write_reg(2, 0xfe, 0x016);
727 apb_write_reg(2, 0xff, 0x000d49fc);
728 apb_write_reg(2, 0xfe, 0x017);
729 apb_write_reg(2, 0xff, 0x0007594e);
730 apb_write_reg(2, 0xfe, 0x018);
731 apb_write_reg(2, 0xff, 0x00024080);
732 apb_write_reg(2, 0xfe, 0x019);
733 apb_write_reg(2, 0xff, 0x003e980e);
734 apb_write_reg(2, 0xfe, 0x01a);
735 apb_write_reg(2, 0xff, 0x003ab796);
736 apb_write_reg(2, 0xfe, 0x01b);
737 apb_write_reg(2, 0xff, 0x00368f15);
738 apb_write_reg(2, 0xfe, 0x01c);
739 apb_write_reg(2, 0xff, 0x00320e8a);
740 apb_write_reg(2, 0xfe, 0x01d);
741 apb_write_reg(2, 0xff, 0x002d25f4);
742 apb_write_reg(2, 0xfe, 0x01e);
743 apb_write_reg(2, 0xff, 0x0027ad4f);
744 apb_write_reg(2, 0xfe, 0x01f);
745 apb_write_reg(2, 0xff, 0x00219496);
746 apb_write_reg(2, 0xfe, 0x020);
747 apb_write_reg(2, 0xff, 0x000003c9);
748 }
749 } else {
750 /* 20.7 MHz Set ACF */
751 if (bandwidth == 0) {
752 /*8M Hz */
753 apb_write_reg(2, 0x2c, 0x318); /* ACF_STAGE1_A1 */
754 apb_write_reg(2, 0x2d, 0x03E); /* ACF_STAGE1_A2 */
755 apb_write_reg(2, 0x2e, 0x1AE); /* ACF_STAGE1_B1 */
756 apb_write_reg(2, 0x2f, 0x00E); /* ACF_STAGE1_GAIN */
757 apb_write_reg(2, 0x30, 0x326); /* ACF_STAGE2_A1 */
758 apb_write_reg(2, 0x31, 0x074); /* ACF_STAGE2_A2 */
759 apb_write_reg(2, 0x32, 0x074); /* ACF_STAGE2_B1 */
760 apb_write_reg(2, 0x33, 0x06F); /* ACF_STAGE2_GAIN */
761 apb_write_reg(2, 0x34, 0x336); /* ACF_STAGE3_A1 */
762 apb_write_reg(2, 0x35, 0x0B1); /* ACF_STAGE3_A2 */
763 apb_write_reg(2, 0x36, 0x3C9); /* ACF_STAGE3_B1 */
764 apb_write_reg(2, 0x37, 0x008); /* ACF_STAGE3_GAIN */
765 apb_write_reg(2, 0x38, 0x33F); /* ACF_STAGE4_A1 */
766 apb_write_reg(2, 0x39, 0x0DC); /* ACF_STAGE4_A2 */
767 apb_write_reg(2, 0x3a, 0x384); /* ACF_STAGE4_B1 */
768 apb_write_reg(2, 0x3b, 0x05A); /* ACF_STAGE4_GAIN */
769 apb_write_reg(2, 0x3c, 0x340); /* ACF_STAGE5_A1 */
770 apb_write_reg(2, 0x3d, 0x0F6); /* ACF_STAGE5_A2 */
771 apb_write_reg(2, 0x3e, 0x36D); /* ACF_STAGE5_B1 */
772 apb_write_reg(2, 0x3f, 0x04B); /* ACF_STAGE5_GAIN */
773
774 apb_write_reg(2, 0xfe, 0x000);
775 apb_write_reg(2, 0xff, 0x003f37ff);
776 apb_write_reg(2, 0xfe, 0x001);
777 apb_write_reg(2, 0xff, 0x003d97cc);
778 apb_write_reg(2, 0xfe, 0x002);
779 apb_write_reg(2, 0xff, 0x003bf798);
780 apb_write_reg(2, 0xfe, 0x003);
781 apb_write_reg(2, 0xff, 0x003a4f64);
782 apb_write_reg(2, 0xfe, 0x004);
783 apb_write_reg(2, 0xff, 0x0038a72f);
784 apb_write_reg(2, 0xfe, 0x005);
785 apb_write_reg(2, 0xff, 0x0036f6f9);
786 apb_write_reg(2, 0xfe, 0x006);
787 apb_write_reg(2, 0xff, 0x003546c3);
788 apb_write_reg(2, 0xfe, 0x007);
789 apb_write_reg(2, 0xff, 0x0033868c);
790 apb_write_reg(2, 0xfe, 0x008);
791 apb_write_reg(2, 0xff, 0x0031be54);
792 apb_write_reg(2, 0xfe, 0x009);
793 apb_write_reg(2, 0xff, 0x002fe61a);
794 apb_write_reg(2, 0xfe, 0x00a);
795 apb_write_reg(2, 0xff, 0x002e05df);
796 apb_write_reg(2, 0xfe, 0x00b);
797 apb_write_reg(2, 0xff, 0x002c15a2);
798 apb_write_reg(2, 0xfe, 0x00c);
799 apb_write_reg(2, 0xff, 0x002a1562);
800 apb_write_reg(2, 0xfe, 0x00d);
801 apb_write_reg(2, 0xff, 0x0027f520);
802 apb_write_reg(2, 0xfe, 0x00e);
803 apb_write_reg(2, 0xff, 0x0025c4dc);
804 apb_write_reg(2, 0xfe, 0x00f);
805 apb_write_reg(2, 0xff, 0x00236c93);
806 apb_write_reg(2, 0xfe, 0x010);
807 apb_write_reg(2, 0xff, 0x0020f446);
808 apb_write_reg(2, 0xfe, 0x011);
809 apb_write_reg(2, 0xff, 0x001e4bf4);
810 apb_write_reg(2, 0xfe, 0x012);
811 apb_write_reg(2, 0xff, 0x001b739d);
812 apb_write_reg(2, 0xfe, 0x013);
813 apb_write_reg(2, 0xff, 0x00185b3d);
814 apb_write_reg(2, 0xfe, 0x014);
815 apb_write_reg(2, 0xff, 0x0014ead5);
816 apb_write_reg(2, 0xfe, 0x015);
817 apb_write_reg(2, 0xff, 0x00111a62);
818 apb_write_reg(2, 0xfe, 0x016);
819 apb_write_reg(2, 0xff, 0x000cb9df);
820 apb_write_reg(2, 0xfe, 0x017);
821 apb_write_reg(2, 0xff, 0x00079148);
822 apb_write_reg(2, 0xfe, 0x018);
823 apb_write_reg(2, 0xff, 0x00030093);
824 apb_write_reg(2, 0xfe, 0x019);
825 apb_write_reg(2, 0xff, 0x003f802a);
826 apb_write_reg(2, 0xfe, 0x01a);
827 apb_write_reg(2, 0xff, 0x003b77b2);
828 apb_write_reg(2, 0xfe, 0x01b);
829 apb_write_reg(2, 0xff, 0x0036a725);
830 apb_write_reg(2, 0xfe, 0x01c);
831 apb_write_reg(2, 0xff, 0x0030ae7b);
832 apb_write_reg(2, 0xfe, 0x01d);
833 apb_write_reg(2, 0xff, 0x00285d9f);
834 apb_write_reg(2, 0xfe, 0x01e);
835 apb_write_reg(2, 0xff, 0x001abc46);
836 apb_write_reg(2, 0xfe, 0x01f);
837 apb_write_reg(2, 0xff, 0x000f8a85);
838 apb_write_reg(2, 0xfe, 0x020);
839 apb_write_reg(2, 0xff, 0x00000187);
840 } else if (bandwidth == 1) {
841 apb_write_reg(2, 0x2c, 0x2F9); /* ACF_STAGE1_A1 */
842 apb_write_reg(2, 0x2d, 0x04C); /* ACF_STAGE1_A2 */
843 apb_write_reg(2, 0x2e, 0x18E); /* ACF_STAGE1_B1 */
844 apb_write_reg(2, 0x2f, 0x00E); /* ACF_STAGE1_GAIN */
845 apb_write_reg(2, 0x30, 0x2FD); /* ACF_STAGE2_A1 */
846 apb_write_reg(2, 0x31, 0x07F); /* ACF_STAGE2_A2 */
847 apb_write_reg(2, 0x32, 0x01A); /* ACF_STAGE2_B1 */
848 apb_write_reg(2, 0x33, 0x06D); /* ACF_STAGE2_GAIN */
849 apb_write_reg(2, 0x34, 0x300); /* ACF_STAGE3_A1 */
850 apb_write_reg(2, 0x35, 0x0B8); /* ACF_STAGE3_A2 */
851 apb_write_reg(2, 0x36, 0x372); /* ACF_STAGE3_B1 */
852 apb_write_reg(2, 0x37, 0x05F); /* ACF_STAGE3_GAIN */
853 apb_write_reg(2, 0x38, 0x301); /* ACF_STAGE4_A1 */
854 apb_write_reg(2, 0x39, 0x0DF); /* ACF_STAGE4_A2 */
855 apb_write_reg(2, 0x3a, 0x335); /* ACF_STAGE4_B1 */
856 apb_write_reg(2, 0x3b, 0x05A); /* ACF_STAGE4_GAIN */
857 apb_write_reg(2, 0x3c, 0x2FE); /* ACF_STAGE5_A1 */
858 apb_write_reg(2, 0x3d, 0x0F7); /* ACF_STAGE5_A2 */
859 apb_write_reg(2, 0x3e, 0x320); /* ACF_STAGE5_B1 */
860 apb_write_reg(2, 0x3f, 0x04B); /* ACF_STAGE5_GAIN */
861
862 apb_write_reg(2, 0xfe, 0x000);
863 apb_write_reg(2, 0xff, 0x003f37ff);
864 apb_write_reg(2, 0xfe, 0x001);
865 apb_write_reg(2, 0xff, 0x003d8fcc);
866 apb_write_reg(2, 0xfe, 0x002);
867 apb_write_reg(2, 0xff, 0x003bef97);
868 apb_write_reg(2, 0xfe, 0x003);
869 apb_write_reg(2, 0xff, 0x003a4762);
870 apb_write_reg(2, 0xfe, 0x004);
871 apb_write_reg(2, 0xff, 0x0038972d);
872 apb_write_reg(2, 0xfe, 0x005);
873 apb_write_reg(2, 0xff, 0x0036e6f7);
874 apb_write_reg(2, 0xfe, 0x006);
875 apb_write_reg(2, 0xff, 0x00352ec1);
876 apb_write_reg(2, 0xfe, 0x007);
877 apb_write_reg(2, 0xff, 0x00336e89);
878 apb_write_reg(2, 0xfe, 0x008);
879 apb_write_reg(2, 0xff, 0x00319e50);
880 apb_write_reg(2, 0xfe, 0x009);
881 apb_write_reg(2, 0xff, 0x002fce16);
882 apb_write_reg(2, 0xfe, 0x00a);
883 apb_write_reg(2, 0xff, 0x002de5db);
884 apb_write_reg(2, 0xfe, 0x00b);
885 apb_write_reg(2, 0xff, 0x002bf59d);
886 apb_write_reg(2, 0xfe, 0x00c);
887 apb_write_reg(2, 0xff, 0x0029ed5e);
888 apb_write_reg(2, 0xfe, 0x00d);
889 apb_write_reg(2, 0xff, 0x0027d51c);
890 apb_write_reg(2, 0xfe, 0x00e);
891 apb_write_reg(2, 0xff, 0x00259cd7);
892 apb_write_reg(2, 0xfe, 0x00f);
893 apb_write_reg(2, 0xff, 0x0023448e);
894 apb_write_reg(2, 0xfe, 0x010);
895 apb_write_reg(2, 0xff, 0x0020cc41);
896 apb_write_reg(2, 0xfe, 0x011);
897 apb_write_reg(2, 0xff, 0x001e23ef);
898 apb_write_reg(2, 0xfe, 0x012);
899 apb_write_reg(2, 0xff, 0x001b4b98);
900 apb_write_reg(2, 0xfe, 0x013);
901 apb_write_reg(2, 0xff, 0x00183339);
902 apb_write_reg(2, 0xfe, 0x014);
903 apb_write_reg(2, 0xff, 0x0014cad1);
904 apb_write_reg(2, 0xfe, 0x015);
905 apb_write_reg(2, 0xff, 0x0010fa5e);
906 apb_write_reg(2, 0xfe, 0x016);
907 apb_write_reg(2, 0xff, 0x000c99dc);
908 apb_write_reg(2, 0xfe, 0x017);
909 apb_write_reg(2, 0xff, 0x00078145);
910 apb_write_reg(2, 0xfe, 0x018);
911 apb_write_reg(2, 0xff, 0x0002f892);
912 apb_write_reg(2, 0xfe, 0x019);
913 apb_write_reg(2, 0xff, 0x003f802a);
914 apb_write_reg(2, 0xfe, 0x01a);
915 apb_write_reg(2, 0xff, 0x003b8fb3);
916 apb_write_reg(2, 0xfe, 0x01b);
917 apb_write_reg(2, 0xff, 0x0036d729);
918 apb_write_reg(2, 0xfe, 0x01c);
919 apb_write_reg(2, 0xff, 0x00310682);
920 apb_write_reg(2, 0xfe, 0x01d);
921 apb_write_reg(2, 0xff, 0x00290dae);
922 apb_write_reg(2, 0xfe, 0x01e);
923 apb_write_reg(2, 0xff, 0x001c0c67);
924 apb_write_reg(2, 0xfe, 0x01f);
925 apb_write_reg(2, 0xff, 0x0010a2ad);
926 apb_write_reg(2, 0xfe, 0x020);
927 apb_write_reg(2, 0xff, 0x000001a8);
928 } else if (bandwidth == 2) {
929 /* 6MHz */
930 apb_write_reg(2, 0x2c, 0x2D9); /* ACF_STAGE1_A1 */
931 apb_write_reg(2, 0x2d, 0x05C); /* ACF_STAGE1_A2 */
932 apb_write_reg(2, 0x2e, 0x161); /* ACF_STAGE1_B1 */
933 apb_write_reg(2, 0x2f, 0x00E); /* ACF_STAGE1_GAIN */
934 apb_write_reg(2, 0x30, 0x2D4); /* ACF_STAGE2_A1 */
935 apb_write_reg(2, 0x31, 0x08B); /* ACF_STAGE2_A2 */
936 apb_write_reg(2, 0x32, 0x3B8); /* ACF_STAGE2_B1 */
937 apb_write_reg(2, 0x33, 0x06B); /* ACF_STAGE2_GAIN */
938 apb_write_reg(2, 0x34, 0x2CD); /* ACF_STAGE3_A1 */
939 apb_write_reg(2, 0x35, 0x0C0); /* ACF_STAGE3_A2 */
940 apb_write_reg(2, 0x36, 0x31E); /* ACF_STAGE3_B1 */
941 apb_write_reg(2, 0x37, 0x05F); /* ACF_STAGE3_GAIN */
942 apb_write_reg(2, 0x38, 0x2C7); /* ACF_STAGE4_A1 */
943 apb_write_reg(2, 0x39, 0x0E3); /* ACF_STAGE4_A2 */
944 apb_write_reg(2, 0x3a, 0x2EB); /* ACF_STAGE4_B1 */
945 apb_write_reg(2, 0x3b, 0x05A); /* ACF_STAGE4_GAIN */
946 apb_write_reg(2, 0x3c, 0x2C1); /* ACF_STAGE5_A1 */
947 apb_write_reg(2, 0x3d, 0x0F8); /* ACF_STAGE5_A2 */
948 apb_write_reg(2, 0x3e, 0x2DA); /* ACF_STAGE5_B1 */
949 apb_write_reg(2, 0x3f, 0x04B); /* ACF_STAGE5_GAIN */
950 apb_write_reg(2, 0xfe, 0x000);
951 apb_write_reg(2, 0xff, 0x003f2fff);
952 apb_write_reg(2, 0xfe, 0x001);
953 apb_write_reg(2, 0xff, 0x003d87cb);
954 apb_write_reg(2, 0xfe, 0x002);
955 apb_write_reg(2, 0xff, 0x003bdf96);
956 apb_write_reg(2, 0xfe, 0x003);
957 apb_write_reg(2, 0xff, 0x003a2f60);
958 apb_write_reg(2, 0xfe, 0x004);
959 apb_write_reg(2, 0xff, 0x00387f2a);
960 apb_write_reg(2, 0xfe, 0x005);
961 apb_write_reg(2, 0xff, 0x0036c6f4);
962 apb_write_reg(2, 0xfe, 0x006);
963 apb_write_reg(2, 0xff, 0x00350ebd);
964 apb_write_reg(2, 0xfe, 0x007);
965 apb_write_reg(2, 0xff, 0x00334684);
966 apb_write_reg(2, 0xfe, 0x008);
967 apb_write_reg(2, 0xff, 0x0031764b);
968 apb_write_reg(2, 0xfe, 0x009);
969 apb_write_reg(2, 0xff, 0x002f9e11);
970 apb_write_reg(2, 0xfe, 0x00a);
971 apb_write_reg(2, 0xff, 0x002db5d4);
972 apb_write_reg(2, 0xfe, 0x00b);
973 apb_write_reg(2, 0xff, 0x002bbd97);
974 apb_write_reg(2, 0xfe, 0x00c);
975 apb_write_reg(2, 0xff, 0x0029b557);
976 apb_write_reg(2, 0xfe, 0x00d);
977 apb_write_reg(2, 0xff, 0x00279515);
978 apb_write_reg(2, 0xfe, 0x00e);
979 apb_write_reg(2, 0xff, 0x00255ccf);
980 apb_write_reg(2, 0xfe, 0x00f);
981 apb_write_reg(2, 0xff, 0x00230c87);
982 apb_write_reg(2, 0xfe, 0x010);
983 apb_write_reg(2, 0xff, 0x0020943a);
984 apb_write_reg(2, 0xfe, 0x011);
985 apb_write_reg(2, 0xff, 0x001debe8);
986 apb_write_reg(2, 0xfe, 0x012);
987 apb_write_reg(2, 0xff, 0x001b1b91);
988 apb_write_reg(2, 0xfe, 0x013);
989 apb_write_reg(2, 0xff, 0x00180b33);
990 apb_write_reg(2, 0xfe, 0x014);
991 apb_write_reg(2, 0xff, 0x0014aacc);
992 apb_write_reg(2, 0xfe, 0x015);
993 apb_write_reg(2, 0xff, 0x0010e25a);
994 apb_write_reg(2, 0xfe, 0x016);
995 apb_write_reg(2, 0xff, 0x000c91da);
996 apb_write_reg(2, 0xfe, 0x017);
997 apb_write_reg(2, 0xff, 0x00078945);
998 apb_write_reg(2, 0xfe, 0x018);
999 apb_write_reg(2, 0xff, 0x00031895);
1000 apb_write_reg(2, 0xfe, 0x019);
1001 apb_write_reg(2, 0xff, 0x003fa82e);
1002 apb_write_reg(2, 0xfe, 0x01a);
1003 apb_write_reg(2, 0xff, 0x003bbfb8);
1004 apb_write_reg(2, 0xfe, 0x01b);
1005 apb_write_reg(2, 0xff, 0x00371730);
1006 apb_write_reg(2, 0xfe, 0x01c);
1007 apb_write_reg(2, 0xff, 0x0031668c);
1008 apb_write_reg(2, 0xfe, 0x01d);
1009 apb_write_reg(2, 0xff, 0x00299dbc);
1010 apb_write_reg(2, 0xfe, 0x01e);
1011 apb_write_reg(2, 0xff, 0x001d1480);
1012 apb_write_reg(2, 0xfe, 0x01f);
1013 apb_write_reg(2, 0xff, 0x00119acf);
1014 apb_write_reg(2, 0xfe, 0x020);
1015 apb_write_reg(2, 0xff, 0x000001c4);
1016 } else {
1017 apb_write_reg(2, 0x2c, 0x2B9); /* ACF_STAGE1_A1 */
1018 apb_write_reg(2, 0x2d, 0x06E); /* ACF_STAGE1_A2 */
1019 apb_write_reg(2, 0x2e, 0x11E); /* ACF_STAGE1_B1 */
1020 apb_write_reg(2, 0x2f, 0x01E); /* ACF_STAGE1_GAIN */
1021 apb_write_reg(2, 0x30, 0x2AB); /* ACF_STAGE2_A1 */
1022 apb_write_reg(2, 0x31, 0x099); /* ACF_STAGE2_A2 */
1023 apb_write_reg(2, 0x32, 0x351); /* ACF_STAGE2_B1 */
1024 apb_write_reg(2, 0x33, 0x06B); /* ACF_STAGE2_GAIN */
1025 apb_write_reg(2, 0x34, 0x29D); /* ACF_STAGE3_A1 */
1026 apb_write_reg(2, 0x35, 0x0C8); /* ACF_STAGE3_A2 */
1027 apb_write_reg(2, 0x36, 0x2D0); /* ACF_STAGE3_B1 */
1028 apb_write_reg(2, 0x37, 0x05F); /* ACF_STAGE3_GAIN */
1029 apb_write_reg(2, 0x38, 0x292); /* ACF_STAGE4_A1 */
1030 apb_write_reg(2, 0x39, 0x0E7); /* ACF_STAGE4_A2 */
1031 apb_write_reg(2, 0x3a, 0x2A8); /* ACF_STAGE4_B1 */
1032 apb_write_reg(2, 0x3b, 0x05A); /* ACF_STAGE4_GAIN */
1033 apb_write_reg(2, 0x3c, 0x28A); /* ACF_STAGE5_A1 */
1034 apb_write_reg(2, 0x3d, 0x0F9); /* ACF_STAGE5_A2 */
1035 apb_write_reg(2, 0x3e, 0x29B); /* ACF_STAGE5_B1 */
1036 apb_write_reg(2, 0x3f, 0x04B); /* ACF_STAGE5_GAIN */
1037
1038 apb_write_reg(2, 0xfe, 0x000);
1039 apb_write_reg(2, 0xff, 0x003f2fff);
1040 apb_write_reg(2, 0xfe, 0x001);
1041 apb_write_reg(2, 0xff, 0x003d7fca);
1042 apb_write_reg(2, 0xfe, 0x002);
1043 apb_write_reg(2, 0xff, 0x003bcf94);
1044 apb_write_reg(2, 0xfe, 0x003);
1045 apb_write_reg(2, 0xff, 0x003a1f5e);
1046 apb_write_reg(2, 0xfe, 0x004);
1047 apb_write_reg(2, 0xff, 0x00386727);
1048 apb_write_reg(2, 0xfe, 0x005);
1049 apb_write_reg(2, 0xff, 0x0036a6f0);
1050 apb_write_reg(2, 0xfe, 0x006);
1051 apb_write_reg(2, 0xff, 0x0034e6b8);
1052 apb_write_reg(2, 0xfe, 0x007);
1053 apb_write_reg(2, 0xff, 0x0033167f);
1054 apb_write_reg(2, 0xfe, 0x008);
1055 apb_write_reg(2, 0xff, 0x00314645);
1056 apb_write_reg(2, 0xfe, 0x009);
1057 apb_write_reg(2, 0xff, 0x002f660a);
1058 apb_write_reg(2, 0xfe, 0x00a);
1059 apb_write_reg(2, 0xff, 0x002d75cd);
1060 apb_write_reg(2, 0xfe, 0x00b);
1061 apb_write_reg(2, 0xff, 0x002b758e);
1062 apb_write_reg(2, 0xfe, 0x00c);
1063 apb_write_reg(2, 0xff, 0x0029654e);
1064 apb_write_reg(2, 0xfe, 0x00d);
1065 apb_write_reg(2, 0xff, 0x0027450a);
1066 apb_write_reg(2, 0xfe, 0x00e);
1067 apb_write_reg(2, 0xff, 0x002504c4);
1068 apb_write_reg(2, 0xfe, 0x00f);
1069 apb_write_reg(2, 0xff, 0x0022a47b);
1070 apb_write_reg(2, 0xfe, 0x010);
1071 apb_write_reg(2, 0xff, 0x0020242d);
1072 apb_write_reg(2, 0xfe, 0x011);
1073 apb_write_reg(2, 0xff, 0x001d7bdb);
1074 apb_write_reg(2, 0xfe, 0x012);
1075 apb_write_reg(2, 0xff, 0x001aa383);
1076 apb_write_reg(2, 0xfe, 0x013);
1077 apb_write_reg(2, 0xff, 0x00178b24);
1078 apb_write_reg(2, 0xfe, 0x014);
1079 apb_write_reg(2, 0xff, 0x00142abd);
1080 apb_write_reg(2, 0xfe, 0x015);
1081 apb_write_reg(2, 0xff, 0x0010624a);
1082 apb_write_reg(2, 0xfe, 0x016);
1083 apb_write_reg(2, 0xff, 0x000c11ca);
1084 apb_write_reg(2, 0xfe, 0x017);
1085 apb_write_reg(2, 0xff, 0x00070935);
1086 apb_write_reg(2, 0xfe, 0x018);
1087 apb_write_reg(2, 0xff, 0x00029885);
1088 apb_write_reg(2, 0xfe, 0x019);
1089 apb_write_reg(2, 0xff, 0x003f281e);
1090 apb_write_reg(2, 0xfe, 0x01a);
1091 apb_write_reg(2, 0xff, 0x003b3fa9);
1092 apb_write_reg(2, 0xfe, 0x01b);
1093 apb_write_reg(2, 0xff, 0x00369720);
1094 apb_write_reg(2, 0xfe, 0x01c);
1095 apb_write_reg(2, 0xff, 0x0030ce7b);
1096 apb_write_reg(2, 0xfe, 0x01d);
1097 apb_write_reg(2, 0xff, 0x0028dda7);
1098 apb_write_reg(2, 0xfe, 0x01e);
1099 apb_write_reg(2, 0xff, 0x001c6464);
1100 apb_write_reg(2, 0xfe, 0x01f);
1101 apb_write_reg(2, 0xff, 0x0011b2c7);
1102 apb_write_reg(2, 0xfe, 0x020);
1103 apb_write_reg(2, 0xff, 0x000001cb);
1104 }
1105 }
1106}
1107
1108static void dvbt_reg_initial(struct aml_demod_sta *demod_sta)
1109{
1110 u32 clk_freq;
1111 u32 adc_freq;
1112 u8 ch_mode;
1113 u8 agc_mode;
1114 u32 ch_freq;
1115 u16 ch_if;
1116 u16 ch_bw;
1117 u16 symb_rate;
1118
1119 u8 bw;
1120 u8 sr;
1121 u8 ifreq;
1122 u32 tmp;
1123
1124 clk_freq = demod_sta->clk_freq; /* kHz */
1125 adc_freq = demod_sta->adc_freq; /* kHz */
1126 ch_mode = demod_sta->ch_mode;
1127 agc_mode = demod_sta->agc_mode;
1128 ch_freq = demod_sta->ch_freq; /* kHz */
1129 ch_if = demod_sta->ch_if; /* kHz */
1130 ch_bw = demod_sta->ch_bw; /* kHz */
1131 symb_rate = demod_sta->symb_rate; /* k/sec */
1132
1133 bw = 8 - ch_bw / 1000;
1134 sr = adc_freq > 40000 ? 3 : adc_freq > 24000 ? 2 :
1135 adc_freq > 20770 ? 1 : 0;
1136 ifreq = ch_if > 35000 ? 0 : 1;
1137
1138 /*//////////////////////////////////// */
1139 /* bw == 0 : 8M */
1140 /* 1 : 7M */
1141 /* 2 : 6M */
1142 /* 3 : 5M */
1143 /* sr == 0 : 20.7M */
1144 /* 1 : 20.8333M */
1145 /* 2 : 28.5714M */
1146 /* 3 : 45M */
1147 /* ifreq == 0: 36.13MHz */
1148 /* 1: 4.57MHz */
1149 /* agc_mode == 0: single AGC */
1150 /* 1: dual AGC */
1151 /*//////////////////////////////////// */
1152 apb_write_reg(2, 0x02, 0x00800000);
1153 /* SW reset bit[23] ; write anything to zero */
1154 apb_write_reg(2, 0x00, 0x00000000);
1155
1156 switch (sr) {
1157 case 0:
1158 apb_write_reg(2, 0x08, 0x00002966);
1159 break;
1160 case 1:
1161 apb_write_reg(2, 0x08, 0x00002999);
1162 break;
1163 case 2:
1164 apb_write_reg(2, 0x08, 0x00003924);
1165 break;
1166 case 3:
1167 apb_write_reg(2, 0x08, 0x00005a00);
1168 break; /*sample_rate /*45M */
1169 default:
1170 break;
1171 }
1172
1173 apb_write_reg(2, 0x0d, 0x00000000);
1174 apb_write_reg(2, 0x0e, 0x00000000);
1175 dvbt_enable_irq(8);
1176
1177 apb_write_reg(2, 0x11, 0x00100002); /* FSM [15:0] TIMER_FEC_LOST */
1178 apb_write_reg(2, 0x12, 0x02100201); /* FSM */
1179 apb_write_reg(2, 0x14, 0xe81c4ff6); /* AGC_TARGET 0xf0121385 */
1180 apb_write_reg(2, 0x15, 0x02050ca6); /* AGC_CTRL */
1181
1182 switch (sr) {
1183 case 0:
1184 apb_write_reg(2, 0x15, apb_read_reg(2, 0x15) | (0x5b << 12));
1185 break;
1186 case 1:
1187 apb_write_reg(2, 0x15, apb_read_reg(2, 0x15) | (0x5b << 12));
1188 break;
1189 case 2:
1190 apb_write_reg(2, 0x15, apb_read_reg(2, 0x15) | (0x7b << 12));
1191 break;
1192 case 3:
1193 apb_write_reg(2, 0x15, apb_read_reg(2, 0x15) | (0xc2 << 12));
1194 break; /* sample_rate /*45M */
1195 default:
1196 break;
1197 }
1198
1199 if (agc_mode == 0)
1200 apb_write_reg(2, 0x16, 0x67f80); /* AGC_IFGAIN_CTRL */
1201 else if (agc_mode == 1)
1202 apb_write_reg(2, 0x16, 0x07f80); /* AGC_IFGAIN_CTRL */
1203
1204 apb_write_reg(2, 0x17, 0x07f80); /* AGC_RFGAIN_CTRL */
1205 apb_write_reg(2, 0x18, 0x00000000); /* AGC_IFGAIN_ACCUM */
1206 apb_write_reg(2, 0x19, 0x00000000); /* AGC_RFGAIN_ACCUM */
1207
1208 if (ifreq == 0) {
1209 switch (sr) {
1210 case 0:
1211 apb_write_reg(2, 0x20, 0x00002096);
1212 break;
1213 /* DDC NORM_PHASE 36.13M IF For 20.7M sample rate */
1214 case 1:
1215 apb_write_reg(2, 0x20, 0x000021a9);
1216 break;
1217 /* DDC NORM_PHASE 36.13M IF For 20.8333M sample rate*/
1218 case 2:
1219 apb_write_reg(2, 0x20, 0x000021dc);
1220 break;
1221 /* DDC NORM_PHASE 36.13M IF For 28.57142M sample rate*/
1222 case 3:
1223 apb_write_reg(2, 0x20, 0x000066e2);
1224 break;
1225 /* DDC NORM_PHASE 36.13M IF For 45M sample rate */
1226 default:
1227 break;
1228 }
1229 } else if (ifreq == 1) {
1230 switch (sr) {
1231 case 0:
1232 apb_write_reg(2, 0x20, 0x00001c42);
1233 break;
1234 /* DDC NORM_PHASE 4.57M IF For 20.7M sample rate */
1235 case 1:
1236 apb_write_reg(2, 0x20, 0x00001c1f);
1237 break;
1238 /* DDC NORM_PHASE 4.57M IF For 20.8333M sample rate */
1239 case 2:
1240 apb_write_reg(2, 0x20, 0x00001479);
1241 break;
1242 /* DDC NORM_PHASE 4.57M IF For 28.57142M sample rate*/
1243 case 3:
1244 apb_write_reg(2, 0x20, 0x0000d00);
1245 break;
1246 /* DDC NORM_PHASE 4.57M IF For 45M sample rate */
1247 default:
1248 break;
1249 }
1250 }
1251 */tmp = ch_if * (1 << 15)/adc_freq;
1252 tmp &= 0x3fff;
1253 apb_write_reg(2, 0x20, tmp);
1254 if (demod_sta->debug)
1255 dprintk("IF: %d kHz ADC: %d kHz DDC: %04x\n", ch_if, adc_freq,
1256 tmp);
1257
1258 apb_write_reg(2, 0x21, 0x001ff000); /* DDC CS_FCFO_ADJ_CTRL */
1259 apb_write_reg(2, 0x22, 0x00000000); /* DDC ICFO_ADJ_CTRL */
1260 apb_write_reg(2, 0x23, 0x00004000); /* DDC TRACK_FCFO_ADJ_CTRL */
1261 apb_write_reg(2, 0x27, 0x00a98200);
1262 /*[23] agc state mode [22:19] icfo_time_limit ;[18:15] tps_time_limit ;
1263 * [14:4] cs_cfo_thres ; [3:0] fsm_state_d;
1264 */
1265 /* 1 010,1 001,1
1266 * 000,0010,0000, xxxx
1267 */
1268 apb_write_reg(2, 0x28, 0x04028032);
1269 /* [31:24] cs_Q_thres; [23:13] sfo_thres; FSM [12:0] fcfo_thres;; */
1270 /* 0000,0100, 0000,0010,100 0,0000,0011,0010 */
1271 apb_write_reg(2, 0x29, 0x0051117F);
1272 /*apb_write_reg(2, 0x29, 0x00010f7F); */
1273 /* [18:16] fec_rs_sh_ctrl ;[15:9] fsm_total_timer;
1274 * [8:6] modeDet_time_limit; FSM [5:0] sfo_time_limit; ;
1275 */
1276 /* 01, () 0000,111 1,01 11,1111 */
1277
1278 /* SRC NORM_INRATE */
1279 switch (bw) {
1280 case 0:
1281 tmp = (1 << 14) * adc_freq / 125 / 8 * 7;
1282 break;
1283 case 1:
1284 tmp = (1 << 14) * adc_freq / 125;
1285 break;
1286 case 2:
1287 tmp = (1 << 14) * adc_freq / 125 / 6 * 7;
1288 break;
1289 case 3:
1290 tmp = (1 << 14) * adc_freq / 125 / 5 * 7;
1291 break;
1292 default:
1293 tmp = (1 << 14) * adc_freq / 125 / 8 * 7;
1294 break;
1295 }
1296
1297 apb_write_reg(2, 0x44, tmp & 0x7fffff);
1298
1299 apb_write_reg(2, 0x45, 0x00000000); /* SRC SRC_PHASE_INI */
1300 apb_write_reg(2, 0x46, 0x02004000);
1301 /* SRC SFO_ADJ_CTRL SFO limit 0x100!! */
1302 apb_write_reg(2, 0x48, 0xc0287); /* DAGC_CTRL */
1303 apb_write_reg(2, 0x49, 0x00000005); /* DAGC_CTRL1 */
1304 apb_write_reg(2, 0x4c, 0x00000bbf); /* CCI_RP */
1305 apb_write_reg(2, 0x4d, 0x00000376); /* CCI_RPSQ */
1306 apb_write_reg(2, 0x4e, 0x00202109); /* CCI_CTRL */
1307 apb_write_reg(2, 0x52, 0x00000000); /* CCI_NOTCH1_A2 */
1308 apb_write_reg(2, 0x53, 0x00000000); /* CCI_NOTCH1_B1 */
1309 apb_write_reg(2, 0x54, 0x00c00000); /* CCI_NOTCH2_A1 */
1310 apb_write_reg(2, 0x55, 0x00000000); /* CCI_NOTCH2_A2 */
1311 apb_write_reg(2, 0x56, 0x00000000); /* CCI_NOTCH2_B1 */
1312 apb_write_reg(2, 0x57, 0x00000000); /* CCI_NOTCH2_B1 */
1313 apb_write_reg(2, 0x58, 0x00000886); /* MODE_DETECT_CTRL */
1314 apb_write_reg(2, 0x5c, 0x00001011); /* ICFO_EST_CTRL */
1315 apb_write_reg(2, 0x5f, 0x00010503); /* TPS_FCFO_CTRL */
1316 apb_write_reg(2, 0x61, 0x00000003); /* DE_PN_CTRL */
1317 apb_write_reg(2, 0x61, apb_read_reg(2, 0x61) | (1 << 2));
1318 /* DE_PN_CTRL SP sync close , Use TPS only ; */
1319 apb_write_reg(2, 0x68, 0x004060c0); /* CHAN_EST_CTRL0 */
1320 apb_write_reg(2, 0x68, apb_read_reg(2, 0x68) & ~(1 << 7));
1321 /* SNR report filter; */
1322 /*apb_write_reg(2, 0x68, apb_read_reg(2, 0x68) &~(1<<13)); //
1323 * Timing Adjust Shutdown;
1324 */
1325 apb_write_reg(2, 0x69, 0x148c3812); /* CHAN_EST_CTRL1 */
1326 /*apb_write_reg(2, 0x69, apb_read_reg(2, 0x69) | (1<<10)); //
1327 * Disable FD data update
1328 */
1329 /*apb_write_reg(2, 0x69, apb_read_reg(2, 0x69) | (1<<9)); //
1330 * set FD coeff
1331 */
1332 /*apb_write_reg(2, 0x69, apb_read_reg(2, 0x69) | (1<<8)); //
1333 * set TD coeff
1334 */
1335 apb_write_reg(2, 0x6a, 0x9101012d); /* CHAN_EST_CTRL2 */
1336 apb_write_reg(2, 0x6b, 0x00442211); /* CHAN_EST_CTRL2 */
1337 apb_write_reg(2, 0x6c, 0x01fc040a); /* CHAN_EST_CTRL3 */
1338 apb_write_reg(2, 0x6d, 0x0030303f); /* SET SNR THRESHOLD */
1339 apb_write_reg(2, 0x73, 0xffffffff); /* CCI0_PILOT_UPDATE_CTRL */
1340 apb_write_reg(2, 0x74, 0xffffffff); /* CCI0_DATA_UPDATE_CTRL */
1341 apb_write_reg(2, 0x75, 0xffffffff); /* CCI1_PILOT_UPDATE_CTRL */
1342 apb_write_reg(2, 0x76, 0xffffffff); /* CCI1_DATA_UPDATE_CTRL */
1343
1344 /* Set ACF and ACFEQ coeffecient */
1345 switch (sr) {
1346 case 0:
1347 set_ACF_coef(21, bw);
1348 break;
1349 case 1:
1350 set_ACF_coef(21, bw);
1351 break;
1352 case 2:
1353 set_ACF_coef(28, bw);
1354 break;
1355 case 3:
1356 set_ACF_coef(45, bw);
1357 break;
1358 default:
1359 break;
1360 }
1361
1362 apb_write_reg(2, 0x78, 0x000001a2);
1363 /* FEC_CTRL parallel mode ; [27:24] is TS clk/valid/sync/error */
1364 apb_write_reg(2, 0x7d, 0x0000009d);
1365 apb_write_reg(2, 0xd6, 0x00000003);
1366 apb_write_reg(2, 0xd7, 0x00000008);
1367 apb_write_reg(2, 0xd8, 0x00000120);
1368 apb_write_reg(2, 0xd9, 0x01010101);
1369 apb_write_reg(2, 0x04, 0x00000000);
1370 /* TPS Current, QPSK, none Hierarchy, HP, LP 1/2 */
1371
1372 tmp = (1 << 25) | ((bw & 3) << 20) | (1 << 16) | (1 << 1);
1373 apb_write_reg(2, 0x02, tmp);
1374 apb_write_reg(2, 0x03, (1 << 6)); /* Cordic parameter Calc */
1375
1376 udelay(1);
1377
1378 tmp = apb_read_reg(2, 0x02);
1379 tmp |= (1 << 24) | 1; /* FSM, Demod enable. */
1380 apb_write_reg(2, 0x02, tmp);
1381}
1382
1383int dvbt_set_ch(struct aml_demod_sta *demod_sta,
1384 struct aml_demod_i2c *demod_i2c,
1385 struct aml_demod_dvbt *demod_dvbt)
1386{
1387 int ret = 0;
1388 u8 bw, sr, ifreq, agc_mode;
1389 u32 ch_freq;
1390
1391 bw = demod_dvbt->bw;
1392 sr = demod_dvbt->sr;
1393 ifreq = demod_dvbt->ifreq;
1394 agc_mode = demod_dvbt->agc_mode;
1395 ch_freq = demod_dvbt->ch_freq;
1396
1397 /* Set registers */
1398 /*//////////////////////////////////// */
1399 /* bw == 0 : 8M */
1400 /* 1 : 7M */
1401 /* 2 : 6M */
1402 /* 3 : 5M */
1403 /* sr == 0 : 20.7M */
1404 /* 1 : 20.8333M */
1405 /* 2 : 28.5714M */
1406 /* 3 : 45M */
1407 /* ifreq == 0: 36.13MHz */
1408 /* 1: 4.57MHz */
1409 /* agc_mode == 0: single AGC */
1410 /* 1: dual AGC */
1411 /*//////////////////////////////////// */
1412 if (bw > 3) {
1413 dprintk("Error: Invalid Bandwidth option %d\n", bw);
1414 bw = 0;
1415 ret = -1;
1416 }
1417
1418 if (sr > 3) {
1419 dprintk("Error: Invalid Sampling Freq option %d\n", sr);
1420 sr = 2;
1421 ret = -1;
1422 }
1423
1424 if (ifreq > 1) {
1425 dprintk("Error: Invalid IFreq option %d\n", ifreq);
1426 ifreq = 0;
1427 ret = -1;
1428 }
1429
1430 if (agc_mode > 3) {
1431 dprintk("Error: Invalid AGC mode option %d\n", agc_mode);
1432 agc_mode = 0;
1433 ret = -1;
1434 }
1435 /* if (ret != 0) return ret; */
1436
1437 /* Set DVB-T */
1438 (*DEMOD_REG0) |= 1;
1439
1440 demod_sta->dvb_mode = 1;
1441 demod_sta->ch_mode = 0; /* TODO */
1442 demod_sta->agc_mode = agc_mode;
1443 demod_sta->ch_freq = ch_freq;
1444 if (demod_i2c->tuner == 1)
1445 demod_sta->ch_if = 36130;
1446 else if (demod_i2c->tuner == 2)
1447 demod_sta->ch_if = 4570;
1448
1449 demod_sta->ch_bw = (8 - bw) * 1000;
1450 demod_sta->symb_rate = 0; /* TODO */
1451
1452 /* Set Tuner */
1453 if (ch_freq < 1000 || ch_freq > 900000) {
1454 dprintk
1455 (
1456 "Error: Invalid Channel Freq option %d, Skip Set tuner\n",
1457 ch_freq);
1458 /*ch_freq = 474000; */
1459 ret = -1;
1460 } else {
1461 /* tuner_set_ch(demod_sta, demod_i2c); */
1462 }
1463
1464 if ((ch_freq % 100) == 2)
1465 dprintk("Input frequency is XXX002, Skip initial demod\n");
1466 else
1467 dvbt_reg_initial(demod_sta);
1468
1469 dvbt_enable_irq(7); /* open symbolhead int */
1470
1471 tuner_type = demod_i2c->tuner;
1472
1473 return ret;
1474}
1475
1476static int dvbt_get_ch_power(struct aml_demod_sta *demod_sta,
1477 struct aml_demod_i2c *demod_i2c)
1478{
1479 u32 ad_power;
1480
1481 ad_power =
1482 agc_power_to_dbm((apb_read_reg(2, 0x1c) & 0x7ff),
1483 apb_read_reg(2, 0x1b) & 0x1ff, 0,
1484 demod_i2c->tuner);
1485 return ad_power;
1486}
1487
1488int dvbt_sfo(void)
1489{
1490 int sfo;
1491
1492 sfo = apb_read_reg(2, 0x47) & 0xfff;
1493 sfo = (sfo > 0x7ff) ? (sfo - 0x1000) : sfo;
1494 return sfo;
1495}
1496
1497int dvbt_fcfo(void)
1498{
1499 int fcfo;
1500
1501 fcfo = (apb_read_reg(2, 0x26)) & 0xffffff;
1502 fcfo = (fcfo > 0x7fffff) ? (fcfo - 0x1000000) : fcfo;
1503 return fcfo;
1504}
1505
1506static int dvbt_total_packet_error(void)
1507{
1508 return apb_read_reg(2, 0xbf);
1509}
1510
1511static int dvbt_super_frame_counter(void)
1512{
1513 return apb_read_reg(2, 0xc0) & 0xfffff;
1514}
1515
1516static int dvbt_packet_correct_in_sframe(void)
1517{
1518 return apb_read_reg(2, 0xc1) & 0xfffff;
1519}
1520
1521/*static int dvbt_resync_counter(void)
1522 * {return((apb_read_reg(2, 0xc0)>>20)&0xff);}
1523 */
1524static int dvbt_packets_per_sframe(void)
1525{
1526 u32 tmp;
1527 int hier_mode;
1528 int constel;
1529 int hp_code_rate;
1530 int lp_code_rate;
1531 int hier_sel;
1532 int code_rate;
1533 int ret;
1534
1535 tmp = apb_read_reg(2, 0x06);
1536 constel = tmp >> 13 & 3;
1537 hier_mode = tmp >> 10 & 7;
1538 hp_code_rate = tmp >> 7 & 7;
1539 lp_code_rate = tmp >> 4 & 7;
1540
1541 if (hier_mode == 0) {
1542 code_rate = hp_code_rate;
1543 } else {
1544 tmp = apb_read_reg(2, 0x78);
1545 hier_sel = tmp >> 9 & 1;
1546 if (hier_sel == 0) {
1547 constel = 0; /* QPSK; */
1548 code_rate = hp_code_rate;
1549 } else {
1550 constel = constel == 2 ? 1 : 0;
1551 code_rate = lp_code_rate;
1552 }
1553 }
1554
1555 switch (code_rate) {
1556 case 0:
1557 ret = (constel == 0) ? 1008 : (constel == 1) ? 2016 : 3024;
1558 break;
1559 case 1:
1560 ret = (constel == 0) ? 1344 : (constel == 1) ? 2688 : 4032;
1561 break;
1562 case 2:
1563 ret = (constel == 0) ? 1512 : (constel == 1) ? 3024 : 4536;
1564 break;
1565 case 3:
1566 ret = (constel == 0) ? 1680 : (constel == 1) ? 3360 : 5040;
1567 break;
1568 case 4:
1569 ret = (constel == 0) ? 1764 : (constel == 1) ? 3528 : 5292;
1570 break;
1571 default:
1572 ret = (constel == 0) ? 1008 : (constel == 1) ? 2016 : 3024;
1573 break;
1574 }
1575 return ret;
1576}
1577
1578static int dvbt_get_per(void)
1579{
1580 int packets_per_sframe;
1581 int error;
1582 int per;
1583
1584 packets_per_sframe = dvbt_packets_per_sframe();
1585 error = packets_per_sframe - dvbt_packet_correct_in_sframe();
1586 per = 1000 * error / packets_per_sframe;
1587
1588 return per;
1589}
1590
1591static void dvbt_set_test_bus(u8 sel)
1592{
1593 u32 tmp;
1594
1595 tmp = apb_read_reg(2, 0x7f);
1596 tmp &= ~(0x1f);
1597 tmp |= ((1 << 15) | (1 << 5) | (sel & 0x1f));
1598 apb_write_reg(2, 0x7f, tmp);
1599}
1600
1601/*
1602 * void dvbt_get_test_out(u8 sel, u32 len, u32 *buf)
1603 * {
1604 * int i;
1605 *
1606 * dvbt_set_test_bus(sel);
1607 *
1608 * for (i=0; i<len; i++) {
1609 * buf[i] = apb_read_reg(2, 0x13);
1610 * }
1611 * }
1612 */
1613void dvbt_get_test_out(u8 sel, u32 len, u32 *buf)
1614{
1615 int i, cnt;
1616
1617 dvbt_set_test_bus(sel);
1618
1619 for (i = 0, cnt = 0; i < len - 4 && cnt < 1000000; i++) {
1620 buf[i] = apb_read_reg(2, 0x13);
1621 if ((buf[i] >> 10) & 0x1) {
1622 buf[i++] = apb_read_reg(2, 0x13);
1623 buf[i++] = apb_read_reg(2, 0x13);
1624 buf[i++] = apb_read_reg(2, 0x13);
1625 buf[i++] = apb_read_reg(2, 0x13);
1626 buf[i++] = apb_read_reg(2, 0x13);
1627 buf[i++] = apb_read_reg(2, 0x13);
1628 buf[i++] = apb_read_reg(2, 0x13);
1629 buf[i++] = apb_read_reg(2, 0x13);
1630 } else {
1631 i--;
1632 }
1633
1634 cnt++;
1635 }
1636}
1637
1638static int dvbt_get_avg_per(void)
1639{
1640 int packets_per_sframe;
1641 static int err_last;
1642 static int err_now;
1643 static int rsnum_now;
1644 static int rsnum_last;
1645 int per;
1646
1647 packets_per_sframe = dvbt_packets_per_sframe();
1648 rsnum_last = rsnum_now;
1649 rsnum_now = dvbt_super_frame_counter();
1650 err_last = err_now;
1651 err_now = dvbt_total_packet_error();
1652 if (rsnum_now != rsnum_last)
1653 per = 1000 * (err_now - err_last) /
1654 ((rsnum_now - rsnum_last) * packets_per_sframe);
1655 else
1656 per = 123;
1657
1658 return per;
1659}
1660
1661int dvbt_status(struct aml_demod_sta *demod_sta,
1662 struct aml_demod_i2c *demod_i2c,
1663 struct aml_demod_sts *demod_sts)
1664{
1665 /* if parameters are needed to calc, pass the struct to func. */
1666 /* all small funcs like read_snr() should be static. */
1667
1668 demod_sts->ch_snr = apb_read_reg(2, 0x0a);
1669 demod_sts->ch_per = dvbt_get_per();
1670 demod_sts->ch_pow = dvbt_get_ch_power(demod_sta, demod_i2c);
1671 demod_sts->ch_ber = apb_read_reg(2, 0x0b);
1672 demod_sts->ch_sts = apb_read_reg(2, 0);
1673 demod_sts->dat0 = dvbt_get_avg_per();
1674 demod_sts->dat1 = apb_read_reg(2, 0x06);
1675 return 0;
1676}
1677
1678static int dvbt_get_status(struct aml_demod_sta *demod_sta,
1679 struct aml_demod_i2c *demod_i2c)
1680{
1681 return apb_read_reg(2, 0x0) >> 12 & 1;
1682}
1683
1684static int dvbt_ber(void);
1685
1686static int dvbt_get_ber(struct aml_demod_sta *demod_sta,
1687 struct aml_demod_i2c *demod_i2c)
1688{
1689 return dvbt_ber(); /*unit: 1e-7 */
1690}
1691
1692static int dvbt_get_snr(struct aml_demod_sta *demod_sta,
1693 struct aml_demod_i2c *demod_i2c)
1694{
1695 return apb_read_reg(2, 0x0a) & 0x3ff; /*dBm: bit0~bit2=decimal */
1696}
1697
1698static int dvbt_get_strength(struct aml_demod_sta *demod_sta,
1699 struct aml_demod_i2c *demod_i2c)
1700{
1701 int dbm = dvbt_get_ch_power(demod_sta, demod_i2c);
1702
1703 return dbm;
1704}
1705
1706static int dvbt_get_ucblocks(struct aml_demod_sta *demod_sta,
1707 struct aml_demod_i2c *demod_i2c)
1708{
1709 return dvbt_get_per();
1710}
1711
1712struct demod_status_ops *dvbt_get_status_ops(void)
1713{
1714 static struct demod_status_ops ops = {
1715 .get_status = dvbt_get_status,
1716 .get_ber = dvbt_get_ber,
1717 .get_snr = dvbt_get_snr,
1718 .get_strength = dvbt_get_strength,
1719 .get_ucblocks = dvbt_get_ucblocks,
1720 };
1721
1722 return &ops;
1723}
1724
1725void dvbt_enable_irq(int dvbt_irq)
1726{
1727 /* clear status & enable irq */
1728 (*OFDM_INT_STS) &= ~(1 << dvbt_irq);
1729 (*OFDM_INT_EN) |= (1 << dvbt_irq);
1730}
1731
1732void dvbt_disable_irq(int dvbt_irq)
1733{
1734 /* disable irq & clear status */
1735 (*OFDM_INT_EN) &= ~(1 << dvbt_irq);
1736 (*OFDM_INT_STS) &= ~(1 << dvbt_irq);
1737}
1738
1739char *dvbt_irq_name[] = {
1740 "PFS_FCFO",
1741 "PFS_ICFO",
1742 " CS_FCFO",
1743 " PFS_SFO",
1744 " PFS_TPS",
1745 " SP",
1746 " CCI",
1747 " Symbol",
1748 " In_Sync",
1749 "Out_Sync",
1750 "FSM Stat"
1751};
1752
1753void dvbt_isr(struct aml_demod_sta *demod_sta)
1754{
1755 u32 stat, mask;
1756 int dvbt_irq;
1757
1758 stat = (*OFDM_INT_STS);
1759 mask = (*OFDM_INT_EN);
1760 stat &= mask;
1761
1762 for (dvbt_irq = 0; dvbt_irq < 11; dvbt_irq++) {
1763 if (stat >> dvbt_irq & 1) {
1764 if (demod_sta->debug)
1765 dprintk("irq: aml_demod dvbt %2d %s %8x %8x\n",
1766 dvbt_irq, dvbt_irq_name[dvbt_irq], stat,
1767 mask);
1768 /* dvbt_disable_irq(dvbt_irq); */
1769 }
1770 }
1771 /* clear status */
1772 (*OFDM_INT_STS) = 0;
1773}
1774
1775static int demod_monitor_ave(void);
1776int dvbt_isr_islock(void)
1777{
1778#define IN_SYNC_MASK (0x100)
1779
1780 u32 stat, mask;
1781
1782 stat = (*OFDM_INT_STS);
1783 *OFDM_INT_STS = stat & (~IN_SYNC_MASK);
1784
1785 mask = (*OFDM_INT_EN);
1786 stat &= mask;
1787
1788 return (stat & IN_SYNC_MASK) == IN_SYNC_MASK;
1789}
1790
1791int dvbt_isr_monitor(void)
1792{
1793#define SYM_HEAD_MASK (0x80)
1794 u32 stat, mask;
1795
1796 stat = (*OFDM_INT_STS);
1797 *OFDM_INT_STS = stat & (~SYM_HEAD_MASK);
1798
1799 mask = (*OFDM_INT_EN);
1800 stat &= mask;
1801 /* symbol_head int */
1802 if ((stat & SYM_HEAD_MASK) == SYM_HEAD_MASK)
1803 demod_monitor_ave();
1804 return 0;
1805}
1806
1807int dvbt_isr_cancel(void)
1808{
1809 *OFDM_INT_STS = 0;
1810 *OFDM_INT_EN = 0;
1811 return 0;
1812}
1813
1814static int demod_monitor_instant(void)
1815{
1816 int SNR;
1817 int SNR_SP = 500;
1818 int SNR_TPS = 0;
1819 int SNR_CP = 0;
1820 int SFO_residual = 0;
1821 int SFO_esti = 0;
1822 int FCFO_esti = 0;
1823 int FCFO_residual = 0;
1824 int AGC_Gain = 0;
1825 int be_vit_error = 0;
1826 int Signal_power = 0;
1827 int FECFlag = 0;
1828 int EQ_seg_ratio = 0;
1829 int tps_0 = 0;
1830 int tps_1 = 0;
1831 int tps_2 = 0;
1832 int cci_blank = 0;
1833
1834 int SFO;
1835 int FCFO;
1836 int timing_adj;
1837 int RS_CorrectNum;
1838 int RS_Error_sum;
1839 int resync_times;
1840 int tps_summary;
1841
1842 int tps_window;
1843 int tps_guard;
1844 int tps_constell;
1845 int tps_Hier_none;
1846 int tps_Hier_alpha;
1847 int tps_HP_cr;
1848 int tps_LP_cr;
1849
1850 int tmpAGCGain;
1851
1852 /* Read Registers */
1853 SNR = apb_read_reg(2, 0x0a);
1854 FECFlag = (apb_read_reg(2, 0x00) >> 11) & 0x3;
1855 SFO = apb_read_reg(2, 0x47) & 0xfff;
1856 SFO_esti = apb_read_reg(2, 0x60) & 0xfff;
1857 FCFO_esti = (apb_read_reg(2, 0x60) >> 11) & 0xfff;
1858 FCFO = (apb_read_reg(2, 0x26)) & 0xffffff;
1859 be_vit_error = apb_read_reg(2, 0x0c) & 0x1fff;
1860 timing_adj = apb_read_reg(2, 0x6f) & 0x1fff;
1861 RS_CorrectNum = apb_read_reg(2, 0xc1) & 0xfffff;
1862 Signal_power = (apb_read_reg(2, 0x1b)) & 0x1ff;
1863 EQ_seg_ratio = apb_read_reg(2, 0x6e) & 0x3ffff;
1864 tps_0 = apb_read_reg(2, 0x64);
1865 tps_1 = apb_read_reg(2, 0x65);
1866 tps_2 = apb_read_reg(2, 0x66) & 0xf;
1867 tps_summary = apb_read_reg(2, 0x04) & 0x7fff;
1868 cci_blank = (apb_read_reg(2, 0x66) >> 16);
1869 RS_Error_sum = apb_read_reg(2, 0xbf) & 0x3ffff;
1870 resync_times = (apb_read_reg(2, 0xc0) >> 20) & 0xff;
1871 AGC_Gain = apb_read_reg(2, 0x1c) & 0x7ff;
1872
1873 /* Calc */
1874 SFO_residual = (SFO > 0x7ff) ? (SFO - 0x1000) : SFO;
1875 FCFO_residual = (FCFO > 0x7fffff) ? (FCFO - 0x1000000) : FCFO;
1876 FCFO_esti = (FCFO_esti > 0x7ff) ? (FCFO_esti - 0x1000) : FCFO_esti;
1877 SNR_CP = (SNR) & 0x3ff;
1878 SNR_TPS = (SNR >> 10) & 0x3ff;
1879 SNR_SP = (SNR >> 20) & 0x3ff;
1880 SNR_SP = (SNR_SP > 0x1ff) ? SNR_SP - 0x400 : SNR_SP;
1881 SNR_TPS = (SNR_TPS > 0x1ff) ? SNR_TPS - 0x400 : SNR_TPS;
1882 SNR_CP = (SNR_CP > 0x1ff) ? SNR_CP - 0x400 : SNR_CP;
1883 tmpAGCGain = AGC_Gain;
1884 timing_adj = (timing_adj > 0xfff) ? timing_adj - 0x2000 : timing_adj;
1885
1886 tps_window = (tps_summary & 0x3);
1887 tps_guard = ((tps_summary >> 2) & 0x3);
1888 tps_constell = ((tps_summary >> 13) & 0x3);
1889 tps_Hier_none = (((tps_summary >> 10) & 0x7) == 0) ? 1 : 0;
1890 tps_Hier_alpha = (tps_summary >> 11) & 0x3;
1891 tps_Hier_alpha = (tps_Hier_alpha == 3) ? 4 : tps_Hier_alpha;
1892 tps_LP_cr = (tps_summary >> 4) & 0x7;
1893 tps_HP_cr = (tps_summary >> 7) & 0x7;
1894
1895 dprintk("\n\n");
1896 switch (tps_window) {
1897 case 0:
1898 dprintk("2K ");
1899 break;
1900 case 1:
1901 dprintk("8K ");
1902 break;
1903 case 2:
1904 dprintk("4K ");
1905 break;
1906 default:
1907 dprintk("UnWin ");
1908 break;
1909 }
1910 switch (tps_guard) {
1911 case 0:
1912 dprintk("1/32 ");
1913 break;
1914 case 1:
1915 dprintk("1/16 ");
1916 break;
1917 case 2:
1918 dprintk("1/ 8 ");
1919 break;
1920 case 3:
1921 dprintk("1/ 4 ");
1922 break;
1923 default:
1924 dprintk("UnGuard ");
1925 break;
1926 }
1927 switch (tps_constell) {
1928 case 0:
1929 dprintk(" QPSK ");
1930 break;
1931 case 1:
1932 dprintk("16QAM ");
1933 break;
1934 case 2:
1935 dprintk("64QAM ");
1936 break;
1937 default:
1938 dprintk("UnConstl ");
1939 break;
1940 }
1941 switch (tps_Hier_none) {
1942 case 0:
1943 dprintk("Hiera ");
1944 break;
1945 case 1:
1946 dprintk("non-H ");
1947 break;
1948 default:
1949 dprintk("UnHier ");
1950 break;
1951 }
1952 dprintk("%d ", tps_Hier_alpha);
1953 dprintk("HP ");
1954 switch (tps_HP_cr) {
1955 case 0:
1956 dprintk("1/2 ");
1957 break;
1958 case 1:
1959 dprintk("2/3 ");
1960 break;
1961 case 2:
1962 dprintk("3/4 ");
1963 break;
1964 case 3:
1965 dprintk("5/6 ");
1966 break;
1967 case 4:
1968 dprintk("7/8 ");
1969 break;
1970 default:
1971 dprintk("UnHCr ");
1972 break;
1973 }
1974 dprintk("LP ");
1975 switch (tps_LP_cr) {
1976 case 0:
1977 dprintk("1/2 ");
1978 break;
1979 case 1:
1980 dprintk("2/3 ");
1981 break;
1982 case 2:
1983 dprintk("3/4 ");
1984 break;
1985 case 3:
1986 dprintk("5/6 ");
1987 break;
1988 case 4:
1989 dprintk("7/8 ");
1990 break;
1991 default:
1992 dprintk("UnLCr ");
1993 break;
1994 }
1995 dprintk("\n");
1996 dprintk("P %4x ", RS_Error_sum);
1997 dprintk("SP %2d ", SNR_SP);
1998 dprintk("TPS %2d ", SNR_TPS);
1999 dprintk("CP %2d ", SNR_CP);
2000 dprintk("EQS %2x ", EQ_seg_ratio);
2001 dprintk("RSC %4d ", RS_CorrectNum);
2002 dprintk("SFO %3d ", SFO_residual);
2003 dprintk("FCFO %4d ", FCFO_residual);
2004 dprintk("Vit %3x ", be_vit_error);
2005 dprintk("Timing %3d ", timing_adj);
2006 dprintk("SigP %3x ", Signal_power);
2007 dprintk("AGC %d ", tmpAGCGain);
2008 dprintk("SigP %d ",
2009 agc_power_to_dbm(tmpAGCGain, Signal_power, 0, tuner_type));
2010 dprintk("FEC %x ", FECFlag);
2011 dprintk("ReSyn %x ", resync_times);
2012 dprintk("cciB %x", cci_blank);
2013
2014 dprintk("\n");
2015
2016 return 0;
2017}
2018
2019int serial_div(int a, int b)
2020{
2021 int c;
2022 int cnt;
2023 int b_buf;
2024
2025 if (b == 0)
2026 return 0x7fffffff;
2027 if (a == 0)
2028 return 0;
2029
2030 c = 0;
2031 cnt = 0;
2032
2033 a = (a < 0) ? -1 * a : a;
2034 b = (b < 0) ? -1 * b : b;
2035
2036 b_buf = b;
2037
2038 while (a >= b) {
2039 b = b << 1;
2040 cnt++;
2041 }
2042 while (b > b_buf) {
2043 b = b >> 1;
2044 c = c << 1;
2045 if (a > b) {
2046 c = c + 1;
2047 a = a - b;
2048 }
2049 }
2050 return c;
2051}
2052
2053static int ave0, bit_unit_L;
2054
2055static int dvbt_ber(void)
2056{
2057 int BER_e_n7 = serial_div(ave0 * 40, bit_unit_L);
2058
2059 return BER_e_n7;
2060}
2061
2062static int demod_monitor_ave(void)
2063{
2064 static int i;
2065 static int ave[3] = { 0, 0, 0 };
2066
2067 ave[0] = ave[0] + (apb_read_reg(2, 0x0b) & 0x7ff);
2068 ave[1] = ave[1] + (apb_read_reg(2, 0x0a) & 0x3ff);
2069 ave[2] = ave[2] + (apb_read_reg(2, 0x0c) & 0x1fff);
2070
2071 i++;
2072
2073 if (i >= 8192) {
2074 int tps_mode;
2075 int tps_constell;
2076 int r_t;
2077 int mode_L;
2078 int const_L;
2079 int SNR_Int;
2080 int SNR_fra;
2081
2082 if (debug_amldvbt)
2083 demod_monitor_instant();
2084
2085 r_t = apb_read_reg(2, 0x04);
2086 tps_mode = r_t & 0x3;
2087 tps_constell = (r_t >> 13) & 0x3;
2088 mode_L = (tps_mode == 0) ? 1 : (tps_mode == 1) ? 4 : 2;
2089 const_L = (tps_constell == 0) ? 2 : (tps_constell == 1) ? 4 : 6;
2090 bit_unit_L = 189 * mode_L * const_L;
2091 SNR_Int = (ave[1] >> 16);
2092 switch ((ave[1] >> 13) & 0x7) {
2093 case 0:
2094 SNR_fra = 0;
2095 break;
2096 case 1:
2097 SNR_fra = 125;
2098 break;
2099 case 2:
2100 SNR_fra = 250;
2101 break;
2102 case 3:
2103 SNR_fra = 375;
2104 break;
2105 case 4:
2106 SNR_fra = 500;
2107 break;
2108 case 5:
2109 SNR_fra = 625;
2110 break;
2111 case 6:
2112 SNR_fra = 750;
2113 break;
2114 case 7:
2115 SNR_fra = 875;
2116 break;
2117 default:
2118 SNR_fra = 0;
2119 break;
2120 }
2121
2122 ave0 = ave[0];
2123
2124 if (debug_amldvbt)
2125 dprintk("RSBi %d Thresh %d SNR %d.%d Vit %x\n\n",
2126 (ave[0] >> 3) * 5, (bit_unit_L * 8), SNR_Int,
2127 SNR_fra, (ave[2] >> 13));
2128 i = 0;
2129 ave[0] = ave[1] = ave[2] = 0;
2130 }
2131
2132 return i;
2133}
2134
2135int dvbt_switch_to_HP(void)
2136{
2137 apb_write_reg(2, 0x78, apb_read_reg(2, 0x78) & ~(1 << 9));
2138 return 0;
2139}
2140
2141int dvbt_switch_to_LP(void)
2142{
2143 apb_write_reg(2, 0x78, apb_read_reg(2, 0x78) | (1 << 9));
2144 return 0;
2145}
2146
2147int dvbt_shutdown(void)
2148{
2149 apb_write_reg(2, 0x02, 0x00800000);
2150 /* SW reset bit[23] ; write anything to zero */
2151 apb_write_reg(2, 0x00, 0x00000000);
2152 return 0;
2153}
2154
2155int dvbt_get_params(struct aml_demod_sta *demod_sta,
2156 struct aml_demod_i2c *adap, int *code_rate_HP,
2157 /* high priority stream code rate */
2158 int *code_rate_LP, /* low priority stream code rate */
2159 int *constellation, /* modulation type (see above) */
2160 int *transmission_mode,
2161 int *guard_interval, int *hierarchy_information)
2162{
2163 int tps_summary, tps_window, tps_guard, tps_constell, tps_Hier_none;
2164 int tps_Hier_alpha, tps_LP_cr, tps_HP_cr;
2165
2166 tps_summary = apb_read_reg(2, 0x04) & 0x7fff;
2167 tps_window = (tps_summary & 0x3);
2168 tps_guard = ((tps_summary >> 2) & 0x3);
2169 tps_constell = ((tps_summary >> 13) & 0x3);
2170 tps_Hier_none = (((tps_summary >> 10) & 0x7) == 0) ? 1 : 0;
2171 tps_Hier_alpha = (tps_summary >> 11) & 0x3;
2172 tps_Hier_alpha = (tps_Hier_alpha == 3) ? 4 : tps_Hier_alpha;
2173 tps_LP_cr = (tps_summary >> 4) & 0x7;
2174 tps_HP_cr = (tps_summary >> 7) & 0x7;
2175 if (code_rate_HP)
2176 *code_rate_HP = tps_HP_cr; /*1/2:2/3:3/4:5/6:7/8 */
2177 if (code_rate_LP)
2178 *code_rate_LP = tps_LP_cr; /*1/2:2/3:3/4:5/6:7/8 */
2179 if (constellation)
2180 *constellation = tps_constell; /*QPSK/16QAM/64QAM */
2181 if (transmission_mode)
2182 *transmission_mode = tps_window; /*2K/8K/4K */
2183 if (guard_interval)
2184 *guard_interval = tps_guard; /*1/32:1/16:1/8:1/4 */
2185 if (hierarchy_information)
2186 *hierarchy_information = tps_Hier_alpha; /*1/2/4 */
2187 return 0;
2188}
2189
generated by cgit at 2024-05-19 21:22:41 (GMT)