blob: 4b231320adbf7aa588ffc8bb2b307a2a1ee3d984
1 | /* |
2 | * Copyright (C) 2017 Amlogic, Inc. All rights reserved. |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify |
5 | * it under the terms of the GNU General Public License as published by |
6 | * the Free Software Foundation; either version 2 of the License, or |
7 | * (at your option) any later version. |
8 | * |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
12 | * more details. |
13 | * |
14 | * You should have received a copy of the GNU General Public License along |
15 | * with this program; if not, write to the Free Software Foundation, Inc., |
16 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
17 | * |
18 | * Description: |
19 | */ |
20 | #ifndef __ADDR_DTMB_CHE_H__ |
21 | #define __ADDR_DTMB_CHE_H__ |
22 | |
23 | #include "addr_dtmb_top.h" |
24 | |
25 | #define DTMB_CHE_ADDR(x) (DTMB_DEMOD_BASE + (x << 2)) |
26 | |
27 | #define DTMB_CHE_TE_HREB_SNR DTMB_CHE_ADDR(0x8d) |
28 | #define DTMB_CHE_MC_SC_TIMING_POWTHR DTMB_CHE_ADDR(0x8e) |
29 | #define DTMB_CHE_MC_SC_PROTECT_GD DTMB_CHE_ADDR(0x8f) |
30 | #define DTMB_CHE_TIMING_LIMIT DTMB_CHE_ADDR(0x90) |
31 | #define DTMB_CHE_TPS_CONFIG DTMB_CHE_ADDR(0x91) |
32 | #define DTMB_CHE_FD_TD_STEPSIZE DTMB_CHE_ADDR(0x92) |
33 | #define DTMB_CHE_QSTEP_SET DTMB_CHE_ADDR(0x93) |
34 | #define DTMB_CHE_SEG_CONFIG DTMB_CHE_ADDR(0x94) |
35 | #define DTMB_CHE_FD_TD_LEAKSIZE_CONFIG1 DTMB_CHE_ADDR(0x95) |
36 | #define DTMB_CHE_FD_TD_LEAKSIZE_CONFIG2 DTMB_CHE_ADDR(0x96) |
37 | #define DTMB_CHE_FD_TD_COEFF DTMB_CHE_ADDR(0x97) |
38 | #define DTMB_CHE_M_CCI_THR_CONFIG1 DTMB_CHE_ADDR(0x98) |
39 | #define DTMB_CHE_M_CCI_THR_CONFIG2 DTMB_CHE_ADDR(0x99) |
40 | #define DTMB_CHE_M_CCI_THR_CONFIG3 DTMB_CHE_ADDR(0x9a) |
41 | #define DTMB_CHE_CCIDET_CONFIG DTMB_CHE_ADDR(0x9b) |
42 | #define DTMB_CHE_IBDFE_CONFIG1 DTMB_CHE_ADDR(0x9d) |
43 | #define DTMB_CHE_IBDFE_CONFIG2 DTMB_CHE_ADDR(0x9e) |
44 | #define DTMB_CHE_IBDFE_CONFIG3 DTMB_CHE_ADDR(0x9f) |
45 | #define DTMB_CHE_TD_COEFF DTMB_CHE_ADDR(0xa0) |
46 | #define DTMB_CHE_FD_TD_STEPSIZE_ADJ DTMB_CHE_ADDR(0xa1) |
47 | #define DTMB_CHE_FD_COEFF_FRZ DTMB_CHE_ADDR(0xa2) |
48 | #define DTMB_CHE_FD_COEFF DTMB_CHE_ADDR(0xa3) |
49 | #define DTMB_CHE_FD_LEAKSIZE DTMB_CHE_ADDR(0xa4) |
50 | #define DTMB_CHE_IBDFE_CONFIG4 DTMB_CHE_ADDR(0xa5) |
51 | #define DTMB_CHE_IBDFE_CONFIG5 DTMB_CHE_ADDR(0xa6) |
52 | #define DTMB_CHE_IBDFE_CONFIG6 DTMB_CHE_ADDR(0xa7) |
53 | #define DTMB_CHE_IBDFE_CONFIG7 DTMB_CHE_ADDR(0xa8) |
54 | #define DTMB_CHE_DCM_SC_MC_GD_LEN DTMB_CHE_ADDR(0xa9) |
55 | #define DTMB_CHE_EQMC_PICK_THR DTMB_CHE_ADDR(0xaa) |
56 | #define DTMB_CHE_EQMC_THRESHOLD DTMB_CHE_ADDR(0xab) |
57 | #define DTMB_CHE_EQSC_PICK_THR DTMB_CHE_ADDR(0xad) |
58 | #define DTMB_CHE_EQSC_THRESHOLD DTMB_CHE_ADDR(0xae) |
59 | #define DTMB_CHE_PROTECT_GD_TPS DTMB_CHE_ADDR(0xaf) |
60 | #define DTMB_CHE_FD_TD_STEPSIZE_THR1 DTMB_CHE_ADDR(0xb0) |
61 | #define DTMB_CHE_TDFD_SWITCH_SYM1 DTMB_CHE_ADDR(0xb1) |
62 | #define DTMB_CHE_TDFD_SWITCH_SYM2 DTMB_CHE_ADDR(0xb2) |
63 | #define DTMB_CHE_EQ_CONFIG DTMB_CHE_ADDR(0xb3) |
64 | #define DTMB_CHE_EQSC_SNR_IMP_THR1 DTMB_CHE_ADDR(0xb4) |
65 | #define DTMB_CHE_EQSC_SNR_IMP_THR2 DTMB_CHE_ADDR(0xb5) |
66 | #define DTMB_CHE_EQMC_SNR_IMP_THR1 DTMB_CHE_ADDR(0xb6) |
67 | #define DTMB_CHE_EQMC_SNR_IMP_THR2 DTMB_CHE_ADDR(0xb7) |
68 | #define DTMB_CHE_EQSC_SNR_DROP_THR DTMB_CHE_ADDR(0xb8) |
69 | #define DTMB_CHE_EQMC_SNR_DROP_THR DTMB_CHE_ADDR(0xb9) |
70 | #define DTMB_CHE_M_CCI_THR DTMB_CHE_ADDR(0xba) |
71 | #define DTMB_CHE_TPS_MC DTMB_CHE_ADDR(0xbb) |
72 | #define DTMB_CHE_TPS_SC DTMB_CHE_ADDR(0xbc) |
73 | #define DTMB_CHE_CHE_SET_FSM DTMB_CHE_ADDR(0xbd) |
74 | #define DTMB_CHE_ZERO_NUM_THR DTMB_CHE_ADDR(0xbe) |
75 | #define DTMB_CHE_TIMING_READY DTMB_CHE_ADDR(0xbf) |
76 | |
77 | #endif |
78 |