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1/*
2* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
3*
4* This program is free software; you can redistribute it and/or modify
5* it under the terms of the GNU General Public License as published by
6* the Free Software Foundation; either version 2 of the License, or
7* (at your option) any later version.
8*
9* This program is distributed in the hope that it will be useful, but WITHOUT
10* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12* more details.
13*
14* You should have received a copy of the GNU General Public License along
15* with this program; if not, write to the Free Software Foundation, Inc.,
16* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17*
18* Description:
19*/
20#ifndef __ADDR_DTMB_CHE_BIT_H__
21#define __ADDR_DTMB_CHE_BIT_H__
22
23struct DTMB_CHE_TE_HREB_SNR_BITS {
24 unsigned int te_hreb_snr:21, reserved0:11;
25};
26struct DTMB_CHE_MC_SC_TIMING_POWTHR_BITS {
27 unsigned int mc_timing_powthr1:5,
28 reserved1:3,
29 mc_timing_powthr0:5,
30 reserved2:2,
31 sc_timing_powthr1:5, reserved3:4, sc_timing_powthr0:5, reserved4:3;
32};
33struct DTMB_CHE_MC_SC_PROTECT_GD_BITS {
34 unsigned int h_valid:2,
35 reserved5:2,
36 dist:3,
37 reserved6:1,
38 ma_size:3,
39 reserved7:1,
40 mc_protect_gd:5, reserved8:3, sc_protect_gd:5, reserved9:7;
41};
42struct DTMB_CHE_TIMING_LIMIT_BITS {
43 unsigned int ncoh_thd:3,
44 reserved10:1,
45 coh_thd:3,
46 reserved11:1,
47 strong_loc_thd:8, reserved12:4, timing_limit:5, reserved13:7;
48};
49struct DTMB_CHE_TPS_CONFIG_BITS {
50 unsigned int tps_pst_num:5,
51 reserved14:3,
52 tps_pre_num:5, reserved15:3, chi_power_thr:8, reserved16:8;
53};
54struct DTMB_CHE_FD_TD_STEPSIZE_BITS {
55 unsigned int fd_stepsize_thr03:5,
56 fd_stepsize_thr02:5,
57 fd_stepsize_thr01:5,
58 td_stepsize_thr03:5,
59 td_stepsize_thr02:5, td_stepsize_thr01:5, reserved17:2;
60};
61struct DTMB_CHE_QSTEP_SET_BITS {
62 unsigned int factor_stable_thres:10,
63 reserved18:2, qstep_set:13, qstep_set_val:1, reserved19:6;
64};
65struct DTMB_CHE_SEG_CONFIG_BITS {
66 unsigned int seg_bypass:1,
67 seg_num_1seg_log2:3,
68 seg_alpha:3,
69 seg_read_val:1, seg_read_addr:12, noise_input_shift:4, reserved20:8;
70};
71struct DTMB_CHE_FD_TD_LEAKSIZE_CONFIG1_BITS {
72 unsigned int fd_leaksize_thr03:5,
73 fd_leaksize_thr02:5,
74 fd_leaksize_thr01:5,
75 td_leaksize_thr03:5,
76 td_leaksize_thr02:5, td_leaksize_thr01:5, reserved21:2;
77};
78struct DTMB_CHE_FD_TD_LEAKSIZE_CONFIG2_BITS {
79 unsigned int fd_leaksize_thr13:5,
80 fd_leaksize_thr12:5,
81 fd_leaksize_thr11:5,
82 td_leaksize_thr13:5,
83 td_leaksize_thr12:5, td_leaksize_thr11:5, reserved22:2;
84};
85struct DTMB_CHE_FD_TD_COEFF_BITS {
86 unsigned int td_coeff_frz:14,
87 reserved23:2,
88 td_coeff_addr:4,
89 td_coeff_init:1,
90 td_coeff_rst:1,
91 fd_coeff_init:1,
92 fd_coeff_done:1,
93 fd_coeff_rst:1, td_coeff_done:1, fd_coeff_addr:5, reserved24:1;
94};
95struct DTMB_CHE_M_CCI_THR_CONFIG1_BITS {
96 unsigned int m_cci_thr_mc1:10,
97 m_cci_thr_mc2:10, m_cci_thr_mc3:10, reserved25:2;
98};
99struct DTMB_CHE_M_CCI_THR_CONFIG2_BITS {
100 unsigned int m_cci_thr_sc2:10,
101 m_cci_thr_sc3:10, m_cci_thr_mc0:10, reserved26:2;
102};
103struct DTMB_CHE_M_CCI_THR_CONFIG3_BITS {
104 unsigned int m_cci_thr_ma:10,
105 m_cci_thr_sc0:10, m_cci_thr_sc1:10, reserved27:2;
106};
107struct DTMB_CHE_CCIDET_CONFIG_BITS {
108 unsigned int ccidet_dly:7,
109 ccidet_malpha:3,
110 ccidet_sc_mask_rng:5,
111 ccidet_mc_mask_rng:5,
112 ccidet_masize:4,
113 ccidect_sat_sft:3,
114 ccicnt_out_sel:2, tune_mask:1, m_cci_bypass:1, reserved28:1;
115};
116struct DTMB_CHE_IBDFE_CONFIG1_BITS {
117 unsigned int ibdfe_cci_just_thr:13,
118 reserved29:3,
119 ibdfe_dmsg_point:5, reserved30:3, ibdfe_dmsg_alp:3, reserved31:5;
120};
121struct DTMB_CHE_IBDFE_CONFIG2_BITS {
122 unsigned int ibdfe_rou_rat_1:10,
123 reserved32:6, ibdfe_rou_rat_0:10, reserved33:6;
124};
125struct DTMB_CHE_IBDFE_CONFIG3_BITS {
126 unsigned int ibdfe_rou_rat_3:10,
127 reserved34:6, ibdfe_rou_rat_2:10, reserved35:6;
128};
129struct DTMB_CHE_TD_COEFF_BITS {
130 unsigned int td_coeff:24, reserved36:8;
131};
132struct DTMB_CHE_FD_TD_STEPSIZE_ADJ_BITS {
133 unsigned int fd_stepsize_adj:3, td_stepsize_adj:3, reserved37:26;
134};
135struct DTMB_CHE_FD_COEFF_BITS {
136 unsigned int fd_coeff:24, reserved38:8;
137};
138struct DTMB_CHE_FD_LEAKSIZE_BITS {
139 unsigned int fd_leaksize:18, reserved39:14;
140};
141struct DTMB_CHE_IBDFE_CONFIG4_BITS {
142 unsigned int ibdfe_fdbk_iter:4,
143 ibdfe_eqout_iter:4,
144 eq_dist_thr_tps:4,
145 eq_soft_slicer_en:1,
146 reserved40:3,
147 gd_len:5, ibdfe_blank_y:1, reserved41:1, ibdfe_dmsg_start_cnt:9;
148};
149struct DTMB_CHE_IBDFE_CONFIG5_BITS {
150 unsigned int ibdfe_init_snr:12,
151 reserved42:4, eq_init_snr:12, reserved43:4;
152};
153struct DTMB_CHE_IBDFE_CONFIG6_BITS {
154 unsigned int ibdfe_const_thr3:4,
155 ibdfe_const_thr2:4,
156 ibdfe_const_thr1:4,
157 ibdfe_const_thr0:4,
158 ibdfe_threshold3:4,
159 ibdfe_threshold2:4, ibdfe_threshold1:4, ibdfe_threshold0:4;
160};
161struct DTMB_CHE_IBDFE_CONFIG7_BITS {
162 unsigned int ibdfe_pick_thr3:8,
163 ibdfe_pick_thr2:8, ibdfe_pick_thr1:8, ibdfe_pick_thr0:8;
164};
165struct DTMB_CHE_DCM_SC_MC_GD_LEN_BITS {
166 unsigned int dcm_mc_gd_len:6,
167 reserved44:2, dcm_sc_gd_len:6, reserved45:2, eq_dsnr_slc2drm:16;
168};
169struct DTMB_CHE_EQMC_PICK_THR_BITS {
170 unsigned int eqmc_pick_thr3:8,
171 eqmc_pick_thr2:8, eqmc_pick_thr1:8, eqmc_pick_thr0:8;
172};
173struct DTMB_CHE_EQMC_THRESHOLD_BITS {
174 unsigned int eqmc_const_thr3:4,
175 eqmc_const_thr2:4,
176 eqmc_const_thr1:4,
177 eqmc_const_thr0:4,
178 eqmc_threshold3:4,
179 eqmc_threshold2:4, eqmc_threshold1:4, eqmc_threshold0:4;
180};
181struct DTMB_CHE_EQSC_PICK_THR_BITS {
182 unsigned int eqsc_pick_thr3:8,
183 eqsc_pick_thr2:8, eqsc_pick_thr1:8, eqsc_pick_thr0:8;
184};
185struct DTMB_CHE_EQSC_THRESHOLD_BITS {
186 unsigned int eqsc_const_thr3:4,
187 eqsc_const_thr2:4,
188 eqsc_const_thr1:4,
189 eqsc_const_thr0:4,
190 eqsc_threshold3:4,
191 eqsc_threshold2:4, eqsc_threshold1:4, eqsc_threshold0:4;
192};
193struct DTMB_CHE_PROTECT_GD_TPS_BITS {
194 unsigned int pow_norm:10,
195 ncoh_thd_tps:3,
196 coh_thd_tps:3, thr_max:10, protect_gd_tps:5, reserved46:1;
197};
198struct DTMB_CHE_FD_TD_STEPSIZE_THR1_BITS {
199 unsigned int fd_stepsize_thr13:5,
200 fd_stepsize_thr12:5,
201 fd_stepsize_thr11:5,
202 td_stepsize_thr13:5,
203 td_stepsize_thr12:5, td_stepsize_thr11:5, reserved47:2;
204};
205struct DTMB_CHE_TDFD_SWITCH_SYM1_BITS {
206 unsigned int tdfd_switch_sym00:16, tdfd_switch_sym01:16;
207};
208struct DTMB_CHE_TDFD_SWITCH_SYM2_BITS {
209 unsigned int tdfd_switch_sym10:16, tdfd_switch_sym11:16;
210};
211struct DTMB_CHE_EQ_CONFIG_BITS {
212 unsigned int eq_dsnr_h2drm:6,
213 eq_cmp_en:1,
214 eq_imp_setzero_en:1,
215 dcm_sc_bypass:1,
216 dcm_mc_bypass:1,
217 dcm_sc_h_limit:4,
218 dcm_mc_h_limit:4,
219 eqsnr_imp_alp:3, eqsnr_avg_alp:3, dcm_alpha:2, reserved48:6;
220};
221struct DTMB_CHE_EQSC_SNR_IMP_THR1_BITS {
222 unsigned int eqsc_snr_imp_thr1:12, eqsc_snr_imp_thr0:12, reserved49:8;
223};
224struct DTMB_CHE_EQSC_SNR_IMP_THR2_BITS {
225 unsigned int eqsc_snr_imp_thr3:12, eqsc_snr_imp_thr2:12, reserved50:8;
226};
227struct DTMB_CHE_EQMC_SNR_IMP_THR1_BITS {
228 unsigned int eqmc_snr_imp_thr1:12, eqmc_snr_imp_thr0:12, reserved51:8;
229};
230struct DTMB_CHE_EQMC_SNR_IMP_THR2_BITS {
231 unsigned int eqmc_snr_imp_thr3:12, eqmc_snr_imp_thr2:12, reserved52:8;
232};
233struct DTMB_CHE_EQSC_SNR_DROP_THR_BITS {
234 unsigned int eqsc_snr_drop_thr3:8,
235 eqsc_snr_drop_thr2:8, eqsc_snr_drop_thr1:8, eqsc_snr_drop_thr0:8;
236};
237struct DTMB_CHE_EQMC_SNR_DROP_THR_BITS {
238 unsigned int eqmc_snr_drop_thr3:8,
239 eqmc_snr_drop_thr2:8, eqmc_snr_drop_thr1:8, eqmc_snr_drop_thr0:8;
240};
241struct DTMB_CHE_M_CCI_THR_BITS {
242 unsigned int ccidet_mask_rng_tps:5,
243 m_cci_thr_tps:10, m_cci_thr_ma_tps:10, reserved53:7;
244};
245struct DTMB_CHE_TPS_MC_BITS {
246 unsigned int tps_mc_run_tim_limit:10,
247 tps_mc_suc_limit:7, tps_mc_q_thr:7, tps_mc_alpha:3, reserved54:5;
248};
249struct DTMB_CHE_TPS_SC_BITS {
250 unsigned int tps_sc_run_tim_limit:10,
251 tps_sc_suc_limit:7, tps_sc_q_thr:7, tps_sc_alpha:3, reserved55:5;
252};
253struct DTMB_CHE_CHE_SET_FSM_BITS {
254 unsigned int che_open_loop_len:12,
255 reserved56:4,
256 che_set_fsm_st:3, reserved57:1, che_set_fsm_en:1, reserved58:11;
257};
258struct DTMB_CHE_ZERO_NUM_THR_BITS {
259 unsigned int null_frame_thr:16, zero_num_thr:12, reserved59:4;
260};
261struct DTMB_CHE_TIMING_READY_BITS {
262 unsigned int timing_offset:11,
263 reserved60:5, timing_ready:1, reserved61:15;
264};
265
266#endif
267
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