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path: root/drivers/stream_input/tv_frontend/dtv_demod/include/addr_dtmb_front_bit.h (plain)
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1/*
2* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
3*
4* This program is free software; you can redistribute it and/or modify
5* it under the terms of the GNU General Public License as published by
6* the Free Software Foundation; either version 2 of the License, or
7* (at your option) any later version.
8*
9* This program is distributed in the hope that it will be useful, but WITHOUT
10* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12* more details.
13*
14* You should have received a copy of the GNU General Public License along
15* with this program; if not, write to the Free Software Foundation, Inc.,
16* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17*
18* Description:
19*/
20#ifndef __ADDR_DTMB_FRONT_BIT_H__
21#define __ADDR_DTMB_FRONT_BIT_H__
22
23union DTMB_FRONT_AFIFO_ADC_BITS {
24 unsigned int d32;
25 struct {
26 unsigned int afifo_nco_rate:8,
27 afifo_data_format:1,
28 afifo_bypass:1,
29 adc_sample:6,
30 adc_IQ:1,
31 reserved0:15;
32 } b;
33};
34struct DTMB_FRONT_AGC_CONFIG1_BITS {
35 unsigned int agc_target:4,
36 agc_cal_intv:2,
37 reserved1:2,
38 agc_gain_step2:6,
39 reserved2:2,
40 agc_gain_step1:6,
41 reserved3:2,
42 agc_a_filter_coef2:3,
43 reserved4:1,
44 agc_a_filter_coef1:3,
45 reserved5:1;
46};
47struct DTMB_FRONT_AGC_CONFIG2_BITS {
48 unsigned int agc_imp_thresh:4,
49 agc_imp_en:1,
50 agc_iq_exchange:1,
51 reserved6:2,
52 agc_clip_ratio:5,
53 reserved7:3,
54 agc_signal_clip_thr:6,
55 reserved8:2,
56 agc_sd_rate:7,
57 reserved9:1;
58};
59struct DTMB_FRONT_AGC_CONFIG3_BITS {
60 unsigned int agc_rffb_value:11,
61 reserved10:1,
62 agc_iffb_value:11,
63 reserved11:1,
64 agc_gain_step_rf:1,
65 agc_rfgain_freeze:1,
66 agc_tuning_slope:1,
67 agc_rffb_set:1,
68 agc_gain_step_if:1,
69 agc_ifgain_freeze:1,
70 agc_if_only:1,
71 agc_iffb_set:1;
72};
73struct DTMB_FRONT_AGC_CONFIG4_BITS {
74 unsigned int agc_rffb_gain_sat_i:8,
75 agc_rffb_gain_sat:8,
76 agc_iffb_gain_sat_i:8,
77 agc_iffb_gain_sat:8;
78};
79struct DTMB_FRONT_DDC_BYPASS_BITS {
80 unsigned int ddc_phase:25,
81 reserved12:3,
82 ddc_bypass:1,
83 reserved13:3;
84};
85struct DTMB_FRONT_DC_HOLD_BITS {
86 unsigned int dc_hold:1,
87 dc_alpha:3,
88 mobi_det_accu_len:3,
89 reserved14:1,
90 mobi_det_observe_len:3,
91 reserved15:1,
92 channel_static_th:4,
93 channel_portable_th:4,
94 dc_bypass:1,
95 reserved16:3,
96 dc_len:3,
97 reserved17:5;
98};
99struct DTMB_FRONT_DAGC_TARGET_POWER_BITS {
100 unsigned int dagc_target_power_l:8,
101 dagc_target_power_h:8,
102 dagc_target_power_ler:8,
103 dagc_target_power_her:8;
104};
105struct DTMB_FRONT_ACF_BYPASS_BITS {
106 unsigned int coef65:11,
107 reserved18:1,
108 coef66:11,
109 reserved19:1,
110 acf_bypass:1,
111 reserved20:7;
112};
113struct DTMB_FRONT_COEF_SET1_BITS {
114 unsigned int coef63:11,
115 reserved21:1,
116 coef64:11,
117 reserved22:9;
118};
119struct DTMB_FRONT_COEF_SET2_BITS {
120 unsigned int coef62:10,
121 reserved23:22;
122};
123struct DTMB_FRONT_COEF_SET3_BITS {
124 unsigned int coef60:10,
125 reserved24:2,
126 coef61:10,
127 reserved25:10;
128};
129struct DTMB_FRONT_COEF_SET4_BITS {
130 unsigned int coef59:9,
131 reserved26:23;
132};
133struct DTMB_FRONT_COEF_SET5_BITS {
134 unsigned int coef57:9,
135 reserved27:3,
136 coef58:9,
137 reserved28:11;
138};
139struct DTMB_FRONT_COEF_SET6_BITS {
140 unsigned int coef54:8,
141 coef55:8,
142 coef56:8,
143 reserved29:8;
144};
145struct DTMB_FRONT_COEF_SET7_BITS {
146 unsigned int coef53:7,
147 reserved30:25;
148};
149struct DTMB_FRONT_COEF_SET8_BITS {
150 unsigned int coef49:7,
151 reserved31:1,
152 coef50:7,
153 reserved32:1,
154 coef51:7,
155 reserved33:1,
156 coef52:7,
157 reserved34:1;
158};
159struct DTMB_FRONT_COEF_SET9_BITS {
160 unsigned int coef45:7,
161 reserved35:1,
162 coef46:7,
163 reserved36:1,
164 coef47:7,
165 reserved37:1,
166 coef48:7,
167 reserved38:1;
168};
169struct DTMB_FRONT_COEF_SET10_BITS {
170 unsigned int coef42:6,
171 reserved39:2,
172 coef43:6,
173 reserved40:2,
174 coef44:6,
175 reserved41:10;
176};
177struct DTMB_FRONT_COEF_SET11_BITS {
178 unsigned int coef38:6,
179 reserved42:2,
180 coef39:6,
181 reserved43:2,
182 coef40:6,
183 reserved44:2,
184 coef41:6,
185 reserved45:2;
186};
187struct DTMB_FRONT_COEF_SET12_BITS {
188 unsigned int coef34:6,
189 reserved46:2,
190 coef35:6,
191 reserved47:2,
192 coef36:6,
193 reserved48:2,
194 coef37:6,
195 reserved49:2;
196};
197struct DTMB_FRONT_COEF_SET13_BITS {
198 unsigned int coef30:6,
199 reserved50:2,
200 coef31:6,
201 reserved51:2,
202 coef32:6,
203 reserved52:2,
204 coef33:6,
205 reserved53:2;
206};
207struct DTMB_FRONT_COEF_SET14_BITS {
208 unsigned int coef27:5,
209 reserved54:3,
210 coef28:5,
211 reserved55:3,
212 coef29:5,
213 reserved56:11;
214};
215struct DTMB_FRONT_COEF_SET15_BITS {
216 unsigned int coef23:5,
217 reserved57:3,
218 coef24:5,
219 reserved58:3,
220 coef25:5,
221 reserved59:3,
222 coef26:5,
223 reserved60:3;
224};
225struct DTMB_FRONT_COEF_SET16_BITS {
226 unsigned int coef19:5,
227 reserved61:3,
228 coef20:5,
229 reserved62:3,
230 coef21:5,
231 reserved63:3,
232 coef22:5,
233 reserved64:3;
234};
235struct DTMB_FRONT_COEF_SET17_BITS {
236 unsigned int coef15:5,
237 reserved65:3,
238 coef16:5,
239 reserved66:3,
240 coef17:5,
241 reserved67:3,
242 coef18:5,
243 reserved68:3;
244};
245struct DTMB_FRONT_COEF_SET18_BITS {
246 unsigned int coef08:4,
247 coef09:4,
248 coef10:4,
249 coef11:4,
250 coef12:4,
251 coef13:4,
252 coef14:4,
253 reserved69:4;
254};
255struct DTMB_FRONT_COEF_SET19_BITS {
256 unsigned int coef00:4,
257 coef01:4,
258 coef02:4,
259 coef03:4,
260 coef04:4,
261 coef05:4,
262 coef06:4,
263 coef07:4;
264};
265struct DTMB_FRONT_SRC_CONFIG1_BITS {
266 unsigned int src_norm_inrate:24,
267 src_tim_shr:4,
268 src_ted_disable:1,
269 reserved70:3;
270};
271struct DTMB_FRONT_SRC_CONFIG2_BITS {
272 unsigned int src_stable_timeout:4,
273 src_seg_len:3,
274 reserved71:1,
275 src_ted_beta:3,
276 reserved72:1,
277 src_time_err_thr:4,
278 src_time_mu1:5,
279 reserved73:3,
280 src_time_mu2:5,
281 reserved74:3;
282};
283struct DTMB_FRONT_SFIFO_OUT_LEN_BITS {
284 unsigned int sfifo_out_len:4,
285 reserved75:28;
286};
287struct DTMB_FRONT_DAGC_GAIN_BITS {
288 unsigned int dagc_bypass:1,
289 dagc_power_alpha:2,
290 dagc_bw:3,
291 dagc_gain_ctrl:12,
292 dagc_gain_step_er:6,
293 dagc_gain_step:6,
294 reserved76:2;
295};
296struct DTMB_FRONT_IQIB_STEP_BITS {
297 unsigned int iqib_step_b:2,
298 iqib_step_a:2,
299 iqib_period:3,
300 reserved77:1,
301 iqib_bypass:1,
302 reserved78:23;
303};
304struct DTMB_FRONT_IQIB_CONFIG_BITS {
305 unsigned int iqib_set_b:12,
306 iqib_set_a:10,
307 reserved79:2,
308 iqib_set_val:1,
309 iqib_hold:1,
310 reserved80:6;
311};
312struct DTMB_FRONT_ST_CONFIG_BITS {
313 unsigned int st_enable:1,
314 reserved81:3,
315 st_dc_len:3,
316 reserved82:1,
317 st_alpha:3,
318 reserved83:1,
319 st_Q_thrsh:8,
320 st_dist:3,
321 reserved84:1,
322 st_len:5,
323 reserved85:3;
324};
325struct DTMB_FRONT_ST_FREQ_BITS {
326 unsigned int st_freq_v:1,
327 st_freq_i:19,
328 reserved86:12;
329};
330
331#endif
332
generated by cgit at 2024-05-19 19:58:15 (GMT)