path: root/drivers/stream_input/tv_frontend/dtv_demod/include/addr_dtmb_sync_bit.h (plain)
blob: 0aebdd101af2bac8b44a17a68b244f00175bf6d1

1	/*
2	* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
3	*
4	* This program is free software; you can redistribute it and/or modify
5	* it under the terms of the GNU General Public License as published by
6	* the Free Software Foundation; either version 2 of the License, or
7	* (at your option) any later version.
8	*
9	* This program is distributed in the hope that it will be useful, but WITHOUT
10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12	* more details.
13	*
14	* You should have received a copy of the GNU General Public License along
15	* with this program; if not, write to the Free Software Foundation, Inc.,
16	* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17	*
18	* Description:
19	*/
20	#ifndef __ADDR_DTMB_SYNC_BIT_H__
21	#define __ADDR_DTMB_SYNC_BIT_H__
22
23	struct DTMB_SYNC_TS_CFO_PN_VALUE_BITS {
24	unsigned int ts_cfo_pn1_value:16, ts_cfo_pn0_value:16;
25	};
26	struct DTMB_SYNC_TS_CFO_ERR_LIMIT_BITS {
27	unsigned int ts_cfo_err_limit:16, ts_cfo_pn2_value:16;
28	};
29	struct DTMB_SYNC_TS_CFO_PN_MODIFY_BITS {
30	unsigned int ts_cfo_pn1_modify:16, ts_cfo_pn0_modify:16;
31	};
32	struct DTMB_SYNC_TS_GAIN_BITS {
33	unsigned int ts_gain:2,
34	reserved0:2,
35	ts_sat_shift:3,
36	reserved1:1,
37	ts_fixpn_en:1,
38	ts_fixpn:2, reserved2:1, ts_cfo_cut:4, ts_cfo_pn2_modify:16;
39	};
40	struct DTMB_SYNC_FE_CONFIG_BITS {
41	unsigned int fe_lock_len:4,
42	fe_sat_shift:3, reserved3:1, fe_cut:4, reserved4:4, fe_modify:16;
43	};
44	struct DTMB_SYNC_PNPHASE_OFFSET_BITS {
45	unsigned int pnphase_offset2:4,
46	pnphase_offset1:4, pnphase_offset0:4, reserved5:20;
47	};
48	struct DTMB_SYNC_PNPHASE_CONFIG_BITS {
49	unsigned int pnphase_gain:2,
50	reserved6:2,
51	pnphase_sat_shift:4, pnphase_cut:4, reserved7:4, pnphase_modify:16;
52	};
53	struct DTMB_SYNC_SFO_SFO_PN0_MODIFY_BITS {
54	unsigned int sfo_cfo_pn0_modify:16, sfo_sfo_pn0_modify:16;
55	};
56	struct DTMB_SYNC_SFO_SFO_PN1_MODIFY_BITS {
57	unsigned int sfo_cfo_pn1_modify:16, sfo_sfo_pn1_modify:16;
58	};
59	struct DTMB_SYNC_SFO_SFO_PN2_MODIFY_BITS {
60	unsigned int sfo_cfo_pn2_modify:16, sfo_sfo_pn2_modify:16;
61	};
62	struct DTMB_SYNC_SFO_CONFIG_BITS {
63	unsigned int sfo_sat_shift:4,
64	sfo_gain:2,
65	reserved8:2,
66	sfo_dist:2,
67	reserved9:2,
68	sfo_cfo_cut:4, sfo_sfo_cut:4, sfo_cci_th:4, reserved10:8;
69	};
70	struct DTMB_SYNC_TRACK_CFO_MAX_BITS {
71	unsigned int track_cfo_max:8,
72	track_sfo_max:8, track_max_en:1, ctrl_fe_to_th:4, reserved11:11;
73	};
74	struct DTMB_SYNC_CCI_DAGC_CONFIG1_BITS {
75	unsigned int cci_dagc_bypass:1,
76	cci_dagc_power_alpha:2,
77	cci_dagc_bw:3,
78	cci_dagc_gain_ctrl:12,
79	cci_dagc_gain_step_er:6, cci_dagc_gain_step:6, reserved12:2;
80	};
81	struct DTMB_SYNC_CCI_DAGC_CONFIG2_BITS {
82	unsigned int cci_dagc_target_power_l:8,
83	cci_dagc_target_power_h:8,
84	cci_dagc_target_power_ler:8, cci_dagc_target_power_her:8;
85	};
86	struct DTMB_SYNC_CCI_RP_BITS {
87	unsigned int cci_rpsq_n:10, reserved13:2, cci_rp_n:13, reserved14:7;
88	};
89	struct DTMB_SYNC_CCI_DET_THRES_BITS {
90	unsigned int cci_avr_times:5,
91	reserved15:3, cci_det_thres:3, reserved16:21;
92	};
93	struct DTMB_SYNC_CCI_NOTCH1_CONFIG1_BITS {
94	unsigned int cci_notch1_a1:10,
95	reserved17:2, cci_notch1_en:1, reserved18:19;
96	};
97	struct DTMB_SYNC_CCI_NOTCH1_CONFIG2_BITS {
98	unsigned int cci_notch1_b1:10,
99	reserved19:2, cci_notch1_a2:10, reserved20:10;
100	};
101	struct DTMB_SYNC_CCI_NOTCH2_CONFIG1_BITS {
102	unsigned int cci_notch2_a1:10,
103	reserved21:2, cci_notch2_en:1, reserved22:3, cci_mpthres:16;
104	};
105	struct DTMB_SYNC_CCI_NOTCH2_CONFIG2_BITS {
106	unsigned int cci_notch2_b1:10,
107	reserved23:2, cci_notch2_a2:10, reserved24:10;
108	};
109
110	#endif
111