blob: c12d26f66c0f05ef5aa03e428dfa44969e6701ea
| 1 | /* |
| 2 | * Copyright (C) 2017 Amlogic, Inc. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; either version 2 of the License, or |
| 7 | * (at your option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License along |
| 15 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 16 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 17 | * |
| 18 | * Description: |
| 19 | */ |
| 20 | #ifndef __ADDR_DTMB_TOP_H__ |
| 21 | #define __ADDR_DTMB_TOP_H__ |
| 22 | |
| 23 | #include "addr_dtmb_top_bit.h" |
| 24 | #include "addr_dtmb_sync.h" |
| 25 | #include "addr_dtmb_sync_bit.h" |
| 26 | #include "addr_dtmb_che.h" |
| 27 | #include "addr_dtmb_che_bit.h" |
| 28 | #include "addr_dtmb_front.h" |
| 29 | #include "addr_dtmb_front_bit.h" |
| 30 | |
| 31 | #define DTMB_DEMOD_BASE DEMOD_REG_ADDR(0x0) |
| 32 | #define DTMB_TOP_ADDR(x) (DTMB_DEMOD_BASE + (x << 2)) |
| 33 | |
| 34 | #define DTMB_TOP_CTRL_SW_RST DTMB_TOP_ADDR(0x1) |
| 35 | #define DTMB_TOP_TESTBUS DTMB_TOP_ADDR(0x2) |
| 36 | #define DTMB_TOP_TB DTMB_TOP_ADDR(0x3) |
| 37 | #define DTMB_TOP_TB_V DTMB_TOP_ADDR(0x4) |
| 38 | #define DTMB_TOP_TB_ADDR_BEGIN DTMB_TOP_ADDR(0x5) |
| 39 | #define DTMB_TOP_TB_ADDR_END DTMB_TOP_ADDR(0x6) |
| 40 | #define DTMB_TOP_CTRL_ENABLE DTMB_TOP_ADDR(0x7) |
| 41 | #define DTMB_TOP_CTRL_LOOP DTMB_TOP_ADDR(0x8) |
| 42 | #define DTMB_TOP_CTRL_FSM DTMB_TOP_ADDR(0x9) |
| 43 | #define DTMB_TOP_CTRL_AGC DTMB_TOP_ADDR(0xa) |
| 44 | #define DTMB_TOP_CTRL_TS_SFO_CFO DTMB_TOP_ADDR(0xb) |
| 45 | #define DTMB_TOP_CTRL_FEC DTMB_TOP_ADDR(0xc) |
| 46 | #define DTMB_TOP_CTRL_INTLV_TIME DTMB_TOP_ADDR(0xd) |
| 47 | #define DTMB_TOP_CTRL_DAGC_CCI DTMB_TOP_ADDR(0xe) |
| 48 | #define DTMB_TOP_CTRL_TPS DTMB_TOP_ADDR(0xf) |
| 49 | #define DTMB_TOP_TPS_BIT DTMB_TOP_ADDR(0x10) |
| 50 | #define DTMB_TOP_CCI_FLG DTMB_TOP_ADDR(0xc7) |
| 51 | #define DTMB_TOP_TESTBUS_OUT DTMB_TOP_ADDR(0xc8) |
| 52 | #define DTMB_TOP_TBUS_DC_ADDR DTMB_TOP_ADDR(0xc9) |
| 53 | #define DTMB_TOP_FRONT_IQIB_CHECK DTMB_TOP_ADDR(0xca) |
| 54 | #define DTMB_TOP_SYNC_TS DTMB_TOP_ADDR(0xcb) |
| 55 | #define DTMB_TOP_SYNC_PNPHASE DTMB_TOP_ADDR(0xcd) |
| 56 | #define DTMB_TOP_CTRL_DDC_ICFO DTMB_TOP_ADDR(0xd2) |
| 57 | #define DTMB_TOP_CTRL_DDC_FCFO DTMB_TOP_ADDR(0xd3) |
| 58 | #define DTMB_TOP_CTRL_FSM_STATE0 DTMB_TOP_ADDR(0xd4) |
| 59 | #define DTMB_TOP_CTRL_FSM_STATE1 DTMB_TOP_ADDR(0xd5) |
| 60 | #define DTMB_TOP_CTRL_FSM_STATE2 DTMB_TOP_ADDR(0xd6) |
| 61 | #define DTMB_TOP_CTRL_FSM_STATE3 DTMB_TOP_ADDR(0xd7) |
| 62 | #define DTMB_TOP_CTRL_TS2 DTMB_TOP_ADDR(0xd8) |
| 63 | #define DTMB_TOP_FRONT_AGC DTMB_TOP_ADDR(0xd9) |
| 64 | #define DTMB_TOP_FRONT_DAGC DTMB_TOP_ADDR(0xda) |
| 65 | #define DTMB_TOP_FEC_TIME_STS DTMB_TOP_ADDR(0xdb) |
| 66 | #define DTMB_TOP_FEC_LDPC_STS DTMB_TOP_ADDR(0xdc) |
| 67 | #define DTMB_TOP_FEC_LDPC_IT_AVG DTMB_TOP_ADDR(0xdd) |
| 68 | #define DTMB_TOP_FEC_LDPC_UNC_ACC DTMB_TOP_ADDR(0xde) |
| 69 | #define DTMB_TOP_FEC_BCH_ACC DTMB_TOP_ADDR(0xdf) |
| 70 | #define DTMB_TOP_CTRL_ICFO_ALL DTMB_TOP_ADDR(0xe0) |
| 71 | #define DTMB_TOP_CTRL_FCFO_ALL DTMB_TOP_ADDR(0xe1) |
| 72 | #define DTMB_TOP_CTRL_SFO_ALL DTMB_TOP_ADDR(0xe2) |
| 73 | #define DTMB_TOP_FEC_LOCK_SNR DTMB_TOP_ADDR(0xe3) |
| 74 | #define DTMB_TOP_CHE_SEG_FACTOR DTMB_TOP_ADDR(0xe4) |
| 75 | #define DTMB_TOP_CTRL_CHE_WORKCNT DTMB_TOP_ADDR(0xe5) |
| 76 | #define DTMB_TOP_CHE_OBS_STATE1 DTMB_TOP_ADDR(0xe6) |
| 77 | #define DTMB_TOP_CHE_OBS_STATE2 DTMB_TOP_ADDR(0xe7) |
| 78 | #define DTMB_TOP_CHE_OBS_STATE3 DTMB_TOP_ADDR(0xe8) |
| 79 | #define DTMB_TOP_CHE_OBS_STATE4 DTMB_TOP_ADDR(0xe9) |
| 80 | #define DTMB_TOP_CHE_OBS_STATE5 DTMB_TOP_ADDR(0xea) |
| 81 | #define DTMB_TOP_SYNC_CCI_NF1 DTMB_TOP_ADDR(0xee) |
| 82 | #define DTMB_TOP_SYNC_CCI_NF2 DTMB_TOP_ADDR(0xef) |
| 83 | #define DTMB_TOP_SYNC_CCI_NF2_POSITION DTMB_TOP_ADDR(0xf0) |
| 84 | #define DTMB_TOP_CTRL_SYS_OFDM_CNT DTMB_TOP_ADDR(0xf1) |
| 85 | #define DTMB_TOP_CTRL_TPS_Q_FINAL DTMB_TOP_ADDR(0xf2) |
| 86 | #define DTMB_TOP_FRONT_DC DTMB_TOP_ADDR(0xf3) |
| 87 | #define DTMB_TOP_CHE_DEBUG DTMB_TOP_ADDR(0xf6) |
| 88 | #define DTMB_TOP_CTRL_TOTPS_READY_CNT DTMB_TOP_ADDR(0xff) |
| 89 | |
| 90 | #endif |
| 91 |