path: root/drivers/stream_input/tv_frontend/dtv_demod/include/addr_dtmb_top_bit.h (plain)
blob: 63233c4e49d9a6fb95aaaf24adc235ff3fa3b0e9

1	/*
2	* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
3	*
4	* This program is free software; you can redistribute it and/or modify
5	* it under the terms of the GNU General Public License as published by
6	* the Free Software Foundation; either version 2 of the License, or
7	* (at your option) any later version.
8	*
9	* This program is distributed in the hope that it will be useful, but WITHOUT
10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12	* more details.
13	*
14	* You should have received a copy of the GNU General Public License along
15	* with this program; if not, write to the Free Software Foundation, Inc.,
16	* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17	*
18	* Description:
19	*/
20	#ifndef __ADDR_DTMB_TOP_BIT_H__
21	#define __ADDR_DTMB_TOP_BIT_H__
22
23	union DTMB_TOP_CTRL_SW_RST_BITS {
24	unsigned int d32;
25	struct {
26	unsigned int ctrl_sw_rst:1, ctrl_sw_rst_noreg:1, reserved0:30;
27	} b;
28	};
29	struct DTMB_TOP_TESTBUS_BITS {
30	unsigned int testbus_addr:16, testbus_en:1, reserved1:15;
31	};
32	struct DTMB_TOP_TB_BITS {
33	unsigned int tb_act_width:5,
34	reserved2:3,
35	tb_dc_mk:3,
36	reserved3:1, tb_capture_stop:1, tb_self_test:1, reserved4:18;
37	};
38	struct DTMB_TOP_CTRL_ENABLE_BITS {
39	unsigned int ctrl_enable:24, reserved5:8;
40	};
41	struct DTMB_TOP_CTRL_LOOP_BITS {
42	unsigned int ctrl_src_pnphase_loop:1,
43	ctrl_src_sfo_loop:1,
44	ctrl_ddc_fcfo_loop:1, ctrl_ddc_icfo_loop:1, reserved6:28;
45	};
46	struct DTMB_TOP_CTRL_FSM_BITS {
47	unsigned int ctrl_fsm_state:5,
48	reserved7:3,
49	ctrl_fsm_v:1, reserved8:3, ctrl_reset_state:4, reserved9:16;
50	};
51	struct DTMB_TOP_CTRL_AGC_BITS {
52	unsigned int ctrl_fast_agc:1,
53	ctrl_agc_bypass:1,
54	ts_cfo_bypass:1, sfo_strong0_bypass:1, reserved10:28;
55	};
56	struct DTMB_TOP_CTRL_TS_SFO_CFO_BITS {
57	unsigned int ctrl_ts_q:10,
58	reserved11:2,
59	ctrl_pnphase_q:7, reserved12:1, ctrl_sfo_q:4, ctrl_cfo_q:8;
60	};
61	struct DTMB_TOP_CTRL_FEC_BITS {
62	unsigned int reserved13:8,
63	ctrl_ts_to_th:4,
64	ctrl_pnphase_to_th:4,
65	ctrl_sfo_to_th:4,
66	ctrl_fe_to_th:4, ctrl_che_to_th:4, ctrl_fec_to_th:4;
67	};
68	struct DTMB_TOP_CTRL_INTLV_TIME_BITS {
69	unsigned int ctrl_intlv720_time:12, ctrl_intlv240_time:12, reserved14:8;
70	};
71	struct DTMB_TOP_CTRL_DAGC_CCI_BITS {
72	unsigned int dagc_mode:2,
73	cci_dagc_mode:2,
74	cci_bypass:1,
75	fe_bypass:1,
76	reserved15:1,
77	new_sync1:1, new_sync2:1, fec_inzero_check:1, reserved16:22;
78	};
79	struct DTMB_TOP_CTRL_TPS_BITS {
80	unsigned int sfo_gain:2,
81	freq_reverse:1,
82	qam4_nr:1,
83	intlv_mode:1,
84	code_rate:2,
85	constell:2,
86	tps_carrier_mode:1,
87	freq_reverse_known:1, tps_known:1, ctrl_tps_to_th:4, reserved17:16;
88	};
89	struct DTMB_TOP_CCI_FLG_BITS {
90	unsigned int cci_flg_cnt:8, m_cci_ready:1, reserved18:23;
91	};
92	struct DTMB_TOP_FRONT_IQIB_CHECK_BITS {
93	unsigned int front_iqib_check_b:12,
94	front_iqib_check_a:10, reserved19:10;
95	};
96	struct DTMB_TOP_SYNC_TS_BITS {
97	unsigned int sync_ts_idx:2, sync_ts_pos:13, sync_ts_q:10, reserved20:7;
98	};
99	struct DTMB_TOP_SYNC_PNPHASE_BITS {
100	unsigned int sync_pnphase_max_q_idx:2,
101	sync_pnphase:8, sync_pnphase_max_q:7, reserved21:15;
102	};
103	struct DTMB_TOP_CTRL_DDC_ICFO_BITS {
104	unsigned int ctrl_ddc_icfo:20, reserved22:12;
105	};
106	struct DTMB_TOP_CTRL_DDC_FCFO_BITS {
107	unsigned int ctrl_src_sfo:17, ctrl_ddc_fcfo:14, reserved23:1;
108	};
109	struct DTMB_TOP_CTRL_TS2_BITS {
110	unsigned int ctrl_ts2_workcnt:8,
111	ctrl_pnphase_workcnt:8, ctrl_sfo_workcnt:8, sync_fe_workcnt:8;
112	};
113	struct DTMB_TOP_FRONT_AGC_BITS {
114	unsigned int front_agc_if_gain:11,
115	front_agc_rf_gain:11, front_agc_power:10;
116	};
117	struct DTMB_TOP_FRONT_DAGC_BITS {
118	unsigned int front_dagc_power:8, front_dagc_gain:12, reserved24:12;
119	};
120	struct DTMB_TOP_FEC_LDPC_IT_AVG_BITS {
121	unsigned int fec_ldpc_it_avg:16, fec_ldpc_per_rpt:13, reserved25:3;
122	};
123	struct DTMB_TOP_CTRL_ICFO_ALL_BITS {
124	unsigned int ctrl_icfo_all:20, reserved26:12;
125	};
126	struct DTMB_TOP_CTRL_FCFO_ALL_BITS {
127	unsigned int ctrl_fcfo_all:20, reserved27:12;
128	};
129	struct DTMB_TOP_CTRL_SFO_ALL_BITS {
130	unsigned int ctrl_sfo_all:25, reserved28:7;
131	};
132	struct DTMB_TOP_FEC_LOCK_SNR_BITS {
133	unsigned int che_snr:14,
134	fec_lock:1, reserved29:1, che_snr_average:14, reserved30:2;
135	};
136	struct DTMB_TOP_CHE_SEG_FACTOR_BITS {
137	unsigned int che_seg_factor:14, reserved31:18;
138	};
139	struct DTMB_TOP_CTRL_CHE_WORKCNT_BITS {
140	unsigned int ctrl_che_workcnt:8,
141	ctrl_fec_workcnt:8,
142	ctrl_constell:2,
143	ctrl_code_rate:2,
144	ctrl_intlv_mode:1,
145	ctrl_qam4_nr:1, ctrl_freq_reverse:1, reserved32:9;
146	};
147	struct DTMB_TOP_SYNC_CCI_NF1_BITS {
148	unsigned int sync_cci_nf1_b1:10,
149	sync_cci_nf1_a2:10, sync_cci_nf1_a1:10, reserved33:2;
150	};
151	struct DTMB_TOP_SYNC_CCI_NF2_BITS {
152	unsigned int sync_cci_nf2_b1:10,
153	sync_cci_nf2_a2:10, sync_cci_nf2_a1:10, reserved34:2;
154	};
155	struct DTMB_TOP_SYNC_CCI_NF2_POSITION_BITS {
156	unsigned int sync_cci_nf2_position:11,
157	sync_cci_nf1_position:11,
158	sync_cci_nf2_det:1, sync_cci_nf1_det:1, reserved35:8;
159	};
160	struct DTMB_TOP_CTRL_SYS_OFDM_CNT_BITS {
161	unsigned int ctrl_sys_ofdm_cnt:8,
162	mobi_det_power_var:19,
163	reserved36:1, ctrl_che_working_state:2, reserved37:2;
164	};
165	struct DTMB_TOP_CTRL_TPS_Q_FINAL_BITS {
166	unsigned int ctrl_tps_q_final:7, ctrl_tps_suc_cnt:7, reserved38:18;
167	};
168	struct DTMB_TOP_FRONT_DC_BITS {
169	unsigned int front_dc_q:10, front_dc_i:10, reserved39:12;
170	};
171	struct DTMB_TOP_CTRL_TOTPS_READY_CNT_BITS {
172	unsigned int ctrl_dead_lock_det:1,
173	ctrl_dead_lock:1,
174	reserved40:2,
175	ctrl_dead_cnt:4, reserved41:8, ctrl_totps_ready_cnt:16;
176	};
177
178	#endif
179