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path: root/drivers/stream_input/tv_frontend/dtv_demod/include/demod_func.h (plain)
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1/*
2* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
3*
4* This program is free software; you can redistribute it and/or modify
5* it under the terms of the GNU General Public License as published by
6* the Free Software Foundation; either version 2 of the License, or
7* (at your option) any later version.
8*
9* This program is distributed in the hope that it will be useful, but WITHOUT
10* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12* more details.
13*
14* You should have received a copy of the GNU General Public License along
15* with this program; if not, write to the Free Software Foundation, Inc.,
16* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17*
18* Description:
19*/
20#ifdef DEMOD_FUNC_H
21#else
22#define DEMOD_FUNC_H
23
24#include <linux/types.h>
25/* #include <mach/am_regs.h> */
26/*#include <mach/register.h>
27 * #include <mach/avosstyle_io.h>
28 #include <mach/io.h>
29*/
30#include <linux/dvb/aml_demod.h>
31#include "aml_fe.h"
32#include "amlfrontend.h"
33#include "addr_dtmb_top.h"
34#include "c_stb_define.h"
35#include "c_stb_regs_define.h"
36#include <linux/io.h>
37
38/* #define G9_TV */
39#define GX_TV
40#define safe_addr
41
42#define PWR_ON 1
43#define PWR_OFF 0
44
45#define dtmb_mobile_mode
46
47
48/* void __iomem *meson_reg_demod_map[1024]; */
49
50#define IO_CBUS_PHY_BASE (0xc0800000)
51
52#ifdef safe_addr
53#define IO_DEMOD_BASE (0xc8844000)
54#define IO_AOBUS_BASE (0xc8100000)
55#define IO_HIU_BASE (0xc883c000)
56#else
57#define IO_DEMOD_BASE (0xda844000)
58#define IO_AOBUS_BASE (0xda100000)
59#define IO_HIU_BASE (0xda83c000)
60#endif
61
62#define DEMOD_REG_OFFSET(reg) (reg & 0xfffff)
63#define DEMOD_REG_ADDR(reg) (IO_DEMOD_BASE + DEMOD_REG_OFFSET(reg))
64
65#define DEMOD_CBUS_REG_OFFSET(reg) (reg << 2)
66#define DEMOD_CBUS_REG_ADDR(reg) (IO_CBUS_PHY_BASE + \
67 DEMOD_CBUS_REG_OFFSET(reg))
68
69#define DEMOD_AOBUS_REG_OFFSET(reg) ((reg))
70#define DEMOD_AOBUS_REG_ADDR(reg) (IO_AOBUS_BASE + \
71 DEMOD_AOBUS_REG_OFFSET(reg))
72
73/* #define DEMOD_BASE APB_REG_ADDR(0x20000) */
74#define DEMOD_BASE DEMOD_REG_ADDR(0x0) /* 0xc8020000 */
75
76/* #define DEMOD_BASE 0xc8020000 */
77#define DTMB_BASE (DEMOD_BASE + 0x000)
78#define DVBT_BASE (DEMOD_BASE + 0x000)
79#define ISDBT_BASE (DEMOD_BASE + 0x000)
80#define QAM_BASE (DEMOD_BASE + 0x400)
81#define ATSC_BASE (DEMOD_BASE + 0x800)
82#define DEMOD_CFG_BASE (DEMOD_BASE + 0xC00)
83
84/* #ifdef TXL_TV */
85#define TXLTV_ADC_RESET_VALUE 0xca6a2110 /* 0xce7a2110 */
86#define TXLTV_ADC_REG1_VALUE 0x5d414260
87#define TXLTV_ADC_REG2_VALUE 0x5ba00384 /* 0x34e0bf81 */
88#define TXLTV_ADC_REG2_VALUE_CRY 0x34e0bf81
89#define TXLTV_ADC_REG3_VALUE 0x4a6a2110 /* 0x4e7a2110 */
90#define TXLTV_ADC_REG4_VALUE 0x02913004
91#define TXLTV_ADC_REG4_CRY_VALUE 0x301
92#define TXLTV_ADC_REG7_VALUE 0x00102038
93#define TXLTV_ADC_REG8_VALUE 0x00000406
94#define TXLTV_ADC_REG9_VALUE 0x00082183
95#define TXLTV_ADC_REGA_VALUE 0x80480240
96#define TXLTV_ADC_REGB_VALUE 0x22000442
97#define TXLTV_ADC_REGC_VALUE 0x00034a00
98#define TXLTV_ADC_REGD_VALUE 0x00005000
99#define TXLTV_ADC_REGE_VALUE 0x00000200
100
101
102/* DADC DPLL */
103#define ADC_REG1 (IO_HIU_BASE + (0xaa << 2))
104#define ADC_REG2 (IO_HIU_BASE + (0xab << 2))
105#define ADC_REG3 (IO_HIU_BASE + (0xac << 2))
106#define ADC_REG4 (IO_HIU_BASE + (0xad << 2))
107
108#define ADC_REG5 (IO_HIU_BASE + (0x73 << 2))
109#define ADC_REG6 (IO_HIU_BASE + (0x74 << 2))
110
111#define ADC_REGB (IO_HIU_BASE + (0xaf << 2))
112#define ADC_REGC (IO_HIU_BASE + (0x9e << 2))
113#define ADC_REGD (IO_HIU_BASE + (0x9f << 2))
114
115/* DADC REG */
116#define ADC_REG7 (IO_HIU_BASE + (0x27 << 2))
117#define ADC_REG8 (IO_HIU_BASE + (0x28 << 2))
118#define ADC_REG9 (IO_HIU_BASE + (0x2a << 2))
119#define ADC_REGA (IO_HIU_BASE + (0x2b << 2))
120#define ADC_REGE (IO_HIU_BASE + (0xbd << 2))
121
122/* #endif */
123
124
125/* #ifdef GX_TV */
126
127#define ADC_RESET_VALUE 0x8a2a2110 /* 0xce7a2110 */
128#define ADC_REG1_VALUE 0x00100228
129#define ADC_REG2_VALUE 0x34e0bf80 /* 0x34e0bf81 */
130#define ADC_REG2_VALUE_CRY 0x34e0bf81
131#define ADC_REG3_VALUE 0x0a2a2110 /* 0x4e7a2110 */
132#define ADC_REG4_VALUE 0x02933800
133#define ADC_REG4_CRY_VALUE 0x301
134#define ADC_REG7_VALUE 0x01411036
135#define ADC_REG8_VALUE 0x00000000
136#define ADC_REG9_VALUE 0x00430036
137#define ADC_REGA_VALUE 0x80480240
138#if 0
139/* DADC DPLL */
140#define ADC_REG1 (IO_HIU_BASE + (0xaa << 2))
141#define ADC_REG2 (IO_HIU_BASE + (0xab << 2))
142#define ADC_REG3 (IO_HIU_BASE + (0xac << 2))
143#define ADC_REG4 (IO_HIU_BASE + (0xad << 2))
144
145#define ADC_REG5 (IO_HIU_BASE + (0x73 << 2))
146#define ADC_REG6 (IO_HIU_BASE + (0x74 << 2))
147
148/* DADC REG */
149#define ADC_REG7 (IO_HIU_BASE + (0x27 << 2))
150#define ADC_REG8 (IO_HIU_BASE + (0x28 << 2))
151#define ADC_REG9 (IO_HIU_BASE + (0x2a << 2))
152#define ADC_REGA (IO_HIU_BASE + (0x2b << 2))
153#endif
154/* #endif */
155
156#ifdef G9_TV
157
158#define ADC_RESET_VALUE 0x8a2a2110 /* 0xce7a2110 */
159#define ADC_REG1_VALUE 0x00100228
160#define ADC_REG2_VALUE 0x34e0bf80 /* 0x34e0bf81 */
161#define ADC_REG2_VALUE_CRY 0x34e0bf81
162#define ADC_REG3_VALUE 0x0a2a2110 /* 0x4e7a2110 */
163#define ADC_REG4_VALUE 0x02933800
164#define ADC_REG4_CRY_VALUE 0x301
165#define ADC_REG7_VALUE 0x01411036
166#define ADC_REG8_VALUE 0x00000000
167#define ADC_REG9_VALUE 0x00430036
168#define ADC_REGA_VALUE 0x80480240
169
170/* DADC DPLL */
171#define ADC_REG1 0x10aa
172#define ADC_REG2 0x10ab
173#define ADC_REG3 0x10ac
174#define ADC_REG4 0x10ad
175
176#define ADC_REG5 0x1073
177#define ADC_REG6 0x1074
178
179/* DADC REG */
180#define ADC_REG7 0x1027
181#define ADC_REG8 0x1028
182#define ADC_REG9 0x102a
183#define ADC_REGA 0x102b
184#endif
185
186#ifdef M6_TV
187#define ADC_REG1_VALUE 0x003b0232
188#define ADC_REG2_VALUE 0x814d3928
189#define ADC_REG3_VALUE 0x6b425012
190#define ADC_REG4_VALUE 0x101
191#define ADC_REG4_CRY_VALUE 0x301
192#define ADC_REG5_VALUE 0x70b
193#define ADC_REG6_VALUE 0x713
194
195#define ADC_REG1 0x10aa
196#define ADC_REG2 0x10ab
197#define ADC_REG3 0x10ac
198#define ADC_REG4 0x10ad
199#define ADC_REG5 0x1073
200#define ADC_REG6 0x1074
201#endif
202
203#define DEMOD_REG1_VALUE 0x0000d007
204#define DEMOD_REG2_VALUE 0x2e805400
205#define DEMOD_REG3_VALUE 0x201
206
207#define DEMOD_REG1 (DEMOD_BASE + 0xc00)
208#define DEMOD_REG2 (DEMOD_BASE + 0xc04)
209#define DEMOD_REG3 (DEMOD_BASE + 0xc08)
210#define DEMOD_REG4 (DEMOD_BASE + 0xc0c)
211
212/* #define Wr(addr, data) WRITE_CBUS_REG(addr, data)*/
213/* #define Rd(addr) READ_CBUS_REG(addr) */
214
215/*#define Wr(addr, data) *(volatile unsigned long *)(addr) = (data)*/
216/*#define Rd(addr) *(volatile unsigned long *)(addr)*/
217
218enum {
219 enable_mobile,
220 disable_mobile
221};
222
223enum {
224 OPEN_TIME_EQ,
225 CLOSE_TIME_EQ
226};
227
228enum {
229 AMLOGIC_DTMB_STEP0,
230 AMLOGIC_DTMB_STEP1,
231 AMLOGIC_DTMB_STEP2,
232 AMLOGIC_DTMB_STEP3,
233 AMLOGIC_DTMB_STEP4,
234 AMLOGIC_DTMB_STEP5, /* time eq */
235 AMLOGIC_DTMB_STEP6, /* set normal mode sc */
236 AMLOGIC_DTMB_STEP7,
237 AMLOGIC_DTMB_STEP8, /* set time eq mode */
238 AMLOGIC_DTMB_STEP9, /* reset */
239 AMLOGIC_DTMB_STEP10, /* set normal mode mc */
240 AMLOGIC_DTMB_STEP11,
241};
242
243enum {
244 DTMB_IDLE = 0,
245 DTMB_AGC_READY = 1,
246 DTMB_TS1_READY = 2,
247 DTMB_TS2_READY = 3,
248 DTMB_FE_READY = 4,
249 DTMB_PNPHASE_READY = 5,
250 DTMB_SFO_INIT_READY = 6,
251 DTMB_TS3_READY = 7,
252 DTMB_PM_INIT_READY = 8,
253 DTMB_CHE_INIT_READY = 9,
254 DTMB_FEC_READY = 10
255};
256
257/* i2c functions */
258/* int aml_i2c_sw_test_bus(struct aml_demod_i2c *adap, char *name); */
259int am_demod_i2c_xfer(struct aml_demod_i2c *adap, struct i2c_msg *msgs,
260 int num);
261int init_tuner_fj2207(struct aml_demod_sta *demod_sta,
262 struct aml_demod_i2c *adap);
263int set_tuner_fj2207(struct aml_demod_sta *demod_sta,
264 struct aml_demod_i2c *adap);
265
266int get_fj2207_ch_power(void);
267int tuner_get_ch_power(struct aml_fe_dev *adap);
268int tda18273_tuner_set_frequnecy(unsigned int dwFrequency,
269 unsigned int dwStandard);
270int dtmb_get_power_strength(int agc_gain);
271
272
273int tuner_set_ch(struct aml_demod_sta *demod_sta,
274 struct aml_demod_i2c *demod_i2c);
275
276/* dvbt */
277int dvbt_set_ch(struct aml_demod_sta *demod_sta,
278 struct aml_demod_i2c *demod_i2c,
279 struct aml_demod_dvbt *demod_dvbt);
280
281struct demod_status_ops {
282 int (*get_status)(struct aml_demod_sta *demod_sta,
283 struct aml_demod_i2c *demod_i2c);
284 int (*get_ber)(struct aml_demod_sta *demod_sta,
285 struct aml_demod_i2c *demod_i2c);
286 int (*get_snr)(struct aml_demod_sta *demod_sta,
287 struct aml_demod_i2c *demod_i2c);
288 int (*get_strength)(struct aml_demod_sta *demod_sta,
289 struct aml_demod_i2c *demod_i2c);
290 int (*get_ucblocks)(struct aml_demod_sta *demod_sta,
291 struct aml_demod_i2c *demod_i2c);
292};
293
294struct demod_status_ops *dvbt_get_status_ops(void);
295
296/* dvbc */
297
298int dvbc_set_ch(struct aml_demod_sta *demod_sta,
299 struct aml_demod_i2c *demod_i2c,
300 struct aml_demod_dvbc *demod_dvbc);
301int dvbc_status(struct aml_demod_sta *demod_sta,
302 struct aml_demod_i2c *demod_i2c,
303 struct aml_demod_sts *demod_sts);
304int dvbc_isr_islock(void);
305void dvbc_isr(struct aml_demod_sta *demod_sta);
306u32 dvbc_set_qam_mode(unsigned char mode);
307u32 dvbc_get_status(void);
308u32 dvbc_set_auto_symtrack(void);
309int dvbc_timer_init(void);
310void dvbc_timer_exit(void);
311int dvbc_cci_task(void *data);
312int dvbc_get_cci_task(void);
313void dvbc_create_cci_task(void);
314void dvbc_kill_cci_task(void);
315
316/* atsc */
317
318int atsc_set_ch(struct aml_demod_sta *demod_sta,
319 struct aml_demod_i2c *demod_i2c,
320 struct aml_demod_atsc *demod_atsc);
321int check_atsc_fsm_status(void);
322
323void atsc_write_reg(int reg_addr, int reg_data);
324
325unsigned long atsc_read_reg(int reg_addr);
326
327unsigned long atsc_read_iqr_reg(void);
328
329int atsc_qam_set(fe_modulation_t mode);
330
331void qam_initial(int qam_id);
332
333/* dtmb */
334
335int dtmb_set_ch(struct aml_demod_sta *demod_sta,
336 struct aml_demod_i2c *demod_i2c,
337 struct aml_demod_dtmb *demod_atsc);
338
339void dtmb_reset(void);
340
341int dtmb_check_status_gxtv(struct dvb_frontend *fe);
342int dtmb_check_status_txl(struct dvb_frontend *fe);
343
344
345void dtmb_write_reg(int reg_addr, int reg_data);
346int dtmb_read_reg(int reg_addr);
347void dtmb_register_reset(void);
348
349/* demod functions */
350unsigned long apb_read_reg_collect(unsigned long addr);
351void apb_write_reg_collect(unsigned int addr, unsigned int data);
352void apb_write_reg(unsigned int reg, unsigned int val);
353unsigned long apb_read_reg_high(unsigned long addr);
354unsigned long apb_read_reg(unsigned long reg);
355int app_apb_write_reg(int addr, int data);
356int app_apb_read_reg(int addr);
357
358void demod_set_cbus_reg(unsigned int data, unsigned int addr);
359unsigned int demod_read_cbus_reg(unsigned int addr);
360void demod_set_demod_reg(unsigned int data, unsigned int addr);
361unsigned int demod_read_demod_reg(unsigned int addr);
362
363/* extern int clk_measure(char index); */
364
365void ofdm_initial(int bandwidth,
366 /* 00:8M 01:7M 10:6M 11:5M */
367 int samplerate,
368 /* 00:45M 01:20.8333M 10:20.7M 11:28.57 */
369 int IF,
370 /* 000:36.13M 001:-5.5M 010:4.57M 011:4M 100:5M */
371 int mode,
372 /* 00:DVBT,01:ISDBT */
373 int tc_mode
374 /* 0: Unsigned, 1:TC */);
375
376void monitor_isdbt(void);
377void demod_set_reg(struct aml_demod_reg *demod_reg);
378void demod_get_reg(struct aml_demod_reg *demod_reg);
379
380/* void demod_calc_clk(struct aml_demod_sta *demod_sta); */
381int demod_set_sys(struct aml_demod_sta *demod_sta,
382 struct aml_demod_i2c *demod_i2c,
383 struct aml_demod_sys *demod_sys);
384/* int demod_get_sys(struct aml_demod_i2c *demod_i2c, */
385/* struct aml_demod_sys *demod_sys); */
386/* int dvbt_set_ch(struct aml_demod_sta *demod_sta, */
387/* struct aml_demod_i2c *demod_i2c, */
388/* struct aml_demod_dvbt *demod_dvbt); */
389/* int tuner_set_ch (struct aml_demod_sta *demod_sta, */
390/* struct aml_demod_i2c *demod_i2c); */
391
392/* typedef char int8_t; */
393/* typedef short int int16_t; */
394/* typedef int int32_t; */
395/* typedef long int64_t; */
396/*typedef unsigned char uint8_t;
397 * typedef unsigned short int uint16_t;
398 * typedef unsigned int uint32_t;
399 * typedef unsigned long uint64_t;
400 */
401
402/*typedef unsigned char u8_t;
403 * typedef signed char s8_t;
404 * typedef unsigned short u16_t;
405 * typedef signed short s16_t;
406 * typedef unsigned int u32_t;
407 * typedef signed int s32_t;
408 * typedef unsigned long u64_t;
409 * typedef signed long s64_t;
410 */
411
412/* #define extadc */
413
414/* for g9tv */
415void adc_dpll_setup(int clk_a, int clk_b, int clk_sys);
416void demod_power_switch(int pwr_cntl);
417
418union adc_pll_cntl {
419 /** raw register data */
420 uint32_t d32;
421 /** register bits */
422 struct {
423 unsigned pll_m:9;
424 unsigned pll_n:5;
425 unsigned pll_od0:2;
426 unsigned pll_od1:2;
427 unsigned pll_od2:2;
428 unsigned pll_xd0:6;
429 unsigned pll_xd1:6;
430 } b;
431};
432
433union adc_pll_cntl2 {
434 /** raw register data */
435 uint32_t d32;
436 /** register bits */
437 struct {
438 unsigned output_mux_ctrl:4;
439 unsigned div2_ctrl:1;
440 unsigned b_polar_control:1;
441 unsigned a_polar_control:1;
442 unsigned gate_ctrl:6;
443 unsigned tdc_buf:8;
444 unsigned lm_s:6;
445 unsigned lm_w:4;
446 unsigned reserved:1;
447 } b;
448};
449
450union adc_pll_cntl3 {
451 /** raw register data */
452 uint32_t d32;
453 /** register bits */
454 struct {
455 unsigned afc_dsel_in:1;
456 unsigned afc_dsel_bypass:1;
457 unsigned dco_sdmck_sel:2;
458 unsigned dc_vc_in:2;
459 unsigned dco_m_en:1;
460 unsigned dpfd_lmode:1;
461 unsigned filter_acq1:11;
462 unsigned enable:1;
463 unsigned filter_acq2:11;
464 unsigned reset:1;
465 } b;
466};
467
468union adc_pll_cntl4 {
469 /** raw register data */
470 uint32_t d32;
471 /** register bits */
472 struct {
473 unsigned reve:12;
474 unsigned tdc_en:1;
475 unsigned dco_sdm_en:1;
476 unsigned dco_iup:2;
477 unsigned pvt_fix_en:1;
478 unsigned iir_bypass_n:1;
479 unsigned pll_od3:2;
480 unsigned filter_pvt1:4;
481 unsigned filter_pvt2:4;
482 unsigned reserved:4;
483 } b;
484};
485
486/* ///////////////////////////////////////////////////////////////// */
487
488union demod_dig_clk {
489 /** raw register data */
490 uint32_t d32;
491 /** register bits */
492 struct {
493 unsigned demod_clk_div:7;
494 unsigned reserved0:1;
495 unsigned demod_clk_en:1;
496 unsigned demod_clk_sel:2;
497 unsigned reserved1:5;
498 unsigned adc_extclk_div:7; /* 34 */
499 unsigned use_adc_extclk:1; /* 1 */
500 unsigned adc_extclk_en:1; /* 1 */
501 unsigned adc_extclk_sel:3; /* 1 */
502 unsigned reserved2:4;
503 } b;
504};
505
506union demod_adc_clk {
507 /** raw register data */
508 uint32_t d32;
509 /** register bits */
510 struct {
511 unsigned pll_m:9;
512 unsigned pll_n:5;
513 unsigned pll_od:2;
514 unsigned pll_xd:5;
515 unsigned reserved0:3;
516 unsigned pll_ss_clk:4;
517 unsigned pll_ss_en:1;
518 unsigned reset:1;
519 unsigned pll_pd:1;
520 unsigned reserved1:1;
521 } b;
522};
523
524union demod_cfg0 {
525 /** raw register data */
526 uint32_t d32;
527 /** register bits */
528 struct {
529 unsigned mode:4;
530 unsigned ts_sel:4;
531 unsigned test_bus_clk:1;
532 unsigned adc_ext:1;
533 unsigned adc_rvs:1;
534 unsigned adc_swap:1;
535 unsigned adc_format:1;
536 unsigned adc_regout:1;
537 unsigned adc_regsel:1;
538 unsigned adc_regadj:5;
539 unsigned adc_value:10;
540 unsigned adc_test:1;
541 unsigned ddr_sel:1;
542 } b;
543};
544
545union demod_cfg1 {
546 /** raw register data */
547 uint32_t d32;
548 /** register bits */
549 struct {
550 unsigned reserved:8;
551 unsigned ref_top:2;
552 unsigned ref_bot:2;
553 unsigned cml_xs:2;
554 unsigned cml_1s:2;
555 unsigned vdda_sel:2;
556 unsigned bias_sel_sha:2;
557 unsigned bias_sel_mdac2:2;
558 unsigned bias_sel_mdac1:2;
559 unsigned fast_chg:1;
560 unsigned rin_sel:3;
561 unsigned en_ext_vbg:1;
562 unsigned en_cmlgen_res:1;
563 unsigned en_ext_vdd12:1;
564 unsigned en_ext_ref:1;
565 } b;
566};
567
568union demod_cfg2 {
569 /** raw register data */
570 uint32_t d32;
571 /** register bits */
572 struct {
573 unsigned en_adc:1;
574 unsigned biasgen_ibipt_sel:2;
575 unsigned biasgen_ibic_sel:2;
576 unsigned biasgen_rsv:4;
577 unsigned biasgen_en:1;
578 unsigned biasgen_bias_sel_adc:2;
579 unsigned biasgen_bias_sel_cml1:2;
580 unsigned biasgen_bias_sel_ref_op:2;
581 unsigned clk_phase_sel:1;
582 unsigned reserved:15;
583 } b;
584};
585
586union demod_cfg3 {
587 /** raw register data */
588 uint32_t d32;
589 /** register bits */
590 struct {
591 unsigned dc_arb_mask:3;
592 unsigned dc_arb_enable:1;
593 unsigned reserved:28;
594 } b;
595};
596
597struct atsc_cfg {
598 int adr;
599 int dat;
600 int rw;
601};
602
603struct agc_power_tab {
604 char name[128];
605 int level;
606 int ncalcE;
607 int *calcE;
608};
609
610struct dtmb_cfg {
611 int dat;
612 int adr;
613 int rw;
614};
615
616void dtvpll_lock_init(void);
617void dtvpll_init_flag(int on);
618void demod_set_irq_mask(void);
619void demod_clr_irq_stat(void);
620void demod_set_adc_core_clk(int adc_clk, int sys_clk, int dvb_mode);
621void demod_set_adc_core_clk_fix(int clk_adc, int clk_dem);
622void calculate_cordic_para(void);
623void ofdm_read_all_regs(void);
624extern int aml_fe_analog_set_frontend(struct dvb_frontend *fe);
625
626#endif
627
generated by cgit at 2024-05-19 19:58:19 (GMT)