| author | Zongdong Jiao <zongdong.jiao@amlogic.com> | 2019-03-08 07:19:51 (GMT) |
|---|---|---|
| committer | Luan Yuan <luan.yuan@amlogic.com> | 2019-05-16 05:20:44 (GMT) |
| commit | 17a3043ac7108e71892174488d9ada5ca8c29cbc (patch) | |
| tree | 80bec4bbf48f62e65845cd54a1060b835397e7b3 | |
| parent | 4b9b578ec047d72e9f57f711541619a31ff0d3e1 (diff) | |
| download | uboot-17a3043ac7108e71892174488d9ada5ca8c29cbc.zip uboot-17a3043ac7108e71892174488d9ada5ca8c29cbc.tar.gz uboot-17a3043ac7108e71892174488d9ada5ca8c29cbc.tar.bz2 | |
hdmitx: adjust PHY parameter with 5.1 ohm resistor [1/2]
PD#SWPL-2927
Problem:
No enough eye diagram when adding TMDS 5.1 ohm resistor
Solution:
adjust PHY parameter with 5.1 ohm resistor
Verify:
G12/U212
Change-Id: I38ddd0551cd643814d41282af82da002fbd863ed
Signed-off-by: Zongdong Jiao <zongdong.jiao@amlogic.com>
| -rw-r--r-- | arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_set.c | 2 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/g12b/hdmitx20/hdmitx_set.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_set.c b/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_set.c index 0a0d9fc..1b9ee80 100644 --- a/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_set.c +++ b/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_set.c @@ -1141,7 +1141,7 @@ static void set_phy_by_mode(struct hdmitx_dev *hdev, unsigned int mode) hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x0000080b); break; case 2: /* 2.97Gbps */ - hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb6262); + hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb6272); if (hdev->dongle_mode) hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb4262); hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); diff --git a/arch/arm/cpu/armv8/g12b/hdmitx20/hdmitx_set.c b/arch/arm/cpu/armv8/g12b/hdmitx20/hdmitx_set.c index 0a0d9fc..1b9ee80 100644 --- a/arch/arm/cpu/armv8/g12b/hdmitx20/hdmitx_set.c +++ b/arch/arm/cpu/armv8/g12b/hdmitx20/hdmitx_set.c @@ -1141,7 +1141,7 @@ static void set_phy_by_mode(struct hdmitx_dev *hdev, unsigned int mode) hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x0000080b); break; case 2: /* 2.97Gbps */ - hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb6262); + hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb6272); if (hdev->dongle_mode) hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb4262); hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); |