sabrina: bring-up modify [1/2]

PD#SWPL-8961

Problem:
1. Modify GPIOZ_12 for VDDHDMI_EN
2. Modify LPDDR4 parameters (Same as Newman)

Solution:
LPDDR4,GPIO

Verify:
sabrina

Change-Id: Ie0926fadd6de13c6ddb72aafc708697c309de2bb
Signed-off-by: Edward Ho <edward.ho@amlogic.com>

2 files changed, 42 insertions, 25 deletions

diff --git a/board/amlogic/sm1_sabrina_v1/firmware/timing.c b/board/amlogic/sm1_sabrina_v1/firmware/timing.c
index 3299808..f85122e 100755
--- a/board/amlogic/sm1_sabrina_v1/firmware/timing.c
+++ b/board/amlogic/sm1_sabrina_v1/firmware/timing.c
@@ -59,15 +59,14 @@
  */
 
 ddr_set_t __ddr_setting[] = {
-	//A311 D T400
-#if 1
 {
-	/* g12a skt (u209) lpddr4 */
+	/* g12a (Google) lpddr4 */
 	.board_id				= CONFIG_BOARD_ID_MASK,
 	.version				= 1,
+	//.fast_boot[0]=6,
 	//.dram_rank_config		= CONFIG_DDR0_32BIT_RANK01_CH0,
-	.dram_rank_config		= CONFIG_DDR0_32BIT_RANK0_CH0,
-	.ddr_rfc_type			= DDR_RFC_TYPE_LPDDR4_8Gbx1,
+	.dram_rank_config		= CONFIG_DDR0_32BIT_RANK0_CH01,
+	.ddr_rfc_type			= DDR_RFC_TYPE_LPDDR4_4Gbx1,
 	.DramType				= CONFIG_DDR_TYPE_LPDDR4,
 	.DRAMFreq				= {1584, 0, 0, 0},
 	.ddr_base_addr			= CFG_DDR_BASE_ADDR,
@@ -78,32 +77,30 @@ ddr_set_t __ddr_setting[] = {
 	.DisabledDbyte			= 0xf0,
 	.Is2Ttiming				= 0,
 	.HdtCtrl				= 0xa,
-	.dram_cs0_size_MB		= 0xffff,//1024,
-	.dram_cs1_size_MB		= 0,//0xffff,//1024,
+	.dram_cs0_size_MB		= 2048,//1024,
+	.dram_cs1_size_MB		= 0,//1024,
 	.training_SequenceCtrl	= {0x131f,0x61}, //ddr3 0x21f 0x31f
 	.phy_odt_config_rank		= {0x23,0x13}, // // 2rank use 0x23 0x13  1rank use 0x30 0x30 Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
 	.dfi_odt_config			= 0x0d0d,  //2rank use 0d0d   1rank use 0808
 	.PllBypassEn			= 0, //bit0-ps0,bit1-ps1
-	.ddr_rdbi_wr_enable		= 3,
-	.clk_drv_ohm			= 40,
-	.cs_drv_ohm				= 40,//48,
-	.ac_drv_ohm				= 40,//48,
-
-	///*
-	.soc_data_drv_ohm_p		= 48,//30,//30,
-	.soc_data_drv_ohm_n		= 48,//30,//30,
+	.ddr_rdbi_wr_enable		= 0,
+	.pll_ssc_mode			= 0,
+	.clk_drv_ohm			= 48,
+	.cs_drv_ohm				= 48,
+	.ac_drv_ohm				= 48,
+	.soc_data_drv_ohm_p		= 48,
+	.soc_data_drv_ohm_n		= 48,
 	.soc_data_odt_ohm_p		= 0,
-	.soc_data_odt_ohm_n		= 48,//40,//60,// 120,//120,
-	.dram_data_drv_ohm		= 48,// 48, //lpddr4 sdram only240/1-6
-	.dram_data_odt_ohm		= 48,// 48,//48,1rank use 48 ohm ,2rank use 80 ohm
+	.soc_data_odt_ohm_n		= 48,
+	.dram_data_drv_ohm		= 48, //lpddr4 sdram only240/1-6
+	.dram_data_odt_ohm		= 48,//120,// 120,
 	.dram_ac_odt_ohm		= 120,
 	.lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq     0 2/5 vddq
-	//*/
 	.soc_clk_slew_rate		= 0x3ff,//0x253,
 	.soc_cs_slew_rate		= 0x100,//0x253,
 	.soc_ac_slew_rate		= 0x100,//0x253,
 	.soc_data_slew_rate		= 0x1ff,
-	.vref_output_permil		= 300,//350,//200,
+	.vref_output_permil		= 350,//200,
 	.vref_receiver_permil	= 0,
 	.vref_dram_permil		= 0,
 	//.vref_reverse			= 0,
@@ -118,14 +115,33 @@ ddr_set_t __ddr_setting[] = {
 							[4] = ( 30| 12 << 5 | 13 << 10 |  14<< 15 |  0 << 20 |  0 << 25 ),
 	},
 	.ddr_lpddr34_ca_remap	= {00,00},
-		.ddr_lpddr34_dq_remap	= {3,2,0,1,7,6,5,4, 10,9,14,11,8,12,13,15, 20,21,23,22,18,17,19,16, 28,26,25,24,31,30,27,29},
-//	.ddr_lpddr34_dq_remap	= {3,2,0,1,7,6,5,4, 14,13,12,15,8,9,11,10, 20,21,22,23,16,17,19,18, 24,25,28,26,31,30,27,29},
-//	.ddr_lpddr34_dq_remap	= {3,0,2,1,7,6,5,4, 13,12,15,14,10,8,11,9, 19,21,22,20,16,18,17,23, 26,27,25,24,31,29,30,28},
-		.pll_ssc_mode			= (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+	.ddr_lpddr34_dq_remap	=
+//{3,2,0,1,7,6,5,4,14,13,12,15,8,9,11,10,20,21,22,23,16,17,19,18,24,25,28,26,31,30,27,29},
+	{3,2,0,1,7,6,5,4, 10,9,14,11,8,12,13,15, 20,21,23,22,18,17,19,16, 28,26,25,24,31,30,27,29},
+	.dram_rtt_nom_wr_park	= {00,00},
+
+	/* pll ssc config:
+	 *
+	 *   pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+	 *      ppm = strength * 500
+	 *      mode: 0=center, 1=up, 2=down
+	 *
+	 *   eg:
+	 *     1. config 1000ppm center ss. then mode=0, strength=2
+	 *        .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+	 *     2. config 3000ppm down ss. then mode=2, strength=6
+	 *        .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+	 */
+	.pll_ssc_mode			= (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
 	.ddr_func				= DDR_FUNC,
 	.magic					= DRAM_CFG_MAGIC,
+	.diagnose				= CONFIG_DIAGNOSE_DISABLE,
+	.bitTimeControl_2d		= 1,
+	//.slt_test_function[0]=DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT,
+	//.dqs_adjust={100,100,100,100,100,100,100,100,
+	//	100,100,100,100,100,100,100,100,
+	//}, //rank 0 --lane 0 1 2 3  rank 1--4 5 6 7 write  //rank 0 --lane 0 1 2 3  rank 1--4 5 6 7 read
 },
-#endif
 {
 	/* g12a skt (u209) ddr4 */
 	.board_id				= CONFIG_BOARD_ID_MASK,
diff --git a/board/amlogic/sm1_sabrina_v1/sm1_sabrina_v1.c b/board/amlogic/sm1_sabrina_v1/sm1_sabrina_v1.c
index 5bd6238..37c13d4 100755
--- a/board/amlogic/sm1_sabrina_v1/sm1_sabrina_v1.c
+++ b/board/amlogic/sm1_sabrina_v1/sm1_sabrina_v1.c
@@ -445,6 +445,7 @@ struct amlogic_usb_config g_usb_config_GXL_skt={
 #ifdef CONFIG_AML_HDMITX20
 static void hdmi_tx_set_hdmi_5v(void)
 {
+	run_command("gpio set GPIOZ_12", 0);
 }
 #endif