| author | Zongdong Jiao <zongdong.jiao@amlogic.com> | 2019-02-26 07:13:13 (GMT) |
|---|---|---|
| committer | Zongdong Jiao <zongdong.jiao@amlogic.com> | 2019-02-26 07:13:13 (GMT) |
| commit | 1fe1291254cd5385523f7932df04f89026d124a9 (patch) | |
| tree | 393d5f35b39b6acdf0542ee3955d72b808fdc62d | |
| parent | d9262852f097da232a7d0e49a69102a228a78bde (diff) | |
| download | common-1fe1291254cd5385523f7932df04f89026d124a9.zip common-1fe1291254cd5385523f7932df04f89026d124a9.tar.gz common-1fe1291254cd5385523f7932df04f89026d124a9.tar.bz2 | |
hdmitx: optimize the hdcp22 init step [1/1]
PD#OTT-1558
Problem:
TV freezes its screen when Tx switches output mode
Solution:
Optimize the hdcp22 init step
Verify:
TBD
Change-Id: I0f423099761dc52e2df1da1f4c494ed9f17a4b0a
Signed-off-by: Zongdong Jiao <zongdong.jiao@amlogic.com>
| -rw-r--r-- | drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c index 6cf1cef..089e278 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c @@ -3437,11 +3437,11 @@ static int hdmitx_cntl_ddc(struct hdmitx_dev *hdev, unsigned int cmd, hdmitx_ddc_hw_op(DDC_MUX_DDC); hdmitx_set_reg_bits(HDMITX_DWC_MC_CLKDIS, 1, 6, 1); udelay(5); - hdmitx_set_reg_bits(HDMITX_DWC_HDCP22REG_CTRL, 3, 1, 2); hdmitx_set_reg_bits(HDMITX_TOP_SW_RESET, 1, 5, 1); udelay(10); hdmitx_set_reg_bits(HDMITX_TOP_SW_RESET, 0, 5, 1); udelay(10); + hdmitx_set_reg_bits(HDMITX_DWC_HDCP22REG_CTRL, 3, 1, 2); hdmitx_wr_reg(HDMITX_DWC_HDCP22REG_MASK, 0); hdmitx_wr_reg(HDMITX_DWC_HDCP22REG_MUTE, 0); set_pkf_duk_nonce(); @@ -3468,8 +3468,13 @@ static int hdmitx_cntl_ddc(struct hdmitx_dev *hdev, unsigned int cmd, hdmitx_hdcp_opr(5); /* wait for start hdcp22app */ } - if (argv == HDCP22_OFF) + if (argv == HDCP22_OFF) { hdmitx_hdcp_opr(6); + hdmitx_set_reg_bits(HDMITX_TOP_SW_RESET, 1, 5, 1); + udelay(10); + hdmitx_set_reg_bits(HDMITX_TOP_SW_RESET, 0, 5, 1); + udelay(10); + } break; case DDC_HDCP_GET_BKSV: tmp_char = (unsigned char *) argv; |