| author | Zongdong Jiao <zongdong.jiao@amlogic.com> | 2018-03-19 11:47:20 (GMT) |
|---|---|---|
| committer | Xindong Xu <xindong.xu@amlogic.com> | 2018-05-02 02:07:46 (GMT) |
| commit | 6f39c6d2a07c9d6a720441fc743ec9608636b257 (patch) | |
| tree | aaa367ec76ce3c3fb285431cdfed66781fd6e1ea | |
| parent | 37b429e74a93f8b7b95c810ca55797debef7c3e6 (diff) | |
| download | common-6f39c6d2a07c9d6a720441fc743ec9608636b257.zip common-6f39c6d2a07c9d6a720441fc743ec9608636b257.tar.gz common-6f39c6d2a07c9d6a720441fc743ec9608636b257.tar.bz2 | |
hdmitx: add sspll for hdmi modes
PD#162511: hdmitx: add sspll for hdmi modes
To reduce EMI issue, enable sspll function under certain modes.
Change-Id: Ib5187aaafbc92eccbdd6a77d1c4828776ff596be
Signed-off-by: Zongdong Jiao <zongdong.jiao@amlogic.com>
4 files changed, 35 insertions, 4 deletions
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/common.h b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/common.h index 4128194..486207b 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/common.h +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/common.h @@ -54,6 +54,8 @@ int read_hpd_gpio_gxl(void); int hdmitx_ddc_hw_op_gxl(enum ddc_op cmd); void set_gxl_hpll_clk_out(unsigned int frac_rate, unsigned int clk); void set_hpll_sspll_gxl(enum hdmi_vic vic); +void set_hpll_sspll_g12a(enum hdmi_vic vic); + void set_hpll_od1_gxl(unsigned int div); void set_hpll_od2_gxl(unsigned int div); void set_hpll_od3_gxl(unsigned int div); diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c index 92ce220..2f022c1 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c @@ -1679,7 +1679,7 @@ static void set_phy_by_mode(unsigned int mode) break; case 3: /* 1.485Gbps, and below */ default: - hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb6262); + hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb4242); hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x00000003); break; diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c index c0f2fd3..e27ecb5 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c @@ -454,6 +454,9 @@ static void set_hpll_sspll(enum hdmi_vic vic) struct hdmitx_dev *hdev = get_hdmitx_device(); switch (hdev->chip_type) { + case MESON_CPU_ID_G12A: + set_hpll_sspll_g12a(vic); + break; case MESON_CPU_ID_GXBB: break; case MESON_CPU_ID_GXTVBB: @@ -967,9 +970,7 @@ static void hdmitx_set_clk_(struct hdmitx_dev *hdev) next: hdmitx_set_cts_sys_clk(hdev); set_hpll_clk_out(p_enc[j].hpll_clk_out); - /* 4K mode doesn't enable SS*/ - if ((cd == COLORDEPTH_24B) && (hdev->sspll) - && (p_enc[j].hpll_clk_out != 5940000)) + if ((cd == COLORDEPTH_24B) && (hdev->sspll)) set_hpll_sspll(vic); set_hpll_od1(p_enc[j].od1); set_hpll_od2(p_enc[j].od2); diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c index 2b5ad47..d7a24b5 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c @@ -350,3 +350,31 @@ int hdmitx_hpd_hw_op_g12a(enum hpd_op cmd) return ret; } + +void set_hpll_sspll_g12a(enum hdmi_vic vic) +{ + switch (vic) { + case HDMI_1920x1080p60_16x9: + case HDMI_1920x1080p50_16x9: + case HDMI_1280x720p60_16x9: + case HDMI_1280x720p50_16x9: + case HDMI_1920x1080i60_16x9: + case HDMI_1920x1080i50_16x9: + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 1, 29, 1); + /* bit[22:20] hdmi_dpll_fref_sel + * bit[8] hdmi_dpll_ssc_en + * bit[7:4] hdmi_dpll_ssc_dep_sel + */ + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 1, 20, 3); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 1, 8, 1); + /* 2: 1000ppm 1: 500ppm */ + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 2, 4, 4); + /* bit[15] hdmi_dpll_sdmnc_en */ + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL3, 0, 15, 1); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0, 29, 1); + break; + default: + break; + } +} + |