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1/*
2 * arch/arm/boot/dts/amlogic/mesong12b_a.dtsi
3 *
4 * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17
18#include <dt-bindings/interrupt-controller/arm-gic.h>
19#include <dt-bindings/clock/amlogic,g12a-clkc.h>
20#include <dt-bindings/clock/amlogic,g12a-audio-clk.h>
21#include <dt-bindings/iio/adc/amlogic-saradc.h>
22#include <dt-bindings/gpio/meson-g12a-gpio.h>
23#include <dt-bindings/pwm/pwm.h>
24#include <dt-bindings/pwm/meson.h>
25#include <dt-bindings/gpio/gpio.h>
26#include <dt-bindings/input/input.h>
27#include <dt-bindings/input/meson_rc.h>
28#include <dt-bindings/phy/phy-amlogic-pcie.h>
29#include "mesong12a-bifrost.dtsi"
30#include "g12b-sched-energy-a.dtsi"
31
32/ {
33 cpus:cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 cpu-map {
38 cluster0:cluster0 {
39 core0 {
40 cpu = <&CPU0>;
41 };
42 core1 {
43 cpu = <&CPU1>;
44 };
45 };
46 cluster1:cluster1 {
47 core0 {
48 cpu = <&CPU2>;
49 };
50 core1 {
51 cpu = <&CPU3>;
52 };
53 core2 {
54 cpu = <&CPU4>;
55 };
56 core3 {
57 cpu = <&CPU5>;
58 };
59 };
60 };
61
62 CPU0:cpu@0 {
63 device_type = "cpu";
64 compatible = "arm,cortex-a53","arm,armv8";
65 reg = <0x0>;
66 enable-method = "psci";
67 //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
68 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
69 clocks = <&clkc CLKID_CPU_CLK>,
70 <&clkc CLKID_CPU_FCLK_P>,
71 <&clkc CLKID_SYS1_PLL>;
72 clock-names = "core_clk",
73 "low_freq_clk_parent",
74 "high_freq_clk_parent";
75 operating-points-v2 = <&cpu_opp_table0>;
76 cpu-supply = <&vddcpu0>;
77 voltage-tolerance = <0>;
78 clock-latency = <50000>;
79 };
80
81 CPU1:cpu@1 {
82 device_type = "cpu";
83 compatible = "arm,cortex-a53","arm,armv8";
84 reg = <0x1>;
85 enable-method = "psci";
86 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
87 clocks = <&clkc CLKID_CPU_CLK>,
88 <&clkc CLKID_CPU_FCLK_P>,
89 <&clkc CLKID_SYS1_PLL>;
90 clock-names = "core_clk",
91 "low_freq_clk_parent",
92 "high_freq_clk_parent";
93 operating-points-v2 = <&cpu_opp_table0>;
94 cpu-supply = <&vddcpu0>;
95 voltage-tolerance = <0>;
96 clock-latency = <50000>;
97 };
98
99 CPU2:cpu@100 {
100 device_type = "cpu";
101 compatible = "arm,cortex-a73","arm,armv8";
102 reg = <0x100>;
103 enable-method = "psci";
104 //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
105 sched-energy-costs = <&CPU_COST_A73 &CLUSTER_COST_A73>;
106 clocks = <&clkc CLKID_CPUB_CLK>,
107 <&clkc CLKID_CPUB_FCLK_P>,
108 <&clkc CLKID_SYS_PLL>;
109 clock-names = "core_clk",
110 "low_freq_clk_parent",
111 "high_freq_clk_parent";
112 operating-points-v2 = <&cpu_opp_table1>;
113 cpu-supply = <&vddcpu1>;
114 voltage-tolerance = <0>;
115 clock-latency = <50000>;
116 };
117
118 CPU3:cpu@101 {
119 device_type = "cpu";
120 compatible = "arm,cortex-a73","arm,armv8";
121 reg = <0x101>;
122 enable-method = "psci";
123 //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
124 sched-energy-costs = <&CPU_COST_A73 &CLUSTER_COST_A73>;
125 clocks = <&clkc CLKID_CPUB_CLK>,
126 <&clkc CLKID_CPUB_FCLK_P>,
127 <&clkc CLKID_SYS_PLL>;
128 clock-names = "core_clk",
129 "low_freq_clk_parent",
130 "high_freq_clk_parent";
131 operating-points-v2 = <&cpu_opp_table1>;
132 cpu-supply = <&vddcpu1>;
133 voltage-tolerance = <0>;
134 clock-latency = <50000>;
135 };
136
137 CPU4:cpu@102 {
138 device_type = "cpu";
139 compatible = "arm,cortex-a73","arm,armv8";
140 reg = <0x102>;
141 enable-method = "psci";
142 //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
143 sched-energy-costs = <&CPU_COST_A73 &CLUSTER_COST_A73>;
144 clocks = <&clkc CLKID_CPUB_CLK>,
145 <&clkc CLKID_CPUB_FCLK_P>,
146 <&clkc CLKID_SYS_PLL>;
147 clock-names = "core_clk",
148 "low_freq_clk_parent",
149 "high_freq_clk_parent";
150 operating-points-v2 = <&cpu_opp_table1>;
151 cpu-supply = <&vddcpu1>;
152 voltage-tolerance = <0>;
153 clock-latency = <50000>;
154 };
155
156 CPU5:cpu@103 {
157 device_type = "cpu";
158 compatible = "arm,cortex-a73","arm,armv8";
159 reg = <0x103>;
160 enable-method = "psci";
161 //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
162 sched-energy-costs = <&CPU_COST_A73 &CLUSTER_COST_A73>;
163 clocks = <&clkc CLKID_CPUB_CLK>,
164 <&clkc CLKID_CPUB_FCLK_P>,
165 <&clkc CLKID_SYS_PLL>;
166 clock-names = "core_clk",
167 "low_freq_clk_parent",
168 "high_freq_clk_parent";
169 operating-points-v2 = <&cpu_opp_table1>;
170 cpu-supply = <&vddcpu1>;
171 voltage-tolerance = <0>;
172 clock-latency = <50000>;
173 };
174
175 idle-states {
176 entry-method = "arm,psci";
177
178 CPU_SLEEP_0: cpu-sleep-0 {
179 compatible = "arm,idle-state";
180 arm,psci-suspend-param = <0x0010000>;
181 local-timer-stop;
182 entry-latency-us = <8000>;
183 exit-latency-us = <8000>;
184 min-residency-us = <20000>;
185 };
186
187 CLUSTER_SLEEP_0: cluster-sleep-0 {
188 compatible = "arm,idle-state";
189 arm,psci-suspend-param = <0x1010000>;
190 local-timer-stop;
191 entry-latency-us = <9000>;
192 exit-latency-us = <9000>;
193 min-residency-us = <25000>;
194 };
195 };
196 };
197
198 timer {
199 compatible = "arm,armv7-timer";
200 interrupts = <GIC_PPI 13 0xff08>,
201 <GIC_PPI 14 0xff08>,
202 <GIC_PPI 11 0xff08>,
203 <GIC_PPI 10 0xff08>;
204 };
205
206 timer_bc {
207 compatible = "arm, meson-bc-timer";
208 reg= <0xffd0f190 0x4 0xffd0f194 0x4>;
209 timer_name = "Meson TimerF";
210 clockevent-rating=<300>;
211 clockevent-shift=<20>;
212 clockevent-features=<0x23>;
213 interrupts = <0 60 1>;
214 bit_enable=<16>;
215 bit_mode=<12>;
216 bit_resolution=<0>;
217 };
218
219 arm_pmu {
220 compatible = "arm,cortex-a15-pmu";
221 clusterb-enabled;
222 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
224 reg = <0xff634680 0x4>,
225 <0xff6347c0 0x04>;
226 cpumasks = <0x3 0x3C>;
227 /* default 10ms */
228 relax-timer-ns = <10000000>;
229 /* default 10000us */
230 max-wait-cnt = <10000>;
231 };
232
233 gic: interrupt-controller@2c001000 {
234 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
235 #interrupt-cells = <3>;
236 #address-cells = <0>;
237 interrupt-controller;
238 reg = <0xffc01000 0x1000>,
239 <0xffc02000 0x0100>;
240 interrupts = <GIC_PPI 9 0xf04>;
241 };
242
243 psci {
244 compatible = "arm,psci-0.2";
245 method = "smc";
246 };
247
248 meson_suspend:pm {
249 compatible = "amlogic, pm";
250 status = "okay";
251 device_name = "aml_pm";
252 reg = <0xff8000a8 0x4>,
253 <0xff80023c 0x4>;
254 };
255
256 secmon {
257 compatible = "amlogic, secmon";
258 memory-region = <&secmon_reserved>;
259 in_base_func = <0x82000020>;
260 out_base_func = <0x82000021>;
261 reserve_mem_size = <0x00300000>;
262 clear_range = <0x05100000 0x200000>;
263 };
264
265 securitykey {
266 compatible = "aml, securitykey";
267 storage_query = <0x82000060>;
268 storage_read = <0x82000061>;
269 storage_write = <0x82000062>;
270 storage_tell = <0x82000063>;
271 storage_verify = <0x82000064>;
272 storage_status = <0x82000065>;
273 storage_list = <0x82000067>;
274 storage_remove = <0x82000068>;
275 storage_in_func = <0x82000023>;
276 storage_out_func = <0x82000024>;
277 storage_block_func = <0x82000025>;
278 storage_size_func = <0x82000027>;
279 storage_set_enctype = <0x8200006A>;
280 storage_get_enctype = <0x8200006B>;
281 storage_version = <0x8200006C>;
282 };
283
284 mailbox: mhu@c883c400 {
285 compatible = "amlogic, meson_mhu";
286 reg = <0xff63c400 0x4c>, /* MHU registers */
287 <0xfffe7000 0x800>; /* Payload area */
288 interrupts = <0 209 1>, /* low priority interrupt */
289 <0 210 1>; /* high priority interrupt */
290 #mbox-cells = <1>;
291 mbox-names = "cpu_to_scp_low", "cpu_to_scp_high";
292 mboxes = <&mailbox 0 &mailbox 1>;
293 };
294
295 cpu_iomap {
296 compatible = "amlogic, iomap";
297 #address-cells=<1>;
298 #size-cells=<1>;
299 ranges;
300 io_cbus_base {
301 reg = <0xffd00000 0x26000>;
302 };
303 io_apb_base {
304 reg = <0xffe01000 0x7f000>;
305 };
306 io_aobus_base {
307 reg = <0xff800000 0xb000>;
308 };
309 io_vapb_base {
310 reg = <0xff900000 0x50000>;
311 };
312 io_hiu_base {
313 reg = <0xff63c000 0x2000>;
314 };
315 };
316
317 xtal: xtal-clk {
318 compatible = "fixed-clock";
319 clock-frequency = <24000000>;
320 clock-output-names = "xtal";
321 #clock-cells = <0>;
322 };
323
324 cpu_info {
325 compatible = "amlogic, cpuinfo";
326 status = "okay";
327 cpuinfo_cmd = <0x82000044>;
328 };
329
330 aml_reboot{
331 compatible = "aml, reboot";
332 sys_reset = <0x84000009>;
333 sys_poweroff = <0x84000008>;
334 };
335
336 vpu {
337 compatible = "amlogic, vpu-g12b";
338 dev_name = "vpu";
339 status = "okay";
340 clocks = <&clkc CLKID_VAPB_MUX>,
341 <&clkc CLKID_VPU_INTR>,
342 <&clkc CLKID_VPU_P0_COMP>,
343 <&clkc CLKID_VPU_P1_COMP>,
344 <&clkc CLKID_VPU_MUX>;
345 clock-names = "vapb_clk",
346 "vpu_intr_gate",
347 "vpu_clk0",
348 "vpu_clk1",
349 "vpu_clk";
350 clk_level = <7>;
351 /* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */
352 /* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */
353 };
354
355 ethmac: ethernet@ff3f0000 {
356 compatible = "amlogic, g12a-eth-dwmac","snps,dwmac";
357 reg = <0xff3f0000 0x10000
358 0xff634540 0x8
359 0xff64c000 0xa0>;
360 reg-names = "eth_base", "eth_cfg", "eth_pll";
361 interrupts = <0 8 1>;
362 interrupt-names = "macirq";
363 status = "disabled";
364 clocks = <&clkc CLKID_ETH_CORE>;
365 clock-names = "ethclk81";
366 pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>;
367 analog_val = <0x20200000 0x0000c000 0x00000023>;
368 };
369
370 pinctrl_aobus: pinctrl@ff800014{
371 compatible = "amlogic,meson-g12a-aobus-pinctrl";
372 #address-cells = <1>;
373 #size-cells = <1>;
374 ranges;
375
376 gpio_ao: ao-bank@ff800014{
377 reg = <0xff800014 0x8>,
378 <0xff800024 0x14>,
379 <0xff80001c 0x8>;
380 reg-names = "mux","gpio", "drive-strength";
381 gpio-controller;
382 #gpio-cells = <2>;
383 };
384 };
385
386 pinctrl_periphs: pinctrl@ff634480{
387 compatible = "amlogic,meson-g12a-periphs-pinctrl";
388 #address-cells = <1>;
389 #size-cells = <1>;
390 ranges;
391
392 gpio: banks@ff6346c0{
393 reg = <0xff6346c0 0x40>,
394 <0xff6344e8 0x18>,
395 <0xff634520 0x18>,
396 <0xff634440 0x4c>,
397 <0xff634740 0x1c>;
398 reg-names = "mux",
399 "pull",
400 "pull-enable",
401 "gpio",
402 "drive-strength";
403 gpio-controller;
404 #gpio-cells = <2>;
405 };
406 };
407
408 audio_data: audio_data {
409 compatible = "amlogic, audio_data";
410 query_licence_cmd = <0x82000050>;
411 status = "disabled";
412 };
413
414 dwc3: dwc3@ff500000 {
415 compatible = "synopsys, dwc3";
416 status = "disabled";
417 reg = <0xff500000 0x100000>;
418 interrupts = <0 30 4>;
419 usb-phy = <&usb2_phy_v2>, <&usb3_phy_v2>;
420 cpu-type = "gxl";
421 clock-src = "usb3.0";
422 clocks = <&clkc CLKID_USB_GENERAL>;
423 clock-names = "dwc_general";
424 };
425
426 usb2_phy_v2: usb2phy@ffe09000 {
427 compatible = "amlogic, amlogic-new-usb2-v2";
428 status = "disabled";
429 reg = <0xffe09000 0x80
430 0xffd01008 0x100
431 0xff636000 0x2000
432 0xff63a000 0x2000>;
433 pll-setting-1 = <0x09400414>;
434 pll-setting-2 = <0x927E0000>;
435 pll-setting-3 = <0xac5f69e5>;
436 pll-setting-4 = <0xfe18>;
437 pll-setting-5 = <0x8000fff>;
438 pll-setting-6 = <0x78000>;
439 pll-setting-7 = <0xe0004>;
440 pll-setting-8 = <0xe000c>;
441 };
442
443 usb3_phy_v2: usb3phy@ffe09080 {
444 compatible = "amlogic, amlogic-new-usb3-v2";
445 status = "disabled";
446 reg = <0xffe09080 0x20>;
447 phy-reg = <0xff646000>;
448 phy-reg-size = <0x2000>;
449 usb2-phy-reg = <0xffe09000>;
450 usb2-phy-reg-size = <0x80>;
451 interrupts = <0 16 4>;
452 clocks = <&clkc CLKID_PCIE_PLL>;
453 clock-names = "pcie_refpll";
454 };
455
456 dwc2_a: dwc2_a@ff400000 {
457 compatible = "amlogic, dwc2";
458 status = "disabled";
459 device_name = "dwc2_a";
460 reg = <0xff400000 0x40000>;
461 interrupts = <0 31 4>;
462 pl-periph-id = <0>; /** lm name */
463 clock-src = "usb0"; /** clock src */
464 port-id = <0>; /** ref to mach/usb.h */
465 port-type = <2>; /** 0: otg, 1: host, 2: slave */
466 port-speed = <0>; /** 0: default, high, 1: full */
467 port-config = <0>; /** 0: default */
468 /*0:default,1:single,2:incr,3:incr4,4:incr8,5:incr16,6:disable*/
469 port-dma = <0>;
470 port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/
471 usb-fifo = <728>;
472 cpu-type = "v2";
473 phy-reg = <0xffe09000>;
474 phy-reg-size = <0xa0>;
475 /** phy-interface: 0x0: amlogic phy, 0x1: synopsys phy **/
476 phy-interface = <0x0>;
477 clocks = <&clkc CLKID_USB_GENERAL
478 &clkc CLKID_USB1_TO_DDR>;
479 clock-names = "usb_general",
480 "usb1";
481 };
482
483 wdt: watchdog@0xffd0f0d0 {
484 compatible = "amlogic, meson-wdt";
485 status = "okay";
486 default_timeout=<10>;
487 reset_watchdog_method=<1>; /* 0:sysfs,1:kernel */
488 reset_watchdog_time=<2>;
489 shutdown_timeout=<10>;
490 firmware_timeout=<6>;
491 suspend_timeout=<6>;
492 reg = <0xffd0f0d0 0x10>;
493 clock-names = "xtal";
494 clocks = <&xtal>;
495 };
496
497 jtag {
498 compatible = "amlogic, jtag";
499 status = "okay";
500 select = "disable"; /* disable/apao/apee */
501 pinctrl-names="jtag_apao_pins", "jtag_apee_pins";
502 pinctrl-0=<&jtag_apao_pins>;
503 pinctrl-1=<&jtag_apee_pins>;
504 };
505
506 saradc:saradc {
507 compatible = "amlogic,meson-g12a-saradc";
508 status = "disabled";
509 #io-channel-cells = <1>;
510 clocks = <&xtal>, <&clkc CLKID_SARADC_GATE>;
511 clock-names = "xtal", "saradc_clk";
512 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
513 reg = <0xff809000 0x48>;
514 };
515
516 p_tsensor: p_tsensor@ff634594 {
517 compatible = "amlogic, r1p1-tsensor";
518 device_name = "meson-pthermal";
519 status = "okay";
520 reg = <0xff634800 0x50>,
521 <0xff800268 0x4>;
522 cal_type = <0x1>;
523 cal_a = <324>;
524 cal_b = <424>;
525 cal_c = <3159>;
526 cal_d = <9411>;
527 rtemp = <115000>;
528 interrupts = <0 35 0>;
529 clocks = <&clkc CLKID_TS_COMP>; /* CLKID_TS_COMP>;*/
530 clock-names = "ts_comp";
531 #thermal-sensor-cells = <1>;
532 };
533
534 d_tsensor: d_tsensor@ff800228 {
535 compatible = "amlogic, r1p1-tsensor";
536 device_name = "meson-dthermal";
537 status = "okay";
538 reg = <0xff634c00 0x50>,
539 <0xff800230 0x4>;
540 cal_type = <0x1>;
541 cal_a = <324>;
542 cal_b = <424>;
543 cal_c = <3159>;
544 cal_d = <9411>;
545 rtemp = <115000>;
546 interrupts = <0 36 0>;
547 clocks = <&clkc CLKID_TS_COMP>; /* CLKID_TS_COMP>;*/
548 clock-names = "ts_comp";
549 #thermal-sensor-cells = <1>;
550 };
551
552 soc {
553 compatible = "simple-bus";
554 #address-cells = <1>;
555 #size-cells = <1>;
556 ranges;
557
558 cbus: cbus@ffd00000 {
559 compatible = "simple-bus";
560 reg = <0xffd00000 0x26000>;
561 #address-cells = <1>;
562 #size-cells = <1>;
563 ranges = <0x0 0xffd00000 0x26000>;
564
565 gpio_intc: interrupt-controller@f080 {
566 compatible = "amlogic,meson-gpio-intc",
567 "amlogic,meson-g12a-gpio-intc";
568 reg = <0xf080 0x10>;
569 interrupt-controller;
570 #interrupt-cells = <2>;
571 amlogic,channel-interrupts =
572 <64 65 66 67 68 69 70 71>;
573 status = "okay";
574 };
575
576 meson_clk_msr {
577 compatible = "amlogic, gxl_measure";
578 reg = <0x18004 0x4
579 0x1800c 0x4>;
580 };
581
582 pwm_ab: pwm@1b000 {
583 compatible = "amlogic,g12b-ee-pwm";
584 reg = <0x1b000 0x20>;
585 #pwm-cells = <3>;
586 clocks = <&xtal>,
587 <&xtal>,
588 <&xtal>,
589 <&xtal>;
590 clock-names = "clkin0",
591 "clkin1",
592 "clkin2",
593 "clkin3";
594 /* default xtal 24m clkin0-clkin2 and
595 * clkin1-clkin3 should be set the same
596 */
597 status = "disabled";
598 };
599
600 pwm_cd: pwm@1a000 {
601 compatible = "amlogic,g12b-ee-pwm";
602 reg = <0x1a000 0x20>;
603 #pwm-cells = <3>;
604 clocks = <&xtal>,
605 <&xtal>,
606 <&xtal>,
607 <&xtal>;
608 clock-names = "clkin0",
609 "clkin1",
610 "clkin2",
611 "clkin3";
612 status = "disabled";
613 };
614
615 pwm_ef: pwm@19000 {
616 compatible = "amlogic,g12b-ee-pwm";
617 reg = <0x19000 0x20>;
618 #pwm-cells = <3>;
619 clocks = <&xtal>,
620 <&xtal>,
621 <&xtal>,
622 <&xtal>;
623 clock-names = "clkin0",
624 "clkin1",
625 "clkin2",
626 "clkin3";
627 status = "disabled";
628 };
629
630 i2c0: i2c@1f000 {
631 compatible = "amlogic,meson-g12b-i2c";
632 status = "disabled";
633 reg = <0x1f000 0x20>;
634 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
635 <GIC_SPI 91 IRQ_TYPE_EDGE_RISING>;
636 #address-cells = <1>;
637 #size-cells = <0>;
638 clocks = <&clkc CLKID_I2C>;
639 clock-names = "clk_i2c";
640 };
641
642 i2c1: i2c@1e000 {
643 compatible = "amlogic,meson-g12b-i2c";
644 status = "disabled";
645 reg = <0x1e000 0x20>;
646 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>,
647 <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>;
648 #address-cells = <1>;
649 #size-cells = <0>;
650 clocks = <&clkc CLKID_I2C>;
651 clock-names = "clk_i2c";
652 };
653
654 i2c2: i2c@1d000 {
655 compatible = "amlogic,meson-g12b-i2c";
656 status = "disabled";
657 reg = <0x1d000 0x20>;
658 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>,
659 <GIC_SPI 94 IRQ_TYPE_EDGE_RISING>;
660 #address-cells = <1>;
661 #size-cells = <0>;
662 clocks = <&clkc CLKID_I2C>;
663 clock-names = "clk_i2c";
664 };
665
666 i2c3: i2c@1c000 {
667 compatible = "amlogic,meson-g12b-i2c";
668 status = "disabled";
669 reg = <0x1c000 0x20>;
670 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
671 <GIC_SPI 95 IRQ_TYPE_EDGE_RISING>;
672 #address-cells = <1>;
673 #size-cells = <0>;
674 clocks = <&clkc CLKID_I2C>;
675 clock-names = "clk_i2c";
676 };
677
678 spicc0: spi@13000 {
679 compatible = "amlogic,meson-g12b-spicc",
680 "amlogic,meson-g12a-spicc";
681 reg = <0x13000 0x44>;
682 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
683 clocks = <&clkc CLKID_SPICC0>,
684 <&clkc CLKID_SPICC0_COMP>;
685 clock-names = "core", "comp";
686 #address-cells = <1>;
687 #size-cells = <0>;
688 status = "disabled";
689 };
690
691 spicc1: spi@15000 {
692 compatible = "amlogic,meson-g12b-spicc",
693 "amlogic,meson-g12a-spicc";
694 reg = <0x15000 0x44>;
695 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
696 clocks = <&clkc CLKID_SPICC1>,
697 <&clkc CLKID_SPICC1_COMP>;
698 clock-names = "core", "comp";
699 #address-cells = <1>;
700 #size-cells = <0>;
701 status = "disabled";
702 };
703 }; /* end of cbus */
704
705 aobus: aobus@ff800000 {
706 compatible = "simple-bus";
707 reg = <0xff800000 0xb000>;
708 #address-cells = <1>;
709 #size-cells = <1>;
710 ranges = <0x0 0xff800000 0xb000>;
711
712 cpu_version {
713 reg=<0x220 0x4>;
714 };
715
716 aoclkc: clock-controller@0 {
717 compatible = "amlogic,g12b-aoclkc";
718 #clock-cells = <1>;
719 reg = <0x0 0x320>;
720 };
721
722 pwm_AO_ab: pwm@7000 {
723 compatible = "amlogic,g12b-ao-pwm";
724 reg = <0x7000 0x20>;
725 #pwm-cells = <3>;
726 clocks = <&xtal>,
727 <&xtal>,
728 <&xtal>,
729 <&xtal>;
730 clock-names = "clkin0",
731 "clkin1",
732 "clkin2",
733 "clkin3";
734 status = "disabled";
735 };
736
737 pwm_AO_cd: pwm@2000 {
738 compatible = "amlogic,g12b-ao-pwm";
739 reg = <0x2000 0x20>;
740 #pwm-cells = <3>;
741 clocks = <&xtal>,
742 <&xtal>,
743 <&xtal>,
744 <&xtal>;
745 clock-names = "clkin0",
746 "clkin1",
747 "clkin2",
748 "clkin3";
749 status = "disabled";
750 };
751
752 i2c_AO: i2c@5000 {
753 compatible = "amlogic,meson-g12b-i2c";
754 status = "disabled";
755 reg = <0x05000 0x20>;
756 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>,
757 <GIC_SPI 201 IRQ_TYPE_EDGE_RISING>;
758 #address-cells = <1>;
759 #size-cells = <0>;
760 clocks = <&clkc CLKID_I2C>;
761 clock-names = "clk_i2c";
762 };
763
764 i2c_AO_slave:i2c_slave@6000 {
765 compatible = "amlogic, meson-i2c-slave";
766 status = "disabled";
767 reg = <0x6000 0x20>;
768 interrupts = <0 194 1>;
769 pinctrl-names="default";
770 pinctrl-0=<&ao_i2c_slave_pins>;
771 };
772
773 uart_AO: serial@3000 {
774 compatible = "amlogic, meson-uart";
775 reg = <0x3000 0x18>;
776 interrupts = <0 193 1>;
777 status = "okay";
778 clocks = <&xtal>;
779 clock-names = "clk_uart";
780 xtal_tick_en = <2>;
781 fifosize = < 64 >;
782 pinctrl-names = "default";
783 /*pinctrl-0 = <&ao_uart_pins>;*/
784 support-sysrq = <0>; /* 0 not support*/
785 };
786
787 uart_AO_B: serial@4000 {
788 compatible = "amlogic, meson-uart";
789 reg = <0x4000 0x18>;
790 interrupts = <0 197 1>;
791 status = "disabled";
792 clocks = <&xtal>;
793 clock-names = "clk_uart";
794 fifosize = < 64 >;
795 pinctrl-names = "default";
796 pinctrl-0 = <&ao_b_uart_pins>;
797 };
798 };/* end of aobus */
799
800 periphs: periphs@ff634400 {
801 compatible = "simple-bus";
802 reg = <0xff634400 0x400>;
803 #address-cells = <1>;
804 #size-cells = <1>;
805 ranges = <0x0 0xff634400 0x400>;
806
807 };/* end of periphs */
808
809 hiubus: hiubus@ff63c000 {
810 compatible = "simple-bus";
811 reg = <0xff63c000 0x2000>;
812 #address-cells = <1>;
813 #size-cells = <1>;
814 ranges = <0x0 0xff63c000 0x2000>;
815
816 clkc: clock-controller@0 {
817 compatible = "amlogic,g12b-clkc-1";
818 #clock-cells = <1>;
819 reg = <0x0 0x3dc>;
820 };
821 clkc_b: clock-controller@1 {
822 compatible = "amlogic,g12b-clkc-2";
823 #clock-cells = <1>;
824 reg = <0x0 0x3dc>;
825 };
826 };/* end of hiubus*/
827
828 ion_dev {
829 compatible = "amlogic, ion_dev";
830 memory-region = <&ion_cma_reserved>;
831 };/* end of ion_dev*/
832
833 audiobus: audiobus@0xff642000 {
834 compatible = "amlogic, audio-controller", "simple-bus";
835 reg = <0xff642000 0x2000>;
836 #address-cells = <1>;
837 #size-cells = <1>;
838 ranges = <0x0 0xff642000 0x2000>;
839 clkaudio: audio_clocks {
840 compatible = "amlogic, g12a-audio-clocks";
841 #clock-cells = <1>;
842 reg = <0x0 0xb0>;
843 };
844 ddr_manager {
845 compatible = "amlogic, g12a-audio-ddr-manager";
846 interrupts = <
847 GIC_SPI 148 IRQ_TYPE_EDGE_RISING
848 GIC_SPI 149 IRQ_TYPE_EDGE_RISING
849 GIC_SPI 150 IRQ_TYPE_EDGE_RISING
850 GIC_SPI 152 IRQ_TYPE_EDGE_RISING
851 GIC_SPI 153 IRQ_TYPE_EDGE_RISING
852 GIC_SPI 154 IRQ_TYPE_EDGE_RISING
853 >;
854 interrupt-names =
855 "toddr_a", "toddr_b", "toddr_c",
856 "frddr_a", "frddr_b", "frddr_c";
857 };
858 };/* end of audiobus*/
859
860 }; /* end of soc*/
861
862 remote:rc@0xff808040 {
863 compatible = "amlogic, aml_remote";
864 dev_name = "meson-remote";
865 reg = <0xff808040 0x44>, /*Multi-format IR controller*/
866 <0xff808000 0x20>; /*Legacy IR controller*/
867 status = "okay";
868 protocol = <REMOTE_TYPE_NEC>;
869 interrupts = <0 196 1>;
870 pinctrl-names = "default";
871 pinctrl-0 = <&remote_pins>;
872 map = <&custom_maps>;
873 max_frame_time = <200>; /*set software decoder max frame time*/
874 };
875
876 custom_maps:custom_maps {
877 mapnum = <3>;
878 map0 = <&map_0>;
879 map1 = <&map_1>;
880 map2 = <&map_2>;
881 map_0: map_0{
882 mapname = "amlogic-remote-1";
883 customcode = <0xfb04>;
884 release_delay = <80>;
885 size = <50>; /*keymap size*/
886 keymap = <REMOTE_KEY(0x47, KEY_0)
887 REMOTE_KEY(0x13, KEY_1)
888 REMOTE_KEY(0x10, KEY_2)
889 REMOTE_KEY(0x11, KEY_3)
890 REMOTE_KEY(0x0F, KEY_4)
891 REMOTE_KEY(0x0C, KEY_5)
892 REMOTE_KEY(0x0D, KEY_6)
893 REMOTE_KEY(0x0B, KEY_7)
894 REMOTE_KEY(0x08, KEY_8)
895 REMOTE_KEY(0x09, KEY_9)
896 REMOTE_KEY(0x5C, KEY_RIGHTCTRL)
897 REMOTE_KEY(0x51, KEY_F3)
898 REMOTE_KEY(0x50, KEY_F4)
899 REMOTE_KEY(0x40, KEY_F5)
900 REMOTE_KEY(0x4d, KEY_F6)
901 REMOTE_KEY(0x43, KEY_F7)
902 REMOTE_KEY(0x17, KEY_F8)
903 REMOTE_KEY(0x00, KEY_F9)
904 REMOTE_KEY(0x01, KEY_F10)
905 REMOTE_KEY(0x16, KEY_F11)
906 REMOTE_KEY(0x49, KEY_BACKSPACE)
907 REMOTE_KEY(0x06, KEY_PROPS)
908 REMOTE_KEY(0x14, KEY_UNDO)
909 REMOTE_KEY(0x44, KEY_UP)
910 REMOTE_KEY(0x1D, KEY_DOWN)
911 REMOTE_KEY(0x1C, KEY_LEFT)
912 REMOTE_KEY(0x48, KEY_RIGHT)
913 REMOTE_KEY(0x53, KEY_LEFTMETA)
914 REMOTE_KEY(0x45, KEY_PAGEUP)
915 REMOTE_KEY(0x19, KEY_PAGEDOWN)
916 REMOTE_KEY(0x52, KEY_PAUSE)
917 REMOTE_KEY(0x05, KEY_HANGEUL)
918 REMOTE_KEY(0x59, KEY_HANJA)
919 REMOTE_KEY(0x1b, KEY_SCALE)
920 REMOTE_KEY(0x04, KEY_KPCOMMA)
921 REMOTE_KEY(0x1A, KEY_POWER)
922 REMOTE_KEY(0x0A, KEY_TAB)
923 REMOTE_KEY(0x0e, KEY_MUTE)
924 REMOTE_KEY(0x1F, KEY_HOME)
925 REMOTE_KEY(0x1e, KEY_FRONT)
926 REMOTE_KEY(0x07, KEY_COPY)
927 REMOTE_KEY(0x12, KEY_OPEN)
928 REMOTE_KEY(0x54, KEY_PASTE)
929 REMOTE_KEY(0x02, KEY_FIND)
930 REMOTE_KEY(0x4f, KEY_A)
931 REMOTE_KEY(0x42, KEY_B)
932 REMOTE_KEY(0x5d, KEY_C)
933 REMOTE_KEY(0x4c, KEY_D)
934 REMOTE_KEY(0x58, KEY_CUT)
935 REMOTE_KEY(0x55, KEY_CALC)>;
936 };
937 map_1: map_1{
938 mapname = "amlogic-remote-2";
939 customcode = <0xfe01>;
940 release_delay = <80>;
941 size = <53>;
942 keymap = <REMOTE_KEY(0x01, KEY_1)
943 REMOTE_KEY(0x02, KEY_2)
944 REMOTE_KEY(0x03, KEY_3)
945 REMOTE_KEY(0x04, KEY_4)
946 REMOTE_KEY(0x05, KEY_5)
947 REMOTE_KEY(0x06, KEY_6)
948 REMOTE_KEY(0x07, KEY_7)
949 REMOTE_KEY(0x08, KEY_8)
950 REMOTE_KEY(0x09, KEY_9)
951 REMOTE_KEY(0x0a, KEY_0)
952 REMOTE_KEY(0x1F, KEY_FN_F1)
953 REMOTE_KEY(0x15, KEY_MENU)
954 REMOTE_KEY(0x16, KEY_TAB)
955 REMOTE_KEY(0x0c, KEY_CHANNELUP)
956 REMOTE_KEY(0x0d, KEY_CHANNELDOWN)
957 REMOTE_KEY(0x0e, KEY_VOLUMEUP)
958 REMOTE_KEY(0x0f, KEY_VOLUMEDOWN)
959 REMOTE_KEY(0x11, KEY_HOME)
960 REMOTE_KEY(0x1c, KEY_RIGHT)
961 REMOTE_KEY(0x1b, KEY_LEFT)
962 REMOTE_KEY(0x19, KEY_UP)
963 REMOTE_KEY(0x1a, KEY_DOWN)
964 REMOTE_KEY(0x1d, KEY_ENTER)
965 REMOTE_KEY(0x17, KEY_MUTE)
966 REMOTE_KEY(0x49, KEY_FINANCE)
967 REMOTE_KEY(0x43, KEY_BACK)
968 REMOTE_KEY(0x12, KEY_FN_F4)
969 REMOTE_KEY(0x14, KEY_FN_F5)
970 REMOTE_KEY(0x18, KEY_FN_F6)
971 REMOTE_KEY(0x59, KEY_INFO)
972 REMOTE_KEY(0x5a, KEY_STOPCD)
973 REMOTE_KEY(0x10, KEY_POWER)
974 REMOTE_KEY(0x42, KEY_PREVIOUSSONG)
975 REMOTE_KEY(0x44, KEY_NEXTSONG)
976 REMOTE_KEY(0x1e, KEY_REWIND)
977 REMOTE_KEY(0x4b, KEY_FASTFORWARD)
978 REMOTE_KEY(0x58, KEY_PLAYPAUSE)
979 REMOTE_KEY(0x46, KEY_PROPS)
980 REMOTE_KEY(0x40, KEY_UNDO)
981 REMOTE_KEY(0x38, KEY_SCROLLLOCK)
982 REMOTE_KEY(0x57, KEY_FN)
983 REMOTE_KEY(0x5b, KEY_FN_ESC)
984 REMOTE_KEY(0x54, KEY_RED)
985 REMOTE_KEY(0x4c, KEY_GREEN)
986 REMOTE_KEY(0x4e, KEY_YELLOW)
987 REMOTE_KEY(0x55, KEY_BLUE)
988 REMOTE_KEY(0x53, KEY_BLUETOOTH)
989 REMOTE_KEY(0x52, KEY_WLAN)
990 REMOTE_KEY(0x39, KEY_CAMERA)
991 REMOTE_KEY(0x41, KEY_SOUND)
992 REMOTE_KEY(0x0b, KEY_QUESTION)
993 REMOTE_KEY(0x00, KEY_CHAT)
994 REMOTE_KEY(0x13, KEY_SEARCH)>;
995 };
996 map_2: map_2{
997 mapname = "amlogic-remote-3";
998 customcode = <0xbd02>;
999 release_delay = <80>;
1000 size = <17>;
1001 keymap = <REMOTE_KEY(0xca,103)
1002 REMOTE_KEY(0xd2,108)
1003 REMOTE_KEY(0x99,105)
1004 REMOTE_KEY(0xc1,106)
1005 REMOTE_KEY(0xce,97)
1006 REMOTE_KEY(0x45,116)
1007 REMOTE_KEY(0xc5,133)
1008 REMOTE_KEY(0x80,113)
1009 REMOTE_KEY(0xd0,15)
1010 REMOTE_KEY(0xd6,125)
1011 REMOTE_KEY(0x95,102)
1012 REMOTE_KEY(0xdd,104)
1013 REMOTE_KEY(0x8c,109)
1014 REMOTE_KEY(0x89,131)
1015 REMOTE_KEY(0x9c,130)
1016 REMOTE_KEY(0x9a,120)
1017 REMOTE_KEY(0xcd,121)>;
1018 };
1019 };
1020
1021 uart_A: serial@ffd24000 {
1022 compatible = "amlogic, meson-uart";
1023 reg = <0xffd24000 0x18>;
1024 interrupts = <0 26 1>;
1025 status = "disabled";
1026 clocks = <&xtal
1027 &clkc CLKID_UART0>;
1028 clock-names = "clk_uart",
1029 "clk_gate";
1030 fifosize = < 128 >;
1031 pinctrl-names = "default";
1032 pinctrl-0 = <&a_uart_pins>;
1033 };
1034
1035 uart_B: serial@ffd23000 {
1036 compatible = "amlogic, meson-uart";
1037 reg = <0xffd23000 0x18>;
1038 interrupts = <0 75 1>;
1039 status = "disabled";
1040 clocks = <&xtal
1041 &clkc CLKID_UART1>;
1042 clock-names = "clk_uart",
1043 "clk_gate";
1044 fifosize = < 64 >;
1045 pinctrl-names = "default";
1046 pinctrl-0 = <&b_uart_pins>;
1047 };
1048
1049 uart_C: serial@ffd22000 {
1050 compatible = "amlogic, meson-uart";
1051 reg = <0xffd22000 0x18>;
1052 interrupts = <0 93 1>;
1053 status = "disabled";
1054 clocks = <&xtal
1055 &clkc CLKID_UART1>;
1056 clock-names = "clk_uart",
1057 "clk_gate";
1058 fifosize = < 64 >;
1059 pinctrl-names = "default";
1060 pinctrl-0 = <&c_uart_pins>;
1061 };
1062
1063
1064 pcie_A: pcieA@fc000000 {
1065 compatible = "amlogic, amlogic-pcie-v2", "snps,dw-pcie";
1066 reg = <0xfc000000 0x400000
1067 0xff648000 0x2000
1068 0xfc400000 0x200000
1069 0xff646000 0x2000
1070 0xffd01080 0x10>;
1071 reg-names = "elbi", "cfg", "config", "phy", "reset";
1072 interrupts = <0 221 0>;
1073 #interrupt-cells = <1>;
1074 bus-range = <0x0 0xff>;
1075 #address-cells = <3>;
1076 #size-cells = <2>;
1077 interrupt-map-mask = <0 0 0 0>;
1078 interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_EDGE_RISING>;
1079 device_type = "pci";
1080 ranges = <0x81000000 0 0 0xfc600000 0x0 0x100000
1081 /* downstream I/O */
1082 0x82000000 0 0xfc700000 0xfc700000 0 0x1900000>;
1083 /* non-prefetchable memory */
1084 num-lanes = <1>;
1085 pcie-num = <1>;
1086
1087 clocks = <&clkc CLKID_PCIE_PLL
1088 &clkc CLKID_PCIE_COMB
1089 &clkc CLKID_PCIE_PHY>;
1090 clock-names = "pcie_refpll",
1091 "pcie",
1092 "pcie_phy";
1093 /*reset-gpio-type 0:Shared pad(no reset)1:OD pad2:Normal pad*/
1094 gpio-type = <2>;
1095 pcie-apb-rst-bit = <15>;
1096 pcie-phy-rst-bit = <14>;
1097 pcie-ctrl-a-rst-bit = <12>;
1098 status = "disabled";
1099 };
1100
1101 amhdmitx: amhdmitx{
1102 compatible = "amlogic, amhdmitx";
1103 dev_name = "amhdmitx";
1104 status = "okay";
1105 vend-data = <&vend_data>;
1106 pinctrl-names="default", "hdmitx_i2c";
1107 pinctrl-0=<&hdmitx_hpd &hdmitx_ddc>;
1108 pinctrl-1=<&hdmitx_hpd_gpio &i2c3_master_pins1>;
1109 clocks = <&clkc CLKID_VCLK2_ENCI
1110 &clkc CLKID_VCLK2_VENCI0
1111 &clkc CLKID_VCLK2_VENCI1
1112 &clkc CLKID_VAPB_MUX
1113 &clkc CLKID_VPU_MUX>;
1114 clock-names = "venci_top_gate",
1115 "venci_0_gate",
1116 "venci_1_gate",
1117 "hdmi_vapb_clk",
1118 "hdmi_vpu_clk";
1119 /* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
1120 interrupts = <0 57 1>;
1121 interrupt-names = "hdmitx_hpd";
1122 /* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
1123 * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
1124 * 10:G12A 11:G12B
1125 */
1126 ic_type = <11>;
1127 vend_data: vend_data{ /* Should modified by Customer */
1128 vendor_name = "Amlogic"; /* Max Chars: 8 */
1129 /* standards.ieee.org/develop/regauth/oui/oui.txt */
1130 vendor_id = <0x000000>;
1131 };
1132 };
1133
1134 galcore {
1135 compatible = "amlogic, galcore";
1136 dev_name = "galcore";
1137 status = "disabled";
1138 clocks = <&clkc CLKID_VNANOQ_AXI_CLK_COMP>,
1139 <&clkc CLKID_VNANOQ_CORE_CLK_COMP>;
1140 clock-names = "cts_vipnanoq_axi_clk_composite",
1141 "cts_vipnanoq_core_clk_composite";
1142 interrupts = <0 147 1>;
1143 interrupt-names = "galcore";
1144 reg = <0xff100000 0x800
1145 0xff000000 0x400000>;
1146 };
1147
1148 aocec: aocec {
1149 compatible = "amlogic, aocec-g12a";
1150 device_name = "aocec";
1151 status = "okay";
1152 vendor_name = "Amlogic"; /* Max Chars: 8 */
1153 /* Refer to the following URL at:
1154 * http://standards.ieee.org/develop/regauth/oui/oui.txt
1155 */
1156 vendor_id = <0x000000>;
1157 product_desc = "G12B"; /* Max Chars: 16 */
1158 cec_osd_string = "AML_MBOX"; /* Max Chars: 14 */
1159 port_num = <1>;
1160 ee_cec;
1161 arc_port_mask = <0x2>;
1162 interrupts = <0 203 1
1163 0 199 1>; /*0:snps 1:ts*/
1164 interrupt-names = "hdmi_aocecb","hdmi_aocec";
1165 pinctrl-names = "default","hdmitx_aocecb","cec_pin_sleep";
1166 pinctrl-0=<&eecec_a>;
1167 pinctrl-1=<&eecec_b>;
1168 pinctrl-2=<&eecec_b>;
1169 reg = <0xFF80023c 0x4
1170 0xFF800000 0x400
1171 0xFF634400 0x26>;
1172 reg-names = "ao_exit","ao","periphs";
1173 };
1174
1175 /*if you want to use vdin just modify status to "ok"*/
1176 vdin0: vdin0 {
1177 compatible = "amlogic, vdin";
1178 dev_name = "vdin0";
1179 status = "disabled";
1180 reserve-iomap = "true";
1181 flag_cma = <0>;/*1:share with codec_mm;2:cma alone*/
1182 /*MByte, if 10bit disable: 64M(YUV422),
1183 *if 10bit enable: 64*1.5 = 96M(YUV422)
1184 *if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M
1185 *if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M
1186 *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M
1187 *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M
1188 */
1189 /*cma_size = <16>;*/
1190 interrupts = <0 83 1>;
1191 rdma-irq = <2>;
1192 /*clocks = <&clock CLK_FPLL_DIV5>,
1193 * <&clock CLK_VDIN_MEAS_CLK>;
1194 *clock-names = "fclk_div5", "cts_vdin_meas_clk";
1195 */
1196 vdin_id = <0>;
1197 };
1198 vdin1: vdin1 {
1199 compatible = "amlogic, vdin";
1200 dev_name = "vdin1";
1201 status = "disabled";
1202 reserve-iomap = "true";
1203 flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/
1204 interrupts = <0 85 1>;
1205 rdma-irq = <4>;
1206 /*clocks = <&clock CLK_FPLL_DIV5>,
1207 * <&clock CLK_VDIN_MEAS_CLK>;
1208 *clock-names = "fclk_div5", "cts_vdin_meas_clk";
1209 */
1210 vdin_id = <1>;
1211 };
1212
1213 vout {
1214 compatible = "amlogic, vout";
1215 dev_name = "vout";
1216 status = "okay";
1217 };
1218
1219 vout2 {
1220 compatible = "amlogic, vout2";
1221 dev_name = "vout";
1222 status = "okay";
1223 clocks = <&clkc CLKID_VPU_CLKC_P0_COMP>,
1224 <&clkc CLKID_VPU_CLKC_MUX>;
1225 clock-names = "vpu_clkc0",
1226 "vpu_clkc";
1227 };
1228
1229 vdac {
1230 compatible = "amlogic, vdac-g12b";
1231 status = "okay";
1232 };
1233
1234 canvas: canvas{
1235 compatible = "amlogic, meson, canvas";
1236 dev_name = "amlogic-canvas";
1237 status = "okay";
1238 reg = <0xff638000 0x2000>;
1239 };
1240
1241 ge2d {
1242 compatible = "amlogic, ge2d-g12a";
1243 dev_name = "ge2d";
1244 status = "okay";
1245 interrupts = <0 146 1>;
1246 interrupt-names = "ge2d";
1247 clocks = <&clkc CLKID_VAPB_MUX>,
1248 <&clkc CLKID_G2D>,
1249 <&clkc CLKID_GE2D_GATE>;
1250 clock-names = "clk_vapb_0",
1251 "clk_ge2d",
1252 "clk_ge2d_gate";
1253 reg = <0xff940000 0x10000>;
1254 };
1255
1256 meson-amvideom {
1257 compatible = "amlogic, amvideom";
1258 dev_name = "amvideom";
1259 status = "okay";
1260 interrupts = <0 3 1>;
1261 interrupt-names = "vsync";
1262 };
1263
1264 codec_io: codec_io {
1265 compatible = "amlogic, codec_io";
1266 status = "okay";
1267 #address-cells=<1>;
1268 #size-cells=<1>;
1269 ranges;
1270 io_cbus_base{
1271 reg = <0xffd00000 0x100000>;
1272 };
1273 io_dos_base{
1274 reg = <0xff620000 0x10000>;
1275 };
1276 io_hiubus_base{
1277 reg = <0xff63c000 0x2000>;
1278 };
1279 io_aobus_base{
1280 reg = <0xff800000 0x10000>;
1281 };
1282 io_vcbus_base{
1283 reg = <0xff900000 0x40000>;
1284 };
1285 io_dmc_base{
1286 reg = <0xff638000 0x2000>;
1287 };
1288 io_efuse_base{
1289 reg = <0xff630000 0x2000>;
1290 };
1291 };
1292
1293 gdc:gdc {
1294 #address-cells=<1>;
1295 #size-cells=<1>;
1296 status = "ok";
1297 compatible = "amlogic, g12b-gdc";
1298 reg = <0xFF950000 0x0000100
1299 0xFF63C16C 0x0000004
1300 0xFF63C100 0x0000004>;
1301 interrupts = <0 144 1>;
1302 interrupt-names = "GDC";
1303 clocks = <&clkc CLKID_GDC_CORE_CLK_COMP
1304 &clkc CLKID_GDC_AXI_CLK_COMP >;
1305 clock-names = "core","axi";
1306 };
1307
1308 mesonstream {
1309 compatible = "amlogic, codec, streambuf";
1310 dev_name = "mesonstream";
1311 status = "okay";
1312 clocks = <&clkc CLKID_DOS_PARSER
1313 &clkc CLKID_DEMUX
1314 &clkc CLKID_AHB_ARB0
1315 &clkc CLKID_DOS
1316 &clkc CLKID_VDEC_MUX
1317 &clkc CLKID_HCODEC_MUX
1318 &clkc CLKID_HEVC_MUX
1319 &clkc CLKID_HEVCF_MUX>;
1320 clock-names = "parser_top",
1321 "demux",
1322 "ahbarb0",
1323 "vdec",
1324 "clk_vdec_mux",
1325 "clk_hcodec_mux",
1326 "clk_hevc_mux",
1327 "clk_hevcb_mux";
1328 };
1329
1330 vdec {
1331 compatible = "amlogic, vdec";
1332 dev_name = "vdec.0";
1333 status = "okay";
1334 interrupts = <0 3 1
1335 0 23 1
1336 0 32 1
1337 0 43 1
1338 0 44 1
1339 0 45 1>;
1340 interrupt-names = "vsync",
1341 "demux",
1342 "parser",
1343 "mailbox_0",
1344 "mailbox_1",
1345 "mailbox_2";
1346 };
1347
1348 amvenc_avc{
1349 compatible = "amlogic, amvenc_avc";
1350 dev_name = "amvenc_avc";
1351 status = "okay";
1352 interrupts = <0 45 1>;
1353 interrupt-names = "mailbox_2";
1354 };
1355
1356 hevc_enc{
1357 compatible = "cnm, HevcEnc";
1358 //memory-region = <&hevc_enc_reserved>;
1359 dev_name = "HevcEnc";
1360 status = "okay";
1361 interrupts = <0 187 1>;
1362 interrupt-names = "wave420l_irq";
1363 #address-cells=<1>;
1364 #size-cells=<1>;
1365 ranges;
1366 io_reg_base{
1367 reg = <0xff610000 0x4000>;
1368 };
1369 };
1370
1371 rdma{
1372 compatible = "amlogic, meson, rdma";
1373 dev_name = "amlogic-rdma";
1374 status = "okay";
1375 interrupts = <0 89 1>;
1376 interrupt-names = "rdma";
1377 };
1378
1379 meson_fb: meson-fb {
1380 compatible = "amlogic, meson-g12b";
1381 memory-region = <&logo_reserved>;
1382 dev_name = "meson-fb";
1383 status = "disable";
1384 interrupts = <0 3 1
1385 0 56 1
1386 0 89 1>;
1387 interrupt-names = "viu-vsync", "viu2-vsync", "rdma";
1388 /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/
1389 display_mode_default = "1080p60hz";
1390 scale_mode = <1>;
1391 /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */
1392 display_size_default = <1920 1080 1920 2160 32>;
1393 /*1920*1080*4*3 = 0x17BB000*/
1394 clocks = <&clkc CLKID_VPU_CLKC_MUX>;
1395 clock-names = "vpu_clkc";
1396 };
1397 irblaster: meson-irblaster {
1398 compatible = "amlogic, meson_irblaster";
1399 reg = <0xff80014c 0x10>,
1400 <0xff800040 0x4>;
1401 pinctrl-names = "default";
1402 pinctrl-0 = <&irblaster_pins>;
1403 interrupts = <0 198 1>;
1404 status = "disabled";
1405 };
1406
1407 sd_emmc_c: emmc@ffe07000 {
1408 status = "disabled";
1409 compatible = "amlogic, meson-mmc-g12b";
1410 reg = <0xffe07000 0x800>;
1411 interrupts = <0 191 1>;
1412 pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins";
1413 pinctrl-0 = <&emmc_clk_cmd_pins>;
1414 pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>;
1415 clocks = <&clkc CLKID_SD_EMMC_C>,
1416 <&clkc CLKID_SD_EMMC_C_P0_COMP>,
1417 <&clkc CLKID_FCLK_DIV2>,
1418 <&clkc CLKID_FCLK_DIV5>,
1419 <&xtal>;
1420 clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal";
1421
1422 bus-width = <8>;
1423 cap-sd-highspeed;
1424 cap-mmc-highspeed;
1425 /* mmc-ddr-1_8v; */
1426 /* mmc-hs200-1_8v; */
1427
1428 max-frequency = <200000000>;
1429 non-removable;
1430 disable-wp;
1431 emmc {
1432 pinname = "emmc";
1433 ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */
1434 /*caps defined in dts*/
1435 tx_delay = <0>;
1436 max_req_size = <0x20000>; /**128KB*/
1437 gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>;
1438 hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>;
1439 card_type = <1>;
1440 /* 1:mmc card(include eMMC),
1441 * 2:sd card(include tSD)
1442 */
1443 };
1444 };
1445
1446 sd_emmc_b:sd@ffe05000 {
1447 status = "disabled";
1448 compatible = "amlogic, meson-mmc-g12b";
1449 reg = <0xffe05000 0x800>;
1450 interrupts = <0 190 1>;
1451
1452 pinctrl-names = "sd_all_pins",
1453 "sd_clk_cmd_pins",
1454 "sd_1bit_pins",
1455 "sd_clk_cmd_uart_pins",
1456 "sd_1bit_uart_pins",
1457 "sd_to_ao_uart_pins",
1458 "ao_to_sd_uart_pins",
1459 "sd_to_ao_jtag_pins",
1460 "ao_to_sd_jtag_pins";
1461 pinctrl-0 = <&sd_all_pins>;
1462 pinctrl-1 = <&sd_clk_cmd_pins>;
1463 pinctrl-2 = <&sd_1bit_pins>;
1464 pinctrl-3 = <&sd_to_ao_uart_clr_pins
1465 &sd_clk_cmd_pins &ao_to_sd_uart_pins>;
1466 pinctrl-4 = <&sd_to_ao_uart_clr_pins
1467 &sd_1bit_pins &ao_to_sd_uart_pins>;
1468 pinctrl-5 = <&sd_all_pins &sd_to_ao_uart_pins>;
1469 pinctrl-6 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>;
1470 pinctrl-7 = <&sd_all_pins &sd_to_ao_uart_pins>;
1471 pinctrl-8 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>;
1472
1473 clocks = <&clkc CLKID_SD_EMMC_B>,
1474 <&clkc CLKID_SD_EMMC_B_P0_COMP>,
1475 <&clkc CLKID_FCLK_DIV2>,
1476 <&clkc CLKID_FCLK_DIV5>,
1477 <&xtal>;
1478 clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal";
1479
1480 bus-width = <4>;
1481 cap-sd-highspeed;
1482 cap-mmc-highspeed;
1483 max-frequency = <100000000>;
1484 disable-wp;
1485 sd {
1486 pinname = "sd";
1487 ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */
1488 max_req_size = <0x20000>; /**128KB*/
1489 gpio_dat3 = <&gpio GPIOC_3 GPIO_ACTIVE_HIGH>;
1490 jtag_pin = <&gpio GPIOC_0 GPIO_ACTIVE_HIGH>;
1491 gpio_cd = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
1492 card_type = <5>;
1493 /* 3:sdio device(ie:sdio-wifi),
1494 * 4:SD combo (IO+mem) card
1495 */
1496 };
1497 };
1498
1499 sd_emmc_a:sdio@ffe03000 {
1500 status = "disabled";
1501 compatible = "amlogic, meson-mmc-g12b";
1502 reg = <0xffe03000 0x800>;
1503 interrupts = <0 189 4>;
1504
1505 pinctrl-names = "sdio_all_pins",
1506 "sdio_clk_cmd_pins";
1507 pinctrl-0 = <&sdio_all_pins>;
1508 pinctrl-1 = <&sdio_clk_cmd_pins>;
1509
1510 clocks = <&clkc CLKID_SD_EMMC_A>,
1511 <&clkc CLKID_SD_EMMC_A_P0_COMP>,
1512 <&clkc CLKID_FCLK_DIV2>,
1513 <&clkc CLKID_FCLK_DIV5>,
1514 <&xtal>;
1515 clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal";
1516
1517 bus-width = <4>;
1518 cap-sd-highspeed;
1519 cap-mmc-highspeed;
1520 max-frequency = <100000000>;
1521 disable-wp;
1522 sdio {
1523 pinname = "sdio";
1524 ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */
1525 max_req_size = <0x20000>; /**128KB*/
1526 card_type = <3>;
1527 /* 3:sdio device(ie:sdio-wifi),
1528 * 4:SD combo (IO+mem) card
1529 */
1530 };
1531 };
1532
1533 nand: nfc@0 {
1534 compatible = "amlogic, aml_mtd_nand";
1535 dev_name = "mtdnand";
1536 status = "disabled";
1537 reg = <0xFFE07800 0x200>;
1538 interrupts = <0 34 1>;
1539
1540 pinctrl-names = "nand_rb_mod","nand_norb_mod", "nand_cs_only";
1541 pinctrl-0 = <&all_nand_pins>;
1542 pinctrl-1 = <&all_nand_pins>;
1543 pinctrl-2 = <&nand_cs_pins>;
1544 clocks = <&clkc CLKID_SD_EMMC_C>,
1545 <&clkc CLKID_SD_EMMC_C_P0_COMP>;
1546 clock-names = "core", "clkin";
1547
1548 device_id = <0>;
1549 /*fip/tpl configurations, must be same
1550 * with uboot if bl_mode was set as 1
1551 * bl_mode: 0 compact mode; 1 descrete mode
1552 * if bl_mode was set as 1, fip configuration will work
1553 */
1554 bl_mode = <1>;
1555 /*copy count of fip*/
1556 fip_copies = <4>;
1557 /*size of each fip copy */
1558 fip_size = <0x200000>;
1559 nand_clk_ctrl = <0xFFE07000>;
1560 /*partions defined in dts */
1561 };
1562
1563 meson_cooldev: meson-cooldev@0 {
1564 status = "okay";
1565 compatible = "amlogic, meson-cooldev";
1566 device_name = "mcooldev";
1567 cooling_devices {
1568 cpufreq_cool_cluster0 {
1569 min_state = <1000000>;
1570 dyn_coeff = <120>;
1571 cluster_id = <0>;
1572 gpu_pp = <2>;
1573 node_name = "cpufreq_cool0";
1574 device_type = "cpufreq";
1575 };
1576 cpufreq_cool_cluster1 {
1577 min_state = <1000000>;
1578 dyn_coeff = <460>;
1579 cluster_id = <1>;
1580 gpu_pp = <2>;
1581 node_name = "cpufreq_cool1";
1582 device_type = "cpufreq";
1583 };
1584 cpucore_cool_cluster0 {
1585 min_state = <1>;
1586 dyn_coeff = <0>;
1587 cluster_id = <0>;
1588 gpu_pp = <2>;
1589 node_name = "cpucore_cool0";
1590 device_type = "cpucore";
1591 };
1592 cpucore_cool_cluster1 {
1593 min_state = <0>;
1594 dyn_coeff = <0>;
1595 cluster_id = <1>;
1596 gpu_pp = <2>;
1597 node_name = "cpucore_cool1";
1598 device_type = "cpucore";
1599 };
1600 gpufreq_cool {
1601 min_state = <400>;
1602 dyn_coeff = <358>;
1603 cluster_id = <0>;
1604 gpu_pp = <2>;
1605 node_name = "gpufreq_cool0";
1606 device_type = "gpufreq";
1607 };
1608 gpucore_cool {
1609 min_state = <1>;
1610 dyn_coeff = <0>;
1611 cluster_id = <0>;
1612 gpu_pp = <2>;
1613 node_name = "gpucore_cool0";
1614 device_type = "gpucore";
1615 };
1616 };
1617 cpufreq_cool0:cpufreq_cool0 {
1618 #cooling-cells = <2>; /* min followed by max */
1619 };
1620 cpufreq_cool1:cpufreq_cool1 {
1621 #cooling-cells = <2>; /* min followed by max */
1622 };
1623 cpucore_cool0:cpucore_cool0 {
1624 #cooling-cells = <2>; /* min followed by max */
1625 };
1626 cpucore_cool1:cpucore_cool1 {
1627 #cooling-cells = <2>; /* min followed by max */
1628 };
1629 gpufreq_cool0:gpufreq_cool0 {
1630 #cooling-cells = <2>; /* min followed by max */
1631 };
1632 gpucore_cool0:gpucore_cool0 {
1633 #cooling-cells = <2>; /* min followed by max */
1634 };
1635 };
1636 /*meson cooling devices end*/
1637
1638 thermal-zones {
1639 soc_thermal: soc_thermal {
1640 polling-delay = <1000>;
1641 polling-delay-passive = <100>;
1642 sustainable-power = <3550>;
1643 thermal-sensors = <&p_tsensor 0>;
1644 trips {
1645 pswitch_on: trip-point@0 {
1646 temperature = <60000>;
1647 hysteresis = <5000>;
1648 type = "passive";
1649 };
1650 pcontrol: trip-point@1 {
1651 temperature = <75000>;
1652 hysteresis = <5000>;
1653 type = "passive";
1654 };
1655 phot: trip-point@2 {
1656 temperature = <85000>;
1657 hysteresis = <5000>;
1658 type = "hot";
1659 };
1660 pcritical: trip-point@3 {
1661 temperature = <110000>;
1662 hysteresis = <1000>;
1663 type = "critical";
1664 };
1665 };
1666
1667 cooling-maps {
1668 cpufreq_cooling_map0 {
1669 trip = <&pcontrol>;
1670 cooling-device = <&cpufreq_cool0 0 10>;
1671 contribution = <1024>;
1672 };
1673 cpufreq_cooling_map1 {
1674 trip = <&pcontrol>;
1675 cooling-device = <&cpufreq_cool1 0 9>;
1676 contribution = <1024>;
1677 };
1678 cpucore_cooling_map0 {
1679 trip = <&pcontrol>;
1680 cooling-device = <&cpucore_cool0 0 1>;
1681 contribution = <1024>;
1682 };
1683 cpucore_cooling_map1 {
1684 trip = <&pcontrol>;
1685 cooling-device = <&cpucore_cool1 0 4>;
1686 contribution = <1024>;
1687 };
1688 gpufreq_cooling_map {
1689 trip = <&pcontrol>;
1690 cooling-device = <&gpufreq_cool0 0 4>;
1691 contribution = <1024>;
1692 };
1693 gpucore_cooling_map {
1694 trip = <&pcontrol>;
1695 cooling-device = <&gpucore_cool0 0 2>;
1696 contribution = <1024>;
1697 };
1698 };
1699 };
1700 ddr_thermal: ddr_thermal {
1701 polling-delay = <1000>;
1702 polling-delay-passive = <100>;
1703 sustainable-power = <3550>;
1704 thermal-sensors = <&d_tsensor 1>;
1705 trips {
1706 dswitch_on: trip-point@0 {
1707 temperature = <60000>;
1708 hysteresis = <5000>;
1709 type = "passive";
1710 };
1711 dcontrol: trip-point@1 {
1712 temperature = <75000>;
1713 hysteresis = <5000>;
1714 type = "passive";
1715 };
1716 dhot: trip-point@2 {
1717 temperature = <85000>;
1718 hysteresis = <5000>;
1719 type = "hot";
1720 };
1721 dcritical: trip-point@3 {
1722 temperature = <110000>;
1723 hysteresis = <1000>;
1724 type = "critical";
1725 };
1726 };
1727
1728 };
1729 };
1730 /*thermal zone end*/
1731
1732 /* Sound iomap */
1733 aml_snd_iomap {
1734 compatible = "amlogic, snd-iomap";
1735 status = "okay";
1736 #address-cells=<1>;
1737 #size-cells=<1>;
1738 ranges;
1739 pdm_bus {
1740 reg = <0xFF640000 0x2000>;
1741 };
1742 audiobus_base {
1743 reg = <0xFF642000 0x2000>;
1744 };
1745 audiolocker_base {
1746 reg = <0xFF64A000 0x2000>;
1747 };
1748 eqdrc_base {
1749 reg = <0xFF656000 0x1800>;
1750 };
1751 reset_base {
1752 reg = <0xFFD01000 0x1000>;
1753 };
1754 };
1755
1756 vddcpu0: pwmao_d-regulator {
1757 compatible = "pwm-regulator";
1758 pinctrl-names = "default";
1759 pinctrl-0 = <&pwm_ao_d_pins3>;
1760 pwms = <&pwm_AO_cd MESON_PWM_1 1250 0>;
1761 regulator-name = "vddcpu0";
1762 regulator-min-microvolt = <721000>;
1763 regulator-max-microvolt = <1022000>;
1764 regulator-always-on;
1765 max-duty-cycle = <1250>;
1766 /* Voltage Duty-Cycle */
1767 voltage-table = <1022000 0>,
1768 <1011000 3>,
1769 <1001000 6>,
1770 <991000 10>,
1771 <981000 13>,
1772 <971000 16>,
1773 <961000 20>,
1774 <951000 23>,
1775 <941000 26>,
1776 <931000 30>,
1777 <921000 33>,
1778 <911000 36>,
1779 <901000 40>,
1780 <891000 43>,
1781 <881000 46>,
1782 <871000 50>,
1783 <861000 53>,
1784 <851000 56>,
1785 <841000 60>,
1786 <831000 63>,
1787 <821000 67>,
1788 <811000 70>,
1789 <801000 73>,
1790 <791000 76>,
1791 <781000 80>,
1792 <771000 83>,
1793 <761000 86>,
1794 <751000 90>,
1795 <741000 93>,
1796 <731000 96>,
1797 <721000 100>;
1798 status = "okay";
1799 };
1800
1801 vddcpu1: pwmab_a-regulator {
1802 compatible = "pwm-regulator";
1803 pinctrl-names = "default";
1804 pinctrl-0 = <&pwm_a_e2>;
1805 pwms = <&pwm_ab MESON_PWM_0 1250 0>;
1806 regulator-name = "vddcpu1";
1807 regulator-min-microvolt = <721000>;
1808 regulator-max-microvolt = <1022000>;
1809 regulator-always-on;
1810 max-duty-cycle = <1250>;
1811 /* Voltage Duty-Cycle */
1812 voltage-table = <1022000 0>,
1813 <1011000 3>,
1814 <1001000 6>,
1815 <991000 10>,
1816 <981000 13>,
1817 <971000 16>,
1818 <961000 20>,
1819 <951000 23>,
1820 <941000 26>,
1821 <931000 30>,
1822 <921000 33>,
1823 <911000 36>,
1824 <901000 40>,
1825 <891000 43>,
1826 <881000 46>,
1827 <871000 50>,
1828 <861000 53>,
1829 <851000 56>,
1830 <841000 60>,
1831 <831000 63>,
1832 <821000 67>,
1833 <811000 70>,
1834 <801000 73>,
1835 <791000 76>,
1836 <781000 80>,
1837 <771000 83>,
1838 <761000 86>,
1839 <751000 90>,
1840 <741000 93>,
1841 <731000 96>,
1842 <721000 100>;
1843 status = "okay";
1844 };
1845
1846 rng {
1847 compatible = "amlogic,meson-rng";
1848 status = "okay";
1849 #address-cells = <1>;
1850 #size-cells = <1>;
1851 reg = <0xff630218 0x4>;
1852 quality = /bits/ 16 <1000>;
1853 };
1854
1855 ddr_bandwidth {
1856 compatible = "amlogic, ddr-bandwidth";
1857 status = "okay";
1858 reg = <0xff638000 0x100
1859 0xff638c00 0x100>;
1860 interrupts = <0 52 1>;
1861 interrupt-names = "ddr_bandwidth";
1862 };
1863 dmc_monitor {
1864 compatible = "amlogic, dmc_monitor";
1865 status = "okay";
1866 reg_base = <0xff639000>;
1867 interrupts = <0 51 1>;
1868 };
1869
1870 isp_sc: isp-sc@ff655400 {
1871 compatible = "amlogic, isp-sc";
1872 reg = <0xff655400 0x00001000>;
1873 reg-names = "isp_sc";
1874 interrupts = <0 17 0>;
1875 interrupt-names = "isp_sc";
1876 };
1877
1878 isp: isp@ff140000 {
1879 compatible = "arm, isp";
1880 reg = <0xff140000 0x00040000>;
1881 reg-names = "ISP";
1882 interrupts = <0 142 4>;
1883 interrupt-names = "ISP";
1884 temper-buf-size = <24>;
1885 clocks = <&clkc CLKID_MIPI_ISP_CLK_COMP>,
1886 <&clkc CLKID_MIPI_CSI_PHY_CLK0_COMP>;
1887 clock-names = "cts_mipi_isp_clk_composite",
1888 "cts_mipi_csi_phy_clk0_composite";
1889 link-device = <&isp_sc>;
1890 };
1891
1892 adapter: isp-adapter@ff650000 {
1893 compatible = "amlogic, isp-adapter";
1894 reg = <0xff650000 0x00006000>;
1895 reg-names = "adapter";
1896 interrupts = <0 179 0>;
1897 interrupt-names = "adapter-irq";
1898 };
1899
1900 phycsi: phy-csi@ff650000 {
1901 compatible = "amlogic, phy-csi";
1902 reg = <0xff650000 0x00002000>,
1903 <0xff652000 0x00002000>,
1904 <0xff63c300 0x00000100>,
1905 <0xff654000 0x00000100>,
1906 <0xff654400 0x00000100>;
1907 reg-names = "csi2_phy0", "csi2_phy1", "aphy_reg",
1908 "csi0_host", "csi1_host";
1909 interrupts = <0 41 0>,
1910 <0 42 0>,
1911 <0 72 0>,
1912 <0 74 0>,
1913 <0 87 0>,
1914 <0 88 0>;
1915 interrupt-names = "phy0-irq",
1916 "phy1-irq",
1917 "csi-host0-intr2",
1918 "csi-host0-intr1",
1919 "csi-host1-intr2",
1920 "csi-host1-intr1";
1921 link-device = <&adapter>;
1922 };
1923
1924 defendkey: defendkey {
1925 compatible = "amlogic, defendkey";
1926 reg = <0xff630218 0x4>; /*RNG_USR_DATA*/
1927 mem_size = <0 0x100000>;
1928 status = "okay";
1929 };
1930};/* end of / */
1931
1932&pinctrl_aobus {
1933 ao_uart_pins:ao_uart {
1934 mux {
1935 groups = "uart_ao_tx_a",
1936 "uart_ao_rx_a";
1937 function = "uart_ao_a";
1938 };
1939 };
1940
1941 ao_b_uart_pins:ao_b_uart {
1942 mux {
1943 groups = "uart_ao_tx_b_2",
1944 "uart_ao_rx_b_3";
1945 function = "uart_ao_b";
1946 };
1947 };
1948
1949 ao_i2c_master_pins1:ao_i2c_pins1 {
1950 mux {
1951 groups = "i2c_ao_sck",
1952 "i2c_ao_sda";
1953 function = "i2c_ao";
1954 bias-pull-up;
1955 drive-strength = <2>;
1956 };
1957 };
1958
1959 ao_i2c_master_pins2:ao_i2c_pins2 {
1960 mux {
1961 groups = "i2c_ao_sck_e",
1962 "i2c_ao_sda_e";
1963 function = "i2c_ao";
1964 bias-pull-up;
1965 drive-strength = <2>;
1966 };
1967 };
1968
1969 ao_i2c_slave_pins:ao_i2c_slave_pins {
1970 mux {
1971 groups = "i2c_ao_slave_sck",
1972 "i2c_ao_slave_sda";
1973 function = "i2c_ao_slave";
1974 };
1975 };
1976
1977 pwm_ao_a_pins: pwm_ao_a {
1978 mux {
1979 groups = "pwm_ao_a";
1980 function = "pwm_ao_a";
1981 };
1982 };
1983
1984 pwm_ao_a_hiz_pins: pwm_ao_a_hiz {
1985 mux {
1986 groups = "pwm_ao_a_hiz";
1987 function = "pwm_ao_a";
1988 };
1989 };
1990
1991 pwm_ao_b_pins: pwm_ao_b {
1992 mux {
1993 groups = "pwm_ao_b";
1994 function = "pwm_ao_b";
1995 };
1996 };
1997
1998 pwm_ao_c_pins1: pwm_ao_c_pins1 {
1999 mux {
2000 groups = "pwm_ao_c_4";
2001 function = "pwm_ao_c";
2002 };
2003 };
2004
2005 pwm_ao_c_pins2: pwm_ao_c_pins2 {
2006 mux {
2007 groups = "pwm_ao_c_6";
2008 function = "pwm_ao_c";
2009 };
2010 };
2011
2012 pwm_ao_c_hiz_pins: pwm_ao_c_hiz {
2013 mux {
2014 groups = "pwm_ao_c_hiz_4";
2015 function = "pwm_ao_c";
2016 };
2017 };
2018
2019 pwm_ao_d_pins1: pwm_ao_d_pins1 {
2020 mux {
2021 groups = "pwm_ao_d_5";
2022 function = "pwm_ao_d";
2023 };
2024 };
2025
2026 pwm_ao_d_pins2: pwm_ao_d_pins2 {
2027 mux {
2028 groups = "pwm_ao_d_10";
2029 function = "pwm_ao_d";
2030 };
2031 };
2032
2033 pwm_ao_d_pins3: pwm_ao_d_pins3 {
2034 mux {
2035 groups = "pwm_ao_d_e";
2036 function = "pwm_ao_d";
2037 };
2038 };
2039
2040 aocec_a: ao_ceca {
2041 mux {
2042 groups = "cec_ao_a";
2043 function = "cec_ao";
2044 };
2045 };
2046
2047 aocec_b: ao_cecb {
2048 mux {
2049 groups = "cec_ao_b";
2050 function = "cec_ao";
2051 };
2052 };
2053 pwm_a_e2: pwm_a_e2 {
2054 mux {
2055 groups = "pwm_a_e2";
2056 function = "pwm_a_gpioe";
2057 };
2058 };
2059
2060 jtag_apao_pins:jtag_apao_pin {
2061 mux {
2062 groups = "jtag_a_tdi",
2063 "jtag_a_tdo",
2064 "jtag_a_clk",
2065 "jtag_a_tms";
2066 function = "jtag_a";
2067 };
2068 };
2069};
2070
2071&pinctrl_periphs {
2072 /* sdemmc portC */
2073 emmc_clk_cmd_pins:emmc_clk_cmd_pins {
2074 mux {
2075 groups = "emmc_clk",
2076 "emmc_cmd";
2077 function = "emmc";
2078 input-enable;
2079 bias-pull-up;
2080 drive-strength = <3>;
2081 };
2082 };
2083
2084 emmc_conf_pull_up:emmc_conf_pull_up {
2085 mux {
2086 groups = "emmc_nand_d7",
2087 "emmc_nand_d6",
2088 "emmc_nand_d5",
2089 "emmc_nand_d4",
2090 "emmc_nand_d3",
2091 "emmc_nand_d2",
2092 "emmc_nand_d1",
2093 "emmc_nand_d0",
2094 "emmc_clk",
2095 "emmc_cmd";
2096 function = "emmc";
2097 input-enable;
2098 bias-pull-up;
2099 drive-strength = <3>;
2100 };
2101 };
2102
2103 emmc_conf_pull_done:emmc_conf_pull_done {
2104 mux {
2105 groups = "emmc_nand_ds";
2106 function = "emmc";
2107 input-enable;
2108 bias-pull-down;
2109 drive-strength = <3>;
2110 };
2111 };
2112
2113 /* sdemmc portB */
2114 sd_clk_cmd_pins:sd_clk_cmd_pins {
2115 mux {
2116 groups = "sdcard_cmd_c",
2117 "sdcard_clk_c";
2118 function = "sdcard";
2119 input-enable;
2120 bias-pull-up;
2121 drive-strength = <3>;
2122 };
2123 };
2124
2125 sd_all_pins:sd_all_pins {
2126 mux {
2127 groups = "sdcard_d0_c",
2128 "sdcard_d1_c",
2129 "sdcard_d2_c",
2130 "sdcard_d3_c",
2131 "sdcard_cmd_c",
2132 "sdcard_clk_c";
2133 function = "sdcard";
2134 input-enable;
2135 bias-pull-up;
2136 drive-strength = <3>;
2137 };
2138 };
2139 sd_1bit_pins:sd_1bit_pins {
2140 mux {
2141 groups = "sdcard_d0_c",
2142 "sdcard_cmd_c",
2143 "sdcard_clk_c";
2144 function = "sdcard";
2145 input-enable;
2146 bias-pull-up;
2147 drive-strength = <3>;
2148 };
2149 };
2150
2151 ao_to_sd_uart_pins:ao_to_sd_uart_pins {
2152 mux {
2153 groups = "uart_ao_tx_a_c3",
2154 "uart_ao_rx_a_c2";
2155 function = "uart_ao_a_ee";
2156 bias-pull-up;
2157 input-enable;
2158 };
2159 };
2160 /* sdemmc portA */
2161 sdio_clk_cmd_pins:sdio_clk_cmd_pins {
2162 mux {
2163 groups = "sdio_clk",
2164 "sdio_cmd";
2165 function = "sdio";
2166 input-enable;
2167 bias-pull-up;
2168 drive-strength = <3>;
2169 };
2170 };
2171
2172 sdio_all_pins:sdio_all_pins {
2173 mux {
2174 groups = "sdio_d0",
2175 "sdio_d1",
2176 "sdio_d2",
2177 "sdio_d3",
2178 "sdio_clk",
2179 "sdio_cmd";
2180 function = "sdio";
2181 input-enable;
2182 bias-pull-up;
2183 drive-strength = <3>;
2184 };
2185 };
2186 all_nand_pins: all_nand_pins {
2187 mux {
2188 groups = "emmc_nand_d0",
2189 "emmc_nand_d1",
2190 "emmc_nand_d2",
2191 "emmc_nand_d3",
2192 "emmc_nand_d4",
2193 "emmc_nand_d5",
2194 "emmc_nand_d6",
2195 "emmc_nand_d7",
2196 "nand_ce0",
2197 "nand_ale",
2198 "nand_cle",
2199 "nand_wen_clk",
2200 "nand_ren_wr",
2201 "nand_rb0";
2202 function = "nand";
2203 input-enable;
2204 };
2205 };
2206
2207 nand_cs_pins: nand_cs {
2208 mux {
2209 groups = "nand_ce0";
2210 function = "nand";
2211 };
2212 };
2213
2214 i2c0_master_pins1:i2c0_pins1 {
2215 mux {
2216 groups = "i2c0_sda_c",
2217 "i2c0_sck_c";
2218 function = "i2c0";
2219 bias-pull-up;
2220 drive-strength = <2>;
2221 };
2222 };
2223
2224 i2c0_master_pins2:i2c0_pins2 {
2225 mux {
2226 groups = "i2c0_sda_z0",
2227 "i2c0_sck_z1";
2228 function = "i2c0";
2229 bias-pull-up;
2230 drive-strength = <2>;
2231 };
2232 };
2233
2234 i2c0_master_pins3:i2c0_pins3 {
2235 mux {
2236 groups = "i2c0_sda_z7",
2237 "i2c0_sck_z8";
2238 function = "i2c0";
2239 bias-pull-up;
2240 drive-strength = <2>;
2241 };
2242 };
2243
2244 i2c1_master_pins1:i2c1_pins1 {
2245 mux {
2246 groups = "i2c1_sda_x",
2247 "i2c1_sck_x";
2248 function = "i2c1";
2249 bias-pull-up;
2250 drive-strength = <2>;
2251 };
2252 };
2253
2254 i2c1_master_pins2:i2c1_pins2 {
2255 mux {
2256 groups = "i2c1_sda_h2",
2257 "i2c1_sck_h3";
2258 function = "i2c1";
2259 bias-pull-up;
2260 drive-strength = <2>;
2261 };
2262 };
2263
2264 i2c1_master_pins3:i2c1_pins3 {
2265 mux {
2266 groups = "i2c1_sda_h6",
2267 "i2c1_sck_h7";
2268 function = "i2c1";
2269 bias-pull-up;
2270 drive-strength = <2>;
2271 };
2272 };
2273
2274 i2c2_master_pins1:i2c2_pins1 {
2275 mux {
2276 groups = "i2c2_sda_x",
2277 "i2c2_sck_x";
2278 function = "i2c2";
2279 bias-pull-up;
2280 drive-strength = <2>;
2281 };
2282 };
2283
2284 i2c2_master_pins2:i2c2_pins2 {
2285 mux {
2286 groups = "i2c2_sda_z",
2287 "i2c2_sck_z";
2288 function = "i2c2";
2289 bias-pull-up;
2290 drive-strength = <2>;
2291 };
2292 };
2293
2294 i2c3_master_pins1:i2c3_pins1 {
2295 mux {
2296 groups = "i2c3_sda_h",
2297 "i2c3_sck_h";
2298 function = "i2c3";
2299 bias-pull-up;
2300 drive-strength = <2>;
2301 };
2302 };
2303
2304 i2c3_master_pins2:i2c3_pins2 {
2305 mux {
2306 groups = "i2c3_sda_a",
2307 "i2c3_sck_a";
2308 function = "i2c3";
2309 bias-pull-up;
2310 drive-strength = <2>;
2311 };
2312 };
2313
2314 pwm_a_pins: pwm_a {
2315 mux {
2316 groups = "pwm_a";
2317 function = "pwm_a";
2318 };
2319 };
2320
2321 pwm_b_pins1: pwm_b_pins1 {
2322 mux {
2323 groups = "pwm_b_x7";
2324 function = "pwm_b";
2325 };
2326 };
2327
2328 pwm_b_pins2: pwm_b_pins2 {
2329 mux {
2330 groups = "pwm_b_x19";
2331 function = "pwm_b";
2332 };
2333 };
2334
2335 pwm_b_pins3: pwm_b_pins3 {
2336 mux {
2337 groups = "pwm_b_h";
2338 function = "pwm_b";
2339 };
2340 };
2341
2342 pwm_b_pins4: pwm_b_pins4 {
2343 mux {
2344 groups = "pwm_b_z0";
2345 function = "pwm_b";
2346 };
2347 };
2348
2349 pwm_b_pins5: pwm_b_pins5 {
2350 mux {
2351 groups = "pwm_b_z13";
2352 function = "pwm_b";
2353 };
2354 };
2355
2356 pwm_c_pins1: pwm_c_pins1 {
2357 mux {
2358 groups = "pwm_c_c4";
2359 function = "pwm_c";
2360 };
2361 };
2362
2363 pwm_c_pins2: pwm_c_pins2 {
2364 mux {
2365 groups = "pwm_c_x5";
2366 function = "pwm_c";
2367 };
2368 };
2369
2370 pwm_c_pins3: pwm_c_pins3 {
2371 mux {
2372 groups = "pwm_c_x8";
2373 function = "pwm_c";
2374 };
2375 };
2376
2377 pwm_c_pins4: pwm_c_pins4 {
2378 mux {
2379 groups = "pwm_c_z";
2380 function = "pwm_c";
2381 };
2382 };
2383
2384 pwm_d_pins1: pwm_d_pins1 {
2385 mux {
2386 groups = "pwm_d_x3";
2387 function = "pwm_d";
2388 };
2389 };
2390
2391 pwm_d_pins2: pwm_d_pins2 {
2392 mux {
2393 groups = "pwm_d_x6";
2394 function = "pwm_d";
2395 };
2396 };
2397
2398 pwm_d_pins3: pwm_d_pins3 {
2399 mux {
2400 groups = "pwm_d_z";
2401 function = "pwm_d";
2402 };
2403 };
2404
2405 pwm_d_pins4: pwm_d_pins4 {
2406 mux {
2407 groups = "pwm_d_a4";
2408 function = "pwm_d";
2409 };
2410 };
2411
2412 pwm_e_pins: pwm_e {
2413 mux {
2414 groups = "pwm_e";
2415 function = "pwm_e";
2416 };
2417 };
2418
2419 pwm_f_pins1: pwm_f_pins1 {
2420 mux {
2421 groups = "pwm_f_x";
2422 function = "pwm_f";
2423 };
2424 };
2425
2426 pwm_f_pins2: pwm_f_pins2 {
2427 mux {
2428 groups = "pwm_f_h";
2429 function = "pwm_f";
2430 };
2431 };
2432
2433 pwm_f_pins3: pwm_f_pins3 {
2434 mux {
2435 groups = "pwm_f_z";
2436 function = "pwm_f";
2437 };
2438 };
2439
2440 pwm_f_pins4: pwm_f_pins4 {
2441 mux {
2442 groups = "pwm_f_a11";
2443 function = "pwm_f";
2444 };
2445 };
2446
2447 spicc0_pins_x: spicc0_pins_x {
2448 mux {
2449 groups = "spi0_mosi_x",
2450 "spi0_miso_x",
2451 //"spi0_ss0_x",
2452 "spi0_clk_x";
2453 function = "spi0";
2454 drive-strength = <1>;
2455 };
2456 };
2457
2458 spicc1_pins: spicc1_pins {
2459 mux {
2460 groups = "spi1_mosi",
2461 "spi1_miso",
2462 //"spi1_ss0",
2463 "spi1_clk";
2464 function = "spi1";
2465 drive-strength = <1>;
2466 };
2467 };
2468
2469 a_uart_pins:a_uart {
2470 mux {
2471 groups = "uart_tx_a",
2472 "uart_rx_a",
2473 "uart_cts_a",
2474 "uart_rts_a";
2475 function = "uart_a";
2476 };
2477 };
2478
2479 b_uart_pins:b_uart {
2480 mux {
2481 groups = "uart_tx_b",
2482 "uart_rx_b";
2483 function = "uart_b";
2484 };
2485 };
2486
2487 c_uart_pins:c_uart {
2488 mux {
2489 groups = "uart_tx_c",
2490 "uart_rx_c";
2491 function = "uart_c";
2492 };
2493 };
2494
2495 hdmitx_hpd: hdmitx_hpd {
2496 mux {
2497 groups = "hdmitx_hpd_in";
2498 function = "hdmitx";
2499 bias-disable;
2500 };
2501 };
2502
2503 hdmitx_hpd_gpio: hdmitx_hpd_gpio {
2504 mux {
2505 groups = "GPIOH_1";
2506 function = "gpio_periphs";
2507 bias-disable;
2508 };
2509 };
2510
2511 hdmitx_ddc: hdmitx_ddc {
2512 mux {
2513 groups = "hdmitx_sda",
2514 "hdmitx_sck";
2515 function = "hdmitx";
2516 bias-disable;
2517 };
2518 };
2519
2520 eecec_a: ee_ceca {
2521 mux {
2522 groups = "cec_ao_a_ee";
2523 function = "cec_ao_ee";
2524 };
2525 };
2526
2527 eecec_b: ee_cecb {
2528 mux {
2529 groups = "cec_ao_b_ee";
2530 function = "cec_ao_ee";
2531 };
2532 };
2533
2534 internal_eth_pins: internal_eth_pins {
2535 mux {
2536 groups = "eth_link_led",
2537 "eth_act_led";
2538 function = "eth";
2539 };
2540 };
2541
2542 external_eth_pins: external_eth_pins {
2543 mux {
2544 groups = "eth_mdio",
2545 "eth_mdc",
2546 "eth_rgmii_rx_clk",
2547 "eth_rx_dv",
2548 "eth_rxd0",
2549 "eth_rxd1",
2550 "eth_rxd2_rgmii",
2551 "eth_rxd3_rgmii",
2552 "eth_rgmii_tx_clk",
2553 "eth_txen",
2554 "eth_txd0",
2555 "eth_txd1",
2556 "eth_txd2_rgmii",
2557 "eth_txd3_rgmii";
2558 function = "eth";
2559 drive-strength = <3>;
2560 };
2561 };
2562
2563 irblaster_pins2:irblaster_pins2 {
2564 mux {
2565 groups = "remote_out_h";
2566 function = "remote_out";
2567 };
2568 };
2569
2570 irblaster_pins3:irblaster_pins3 {
2571 mux {
2572 groups = "remote_out_z";
2573 function = "remote_out";
2574 };
2575 };
2576
2577 jtag_apee_pins:jtag_apee_pin {
2578 mux {
2579 groups = "jtag_b_tdi",
2580 "jtag_b_tdo",
2581 "jtag_b_clk",
2582 "jtag_b_tms";
2583 function = "jtag_b";
2584 };
2585 };
2586};
2587
2588&gpu{
2589 system-coherency = <0>;
2590 tbl = <&dvfs285_cfg
2591 &dvfs400_cfg
2592 &dvfs500_cfg
2593 &dvfs666_cfg
2594 &dvfs800_cfg
2595 &dvfs800_cfg>;
2596};
2597
2598&pinctrl_aobus {
2599 sd_to_ao_uart_clr_pins:sd_to_ao_uart_clr_pins {
2600 mux {
2601 groups = "GPIOAO_0",
2602 "GPIOAO_1";
2603 function = "gpio_aobus";
2604 };
2605 };
2606
2607 sd_to_ao_uart_pins:sd_to_ao_uart_pins {
2608 mux {
2609 groups = "uart_ao_tx_a",
2610 "uart_ao_rx_a";
2611 function = "uart_ao_a";
2612 bias-pull-up;
2613 input-enable;
2614 };
2615 };
2616
2617 remote_pins:remote_pin {
2618 mux {
2619 groups = "remote_input_ao";
2620 function = "remote_input_ao";
2621 };
2622 };
2623
2624 irblaster_pins:irblaster_pin {
2625 mux {
2626 groups = "remote_out_ao";
2627 function = "remote_out_ao";
2628 };
2629 };
2630
2631 irblaster_pins1:irblaster_pin1 {
2632 mux {
2633 groups = "remote_out_ao9";
2634 function = "remote_out_ao";
2635 };
2636 };
2637}; /* end of pinctrl_aobus */
2638
generated by cgit at 2024-05-15 19:50:50 (GMT)