summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/amlogic/tl1_t962x2_t309.dts (plain)
blob: 4fa15766a145f13b5f78cea5116846c7bee9547f
1/*
2 * arch/arm64/boot/dts/amlogic/tl1_t962x2_t309.dts
3 *
4 * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17
18/dts-v1/;
19
20#include "mesontl1.dtsi"
21#include "partition_mbox_normal.dtsi"
22#include "mesontl1_t309-panel.dtsi"
23
24/ {
25 model = "Amlogic TL1 T962X2 T309";
26 amlogic-dt-id = "tl1_t962x2_t309";
27 compatible = "amlogic, tl1_t962x2_t309";
28
29 aliases {
30 serial0 = &uart_AO;
31 serial1 = &uart_A;
32 serial2 = &uart_B;
33 serial3 = &uart_C;
34 serial4 = &uart_AO_B;
35 tsensor0 = &p_tsensor;
36 tsensor1 = &d_tsensor;
37 tsensor2 = &s_tsensor;
38 i2c0 = &i2c0;
39 i2c1 = &i2c1;
40 i2c2 = &i2c2;
41 i2c3 = &i2c3;
42 i2c4 = &i2c_AO;
43 };
44
45 memory@00000000 {
46 device_type = "memory";
47 linux,usable-memory = <0x0 0x0 0x0 0x80000000>;
48 };
49
50 reserved-memory {
51 #address-cells = <2>;
52 #size-cells = <2>;
53 ranges;
54 /* global autoconfigured region for contiguous allocations */
55 ramoops@0x07400000 {
56 compatible = "ramoops";
57 reg = <0x0 0x07400000 0x0 0x00100000>;
58 record-size = <0x8000>;
59 console-size = <0x8000>;
60 ftrace-size = <0x0>;
61 pmsg-size = <0x8000>;
62 };
63
64 secmon_reserved: linux,secmon {
65 compatible = "shared-dma-pool";
66 reusable;
67 size = <0x0 0x400000>;
68 alignment = <0x0 0x400000>;
69 alloc-ranges = <0x0 0x05000000 0x0 0x400000>;
70 };
71
72 logo_reserved:linux,meson-fb {
73 compatible = "shared-dma-pool";
74 reusable;
75 size = <0x0 0x800000>;
76 alignment = <0x0 0x400000>;
77 alloc-ranges = <0x0 0x7f800000 0x0 0x800000>;
78 };
79
80 lcd_tcon_reserved:linux,lcd_tcon {
81 compatible = "shared-dma-pool";
82 reusable;
83 size = <0x0 0xc00000>;
84 alignment = <0x0 0x400000>;
85 alloc-ranges = <0x0 0x7ec00000 0x0 0xc00000>;
86 };
87
88 codec_mm_cma:linux,codec_mm_cma {
89 compatible = "shared-dma-pool";
90 reusable;
91 /* ion_codec_mm max can alloc size 80M*/
92 size = <0x0 0x13400000>;
93 alignment = <0x0 0x400000>;
94 linux,contiguous-region;
95 };
96
97 /* codec shared reserved */
98 codec_mm_reserved:linux,codec_mm_reserved {
99 compatible = "amlogic, codec-mm-reserved";
100 size = <0x0 0x0>;
101 alignment = <0x0 0x100000>;
102 //no-map;
103 };
104
105 ion_cma_reserved:linux,ion-dev {
106 compatible = "shared-dma-pool";
107 reusable;
108 size = <0x0 0x8000000>;
109 alignment = <0x0 0x400000>;
110 };
111
112 /* vdin0 CMA pool */
113 //vdin0_cma_reserved:linux,vdin0_cma {
114 // compatible = "shared-dma-pool";
115 // reusable;
116 /* 3840x2160x4x4 ~=128 M */
117 // size = <0x0 0xc400000>;
118 // alignment = <0x0 0x400000>;
119 //};
120
121 /* vdin1 CMA pool */
122 vdin1_cma_reserved:linux,vdin1_cma {
123 compatible = "shared-dma-pool";
124 reusable;
125 /* 1920x1080x2x4 =16 M */
126 size = <0x0 0x1400000>;
127 alignment = <0x0 0x400000>;
128 };
129
130 /*demod_reserved:linux,demod {
131 * compatible = "amlogic, demod-mem";
132 * size = <0x0 0x800000>; //8M //100m 0x6400000
133 * alloc-ranges = <0x0 0x0 0x0 0x30000000>;
134 * //multi-use;
135 * //no-map;
136 *};
137 */
138
139 demod_cma_reserved:linux,demod_cma {
140 compatible = "shared-dma-pool";
141 reusable;
142 /* 8M */
143 size = <0x0 0x0800000>;
144 alignment = <0x0 0x400000>;
145 };
146
147 /*di CMA pool */
148 di_cma_reserved:linux,di_cma {
149 compatible = "shared-dma-pool";
150 reusable;
151 /* buffer_size = 3621952(yuv422 8bit)
152 * | 4736064(yuv422 10bit)
153 * | 4074560(yuv422 10bit full pack mode)
154 * 10x3621952=34.6M(0x23) support 8bit
155 * 10x4736064=45.2M(0x2e) support 12bit
156 * 10x4074560=40M(0x28) support 10bit
157 */
158 size = <0x0 0x02800000>;
159 alignment = <0x0 0x400000>;
160 };
161
162 /* for hdmi rx emp use */
163 hdmirx_emp_cma_reserved:linux,emp_cma {
164 compatible = "shared-dma-pool";
165 /*linux,phandle = <5>;*/
166 reusable;
167 /* 4M for emp to ddr */
168 /* 32M for tmds to ddr */
169 size = <0x0 0x2000000>;
170 alignment = <0x0 0x400000>;
171 };
172
173 /* POST PROCESS MANAGER */
174 ppmgr_reserved:linux,ppmgr {
175 compatible = "amlogic, ppmgr_memory";
176 size = <0x0 0x0>;
177 };
178
179 picdec_cma_reserved:linux,picdec {
180 compatible = "shared-dma-pool";
181 reusable;
182 size = <0x0 0x0>;
183 alignment = <0x0 0x0>;
184 linux,contiguous-region;
185 };
186 }; /* end of reserved-memory */
187
188 codec_mm {
189 compatible = "amlogic, codec, mm";
190 status = "okay";
191 memory-region = <&codec_mm_cma &codec_mm_reserved>;
192 };
193
194 picdec {
195 compatible = "amlogic, picdec";
196 memory-region = <&picdec_cma_reserved>;
197 dev_name = "picdec";
198 status = "okay";
199 };
200
201 ppmgr {
202 compatible = "amlogic, ppmgr";
203 memory-region = <&ppmgr_reserved>;
204 status = "okay";
205 };
206
207 deinterlace {
208 compatible = "amlogic, deinterlace";
209 status = "okay";
210 /* 0:use reserved; 1:use cma; 2:use cma as reserved */
211 flag_cma = <1>;
212 //memory-region = <&di_reserved>;
213 memory-region = <&di_cma_reserved>;
214 interrupts = <0 46 1
215 0 40 1>;
216 interrupt-names = "pre_irq", "post_irq";
217 clocks = <&clkc CLKID_VPU_CLKB_TMP_COMP>,
218 <&clkc CLKID_VPU_CLKB_COMP>;
219 clock-names = "vpu_clkb_tmp_composite",
220 "vpu_clkb_composite";
221 clock-range = <334 667>;
222 /* buffer-size = <3621952>;(yuv422 8bit) */
223 buffer-size = <4074560>;/*yuv422 fullpack*/
224 /* reserve-iomap = "true"; */
225 /* if enable nr10bit, set nr10bit-support to 1 */
226 post-wr-support = <1>;
227 nr10bit-support = <1>;
228 nrds-enable = <1>;
229 pps-enable = <1>;
230 };
231
232 vout {
233 compatible = "amlogic, vout";
234 status = "okay";
235 fr_auto_policy = <0>;
236 };
237
238 /* Audio Related start */
239 pdm_codec:dummy {
240 #sound-dai-cells = <0>;
241 compatible = "amlogic, pdm_dummy_codec";
242 status = "okay";
243 };
244
245 dummy_codec:dummy {
246 #sound-dai-cells = <0>;
247 compatible = "amlogic, aml_dummy_codec";
248 status = "okay";
249 };
250
251 tl1_codec:codec {
252 #sound-dai-cells = <0>;
253 compatible = "amlogic, tl1_acodec";
254 status = "okay";
255 reg = <0x0 0xff632000 0x0 0x1c>;
256 tdmout_index = <0>;
257 tdmin_index = <0>;
258 dat1_ch_sel = <1>;
259 };
260
261 aml_dtv_demod {
262 compatible = "amlogic, ddemod-tl1";
263 dev_name = "aml_dtv_demod";
264 status = "okay";
265
266 pinctrl-names="dtvdemod_agc_pins";
267 pinctrl-0=<&dtvdemod_agc_pins>;
268
269 clocks = <&clkc CLKID_DAC_CLK>;
270 clock-names = "vdac_clk_gate";
271
272 reg = <0x0 0xff650000 0x0 0x4000 /*dtv demod base*/
273 0x0 0xff63c000 0x0 0x2000 /*hiu reg base*/
274 0x0 0xff800000 0x0 0x1000 /*io_aobus_base*/
275 0x0 0xffd01000 0x0 0x1000 /*reset*/
276 >;
277
278 dtv_demod0_mem = <0>; // need move to aml_dtv_demod ?
279 spectrum = <1>;
280 cma_flag = <1>;
281 cma_mem_size = <8>;
282 memory-region = <&demod_cma_reserved>;//<&demod_reserved>;
283 };
284
285 auge_sound {
286 compatible = "amlogic, tl1-sound-card";
287 aml-audio-card,name = "AML-AUGESOUND";
288
289 avout_mute-gpios = <&gpio GPIODV_3 GPIO_ACTIVE_HIGH>;
290
291 aml-audio-card,dai-link@0 {
292 format = "i2s";
293 mclk-fs = <256>;
294 //continuous-clock;
295 //bitclock-inversion;
296 //frame-inversion;
297 /* master mode */
298 bitclock-master = <&tdma>;
299 frame-master = <&tdma>;
300 /* slave mode */
301 /*
302 * bitclock-master = <&tdmacodec>;
303 * frame-master = <&tdmacodec>;
304 */
305 /* suffix-name, sync with android audio hal used for */
306 suffix-name = "alsaPORT-i2s";
307 tdmacpu: cpu {
308 sound-dai = <&tdma>;
309 dai-tdm-slot-tx-mask =
310 <1 1>;
311 dai-tdm-slot-rx-mask =
312 <1 1>;
313 dai-tdm-slot-num = <2>;
314 dai-tdm-slot-width = <32>;
315 system-clock-frequency = <12288000>;
316 };
317 tdmacodec: codec {
318 //sound-dai = <&dummy_codec>;
319 sound-dai = <&ad82584f &tl1_codec>;
320 };
321 };
322
323 aml-audio-card,dai-link@1 {
324 status = "disabled";
325
326 format = "i2s";
327 mclk-fs = <256>;
328 //continuous-clock;
329 //bitclock-inversion;
330 //frame-inversion;
331 /* master mode */
332 bitclock-master = <&tdmb>;
333 frame-master = <&tdmb>;
334 /* slave mode */
335 //bitclock-master = <&tdmbcodec>;
336 //frame-master = <&tdmbcodec>;
337 /* suffix-name, sync with android audio hal used for */
338 suffix-name = "alsaPORT-pcm";
339 cpu {
340 sound-dai = <&tdmb>;
341 dai-tdm-slot-tx-mask = <1 1>;
342 dai-tdm-slot-rx-mask = <1 1>;
343 dai-tdm-slot-num = <2>;
344 /*
345 * dai-tdm-slot-tx-mask =
346 * <1 1 1 1 1 1 1 1>;
347 * dai-tdm-slot-rx-mask =
348 * <1 1 1 1 1 1 1 1>;
349 * dai-tdm-slot-num = <8>;
350 */
351 dai-tdm-slot-width = <32>;
352 system-clock-frequency = <12288000>;
353 };
354 tdmbcodec: codec {
355 sound-dai = <&dummy_codec>;
356 };
357 };
358
359 aml-audio-card,dai-link@2 {
360 status = "disabled";
361
362 format = "i2s";
363 mclk-fs = <256>;
364 //continuous-clock;
365 //bitclock-inversion;
366 //frame-inversion;
367 /* master mode */
368 bitclock-master = <&tdmc>;
369 frame-master = <&tdmc>;
370 /* slave mode */
371 //bitclock-master = <&tdmccodec>;
372 //frame-master = <&tdmccodec>;
373 /* suffix-name, sync with android audio hal used for */
374 //suffix-name = "alsaPORT-tdm";
375 cpu {
376 sound-dai = <&tdmc>;
377 dai-tdm-slot-tx-mask = <1 1>;
378 dai-tdm-slot-rx-mask = <1 1>;
379 dai-tdm-slot-num = <2>;
380 dai-tdm-slot-width = <32>;
381 system-clock-frequency = <12288000>;
382 };
383 tdmccodec: codec {
384 sound-dai = <&dummy_codec>;
385 };
386 };
387
388 aml-audio-card,dai-link@3 {
389 mclk-fs = <64>;
390 /* suffix-name, sync with android audio hal used for */
391 suffix-name = "alsaPORT-pdm";
392 cpu {
393 sound-dai = <&pdm>;
394 };
395 codec {
396 sound-dai = <&pdm_codec>;
397 };
398 };
399
400 aml-audio-card,dai-link@4 {
401 mclk-fs = <128>;
402 /* suffix-name, sync with android audio hal used for */
403 suffix-name = "alsaPORT-spdif";
404 cpu {
405 sound-dai = <&spdifa>;
406 system-clock-frequency = <6144000>;
407 };
408 codec {
409 sound-dai = <&dummy_codec>;
410 };
411 };
412
413 aml-audio-card,dai-link@5 {
414 mclk-fs = <128>;
415 cpu {
416 sound-dai = <&spdifb>;
417 system-clock-frequency = <6144000>;
418 };
419 codec {
420 sound-dai = <&dummy_codec>;
421 };
422 };
423
424 aml-audio-card,dai-link@6 {
425 mclk-fs = <256>;
426 suffix-name = "alsaPORT-tv";
427 cpu {
428 sound-dai = <&extn>;
429 system-clock-frequency = <12288000>;
430 };
431 codec {
432 sound-dai = <&dummy_codec>;
433 };
434 };
435
436 };
437 /* Audio Related end */
438
439 dvb {
440 compatible = "amlogic, dvb";
441 status = "okay";
442 fe0_mode = "internal";
443 fe0_tuner = <&tuner>;
444
445 /*"parallel","serial","disable"*/
446 ts2 = "parallel";
447 ts2_control = <0>;
448 ts2_invert = <0>;
449 interrupts = <0 23 1
450 0 5 1
451 0 53 1
452 0 19 1
453 0 25 1
454 0 17 1>;
455 interrupt-names = "demux0_irq",
456 "demux1_irq",
457 "demux2_irq",
458 "dvr0_irq",
459 "dvr1_irq",
460 "dvr2_irq";
461 clocks = <&clkc CLKID_DEMUX
462 &clkc CLKID_ASYNC_FIFO
463 &clkc CLKID_AHB_ARB0
464/* &clkc CLKID_DOS_PARSER>;*/
465 &clkc CLKID_U_PARSER>;
466 clock-names = "demux", "asyncfifo", "ahbarb0", "uparsertop";
467 };
468
469 tvafe_avin_detect {
470 compatible = "amlogic, tl1_tvafe_avin_detect";
471 status = "okay";
472 device_mask = <1>;/*bit0:ch1;bit1:ch2*/
473 interrupts = <0 12 1>,
474 <0 13 1>;
475 };
476
477 amlvecm {
478 compatible = "amlogic, vecm";
479 dev_name = "aml_vecm";
480 status = "okay";
481 gamma_en = <1>;/*1:enabel ;0:disable*/
482 wb_en = <1>;/*1:enabel ;0:disable*/
483 cm_en = <1>;/*1:enabel ;0:disable*/
484 wb_sel = <1>;/*1:mtx ;0:gainoff*/
485 vlock_en = <1>;/*1:enable;0:disable*/
486 vlock_mode = <0x4>;
487 /* vlock work mode:
488 *bit0:auto ENC
489 *bit1:auto PLL
490 *bit2:manual PLL
491 *bit3:manual ENC
492 *bit4:manual soft ENC
493 *bit5:manual MIX PLL ENC
494 */
495 vlock_pll_m_limit = <1>;
496 vlock_line_limit = <3>;
497 };
498
499 vdin@0 {
500 compatible = "amlogic, vdin";
501 /*memory-region = <&vdin0_cma_reserved>;*/
502 status = "okay";
503 /*bit0:(1:share with codec_mm;0:cma alone)
504 *bit8:(1:alloc in discontinus way;0:alone in continuous way)
505 */
506 flag_cma = <0x101>;
507 /*MByte, if 10bit disable: 64M(YUV422),
508 *if 10bit enable: 64*1.5 = 96M(YUV422)
509 *if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M
510 *if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M
511 *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M
512 *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M
513 */
514 cma_size = <190>;
515 interrupts = <0 83 1>;
516 rdma-irq = <2>;
517 clocks = <&clkc CLKID_FCLK_DIV5>,
518 <&clkc CLKID_VDIN_MEAS_COMP>;
519 clock-names = "fclk_div5", "cts_vdin_meas_clk";
520 vdin_id = <0>;
521 /*vdin write mem color depth support:
522 * bit0:support 8bit
523 * bit1:support 9bit
524 * bit2:support 10bit
525 * bit3:support 12bit
526 * bit4:support yuv422 10bit full pack mode (from txl new add)
527 * bit8:use 8bit at 4k_50/60hz_10bit
528 * bit9:use 10bit at 4k_50/60hz_10bit
529 */
530 tv_bit_mode = <0x215>;
531 /* afbce_bit_mode: (amlogic frame buff compression encoder)
532 * bit 0~3:
533 * 0 -- normal mode, not use afbce
534 * 1 -- use afbce non-mmu mode
535 * 2 -- use afbce mmu mode
536 * bit 4:
537 * 0 -- afbce compression-lossy disable
538 * 1 -- afbce compression-lossy enable
539 */
540 afbce_bit_mode = <0>;
541 };
542
543 vdin@1 {
544 compatible = "amlogic, vdin";
545 memory-region = <&vdin1_cma_reserved>;
546 status = "okay";
547 /*bit0:(1:share with codec_mm;0:cma alone)
548 *bit8:(1:alloc in discontinus way;0:alone in continuous way)
549 */
550 flag_cma = <0>;
551 interrupts = <0 85 1>;
552 rdma-irq = <4>;
553 clocks = <&clkc CLKID_FCLK_DIV5>,
554 <&clkc CLKID_VDIN_MEAS_COMP>;
555 clock-names = "fclk_div5", "cts_vdin_meas_clk";
556 vdin_id = <1>;
557 /*vdin write mem color depth support:
558 *bit0:support 8bit
559 *bit1:support 9bit
560 *bit2:support 10bit
561 *bit3:support 12bit
562 */
563 tv_bit_mode = <0x15>;
564 };
565
566 tvafe {
567 compatible = "amlogic, tvafe-tl1";
568 /*memory-region = <&tvafe_cma_reserved>;*/
569 status = "okay";
570 flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/
571 cma_size = <5>;/*MByte*/
572 reg = <0x0 0xff654000 0x0 0x2000>;/*tvafe reg base*/
573 reserve-iomap = "true";
574 tvafe_id = <0>;
575 //pinctrl-names = "default";
576 /*!!particular sequence, no more and no less!!!*/
577 tvafe_pin_mux = <
578 3 /* TVAFE_CVBS_IN2, CVBS_IN0 = 0 */
579 1 /* TVAFE_CVBS_IN0, CVBS_IN1 */
580 2 /* TVAFE_CVBS_IN1, CVBS_IN2 */
581 4 /* TVAFE_CVBS_IN3, CVBS_IN3 */
582 >;
583 clocks = <&clkc CLKID_DAC_CLK>;
584 clock-names = "vdac_clk_gate";
585 };
586
587 vbi {
588 compatible = "amlogic, vbi";
589 status = "okay";
590 interrupts = <0 83 1>;
591 };
592
593 cvbsout {
594 compatible = "amlogic, cvbsout-tl1";
595 status = "disabled";
596 clocks = <&clkc CLKID_VCLK2_ENCI
597 &clkc CLKID_VCLK2_VENCI0
598 &clkc CLKID_VCLK2_VENCI1
599 &clkc CLKID_DAC_CLK>;
600 clock-names = "venci_top_gate",
601 "venci_0_gate",
602 "venci_1_gate",
603 "vdac_clk_gate";
604 /* clk path */
605 /* 0:vid_pll vid2_clk */
606 /* 1:gp0_pll vid2_clk */
607 /* 2:vid_pll vid1_clk */
608 /* 3:gp0_pll vid1_clk */
609 clk_path = <0>;
610
611 /* performance: reg_address, reg_value */
612 /* tl1 */
613 performance = <0x1bf0 0x9
614 0x1b56 0x333
615 0x1b12 0x8080
616 0x1b05 0xfd
617 0x1c59 0xf850
618 0xffff 0x0>; /* ending flag */
619 performance_sarft = <0x1bf0 0x9
620 0x1b56 0x333
621 0x1b12 0x0
622 0x1b05 0x9
623 0x1c59 0xfc48
624 0xffff 0x0>; /* ending flag */
625 performance_revB_telecom = <0x1bf0 0x9
626 0x1b56 0x546
627 0x1b12 0x8080
628 0x1b05 0x9
629 0x1c59 0xf850
630 0xffff 0x0>; /* ending flag */
631 };
632
633 /* for external keypad */
634 adc_keypad {
635 compatible = "amlogic, adc_keypad";
636 status = "okay";
637 key_name = "power","up","down","enter","left","right","home";
638 key_num = <7>;
639 io-channels = <&saradc SARADC_CH2>,<&saradc SARADC_CH3>;
640 io-channel-names = "key-chan-2", "key-chan-3";
641 key_chan = <SARADC_CH2 SARADC_CH2 SARADC_CH2 SARADC_CH2
642 SARADC_CH2 SARADC_CH3 SARADC_CH3>;
643 key_code = <116 103 108 28 105 106 102>;
644 key_val = <0 143 266 389 512 143 266>; //val=voltage/1800mV*1023
645 key_tolerance = <40 40 40 40 40 40 40>;
646};
647
648 unifykey {
649 compatible = "amlogic, unifykey";
650 status = "okay";
651
652 unifykey-num = <21>;
653 unifykey-index-0 = <&keysn_0>;
654 unifykey-index-1 = <&keysn_1>;
655 unifykey-index-2 = <&keysn_2>;
656 unifykey-index-3 = <&keysn_3>;
657 unifykey-index-4 = <&keysn_4>;
658 unifykey-index-5 = <&keysn_5>;
659 unifykey-index-6 = <&keysn_6>;
660 unifykey-index-7 = <&keysn_7>;
661 unifykey-index-8 = <&keysn_8>;
662 unifykey-index-9 = <&keysn_9>;
663 unifykey-index-10= <&keysn_10>;
664 unifykey-index-11 = <&keysn_11>;
665 unifykey-index-12 = <&keysn_12>;
666 unifykey-index-13 = <&keysn_13>;
667 unifykey-index-14 = <&keysn_14>;
668 unifykey-index-15 = <&keysn_15>;
669 unifykey-index-16 = <&keysn_16>;
670 unifykey-index-17 = <&keysn_17>;
671 unifykey-index-18 = <&keysn_18>;
672 unifykey-index-19 = <&keysn_19>;
673 unifykey-index-20 = <&keysn_20>;
674
675 keysn_0: key_0{
676 key-name = "usid";
677 key-device = "normal";
678 key-permit = "read","write","del";
679 };
680 keysn_1:key_1{
681 key-name = "mac";
682 key-device = "normal";
683 key-permit = "read","write","del";
684 };
685 keysn_2:key_2{
686 key-name = "hdcp";
687 key-device = "secure";
688 key-type = "sha1";
689 key-permit = "read","write","del";
690 };
691 keysn_3:key_3{
692 key-name = "secure_boot_set";
693 key-device = "efuse";
694 key-permit = "write";
695 };
696 keysn_4:key_4{
697 key-name = "mac_bt";
698 key-device = "normal";
699 key-permit = "read","write","del";
700 key-type = "mac";
701 };
702 keysn_5:key_5{
703 key-name = "mac_wifi";
704 key-device = "normal";
705 key-permit = "read","write","del";
706 key-type = "mac";
707 };
708 keysn_6:key_6{
709 key-name = "hdcp2_tx";
710 key-device = "normal";
711 key-permit = "read","write","del";
712 };
713 keysn_7:key_7{
714 key-name = "hdcp2_rx";
715 key-device = "normal";
716 key-permit = "read","write","del";
717 };
718 keysn_8:key_8{
719 key-name = "widevinekeybox";
720 key-device = "secure";
721 key-type = "sha1";
722 key-permit = "read","write","del";
723 };
724 keysn_9:key_9{
725 key-name = "deviceid";
726 key-device = "normal";
727 key-permit = "read","write","del";
728 };
729 keysn_10:key_10{
730 key-name = "hdcp22_fw_private";
731 key-device = "secure";
732 key-permit = "read","write","del";
733 };
734 keysn_11:key_11{
735 key-name = "hdcp22_rx_private";
736 key-device = "secure";
737 key-permit = "read","write","del";
738 };
739 keysn_12:key_12{
740 key-name = "hdcp22_rx_fw";
741 key-device = "normal";
742 key-permit = "read","write","del";
743 };
744 keysn_13:key_13{
745 key-name = "hdcp14_rx";
746 key-device = "normal";
747 key-type = "sha1";
748 key-permit = "read","write","del";
749 };
750 keysn_14:key_14{
751 key-name = "prpubkeybox";// PlayReady
752 key-device = "secure";
753 key-permit = "read","write","del";
754 };
755 keysn_15:key_15{
756 key-name = "prprivkeybox";// PlayReady
757 key-device = "secure";
758 key-permit = "read","write","del";
759 };
760 keysn_16:key_16{
761 key-name = "lcd";
762 key-device = "normal";
763 key-permit = "read","write","del";
764 };
765 keysn_17:key_17{
766 key-name = "lcd_extern";
767 key-device = "normal";
768 key-permit = "read","write","del";
769 };
770 keysn_18:key_18{
771 key-name = "backlight";
772 key-device = "normal";
773 key-permit = "read","write","del";
774 };
775 keysn_19:key_19{
776 key-name = "lcd_tcon";
777 key-device = "normal";
778 key-permit = "read","write","del";
779 };
780 keysn_20:key_20{
781 key-name = "attestationkeybox";// attestation key
782 key-device = "secure";
783 key-permit = "read","write","del";
784 };
785 }; /* End unifykey */
786
787 hdmirx {
788 compatible = "amlogic, hdmirx_tl1";
789 #address-cells=<1>;
790 #size-cells=<1>;
791 memory-region = <&hdmirx_emp_cma_reserved>;
792 status = "okay";
793 pinctrl-names = "default";
794 pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
795 &hdmirx_c_mux>;
796 repeat = <0>;
797 interrupts = <0 41 1>;
798 clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
799 <&clkc CLKID_HDMIRX_CFG_COMP>,
800 <&clkc CLKID_HDMIRX_ACR_COMP>,
801 <&clkc CLKID_HDMIRX_METER_COMP>,
802 <&clkc CLKID_HDMIRX_AXI_COMP>,
803 <&xtal>,
804 <&clkc CLKID_FCLK_DIV5>,
805 <&clkc CLKID_FCLK_DIV7>,
806 <&clkc CLKID_HDCP22_SKP_COMP>,
807 <&clkc CLKID_HDCP22_ESM_COMP>;
808 // <&clkc CLK_AUD_PLL2FS>,
809 // <&clkc CLK_AUD_PLL4FS>,
810 // <&clkc CLK_AUD_OUT>;
811 clock-names = "hdmirx_modet_clk",
812 "hdmirx_cfg_clk",
813 "hdmirx_acr_ref_clk",
814 "cts_hdmirx_meter_clk",
815 "cts_hdmi_axi_clk",
816 "xtal",
817 "fclk_div5",
818 "fclk_div7",
819 "hdcp_rx22_skp",
820 "hdcp_rx22_esm";
821 // "hdmirx_aud_pll2fs",
822 // "hdmirx_aud_pll4f",
823 // "clk_aud_out";
824 hdmirx_id = <0>;
825 en_4k_2_2k = <0>;
826 hpd_low_cec_off = <1>;
827 /* bit4: enable feature, bit3~0: port number */
828 disable_port = <0x0>;
829 /* MAP_ADDR_MODULE_CBUS */
830 /* MAP_ADDR_MODULE_HIU */
831 /* MAP_ADDR_MODULE_HDMIRX_CAPB3 */
832 /* MAP_ADDR_MODULE_SEC_AHB */
833 /* MAP_ADDR_MODULE_SEC_AHB2 */
834 /* MAP_ADDR_MODULE_APB4 */
835 /* MAP_ADDR_MODULE_TOP */
836 reg = < 0x0 0x0 0x0 0x0
837 0x0 0xff63C000 0x0 0x2000
838 0x0 0xffe0d000 0x0 0x2000
839 0x0 0x0 0x0 0x0
840 0x0 0x0 0x0 0x0
841 0x0 0x0 0x0 0x0
842 0x0 0xff610000 0x0 0xa000>;
843 };
844
845 aocec: aocec {
846 compatible = "amlogic, aocec-tl1";
847 /*device_name = "aocec";*/
848 status = "okay";
849 vendor_name = "Amlogic"; /* Max Chars: 8 */
850 /* Refer to the following URL at:
851 * http://standards.ieee.org/develop/regauth/oui/oui.txt
852 */
853 vendor_id = <0x000000>;
854 product_desc = "TL1"; /* Max Chars: 16 */
855 cec_osd_string = "AML_TV"; /* Max Chars: 14 */
856 port_num = <3>;
857 ee_cec;
858 arc_port_mask = <0x2>;
859 interrupts = <0 205 1
860 0 199 1>;
861 interrupt-names = "hdmi_aocecb","hdmi_aocec";
862 pinctrl-names = "default","hdmitx_aocecb","cec_pin_sleep";
863 pinctrl-0=<&aoceca_mux>;
864 pinctrl-1=<&aocecb_mux>;
865 pinctrl-2=<&aoceca_mux>;
866 reg = <0x0 0xFF80023c 0x0 0x4
867 0x0 0xFF800000 0x0 0x400>;
868 reg-names = "ao_exit","ao";
869 };
870
871 p_tsensor: p_tsensor@ff634800 {
872 compatible = "amlogic, r1p1-tsensor";
873 status = "okay";
874 reg = <0x0 0xff634800 0x0 0x50>,
875 <0x0 0xff800268 0x0 0x4>;
876 cal_type = <0x1>;
877 cal_a = <324>;
878 cal_b = <424>;
879 cal_c = <3159>;
880 cal_d = <9411>;
881 rtemp = <115000>;
882 interrupts = <0 35 0>;
883 clocks = <&clkc CLKID_TS_CLK_COMP>; /* CLKID_TS_COMP>;*/
884 clock-names = "ts_comp";
885 #thermal-sensor-cells = <1>;
886 };
887
888 d_tsensor: d_tsensor@ff634c00 {
889 compatible = "amlogic, r1p1-tsensor";
890 status = "okay";
891 reg = <0x0 0xff634c00 0x0 0x50>,
892 <0x0 0xff800230 0x0 0x4>;
893 cal_type = <0x1>;
894 cal_a = <324>;
895 cal_b = <424>;
896 cal_c = <3159>;
897 cal_d = <9411>;
898 rtemp = <115000>;
899 interrupts = <0 36 0>;
900 clocks = <&clkc CLKID_TS_CLK_COMP>; /* CLKID_TS_COMP>;*/
901 clock-names = "ts_comp";
902 #thermal-sensor-cells = <1>;
903 };
904
905 s_tsensor: s_tsensor@ff635000 {
906 compatible = "amlogic, r1p1-tsensor";
907 status = "okay";
908 reg = <0x0 0xff635000 0x0 0x50>,
909 <0x0 0xff80026c 0x0 0x4>;
910 cal_type = <0x1>;
911 cal_a = <324>;
912 cal_b = <424>;
913 cal_c = <3159>;
914 cal_d = <9411>;
915 rtemp = <115000>;
916 interrupts = <0 38 0>;
917 clocks = <&clkc CLKID_TS_CLK_COMP>; /* CLKID_TS_COMP>;*/
918 clock-names = "ts_comp";
919 #thermal-sensor-cells = <1>;
920 };
921
922 meson_cooldev: meson-cooldev@0 {
923 status = "okay";
924 compatible = "amlogic, meson-cooldev";
925 cooling_devices {
926 cpufreq_cool_cluster0 {
927 min_state = <1000000>;
928 dyn_coeff = <140>;
929 gpu_pp = <2>;
930 cluster_id = <0>;
931 node_name = "cpufreq_cool0";
932 device_type = "cpufreq";
933 };
934 cpucore_cool_cluster0 {
935 min_state = <1>;
936 dyn_coeff = <0>;
937 gpu_pp = <2>;
938 cluster_id = <0>;
939 node_name = "cpucore_cool0";
940 device_type = "cpucore";
941 };
942 gpufreq_cool {
943 min_state = <400>;
944 dyn_coeff = <140>;
945 gpu_pp = <2>;
946 cluster_id = <0>;
947 node_name = "gpufreq_cool0";
948 device_type = "gpufreq";
949 };
950 gpucore_cool {
951 min_state = <1>;
952 dyn_coeff = <0>;
953 gpu_pp = <2>;
954 cluster_id = <0>;
955 node_name = "gpucore_cool0";
956 device_type = "gpucore";
957 };
958 };
959 cpufreq_cool0:cpufreq_cool0 {
960 #cooling-cells = <2>; /* min followed by max */
961 };
962 cpucore_cool0:cpucore_cool0 {
963 #cooling-cells = <2>; /* min followed by max */
964 };
965 gpufreq_cool0:gpufreq_cool0 {
966 #cooling-cells = <2>; /* min followed by max */
967 };
968 gpucore_cool0:gpucore_cool0 {
969 #cooling-cells = <2>; /* min followed by max */
970 };
971 };/*meson cooling devices end*/
972
973 thermal-zones {
974 pll_thermal: pll_thermal {
975 polling-delay = <1000>;
976 polling-delay-passive = <100>;
977 sustainable-power = <1322>;
978 thermal-sensors = <&p_tsensor 0>;
979 trips {
980 pswitch_on: trip-point@0 {
981 temperature = <60000>;
982 hysteresis = <5000>;
983 type = "passive";
984 };
985 pcontrol: trip-point@1 {
986 temperature = <75000>;
987 hysteresis = <5000>;
988 type = "passive";
989 };
990 phot: trip-point@2 {
991 temperature = <85000>;
992 hysteresis = <5000>;
993 type = "hot";
994 };
995 pcritical: trip-point@3 {
996 temperature = <110000>;
997 hysteresis = <1000>;
998 type = "critical";
999 };
1000 };
1001 cooling-maps {
1002 cpufreq_cooling_map {
1003 trip = <&pcontrol>;
1004 cooling-device = <&cpufreq_cool0 0 11>;
1005 contribution = <1024>;
1006 };
1007 cpucore_cooling_map {
1008 trip = <&pcontrol>;
1009 cooling-device = <&cpucore_cool0 0 4>;
1010 contribution = <1024>;
1011 };
1012 gpufreq_cooling_map {
1013 trip = <&pcontrol>;
1014 cooling-device = <&gpufreq_cool0 0 4>;
1015 contribution = <1024>;
1016 };
1017 };
1018 };
1019 ddr_thermal: ddr_thermal {
1020 polling-delay = <2000>;
1021 polling-delay-passive = <1000>;
1022 sustainable-power = <1322>;
1023 thermal-sensors = <&d_tsensor 1>;
1024 trips {
1025 dswitch_on: trip-point@0 {
1026 temperature = <60000>;
1027 hysteresis = <5000>;
1028 type = "passive";
1029 };
1030 dcontrol: trip-point@1 {
1031 temperature = <75000>;
1032 hysteresis = <5000>;
1033 type = "passive";
1034 };
1035 dhot: trip-point@2 {
1036 temperature = <85000>;
1037 hysteresis = <5000>;
1038 type = "hot";
1039 };
1040 dcritical: trip-point@3 {
1041 temperature = <110000>;
1042 hysteresis = <1000>;
1043 type = "critical";
1044 };
1045 };
1046 };
1047 sar_thermal: sar_thermal {
1048 polling-delay = <2000>;
1049 polling-delay-passive = <1000>;
1050 sustainable-power = <1322>;
1051 thermal-sensors = <&s_tsensor 2>;
1052 trips {
1053 sswitch_on: trip-point@0 {
1054 temperature = <60000>;
1055 hysteresis = <5000>;
1056 type = "passive";
1057 };
1058 scontrol: trip-point@1 {
1059 temperature = <75000>;
1060 hysteresis = <5000>;
1061 type = "passive";
1062 };
1063 shot: trip-point@2 {
1064 temperature = <85000>;
1065 hysteresis = <5000>;
1066 type = "hot";
1067 };
1068 scritical: trip-point@3 {
1069 temperature = <110000>;
1070 hysteresis = <1000>;
1071 type = "critical";
1072 };
1073 };
1074 };
1075 }; /*thermal zone end*/
1076
1077 /*DCDC for MP8756GD*/
1078 cpu_opp_table0: cpu_opp_table0 {
1079 compatible = "operating-points-v2";
1080 opp-shared;
1081
1082 opp00 {
1083 opp-hz = /bits/ 64 <100000000>;
1084 opp-microvolt = <699000>;
1085 };
1086 opp01 {
1087 opp-hz = /bits/ 64 <250000000>;
1088 opp-microvolt = <699000>;
1089 };
1090 opp02 {
1091 opp-hz = /bits/ 64 <500000000>;
1092 opp-microvolt = <709000>;
1093 };
1094 opp03 {
1095 opp-hz = /bits/ 64 <667000000>;
1096 opp-microvolt = <719000>;
1097 };
1098 opp04 {
1099 opp-hz = /bits/ 64 <1000000000>;
1100 opp-microvolt = <729000>;
1101 };
1102 opp05 {
1103 opp-hz = /bits/ 64 <1200000000>;
1104 opp-microvolt = <749000>;
1105 };
1106 opp06 {
1107 opp-hz = /bits/ 64 <1404000000>;
1108 opp-microvolt = <769000>;
1109 };
1110 opp07 {
1111 opp-hz = /bits/ 64 <1500000000>;
1112 opp-microvolt = <779000>;
1113 };
1114 opp08 {
1115 opp-hz = /bits/ 64 <1608000000>;
1116 opp-microvolt = <789000>;
1117 };
1118 opp09 {
1119 opp-hz = /bits/ 64 <1704000000>;
1120 opp-microvolt = <829000>;
1121 };
1122 opp10 {
1123 opp-hz = /bits/ 64 <1800000000>;
1124 opp-microvolt = <879000>;
1125 };
1126 opp11 {
1127 opp-hz = /bits/ 64 <1908000000>;
1128 opp-microvolt = <929000>;
1129 };
1130 };
1131
1132 cpufreq-meson {
1133 compatible = "amlogic, cpufreq-meson";
1134 pinctrl-names = "default";
1135 pinctrl-0 = <&pwm_ao_d_pins3>;
1136 status = "okay";
1137 };
1138
1139 tuner: tuner {
1140 compatible = "amlogic, tuner";
1141 status = "okay";
1142 tuner_name = "r842_tuner";
1143 tuner_i2c_adap = <&i2c0>;
1144 tuner_i2c_addr = <0xf6>;
1145 tuner_xtal = <1>; /* 0: 16MHz, 1: 24MHz */
1146 tuner_xtal_mode = <0>;
1147 /* NO_SHARE_XTAL(0)
1148 * MASTER_TO_SLAVE_XTAL_IN(1)
1149 * MASTER_TO_SLAVE_XTAL_OUT(2)
1150 * SLAVE_XTAL_OUT(3)
1151 */
1152 tuner_xtal_cap = <38>; /* when tuner_xtal_mode = 3, set 25 */
1153 };
1154
1155 atv-demod {
1156 compatible = "amlogic, atv-demod";
1157 status = "okay";
1158 tuner = <&tuner>;
1159 btsc_sap_mode = <1>;
1160 pinctrl-names="atvdemod_agc_pins";
1161 pinctrl-0=<&atvdemod_agc_pins>;
1162 reg = <0x0 0xff656000 0x0 0x2000 /* demod reg */
1163 0x0 0xff63c000 0x0 0x2000 /* hiu reg */
1164 0x0 0xff634000 0x0 0x2000 /* periphs reg */
1165 0x0 0xff64a000 0x0 0x2000>; /* audio reg */
1166 reg_23cf = <0x88188832>;
1167 /*default:0x88188832;r840 on haier:0x48188832*/
1168 };
1169
1170 bt-dev{
1171 compatible = "amlogic, bt-dev";
1172 status = "okay";
1173 gpio_reset = <&gpio GPIOC_13 GPIO_ACTIVE_HIGH>;
1174 };
1175
1176 wifi{
1177 compatible = "amlogic, aml_wifi";
1178 status = "okay";
1179 interrupt_pin = <&gpio GPIOC_12 GPIO_ACTIVE_HIGH>;
1180 irq_trigger_type = "GPIO_IRQ_LOW";
1181 dhd_static_buf; //dhd_static_buf support
1182 power_on_pin = <&gpio GPIOC_11 GPIO_ACTIVE_HIGH>;
1183 pinctrl-names = "default";
1184 pinctrl-0 = <&pwm_b_pins1>;
1185 pwm_config = <&wifi_pwm_conf>;
1186 };
1187
1188 wifi_pwm_conf:wifi_pwm_conf{
1189 pwm_channel1_conf {
1190 pwms = <&pwm_ab MESON_PWM_1 30541 0>;
1191 duty-cycle = <15270>;
1192 times = <8>;
1193 };
1194 pwm_channel2_conf {
1195 pwms = <&pwm_ab MESON_PWM_3 30500 0>;
1196 duty-cycle = <15250>;
1197 times = <12>;
1198 };
1199 };
1200
1201 sd_emmc_b: sdio@ffe05000 {
1202 status = "okay";
1203 compatible = "amlogic, meson-mmc-tl1";
1204 reg = <0x0 0xffe05000 0x0 0x800>;
1205 interrupts = <0 190 4>;
1206
1207 pinctrl-names = "sdio_all_pins",
1208 "sdio_clk_cmd_pins";
1209 pinctrl-0 = <&sdio_all_pins>;
1210 pinctrl-1 = <&sdio_clk_cmd_pins>;
1211
1212 clocks = <&clkc CLKID_SD_EMMC_B>,
1213 <&clkc CLKID_SD_EMMC_B_P0_COMP>,
1214 <&clkc CLKID_FCLK_DIV2>,
1215 <&clkc CLKID_FCLK_DIV5>,
1216 <&xtal>;
1217 clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal";
1218
1219 bus-width = <4>;
1220 cap-sd-highspeed;
1221 cap-mmc-highspeed;
1222 max-frequency = <100000000>;
1223 disable-wp;
1224 sdio {
1225 pinname = "sdio";
1226 ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */
1227 caps = "MMC_CAP_4_BIT_DATA",
1228 "MMC_CAP_MMC_HIGHSPEED",
1229 "MMC_CAP_SD_HIGHSPEED",
1230 "MMC_CAP_NONREMOVABLE", /**ptm debug */
1231 "MMC_CAP_UHS_SDR12",
1232 "MMC_CAP_UHS_SDR25",
1233 "MMC_CAP_UHS_SDR50",
1234 "MMC_CAP_UHS_SDR104",
1235 "MMC_PM_KEEP_POWER",
1236 "MMC_CAP_SDIO_IRQ";
1237 f_min = <400000>;
1238 f_max = <200000000>;
1239 max_req_size = <0x20000>; /**128KB*/
1240 card_type = <3>;
1241 /* 3:sdio device(ie:sdio-wifi),
1242 * 4:SD combo (IO+mem) card
1243 */
1244 };
1245 };
1246}; /* end of / */
1247
1248&i2c0 {
1249 status = "okay";
1250 clock-frequency = <300000>;
1251 pinctrl-names="default";
1252 pinctrl-0=<&i2c0_dv_pins>;
1253};
1254
1255&audiobus {
1256 tdma:tdm@0 {
1257 compatible = "amlogic, tl1-snd-tdma";
1258 #sound-dai-cells = <0>;
1259
1260 dai-tdm-lane-slot-mask-in = <1 0>;
1261 dai-tdm-lane-slot-mask-out = <1 1 1 1>;
1262 dai-tdm-clk-sel = <0>;
1263
1264 clocks = <&clkaudio CLKID_AUDIO_MCLK_A
1265 &clkc CLKID_MPLL0
1266 &clkc CLKID_MPLL1
1267 &clkaudio CLKID_AUDIO_SPDIFOUT_A>;
1268 clock-names = "mclk", "clk_srcpll",
1269 "samesource_srcpll", "samesource_clk";
1270
1271 pinctrl-names = "tdm_pins";
1272 pinctrl-0 = <&tdma_mclk &tdmout_a>;
1273
1274 /*
1275 * 0: tdmout_a;
1276 * 1: tdmout_b;
1277 * 2: tdmout_c;
1278 * 3: spdifout;
1279 * 4: spdifout_b;
1280 */
1281 samesource_sel = <3>;
1282
1283 /* In for ACODEC_ADC */
1284 acodec_adc = <1>;
1285
1286 status = "okay";
1287 };
1288
1289 tdmb:tdm@1 {
1290 compatible = "amlogic, tl1-snd-tdmb";
1291 #sound-dai-cells = <0>;
1292
1293 dai-tdm-lane-slot-mask-in = <1 0 0 0>;
1294 dai-tdm-lane-slot-mask-out = <1 0 0 0>;
1295 dai-tdm-clk-sel = <1>;
1296
1297 clocks = <&clkaudio CLKID_AUDIO_MCLK_B
1298 &clkc CLKID_MPLL1>;
1299 clock-names = "mclk", "clk_srcpll";
1300
1301 status = "okay";
1302 };
1303
1304 tdmc:tdm@2 {
1305 compatible = "amlogic, tl1-snd-tdmc";
1306 #sound-dai-cells = <0>;
1307
1308 dai-tdm-lane-slot-mask-in = <1 0 0 0>;
1309 dai-tdm-lane-slot-mask-out = <1 0 0 0>;
1310 dai-tdm-clk-sel = <2>;
1311
1312 clocks = <&clkaudio CLKID_AUDIO_MCLK_C
1313 &clkc CLKID_MPLL2>;
1314 clock-names = "mclk", "clk_srcpll";
1315
1316 pinctrl-names = "tdm_pins";
1317 pinctrl-0 = <&tdmout_c &tdmin_c>;
1318
1319 status = "okay";
1320 };
1321
1322 spdifa:spdif@0 {
1323 compatible = "amlogic, tl1-snd-spdif-a";
1324 #sound-dai-cells = <0>;
1325
1326 clocks = <&clkc CLKID_MPLL1
1327 &clkc CLKID_FCLK_DIV4
1328 &clkaudio CLKID_AUDIO_GATE_SPDIFIN
1329 &clkaudio CLKID_AUDIO_GATE_SPDIFOUT_A
1330 &clkaudio CLKID_AUDIO_SPDIFIN
1331 &clkaudio CLKID_AUDIO_SPDIFOUT_A>;
1332 clock-names = "sysclk", "fixed_clk", "gate_spdifin",
1333 "gate_spdifout", "clk_spdifin", "clk_spdifout";
1334
1335 interrupts =
1336 <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
1337 interrupt-names = "irq_spdifin";
1338
1339 pinctrl-names = "spdif_pins";
1340 pinctrl-0 = <&spdifout_a>;
1341
1342 /*
1343 * whether do asrc for pcm and resample a or b
1344 * if raw data, asrc is disabled automatically
1345 * 0: "Disable",
1346 * 1: "Enable:32K",
1347 * 2: "Enable:44K",
1348 * 3: "Enable:48K",
1349 * 4: "Enable:88K",
1350 * 5: "Enable:96K",
1351 * 6: "Enable:176K",
1352 * 7: "Enable:192K",
1353 */
1354 asrc_id = <0>;
1355 auto_asrc = <3>;
1356
1357 status = "okay";
1358 };
1359
1360 spdifb:spdif@1 {
1361 compatible = "amlogic, tl1-snd-spdif-b";
1362 #sound-dai-cells = <0>;
1363
1364 clocks = <&clkc CLKID_MPLL0 /*CLKID_HIFI_PLL*/
1365 &clkaudio CLKID_AUDIO_GATE_SPDIFOUT_B
1366 &clkaudio CLKID_AUDIO_SPDIFOUT_B>;
1367 clock-names = "sysclk",
1368 "gate_spdifout", "clk_spdifout";
1369
1370 status = "okay";
1371 };
1372
1373 pdm:pdm {
1374 compatible = "amlogic, tl1-snd-pdm";
1375 #sound-dai-cells = <0>;
1376
1377 clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
1378 &clkc CLKID_FCLK_DIV3
1379 &clkc CLKID_MPLL3
1380 &clkaudio CLKID_AUDIO_PDMIN0
1381 &clkaudio CLKID_AUDIO_PDMIN1>;
1382 clock-names = "gate",
1383 "sysclk_srcpll",
1384 "dclk_srcpll",
1385 "pdm_dclk",
1386 "pdm_sysclk";
1387
1388 pinctrl-names = "pdm_pins";
1389 pinctrl-0 = <&pdmin>;
1390
1391 /* mode 0~4, defalut:1 */
1392 filter_mode = <1>;
1393
1394 status = "okay";
1395 };
1396
1397 extn:extn {
1398 compatible = "amlogic, snd-extn";
1399 #sound-dai-cells = <0>;
1400
1401 interrupts =
1402 <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
1403 interrupt-names = "irq_frhdmirx";
1404
1405 status = "okay";
1406 };
1407
1408 aed:effect {
1409 compatible = "amlogic, snd-effect-v2";
1410 #sound-dai-cells = <0>;
1411
1412 clocks = <&clkaudio CLKID_AUDIO_GATE_EQDRC
1413 &clkc CLKID_FCLK_DIV5
1414 &clkaudio CLKID_AUDIO_EQDRC>;
1415 clock-names = "gate", "srcpll", "eqdrc";
1416
1417 /*
1418 * 0:tdmout_a
1419 * 1:tdmout_b
1420 * 2:tdmout_c
1421 * 3:spdifout
1422 * 4:spdifout_b
1423 */
1424 eqdrc_module = <0>;
1425 /* max 0xf, each bit for one lane, usually one lane */
1426 lane_mask = <0x1>;
1427 /* max 0xff, each bit for one channel */
1428 channel_mask = <0xff>;
1429
1430 status = "okay";
1431 };
1432
1433 asrca: resample@0 {
1434 compatible = "amlogic, tl1-resample-a";
1435 clocks = <&clkc CLKID_MPLL0
1436 &clkaudio CLKID_AUDIO_MCLK_A
1437 &clkaudio CLKID_AUDIO_RESAMPLE_A>;
1438 clock-names = "resample_pll", "resample_src", "resample_clk";
1439 /*same with toddr_src
1440 * TDMIN_A, 0
1441 * TDMIN_B, 1
1442 * TDMIN_C, 2
1443 * SPDIFIN, 3
1444 * PDMIN, 4
1445 * NONE,
1446 * TDMIN_LB, 6
1447 * LOOPBACK, 7
1448 */
1449 resample_module = <3>;
1450
1451 status = "okay";
1452 };
1453
1454 asrcb: resample@1 {
1455 compatible = "amlogic, tl1-resample-b";
1456
1457 clocks = <&clkc CLKID_MPLL3
1458 &clkaudio CLKID_AUDIO_MCLK_F
1459 &clkaudio CLKID_AUDIO_RESAMPLE_B>;
1460 clock-names = "resample_pll", "resample_src", "resample_clk";
1461
1462 /*same with toddr_src
1463 * TDMIN_A, 0
1464 * TDMIN_B, 1
1465 * TDMIN_C, 2
1466 * SPDIFIN, 3
1467 * PDMIN, 4
1468 * NONE,
1469 * TDMIN_LB, 6
1470 * LOOPBACK, 7
1471 */
1472 resample_module = <3>;
1473
1474 status = "disabled";
1475 };
1476
1477}; /* end of audiobus */
1478
1479&pinctrl_periphs {
1480 /* audio pin mux */
1481
1482 tdma_mclk: tdma_mclk {
1483 mux { /* GPIOZ_0 */
1484 groups = "mclk0_z";
1485 function = "mclk0";
1486 };
1487 };
1488
1489 tdmout_a: tdmout_a {
1490 mux { /* GPIOZ_1, GPIOZ_2, GPIOZ_3 */
1491 groups = "tdma_sclk_z",
1492 "tdma_fs_z",
1493 "tdma_dout0_z";
1494 function = "tdma_out";
1495 };
1496 };
1497
1498 tdmin_a: tdmin_a {
1499 mux { /* GPIOZ_9 */
1500 groups = "tdma_din2_z";
1501 function = "tdma_in";
1502 };
1503 };
1504
1505 tdmout_c: tdmout_c {
1506 mux { /* GPIODV_7, GPIODV_8, GPIODV_9 */
1507 groups = "tdmc_sclk",
1508 "tdmc_fs",
1509 "tdmc_dout0";
1510 function = "tdmc_out";
1511 };
1512 };
1513
1514 tdmin_c: tdmin_c {
1515 mux { /* GPIODV_10 */
1516 groups = "tdmc_din1";
1517 function = "tdmc_in";
1518 };
1519 };
1520
1521 spdifin_a: spdifin_a {
1522 mux { /* GPIODV_5 */
1523 groups = "spdif_in";
1524 function = "spdif_in";
1525 };
1526 };
1527
1528 spdifout_a: spdifout_a {
1529 mux { /* GPIODV_4 */
1530 groups = "spdif_out_dv4";
1531 function = "spdif_out";
1532 };
1533 };
1534
1535 pdmin: pdmin {
1536 mux { /* GPIOZ_7, GPIOZ_8, pdm_din2_z4 */
1537 groups = "pdm_dclk_z",
1538 "pdm_din0_z",
1539 "pdm_din2_z4";
1540 function = "pdm";
1541 };
1542 };
1543
1544 /*backlight*/
1545 bl_pwm_vs_on_pins:bl_pwm_vs_on_pin {
1546 mux {
1547 groups = "pwm_vs_z5";
1548 function = "pwm_vs";
1549 };
1550 };
1551 bl_pwm_off_pins:bl_pwm_off_pin {
1552 mux {
1553 groups = "GPIOZ_5";
1554 function = "gpio_periphs";
1555 output-low;
1556 };
1557 };
1558 bl_pwm_combo_0_vs_on_pins:bl_pwm_combo_0_vs_on_pin {
1559 mux {
1560 groups = "pwm_vs_z5";
1561 function = "pwm_vs";
1562 };
1563 };
1564 bl_pwm_combo_1_vs_on_pins:bl_pwm_combo_1_vs_on_pin {
1565 mux {
1566 groups = "pwm_vs_z6";
1567 function = "pwm_vs";
1568 };
1569 };
1570 bl_pwm_combo_off_pins:bl_pwm_combo_off_pin {
1571 mux {
1572 groups = "GPIOZ_5",
1573 "GPIOZ_6";
1574 function = "gpio_periphs";
1575 output-low;
1576 };
1577 };
1578
1579}; /* end of pinctrl_periphs */
1580
1581&audio_data{
1582 status = "okay";
1583};
1584
1585&i2c2 {
1586 status = "okay";
1587 pinctrl-names="default";
1588 pinctrl-0=<&i2c2_z_pins>;
1589 clock-frequency = <400000>;
1590
1591 tas5805: tas5805@36 {
1592 compatible = "ti,tas5805";
1593 #sound-dai-cells = <0>;
1594 codec_name = "tas5805";
1595 reg = <0x0 0x2d>;
1596 status = "disable";
1597 };
1598
1599 ad82584f: ad82584f@62 {
1600 compatible = "ESMT, ad82584f";
1601 #sound-dai-cells = <0>;
1602 reg = <0x0 0x31>;
1603 status = "okay";
1604 reset_pin = <&gpio_ao GPIOAO_6 0>;
1605 };
1606
1607};
1608
1609&sd_emmc_c {
1610 status = "okay";
1611 emmc {
1612 caps = "MMC_CAP_8_BIT_DATA",
1613 "MMC_CAP_MMC_HIGHSPEED",
1614 "MMC_CAP_SD_HIGHSPEED",
1615 "MMC_CAP_NONREMOVABLE",
1616 "MMC_CAP_1_8V_DDR",
1617 "MMC_CAP_HW_RESET",
1618 "MMC_CAP_ERASE",
1619 "MMC_CAP_CMD23";
1620 caps2 = "MMC_CAP2_HS200";
1621 /* "MMC_CAP2_HS400";*/
1622 f_min = <400000>;
1623 f_max = <200000000>;
1624 };
1625};
1626
1627
1628
1629&spifc {
1630 status = "disabled";
1631 spi-nor@0 {
1632 cs_gpios = <&gpio BOOT_13 GPIO_ACTIVE_HIGH>;
1633 };
1634};
1635
1636&slc_nand {
1637 status = "disabled";
1638 plat-names = "bootloader", "nandnormal";
1639 plat-num = <2>;
1640 plat-part-0 = <&bootloader>;
1641 plat-part-1 = <&nandnormal>;
1642 bootloader: bootloader{
1643 enable_pad = "ce0";
1644 busy_pad = "rb0";
1645 timming_mode = "mode5";
1646 bch_mode = "bch8_1k";
1647 t_rea = <20>;
1648 t_rhoh = <15>;
1649 chip_num = <1>;
1650 part_num = <0>;
1651 rb_detect = <1>;
1652 };
1653 nandnormal: nandnormal{
1654 enable_pad = "ce0";
1655 busy_pad = "rb0";
1656 timming_mode = "mode5";
1657 bch_mode = "bch8_1k";
1658 plane_mode = "twoplane";
1659 t_rea = <20>;
1660 t_rhoh = <15>;
1661 chip_num = <2>;
1662 part_num = <3>;
1663 partition = <&nand_partitions>;
1664 rb_detect = <1>;
1665 };
1666 nand_partitions:nand_partition{
1667 /*
1668 * if bl_mode is 1, tpl size was generate by
1669 * fip_copies * fip_size which
1670 * will not skip bad when calculating
1671 * the partition size;
1672 *
1673 * if bl_mode is 0,
1674 * tpl partition must be comment out.
1675 */
1676 tpl{
1677 offset=<0x0 0x0>;
1678 size=<0x0 0x0>;
1679 };
1680 logo{
1681 offset=<0x0 0x0>;
1682 size=<0x0 0x200000>;
1683 };
1684 recovery{
1685 offset=<0x0 0x0>;
1686 size=<0x0 0x1000000>;
1687 };
1688 boot{
1689 offset=<0x0 0x0>;
1690 size=<0x0 0x1000000>;
1691 };
1692 system{
1693 offset=<0x0 0x0>;
1694 size=<0x0 0x4000000>;
1695 };
1696 data{
1697 offset=<0xffffffff 0xffffffff>;
1698 size=<0x0 0x0>;
1699 };
1700 };
1701};
1702
1703&ethmac {
1704 status = "okay";
1705 pinctrl-names = "internal_eth_pins";
1706 pinctrl-0 = <&internal_eth_pins>;
1707 mc_val = <0x4be04>;
1708
1709 internal_phy=<1>;
1710};
1711
1712&uart_A {
1713 status = "okay";
1714};
1715
1716&dwc3 {
1717 status = "okay";
1718};
1719
1720&usb2_phy_v2 {
1721 status = "okay";
1722 portnum = <3>;
1723};
1724
1725&usb3_phy_v2 {
1726 status = "okay";
1727 portnum = <0>;
1728 otg = <0>;
1729};
1730
1731&dwc2_a {
1732 status = "okay";
1733 /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/
1734 controller-type = <1>;
1735};
1736
1737&spicc0 {
1738 status = "okay";
1739 pinctrl-names = "default";
1740 pinctrl-0 = <&spicc0_pins_h>;
1741 cs-gpios = <&gpio GPIOH_20 0>;
1742};
1743
1744&meson_fb {
1745 status = "okay";
1746 display_size_default = <1920 1080 1920 2160 32>;
1747 mem_size = <0x00800000 0x1980000 0x100000 0x800000>;
1748 logo_addr = "0x7f800000";
1749 mem_alloc = <0>;
1750 pxp_mode = <0>; /** 0:normal mode 1:pxp mode */
1751};
1752
1753&pwm_AO_cd {
1754 status = "okay";
1755};
1756
1757&saradc {
1758 status = "okay";
1759};
1760
1761&i2c1 {
1762 status = "okay";
1763 clock-frequency = <300000>;
1764 pinctrl-names="default";
1765 pinctrl-0=<&i2c1_h_pins>;
1766
1767 lcd_extern_i2c0: lcd_extern_i2c@0 {
1768 compatible = "lcd_ext, i2c";
1769 dev_name = "i2c_T5800Q";
1770 reg = <0x0 0x1c>;
1771 status = "okay";
1772 };
1773
1774 lcd_extern_i2c1: lcd_extern_i2c@1 {
1775 compatible = "lcd_ext, i2c";
1776 dev_name = "i2c_ANX6862";
1777 reg = <0x0 0x20>;
1778 status = "okay";
1779 };
1780
1781 lcd_extern_i2c2: lcd_extern_i2c@2 {
1782 compatible = "lcd_ext, i2c";
1783 dev_name = "i2c_ANX7911";
1784 reg = <0x0 0x74>;
1785 status = "okay";
1786 };
1787};
1788
1789&pwm_ab {
1790 status = "okay";
1791};
1792
1793&pwm_cd {
1794 status = "okay";
1795};
1796
1797&efuse {
1798 status = "okay";
1799};
1800
generated by cgit at 2024-05-17 09:31:22 (GMT)