summaryrefslogtreecommitdiff
path: root/drivers/amlogic/cec/hdmi_ao_cec.h (plain)
blob: ef1182acd10d9bc0681a3319eb4b2031c032e708
1/*
2 * drivers/amlogic/cec/hdmi_ao_cec.h
3 *
4 * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17
18#ifndef __AO_CEC_H__
19#define __AO_CEC_H__
20
21#define CEC_DRIVER_VERSION "2018/02/05\n"
22
23#define CEC_FRAME_DELAY msecs_to_jiffies(400)
24#define CEC_DEV_NAME "cec"
25
26#define CEC_EARLY_SUSPEND (1 << 0)
27#define CEC_DEEP_SUSPEND (1 << 1)
28
29#define HR_DELAY(n) (ktime_set(0, n * 1000 * 1000))
30
31#define CEC_FUNC_MASK 0
32#define ONE_TOUCH_PLAY_MASK 1
33#define ONE_TOUCH_STANDBY_MASK 2
34#define AUTO_POWER_ON_MASK 3
35
36
37#define AO_BASE 0xc8100000
38
39#define AO_GPIO_I ((0x0A << 2))
40
41#define AO_CEC_GEN_CNTL ((0x40 << 2))
42#define AO_CEC_RW_REG ((0x41 << 2))
43#define AO_CEC_INTR_MASKN ((0x42 << 2))
44#define AO_CEC_INTR_CLR ((0x43 << 2))
45#define AO_CEC_INTR_STAT ((0x44 << 2))
46
47#define AO_RTI_PWR_CNTL_REG0 ((0x04 << 2))
48#define AO_CRT_CLK_CNTL1 ((0x1a << 2))
49#define AO_RTC_ALT_CLK_CNTL0 ((0x25 << 2))
50#define AO_RTC_ALT_CLK_CNTL1 ((0x26 << 2))
51
52/* for TXLX, same as AO_RTC_ALT_CLK_CNTLx */
53#define AO_CEC_CLK_CNTL_REG0 ((0x1d << 2))
54#define AO_CEC_CLK_CNTL_REG1 ((0x1e << 2))
55
56#define AO_RTI_STATUS_REG1 ((0x01 << 2))
57#define AO_DEBUG_REG0 ((0x28 << 2))
58#define AO_DEBUG_REG1 ((0x29 << 2))
59#define AO_DEBUG_REG2 ((0x2a << 2))
60#define AO_DEBUG_REG3 ((0x2b << 2))
61
62/*
63 * AOCEC_B
64 */
65#define AO_CECB_CLK_CNTL_REG0 ((0xa0 << 2))
66#define AO_CECB_CLK_CNTL_REG1 ((0xa1 << 2))
67#define AO_CECB_GEN_CNTL ((0xa2 << 2))
68#define AO_CECB_RW_REG ((0xa3 << 2))
69#define AO_CECB_INTR_MASKN ((0xa4 << 2))
70#define AO_CECB_INTR_CLR ((0xa5 << 2))
71#define AO_CECB_INTR_STAT ((0xa6 << 2))
72
73/* read/write */
74#define CEC_TX_MSG_0_HEADER 0x00
75#define CEC_TX_MSG_1_OPCODE 0x01
76#define CEC_TX_MSG_2_OP1 0x02
77#define CEC_TX_MSG_3_OP2 0x03
78#define CEC_TX_MSG_4_OP3 0x04
79#define CEC_TX_MSG_5_OP4 0x05
80#define CEC_TX_MSG_6_OP5 0x06
81#define CEC_TX_MSG_7_OP6 0x07
82#define CEC_TX_MSG_8_OP7 0x08
83#define CEC_TX_MSG_9_OP8 0x09
84#define CEC_TX_MSG_A_OP9 0x0A
85#define CEC_TX_MSG_B_OP10 0x0B
86#define CEC_TX_MSG_C_OP11 0x0C
87#define CEC_TX_MSG_D_OP12 0x0D
88#define CEC_TX_MSG_E_OP13 0x0E
89#define CEC_TX_MSG_F_OP14 0x0F
90
91/* read/write */
92#define CEC_TX_MSG_LENGTH 0x10
93#define CEC_TX_MSG_CMD 0x11
94#define CEC_TX_WRITE_BUF 0x12
95#define CEC_TX_CLEAR_BUF 0x13
96#define CEC_RX_MSG_CMD 0x14
97#define CEC_RX_CLEAR_BUF 0x15
98#define CEC_LOGICAL_ADDR0 0x16
99#define CEC_LOGICAL_ADDR1 0x17
100#define CEC_LOGICAL_ADDR2 0x18
101#define CEC_LOGICAL_ADDR3 0x19
102#define CEC_LOGICAL_ADDR4 0x1A
103#define CEC_CLOCK_DIV_H 0x1B
104#define CEC_CLOCK_DIV_L 0x1C
105
106/* The following registers are for fine tuning CEC bit timing parameters.
107 * They are only valid in AO CEC, NOT valid in HDMITX CEC.
108 * The AO CEC's timing parameters are already set default to work with
109 * 32768Hz clock, so hopefully SW never need to program these registers.
110 * The timing registers are made programmable just in case.
111 */
112#define AO_CEC_QUIESCENT_25MS_BIT7_0 0x20
113#define AO_CEC_QUIESCENT_25MS_BIT11_8 0x21
114#define AO_CEC_STARTBITMINL2H_3MS5_BIT7_0 0x22
115#define AO_CEC_STARTBITMINL2H_3MS5_BIT8 0x23
116#define AO_CEC_STARTBITMAXL2H_3MS9_BIT7_0 0x24
117#define AO_CEC_STARTBITMAXL2H_3MS9_BIT8 0x25
118#define AO_CEC_STARTBITMINH_0MS6_BIT7_0 0x26
119#define AO_CEC_STARTBITMINH_0MS6_BIT8 0x27
120#define AO_CEC_STARTBITMAXH_1MS0_BIT7_0 0x28
121#define AO_CEC_STARTBITMAXH_1MS0_BIT8 0x29
122#define AO_CEC_STARTBITMINTOTAL_4MS3_BIT7_0 0x2A
123#define AO_CEC_STARTBITMINTOTAL_4MS3_BIT9_8 0x2B
124#define AO_CEC_STARTBITMAXTOTAL_4MS7_BIT7_0 0x2C
125#define AO_CEC_STARTBITMAXTOTAL_4MS7_BIT9_8 0x2D
126#define AO_CEC_LOGIC1MINL2H_0MS4_BIT7_0 0x2E
127#define AO_CEC_LOGIC1MINL2H_0MS4_BIT8 0x2F
128#define AO_CEC_LOGIC1MAXL2H_0MS8_BIT7_0 0x30
129#define AO_CEC_LOGIC1MAXL2H_0MS8_BIT8 0x31
130#define AO_CEC_LOGIC0MINL2H_1MS3_BIT7_0 0x32
131#define AO_CEC_LOGIC0MINL2H_1MS3_BIT8 0x33
132#define AO_CEC_LOGIC0MAXL2H_1MS7_BIT7_0 0x34
133#define AO_CEC_LOGIC0MAXL2H_1MS7_BIT8 0x35
134#define AO_CEC_LOGICMINTOTAL_2MS05_BIT7_0 0x36
135#define AO_CEC_LOGICMINTOTAL_2MS05_BIT9_8 0x37
136#define AO_CEC_LOGICMAXHIGH_2MS8_BIT7_0 0x38
137#define AO_CEC_LOGICMAXHIGH_2MS8_BIT8 0x39
138#define AO_CEC_LOGICERRLOW_3MS4_BIT7_0 0x3A
139#define AO_CEC_LOGICERRLOW_3MS4_BIT8 0x3B
140#define AO_CEC_NOMSMPPOINT_1MS05 0x3C
141#define AO_CEC_DELCNTR_LOGICERR 0x3E
142#define AO_CEC_TXTIME_17MS_BIT7_0 0x40
143#define AO_CEC_TXTIME_17MS_BIT10_8 0x41
144#define AO_CEC_TXTIME_2BIT_BIT7_0 0x42
145#define AO_CEC_TXTIME_2BIT_BIT10_8 0x43
146#define AO_CEC_TXTIME_4BIT_BIT7_0 0x44
147#define AO_CEC_TXTIME_4BIT_BIT10_8 0x45
148#define AO_CEC_STARTBITNOML2H_3MS7_BIT7_0 0x46
149#define AO_CEC_STARTBITNOML2H_3MS7_BIT8 0x47
150#define AO_CEC_STARTBITNOMH_0MS8_BIT7_0 0x48
151#define AO_CEC_STARTBITNOMH_0MS8_BIT8 0x49
152#define AO_CEC_LOGIC1NOML2H_0MS6_BIT7_0 0x4A
153#define AO_CEC_LOGIC1NOML2H_0MS6_BIT8 0x4B
154#define AO_CEC_LOGIC0NOML2H_1MS5_BIT7_0 0x4C
155#define AO_CEC_LOGIC0NOML2H_1MS5_BIT8 0x4D
156#define AO_CEC_LOGIC1NOMH_1MS8_BIT7_0 0x4E
157#define AO_CEC_LOGIC1NOMH_1MS8_BIT8 0x4F
158#define AO_CEC_LOGIC0NOMH_0MS9_BIT7_0 0x50
159#define AO_CEC_LOGIC0NOMH_0MS9_BIT8 0x51
160#define AO_CEC_LOGICERRLOW_3MS6_BIT7_0 0x52
161#define AO_CEC_LOGICERRLOW_3MS6_BIT8 0x53
162#define AO_CEC_CHKCONTENTION_0MS1 0x54
163#define AO_CEC_PREPARENXTBIT_0MS05_BIT7_0 0x56
164#define AO_CEC_PREPARENXTBIT_0MS05_BIT8 0x57
165#define AO_CEC_NOMSMPACKPOINT_0MS45 0x58
166#define AO_CEC_ACK0NOML2H_1MS5_BIT7_0 0x5A
167#define AO_CEC_ACK0NOML2H_1MS5_BIT8 0x5B
168
169#define AO_CEC_BUGFIX_DISABLE_0 0x60
170#define AO_CEC_BUGFIX_DISABLE_1 0x61
171
172/* read only */
173#define CEC_RX_MSG_0_HEADER 0x80
174#define CEC_RX_MSG_1_OPCODE 0x81
175#define CEC_RX_MSG_2_OP1 0x82
176#define CEC_RX_MSG_3_OP2 0x83
177#define CEC_RX_MSG_4_OP3 0x84
178#define CEC_RX_MSG_5_OP4 0x85
179#define CEC_RX_MSG_6_OP5 0x86
180#define CEC_RX_MSG_7_OP6 0x87
181#define CEC_RX_MSG_8_OP7 0x88
182#define CEC_RX_MSG_9_OP8 0x89
183#define CEC_RX_MSG_A_OP9 0x8A
184#define CEC_RX_MSG_B_OP10 0x8B
185#define CEC_RX_MSG_C_OP11 0x8C
186#define CEC_RX_MSG_D_OP12 0x8D
187#define CEC_RX_MSG_E_OP13 0x8E
188#define CEC_RX_MSG_F_OP14 0x8F
189
190/* read only */
191#define CEC_RX_MSG_LENGTH 0x90
192#define CEC_RX_MSG_STATUS 0x91
193#define CEC_RX_NUM_MSG 0x92
194#define CEC_TX_MSG_STATUS 0x93
195#define CEC_TX_NUM_MSG 0x94
196
197/* tx_msg_cmd definition */
198#define TX_NO_OP 0 /* No transaction */
199#define TX_REQ_CURRENT 1 /* Transmit earliest message in buffer */
200#define TX_ABORT 2 /* Abort transmitting earliest message */
201/* Overwrite earliest message in buffer and transmit next message */
202#define TX_REQ_NEXT 3
203
204/* tx_msg_status definition */
205#define TX_IDLE 0 /* No transaction */
206#define TX_BUSY 1 /* Transmitter is busy */
207/* Message has been successfully transmitted */
208#define TX_DONE 2
209#define TX_ERROR 3 /* Message has been transmitted with error */
210
211/* rx_msg_cmd */
212#define RX_NO_OP 0 /* No transaction */
213#define RX_ACK_CURRENT 1 /* Read earliest message in buffer */
214#define RX_DISABLE 2 /* Disable receiving latest message */
215/* Clear earliest message from buffer and read next message */
216#define RX_ACK_NEXT 3
217
218/* rx_msg_status */
219#define RX_IDLE 0 /* No transaction */
220#define RX_BUSY 1 /* Receiver is busy */
221#define RX_DONE 2 /* Message has been received successfully */
222#define RX_ERROR 3 /* Message has been received with error */
223
224#define TOP_HPD_PWR5V 0x002
225#define TOP_ARCTX_CNTL 0x010
226#define TOP_CLK_CNTL 0x001
227#define TOP_EDID_GEN_CNTL 0x004
228#define TOP_EDID_ADDR_CEC 0x005
229
230/** Register address: audio clock interrupt clear enable */
231#define DWC_AUD_CEC_IEN_CLR (0xF90UL)
232/** Register address: audio clock interrupt set enable */
233#define DWC_AUD_CEC_IEN_SET (0xF94UL)
234/** Register address: audio clock interrupt status */
235#define DWC_AUD_CEC_ISTS (0xF98UL)
236/** Register address: audio clock interrupt enable */
237#define DWC_AUD_CEC_IEN (0xF9CUL)
238/** Register address: audio clock interrupt clear status */
239#define DWC_AUD_CEC_ICLR (0xFA0UL)
240/** Register address: audio clock interrupt set status */
241#define DWC_AUD_CEC_ISET (0xFA4UL)
242/** Register address: DMI disable interface */
243#define DWC_DMI_DISABLE_IF (0xFF4UL)
244
245/*---- registers for EE CEC ----*/
246#define DWC_CEC_CTRL 0x1F00
247#define DWC_CEC_STAT 0x1F04
248#define DWC_CEC_MASK 0x1F08
249#define DWC_CEC_POLARITY 0x1F0C
250#define DWC_CEC_INT 0x1F10
251#define DWC_CEC_ADDR_L 0x1F14
252#define DWC_CEC_ADDR_H 0x1F18
253#define DWC_CEC_TX_CNT 0x1F1C
254#define DWC_CEC_RX_CNT 0x1F20
255#define DWC_CEC_TX_DATA0 0x1F40
256#define DWC_CEC_TX_DATA1 0x1F44
257#define DWC_CEC_TX_DATA2 0x1F48
258#define DWC_CEC_TX_DATA3 0x1F4C
259#define DWC_CEC_TX_DATA4 0x1F50
260#define DWC_CEC_TX_DATA5 0x1F54
261#define DWC_CEC_TX_DATA6 0x1F58
262#define DWC_CEC_TX_DATA7 0x1F5C
263#define DWC_CEC_TX_DATA8 0x1F60
264#define DWC_CEC_TX_DATA9 0x1F64
265#define DWC_CEC_TX_DATA10 0x1F68
266#define DWC_CEC_TX_DATA11 0x1F6C
267#define DWC_CEC_TX_DATA12 0x1F70
268#define DWC_CEC_TX_DATA13 0x1F74
269#define DWC_CEC_TX_DATA14 0x1F78
270#define DWC_CEC_TX_DATA15 0x1F7C
271#define DWC_CEC_RX_DATA0 0x1F80
272#define DWC_CEC_RX_DATA1 0x1F84
273#define DWC_CEC_RX_DATA2 0x1F88
274#define DWC_CEC_RX_DATA3 0x1F8C
275#define DWC_CEC_RX_DATA4 0x1F90
276#define DWC_CEC_RX_DATA5 0x1F94
277#define DWC_CEC_RX_DATA6 0x1F98
278#define DWC_CEC_RX_DATA7 0x1F9C
279#define DWC_CEC_RX_DATA8 0x1FA0
280#define DWC_CEC_RX_DATA9 0x1FA4
281#define DWC_CEC_RX_DATA10 0x1FA8
282#define DWC_CEC_RX_DATA11 0x1FAC
283#define DWC_CEC_RX_DATA12 0x1FB0
284#define DWC_CEC_RX_DATA13 0x1FB4
285#define DWC_CEC_RX_DATA14 0x1FB8
286#define DWC_CEC_RX_DATA15 0x1FBC
287#define DWC_CEC_LOCK 0x1FC0
288#define DWC_CEC_WKUPCTRL 0x1FC4
289
290/* FOR AO_CECB */
291#define AO_CECB_CTRL_ADDR 0x00
292#define AO_CECB_INTR_MASK_ADDR 0x02
293#define AO_CECB_LADD_LOW_ADDR 0x05
294#define AO_CECB_LADD_HIGH_ADDR 0x06
295#define AO_CECB_TX_CNT_ADDR 0x07
296#define AO_CECB_RX_CNT_ADDR 0x08
297#define AO_CECB_TX_DATA00_ADDR 0x10
298#define AO_CECB_TX_DATA01_ADDR 0x11
299#define AO_CECB_TX_DATA02_ADDR 0x12
300#define AO_CECB_TX_DATA03_ADDR 0x13
301#define AO_CECB_TX_DATA04_ADDR 0x14
302#define AO_CECB_TX_DATA05_ADDR 0x15
303#define AO_CECB_TX_DATA06_ADDR 0x16
304#define AO_CECB_TX_DATA07_ADDR 0x17
305#define AO_CECB_TX_DATA08_ADDR 0x18
306#define AO_CECB_TX_DATA09_ADDR 0x19
307#define AO_CECB_TX_DATA10_ADDR 0x1A
308#define AO_CECB_TX_DATA11_ADDR 0x1B
309#define AO_CECB_TX_DATA12_ADDR 0x1C
310#define AO_CECB_TX_DATA13_ADDR 0x1D
311#define AO_CECB_TX_DATA14_ADDR 0x1E
312#define AO_CECB_TX_DATA15_ADDR 0x1F
313#define AO_CECB_RX_DATA00_ADDR 0x20
314#define AO_CECB_RX_DATA01_ADDR 0x21
315#define AO_CECB_RX_DATA02_ADDR 0x22
316#define AO_CECB_RX_DATA03_ADDR 0x23
317#define AO_CECB_RX_DATA04_ADDR 0x24
318#define AO_CECB_RX_DATA05_ADDR 0x25
319#define AO_CECB_RX_DATA06_ADDR 0x26
320#define AO_CECB_RX_DATA07_ADDR 0x27
321#define AO_CECB_RX_DATA08_ADDR 0x28
322#define AO_CECB_RX_DATA09_ADDR 0x29
323#define AO_CECB_RX_DATA10_ADDR 0x2A
324#define AO_CECB_RX_DATA11_ADDR 0x2B
325#define AO_CECB_RX_DATA12_ADDR 0x2C
326#define AO_CECB_RX_DATA13_ADDR 0x2D
327#define AO_CECB_RX_DATA14_ADDR 0x2E
328#define AO_CECB_RX_DATA15_ADDR 0x2F
329#define AO_CECB_LOCK_BUF_ADDR 0x30
330#define AO_CECB_WAKEUPCTRL_ADDR 0x31
331
332/* cec ip irq flags bit discription */
333#define EECEC_IRQ_TX_DONE (1 << 16)
334#define EECEC_IRQ_RX_EOM (1 << 17)
335#define EECEC_IRQ_TX_NACK (1 << 18)
336#define EECEC_IRQ_TX_ARB_LOST (1 << 19)
337#define EECEC_IRQ_TX_ERR_INITIATOR (1 << 20)
338#define EECEC_IRQ_RX_ERR_FOLLOWER (1 << 21)
339#define EECEC_IRQ_RX_WAKEUP (1 << 22)
340#define EE_CEC_IRQ_EN_MASK (0xf << 16)
341
342/* cec irq bit flags for AO_CEC_B */
343#define CECB_IRQ_TX_DONE (1 << 0)
344#define CECB_IRQ_RX_EOM (1 << 1)
345#define CECB_IRQ_TX_NACK (1 << 2)
346#define CECB_IRQ_TX_ARB_LOST (1 << 3)
347#define CECB_IRQ_TX_ERR_INITIATOR (1 << 4)
348#define CECB_IRQ_RX_ERR_FOLLOWER (1 << 5)
349#define CECB_IRQ_RX_WAKEUP (1 << 6)
350#define CECB_IRQ_EN_MASK (0xf << 0)
351
352/* common mask */
353#define CEC_IRQ_TX_DONE (1 << (16 - shift))
354#define CEC_IRQ_RX_EOM (1 << (17 - shift))
355#define CEC_IRQ_TX_NACK (1 << (18 - shift))
356#define CEC_IRQ_TX_ARB_LOST (1 << (19 - shift))
357#define CEC_IRQ_TX_ERR_INITIATOR (1 << (20 - shift))
358#define CEC_IRQ_RX_ERR_FOLLOWER (1 << (21 - shift))
359#define CEC_IRQ_RX_WAKEUP (1 << (22 - shift))
360
361#define EDID_CEC_ID_ADDR 0x00a100a0
362#define EDID_AUTO_CEC_EN 0
363
364#define HHI_32K_CLK_CNTL (0x89 << 2)
365
366#ifdef CONFIG_AMLOGIC_AO_CEC
367unsigned int aocec_rd_reg(unsigned long addr);
368void aocec_wr_reg(unsigned long addr, unsigned long data);
369void cecrx_irq_handle(void);
370void cec_logicaddr_set(int l_add);
371void cec_arbit_bit_time_set(unsigned int bit_set,
372 unsigned int time_set, unsigned int flag);
373void cec_irq_enable(bool enable);
374void aocec_irq_enable(bool enable);
375#endif
376
377#ifdef CONFIG_AMLOGIC_MEDIA_TVIN_HDMI
378extern unsigned long hdmirx_rd_top(unsigned long addr);
379extern void hdmirx_wr_top(unsigned long addr, unsigned long data);
380extern uint32_t hdmirx_rd_dwc(uint16_t addr);
381extern void hdmirx_wr_dwc(uint16_t addr, uint32_t data);
382#else
383static inline unsigned long hdmirx_rd_top(unsigned long addr)
384{
385 return 0;
386}
387
388static inline void hdmirx_wr_top(unsigned long addr, unsigned long data)
389{
390}
391
392static inline uint32_t hdmirx_rd_dwc(uint16_t addr)
393{
394 return 0;
395}
396static inline void hdmirx_wr_dwc(uint16_t addr, uint32_t data)
397{
398}
399#endif
400
401#endif /* __AO_CEC_H__ */
402
generated by cgit at 2024-05-17 08:33:27 (GMT)