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path: root/drivers/amlogic/media/vout/lcd/lcd_phy_config.c (plain)
blob: bdc31b171ab564720d549a2343d37c4fce00d5f9
1/*
2 * drivers/amlogic/media/vout/lcd/lcd_phy_config.c
3 *
4 * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17
18#include <linux/init.h>
19#include <linux/version.h>
20#include <linux/types.h>
21#include <linux/slab.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/delay.h>
26#include <linux/amlogic/media/vout/lcd/lcd_vout.h>
27#include "lcd_reg.h"
28#include "lcd_phy_config.h"
29#include "lcd_common.h"
30
31static unsigned int lcd_lvds_channel_on_value(struct lcd_config_s *pconf)
32{
33 unsigned int channel_on = 0;
34
35 if (pconf->lcd_control.lvds_config->dual_port == 0) {
36 if (pconf->lcd_control.lvds_config->lane_reverse == 0) {
37 switch (pconf->lcd_basic.lcd_bits) {
38 case 6:
39 channel_on = 0xf;
40 break;
41 case 8:
42 channel_on = 0x1f;
43 break;
44 case 10:
45 default:
46 channel_on = 0x3f;
47 break;
48 }
49 } else {
50 switch (pconf->lcd_basic.lcd_bits) {
51 case 6:
52 channel_on = 0x3c;
53 break;
54 case 8:
55 channel_on = 0x3e;
56 break;
57 case 10:
58 default:
59 channel_on = 0x3f;
60 break;
61 }
62 }
63 if (pconf->lcd_control.lvds_config->port_swap == 1)
64 channel_on = (channel_on << 6); /* use channel B */
65 } else {
66 if (pconf->lcd_control.lvds_config->lane_reverse == 0) {
67 switch (pconf->lcd_basic.lcd_bits) {
68 case 6:
69 channel_on = 0x3cf;
70 break;
71 case 8:
72 channel_on = 0x7df;
73 break;
74 case 10:
75 default:
76 channel_on = 0xfff;
77 break;
78 }
79 } else {
80 switch (pconf->lcd_basic.lcd_bits) {
81 case 6:
82 channel_on = 0xf3c;
83 break;
84 case 8:
85 channel_on = 0xfbe;
86 break;
87 case 10:
88 default:
89 channel_on = 0xfff;
90 break;
91 }
92 }
93 }
94 return channel_on;
95}
96
97void lcd_lvds_phy_set(struct lcd_config_s *pconf, int status)
98{
99 unsigned int vswing, preem, clk_vswing, clk_preem, channel_on;
100 unsigned int data32, size;
101 struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
102 struct lvds_config_s *lvds_conf;
103
104 if (lcd_debug_print_flag)
105 LCDPR("%s: %d\n", __func__, status);
106
107 lvds_conf = pconf->lcd_control.lvds_config;
108 if (status) {
109 vswing = lvds_conf->phy_vswing & 0xf;
110 preem = lvds_conf->phy_preem & 0xf;
111 clk_vswing = lvds_conf->phy_clk_vswing & 0xf;
112 clk_preem = lvds_conf->phy_clk_preem & 0xf;
113 if (lcd_debug_print_flag)
114 LCDPR("vswing=0x%x, prrem=0x%x\n", vswing, preem);
115
116 switch (lcd_drv->data->chip_type) {
117 case LCD_CHIP_TL1:
118 size = sizeof(lvds_vx1_p2p_phy_preem_tl1) /
119 sizeof(unsigned int);
120 if (preem >= size) {
121 LCDERR("%s: invalid preem=0x%x, use default\n",
122 __func__, preem);
123 preem = 0;
124 }
125 data32 = lvds_vx1_p2p_phy_preem_tl1[preem];
126 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14,
127 0xff2027e0 | vswing);
128 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0);
129 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0x80000000);
130 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0);
131 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32);
132 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0);
133 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32);
134 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0);
135 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32);
136 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0);
137 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, data32);
138 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0);
139 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, data32);
140 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0);
141 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, data32);
142 break;
143 default:
144 if (vswing > 7) {
145 LCDERR("%s: invalid vswing=0x%x, use default\n",
146 __func__, vswing);
147 vswing = LVDS_PHY_VSWING_DFT;
148 }
149 if (preem > 7) {
150 LCDERR("%s: invalid preem=0x%x, use default\n",
151 __func__, preem);
152 preem = LVDS_PHY_PREEM_DFT;
153 }
154 if (clk_vswing > 3) {
155 LCDERR(
156 "%s: invalid clk_vswing=0x%x, use default\n",
157 __func__, clk_vswing);
158 clk_vswing = LVDS_PHY_CLK_VSWING_DFT;
159 }
160 if (clk_preem > 7) {
161 LCDERR(
162 "%s: invalid clk_preem=0x%x, use default\n",
163 __func__, clk_preem);
164 clk_preem = LVDS_PHY_CLK_PREEM_DFT;
165 }
166 channel_on = lcd_lvds_channel_on_value(pconf);
167
168 data32 = LVDS_PHY_CNTL1_G9TV |
169 (vswing << 26) | (preem << 0);
170 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32);
171 data32 = LVDS_PHY_CNTL2_G9TV;
172 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32);
173 data32 = LVDS_PHY_CNTL3_G9TV |
174 (channel_on << 16) |
175 (clk_vswing << 8) |
176 (clk_preem << 5);
177 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32);
178 break;
179 }
180 } else {
181 switch (lcd_drv->data->chip_type) {
182 case LCD_CHIP_TL1:
183 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, 0);
184 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0);
185 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0);
186 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0);
187 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0);
188 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0);
189 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0);
190 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0);
191 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0);
192 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0);
193 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, 0);
194 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0);
195 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, 0);
196 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0);
197 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, 0);
198 break;
199 default:
200 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x0);
201 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x0);
202 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x0);
203 break;
204 }
205 }
206}
207
208void lcd_vbyone_phy_set(struct lcd_config_s *pconf, int status)
209{
210 unsigned int vswing, preem, ext_pullup;
211 unsigned int data32, size;
212 unsigned int rinner_table[] = {0xa, 0xa, 0x6, 0x4};
213 struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
214 struct vbyone_config_s *vbyone_conf;
215
216 if (lcd_debug_print_flag)
217 LCDPR("%s: %d\n", __func__, status);
218
219 vbyone_conf = pconf->lcd_control.vbyone_config;
220 if (status) {
221 ext_pullup = (vbyone_conf->phy_vswing >> 4) & 0x3;
222 vswing = vbyone_conf->phy_vswing & 0xf;
223 preem = vbyone_conf->phy_preem & 0xf;
224 if (lcd_debug_print_flag) {
225 LCDPR("vswing=0x%x, prrem=0x%x\n",
226 vbyone_conf->phy_vswing, preem);
227 }
228
229 switch (lcd_drv->data->chip_type) {
230 case LCD_CHIP_TL1:
231 size = sizeof(lvds_vx1_p2p_phy_preem_tl1) /
232 sizeof(unsigned int);
233 if (preem >= size) {
234 LCDERR("%s: invalid preem=0x%x, use default\n",
235 __func__, preem);
236 preem = 0x1;
237 }
238 data32 = lvds_vx1_p2p_phy_preem_tl1[preem];
239 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14,
240 0xf02027a0 | vswing);
241 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0);
242 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0x80000000);
243 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0x40004);
244 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32);
245 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0x40004);
246 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32);
247 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0x40004);
248 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32);
249 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0x40004);
250 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, data32);
251 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0x40004);
252 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, data32);
253 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0x40004);
254 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, data32);
255 break;
256 default:
257 if (vswing > 7) {
258 LCDERR("%s: invalid vswing=0x%x, use default\n",
259 __func__, vswing);
260 vswing = VX1_PHY_VSWING_DFT;
261 }
262 if (preem > 7) {
263 LCDERR("%s: invalid preem=0x%x, use default\n",
264 __func__, preem);
265 preem = VX1_PHY_PREEM_DFT;
266 }
267 if (ext_pullup) {
268 data32 = VX1_PHY_CNTL1_G9TV_PULLUP |
269 (vswing << 3);
270 } else {
271 data32 = VX1_PHY_CNTL1_G9TV | (vswing << 3);
272 }
273 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32);
274 data32 = VX1_PHY_CNTL2_G9TV | (preem << 20) |
275 (rinner_table[ext_pullup] << 8);
276 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32);
277 data32 = VX1_PHY_CNTL3_G9TV;
278 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32);
279 break;
280 }
281 } else {
282 switch (lcd_drv->data->chip_type) {
283 case LCD_CHIP_TL1:
284 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, 0);
285 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0);
286 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0);
287 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0);
288 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0);
289 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0);
290 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0);
291 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0);
292 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0);
293 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0);
294 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, 0);
295 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0);
296 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, 0);
297 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0);
298 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, 0);
299 break;
300 default:
301 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x0);
302 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x0);
303 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x0);
304 break;
305 }
306 }
307}
308
309void lcd_mlvds_phy_set(struct lcd_config_s *pconf, int status)
310{
311 unsigned int vswing, preem;
312 unsigned int data32, size, cntl16;
313 struct mlvds_config_s *mlvds_conf;
314
315 if (lcd_debug_print_flag)
316 LCDPR("%s: %d\n", __func__, status);
317
318 mlvds_conf = pconf->lcd_control.mlvds_config;
319 if (status) {
320 vswing = mlvds_conf->phy_vswing & 0xf;
321 preem = mlvds_conf->phy_preem & 0xf;
322 if (lcd_debug_print_flag)
323 LCDPR("vswing=0x%x, prrem=0x%x\n", vswing, preem);
324
325 size = sizeof(lvds_vx1_p2p_phy_preem_tl1) /
326 sizeof(unsigned int);
327 if (preem >= size) {
328 LCDERR("%s: invalid preem=0x%x, use default\n",
329 __func__, preem);
330 preem = 0;
331 }
332 data32 = lvds_vx1_p2p_phy_preem_tl1[preem];
333 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14,
334 0xff2027e0 | vswing);
335 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0);
336 cntl16 = (mlvds_conf->pi_clk_sel << 12);
337 cntl16 |= 0x80000000;
338 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, cntl16);
339 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0);
340 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32);
341 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0);
342 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32);
343 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0);
344 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32);
345 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0);
346 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, data32);
347 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0);
348 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, data32);
349 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0);
350 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, data32);
351 } else {
352 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, 0);
353 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0);
354 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0);
355 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0);
356 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0);
357 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0);
358 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0);
359 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0);
360 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0);
361 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0);
362 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, 0);
363 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0);
364 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, 0);
365 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0);
366 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, 0);
367 }
368}
369
370void lcd_p2p_phy_set(struct lcd_config_s *pconf, int status)
371{
372 unsigned int vswing, preem;
373 unsigned int data32, size, cntl16;
374 struct p2p_config_s *p2p_conf;
375
376 if (lcd_debug_print_flag)
377 LCDPR("%s: %d\n", __func__, status);
378
379 p2p_conf = pconf->lcd_control.p2p_config;
380 if (status) {
381 vswing = p2p_conf->phy_vswing & 0xf;
382 preem = p2p_conf->phy_preem & 0xf;
383 if (lcd_debug_print_flag)
384 LCDPR("vswing=0x%x, prrem=0x%x\n", vswing, preem);
385
386 switch (p2p_conf->p2p_type) {
387 case P2P_CEDS:
388 case P2P_CMPI:
389 case P2P_ISP:
390 case P2P_EPI:
391 size = sizeof(lvds_vx1_p2p_phy_preem_tl1) /
392 sizeof(unsigned int);
393 if (preem >= size) {
394 LCDERR("%s: invalid preem=0x%x, use default\n",
395 __func__, preem);
396 preem = 0x1;
397 }
398 data32 = lvds_vx1_p2p_phy_preem_tl1[preem];
399 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14,
400 0xff2027a0 | vswing);
401 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0);
402 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0x80000000);
403 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0x40004);
404 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32);
405 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0x40004);
406 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32);
407 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0x40004);
408 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32);
409 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0x40004);
410 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, data32);
411 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0x40004);
412 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, data32);
413 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0x40004);
414 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, data32);
415 break;
416 case P2P_CHPI: /* low common mode */
417 case P2P_CSPI:
418 case P2P_USIT:
419 size = sizeof(p2p_low_common_phy_preem_tl1) /
420 sizeof(unsigned int);
421 if (preem >= size) {
422 LCDERR("%s: invalid preem=0x%x, use default\n",
423 __func__, preem);
424 preem = 0x1;
425 }
426 data32 = p2p_low_common_phy_preem_tl1[preem];
427 cntl16 = 0x80000000;
428 if (p2p_conf->p2p_type == P2P_CHPI) {
429 /* weakly pull down */
430 data32 &= ~((1 << 19) | (1 << 3));
431 }
432 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, 0xfe60027f);
433 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0);
434 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, cntl16);
435 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0x40004);
436 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32);
437 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0x40004);
438 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32);
439 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0x40004);
440 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32);
441 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0x40004);
442 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, data32);
443 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0x40004);
444 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, data32);
445 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0x40004);
446 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, data32);
447 break;
448 default:
449 LCDERR("%s: invalid p2p_type %d\n",
450 __func__, p2p_conf->p2p_type);
451 break;
452 }
453 } else {
454 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, 0);
455 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0);
456 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0);
457 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0);
458 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0);
459 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0);
460 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0);
461 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0);
462 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0);
463 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0);
464 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, 0);
465 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0);
466 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, 0);
467 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0);
468 lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, 0);
469 }
470}
471
472void lcd_mipi_phy_set(struct lcd_config_s *pconf, int status)
473{
474 unsigned int phy_reg, phy_bit, phy_width;
475 unsigned int lane_cnt;
476 struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
477
478 if (status) {
479 switch (lcd_drv->data->chip_type) {
480 case LCD_CHIP_G12A:
481 case LCD_CHIP_G12B:
482 /* HHI_MIPI_CNTL0 */
483 /* DIF_REF_CTL1:31-16bit, DIF_REF_CTL0:15-0bit */
484 lcd_hiu_write(HHI_MIPI_CNTL0,
485 (0xa487 << 16) | (0x8 << 0));
486
487 /* HHI_MIPI_CNTL1 */
488 /* DIF_REF_CTL2:15-0bit; bandgap bit16 */
489 lcd_hiu_write(HHI_MIPI_CNTL1,
490 (0x1 << 16) | (0x002e << 0));
491
492 /* HHI_MIPI_CNTL2 */
493 /* DIF_TX_CTL1:31-16bit, DIF_TX_CTL0:15-0bit */
494 lcd_hiu_write(HHI_MIPI_CNTL2,
495 (0x2680 << 16) | (0x45a << 0));
496 break;
497 default: /* LCD_CHIP_AXG */
498 /* HHI_MIPI_CNTL0 */
499 /* DIF_REF_CTL1:31-16bit, DIF_REF_CTL0:15-0bit */
500 lcd_hiu_setb(HHI_MIPI_CNTL0, 0x1b8, 16, 10);
501 lcd_hiu_setb(HHI_MIPI_CNTL0, 1, 26, 1); /* bandgap */
502 lcd_hiu_setb(HHI_MIPI_CNTL0, 1, 29, 1); /* current */
503 lcd_hiu_setb(HHI_MIPI_CNTL0, 1, 31, 1);
504 lcd_hiu_setb(HHI_MIPI_CNTL0, 0x8, 0, 16);
505
506 /* HHI_MIPI_CNTL1 */
507 /* DIF_REF_CTL2:15-0bit */
508 lcd_hiu_write(HHI_MIPI_CNTL1, (0x001e << 0));
509
510 /* HHI_MIPI_CNTL2 */
511 /* DIF_TX_CTL1:31-16bit, DIF_TX_CTL0:15-0bit */
512 lcd_hiu_write(HHI_MIPI_CNTL2,
513 (0x26e0 << 16) | (0x459 << 0));
514 break;
515 }
516
517 phy_reg = HHI_MIPI_CNTL2;
518 phy_bit = MIPI_PHY_LANE_BIT;
519 phy_width = MIPI_PHY_LANE_WIDTH;
520 switch (pconf->lcd_control.mipi_config->lane_num) {
521 case 1:
522 lane_cnt = DSI_LANE_COUNT_1;
523 break;
524 case 2:
525 lane_cnt = DSI_LANE_COUNT_2;
526 break;
527 case 3:
528 lane_cnt = DSI_LANE_COUNT_3;
529 break;
530 case 4:
531 lane_cnt = DSI_LANE_COUNT_4;
532 break;
533 default:
534 lane_cnt = 0;
535 break;
536 }
537 lcd_hiu_setb(phy_reg, lane_cnt, phy_bit, phy_width);
538 } else {
539 switch (lcd_drv->data->chip_type) {
540 case LCD_CHIP_G12A:
541 case LCD_CHIP_G12B:
542 lcd_hiu_write(HHI_MIPI_CNTL0, 0);
543 lcd_hiu_write(HHI_MIPI_CNTL1, 0);
544 lcd_hiu_write(HHI_MIPI_CNTL2, 0);
545 break;
546 default:/* LCD_CHIP_AXG */
547 lcd_hiu_setb(HHI_MIPI_CNTL0, 0, 16, 10);
548 lcd_hiu_setb(HHI_MIPI_CNTL0, 0, 31, 1);
549 lcd_hiu_setb(HHI_MIPI_CNTL0, 0, 0, 16);
550 lcd_hiu_write(HHI_MIPI_CNTL1, 0x6);
551 lcd_hiu_write(HHI_MIPI_CNTL2, 0x00200000);
552 break;
553 }
554 }
555}
556
generated by cgit at 2024-05-17 01:48:35 (GMT)