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1/*
2 * include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h
3 *
4 * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17
18#ifndef _HDMI_TX_MODULE_H
19#define _HDMI_TX_MODULE_H
20#include "hdmi_info_global.h"
21#include "hdmi_config.h"
22#include <linux/wait.h>
23#include <linux/clk.h>
24#include <linux/cdev.h>
25#include <linux/clk-provider.h>
26#include <linux/device.h>
27/* #include <linux/amlogic/aml_gpio_consumer.h> */
28
29/*****************************
30 * hdmitx attr management
31 ******************************/
32
33/************************************
34 * hdmitx device structure
35 *************************************/
36/* VIC_MAX_VALID_MODE and VIC_MAX_NUM are associated with
37 * HDMITX_VIC420_OFFSET and HDMITX_VIC_MASK in hdmi_common.h
38 */
39#define VIC_MAX_VALID_MODE 256 /* consider 4k2k */
40/* half for valid vic, half for vic with y420*/
41#define VIC_MAX_NUM 512
42#define AUD_MAX_NUM 60
43struct rx_audiocap {
44 unsigned char audio_format_code;
45 unsigned char channel_num_max;
46 unsigned char freq_cc;
47 unsigned char cc3;
48};
49
50enum hd_ctrl {
51 VID_EN, VID_DIS, AUD_EN, AUD_DIS, EDID_EN, EDID_DIS, HDCP_EN, HDCP_DIS,
52};
53
54struct rx_cap {
55 unsigned int native_Mode;
56 /*video*/
57 unsigned int VIC[VIC_MAX_NUM];
58 unsigned int VIC_count;
59 unsigned int native_VIC;
60 /*audio*/
61 struct rx_audiocap RxAudioCap[AUD_MAX_NUM];
62 unsigned char AUD_count;
63 unsigned char RxSpeakerAllocation;
64 /*vendor*/
65 unsigned int IEEEOUI;
66 unsigned int Max_TMDS_Clock1; /* HDMI1.4b TMDS_CLK */
67 unsigned int HF_IEEEOUI; /* For HDMI Forum */
68 unsigned int Max_TMDS_Clock2; /* HDMI2.0 TMDS_CLK */
69 /* CEA861-F, Table 56, Colorimetry Data Block */
70 unsigned int colorimetry_data;
71 unsigned int scdc_present:1;
72 unsigned int scdc_rr_capable:1; /* SCDC read request */
73 unsigned int lte_340mcsc_scramble:1;
74 unsigned int dc_y444:1;
75 unsigned int dc_30bit:1;
76 unsigned int dc_36bit:1;
77 unsigned int dc_48bit:1;
78 unsigned int dc_30bit_420:1;
79 unsigned int dc_36bit_420:1;
80 unsigned int dc_48bit_420:1;
81 unsigned int hdr_sup_eotf_sdr:1;
82 unsigned int hdr_sup_eotf_hdr:1;
83 unsigned int hdr_sup_eotf_smpte_st_2084:1;
84 unsigned int hdr_sup_eotf_hlg:1;
85 unsigned int hdr_sup_SMD_type1:1;
86 unsigned char hdr_lum_max;
87 unsigned char hdr_lum_avg;
88 unsigned char hdr_lum_min;
89 unsigned char IDManufacturerName[4];
90 unsigned char IDProductCode[2];
91 unsigned char IDSerialNumber[4];
92 unsigned char ReceiverProductName[16];
93 unsigned char manufacture_week;
94 unsigned char manufacture_year;
95 unsigned char physcial_weight;
96 unsigned char physcial_height;
97 unsigned char edid_version;
98 unsigned char edid_revision;
99 unsigned int ColorDeepSupport;
100 unsigned int Video_Latency;
101 unsigned int Audio_Latency;
102 unsigned int Interlaced_Video_Latency;
103 unsigned int Interlaced_Audio_Latency;
104 unsigned int threeD_present;
105 unsigned int threeD_Multi_present;
106 unsigned int hdmi_vic_LEN;
107 unsigned int HDMI_3D_LEN;
108 unsigned int threeD_Structure_ALL_15_0;
109 unsigned int threeD_MASK_15_0;
110 struct {
111 unsigned char frame_packing;
112 unsigned char top_and_bottom;
113 unsigned char side_by_side;
114 } support_3d_format[VIC_MAX_NUM];
115 struct dv_info dv_info;
116 enum hdmi_vic preferred_mode;
117 struct dtd dtd[16];
118 unsigned char dtd_idx;
119 unsigned char flag_vfpdb;
120 unsigned char number_of_dtd;
121 /*blk0 check sum*/
122 unsigned char blk0_chksum;
123};
124
125struct cts_conftab {
126 unsigned int fixed_n;
127 unsigned int tmds_clk;
128 unsigned int fixed_cts;
129};
130
131struct vic_attrmap {
132 enum hdmi_vic VIC;
133 unsigned int tmds_clk;
134};
135
136enum hdmi_event_t {
137 HDMI_TX_NONE = 0,
138 HDMI_TX_HPD_PLUGIN = 1,
139 HDMI_TX_HPD_PLUGOUT = 2,
140 HDMI_TX_INTERNAL_INTR = 4,
141};
142
143struct hdmi_phy_t {
144 unsigned long reg;
145 unsigned long val_sleep;
146 unsigned long val_save;
147};
148
149struct audcts_log {
150 unsigned int val:20;
151 unsigned int stable:1;
152};
153
154struct frac_rate_table {
155 char *hz;
156 u32 sync_num_int;
157 u32 sync_den_int;
158 u32 sync_num_dec;
159 u32 sync_den_dec;
160};
161
162enum hdmi_hdr_transfer {
163 T_UNKNOWN = 0,
164 T_BT709,
165 T_UNDEF,
166 T_BT601,
167 T_BT470M,
168 T_BT470BG,
169 T_SMPTE170M,
170 T_SMPTE240M,
171 T_LINEAR,
172 T_LOG100,
173 T_LOG316,
174 T_IEC61966_2_4,
175 T_BT1361E,
176 T_IEC61966_2_1,
177 T_BT2020_10,
178 T_BT2020_12,
179 T_SMPTE_ST_2084,
180 T_SMPTE_ST_28,
181 T_HLG,
182};
183
184enum hdmi_hdr_color {
185 C_UNKNOWN = 0,
186 C_BT709,
187 C_UNDEF,
188 C_BT601,
189 C_BT470M,
190 C_BT470BG,
191 C_SMPTE170M,
192 C_SMPTE240M,
193 C_FILM,
194 C_BT2020,
195};
196
197#define EDID_MAX_BLOCK 4
198#define HDMI_TMP_BUF_SIZE 1024
199struct hdmitx_dev {
200 struct cdev cdev; /* The cdev structure */
201 struct proc_dir_entry *proc_file;
202 struct task_struct *task;
203 struct task_struct *task_monitor;
204 struct task_struct *task_hdcp;
205 struct notifier_block nb;
206 struct workqueue_struct *hdmi_wq;
207 struct workqueue_struct *rxsense_wq;
208 struct device *hdtx_dev;
209 struct delayed_work work_hpd_plugin;
210 struct delayed_work work_hpd_plugout;
211 struct delayed_work work_rxsense;
212 struct work_struct work_internal_intr;
213 struct work_struct work_hdr;
214 struct delayed_work work_do_hdcp;
215#ifdef CONFIG_AML_HDMI_TX_14
216 struct delayed_work cec_work;
217#endif
218 struct timer_list hdcp_timer;
219 const char *hpd_pin;
220 const char *ddc_pin;
221 int chip_type;
222 int hdcp_try_times;
223 /* -1, no hdcp; 0, NULL; 1, 1.4; 2, 2.2 */
224 int hdcp_mode;
225 int hdcp_bcaps_repeater;
226 int ready; /* 1, hdmi stable output, others are 0 */
227 int hdcp_hpd_stick; /* 1 not init & reset at plugout */
228 struct {
229 void (*SetPacket)(int type, unsigned char *DB,
230 unsigned char *HB);
231 void (*SetAudioInfoFrame)(unsigned char *AUD_DB,
232 unsigned char *CHAN_STAT_BUF);
233 int (*SetDispMode)(struct hdmitx_dev *hdmitx_device);
234 int (*SetAudMode)(struct hdmitx_dev *hdmitx_device,
235 struct hdmitx_audpara *audio_param);
236 void (*SetupIRQ)(struct hdmitx_dev *hdmitx_device);
237 void (*DebugFun)(struct hdmitx_dev *hdmitx_device,
238 const char *buf);
239 void (*UnInit)(struct hdmitx_dev *hdmitx_device);
240 int (*CntlPower)(struct hdmitx_dev *hdmitx_device,
241 unsigned int cmd, unsigned int arg); /* Power control */
242 /* edid/hdcp control */
243 int (*CntlDDC)(struct hdmitx_dev *hdmitx_device,
244 unsigned int cmd, unsigned long arg);
245 /* Audio/Video/System Status */
246 int (*GetState)(struct hdmitx_dev *hdmitx_device,
247 unsigned int cmd, unsigned int arg);
248 int (*CntlPacket)(struct hdmitx_dev *hdmitx_device,
249 unsigned int cmd,
250 unsigned int arg); /* Packet control */
251 int (*CntlConfig)(struct hdmitx_dev *hdmitx_device,
252 unsigned int cmd,
253 unsigned int arg); /* Configure control */
254 int (*CntlMisc)(struct hdmitx_dev *hdmitx_device,
255 unsigned int cmd, unsigned int arg); /* Other control */
256 int (*Cntl)(struct hdmitx_dev *hdmitx_device, unsigned int cmd,
257 unsigned int arg); /* Other control */
258 } HWOp;
259 struct {
260 unsigned int hdcp14_en;
261 unsigned int hdcp14_rslt;
262 } hdcpop;
263 struct hdmi_config_platform_data config_data;
264 enum hdmi_event_t hdmitx_event;
265 unsigned int irq_hpd;
266 /* wait_queue_head_t wait_queue;*/
267 /*EDID*/
268 unsigned int cur_edid_block;
269 unsigned int cur_phy_block_ptr;
270 unsigned char EDID_buf[EDID_MAX_BLOCK * 128];
271 unsigned char EDID_buf1[EDID_MAX_BLOCK*128]; /* for second read */
272 unsigned char *edid_ptr;
273 unsigned int edid_parsing; /* Indicator that RX edid data integrated */
274 unsigned char EDID_hash[20];
275 struct rx_cap RXCap;
276 struct hdmitx_vidpara *cur_video_param;
277 int vic_count;
278 /*audio*/
279 struct hdmitx_audpara cur_audio_param;
280 int audio_param_update_flag;
281 /*status*/
282#define DISP_SWITCH_FORCE 0
283#define DISP_SWITCH_EDID 1
284 unsigned char disp_switch_config; /* 0, force; 1,edid */
285 unsigned char unplug_powerdown;
286 unsigned short physical_addr;
287 unsigned int cur_VIC;
288 /**/
289 unsigned char hpd_event; /* 1, plugin; 2, plugout */
290 unsigned char hpd_state; /* 1, connect; 0, disconnect */
291 unsigned char force_audio_flag;
292 unsigned char mux_hpd_if_pin_high_flag;
293 int auth_process_timer;
294 struct hdmitx_info hdmi_info;
295 unsigned char tmp_buf[HDMI_TMP_BUF_SIZE];
296 unsigned int log;
297 unsigned int tx_aud_cfg; /* 0, off; 1, on */
298 /* For some un-well-known TVs, no edid at all */
299 unsigned int tv_no_edid;
300 unsigned int hpd_lock;
301 struct hdmi_format_para *para;
302 /* 0: RGB444 1: Y444 2: Y422 3: Y420 */
303 /* 4: 24bit 5: 30bit 6: 36bit 7: 48bit */
304 /* if equals to 1, means current video & audio output are blank */
305 unsigned int output_blank_flag;
306 unsigned int audio_notify_flag;
307 unsigned int audio_step;
308 unsigned int repeater_tx;
309 /* 0.1% clock shift, 1080p60hz->59.94hz */
310 unsigned int frac_rate_policy;
311 unsigned int rxsense_policy;
312 /* configure for I2S: 8ch in, 2ch out */
313 /* 0: default setting 1:ch0/1 2:ch2/3 3:ch4/5 4:ch6/7 */
314 unsigned int aud_output_ch;
315 enum hdmi_hdr_transfer hdr_transfer_feature;
316 enum hdmi_hdr_color hdr_color_feature;
317 unsigned int sdr_hdr_feature;
318 unsigned int flag_3dfp:1;
319 unsigned int flag_3dtb:1;
320 unsigned int flag_3dss:1;
321};
322
323#define CMD_DDC_OFFSET (0x10 << 24)
324#define CMD_STATUS_OFFSET (0x11 << 24)
325#define CMD_PACKET_OFFSET (0x12 << 24)
326#define CMD_MISC_OFFSET (0x13 << 24)
327#define CMD_CONF_OFFSET (0x14 << 24)
328#define CMD_STAT_OFFSET (0x15 << 24)
329
330/***********************************************************************
331 * DDC CONTROL //CntlDDC
332 **********************************************************************/
333#define DDC_RESET_EDID (CMD_DDC_OFFSET + 0x00)
334#define DDC_RESET_HDCP (CMD_DDC_OFFSET + 0x01)
335#define DDC_HDCP_OP (CMD_DDC_OFFSET + 0x02)
336 #define HDCP14_ON 0x1
337 #define HDCP14_OFF 0x2
338 #define HDCP22_ON 0x3
339 #define HDCP22_OFF 0x4
340#define DDC_IS_HDCP_ON (CMD_DDC_OFFSET + 0x04)
341#define DDC_HDCP_GET_AKSV (CMD_DDC_OFFSET + 0x05)
342#define DDC_HDCP_GET_BKSV (CMD_DDC_OFFSET + 0x06)
343#define DDC_HDCP_GET_AUTH (CMD_DDC_OFFSET + 0x07)
344#define DDC_PIN_MUX_OP (CMD_DDC_OFFSET + 0x08)
345#define PIN_MUX 0x1
346#define PIN_UNMUX 0x2
347#define DDC_EDID_READ_DATA (CMD_DDC_OFFSET + 0x0a)
348#define DDC_IS_EDID_DATA_READY (CMD_DDC_OFFSET + 0x0b)
349#define DDC_EDID_GET_DATA (CMD_DDC_OFFSET + 0x0c)
350#define DDC_EDID_CLEAR_RAM (CMD_DDC_OFFSET + 0x0d)
351#define DDC_HDCP_MUX_INIT (CMD_DDC_OFFSET + 0x0e)
352#define DDC_HDCP_14_LSTORE (CMD_DDC_OFFSET + 0x0f)
353#define DDC_HDCP_22_LSTORE (CMD_DDC_OFFSET + 0x10)
354#define DDC_SCDC_DIV40_SCRAMB (CMD_DDC_OFFSET + 0x20)
355#define DDC_HDCP14_GET_BCAPS_RP (CMD_DDC_OFFSET + 0x30)
356
357/***********************************************************************
358 * CONFIG CONTROL //CntlConfig
359 **********************************************************************/
360/* Video part */
361#define CONF_VIDEO_BLANK_OP (CMD_CONF_OFFSET + 0x00)
362#define VIDEO_BLANK 0x1
363#define VIDEO_UNBLANK 0x2
364#define CONF_HDMI_DVI_MODE (CMD_CONF_OFFSET + 0x02)
365#define HDMI_MODE 0x1
366#define DVI_MODE 0x2
367#define CONF_SYSTEM_ST (CMD_CONF_OFFSET + 0x03)
368/* Audio part */
369#define CONF_CLR_AVI_PACKET (CMD_CONF_OFFSET + 0x04)
370#define CONF_CLR_VSDB_PACKET (CMD_CONF_OFFSET + 0x05)
371#define CONF_VIDEO_MAPPING (CMD_CONF_OFFSET + 0x06)
372#define CONF_GET_HDMI_DVI_MODE (CMD_CONF_OFFSET + 0x07)
373
374#define CONF_AUDIO_MUTE_OP (CMD_CONF_OFFSET + 0x1000 + 0x00)
375#define AUDIO_MUTE 0x1
376#define AUDIO_UNMUTE 0x2
377#define CONF_CLR_AUDINFO_PACKET (CMD_CONF_OFFSET + 0x1000 + 0x01)
378#define CONF_AVI_BT2020 (CMD_CONF_OFFSET + 0X2000 + 0x00)
379 #define CLR_AVI_BT2020 0x0
380 #define SET_AVI_BT2020 0x1
381/* set value as COLORSPACE_RGB444, YUV422, YUV444, YUV420 */
382#define CONF_AVI_RGBYCC_INDIC (CMD_CONF_OFFSET + 0X2000 + 0x01)
383#define CONF_AVI_Q01 (CMD_CONF_OFFSET + 0X2000 + 0x02)
384 #define RGB_RANGE_DEFAULT 0
385 #define RGB_RANGE_LIM 1
386 #define RGB_RANGE_FUL 2
387 #define RGB_RANGE_RSVD 3
388#define CONF_AVI_YQ01 (CMD_CONF_OFFSET + 0X2000 + 0x03)
389 #define YCC_RANGE_LIM 0
390 #define YCC_RANGE_FUL 1
391 #define YCC_RANGE_RSVD 2
392#define CONF_VIDEO_MUTE_OP (CMD_CONF_OFFSET + 0x1000 + 0x04)
393#define VIDEO_MUTE 0x1
394#define VIDEO_UNMUTE 0x2
395
396/***********************************************************************
397 * MISC control, hpd, hpll //CntlMisc
398 **********************************************************************/
399#define MISC_HPD_MUX_OP (CMD_MISC_OFFSET + 0x00)
400#define MISC_HPD_GPI_ST (CMD_MISC_OFFSET + 0x02)
401#define MISC_HPLL_OP (CMD_MISC_OFFSET + 0x03)
402#define HPLL_ENABLE 0x1
403#define HPLL_DISABLE 0x2
404#define HPLL_SET 0x3
405#define MISC_TMDS_PHY_OP (CMD_MISC_OFFSET + 0x04)
406#define TMDS_PHY_ENABLE 0x1
407#define TMDS_PHY_DISABLE 0x2
408#define MISC_VIID_IS_USING (CMD_MISC_OFFSET + 0x05)
409#define MISC_CONF_MODE420 (CMD_MISC_OFFSET + 0x06)
410#define MISC_TMDS_CLK_DIV40 (CMD_MISC_OFFSET + 0x07)
411#define MISC_COMP_HPLL (CMD_MISC_OFFSET + 0x08)
412#define COMP_HPLL_SET_OPTIMISE_HPLL1 0x1
413#define COMP_HPLL_SET_OPTIMISE_HPLL2 0x2
414#define MISC_COMP_AUDIO (CMD_MISC_OFFSET + 0x09)
415#define COMP_AUDIO_SET_N_6144x2 0x1
416#define COMP_AUDIO_SET_N_6144x3 0x2
417#define MISC_AVMUTE_OP (CMD_MISC_OFFSET + 0x0a)
418#define MISC_FINE_TUNE_HPLL (CMD_MISC_OFFSET + 0x0b)
419 #define OFF_AVMUTE 0x0
420 #define CLR_AVMUTE 0x1
421 #define SET_AVMUTE 0x2
422#define MISC_HPLL_FAKE (CMD_MISC_OFFSET + 0x0c)
423#define MISC_ESM_RESET (CMD_MISC_OFFSET + 0x0d)
424#define MISC_HDCP_CLKDIS (CMD_MISC_OFFSET + 0x0e)
425#define MISC_TMDS_RXSENSE (CMD_MISC_OFFSET + 0x0f)
426#define MISC_I2C_REACTIVE (CMD_MISC_OFFSET + 0x10)
427
428/***********************************************************************
429 * Get State //GetState
430 **********************************************************************/
431#define STAT_VIDEO_VIC (CMD_STAT_OFFSET + 0x00)
432#define STAT_VIDEO_CLK (CMD_STAT_OFFSET + 0x01)
433#define STAT_AUDIO_FORMAT (CMD_STAT_OFFSET + 0x10)
434#define STAT_AUDIO_CHANNEL (CMD_STAT_OFFSET + 0x11)
435#define STAT_AUDIO_CLK_STABLE (CMD_STAT_OFFSET + 0x12)
436#define STAT_AUDIO_PACK (CMD_STAT_OFFSET + 0x13)
437
438/* HDMI LOG */
439#define HDMI_LOG_HDCP (1 << 0)
440
441#define HDMI_SOURCE_DESCRIPTION 0
442#define HDMI_PACKET_VEND 1
443#define HDMI_MPEG_SOURCE_INFO 2
444#define HDMI_PACKET_AVI 3
445#define HDMI_AUDIO_INFO 4
446#define HDMI_AUDIO_CONTENT_PROTECTION 5
447#define HDMI_PACKET_HBR 6
448#define HDMI_PACKET_DRM 0x86
449
450#define HDMI_PROCESS_DELAY msleep(10)
451/* reduce a little time, previous setting is 4000/10 */
452#define AUTH_PROCESS_TIME (1000/100)
453
454#define HDMITX_VER "20170622"
455
456/***********************************************************************
457 * hdmitx protocol level interface
458 **********************************************************************/
459extern void hdmitx_init_parameters(struct hdmitx_info *info);
460extern enum hdmi_vic hdmitx_edid_vic_tab_map_vic(const char *disp_mode);
461
462extern int hdmitx_edid_parse(struct hdmitx_dev *hdmitx_device);
463extern int check_dvi_hdmi_edid_valid(unsigned char *buf);
464
465enum hdmi_vic hdmitx_edid_get_VIC(struct hdmitx_dev *hdmitx_device,
466 const char *disp_mode, char force_flag);
467
468extern int hdmitx_edid_VIC_support(enum hdmi_vic vic);
469
470extern int hdmitx_edid_dump(struct hdmitx_dev *hdmitx_device, char *buffer,
471 int buffer_len);
472bool hdmitx_edid_check_valid_mode(struct hdmitx_dev *hdev,
473 struct hdmi_format_para *para);
474extern const char *hdmitx_edid_vic_to_string(enum hdmi_vic vic);
475extern void hdmitx_edid_clear(struct hdmitx_dev *hdmitx_device);
476
477extern void hdmitx_edid_ram_buffer_clear(struct hdmitx_dev *hdmitx_device);
478
479extern void hdmitx_edid_buf_compare_print(struct hdmitx_dev *hdmitx_device);
480
481extern const char *hdmitx_edid_get_native_VIC(struct hdmitx_dev *hdmitx_device);
482
483/*
484 * HDMI Repeater TX I/F
485 * RX downstream Information from rptx to rprx
486 */
487/* send part raw edid from TX to RX */
488extern void rx_repeat_hpd_state(unsigned int st);
489/* prevent compile error in no HDMIRX case */
490void __attribute__((weak))rx_repeat_hpd_state(unsigned int st)
491{
492}
493
494extern void rx_edid_physical_addr(unsigned char a, unsigned char b,
495 unsigned char c, unsigned char d);
496void __attribute__((weak))rx_edid_physical_addr(unsigned char a,
497 unsigned char b, unsigned char c, unsigned char d)
498{
499}
500
501extern void rx_set_repeater_support(bool enable);
502void __attribute__((weak))rx_set_repeater_support(bool enable)
503{
504}
505
506extern void rx_set_receiver_edid(unsigned char *data, int len);
507void __attribute__((weak))rx_set_receiver_edid(unsigned char *data, int len)
508{
509}
510
511/*
512 * ver = 22 means downstream supports HDCP22
513 * ver = 14 means support HDCP14
514 * ver = 0 means support NO HDCP
515 */
516extern void rx_repeat_hdcp_ver(unsigned int ver);
517void __attribute__((weak))rx_repeat_hdcp_ver(unsigned int ver)
518{
519}
520
521extern void rx_set_receive_hdcp(unsigned char *data, int len, int depth,
522 bool max_cascade, bool max_devs);
523void __attribute__((weak))rx_set_receive_hdcp(unsigned char *data, int len,
524 int depth, bool max_cascade, bool max_devs)
525{
526}
527
528extern int hdmitx_set_display(struct hdmitx_dev *hdmitx_device,
529 enum hdmi_vic VideoCode);
530
531extern int hdmi_set_3d(struct hdmitx_dev *hdmitx_device, int type,
532 unsigned int param);
533
534extern int hdmitx_set_audio(struct hdmitx_dev *hdmitx_device,
535 struct hdmitx_audpara *audio_param, int hdmi_ch);
536
537/* for notify to cec */
538#define HDMITX_PLUG 1
539#define HDMITX_UNPLUG 2
540#define HDMITX_PHY_ADDR_VALID 3
541
542#ifdef CONFIG_AMLOGIC_HDMITX
543extern struct hdmitx_dev *get_hdmitx_device(void);
544extern int get_hpd_state(void);
545extern int hdmitx_event_notifier_regist(struct notifier_block *nb);
546extern int hdmitx_event_notifier_unregist(struct notifier_block *nb);
547extern void hdmitx_event_notify(unsigned long state, void *arg);
548extern void hdmitx_hdcp_status(int hdmi_authenticated);
549#else
550static inline struct hdmitx_dev *get_hdmitx_device(void)
551{
552 return NULL;
553}
554static inline int get_hpd_state(void)
555{
556 return -1;
557}
558static inline int hdmitx_event_notifier_regist(struct notifier_block *nb)
559{
560 return -EINVAL;
561}
562
563static inline int hdmitx_event_notifier_unregist(struct notifier_block *nb)
564{
565 return -EINVAL;
566}
567#endif
568
569extern int hdmi_print_buf(char *buf, int len);
570
571extern void hdmi_set_audio_para(int para);
572
573extern void hdmitx_output_rgb(void);
574
575extern int get_cur_vout_index(void);
576extern struct vinfo_s *hdmi_get_current_vinfo(void);
577void phy_pll_off(void);
578
579extern int get_hpd_state(void);
580void hdmitx_hdcp_do_work(struct hdmitx_dev *hdev);
581
582/***********************************************************************
583 * hdmitx hardware level interface
584 ***********************************************************************/
585/* #define DOUBLE_CLK_720P_1080I */
586extern unsigned char hdmi_pll_mode; /* 1, use external clk as hdmi pll source */
587
588extern void HDMITX_Meson_Init(struct hdmitx_dev *hdmitx_device);
589
590extern unsigned char hdmi_audio_off_flag;
591extern unsigned int get_hdcp22_base(void);
592/*
593 * hdmitx_audio_mute_op() is used by external driver call
594 * flag: 0: audio off 1: audio_on
595 * 2: for EDID auto mode
596 */
597extern void hdmitx_audio_mute_op(unsigned int flag);
598extern void hdmitx_video_mute_op(unsigned int flag);
599
600#define HDMITX_HWCMD_MUX_HPD_IF_PIN_HIGH 0x3
601#define HDMITX_HWCMD_TURNOFF_HDMIHW 0x4
602#define HDMITX_HWCMD_MUX_HPD 0x5
603#define HDMITX_HWCMD_PLL_MODE 0x6
604#define HDMITX_HWCMD_TURN_ON_PRBS 0x7
605#define HDMITX_FORCE_480P_CLK 0x8
606#define HDMITX_GET_AUTHENTICATE_STATE 0xa
607#define HDMITX_SW_INTERNAL_HPD_TRIG 0xb
608#define HDMITX_HWCMD_OSD_ENABLE 0xf
609
610#define HDMITX_HDCP_MONITOR 0x11
611#define HDMITX_IP_INTR_MASN_RST 0x12
612#define HDMITX_EARLY_SUSPEND_RESUME_CNTL 0x14
613#define HDMITX_EARLY_SUSPEND 0x1
614#define HDMITX_LATE_RESUME 0x2
615/* Refer to HDMI_OTHER_CTRL0 in hdmi_tx_reg.h */
616#define HDMITX_IP_SW_RST 0x15
617#define TX_CREG_SW_RST (1<<5)
618#define TX_SYS_SW_RST (1<<4)
619#define CEC_CREG_SW_RST (1<<3)
620#define CEC_SYS_SW_RST (1<<2)
621#define HDMITX_AVMUTE_CNTL 0x19
622#define AVMUTE_SET 0 /* set AVMUTE to 1 */
623#define AVMUTE_CLEAR 1 /* set AVunMUTE to 1 */
624#define AVMUTE_OFF 2 /* set both AVMUTE and AVunMUTE to 0 */
625#define HDMITX_CBUS_RST 0x1A
626#define HDMITX_INTR_MASKN_CNTL 0x1B
627#define INTR_MASKN_ENABLE 0
628#define INTR_MASKN_DISABLE 1
629#define INTR_CLEAR 2
630
631#define HDMI_HDCP_DELAYTIME_AFTER_DISPLAY 20 /* unit: ms */
632
633#define HDMITX_HDCP_MONITOR_BUF_SIZE 1024
634struct Hdcp_Sub {
635 char *hdcp_sub_name;
636 unsigned int hdcp_sub_addr_start;
637 unsigned int hdcp_sub_len;
638};
639
640/***********************************************************************
641 * hdmi debug printk
642 * level: 0 ~ 4 Default is 2
643 * 0: ERRor 1: IMPortant 2: INFormative 3: DETtal 4: LOW
644 * hdmi_print(ERR, EDID "edid bad\");
645 * hdmi_print(IMP, AUD "set audio format: AC-3\n");
646 * hdmi_print(DET)
647 **********************************************************************/
648#define HD "hdmitx: "
649#define VID HD "video: "
650#define AUD HD "audio: "
651#define CEC HD "cec: "
652#define EDID HD "edid: "
653#define HDCP HD "hdcp: "
654#define SYS HD "system: "
655#define HPD HD "hpd: "
656
657#define ERR 1
658#define IMP 2
659#define INF 3
660#define LOW 4
661#define DET (5, "%s[%d]", __func__, __LINE__)
662
663extern void hdmi_print(int level, const char *fmt, ...);
664
665#define dd()
666#ifndef dd
667#error delete debug information
668#endif
669#endif
670
671
generated by cgit at 2024-05-17 05:14:54 (GMT)