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path: root/sound/soc/amlogic/auge/earc_hw.h (plain)
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1/*
2 * sound/soc/amlogic/auge/earc_hw.h
3 *
4 * Copyright (C) 2019 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17#ifndef __EARC_HW_H__
18#define __EARC_HW_H__
19
20#include "regs.h"
21#include "iomap.h"
22#include <linux/amlogic/media/sound/iomapres.h>
23#include <linux/amlogic/media/sound/spdif_info.h>
24
25#define INT_EARCRX_CMDC_IDLE2 (0x1 << 15)
26#define INT_EARCRX_CMDC_IDLE1 (0x1 << 14)
27#define INT_EARCRX_CMDC_DISC2 (0x1 << 13)
28#define INT_EARCRX_CMDC_DISC1 (0x1 << 12)
29#define INT_EARCRX_CMDC_EARC (0x1 << 11)
30#define INT_EARCRX_CMDC_HB_STATUS (0x1 << 10)
31#define INT_EARCRX_CMDC_LOSTHB (0x1 << 9)
32#define INT_EARCRX_CMDC_TIMEOUT (0x1 << 8)
33#define INT_EARCRX_CMDC_STATUS_CH (0x1 << 7)
34#define INT_EARCRX_CMDC_REC_INVALID_ID (0x1 << 6)
35#define INT_EARCRX_CMDC_REC_INVALID_OFFSET (0x1 << 5)
36#define INT_EARCRX_CMDC_REC_UNEXP (0x1 << 4)
37#define INT_EARCRX_CMDC_REC_ECC_ERR (0x1 << 3)
38#define INT_EARCRX_CMDC_REC_PARITY_ERR (0x1 << 2)
39#define INT_EARCRX_CMDC_RECV_PACKET (0x1 << 1)
40#define INT_EARCRX_CMDC_REC_TIME_OUT (0x1 << 0)
41
42#define INT_EARCRX_ANA_RST_C_NEW_FORMAT_SET (0x1 << 17)
43#define INT_EARCRX_ANA_RST_C_EARCRX_DIV2_HOLD_SET (0x1 << 16)
44#define INT_EARCRX_ERR_CORRECT_C_BCHERR_INT_SET (0x1 << 15)
45#define INT_EARCRX_ERR_CORRECT_R_AFIFO_OVERFLOW_SET (0x1 << 14)
46#define INT_EARCRX_ERR_CORRECT_R_FIFO_OVERFLOW_SET (0x1 << 13)
47#define INT_EARCRX_USER_BIT_CHECK_R_FIFO_OVERFLOW (0x1 << 12)
48#define INT_EARCRX_USER_BIT_CHECK_C_FIFO_THD_PASS (0x1 << 11)
49#define INT_EARCRX_USER_BIT_CHECK_C_U_PK_LOST_INT_SET (0x1 << 10)
50#define INT_ARCRX_USER_BIT_CHECK_C_IU_PK_END (0x1 << 9)
51#define INT_ARCRX_BIPHASE_DECODE_C_CHST_MUTE_CLR (0x1 << 8)
52#define INT_ARCRX_BIPHASE_DECODE_C_FIND_PAPB (0x1 << 7)
53#define INT_ARCRX_BIPHASE_DECODE_C_VALID_CHANGE (0x1 << 6)
54#define INT_ARCRX_BIPHASE_DECODE_C_FIND_NONPCM2PCM (0x1 << 5)
55#define INT_ARCRX_BIPHASE_DECODE_C_PCPD_CHANGE (0x1 << 4)
56#define INT_ARCRX_BIPHASE_DECODE_C_CH_STATUS_CHANGE (0x1 << 3)
57#define INT_ARCRX_BIPHASE_DECODE_I_SAMPLE_MODE_CHANGE (0x1 << 2)
58#define INT_ARCRX_BIPHASE_DECODE_R_PARITY_ERR (0x1 << 1)
59#define INT_ARCRX_DMAC_SYNC_AFIFO_OVERFLOW (0x1 << 0)
60
61#define INT_EARCTX_CMDC_HPD_H (0x1 << 17)
62#define INT_EARCTX_CMDC_HPD_L (0x1 << 16)
63#define INT_EARCTX_CMDC_IDLE2 (0x1 << 15)
64#define INT_EARCTX_CMDC_IDLE1 (0x1 << 14)
65#define INT_EARCTX_CMDC_DISC2 (0x1 << 13)
66#define INT_EARCTX_CMDC_DISC1 (0x1 << 12)
67#define INT_EARCTX_CMDC_EARC (0x1 << 11)
68#define INT_EARCTX_CMDC_HB_STATUS (0x1 << 10)
69#define INT_EARCTX_CMDC_LOSTHB (0x1 << 9)
70#define INT_EARCTX_CMDC_TIMEOUT (0x1 << 8)
71#define INT_EARCTX_CMDC_STATUS_CH (0x1 << 7)
72#define INT_EARCTX_CMDC_RECV_FINISHED (0x1 << 6)
73#define INT_EARCTX_CMDC_RECV_NACK (0x1 << 5)
74#define INT_EARCTX_CMDC_RECV_NORSP (0x1 << 4)
75#define INT_EARCTX_CMDC_RECV_UNEXP (0x1 << 3)
76#define INT_EARCTX_CMDC_RECV_DATA (0x1 << 2)
77#define INT_EARCTX_CMDC_RECV_ACK (0x1 << 1)
78#define INT_EARCTX_CMDC_RECV_ECC_ERR (0x1 << 0)
79
80#define INT_EARCTX_FEM_C_HOLD_CLR (0x1 << 4)
81#define INT_EARCTX_FEM_C_HOLD_START (0x1 << 3)
82#define INT_EARCTX_ERRCORR_C_FIFO_THD_LESS_PASS (0x1 << 2)
83#define INT_EARCTX_ERRCORR_C_FIFO_OVERFLOW (0x1 << 1)
84#define INT_EARCTX_ERRCORR_C_FIFO_EMPTY (0x1 << 0)
85
86/* cmdc discovery and disconnect state */
87enum cmdc_st {
88 CMDC_ST_OFF,
89 CMDC_ST_IDLE1,
90 CMDC_ST_IDLE2,
91 CMDC_ST_DISC1,
92 CMDC_ST_DISC2,
93 CMDC_ST_EARC,
94 CMDC_ST_ARC
95};
96
97/* attended type: disconect, ARC, eARC */
98enum attend_type {
99 ATNDTYP_DISCNCT,
100 ATNDTYP_ARC,
101 ATNDTYP_EARC
102};
103
104enum tx_hd_hdp_mux {
105 GPIOW_1,
106 GPIOW_9,
107 GPIOW_5
108};
109
110void earcrx_cmdc_init(struct regmap *top_map);
111void earcrx_cmdc_arc_connect(struct regmap *cmdc_map, bool init);
112void earcrx_cmdc_hpd_detect(struct regmap *cmdc_map, bool st);
113void earcrx_dmac_init(struct regmap *top_map, struct regmap *dmac_map);
114void earcrx_arc_init(struct regmap *dmac_map);
115enum cmdc_st earcrx_cmdc_get_state(struct regmap *cmdc_map);
116enum attend_type earcrx_cmdc_get_attended_type(struct regmap *cmdc_map);
117void earcrx_cdmc_clr_irqs(struct regmap *top_map, int clr);
118int earcrx_cdmc_get_irqs(struct regmap *top_map);
119void earcrx_dmac_clr_irqs(struct regmap *top_map, int clr);
120int earcrx_dmac_get_irqs(struct regmap *top_map);
121void earcrx_enable(struct regmap *cmdc_map,
122 struct regmap *dmac_map, bool enable);
123void earctx_cmdc_int_mask(struct regmap *top_map);
124
125void earctx_cmdc_init(struct regmap *top_map);
126void earctx_cmdc_arc_connect(struct regmap *cmdc_map, bool init);
127void earctx_cmdc_hpd_detect(struct regmap *top_map,
128 struct regmap *cmdc_map,
129 int earc_port, bool st);
130void earctx_dmac_init(struct regmap *top_map, struct regmap *dmac_map);
131void earctx_dmac_set_format(struct regmap *dmac_map,
132 int frddr_idx, int msb, int frddr_type);
133void earctx_set_channel_status_info(struct regmap *dmac_map,
134 struct iec958_chsts *chsts);
135void earctx_cdmc_clr_irqs(struct regmap *top_map, int clr);
136int earctx_cdmc_get_irqs(struct regmap *top_map);
137void earctx_dmac_clr_irqs(struct regmap *top_map, int clr);
138int earctx_dmac_get_irqs(struct regmap *top_map);
139void earctx_enable(struct regmap *top_map,
140 struct regmap *cmdc_map,
141 struct regmap *dmac_map,
142 bool enable);
143
144#endif
145
generated by cgit at 2024-05-15 19:17:41 (GMT)