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path: root/sound/soc/amlogic/auge/tdm.c (plain)
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1/*
2 * sound/soc/amlogic/auge/tdm.c
3 *
4 * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17#define DEBUG
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/platform_device.h>
21#include <linux/init.h>
22#include <linux/errno.h>
23#include <linux/ioctl.h>
24#include <linux/of.h>
25#include <linux/of_platform.h>
26#include <linux/clk.h>
27#include <sound/core.h>
28#include <sound/pcm.h>
29#include <sound/initval.h>
30#include <sound/control.h>
31#include <sound/soc.h>
32#include <sound/pcm_params.h>
33
34#include <linux/amlogic/clk_measure.h>
35#include <linux/amlogic/cpu_version.h>
36
37#include <linux/amlogic/media/sound/aout_notify.h>
38
39#include "ddr_mngr.h"
40#include "tdm_hw.h"
41#include "sharebuffer.h"
42#include "vad.h"
43#include "spdif_hw.h"
44
45/*#define __PTM_TDM_CLK__*/
46
47
48#define DRV_NAME "aml_tdm"
49
50#define TDM_A 0
51#define TDM_B 1
52#define TDM_C 2
53#define LANE_MAX 4
54
55static void dump_pcm_setting(struct pcm_setting *setting)
56{
57 if (setting == NULL)
58 return;
59
60 pr_debug("dump_pcm_setting(%p)\n", setting);
61 pr_debug("\tpcm_mode(%d)\n", setting->pcm_mode);
62 pr_debug("\tsysclk(%d)\n", setting->sysclk);
63 pr_debug("\tsysclk_bclk_ratio(%d)\n", setting->sysclk_bclk_ratio);
64 pr_debug("\tbclk(%d)\n", setting->bclk);
65 pr_debug("\tbclk_lrclk_ratio(%d)\n", setting->bclk_lrclk_ratio);
66 pr_debug("\tlrclk(%d)\n", setting->lrclk);
67 pr_debug("\ttx_mask(%#x)\n", setting->tx_mask);
68 pr_debug("\trx_mask(%#x)\n", setting->rx_mask);
69 pr_debug("\tslots(%d)\n", setting->slots);
70 pr_debug("\tslot_width(%d)\n", setting->slot_width);
71 pr_debug("\tlane_mask_in(%#x)\n", setting->lane_mask_in);
72 pr_debug("\tlane_mask_out(%#x)\n", setting->lane_mask_out);
73 pr_debug("\tlane_oe_mask_in(%#x)\n", setting->lane_oe_mask_in);
74 pr_debug("\tlane_oe_mask_out(%#x)\n", setting->lane_oe_mask_out);
75 pr_debug("\tlane_lb_mask_in(%#x)\n", setting->lane_lb_mask_in);
76}
77
78struct tdm_chipinfo {
79 /* device id */
80 unsigned int id;
81
82 /* no eco, sclk_ws_inv for out */
83 bool sclk_ws_inv;
84
85 /* output en (oe) for pinmux */
86 bool oe_fn;
87
88 /* clk pad */
89 bool clk_pad_ctl;
90
91 /* same source */
92 bool same_src_fn;
93
94 /* same source, spdif re-enable */
95 bool same_src_spdif_reen;
96
97 /* ACODEC_ADC function */
98 bool adc_fn;
99};
100
101struct aml_tdm {
102 struct pcm_setting setting;
103 struct pinctrl *pin_ctl;
104 struct aml_audio_controller *actrl;
105 struct device *dev;
106 struct clk *clk;
107 struct clk *clk_gate;
108 struct clk *mclk;
109 struct clk *samesrc_srcpll;
110 struct clk *samesrc_clk;
111 bool contns_clk;
112 unsigned int id;
113 /* bclk src selection */
114 unsigned int clk_sel;
115 struct toddr *tddr;
116 struct frddr *fddr;
117
118 struct tdm_chipinfo *chipinfo;
119 /* share buffer with module */
120 int samesource_sel;
121 /* virtual link for i2s to hdmitx */
122 int i2s2hdmitx;
123 int acodec_adc;
124 uint last_mpll_freq;
125 uint last_mclk_freq;
126 uint last_fmt;
127};
128
129static const struct snd_pcm_hardware aml_tdm_hardware = {
130 .info =
131 SNDRV_PCM_INFO_MMAP |
132 SNDRV_PCM_INFO_MMAP_VALID |
133 SNDRV_PCM_INFO_INTERLEAVED |
134 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE,
135 .formats =
136 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
137 SNDRV_PCM_FMTBIT_S32_LE,
138
139 .period_bytes_min = 64,
140 .period_bytes_max = 256 * 1024,
141 .periods_min = 2,
142 .periods_max = 1024,
143 .buffer_bytes_max = 512 * 1024,
144
145 .rate_min = 8000,
146 .rate_max = 192000,
147 .channels_min = 1,
148 .channels_max = 32,
149};
150
151static int tdmin_clk_get(struct snd_kcontrol *kcontrol,
152 struct snd_ctl_elem_value *ucontrol)
153{
154 int clk;
155 int value;
156
157 clk = meson_clk_measure(70);
158 if (clk >= 11000000)
159 value = 3;
160 else if (clk >= 6000000)
161 value = 2;
162 else if (clk >= 2000000)
163 value = 1;
164 else
165 value = 0;
166
167
168 ucontrol->value.integer.value[0] = value;
169
170 return 0;
171}
172
173/* current sample mode and its sample rate */
174static const char *const i2sin_clk[] = {
175 "0",
176 "3000000",
177 "6000000",
178 "12000000"
179};
180
181
182
183static const struct soc_enum i2sin_clk_enum[] = {
184 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(i2sin_clk),
185 i2sin_clk),
186};
187
188
189
190static const struct snd_kcontrol_new snd_tdm_controls[] = {
191 SOC_ENUM_EXT("I2SIn CLK", i2sin_clk_enum,
192 tdmin_clk_get,
193 NULL)
194};
195
196
197
198static irqreturn_t aml_tdm_ddr_isr(int irq, void *devid)
199{
200 struct snd_pcm_substream *substream = (struct snd_pcm_substream *)devid;
201
202 if (!snd_pcm_running(substream))
203 return IRQ_HANDLED;
204
205 snd_pcm_period_elapsed(substream);
206
207 return IRQ_HANDLED;
208}
209
210/* get counts of '1's in val */
211static unsigned int pop_count(unsigned int val)
212{
213 unsigned int count = 0;
214
215 while (val) {
216 count++;
217 val = val & (val - 1);
218 }
219
220 return count;
221}
222
223static int snd_soc_of_get_slot_mask(struct device_node *np,
224 const char *prop_name,
225 unsigned int *mask)
226{
227 u32 val;
228 const __be32 *of_slot_mask = of_get_property(np, prop_name, &val);
229 int i;
230
231 if (!of_slot_mask)
232 return -EINVAL;
233
234 val /= sizeof(u32);
235 for (i = 0; i < val; i++)
236 if (be32_to_cpup(&of_slot_mask[i]))
237 *mask |= (1 << i);
238
239 return val;
240}
241
242static int of_parse_tdm_lane_slot_in(struct device_node *np,
243 unsigned int *lane_mask)
244{
245 if (lane_mask)
246 return snd_soc_of_get_slot_mask(np,
247 "dai-tdm-lane-slot-mask-in", lane_mask);
248
249 return -EINVAL;
250}
251
252static int of_parse_tdm_lane_slot_out(struct device_node *np,
253 unsigned int *lane_mask)
254{
255 if (lane_mask)
256 return snd_soc_of_get_slot_mask(np,
257 "dai-tdm-lane-slot-mask-out", lane_mask);
258
259 return -EINVAL;
260}
261
262static int of_parse_tdm_lane_oe_slot_in(struct device_node *np,
263 unsigned int *lane_mask)
264{
265 if (lane_mask)
266 return snd_soc_of_get_slot_mask(np,
267 "dai-tdm-lane-oe-slot-mask-in", lane_mask);
268
269 return -EINVAL;
270}
271
272static int of_parse_tdm_lane_oe_slot_out(struct device_node *np,
273 unsigned int *lane_mask)
274{
275 if (lane_mask)
276 return snd_soc_of_get_slot_mask(np,
277 "dai-tdm-lane-oe-slot-mask-out", lane_mask);
278
279 return -EINVAL;
280}
281
282static int of_parse_tdm_lane_lb_slot_in(struct device_node *np,
283 unsigned int *lane_mask)
284{
285 if (lane_mask)
286 return snd_soc_of_get_slot_mask(np,
287 "dai-tdm-lane-lb-slot-mask-in", lane_mask);
288
289 return -EINVAL;
290}
291
292static int aml_tdm_open(struct snd_pcm_substream *substream)
293{
294 struct snd_pcm_runtime *runtime = substream->runtime;
295 struct snd_soc_pcm_runtime *rtd = substream->private_data;
296 struct device *dev = rtd->platform->dev;
297 struct aml_tdm *p_tdm;
298
299 p_tdm = (struct aml_tdm *)dev_get_drvdata(dev);
300
301 snd_soc_set_runtime_hwparams(substream, &aml_tdm_hardware);
302
303 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
304 p_tdm->fddr = aml_audio_register_frddr(dev,
305 p_tdm->actrl, aml_tdm_ddr_isr, substream);
306 if (p_tdm->fddr == NULL) {
307 dev_err(dev, "failed to claim from ddr\n");
308 return -ENXIO;
309 }
310 } else {
311 p_tdm->tddr = aml_audio_register_toddr(dev,
312 p_tdm->actrl, aml_tdm_ddr_isr, substream);
313 if (p_tdm->tddr == NULL) {
314 dev_err(dev, "failed to claim to ddr\n");
315 return -ENXIO;
316 }
317 }
318
319 runtime->private_data = p_tdm;
320 return 0;
321}
322
323static int aml_tdm_close(struct snd_pcm_substream *substream)
324{
325 struct snd_pcm_runtime *runtime = substream->runtime;
326 struct aml_tdm *p_tdm = runtime->private_data;
327
328 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
329 aml_audio_unregister_frddr(p_tdm->dev,
330 substream);
331 else
332 aml_audio_unregister_toddr(p_tdm->dev,
333 substream);
334
335 return 0;
336}
337
338static int aml_tdm_hw_params(struct snd_pcm_substream *substream,
339 struct snd_pcm_hw_params *hw_params)
340{
341 return snd_pcm_lib_malloc_pages(substream,
342 params_buffer_bytes(hw_params));
343}
344
345static int aml_tdm_hw_free(struct snd_pcm_substream *substream)
346{
347 return snd_pcm_lib_free_pages(substream);
348}
349
350static int aml_tdm_prepare(struct snd_pcm_substream *substream)
351{
352 struct snd_pcm_runtime *runtime = substream->runtime;
353 struct aml_tdm *p_tdm = runtime->private_data;
354 unsigned int start_addr, end_addr, int_addr;
355
356 start_addr = runtime->dma_addr;
357 end_addr = start_addr + runtime->dma_bytes - 8;
358 int_addr = frames_to_bytes(runtime, runtime->period_size)/8;
359
360 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
361 struct frddr *fr = p_tdm->fddr;
362
363 aml_frddr_set_buf(fr, start_addr, end_addr);
364 aml_frddr_set_intrpt(fr, int_addr);
365 } else {
366 struct toddr *to = p_tdm->tddr;
367
368 aml_toddr_set_buf(to, start_addr, end_addr);
369 aml_toddr_set_intrpt(to, int_addr);
370 }
371
372 return 0;
373}
374
375static snd_pcm_uframes_t aml_tdm_pointer(struct snd_pcm_substream *substream)
376{
377 struct snd_pcm_runtime *runtime = substream->runtime;
378 struct aml_tdm *p_tdm = runtime->private_data;
379 unsigned int addr, start_addr;
380 snd_pcm_uframes_t frames;
381
382 start_addr = runtime->dma_addr;
383 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
384 addr = aml_frddr_get_position(p_tdm->fddr);
385 else
386 addr = aml_toddr_get_position(p_tdm->tddr);
387
388 frames = bytes_to_frames(runtime, addr - start_addr);
389 if (frames > runtime->buffer_size)
390 frames = 0;
391
392 return frames;
393}
394
395static int aml_tdm_mmap(struct snd_pcm_substream *substream,
396 struct vm_area_struct *vma)
397{
398 return snd_pcm_lib_default_mmap(substream, vma);
399}
400
401static struct snd_pcm_ops aml_tdm_ops = {
402 .open = aml_tdm_open,
403 .close = aml_tdm_close,
404 .ioctl = snd_pcm_lib_ioctl,
405 .hw_params = aml_tdm_hw_params,
406 .hw_free = aml_tdm_hw_free,
407 .prepare = aml_tdm_prepare,
408 .pointer = aml_tdm_pointer,
409 .mmap = aml_tdm_mmap,
410};
411
412#define PREALLOC_BUFFER (128 * 1024)
413#define PREALLOC_BUFFER_MAX (256 * 1024)
414static int aml_tdm_new(struct snd_soc_pcm_runtime *rtd)
415{
416 return snd_pcm_lib_preallocate_pages_for_all(
417 rtd->pcm, SNDRV_DMA_TYPE_DEV,
418 rtd->card->snd_card->dev, PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
419}
420
421struct snd_soc_platform_driver aml_tdm_platform = {
422 .ops = &aml_tdm_ops,
423 .pcm_new = aml_tdm_new,
424};
425
426static int aml_dai_tdm_prepare(struct snd_pcm_substream *substream,
427 struct snd_soc_dai *cpu_dai)
428{
429 struct snd_pcm_runtime *runtime = substream->runtime;
430 struct aml_tdm *p_tdm = snd_soc_dai_get_drvdata(cpu_dai);
431 int bit_depth;
432
433 bit_depth = snd_pcm_format_width(runtime->format);
434
435 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
436 struct frddr *fr = p_tdm->fddr;
437 enum frddr_dest dst;
438 unsigned int fifo_id;
439
440 /* share buffer prepare */
441 if (p_tdm->chipinfo &&
442 p_tdm->chipinfo->same_src_fn
443 && (p_tdm->samesource_sel >= 0)
444 && (aml_check_sharebuffer_valid(p_tdm->fddr,
445 p_tdm->samesource_sel))) {
446 sharebuffer_prepare(substream,
447 fr, p_tdm->samesource_sel);
448 }
449
450 /* i2s source to hdmix */
451 if (p_tdm->i2s2hdmitx) {
452 i2s_to_hdmitx_ctrl(p_tdm->id);
453 aout_notifier_call_chain(AOUT_EVENT_IEC_60958_PCM,
454 substream);
455 }
456
457 fifo_id = aml_frddr_get_fifo_id(fr);
458 aml_tdm_fifo_ctrl(p_tdm->actrl,
459 bit_depth,
460 substream->stream,
461 p_tdm->id,
462 fifo_id);
463
464 switch (p_tdm->id) {
465 case 0:
466 dst = TDMOUT_A;
467 break;
468 case 1:
469 dst = TDMOUT_B;
470 break;
471 case 2:
472 dst = TDMOUT_C;
473 break;
474 default:
475 dev_err(p_tdm->dev, "invalid id: %d\n",
476 p_tdm->id);
477 return -EINVAL;
478 }
479 aml_frddr_set_format(fr,
480 runtime->channels,
481 bit_depth - 1,
482 tdmout_get_frddr_type(bit_depth));
483 aml_frddr_select_dst(fr, dst);
484 aml_frddr_set_fifos(fr, 0x40, 0x20);
485 } else {
486 struct toddr *to = p_tdm->tddr;
487 enum toddr_src src;
488 unsigned int lsb = 32 - bit_depth;
489 unsigned int toddr_type;
490 struct toddr_fmt fmt;
491
492 if (vad_tdm_is_running(p_tdm->id)
493 && pm_audio_is_suspend())
494 return 0;
495
496 switch (bit_depth) {
497 case 8:
498 case 16:
499 case 32:
500 toddr_type = 0;
501 break;
502 case 24:
503 toddr_type = 4;
504 break;
505 default:
506 dev_err(p_tdm->dev, "invalid bit_depth: %d\n",
507 bit_depth);
508 return -EINVAL;
509 }
510
511 dev_info(substream->pcm->card->dev, "tdm prepare----capture\n");
512 switch (p_tdm->id) {
513 case 0:
514 src = TDMIN_A;
515 break;
516 case 1:
517 src = TDMIN_B;
518 break;
519 case 2:
520 src = TDMIN_C;
521 break;
522 default:
523 dev_err(p_tdm->dev, "invalid id: %d\n",
524 p_tdm->id);
525 return -EINVAL;
526 }
527
528 if (toddr_src_get() == FRHDMIRX) {
529 src = FRHDMIRX;
530
531 aml_update_tdmin_src(p_tdm->actrl,
532 p_tdm->id,
533 HDMIRX_I2S);
534 } else if (p_tdm->chipinfo
535 && p_tdm->chipinfo->adc_fn
536 && p_tdm->acodec_adc)
537 aml_update_tdmin_src(p_tdm->actrl,
538 p_tdm->id,
539 ACODEC_ADC);
540
541 pr_info("%s Expected toddr src:%s\n",
542 __func__,
543 toddr_src_get_str(src));
544
545 fmt.type = toddr_type;
546 fmt.msb = 31;
547 fmt.lsb = lsb;
548 fmt.endian = 0;
549 fmt.bit_depth = bit_depth;
550 fmt.ch_num = runtime->channels;
551 fmt.rate = runtime->rate;
552 aml_toddr_select_src(to, src);
553 aml_toddr_set_format(to, &fmt);
554 aml_toddr_set_fifos(to, 0x40);
555 }
556
557 return 0;
558}
559
560static int aml_dai_tdm_trigger(struct snd_pcm_substream *substream, int cmd,
561 struct snd_soc_dai *cpu_dai)
562{
563 struct aml_tdm *p_tdm = snd_soc_dai_get_drvdata(cpu_dai);
564
565 /* share buffer trigger */
566 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
567 && p_tdm->chipinfo
568 && p_tdm->chipinfo->same_src_fn
569 && (p_tdm->samesource_sel >= 0)
570 && (aml_check_sharebuffer_valid(p_tdm->fddr,
571 p_tdm->samesource_sel))
572 )
573 sharebuffer_trigger(cmd,
574 p_tdm->samesource_sel,
575 p_tdm->chipinfo->same_src_spdif_reen);
576
577 switch (cmd) {
578 case SNDRV_PCM_TRIGGER_START:
579 case SNDRV_PCM_TRIGGER_RESUME:
580 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
581
582 if ((substream->stream == SNDRV_PCM_STREAM_CAPTURE)
583 && vad_tdm_is_running(p_tdm->id)
584 && pm_audio_is_suspend()) {
585 pm_audio_set_suspend(false);
586 /* VAD switch to alsa buffer */
587 vad_update_buffer(0);
588 break;
589 }
590
591 /* reset fifo here.
592 * If not, xrun will cause channel mapping mismatch
593 */
594 aml_tdm_fifo_reset(p_tdm->actrl, substream->stream, p_tdm->id);
595
596 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
597 dev_info(substream->pcm->card->dev, "tdm playback enable\n");
598 aml_frddr_enable(p_tdm->fddr, 1);
599 aml_tdm_enable(p_tdm->actrl,
600 substream->stream, p_tdm->id, true);
601 udelay(100);
602 aml_tdm_mute_playback(p_tdm->actrl, p_tdm->id, false);
603 if (p_tdm->chipinfo
604 && p_tdm->chipinfo->same_src_fn
605 && (p_tdm->samesource_sel >= 0)
606 && (aml_check_sharebuffer_valid(p_tdm->fddr,
607 p_tdm->samesource_sel))) {
608 aml_spdifout_mute_without_actrl(0, false);
609 }
610 } else {
611 dev_info(substream->pcm->card->dev, "tdm capture enable\n");
612 aml_toddr_enable(p_tdm->tddr, 1);
613 aml_tdm_enable(p_tdm->actrl,
614 substream->stream, p_tdm->id, true);
615 }
616 break;
617 case SNDRV_PCM_TRIGGER_STOP:
618 case SNDRV_PCM_TRIGGER_SUSPEND:
619 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
620 if ((substream->stream == SNDRV_PCM_STREAM_CAPTURE)
621 && vad_tdm_is_running(p_tdm->id)
622 && pm_audio_is_suspend()) {
623 /* switch to VAD buffer */
624 vad_update_buffer(1);
625 break;
626 }
627
628 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
629 dev_info(substream->pcm->card->dev, "tdm playback stop\n");
630 aml_frddr_enable(p_tdm->fddr, 0);
631 aml_tdm_mute_playback(p_tdm->actrl, p_tdm->id, true);
632 if (p_tdm->chipinfo
633 && p_tdm->chipinfo->same_src_fn
634 && (p_tdm->samesource_sel >= 0)
635 && (aml_check_sharebuffer_valid(p_tdm->fddr,
636 p_tdm->samesource_sel))) {
637 aml_spdifout_mute_without_actrl(0, true);
638 }
639 } else {
640 dev_info(substream->pcm->card->dev, "tdm capture stop\n");
641 aml_toddr_enable(p_tdm->tddr, 0);
642 }
643 aml_tdm_enable(p_tdm->actrl,
644 substream->stream, p_tdm->id, false);
645 break;
646 default:
647 return -EINVAL;
648 }
649
650 return 0;
651}
652
653static int pcm_setting_init(struct pcm_setting *setting, unsigned int rate,
654 unsigned int channels)
655{
656 unsigned int ratio = 0;
657
658 setting->lrclk = rate;
659 setting->bclk_lrclk_ratio = setting->slots * setting->slot_width;
660 setting->bclk = setting->lrclk * setting->bclk_lrclk_ratio;
661
662 /* calculate mclk */
663 if (setting->pcm_mode == SND_SOC_DAIFMT_DSP_A ||
664 setting->pcm_mode == SND_SOC_DAIFMT_DSP_B) {
665 /* for some TDM codec, mclk limites */
666 ratio = 2;
667 } else {
668 ratio = 4;
669 }
670 setting->sysclk_bclk_ratio = ratio;
671 setting->sysclk = ratio * setting->bclk;
672
673 return 0;
674}
675static int aml_tdm_set_lanes(struct aml_tdm *p_tdm,
676 unsigned int channels, int stream)
677{
678 struct pcm_setting *setting = &p_tdm->setting;
679 unsigned int lanes, swap_val;
680 unsigned int lane_mask;
681 unsigned int set_num = 0;
682 unsigned int i;
683
684 pr_debug("asoc channels:%d, slots:%d\n", channels, setting->slots);
685
686 swap_val = 0;
687 // calc lanes by channels and slots
688 lanes = (channels - 1) / setting->slots + 1;
689 if (lanes > 4) {
690 pr_err("lanes setting error\n");
691 return -EINVAL;
692 }
693
694 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
695 // set lanes mask acordingly
696 if (p_tdm->chipinfo
697 && p_tdm->chipinfo->oe_fn
698 && p_tdm->setting.lane_oe_mask_out)
699 lane_mask = setting->lane_oe_mask_out;
700 else
701 lane_mask = setting->lane_mask_out;
702 for (i = 0; i < 4; i++) {
703 if (((1 << i) & lane_mask) && lanes) {
704 aml_tdm_set_channel_mask(p_tdm->actrl,
705 stream, p_tdm->id, i, setting->tx_mask);
706 lanes--;
707 }
708 }
709 swap_val = 0x76543210;
710 aml_tdm_set_lane_channel_swap(p_tdm->actrl,
711 stream, p_tdm->id, swap_val);
712 } else {
713 if (p_tdm->chipinfo
714 && p_tdm->chipinfo->oe_fn
715 && p_tdm->setting.lane_oe_mask_in)
716 lane_mask = setting->lane_oe_mask_in;
717 else
718 lane_mask = setting->lane_mask_in;
719
720 for (i = 0; i < 4; i++) {
721 if (i < lanes)
722 aml_tdm_set_channel_mask(p_tdm->actrl,
723 stream, p_tdm->id, i, setting->rx_mask);
724 if ((1 << i) & lane_mask) {
725 // each lane only L/R masked
726 pr_info("tdmin set lane %d\n", i);
727 swap_val |= (i * 2) << (set_num++ * 4);
728 swap_val |= (i * 2 + 1) << (set_num++ * 4);
729 }
730 }
731
732 aml_tdm_set_lane_channel_swap(p_tdm->actrl,
733 stream, p_tdm->id, swap_val);
734 }
735
736
737 return 0;
738}
739
740static int aml_tdm_set_clk_pad(struct aml_tdm *p_tdm)
741{
742 unsigned int mpad, mclk_sel;
743
744 // TODO: update pad
745 if (p_tdm->id >= 1) {
746 mpad = p_tdm->id - 1;
747 mclk_sel = p_tdm->id;
748 } else {
749 mpad = 0;
750 mclk_sel = 0;
751 }
752
753 /* clk pad */
754 aml_tdm_clk_pad_select(p_tdm->actrl, mpad, mclk_sel,
755 p_tdm->id, p_tdm->clk_sel);
756
757 return 0;
758}
759
760static int aml_dai_tdm_hw_params(struct snd_pcm_substream *substream,
761 struct snd_pcm_hw_params *params,
762 struct snd_soc_dai *cpu_dai)
763{
764 struct aml_tdm *p_tdm = snd_soc_dai_get_drvdata(cpu_dai);
765 struct pcm_setting *setting = &p_tdm->setting;
766 unsigned int rate = params_rate(params);
767 unsigned int channels = params_channels(params);
768 int ret;
769
770 ret = pcm_setting_init(setting, rate, channels);
771 if (ret)
772 return ret;
773
774 dump_pcm_setting(setting);
775
776 /* set pcm dai hw params */
777 // TODO: add clk_id
778 snd_soc_dai_set_sysclk(cpu_dai,
779 0, setting->sysclk, SND_SOC_CLOCK_OUT);
780 ret = snd_soc_dai_set_clkdiv(cpu_dai, 0, setting->sysclk_bclk_ratio);
781 if (ret)
782 return ret;
783
784 ret = snd_soc_dai_set_bclk_ratio(cpu_dai, setting->bclk_lrclk_ratio);
785 if (ret)
786 return ret;
787
788 ret = aml_tdm_set_lanes(p_tdm, channels, substream->stream);
789 if (ret)
790 return ret;
791
792 if (p_tdm->chipinfo && p_tdm->chipinfo->clk_pad_ctl) {
793 ret = aml_tdm_set_clk_pad(p_tdm);
794 if (ret)
795 return ret;
796 }
797
798 /* Must enabe channel number for VAD */
799 if ((substream->stream == SNDRV_PCM_STREAM_CAPTURE)
800 && (vad_tdm_is_running(p_tdm->id)))
801 tdmin_set_chnum_en(p_tdm->actrl, p_tdm->id, true);
802
803 /* share buffer trigger */
804 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
805 && p_tdm->chipinfo
806 && (p_tdm->chipinfo->same_src_fn)
807 && (p_tdm->samesource_sel >= 0)
808 && (aml_check_sharebuffer_valid(p_tdm->fddr,
809 p_tdm->samesource_sel))) {
810 int mux = 0, ratio = 0;
811
812 sharebuffer_get_mclk_fs_ratio(p_tdm->samesource_sel,
813 &mux, &ratio);
814 pr_info("samesource sysclk:%d\n", rate * ratio * mux);
815 if (!IS_ERR(p_tdm->samesrc_srcpll)) {
816 clk_set_rate(p_tdm->samesrc_srcpll,
817 rate * ratio * mux);
818 clk_prepare_enable(p_tdm->samesrc_srcpll);
819 }
820 if (!IS_ERR(p_tdm->samesrc_clk)) {
821 clk_set_rate(p_tdm->samesrc_clk,
822 rate * ratio);
823 clk_prepare_enable(p_tdm->samesrc_clk);
824 }
825 }
826
827 if (!p_tdm->contns_clk && !IS_ERR(p_tdm->mclk)) {
828 pr_debug("%s(), enable mclk for %s", __func__, cpu_dai->name);
829 ret = clk_prepare_enable(p_tdm->mclk);
830 if (ret) {
831 pr_err("Can't enable mclk: %d\n", ret);
832 return ret;
833 }
834 }
835
836 return 0;
837}
838
839static int aml_dai_tdm_hw_free(struct snd_pcm_substream *substream,
840 struct snd_soc_dai *cpu_dai)
841{
842 struct aml_tdm *p_tdm = snd_soc_dai_get_drvdata(cpu_dai);
843 struct frddr *fr = p_tdm->fddr;
844 int i;
845
846 for (i = 0; i < 4; i++)
847 aml_tdm_set_channel_mask(p_tdm->actrl,
848 substream->stream, p_tdm->id, i, 0);
849
850 /* Disable channel number for VAD */
851 if ((substream->stream == SNDRV_PCM_STREAM_CAPTURE)
852 && (vad_tdm_is_running(p_tdm->id)))
853 tdmin_set_chnum_en(p_tdm->actrl, p_tdm->id, false);
854
855 /* share buffer free */
856 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
857 && p_tdm->chipinfo
858 && p_tdm->chipinfo->same_src_fn
859 && (p_tdm->samesource_sel >= 0)
860 && fr
861 && (aml_check_sharebuffer_valid(fr, p_tdm->samesource_sel))) {
862 sharebuffer_free(substream,
863 fr, p_tdm->samesource_sel);
864 }
865
866 /* disable clock and gate */
867 if (!p_tdm->contns_clk && !IS_ERR(p_tdm->mclk)) {
868 pr_info("%s(), disable mclk for %s", __func__, cpu_dai->name);
869 clk_disable_unprepare(p_tdm->mclk);
870 }
871
872 return 0;
873}
874
875static int aml_dai_set_tdm_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
876{
877 struct aml_tdm *p_tdm = snd_soc_dai_get_drvdata(cpu_dai);
878
879 pr_debug("asoc aml_dai_set_tdm_fmt, %#x, %p, id(%d), clksel(%d)\n",
880 fmt, p_tdm, p_tdm->id, p_tdm->clk_sel);
881 if (p_tdm->last_fmt == fmt) {
882 pr_debug("%s(), fmt not change\n", __func__);
883 goto capture;
884 } else
885 p_tdm->last_fmt = fmt;
886
887 switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
888 case SND_SOC_DAIFMT_CONT:
889 p_tdm->contns_clk = true;
890 break;
891 case SND_SOC_DAIFMT_GATED:
892 p_tdm->contns_clk = false;
893 break;
894 default:
895 return -EINVAL;
896 }
897
898 if (p_tdm->chipinfo)
899 p_tdm->setting.sclk_ws_inv = p_tdm->chipinfo->sclk_ws_inv;
900
901 aml_tdm_set_format(p_tdm->actrl,
902 &(p_tdm->setting), p_tdm->clk_sel, p_tdm->id, fmt,
903 1, 1);
904 if (p_tdm->contns_clk && !IS_ERR(p_tdm->mclk)) {
905 int ret = clk_prepare_enable(p_tdm->mclk);
906
907 if (ret) {
908 pr_err("Can't enable mclk: %d\n", ret);
909 return ret;
910 }
911 }
912
913capture:
914 /* update skew for ACODEC_ADC */
915 if (cpu_dai->capture_active
916 && p_tdm->chipinfo
917 && p_tdm->chipinfo->adc_fn
918 && p_tdm->acodec_adc){
919 aml_update_tdmin_skew(p_tdm->actrl, p_tdm->id, 4);
920 aml_update_tdmin_rev_ws(p_tdm->actrl, p_tdm->id, 0);
921 }
922
923 return 0;
924}
925
926/* mpll clk range from 5M to 500M */
927#define AML_MPLL_FREQ_MIN 5000000
928static unsigned int aml_mpll_mclk_ratio(unsigned int freq)
929{
930 unsigned int i, ratio = 2;
931 unsigned int mpll_freq = 0;
932
933 for (i = 1; i < 15; i++) {
934 ratio = 1 << i;
935 mpll_freq = freq * ratio;
936
937 if (mpll_freq > AML_MPLL_FREQ_MIN)
938 break;
939 }
940
941 return ratio;
942}
943
944static int aml_dai_set_tdm_sysclk(struct snd_soc_dai *cpu_dai,
945 int clk_id, unsigned int freq, int dir)
946{
947 struct aml_tdm *p_tdm = snd_soc_dai_get_drvdata(cpu_dai);
948 unsigned int ratio = aml_mpll_mclk_ratio(freq);
949 unsigned int mpll_freq = 0;
950
951 p_tdm->setting.sysclk = freq;
952
953#ifdef __PTM_TDM_CLK__
954 if (p_tdm->id == 0)
955 ratio = 14;
956 else if (p_tdm->id == 1)
957 ratio = 18 * 2;
958 else if (p_tdm->id == 2)
959 ratio = 20;
960#endif
961
962 mpll_freq = freq * ratio;
963 if (mpll_freq != p_tdm->last_mpll_freq) {
964 clk_set_rate(p_tdm->clk, mpll_freq);
965 p_tdm->last_mpll_freq = mpll_freq;
966 } else {
967 pr_debug("%s(), mpll no change, keep clk\n", __func__);
968 }
969
970 if (freq != p_tdm->last_mclk_freq) {
971 clk_set_rate(p_tdm->mclk, freq);
972 p_tdm->last_mclk_freq = freq;
973 } else {
974 pr_debug("%s(), mclk no change, keep clk\n", __func__);
975 }
976
977 pr_debug("set mclk:%d, mpll:%d, get mclk:%lu, mpll:%lu\n",
978 freq,
979 freq * ratio,
980 clk_get_rate(p_tdm->mclk),
981 clk_get_rate(p_tdm->clk));
982
983 return 0;
984}
985
986static int aml_dai_set_bclk_ratio(struct snd_soc_dai *cpu_dai,
987 unsigned int ratio)
988{
989 struct aml_tdm *p_tdm = snd_soc_dai_get_drvdata(cpu_dai);
990 unsigned int bclk_ratio, lrclk_hi;
991
992 p_tdm->setting.bclk_lrclk_ratio = ratio;
993 bclk_ratio = ratio - 1;
994 lrclk_hi = 0;
995
996 if (p_tdm->setting.pcm_mode == SND_SOC_DAIFMT_I2S ||
997 p_tdm->setting.pcm_mode == SND_SOC_DAIFMT_LEFT_J) {
998 pr_debug("aml_dai_set_bclk_ratio, select I2S mode\n");
999 lrclk_hi = bclk_ratio / 2;
1000 } else {
1001 pr_debug("aml_dai_set_bclk_ratio, select TDM mode\n");
1002 }
1003 aml_tdm_set_bclk_ratio(p_tdm->actrl,
1004 p_tdm->clk_sel, lrclk_hi, bclk_ratio);
1005
1006 return 0;
1007}
1008
1009static int aml_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
1010 int div_id, int div)
1011{
1012 struct aml_tdm *p_tdm = snd_soc_dai_get_drvdata(cpu_dai);
1013 unsigned int mclk_ratio;
1014
1015 pr_debug("aml_dai_set_clkdiv, div %d, clksel(%d)\n",
1016 div, p_tdm->clk_sel);
1017
1018 p_tdm->setting.sysclk_bclk_ratio = div;
1019 mclk_ratio = div - 1;
1020 aml_tdm_set_lrclkdiv(p_tdm->actrl, p_tdm->clk_sel, mclk_ratio);
1021
1022 return 0;
1023}
1024
1025static int aml_dai_set_tdm_slot(struct snd_soc_dai *cpu_dai,
1026 unsigned int tx_mask, unsigned int rx_mask,
1027 int slots, int slot_width)
1028{
1029 struct aml_tdm *p_tdm = snd_soc_dai_get_drvdata(cpu_dai);
1030 struct snd_soc_dai_driver *drv = cpu_dai->driver;
1031 unsigned int lanes_out_cnt = 0, lanes_in_cnt = 0;
1032 unsigned int lanes_oe_out_cnt = 0, lanes_oe_in_cnt = 0;
1033 unsigned int force_oe = 0, oe_val = 0;
1034 unsigned int lanes_lb_cnt = 0;
1035 int out_lanes, in_lanes;
1036 int in_src = -1;
1037
1038 lanes_out_cnt = pop_count(p_tdm->setting.lane_mask_out);
1039 lanes_in_cnt = pop_count(p_tdm->setting.lane_mask_in);
1040 lanes_oe_out_cnt = pop_count(p_tdm->setting.lane_oe_mask_out);
1041 lanes_oe_in_cnt = pop_count(p_tdm->setting.lane_oe_mask_in);
1042 lanes_lb_cnt = pop_count(p_tdm->setting.lane_lb_mask_in);
1043
1044 pr_debug("%s(), txmask(%#x), rxmask(%#x)\n",
1045 __func__, tx_mask, rx_mask);
1046 pr_debug("\tlanes_out_cnt(%d), lanes_in_cnt(%d)\n",
1047 lanes_out_cnt, lanes_in_cnt);
1048 pr_debug("\tlanes_oe_out_cnt(%d), lanes_oe_in_cnt(%d)\n",
1049 lanes_oe_out_cnt, lanes_oe_in_cnt);
1050 pr_debug("\tlanes_lb_cnt(%d)\n",
1051 lanes_lb_cnt);
1052 pr_debug("\tslots(%d), slot_width(%d)\n",
1053 slots, slot_width);
1054 p_tdm->setting.tx_mask = tx_mask;
1055 p_tdm->setting.rx_mask = rx_mask;
1056 p_tdm->setting.slots = slots;
1057 p_tdm->setting.slot_width = slot_width;
1058
1059 if (p_tdm->setting.lane_mask_in
1060 & p_tdm->setting.lane_lb_mask_in)
1061 pr_err("pin(%x) should be selected for only one usage\n",
1062 p_tdm->setting.lane_mask_in
1063 & p_tdm->setting.lane_lb_mask_in);
1064
1065 if (p_tdm->chipinfo && p_tdm->chipinfo->oe_fn) {
1066 if (p_tdm->setting.lane_mask_out
1067 & p_tdm->setting.lane_oe_mask_out)
1068 pr_err("pin(%x) should be selected for only one usage\n",
1069 p_tdm->setting.lane_mask_out
1070 & p_tdm->setting.lane_oe_mask_out);
1071
1072 if ((p_tdm->setting.lane_mask_in
1073 & p_tdm->setting.lane_oe_mask_in)
1074 || (p_tdm->setting.lane_lb_mask_in
1075 & p_tdm->setting.lane_oe_mask_in))
1076 pr_err("pin(%x:%x) should be selected for only one usage\n",
1077 p_tdm->setting.lane_mask_in
1078 & p_tdm->setting.lane_oe_mask_in,
1079 p_tdm->setting.lane_lb_mask_in
1080 & p_tdm->setting.lane_oe_mask_in);
1081
1082 if (lanes_oe_out_cnt) {
1083 force_oe = p_tdm->setting.lane_oe_mask_out;
1084 oe_val = p_tdm->setting.lane_oe_mask_out;
1085 }
1086
1087 if (lanes_lb_cnt) {
1088 in_src = p_tdm->id + 6;
1089 if (in_src > 7) {
1090 pr_err("unknown src(%d) for tdmin\n", in_src);
1091 return -EINVAL;
1092 }
1093 }
1094 if (lanes_oe_in_cnt)
1095 in_src = p_tdm->id + 3;
1096 if (lanes_in_cnt)
1097 in_src = p_tdm->id;
1098 } else {
1099 if (lanes_lb_cnt)
1100 in_src = p_tdm->id + 3;
1101 if (lanes_in_cnt && lanes_in_cnt <= 4)
1102 in_src = p_tdm->id;
1103 if (in_src > 5) {
1104 pr_err("unknown src(%d) for tdmin\n", in_src);
1105 return -EINVAL;
1106 }
1107 }
1108
1109 out_lanes = lanes_out_cnt + lanes_oe_out_cnt;
1110 in_lanes = lanes_in_cnt + lanes_oe_in_cnt + lanes_lb_cnt;
1111
1112 if (p_tdm->chipinfo
1113 && p_tdm->chipinfo->adc_fn
1114 && p_tdm->acodec_adc) {
1115 in_src = ACODEC_ADC;
1116 }
1117
1118 if (in_lanes >= 0 && in_lanes <= 4)
1119 aml_tdm_set_slot_in(p_tdm->actrl,
1120 p_tdm->id, in_src, slot_width);
1121
1122 if (out_lanes >= 0 && out_lanes <= 4)
1123 aml_tdm_set_slot_out(p_tdm->actrl,
1124 p_tdm->id, slots, slot_width,
1125 force_oe, oe_val);
1126
1127 /* constrains hw channels_max by DTS configs */
1128 drv->playback.channels_max = slots * out_lanes;
1129 drv->capture.channels_max = slots * in_lanes;
1130
1131 return 0;
1132}
1133
1134static int aml_dai_tdm_probe(struct snd_soc_dai *cpu_dai)
1135{
1136 int ret = 0;
1137 struct aml_tdm *p_tdm = snd_soc_dai_get_drvdata(cpu_dai);
1138
1139 ret = snd_soc_add_dai_controls(cpu_dai, snd_tdm_controls,
1140 ARRAY_SIZE(snd_tdm_controls));
1141 if (ret < 0)
1142 pr_err("%s, failed add snd spdif controls\n", __func__);
1143
1144 /* config ddr arb */
1145 aml_tdm_arb_config(p_tdm->actrl);
1146
1147 return 0;
1148}
1149
1150static int aml_dai_tdm_remove(struct snd_soc_dai *cpu_dai)
1151{
1152
1153 return 0;
1154}
1155
1156static int aml_dai_tdm_mute_stream(struct snd_soc_dai *cpu_dai,
1157 int mute, int stream)
1158{
1159 struct aml_tdm *p_tdm = snd_soc_dai_get_drvdata(cpu_dai);
1160
1161 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1162 pr_debug("tdm playback mute: %d\n", mute);
1163 //aml_tdm_mute_playback(p_tdm->actrl, p_tdm->id, mute);
1164 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
1165 pr_debug("tdm capture mute: %d\n", mute);
1166 aml_tdm_mute_capture(p_tdm->actrl, p_tdm->id, mute);
1167 }
1168 return 0;
1169}
1170
1171static struct snd_soc_dai_ops aml_dai_tdm_ops = {
1172 .prepare = aml_dai_tdm_prepare,
1173 .trigger = aml_dai_tdm_trigger,
1174 .hw_params = aml_dai_tdm_hw_params,
1175 .hw_free = aml_dai_tdm_hw_free,
1176 .set_fmt = aml_dai_set_tdm_fmt,
1177 .set_sysclk = aml_dai_set_tdm_sysclk,
1178 .set_bclk_ratio = aml_dai_set_bclk_ratio,
1179 .set_clkdiv = aml_dai_set_clkdiv,
1180 .set_tdm_slot = aml_dai_set_tdm_slot,
1181 .mute_stream = aml_dai_tdm_mute_stream,
1182};
1183
1184#define AML_DAI_TDM_RATES (SNDRV_PCM_RATE_8000_192000)
1185#define AML_DAI_TDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1186 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1187
1188static struct snd_soc_dai_driver aml_tdm_dai[] = {
1189 {
1190 .name = "TDM-A",
1191 .id = 1,
1192 .probe = aml_dai_tdm_probe,
1193 .remove = aml_dai_tdm_remove,
1194 .playback = {
1195 .channels_min = 1,
1196 .channels_max = 32,
1197 .rates = AML_DAI_TDM_RATES,
1198 .formats = AML_DAI_TDM_FORMATS,
1199 },
1200 .capture = {
1201 .channels_min = 1,
1202 .channels_max = 32,
1203 .rates = AML_DAI_TDM_RATES,
1204 .formats = AML_DAI_TDM_FORMATS,
1205 },
1206 .ops = &aml_dai_tdm_ops,
1207 .symmetric_rates = 1,
1208 },
1209 {
1210 .name = "TDM-B",
1211 .id = 2,
1212 .probe = aml_dai_tdm_probe,
1213 .remove = aml_dai_tdm_remove,
1214 .playback = {
1215 .channels_min = 1,
1216 .channels_max = 8,
1217 .rates = AML_DAI_TDM_RATES,
1218 .formats = AML_DAI_TDM_FORMATS,
1219 },
1220 .capture = {
1221 .channels_min = 1,
1222 .channels_max = 32,
1223 .rates = AML_DAI_TDM_RATES,
1224 .formats = AML_DAI_TDM_FORMATS,
1225 },
1226 .ops = &aml_dai_tdm_ops,
1227 .symmetric_rates = 1,
1228 },
1229 {
1230 .name = "TDM-C",
1231 .id = 3,
1232 .probe = aml_dai_tdm_probe,
1233 .remove = aml_dai_tdm_remove,
1234 .playback = {
1235 .channels_min = 1,
1236 .channels_max = 8,
1237 .rates = AML_DAI_TDM_RATES,
1238 .formats = AML_DAI_TDM_FORMATS,
1239 },
1240 .capture = {
1241 .channels_min = 1,
1242 .channels_max = 32,
1243 .rates = AML_DAI_TDM_RATES,
1244 .formats = AML_DAI_TDM_FORMATS,
1245 },
1246 .ops = &aml_dai_tdm_ops,
1247 .symmetric_rates = 1,
1248 },
1249};
1250
1251static const struct snd_soc_component_driver aml_tdm_component = {
1252 .name = DRV_NAME,
1253};
1254
1255struct tdm_chipinfo axg_tdma_chipinfo = {
1256 .id = TDM_A,
1257};
1258
1259struct tdm_chipinfo axg_tdmb_chipinfo = {
1260 .id = TDM_B,
1261};
1262
1263struct tdm_chipinfo axg_tdmc_chipinfo = {
1264 .id = TDM_C,
1265};
1266
1267struct tdm_chipinfo g12a_tdma_chipinfo = {
1268 .id = TDM_A,
1269 .sclk_ws_inv = true,
1270 .oe_fn = true,
1271 .clk_pad_ctl = true,
1272 .same_src_fn = true,
1273};
1274
1275struct tdm_chipinfo g12a_tdmb_chipinfo = {
1276 .id = TDM_B,
1277 .sclk_ws_inv = true,
1278 .oe_fn = true,
1279 .clk_pad_ctl = true,
1280 .same_src_fn = true,
1281};
1282
1283struct tdm_chipinfo g12a_tdmc_chipinfo = {
1284 .id = TDM_C,
1285 .sclk_ws_inv = true,
1286 .oe_fn = true,
1287 .clk_pad_ctl = true,
1288 .same_src_fn = true,
1289};
1290
1291struct tdm_chipinfo tl1_tdma_chipinfo = {
1292 .id = TDM_A,
1293 .sclk_ws_inv = true,
1294 .oe_fn = true,
1295 .clk_pad_ctl = true,
1296 .same_src_fn = true,
1297 .adc_fn = true,
1298 .same_src_spdif_reen = true,
1299};
1300
1301struct tdm_chipinfo tl1_tdmb_chipinfo = {
1302 .id = TDM_B,
1303 .sclk_ws_inv = true,
1304 .oe_fn = true,
1305 .clk_pad_ctl = true,
1306 .same_src_fn = true,
1307 .adc_fn = true,
1308 .same_src_spdif_reen = true,
1309};
1310
1311struct tdm_chipinfo tl1_tdmc_chipinfo = {
1312 .id = TDM_C,
1313 .sclk_ws_inv = true,
1314 .oe_fn = true,
1315 .clk_pad_ctl = true,
1316 .same_src_fn = true,
1317 .adc_fn = true,
1318 .same_src_spdif_reen = true,
1319};
1320
1321static const struct of_device_id aml_tdm_device_id[] = {
1322 {
1323 .compatible = "amlogic, axg-snd-tdma",
1324 .data = &axg_tdma_chipinfo,
1325 },
1326 {
1327 .compatible = "amlogic, axg-snd-tdmb",
1328 .data = &axg_tdmb_chipinfo,
1329 },
1330 {
1331 .compatible = "amlogic, axg-snd-tdmc",
1332 .data = &axg_tdmc_chipinfo,
1333 },
1334 {
1335 .compatible = "amlogic, g12a-snd-tdma",
1336 .data = &g12a_tdma_chipinfo,
1337 },
1338 {
1339 .compatible = "amlogic, g12a-snd-tdmb",
1340 .data = &g12a_tdmb_chipinfo,
1341 },
1342 {
1343 .compatible = "amlogic, g12a-snd-tdmc",
1344 .data = &g12a_tdmc_chipinfo,
1345 },
1346 {
1347 .compatible = "amlogic, tl1-snd-tdma",
1348 .data = &tl1_tdma_chipinfo,
1349 },
1350 {
1351 .compatible = "amlogic, tl1-snd-tdmb",
1352 .data = &tl1_tdmb_chipinfo,
1353 },
1354 {
1355 .compatible = "amlogic, tl1-snd-tdmc",
1356 .data = &tl1_tdmc_chipinfo,
1357 },
1358 {},
1359};
1360MODULE_DEVICE_TABLE(of, aml_tdm_device_id);
1361
1362static int aml_tdm_platform_probe(struct platform_device *pdev)
1363{
1364 struct device_node *node = pdev->dev.of_node;
1365 struct device_node *node_prt = NULL;
1366 struct platform_device *pdev_parent;
1367 struct device *dev = &pdev->dev;
1368 struct aml_audio_controller *actrl = NULL;
1369 struct aml_tdm *p_tdm = NULL;
1370 struct tdm_chipinfo *p_chipinfo;
1371 int ret = 0;
1372
1373 p_tdm = devm_kzalloc(dev, sizeof(struct aml_tdm), GFP_KERNEL);
1374 if (!p_tdm)
1375 return -ENOMEM;
1376
1377 /* match data */
1378 p_chipinfo = (struct tdm_chipinfo *)
1379 of_device_get_match_data(dev);
1380 if (!p_chipinfo) {
1381 dev_warn_once(dev, "check whether to update tdm chipinfo\n");
1382 return -ENOMEM;
1383 }
1384 p_tdm->chipinfo = p_chipinfo;
1385 p_tdm->id = p_chipinfo->id;
1386 pr_info("%s, tdm ID = %u\n", __func__, p_tdm->id);
1387
1388 /* get audio controller */
1389 node_prt = of_get_parent(node);
1390 if (node_prt == NULL)
1391 return -ENXIO;
1392
1393 pdev_parent = of_find_device_by_node(node_prt);
1394 of_node_put(node_prt);
1395 actrl = (struct aml_audio_controller *)
1396 platform_get_drvdata(pdev_parent);
1397 p_tdm->actrl = actrl;
1398
1399 /* get tdm mclk sel configs */
1400 ret = of_property_read_u32(node, "dai-tdm-clk-sel",
1401 &p_tdm->clk_sel);
1402 if (ret < 0) {
1403 dev_err(&pdev->dev, "Can't retrieve dai-tdm-clk-sel\n");
1404 return -ENXIO;
1405 }
1406
1407 /* default no same source */
1408 if (p_tdm->chipinfo &&
1409 p_tdm->chipinfo->same_src_fn) {
1410
1411 ret = of_property_read_u32(node, "samesource_sel",
1412 &p_tdm->samesource_sel);
1413 if (ret < 0)
1414 p_tdm->samesource_sel = -1;
1415 else {
1416 p_tdm->samesrc_srcpll = devm_clk_get(&pdev->dev,
1417 "samesource_srcpll");
1418 if (IS_ERR(p_tdm->samesrc_srcpll)) {
1419 dev_err(&pdev->dev,
1420 "Can't retrieve samesrc_srcpll clock\n");
1421 return PTR_ERR(p_tdm->samesrc_srcpll);
1422 }
1423 p_tdm->samesrc_clk = devm_clk_get(&pdev->dev,
1424 "samesource_clk");
1425 if (IS_ERR(p_tdm->samesrc_clk)) {
1426 dev_err(&pdev->dev,
1427 "Can't retrieve samesrc_clk clock\n");
1428 return PTR_ERR(p_tdm->samesrc_clk);
1429 }
1430 ret = clk_set_parent(p_tdm->samesrc_clk,
1431 p_tdm->samesrc_srcpll);
1432 if (ret) {
1433 dev_err(dev, "can't set samesource clock\n");
1434 return ret;
1435 }
1436 pr_info("TDM id %d samesource_sel:%d\n",
1437 p_tdm->id,
1438 p_tdm->samesource_sel);
1439 }
1440 }
1441 /* default no acodec_adc */
1442 if (p_tdm->chipinfo &&
1443 p_tdm->chipinfo->adc_fn) {
1444
1445 ret = of_property_read_u32(node, "acodec_adc",
1446 &p_tdm->acodec_adc);
1447 if (ret < 0)
1448 p_tdm->acodec_adc = 0;
1449 else
1450 pr_info("TDM id %d supports ACODEC_ADC\n", p_tdm->id);
1451 }
1452
1453 ret = of_property_read_u32(node, "i2s2hdmi",
1454 &p_tdm->i2s2hdmitx);
1455 if (ret < 0)
1456 p_tdm->i2s2hdmitx = 0;
1457 pr_info("TDM id %d i2s2hdmi:%d\n",
1458 p_tdm->id,
1459 p_tdm->i2s2hdmitx);
1460
1461 /* get tdm lanes info. if not, set to default 0 */
1462 ret = of_parse_tdm_lane_slot_in(node,
1463 &p_tdm->setting.lane_mask_in);
1464 if (ret < 0)
1465 p_tdm->setting.lane_mask_in = 0x0;
1466
1467 ret = of_parse_tdm_lane_slot_out(node,
1468 &p_tdm->setting.lane_mask_out);
1469 if (ret < 0)
1470 p_tdm->setting.lane_mask_out = 0x0;
1471
1472 /* get tdm lanes oe info. if not, set to default 0 */
1473 ret = of_parse_tdm_lane_oe_slot_in(node,
1474 &p_tdm->setting.lane_oe_mask_in);
1475 if (ret < 0)
1476 p_tdm->setting.lane_oe_mask_in = 0x0;
1477
1478 ret = of_parse_tdm_lane_oe_slot_out(node,
1479 &p_tdm->setting.lane_oe_mask_out);
1480 if (ret < 0)
1481 p_tdm->setting.lane_oe_mask_out = 0x0;
1482
1483 /* get tdm lanes lb info. if not, set to default 0 */
1484 ret = of_parse_tdm_lane_lb_slot_in(node,
1485 &p_tdm->setting.lane_lb_mask_in);
1486 if (ret < 0)
1487 p_tdm->setting.lane_lb_mask_in = 0x0;
1488
1489 p_tdm->clk = devm_clk_get(&pdev->dev, "clk_srcpll");
1490 if (IS_ERR(p_tdm->clk)) {
1491 dev_err(&pdev->dev, "Can't retrieve mpll2 clock\n");
1492 return PTR_ERR(p_tdm->clk);
1493 }
1494
1495 p_tdm->mclk = devm_clk_get(&pdev->dev, "mclk");
1496 if (IS_ERR(p_tdm->mclk)) {
1497 dev_err(&pdev->dev, "Can't retrieve mclk\n");
1498 return PTR_ERR(p_tdm->mclk);
1499 }
1500
1501 ret = clk_set_parent(p_tdm->mclk, p_tdm->clk);
1502 if (ret) {
1503 dev_err(dev, "can't set tdm parent clock\n");
1504 return ret;
1505 }
1506
1507 /* complete mclk for tdm */
1508 if (get_meson_cpu_version(MESON_CPU_VERSION_LVL_MINOR) == 0xa)
1509 meson_clk_measure((1<<16) | 0x67);
1510
1511 p_tdm->pin_ctl = devm_pinctrl_get_select(dev, "tdm_pins");
1512 if (IS_ERR(p_tdm->pin_ctl)) {
1513 dev_info(dev, "aml_tdm_get_pins error!\n");
1514 /*return PTR_ERR(p_tdm->pin_ctl);*/
1515 }
1516
1517 p_tdm->dev = dev;
1518 dev_set_drvdata(dev, p_tdm);
1519
1520 ret = devm_snd_soc_register_component(dev, &aml_tdm_component,
1521 &aml_tdm_dai[p_tdm->id], 1);
1522 if (ret) {
1523 dev_err(dev, "devm_snd_soc_register_component failed\n");
1524 return ret;
1525 }
1526
1527 return devm_snd_soc_register_platform(dev, &aml_tdm_platform);
1528}
1529
1530static int aml_tdm_platform_suspend(struct platform_device *pdev,
1531 pm_message_t state)
1532{
1533 return 0;
1534}
1535static int aml_tdm_platform_resume(struct platform_device *pdev)
1536{
1537 /* complete mclk for tdm */
1538 if (get_meson_cpu_version(MESON_CPU_VERSION_LVL_MINOR) == 0xa)
1539 meson_clk_measure((1<<16) | 0x67);
1540
1541 return 0;
1542}
1543
1544struct platform_driver aml_tdm_driver = {
1545 .driver = {
1546 .name = DRV_NAME,
1547 .of_match_table = aml_tdm_device_id,
1548 },
1549 .probe = aml_tdm_platform_probe,
1550 .suspend = aml_tdm_platform_suspend,
1551 .resume = aml_tdm_platform_resume,
1552};
1553module_platform_driver(aml_tdm_driver);
1554
1555MODULE_AUTHOR("Amlogic, Inc.");
1556MODULE_DESCRIPTION("Amlogic TDM ASoc driver");
1557MODULE_LICENSE("GPL");
1558MODULE_ALIAS("platform:" DRV_NAME);
1559MODULE_DEVICE_TABLE(of, aml_tdm_device_id);
1560
generated by cgit at 2024-05-17 11:57:36 (GMT)