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path: root/sound/soc/amlogic/auge/tdm.c (plain)
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1/*
2 * sound/soc/amlogic/auge/tdm.c
3 *
4 * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17#define DEBUG
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/platform_device.h>
21#include <linux/init.h>
22#include <linux/errno.h>
23#include <linux/ioctl.h>
24#include <linux/of.h>
25#include <linux/of_platform.h>
26#include <linux/clk.h>
27#include <sound/core.h>
28#include <sound/pcm.h>
29#include <sound/initval.h>
30#include <sound/control.h>
31#include <sound/soc.h>
32#include <sound/pcm_params.h>
33
34#include <linux/amlogic/clk_measure.h>
35#include <linux/amlogic/cpu_version.h>
36
37#include <linux/amlogic/media/sound/aout_notify.h>
38
39#include "ddr_mngr.h"
40#include "tdm_hw.h"
41#include "sharebuffer.h"
42#include "vad.h"
43#include "spdif_hw.h"
44
45/*#define __PTM_TDM_CLK__*/
46
47
48#define DRV_NAME "aml_tdm"
49
50#define TDM_A 0
51#define TDM_B 1
52#define TDM_C 2
53#define LANE_MAX 4
54
55static void dump_pcm_setting(struct pcm_setting *setting)
56{
57 if (setting == NULL)
58 return;
59
60 pr_debug("dump_pcm_setting(%p)\n", setting);
61 pr_debug("\tpcm_mode(%d)\n", setting->pcm_mode);
62 pr_debug("\tsysclk(%d)\n", setting->sysclk);
63 pr_debug("\tsysclk_bclk_ratio(%d)\n", setting->sysclk_bclk_ratio);
64 pr_debug("\tbclk(%d)\n", setting->bclk);
65 pr_debug("\tbclk_lrclk_ratio(%d)\n", setting->bclk_lrclk_ratio);
66 pr_debug("\tlrclk(%d)\n", setting->lrclk);
67 pr_debug("\ttx_mask(%#x)\n", setting->tx_mask);
68 pr_debug("\trx_mask(%#x)\n", setting->rx_mask);
69 pr_debug("\tslots(%d)\n", setting->slots);
70 pr_debug("\tslot_width(%d)\n", setting->slot_width);
71 pr_debug("\tlane_mask_in(%#x)\n", setting->lane_mask_in);
72 pr_debug("\tlane_mask_out(%#x)\n", setting->lane_mask_out);
73 pr_debug("\tlane_oe_mask_in(%#x)\n", setting->lane_oe_mask_in);
74 pr_debug("\tlane_oe_mask_out(%#x)\n", setting->lane_oe_mask_out);
75 pr_debug("\tlane_lb_mask_in(%#x)\n", setting->lane_lb_mask_in);
76}
77
78struct tdm_chipinfo {
79 /* device id */
80 unsigned int id;
81
82 /* no eco, sclk_ws_inv for out */
83 bool sclk_ws_inv;
84
85 /* output en (oe) for pinmux */
86 bool oe_fn;
87
88 /* clk pad */
89 bool clk_pad_ctl;
90
91 /* same source */
92 bool same_src_fn;
93
94 /* same source, spdif re-enable */
95 bool same_src_spdif_reen;
96
97 /* ACODEC_ADC function */
98 bool adc_fn;
99};
100
101struct aml_tdm {
102 struct pcm_setting setting;
103 struct pinctrl *pin_ctl;
104 struct aml_audio_controller *actrl;
105 struct device *dev;
106 struct clk *clk;
107 struct clk *clk_gate;
108 struct clk *mclk;
109 struct clk *samesrc_srcpll;
110 struct clk *samesrc_clk;
111 bool contns_clk;
112 unsigned int id;
113 /* bclk src selection */
114 unsigned int clk_sel;
115 struct toddr *tddr;
116 struct frddr *fddr;
117
118 struct tdm_chipinfo *chipinfo;
119 /* share buffer with module */
120 int samesource_sel;
121 /* virtual link for i2s to hdmitx */
122 int i2s2hdmitx;
123 int acodec_adc;
124 uint last_mpll_freq;
125 uint last_mclk_freq;
126 uint last_fmt;
127};
128
129static const struct snd_pcm_hardware aml_tdm_hardware = {
130 .info =
131 SNDRV_PCM_INFO_MMAP |
132 SNDRV_PCM_INFO_MMAP_VALID |
133 SNDRV_PCM_INFO_INTERLEAVED |
134 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE,
135 .formats =
136 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
137 SNDRV_PCM_FMTBIT_S32_LE,
138
139 .period_bytes_min = 64,
140 .period_bytes_max = 256 * 1024,
141 .periods_min = 2,
142 .periods_max = 1024,
143 .buffer_bytes_max = 512 * 1024,
144
145 .rate_min = 8000,
146 .rate_max = 192000,
147 .channels_min = 1,
148 .channels_max = 32,
149};
150
151static int tdmin_clk_get(struct snd_kcontrol *kcontrol,
152 struct snd_ctl_elem_value *ucontrol)
153{
154 int clk;
155 int value;
156
157 clk = meson_clk_measure(70);
158 if (clk >= 11000000)
159 value = 3;
160 else if (clk >= 6000000)
161 value = 2;
162 else if (clk >= 2000000)
163 value = 1;
164 else
165 value = 0;
166
167
168 ucontrol->value.integer.value[0] = value;
169
170 return 0;
171}
172
173/* current sample mode and its sample rate */
174static const char *const i2sin_clk[] = {
175 "0",
176 "3000000",
177 "6000000",
178 "12000000"
179};
180
181
182
183static const struct soc_enum i2sin_clk_enum[] = {
184 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(i2sin_clk),
185 i2sin_clk),
186};
187
188
189
190static const struct snd_kcontrol_new snd_tdm_controls[] = {
191 SOC_ENUM_EXT("I2SIn CLK", i2sin_clk_enum,
192 tdmin_clk_get,
193 NULL)
194};
195
196
197
198static irqreturn_t aml_tdm_ddr_isr(int irq, void *devid)
199{
200 struct snd_pcm_substream *substream = (struct snd_pcm_substream *)devid;
201
202 if (!snd_pcm_running(substream))
203 return IRQ_HANDLED;
204
205 snd_pcm_period_elapsed(substream);
206
207 return IRQ_HANDLED;
208}
209
210/* get counts of '1's in val */
211static unsigned int pop_count(unsigned int val)
212{
213 unsigned int count = 0;
214
215 while (val) {
216 count++;
217 val = val & (val - 1);
218 }
219
220 return count;
221}
222
223static int snd_soc_of_get_slot_mask(struct device_node *np,
224 const char *prop_name,
225 unsigned int *mask)
226{
227 u32 val;
228 const __be32 *of_slot_mask = of_get_property(np, prop_name, &val);
229 int i;
230
231 if (!of_slot_mask)
232 return -EINVAL;
233
234 val /= sizeof(u32);
235 for (i = 0; i < val; i++)
236 if (be32_to_cpup(&of_slot_mask[i]))
237 *mask |= (1 << i);
238
239 return val;
240}
241
242static int of_parse_tdm_lane_slot_in(struct device_node *np,
243 unsigned int *lane_mask)
244{
245 if (lane_mask)
246 return snd_soc_of_get_slot_mask(np,
247 "dai-tdm-lane-slot-mask-in", lane_mask);
248
249 return -EINVAL;
250}
251
252static int of_parse_tdm_lane_slot_out(struct device_node *np,
253 unsigned int *lane_mask)
254{
255 if (lane_mask)
256 return snd_soc_of_get_slot_mask(np,
257 "dai-tdm-lane-slot-mask-out", lane_mask);
258
259 return -EINVAL;
260}
261
262static int of_parse_tdm_lane_oe_slot_in(struct device_node *np,
263 unsigned int *lane_mask)
264{
265 if (lane_mask)
266 return snd_soc_of_get_slot_mask(np,
267 "dai-tdm-lane-oe-slot-mask-in", lane_mask);
268
269 return -EINVAL;
270}
271
272static int of_parse_tdm_lane_oe_slot_out(struct device_node *np,
273 unsigned int *lane_mask)
274{
275 if (lane_mask)
276 return snd_soc_of_get_slot_mask(np,
277 "dai-tdm-lane-oe-slot-mask-out", lane_mask);
278
279 return -EINVAL;
280}
281
282static int of_parse_tdm_lane_lb_slot_in(struct device_node *np,
283 unsigned int *lane_mask)
284{
285 if (lane_mask)
286 return snd_soc_of_get_slot_mask(np,
287 "dai-tdm-lane-lb-slot-mask-in", lane_mask);
288
289 return -EINVAL;
290}
291
292static int aml_tdm_open(struct snd_pcm_substream *substream)
293{
294 struct snd_pcm_runtime *runtime = substream->runtime;
295 struct snd_soc_pcm_runtime *rtd = substream->private_data;
296 struct device *dev = rtd->platform->dev;
297 struct aml_tdm *p_tdm;
298
299 p_tdm = (struct aml_tdm *)dev_get_drvdata(dev);
300
301 snd_soc_set_runtime_hwparams(substream, &aml_tdm_hardware);
302
303 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
304 p_tdm->fddr = aml_audio_register_frddr(dev,
305 p_tdm->actrl, aml_tdm_ddr_isr, substream);
306 if (p_tdm->fddr == NULL) {
307 dev_err(dev, "failed to claim from ddr\n");
308 return -ENXIO;
309 }
310 } else {
311 p_tdm->tddr = aml_audio_register_toddr(dev,
312 p_tdm->actrl, aml_tdm_ddr_isr, substream);
313 if (p_tdm->tddr == NULL) {
314 dev_err(dev, "failed to claim to ddr\n");
315 return -ENXIO;
316 }
317 }
318
319 runtime->private_data = p_tdm;
320 return 0;
321}
322
323static int aml_tdm_close(struct snd_pcm_substream *substream)
324{
325 struct snd_pcm_runtime *runtime = substream->runtime;
326 struct aml_tdm *p_tdm = runtime->private_data;
327
328 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
329 aml_audio_unregister_frddr(p_tdm->dev,
330 substream);
331 else
332 aml_audio_unregister_toddr(p_tdm->dev,
333 substream);
334
335 return 0;
336}
337
338static int aml_tdm_hw_params(struct snd_pcm_substream *substream,
339 struct snd_pcm_hw_params *hw_params)
340{
341 return snd_pcm_lib_malloc_pages(substream,
342 params_buffer_bytes(hw_params));
343}
344
345static int aml_tdm_hw_free(struct snd_pcm_substream *substream)
346{
347 return snd_pcm_lib_free_pages(substream);
348}
349
350static int aml_tdm_prepare(struct snd_pcm_substream *substream)
351{
352 struct snd_pcm_runtime *runtime = substream->runtime;
353 struct aml_tdm *p_tdm = runtime->private_data;
354 unsigned int start_addr, end_addr, int_addr;
355
356 start_addr = runtime->dma_addr;
357 end_addr = start_addr + runtime->dma_bytes - 8;
358 int_addr = frames_to_bytes(runtime, runtime->period_size)/8;
359
360 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
361 struct frddr *fr = p_tdm->fddr;
362
363 aml_frddr_set_buf(fr, start_addr, end_addr);
364 aml_frddr_set_intrpt(fr, int_addr);
365 } else {
366 struct toddr *to = p_tdm->tddr;
367
368 aml_toddr_set_buf(to, start_addr, end_addr);
369 aml_toddr_set_intrpt(to, int_addr);
370 }
371
372 return 0;
373}
374
375static snd_pcm_uframes_t aml_tdm_pointer(struct snd_pcm_substream *substream)
376{
377 struct snd_pcm_runtime *runtime = substream->runtime;
378 struct aml_tdm *p_tdm = runtime->private_data;
379 unsigned int addr, start_addr;
380 snd_pcm_uframes_t frames;
381
382 start_addr = runtime->dma_addr;
383 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
384 addr = aml_frddr_get_position(p_tdm->fddr);
385 else
386 addr = aml_toddr_get_position(p_tdm->tddr);
387
388 frames = bytes_to_frames(runtime, addr - start_addr);
389 if (frames > runtime->buffer_size)
390 frames = 0;
391
392 return frames;
393}
394
395static int aml_tdm_mmap(struct snd_pcm_substream *substream,
396 struct vm_area_struct *vma)
397{
398 return snd_pcm_lib_default_mmap(substream, vma);
399}
400
401static struct snd_pcm_ops aml_tdm_ops = {
402 .open = aml_tdm_open,
403 .close = aml_tdm_close,
404 .ioctl = snd_pcm_lib_ioctl,
405 .hw_params = aml_tdm_hw_params,
406 .hw_free = aml_tdm_hw_free,
407 .prepare = aml_tdm_prepare,
408 .pointer = aml_tdm_pointer,
409 .mmap = aml_tdm_mmap,
410};
411
412#define PREALLOC_BUFFER (128 * 1024)
413#define PREALLOC_BUFFER_MAX (256 * 1024)
414static int aml_tdm_new(struct snd_soc_pcm_runtime *rtd)
415{
416 return snd_pcm_lib_preallocate_pages_for_all(
417 rtd->pcm, SNDRV_DMA_TYPE_DEV,
418 rtd->card->snd_card->dev, PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
419}
420
421struct snd_soc_platform_driver aml_tdm_platform = {
422 .ops = &aml_tdm_ops,
423 .pcm_new = aml_tdm_new,
424};
425
426static int aml_dai_tdm_prepare(struct snd_pcm_substream *substream,
427 struct snd_soc_dai *cpu_dai)
428{
429 struct snd_pcm_runtime *runtime = substream->runtime;
430 struct aml_tdm *p_tdm = snd_soc_dai_get_drvdata(cpu_dai);
431 int bit_depth;
432
433 bit_depth = snd_pcm_format_width(runtime->format);
434
435 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
436 struct frddr *fr = p_tdm->fddr;
437 enum frddr_dest dst;
438 unsigned int fifo_id;
439
440 /* share buffer prepare */
441 if (p_tdm->chipinfo &&
442 p_tdm->chipinfo->same_src_fn
443 && (p_tdm->samesource_sel >= 0)
444 && (aml_check_sharebuffer_valid(p_tdm->fddr,
445 p_tdm->samesource_sel))) {
446 sharebuffer_prepare(substream,
447 fr, p_tdm->samesource_sel);
448 }
449
450 /* i2s source to hdmix */
451 if (p_tdm->i2s2hdmitx) {
452 i2s_to_hdmitx_ctrl(p_tdm->id);
453 aout_notifier_call_chain(AOUT_EVENT_IEC_60958_PCM,
454 substream);
455 }
456
457 fifo_id = aml_frddr_get_fifo_id(fr);
458 aml_tdm_fifo_ctrl(p_tdm->actrl,
459 bit_depth,
460 substream->stream,
461 p_tdm->id,
462 fifo_id);
463
464 switch (p_tdm->id) {
465 case 0:
466 dst = TDMOUT_A;
467 break;
468 case 1:
469 dst = TDMOUT_B;
470 break;
471 case 2:
472 dst = TDMOUT_C;
473 break;
474 default:
475 dev_err(p_tdm->dev, "invalid id: %d\n",
476 p_tdm->id);
477 return -EINVAL;
478 }
479 aml_frddr_set_format(fr,
480 runtime->channels,
481 bit_depth - 1,
482 tdmout_get_frddr_type(bit_depth));
483 aml_frddr_select_dst(fr, dst);
484 aml_frddr_set_fifos(fr, 0x40, 0x20);
485 } else {
486 struct toddr *to = p_tdm->tddr;
487 enum toddr_src src;
488 unsigned int lsb = 32 - bit_depth;
489 unsigned int toddr_type;
490 struct toddr_fmt fmt;
491
492 if (vad_tdm_is_running(p_tdm->id)
493 && pm_audio_is_suspend())
494 return 0;
495
496 switch (bit_depth) {
497 case 8:
498 case 16:
499 case 32:
500 toddr_type = 0;
501 break;
502 case 24:
503 toddr_type = 4;
504 break;
505 default:
506 dev_err(p_tdm->dev, "invalid bit_depth: %d\n",
507 bit_depth);
508 return -EINVAL;
509 }
510
511 dev_info(substream->pcm->card->dev, "tdm prepare----capture\n");
512 switch (p_tdm->id) {
513 case 0:
514 src = TDMIN_A;
515 break;
516 case 1:
517 src = TDMIN_B;
518 break;
519 case 2:
520 src = TDMIN_C;
521 break;
522 default:
523 dev_err(p_tdm->dev, "invalid id: %d\n",
524 p_tdm->id);
525 return -EINVAL;
526 }
527
528 if (toddr_src_get() == FRHDMIRX) {
529 src = FRHDMIRX;
530
531 aml_update_tdmin_src(p_tdm->actrl,
532 p_tdm->id,
533 HDMIRX_I2S);
534 } else if (p_tdm->chipinfo
535 && p_tdm->chipinfo->adc_fn
536 && p_tdm->acodec_adc)
537 aml_update_tdmin_src(p_tdm->actrl,
538 p_tdm->id,
539 ACODEC_ADC);
540
541 pr_info("%s Expected toddr src:%s\n",
542 __func__,
543 toddr_src_get_str(src));
544
545 fmt.type = toddr_type;
546 fmt.msb = 31;
547 fmt.lsb = lsb;
548 fmt.endian = 0;
549 fmt.bit_depth = bit_depth;
550 fmt.ch_num = runtime->channels;
551 fmt.rate = runtime->rate;
552 aml_toddr_select_src(to, src);
553 aml_toddr_set_format(to, &fmt);
554 aml_toddr_set_fifos(to, 0x40);
555 }
556
557 return 0;
558}
559
560static int aml_dai_tdm_trigger(struct snd_pcm_substream *substream, int cmd,
561 struct snd_soc_dai *cpu_dai)
562{
563 struct aml_tdm *p_tdm = snd_soc_dai_get_drvdata(cpu_dai);
564
565 /* share buffer trigger */
566 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
567 && p_tdm->chipinfo
568 && p_tdm->chipinfo->same_src_fn
569 && (p_tdm->samesource_sel >= 0)
570 && (aml_check_sharebuffer_valid(p_tdm->fddr,
571 p_tdm->samesource_sel))
572 )
573 sharebuffer_trigger(cmd,
574 p_tdm->samesource_sel,
575 p_tdm->chipinfo->same_src_spdif_reen);
576
577 switch (cmd) {
578 case SNDRV_PCM_TRIGGER_START:
579 case SNDRV_PCM_TRIGGER_RESUME:
580 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
581
582 if ((substream->stream == SNDRV_PCM_STREAM_CAPTURE)
583 && vad_tdm_is_running(p_tdm->id)
584 && pm_audio_is_suspend()) {
585 pm_audio_set_suspend(false);
586 /* VAD switch to alsa buffer */
587 vad_update_buffer(0);
588 break;
589 }
590
591 /* reset fifo here.
592 * If not, xrun will cause channel mapping mismatch
593 */
594 aml_tdm_fifo_reset(p_tdm->actrl, substream->stream, p_tdm->id);
595
596 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
597 dev_info(substream->pcm->card->dev, "tdm playback enable\n");
598 aml_frddr_enable(p_tdm->fddr, 1);
599 aml_tdm_enable(p_tdm->actrl,
600 substream->stream, p_tdm->id, true);
601 udelay(100);
602 aml_tdm_mute_playback(p_tdm->actrl, p_tdm->id, false);
603 if (p_tdm->chipinfo
604 && p_tdm->chipinfo->same_src_fn
605 && (p_tdm->samesource_sel >= 0)
606 && (aml_check_sharebuffer_valid(p_tdm->fddr,
607 p_tdm->samesource_sel))) {
608 aml_spdifout_mute_without_actrl(0, false);
609 }
610 } else {
611 dev_info(substream->pcm->card->dev, "tdm capture enable\n");
612 aml_toddr_enable(p_tdm->tddr, 1);
613 aml_tdm_enable(p_tdm->actrl,
614 substream->stream, p_tdm->id, true);
615 }
616 break;
617 case SNDRV_PCM_TRIGGER_STOP:
618 case SNDRV_PCM_TRIGGER_SUSPEND:
619 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
620 if ((substream->stream == SNDRV_PCM_STREAM_CAPTURE)
621 && vad_tdm_is_running(p_tdm->id)
622 && pm_audio_is_suspend()) {
623 /* switch to VAD buffer */
624 vad_update_buffer(1);
625 break;
626 }
627
628 aml_tdm_enable(p_tdm->actrl,
629 substream->stream, p_tdm->id, false);
630
631 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
632 dev_info(substream->pcm->card->dev, "tdm playback stop\n");
633 aml_frddr_enable(p_tdm->fddr, 0);
634 aml_tdm_mute_playback(p_tdm->actrl, p_tdm->id, true);
635 if (p_tdm->chipinfo
636 && p_tdm->chipinfo->same_src_fn
637 && (p_tdm->samesource_sel >= 0)
638 && (aml_check_sharebuffer_valid(p_tdm->fddr,
639 p_tdm->samesource_sel))) {
640 aml_spdifout_mute_without_actrl(0, true);
641 }
642 } else {
643 dev_info(substream->pcm->card->dev, "tdm capture stop\n");
644 aml_toddr_enable(p_tdm->tddr, 0);
645 }
646 break;
647 default:
648 return -EINVAL;
649 }
650
651 return 0;
652}
653
654static int pcm_setting_init(struct pcm_setting *setting, unsigned int rate,
655 unsigned int channels)
656{
657 unsigned int ratio = 0;
658
659 setting->lrclk = rate;
660 setting->bclk_lrclk_ratio = setting->slots * setting->slot_width;
661 setting->bclk = setting->lrclk * setting->bclk_lrclk_ratio;
662
663 /* calculate mclk */
664 if (setting->pcm_mode == SND_SOC_DAIFMT_DSP_A ||
665 setting->pcm_mode == SND_SOC_DAIFMT_DSP_B) {
666 /* for some TDM codec, mclk limites */
667 ratio = 2;
668 } else {
669 ratio = 4;
670 }
671 setting->sysclk_bclk_ratio = ratio;
672 setting->sysclk = ratio * setting->bclk;
673
674 return 0;
675}
676static int aml_tdm_set_lanes(struct aml_tdm *p_tdm,
677 unsigned int channels, int stream)
678{
679 struct pcm_setting *setting = &p_tdm->setting;
680 unsigned int lanes, swap_val;
681 unsigned int lane_mask;
682 unsigned int set_num = 0;
683 unsigned int i;
684
685 pr_debug("asoc channels:%d, slots:%d\n", channels, setting->slots);
686
687 swap_val = 0;
688 // calc lanes by channels and slots
689 lanes = (channels - 1) / setting->slots + 1;
690 if (lanes > 4) {
691 pr_err("lanes setting error\n");
692 return -EINVAL;
693 }
694
695 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
696 // set lanes mask acordingly
697 if (p_tdm->chipinfo
698 && p_tdm->chipinfo->oe_fn
699 && p_tdm->setting.lane_oe_mask_out)
700 lane_mask = setting->lane_oe_mask_out;
701 else
702 lane_mask = setting->lane_mask_out;
703 for (i = 0; i < 4; i++) {
704 if (((1 << i) & lane_mask) && lanes) {
705 aml_tdm_set_channel_mask(p_tdm->actrl,
706 stream, p_tdm->id, i, setting->tx_mask);
707 lanes--;
708 }
709 }
710 swap_val = 0x76543210;
711 aml_tdm_set_lane_channel_swap(p_tdm->actrl,
712 stream, p_tdm->id, swap_val);
713 } else {
714 if (p_tdm->chipinfo
715 && p_tdm->chipinfo->oe_fn
716 && p_tdm->setting.lane_oe_mask_in)
717 lane_mask = setting->lane_oe_mask_in;
718 else
719 lane_mask = setting->lane_mask_in;
720
721 for (i = 0; i < 4; i++) {
722 if (i < lanes)
723 aml_tdm_set_channel_mask(p_tdm->actrl,
724 stream, p_tdm->id, i, setting->rx_mask);
725 if ((1 << i) & lane_mask) {
726 // each lane only L/R masked
727 pr_info("tdmin set lane %d\n", i);
728 swap_val |= (i * 2) << (set_num++ * 4);
729 swap_val |= (i * 2 + 1) << (set_num++ * 4);
730 }
731 }
732
733 aml_tdm_set_lane_channel_swap(p_tdm->actrl,
734 stream, p_tdm->id, swap_val);
735 }
736
737
738 return 0;
739}
740
741static int aml_tdm_set_clk_pad(struct aml_tdm *p_tdm)
742{
743 unsigned int mpad, mclk_sel;
744
745 // TODO: update pad
746 if (p_tdm->id >= 1) {
747 mpad = p_tdm->id - 1;
748 mclk_sel = p_tdm->id;
749 } else {
750 mpad = 0;
751 mclk_sel = 0;
752 }
753
754 /* clk pad */
755 aml_tdm_clk_pad_select(p_tdm->actrl, mpad, mclk_sel,
756 p_tdm->id, p_tdm->clk_sel);
757
758 return 0;
759}
760
761static int aml_dai_tdm_hw_params(struct snd_pcm_substream *substream,
762 struct snd_pcm_hw_params *params,
763 struct snd_soc_dai *cpu_dai)
764{
765 struct aml_tdm *p_tdm = snd_soc_dai_get_drvdata(cpu_dai);
766 struct pcm_setting *setting = &p_tdm->setting;
767 unsigned int rate = params_rate(params);
768 unsigned int channels = params_channels(params);
769 int ret;
770
771 ret = pcm_setting_init(setting, rate, channels);
772 if (ret)
773 return ret;
774
775 dump_pcm_setting(setting);
776
777 /* set pcm dai hw params */
778 // TODO: add clk_id
779 snd_soc_dai_set_sysclk(cpu_dai,
780 0, setting->sysclk, SND_SOC_CLOCK_OUT);
781 ret = snd_soc_dai_set_clkdiv(cpu_dai, 0, setting->sysclk_bclk_ratio);
782 if (ret)
783 return ret;
784
785 ret = snd_soc_dai_set_bclk_ratio(cpu_dai, setting->bclk_lrclk_ratio);
786 if (ret)
787 return ret;
788
789 ret = aml_tdm_set_lanes(p_tdm, channels, substream->stream);
790 if (ret)
791 return ret;
792
793 if (p_tdm->chipinfo && p_tdm->chipinfo->clk_pad_ctl) {
794 ret = aml_tdm_set_clk_pad(p_tdm);
795 if (ret)
796 return ret;
797 }
798
799 /* Must enabe channel number for VAD */
800 if ((substream->stream == SNDRV_PCM_STREAM_CAPTURE)
801 && (vad_tdm_is_running(p_tdm->id)))
802 tdmin_set_chnum_en(p_tdm->actrl, p_tdm->id, true);
803
804 /* share buffer trigger */
805 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
806 && p_tdm->chipinfo
807 && (p_tdm->chipinfo->same_src_fn)
808 && (p_tdm->samesource_sel >= 0)
809 && (aml_check_sharebuffer_valid(p_tdm->fddr,
810 p_tdm->samesource_sel))) {
811 int mux = 0, ratio = 0;
812
813 sharebuffer_get_mclk_fs_ratio(p_tdm->samesource_sel,
814 &mux, &ratio);
815 pr_info("samesource sysclk:%d\n", rate * ratio * mux);
816 if (!IS_ERR(p_tdm->samesrc_srcpll)) {
817 clk_set_rate(p_tdm->samesrc_srcpll,
818 rate * ratio * mux);
819 clk_prepare_enable(p_tdm->samesrc_srcpll);
820 }
821 if (!IS_ERR(p_tdm->samesrc_clk)) {
822 clk_set_rate(p_tdm->samesrc_clk,
823 rate * ratio);
824 clk_prepare_enable(p_tdm->samesrc_clk);
825 }
826 }
827
828 if (!p_tdm->contns_clk && !IS_ERR(p_tdm->mclk)) {
829 pr_debug("%s(), enable mclk for %s", __func__, cpu_dai->name);
830 ret = clk_prepare_enable(p_tdm->mclk);
831 if (ret) {
832 pr_err("Can't enable mclk: %d\n", ret);
833 return ret;
834 }
835 }
836
837 return 0;
838}
839
840static int aml_dai_tdm_hw_free(struct snd_pcm_substream *substream,
841 struct snd_soc_dai *cpu_dai)
842{
843 struct aml_tdm *p_tdm = snd_soc_dai_get_drvdata(cpu_dai);
844 struct frddr *fr = p_tdm->fddr;
845 int i;
846
847 for (i = 0; i < 4; i++)
848 aml_tdm_set_channel_mask(p_tdm->actrl,
849 substream->stream, p_tdm->id, i, 0);
850
851 /* Disable channel number for VAD */
852 if ((substream->stream == SNDRV_PCM_STREAM_CAPTURE)
853 && (vad_tdm_is_running(p_tdm->id)))
854 tdmin_set_chnum_en(p_tdm->actrl, p_tdm->id, false);
855
856 /* share buffer free */
857 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
858 && p_tdm->chipinfo
859 && p_tdm->chipinfo->same_src_fn
860 && (p_tdm->samesource_sel >= 0)
861 && fr
862 && (aml_check_sharebuffer_valid(fr, p_tdm->samesource_sel))) {
863 sharebuffer_free(substream,
864 fr, p_tdm->samesource_sel);
865 }
866
867 /* disable clock and gate */
868 if (!p_tdm->contns_clk && !IS_ERR(p_tdm->mclk)) {
869 pr_info("%s(), disable mclk for %s", __func__, cpu_dai->name);
870 clk_disable_unprepare(p_tdm->mclk);
871 }
872
873 return 0;
874}
875
876static int aml_dai_set_tdm_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
877{
878 struct aml_tdm *p_tdm = snd_soc_dai_get_drvdata(cpu_dai);
879
880 pr_debug("asoc aml_dai_set_tdm_fmt, %#x, %p, id(%d), clksel(%d)\n",
881 fmt, p_tdm, p_tdm->id, p_tdm->clk_sel);
882 if (p_tdm->last_fmt == fmt) {
883 pr_debug("%s(), fmt not change\n", __func__);
884 goto capture;
885 } else
886 p_tdm->last_fmt = fmt;
887
888 switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
889 case SND_SOC_DAIFMT_CONT:
890 p_tdm->contns_clk = true;
891 break;
892 case SND_SOC_DAIFMT_GATED:
893 p_tdm->contns_clk = false;
894 break;
895 default:
896 return -EINVAL;
897 }
898
899 if (p_tdm->chipinfo)
900 p_tdm->setting.sclk_ws_inv = p_tdm->chipinfo->sclk_ws_inv;
901
902 aml_tdm_set_format(p_tdm->actrl,
903 &(p_tdm->setting), p_tdm->clk_sel, p_tdm->id, fmt,
904 1, 1);
905
906capture:
907 /* update skew for ACODEC_ADC */
908 if (cpu_dai->capture_active
909 && p_tdm->chipinfo
910 && p_tdm->chipinfo->adc_fn
911 && p_tdm->acodec_adc){
912 aml_update_tdmin_skew(p_tdm->actrl, p_tdm->id, 4);
913 aml_update_tdmin_rev_ws(p_tdm->actrl, p_tdm->id, 0);
914 }
915
916 return 0;
917}
918
919/* mpll clk range from 5M to 500M */
920#define AML_MPLL_FREQ_MIN 5000000
921static unsigned int aml_mpll_mclk_ratio(unsigned int freq)
922{
923 unsigned int i, ratio = 2;
924 unsigned int mpll_freq = 0;
925
926 for (i = 1; i < 15; i++) {
927 ratio = 1 << i;
928 mpll_freq = freq * ratio;
929
930 if (mpll_freq > AML_MPLL_FREQ_MIN)
931 break;
932 }
933
934 return ratio;
935}
936
937static int aml_dai_set_tdm_sysclk(struct snd_soc_dai *cpu_dai,
938 int clk_id, unsigned int freq, int dir)
939{
940 struct aml_tdm *p_tdm = snd_soc_dai_get_drvdata(cpu_dai);
941 unsigned int ratio = aml_mpll_mclk_ratio(freq);
942 unsigned int mpll_freq = 0;
943
944 p_tdm->setting.sysclk = freq;
945
946#ifdef __PTM_TDM_CLK__
947 if (p_tdm->id == 0)
948 ratio = 14;
949 else if (p_tdm->id == 1)
950 ratio = 18 * 2;
951 else if (p_tdm->id == 2)
952 ratio = 20;
953#endif
954
955 mpll_freq = freq * ratio;
956 if (mpll_freq != p_tdm->last_mpll_freq) {
957 clk_set_rate(p_tdm->clk, mpll_freq);
958 p_tdm->last_mpll_freq = mpll_freq;
959 } else {
960 pr_debug("%s(), mpll no change, keep clk\n", __func__);
961 }
962
963 if (freq != p_tdm->last_mclk_freq) {
964 clk_set_rate(p_tdm->mclk, freq);
965 p_tdm->last_mclk_freq = freq;
966 } else {
967 pr_debug("%s(), mclk no change, keep clk\n", __func__);
968 }
969
970 pr_debug("set mclk:%d, mpll:%d, get mclk:%lu, mpll:%lu\n",
971 freq,
972 freq * ratio,
973 clk_get_rate(p_tdm->mclk),
974 clk_get_rate(p_tdm->clk));
975
976 return 0;
977}
978
979static int aml_dai_set_bclk_ratio(struct snd_soc_dai *cpu_dai,
980 unsigned int ratio)
981{
982 struct aml_tdm *p_tdm = snd_soc_dai_get_drvdata(cpu_dai);
983 unsigned int bclk_ratio, lrclk_hi;
984
985 p_tdm->setting.bclk_lrclk_ratio = ratio;
986 bclk_ratio = ratio - 1;
987 lrclk_hi = 0;
988
989 if (p_tdm->setting.pcm_mode == SND_SOC_DAIFMT_I2S ||
990 p_tdm->setting.pcm_mode == SND_SOC_DAIFMT_LEFT_J) {
991 pr_debug("aml_dai_set_bclk_ratio, select I2S mode\n");
992 lrclk_hi = bclk_ratio / 2;
993 } else {
994 pr_debug("aml_dai_set_bclk_ratio, select TDM mode\n");
995 }
996 aml_tdm_set_bclk_ratio(p_tdm->actrl,
997 p_tdm->clk_sel, lrclk_hi, bclk_ratio);
998
999 return 0;
1000}
1001
1002static int aml_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
1003 int div_id, int div)
1004{
1005 struct aml_tdm *p_tdm = snd_soc_dai_get_drvdata(cpu_dai);
1006 unsigned int mclk_ratio;
1007
1008 pr_debug("aml_dai_set_clkdiv, div %d, clksel(%d)\n",
1009 div, p_tdm->clk_sel);
1010
1011 p_tdm->setting.sysclk_bclk_ratio = div;
1012 mclk_ratio = div - 1;
1013 aml_tdm_set_lrclkdiv(p_tdm->actrl, p_tdm->clk_sel, mclk_ratio);
1014
1015 return 0;
1016}
1017
1018static int aml_dai_set_tdm_slot(struct snd_soc_dai *cpu_dai,
1019 unsigned int tx_mask, unsigned int rx_mask,
1020 int slots, int slot_width)
1021{
1022 struct aml_tdm *p_tdm = snd_soc_dai_get_drvdata(cpu_dai);
1023 struct snd_soc_dai_driver *drv = cpu_dai->driver;
1024 unsigned int lanes_out_cnt = 0, lanes_in_cnt = 0;
1025 unsigned int lanes_oe_out_cnt = 0, lanes_oe_in_cnt = 0;
1026 unsigned int force_oe = 0, oe_val = 0;
1027 unsigned int lanes_lb_cnt = 0;
1028 int out_lanes, in_lanes;
1029 int in_src = -1;
1030
1031 lanes_out_cnt = pop_count(p_tdm->setting.lane_mask_out);
1032 lanes_in_cnt = pop_count(p_tdm->setting.lane_mask_in);
1033 lanes_oe_out_cnt = pop_count(p_tdm->setting.lane_oe_mask_out);
1034 lanes_oe_in_cnt = pop_count(p_tdm->setting.lane_oe_mask_in);
1035 lanes_lb_cnt = pop_count(p_tdm->setting.lane_lb_mask_in);
1036
1037 pr_debug("%s(), txmask(%#x), rxmask(%#x)\n",
1038 __func__, tx_mask, rx_mask);
1039 pr_debug("\tlanes_out_cnt(%d), lanes_in_cnt(%d)\n",
1040 lanes_out_cnt, lanes_in_cnt);
1041 pr_debug("\tlanes_oe_out_cnt(%d), lanes_oe_in_cnt(%d)\n",
1042 lanes_oe_out_cnt, lanes_oe_in_cnt);
1043 pr_debug("\tlanes_lb_cnt(%d)\n",
1044 lanes_lb_cnt);
1045 pr_debug("\tslots(%d), slot_width(%d)\n",
1046 slots, slot_width);
1047 p_tdm->setting.tx_mask = tx_mask;
1048 p_tdm->setting.rx_mask = rx_mask;
1049 p_tdm->setting.slots = slots;
1050 p_tdm->setting.slot_width = slot_width;
1051
1052 if (p_tdm->setting.lane_mask_in
1053 & p_tdm->setting.lane_lb_mask_in)
1054 pr_err("pin(%x) should be selected for only one usage\n",
1055 p_tdm->setting.lane_mask_in
1056 & p_tdm->setting.lane_lb_mask_in);
1057
1058 if (p_tdm->chipinfo && p_tdm->chipinfo->oe_fn) {
1059 if (p_tdm->setting.lane_mask_out
1060 & p_tdm->setting.lane_oe_mask_out)
1061 pr_err("pin(%x) should be selected for only one usage\n",
1062 p_tdm->setting.lane_mask_out
1063 & p_tdm->setting.lane_oe_mask_out);
1064
1065 if ((p_tdm->setting.lane_mask_in
1066 & p_tdm->setting.lane_oe_mask_in)
1067 || (p_tdm->setting.lane_lb_mask_in
1068 & p_tdm->setting.lane_oe_mask_in))
1069 pr_err("pin(%x:%x) should be selected for only one usage\n",
1070 p_tdm->setting.lane_mask_in
1071 & p_tdm->setting.lane_oe_mask_in,
1072 p_tdm->setting.lane_lb_mask_in
1073 & p_tdm->setting.lane_oe_mask_in);
1074
1075 if (lanes_oe_out_cnt) {
1076 force_oe = p_tdm->setting.lane_oe_mask_out;
1077 oe_val = p_tdm->setting.lane_oe_mask_out;
1078 }
1079
1080 if (lanes_lb_cnt) {
1081 in_src = p_tdm->id + 6;
1082 if (in_src > 7) {
1083 pr_err("unknown src(%d) for tdmin\n", in_src);
1084 return -EINVAL;
1085 }
1086 }
1087 if (lanes_oe_in_cnt)
1088 in_src = p_tdm->id + 3;
1089 if (lanes_in_cnt)
1090 in_src = p_tdm->id;
1091 } else {
1092 if (lanes_lb_cnt)
1093 in_src = p_tdm->id + 3;
1094 if (lanes_in_cnt && lanes_in_cnt <= 4)
1095 in_src = p_tdm->id;
1096 if (in_src > 5) {
1097 pr_err("unknown src(%d) for tdmin\n", in_src);
1098 return -EINVAL;
1099 }
1100 }
1101
1102 out_lanes = lanes_out_cnt + lanes_oe_out_cnt;
1103 in_lanes = lanes_in_cnt + lanes_oe_in_cnt + lanes_lb_cnt;
1104
1105 if (p_tdm->chipinfo
1106 && p_tdm->chipinfo->adc_fn
1107 && p_tdm->acodec_adc) {
1108 in_src = ACODEC_ADC;
1109 }
1110
1111 if (in_lanes >= 0 && in_lanes <= 4)
1112 aml_tdm_set_slot_in(p_tdm->actrl,
1113 p_tdm->id, in_src, slot_width);
1114
1115 if (out_lanes >= 0 && out_lanes <= 4)
1116 aml_tdm_set_slot_out(p_tdm->actrl,
1117 p_tdm->id, slots, slot_width,
1118 force_oe, oe_val);
1119
1120 /* constrains hw channels_max by DTS configs */
1121 drv->playback.channels_max = slots * out_lanes;
1122 drv->capture.channels_max = slots * in_lanes;
1123
1124 return 0;
1125}
1126
1127static int aml_dai_tdm_probe(struct snd_soc_dai *cpu_dai)
1128{
1129 int ret = 0;
1130 struct aml_tdm *p_tdm = snd_soc_dai_get_drvdata(cpu_dai);
1131
1132 ret = snd_soc_add_dai_controls(cpu_dai, snd_tdm_controls,
1133 ARRAY_SIZE(snd_tdm_controls));
1134 if (ret < 0)
1135 pr_err("%s, failed add snd spdif controls\n", __func__);
1136
1137 /* config ddr arb */
1138 aml_tdm_arb_config(p_tdm->actrl);
1139
1140 return 0;
1141}
1142
1143static int aml_dai_tdm_remove(struct snd_soc_dai *cpu_dai)
1144{
1145
1146 return 0;
1147}
1148
1149static int aml_dai_tdm_mute_stream(struct snd_soc_dai *cpu_dai,
1150 int mute, int stream)
1151{
1152 struct aml_tdm *p_tdm = snd_soc_dai_get_drvdata(cpu_dai);
1153
1154 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1155 pr_debug("tdm playback mute: %d\n", mute);
1156 //aml_tdm_mute_playback(p_tdm->actrl, p_tdm->id, mute);
1157 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
1158 pr_debug("tdm capture mute: %d\n", mute);
1159 aml_tdm_mute_capture(p_tdm->actrl, p_tdm->id, mute);
1160 }
1161 return 0;
1162}
1163
1164static struct snd_soc_dai_ops aml_dai_tdm_ops = {
1165 .prepare = aml_dai_tdm_prepare,
1166 .trigger = aml_dai_tdm_trigger,
1167 .hw_params = aml_dai_tdm_hw_params,
1168 .hw_free = aml_dai_tdm_hw_free,
1169 .set_fmt = aml_dai_set_tdm_fmt,
1170 .set_sysclk = aml_dai_set_tdm_sysclk,
1171 .set_bclk_ratio = aml_dai_set_bclk_ratio,
1172 .set_clkdiv = aml_dai_set_clkdiv,
1173 .set_tdm_slot = aml_dai_set_tdm_slot,
1174 .mute_stream = aml_dai_tdm_mute_stream,
1175};
1176
1177#define AML_DAI_TDM_RATES (SNDRV_PCM_RATE_8000_192000)
1178#define AML_DAI_TDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1179 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1180
1181static struct snd_soc_dai_driver aml_tdm_dai[] = {
1182 {
1183 .name = "TDM-A",
1184 .id = 1,
1185 .probe = aml_dai_tdm_probe,
1186 .remove = aml_dai_tdm_remove,
1187 .playback = {
1188 .channels_min = 1,
1189 .channels_max = 32,
1190 .rates = AML_DAI_TDM_RATES,
1191 .formats = AML_DAI_TDM_FORMATS,
1192 },
1193 .capture = {
1194 .channels_min = 1,
1195 .channels_max = 32,
1196 .rates = AML_DAI_TDM_RATES,
1197 .formats = AML_DAI_TDM_FORMATS,
1198 },
1199 .ops = &aml_dai_tdm_ops,
1200 .symmetric_rates = 1,
1201 },
1202 {
1203 .name = "TDM-B",
1204 .id = 2,
1205 .probe = aml_dai_tdm_probe,
1206 .remove = aml_dai_tdm_remove,
1207 .playback = {
1208 .channels_min = 1,
1209 .channels_max = 8,
1210 .rates = AML_DAI_TDM_RATES,
1211 .formats = AML_DAI_TDM_FORMATS,
1212 },
1213 .capture = {
1214 .channels_min = 1,
1215 .channels_max = 32,
1216 .rates = AML_DAI_TDM_RATES,
1217 .formats = AML_DAI_TDM_FORMATS,
1218 },
1219 .ops = &aml_dai_tdm_ops,
1220 .symmetric_rates = 1,
1221 },
1222 {
1223 .name = "TDM-C",
1224 .id = 3,
1225 .probe = aml_dai_tdm_probe,
1226 .remove = aml_dai_tdm_remove,
1227 .playback = {
1228 .channels_min = 1,
1229 .channels_max = 8,
1230 .rates = AML_DAI_TDM_RATES,
1231 .formats = AML_DAI_TDM_FORMATS,
1232 },
1233 .capture = {
1234 .channels_min = 1,
1235 .channels_max = 32,
1236 .rates = AML_DAI_TDM_RATES,
1237 .formats = AML_DAI_TDM_FORMATS,
1238 },
1239 .ops = &aml_dai_tdm_ops,
1240 .symmetric_rates = 1,
1241 },
1242};
1243
1244static const struct snd_soc_component_driver aml_tdm_component = {
1245 .name = DRV_NAME,
1246};
1247
1248struct tdm_chipinfo axg_tdma_chipinfo = {
1249 .id = TDM_A,
1250};
1251
1252struct tdm_chipinfo axg_tdmb_chipinfo = {
1253 .id = TDM_B,
1254};
1255
1256struct tdm_chipinfo axg_tdmc_chipinfo = {
1257 .id = TDM_C,
1258};
1259
1260struct tdm_chipinfo g12a_tdma_chipinfo = {
1261 .id = TDM_A,
1262 .sclk_ws_inv = true,
1263 .oe_fn = true,
1264 .clk_pad_ctl = true,
1265 .same_src_fn = true,
1266};
1267
1268struct tdm_chipinfo g12a_tdmb_chipinfo = {
1269 .id = TDM_B,
1270 .sclk_ws_inv = true,
1271 .oe_fn = true,
1272 .clk_pad_ctl = true,
1273 .same_src_fn = true,
1274};
1275
1276struct tdm_chipinfo g12a_tdmc_chipinfo = {
1277 .id = TDM_C,
1278 .sclk_ws_inv = true,
1279 .oe_fn = true,
1280 .clk_pad_ctl = true,
1281 .same_src_fn = true,
1282};
1283
1284struct tdm_chipinfo tl1_tdma_chipinfo = {
1285 .id = TDM_A,
1286 .sclk_ws_inv = true,
1287 .oe_fn = true,
1288 .clk_pad_ctl = true,
1289 .same_src_fn = true,
1290 .adc_fn = true,
1291 .same_src_spdif_reen = true,
1292};
1293
1294struct tdm_chipinfo tl1_tdmb_chipinfo = {
1295 .id = TDM_B,
1296 .sclk_ws_inv = true,
1297 .oe_fn = true,
1298 .clk_pad_ctl = true,
1299 .same_src_fn = true,
1300 .adc_fn = true,
1301 .same_src_spdif_reen = true,
1302};
1303
1304struct tdm_chipinfo tl1_tdmc_chipinfo = {
1305 .id = TDM_C,
1306 .sclk_ws_inv = true,
1307 .oe_fn = true,
1308 .clk_pad_ctl = true,
1309 .same_src_fn = true,
1310 .adc_fn = true,
1311 .same_src_spdif_reen = true,
1312};
1313
1314static const struct of_device_id aml_tdm_device_id[] = {
1315 {
1316 .compatible = "amlogic, axg-snd-tdma",
1317 .data = &axg_tdma_chipinfo,
1318 },
1319 {
1320 .compatible = "amlogic, axg-snd-tdmb",
1321 .data = &axg_tdmb_chipinfo,
1322 },
1323 {
1324 .compatible = "amlogic, axg-snd-tdmc",
1325 .data = &axg_tdmc_chipinfo,
1326 },
1327 {
1328 .compatible = "amlogic, g12a-snd-tdma",
1329 .data = &g12a_tdma_chipinfo,
1330 },
1331 {
1332 .compatible = "amlogic, g12a-snd-tdmb",
1333 .data = &g12a_tdmb_chipinfo,
1334 },
1335 {
1336 .compatible = "amlogic, g12a-snd-tdmc",
1337 .data = &g12a_tdmc_chipinfo,
1338 },
1339 {
1340 .compatible = "amlogic, tl1-snd-tdma",
1341 .data = &tl1_tdma_chipinfo,
1342 },
1343 {
1344 .compatible = "amlogic, tl1-snd-tdmb",
1345 .data = &tl1_tdmb_chipinfo,
1346 },
1347 {
1348 .compatible = "amlogic, tl1-snd-tdmc",
1349 .data = &tl1_tdmc_chipinfo,
1350 },
1351 {},
1352};
1353MODULE_DEVICE_TABLE(of, aml_tdm_device_id);
1354
1355static int aml_tdm_platform_probe(struct platform_device *pdev)
1356{
1357 struct device_node *node = pdev->dev.of_node;
1358 struct device_node *node_prt = NULL;
1359 struct platform_device *pdev_parent;
1360 struct device *dev = &pdev->dev;
1361 struct aml_audio_controller *actrl = NULL;
1362 struct aml_tdm *p_tdm = NULL;
1363 struct tdm_chipinfo *p_chipinfo;
1364 int ret = 0;
1365
1366 p_tdm = devm_kzalloc(dev, sizeof(struct aml_tdm), GFP_KERNEL);
1367 if (!p_tdm)
1368 return -ENOMEM;
1369
1370 /* match data */
1371 p_chipinfo = (struct tdm_chipinfo *)
1372 of_device_get_match_data(dev);
1373 if (!p_chipinfo) {
1374 dev_warn_once(dev, "check whether to update tdm chipinfo\n");
1375 return -ENOMEM;
1376 }
1377 p_tdm->chipinfo = p_chipinfo;
1378 p_tdm->id = p_chipinfo->id;
1379 pr_info("%s, tdm ID = %u\n", __func__, p_tdm->id);
1380
1381 /* get audio controller */
1382 node_prt = of_get_parent(node);
1383 if (node_prt == NULL)
1384 return -ENXIO;
1385
1386 pdev_parent = of_find_device_by_node(node_prt);
1387 of_node_put(node_prt);
1388 actrl = (struct aml_audio_controller *)
1389 platform_get_drvdata(pdev_parent);
1390 p_tdm->actrl = actrl;
1391
1392 /* get tdm mclk sel configs */
1393 ret = of_property_read_u32(node, "dai-tdm-clk-sel",
1394 &p_tdm->clk_sel);
1395 if (ret < 0) {
1396 dev_err(&pdev->dev, "Can't retrieve dai-tdm-clk-sel\n");
1397 return -ENXIO;
1398 }
1399
1400 /* default no same source */
1401 if (p_tdm->chipinfo &&
1402 p_tdm->chipinfo->same_src_fn) {
1403
1404 ret = of_property_read_u32(node, "samesource_sel",
1405 &p_tdm->samesource_sel);
1406 if (ret < 0)
1407 p_tdm->samesource_sel = -1;
1408 else {
1409 p_tdm->samesrc_srcpll = devm_clk_get(&pdev->dev,
1410 "samesource_srcpll");
1411 if (IS_ERR(p_tdm->samesrc_srcpll)) {
1412 dev_err(&pdev->dev,
1413 "Can't retrieve samesrc_srcpll clock\n");
1414 return PTR_ERR(p_tdm->samesrc_srcpll);
1415 }
1416 p_tdm->samesrc_clk = devm_clk_get(&pdev->dev,
1417 "samesource_clk");
1418 if (IS_ERR(p_tdm->samesrc_clk)) {
1419 dev_err(&pdev->dev,
1420 "Can't retrieve samesrc_clk clock\n");
1421 return PTR_ERR(p_tdm->samesrc_clk);
1422 }
1423 ret = clk_set_parent(p_tdm->samesrc_clk,
1424 p_tdm->samesrc_srcpll);
1425 if (ret) {
1426 dev_err(dev, "can't set samesource clock\n");
1427 return ret;
1428 }
1429 pr_info("TDM id %d samesource_sel:%d\n",
1430 p_tdm->id,
1431 p_tdm->samesource_sel);
1432 }
1433 }
1434 /* default no acodec_adc */
1435 if (p_tdm->chipinfo &&
1436 p_tdm->chipinfo->adc_fn) {
1437
1438 ret = of_property_read_u32(node, "acodec_adc",
1439 &p_tdm->acodec_adc);
1440 if (ret < 0)
1441 p_tdm->acodec_adc = 0;
1442 else
1443 pr_info("TDM id %d supports ACODEC_ADC\n", p_tdm->id);
1444 }
1445
1446 ret = of_property_read_u32(node, "i2s2hdmi",
1447 &p_tdm->i2s2hdmitx);
1448 if (ret < 0)
1449 p_tdm->i2s2hdmitx = 0;
1450 pr_info("TDM id %d i2s2hdmi:%d\n",
1451 p_tdm->id,
1452 p_tdm->i2s2hdmitx);
1453
1454 /* get tdm lanes info. if not, set to default 0 */
1455 ret = of_parse_tdm_lane_slot_in(node,
1456 &p_tdm->setting.lane_mask_in);
1457 if (ret < 0)
1458 p_tdm->setting.lane_mask_in = 0x0;
1459
1460 ret = of_parse_tdm_lane_slot_out(node,
1461 &p_tdm->setting.lane_mask_out);
1462 if (ret < 0)
1463 p_tdm->setting.lane_mask_out = 0x0;
1464
1465 /* get tdm lanes oe info. if not, set to default 0 */
1466 ret = of_parse_tdm_lane_oe_slot_in(node,
1467 &p_tdm->setting.lane_oe_mask_in);
1468 if (ret < 0)
1469 p_tdm->setting.lane_oe_mask_in = 0x0;
1470
1471 ret = of_parse_tdm_lane_oe_slot_out(node,
1472 &p_tdm->setting.lane_oe_mask_out);
1473 if (ret < 0)
1474 p_tdm->setting.lane_oe_mask_out = 0x0;
1475
1476 /* get tdm lanes lb info. if not, set to default 0 */
1477 ret = of_parse_tdm_lane_lb_slot_in(node,
1478 &p_tdm->setting.lane_lb_mask_in);
1479 if (ret < 0)
1480 p_tdm->setting.lane_lb_mask_in = 0x0;
1481
1482 p_tdm->clk = devm_clk_get(&pdev->dev, "clk_srcpll");
1483 if (IS_ERR(p_tdm->clk)) {
1484 dev_err(&pdev->dev, "Can't retrieve mpll2 clock\n");
1485 return PTR_ERR(p_tdm->clk);
1486 }
1487
1488 p_tdm->mclk = devm_clk_get(&pdev->dev, "mclk");
1489 if (IS_ERR(p_tdm->mclk)) {
1490 dev_err(&pdev->dev, "Can't retrieve mclk\n");
1491 return PTR_ERR(p_tdm->mclk);
1492 }
1493
1494 ret = clk_set_parent(p_tdm->mclk, p_tdm->clk);
1495 if (ret) {
1496 dev_err(dev, "can't set tdm parent clock\n");
1497 return ret;
1498 }
1499
1500 /* complete mclk for tdm */
1501 if (get_meson_cpu_version(MESON_CPU_VERSION_LVL_MINOR) == 0xa)
1502 meson_clk_measure((1<<16) | 0x67);
1503
1504 p_tdm->pin_ctl = devm_pinctrl_get_select(dev, "tdm_pins");
1505 if (IS_ERR(p_tdm->pin_ctl)) {
1506 dev_info(dev, "aml_tdm_get_pins error!\n");
1507 /*return PTR_ERR(p_tdm->pin_ctl);*/
1508 }
1509
1510 p_tdm->dev = dev;
1511 dev_set_drvdata(dev, p_tdm);
1512
1513 ret = devm_snd_soc_register_component(dev, &aml_tdm_component,
1514 &aml_tdm_dai[p_tdm->id], 1);
1515 if (ret) {
1516 dev_err(dev, "devm_snd_soc_register_component failed\n");
1517 return ret;
1518 }
1519
1520 return devm_snd_soc_register_platform(dev, &aml_tdm_platform);
1521}
1522
1523static int aml_tdm_platform_suspend(struct platform_device *pdev,
1524 pm_message_t state)
1525{
1526 return 0;
1527}
1528static int aml_tdm_platform_resume(struct platform_device *pdev)
1529{
1530 /* complete mclk for tdm */
1531 if (get_meson_cpu_version(MESON_CPU_VERSION_LVL_MINOR) == 0xa)
1532 meson_clk_measure((1<<16) | 0x67);
1533
1534 return 0;
1535}
1536
1537struct platform_driver aml_tdm_driver = {
1538 .driver = {
1539 .name = DRV_NAME,
1540 .of_match_table = aml_tdm_device_id,
1541 },
1542 .probe = aml_tdm_platform_probe,
1543 .suspend = aml_tdm_platform_suspend,
1544 .resume = aml_tdm_platform_resume,
1545};
1546module_platform_driver(aml_tdm_driver);
1547
1548MODULE_AUTHOR("Amlogic, Inc.");
1549MODULE_DESCRIPTION("Amlogic TDM ASoc driver");
1550MODULE_LICENSE("GPL");
1551MODULE_ALIAS("platform:" DRV_NAME);
1552MODULE_DEVICE_TABLE(of, aml_tdm_device_id);
1553
generated by cgit at 2024-05-17 09:55:03 (GMT)