blob: 799c1b3f16f14e1159da24129de8b903b4b9e383
| 1 | //----------------------------------------------------------------------------- |
| 2 | // add for AIFIFO channel (old $cdrom/rtl/cdr_top/getbit) |
| 3 | //----------------------------------------------------------------------------- |
| 4 | // Bit 3 CRC pop aififo enable |
| 5 | // Bit 2 writing to this bit to 1 causes CRC module reset |
| 6 | // Bit 1 enable aififo |
| 7 | // Bit 0 writing to this bit to 1 causes aififo soft reset |
| 8 | #define AIU_AIFIFO_CTRL 0x1580 |
| 9 | //'h0000 |
| 10 | // AIFIFO status register |
| 11 | // Bit 13 //aififo request to dcu status |
| 12 | // Bit 12 //dcu select status |
| 13 | // Bit 11:5 //aififo word counter number |
| 14 | // Bit 4:0 //how many bits left in the first pop register |
| 15 | #define AIU_AIFIFO_STATUS 0x1581 |
| 16 | // Same fucntion as the AIGBIT of AIFIFO in CDROM module |
| 17 | // write to this register how many bits wanna pop, |
| 18 | // and reading this register gets the corresponding bits data |
| 19 | #define AIU_AIFIFO_GBIT 0x1582 |
| 20 | // Same function as the AICLB of AIFIFO in CDROM module |
| 21 | // return the leading zeros by reading this registers |
| 22 | #define AIU_AIFIFO_CLB 0x1583 |
| 23 | // -------------------------------------------- |
| 24 | // AIFIFO DDR Interface |
| 25 | // -------------------------------------------- |
| 26 | // The AIFIFO start pointer into DDR memory is a 32-bit number |
| 27 | // The Start pointer will automatically be truncated to land on |
| 28 | // an 8-byte boundary. That is, bits [2:0] = 0; |
| 29 | #define AIU_MEM_AIFIFO_START_PTR 0x1584 |
| 30 | // The current pointer points so some location between the START and END |
| 31 | // pointers. The current pointer is a BYTE pointer. That is, you can |
| 32 | // point to any BYTE address within the START/END range |
| 33 | #define AIU_MEM_AIFIFO_CURR_PTR 0x1585 |
| 34 | #define AIU_MEM_AIFIFO_END_PTR 0x1586 |
| 35 | #define AIU_MEM_AIFIFO_BYTES_AVAIL 0x1587 |
| 36 | // AIFIFO FIFO Control |
| 37 | // bit [15:11] unused |
| 38 | // bit [10] use_level Set this bit to 1 to enable filling of the FIFO controlled by the buffer |
| 39 | // level control. If this bit is 0, then use bit[1] to control the enabling of filling |
| 40 | // bit [9] Data Ready. This bit is set when data can be popped |
| 41 | // bit [8] fill busy This bit will be high when we're fetching data from the DDR memory |
| 42 | // To reset this module, set cntl_enable = 0, and then wait for busy = 0. |
| 43 | // After that you can pulse cntl_init to start over |
| 44 | // bit [7] cntl_endian_jic Just in case endian. last minute byte swap of the data out of |
| 45 | // the FIFO to getbit |
| 46 | // bit [6] unused |
| 47 | // bits [5:3] endian: see $lib/rtl/ddr_endian.v |
| 48 | // bit [2] cntl_empty_en Set to 1 to enable reading the DDR memory FIFO and filling the pipeline to get-bit |
| 49 | // Set cntl_empty_en = cntl_fill_en = 0 when pulsing cntl_init |
| 50 | // bit [1] cntl_fill_en Set to 1 to enable reading data from DDR memory |
| 51 | // bit [0] cntl_init: After setting the read pointers, sizes, channel masks |
| 52 | // and read masks, set this bit to 1 and then to 0 |
| 53 | // NOTE: You don't need to pulse cntl_init if only the start address is |
| 54 | // being changed |
| 55 | #define AIU_MEM_AIFIFO_CONTROL 0x1588 |
| 56 | // -------------------------------------------- |
| 57 | // AIFIFO Buffer Level Manager |
| 58 | // -------------------------------------------- |
| 59 | #define AIU_MEM_AIFIFO_MAN_WP 0x1589 |
| 60 | #define AIU_MEM_AIFIFO_MAN_RP 0x158a |
| 61 | #define AIU_MEM_AIFIFO_LEVEL 0x158b |
| 62 | // |
| 63 | // bit [1] manual mode Set to 1 for manual write pointer mode |
| 64 | // bit [0] Init Set high then low after everything has been initialized |
| 65 | #define AIU_MEM_AIFIFO_BUF_CNTL 0x158c |
| 66 | |
| 67 | #define AIU_MEM_AIFIFO_BUF_WRAP_COUNT 0x158d |
| 68 | #define AIU_MEM_AIFIFO2_BUF_WRAP_COUNT 0x158e |
| 69 | // bit 29:24 A_brst_num |
| 70 | // bit 21:16 A_id |
| 71 | // bit 15:0 level_hold |
| 72 | #define AIU_MEM_AIFIFO_MEM_CTL 0x158f |
| 73 | |
| 74 | int uio_init(aml_audio_dec_t *audec); |
| 75 | int uio_deinit(aml_audio_dec_t *audec); |
| 76 | |
| 77 |