blob: ceb3e2b7b47781125a3dc9b9832dcc627cb71692
1 | @ ***** BEGIN LICENSE BLOCK ***** |
2 | @ Source last modified: $Id: sbrqmfak.s,v 1.1 2005/04/08 21:59:46 jrecker Exp $ |
3 | @ |
4 | @ Portions Copyright (c) 1995-2005 RealNetworks, Inc. All Rights Reserved. |
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8 | @ Source License (the "RPSL") available at |
9 | @ http://www.helixcommunity.org/content/rpsl unless you have licensed |
10 | @ the file under the current version of the RealNetworks Community |
11 | @ Source License (the "RCSL") available at |
12 | @ http://www.helixcommunity.org/content/rcsl, in which case the RCSL |
13 | @ will apply. You may also obtain the license terms directly from |
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18 | @ contents of the file. |
19 | @ |
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21 | @ developer and/or licensor of the Original Code and owns the |
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24 | @ This file, and the files included with this file, is distributed |
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33 | @ |
34 | @ Contributor(s): |
35 | @ |
36 | @ ***** END LICENSE BLOCK ***** |
37 | |
38 | .text |
39 | .code 32 |
40 | .align |
41 | |
42 | @void QMFAnalysisConv(int *cTab, int *delay, int dIdx, int *uBuf) |
43 | @ see comments in sbrqmf.c |
44 | |
45 | .global raac_QMFAnalysisConv |
46 | .type raac_QMFAnalysisConv, %function |
47 | raac_QMFAnalysisConv: |
48 | stmfd sp!, {r4-r11, r14} |
49 | |
50 | mov r6, r2, lsl #5 @ dOff0 = 32*dIdx |
51 | add r6, r6, #31 @ dOff0 = 32*dIdx + 31 |
52 | add r4, r0, #4*(164) @ cPtr1 = cPtr0 + 164 |
53 | |
54 | @ special first pass (flip sign for cTab[384], cTab[512]) |
55 | ldr r11, [r0], #4 |
56 | ldr r14, [r0], #4 |
57 | ldr r12, [r1, r6, lsl #2] |
58 | subs r6, r6, #32 |
59 | addlt r6, r6, #320 |
60 | ldr r2, [r1, r6, lsl #2] |
61 | subs r6, r6, #32 |
62 | addlt r6, r6, #320 |
63 | smull r7, r8, r11, r12 |
64 | smull r9, r10, r14, r2 |
65 | |
66 | ldr r11, [r0], #4 |
67 | ldr r14, [r0], #4 |
68 | ldr r12, [r1, r6, lsl #2] |
69 | subs r6, r6, #32 |
70 | addlt r6, r6, #320 |
71 | ldr r2, [r1, r6, lsl #2] |
72 | subs r6, r6, #32 |
73 | addlt r6, r6, #320 |
74 | smlal r7, r8, r11, r12 |
75 | smlal r9, r10, r14, r2 |
76 | |
77 | ldr r11, [r0], #4 |
78 | ldr r14, [r4], #-4 |
79 | ldr r12, [r1, r6, lsl #2] |
80 | subs r6, r6, #32 |
81 | addlt r6, r6, #320 |
82 | ldr r2, [r1, r6, lsl #2] |
83 | subs r6, r6, #32 |
84 | addlt r6, r6, #320 |
85 | smlal r7, r8, r11, r12 |
86 | smlal r9, r10, r14, r2 |
87 | |
88 | ldr r11, [r4], #-4 |
89 | ldr r14, [r4], #-4 |
90 | ldr r12, [r1, r6, lsl #2] |
91 | subs r6, r6, #32 |
92 | addlt r6, r6, #320 |
93 | ldr r2, [r1, r6, lsl #2] |
94 | subs r6, r6, #32 |
95 | addlt r6, r6, #320 |
96 | rsb r11, r11, #0 |
97 | smlal r7, r8, r11, r12 |
98 | smlal r9, r10, r14, r2 |
99 | |
100 | ldr r11, [r4], #-4 |
101 | ldr r14, [r4], #-4 |
102 | ldr r12, [r1, r6, lsl #2] |
103 | subs r6, r6, #32 |
104 | addlt r6, r6, #320 |
105 | ldr r2, [r1, r6, lsl #2] |
106 | subs r6, r6, #32 |
107 | addlt r6, r6, #320 |
108 | rsb r11, r11, #0 |
109 | smlal r7, r8, r11, r12 |
110 | smlal r9, r10, r14, r2 |
111 | |
112 | str r10, [r3, #4*32] |
113 | str r8, [r3], #4 |
114 | sub r6, r6, #1 |
115 | mov r5, #31 |
116 | |
117 | SRC_Loop_Start: |
118 | ldr r11, [r0], #4 |
119 | ldr r14, [r0], #4 |
120 | ldr r12, [r1, r6, lsl #2] |
121 | subs r6, r6, #32 |
122 | addlt r6, r6, #320 |
123 | ldr r2, [r1, r6, lsl #2] |
124 | subs r6, r6, #32 |
125 | addlt r6, r6, #320 |
126 | smull r7, r8, r11, r12 |
127 | smull r9, r10, r14, r2 |
128 | |
129 | ldr r11, [r0], #4 |
130 | ldr r14, [r0], #4 |
131 | ldr r12, [r1, r6, lsl #2] |
132 | subs r6, r6, #32 |
133 | addlt r6, r6, #320 |
134 | ldr r2, [r1, r6, lsl #2] |
135 | subs r6, r6, #32 |
136 | addlt r6, r6, #320 |
137 | smlal r7, r8, r11, r12 |
138 | smlal r9, r10, r14, r2 |
139 | |
140 | ldr r11, [r0], #4 |
141 | ldr r14, [r4], #-4 |
142 | ldr r12, [r1, r6, lsl #2] |
143 | subs r6, r6, #32 |
144 | addlt r6, r6, #320 |
145 | ldr r2, [r1, r6, lsl #2] |
146 | subs r6, r6, #32 |
147 | addlt r6, r6, #320 |
148 | smlal r7, r8, r11, r12 |
149 | smlal r9, r10, r14, r2 |
150 | |
151 | ldr r11, [r4], #-4 |
152 | ldr r14, [r4], #-4 |
153 | ldr r12, [r1, r6, lsl #2] |
154 | subs r6, r6, #32 |
155 | addlt r6, r6, #320 |
156 | ldr r2, [r1, r6, lsl #2] |
157 | subs r6, r6, #32 |
158 | addlt r6, r6, #320 |
159 | smlal r7, r8, r11, r12 |
160 | smlal r9, r10, r14, r2 |
161 | |
162 | ldr r11, [r4], #-4 |
163 | ldr r14, [r4], #-4 |
164 | ldr r12, [r1, r6, lsl #2] |
165 | subs r6, r6, #32 |
166 | addlt r6, r6, #320 |
167 | ldr r2, [r1, r6, lsl #2] |
168 | subs r6, r6, #32 |
169 | addlt r6, r6, #320 |
170 | smlal r7, r8, r11, r12 |
171 | smlal r9, r10, r14, r2 |
172 | |
173 | str r10, [r3, #4*32] |
174 | str r8, [r3], #4 |
175 | sub r6, r6, #1 |
176 | |
177 | subs r5, r5, #1 |
178 | bne SRC_Loop_Start |
179 | |
180 | ldmfd sp!, {r4-r11, pc} |
181 | |
182 | .end |
183 |