blob: ea93f7add3a7c0942d0624e27d5e77eb6102ce30
| 1 | @ ***** BEGIN LICENSE BLOCK ***** |
| 2 | @ Source last modified: $Id: sbrqmfsk.s,v 1.1 2005/04/08 21:59:46 jrecker Exp $ |
| 3 | @ |
| 4 | @ Portions Copyright (c) 1995-2005 RealNetworks, Inc. All Rights Reserved. |
| 5 | @ |
| 6 | @ The contents of this file, and the files included with this file, |
| 7 | @ are subject to the current version of the RealNetworks Public |
| 8 | @ Source License (the "RPSL") available at |
| 9 | @ http://www.helixcommunity.org/content/rpsl unless you have licensed |
| 10 | @ the file under the current version of the RealNetworks Community |
| 11 | @ Source License (the "RCSL") available at |
| 12 | @ http://www.helixcommunity.org/content/rcsl, in which case the RCSL |
| 13 | @ will apply. You may also obtain the license terms directly from |
| 14 | @ RealNetworks. You may not use this file except in compliance with |
| 15 | @ the RPSL or, if you have a valid RCSL with RealNetworks applicable |
| 16 | @ to this file, the RCSL. Please see the applicable RPSL or RCSL for |
| 17 | @ the rights, obligations and limitations governing use of the |
| 18 | @ contents of the file. |
| 19 | @ |
| 20 | @ This file is part of the Helix DNA Technology. RealNetworks is the |
| 21 | @ developer and/or licensor of the Original Code and owns the |
| 22 | @ copyrights in the portions it created. |
| 23 | @ |
| 24 | @ This file, and the files included with this file, is distributed |
| 25 | @ and made available on an 'AS IS' basis, WITHOUT WARRANTY OF ANY |
| 26 | @ KIND, EITHER EXPRESS OR IMPLIED, AND REALNETWORKS HEREBY DISCLAIMS |
| 27 | @ ALL SUCH WARRANTIES, INCLUDING WITHOUT LIMITATION, ANY WARRANTIES |
| 28 | @ OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIET |
| 29 | @ ENJOYMENT OR NON-INFRINGEMENT. |
| 30 | @ |
| 31 | @ Technology Compatibility Kit Test Suite(s) Location: |
| 32 | @ http://www.helixcommunity.org/content/tck |
| 33 | @ |
| 34 | @ Contributor(s): |
| 35 | @ |
| 36 | @ ***** END LICENSE BLOCK ***** |
| 37 | |
| 38 | .text |
| 39 | .code 32 |
| 40 | .align |
| 41 | |
| 42 | @ void QMFSynthesisConv(int *cPtr, int *delay, int dIdx, short *outbuf, int nChans); |
| 43 | @ see comments in sbrqmf.c |
| 44 | |
| 45 | .global raac_QMFSynthesisConv |
| 46 | .type raac_QMFSynthesisConv, %function |
| 47 | raac_QMFSynthesisConv: |
| 48 | stmfd sp!, {r4-r11, r14} |
| 49 | |
| 50 | ldr r9, [r13, #4*9] @ we saved 9 registers on stack |
| 51 | mov r5, r2, lsl #7 @ dOff0 = 128*dIdx |
| 52 | subs r6, r5, #1 @ dOff1 = dOff0 - 1 |
| 53 | addlt r6, r6, #1280 @ if (dOff1 < 0) then dOff1 += 1280 |
| 54 | mov r4, #64 |
| 55 | |
| 56 | SRC_Loop_Start: |
| 57 | ldr r10, [r0], #4 |
| 58 | ldr r12, [r0], #4 |
| 59 | ldr r11, [r1, r5, lsl #2] |
| 60 | ldr r14, [r1, r6, lsl #2] |
| 61 | smull r7, r8, r10, r11 |
| 62 | subs r5, r5, #256 |
| 63 | addlt r5, r5, #1280 |
| 64 | smlal r7, r8, r12, r14 |
| 65 | subs r6, r6, #256 |
| 66 | addlt r6, r6, #1280 |
| 67 | |
| 68 | ldr r10, [r0], #4 |
| 69 | ldr r12, [r0], #4 |
| 70 | ldr r11, [r1, r5, lsl #2] |
| 71 | ldr r14, [r1, r6, lsl #2] |
| 72 | smlal r7, r8, r10, r11 |
| 73 | subs r5, r5, #256 |
| 74 | addlt r5, r5, #1280 |
| 75 | smlal r7, r8, r12, r14 |
| 76 | subs r6, r6, #256 |
| 77 | addlt r6, r6, #1280 |
| 78 | |
| 79 | ldr r10, [r0], #4 |
| 80 | ldr r12, [r0], #4 |
| 81 | ldr r11, [r1, r5, lsl #2] |
| 82 | ldr r14, [r1, r6, lsl #2] |
| 83 | smlal r7, r8, r10, r11 |
| 84 | subs r5, r5, #256 |
| 85 | addlt r5, r5, #1280 |
| 86 | smlal r7, r8, r12, r14 |
| 87 | subs r6, r6, #256 |
| 88 | addlt r6, r6, #1280 |
| 89 | |
| 90 | ldr r10, [r0], #4 |
| 91 | ldr r12, [r0], #4 |
| 92 | ldr r11, [r1, r5, lsl #2] |
| 93 | ldr r14, [r1, r6, lsl #2] |
| 94 | smlal r7, r8, r10, r11 |
| 95 | subs r5, r5, #256 |
| 96 | addlt r5, r5, #1280 |
| 97 | smlal r7, r8, r12, r14 |
| 98 | subs r6, r6, #256 |
| 99 | addlt r6, r6, #1280 |
| 100 | |
| 101 | ldr r10, [r0], #4 |
| 102 | ldr r12, [r0], #4 |
| 103 | ldr r11, [r1, r5, lsl #2] |
| 104 | ldr r14, [r1, r6, lsl #2] |
| 105 | smlal r7, r8, r10, r11 |
| 106 | subs r5, r5, #256 |
| 107 | addlt r5, r5, #1280 |
| 108 | smlal r7, r8, r12, r14 |
| 109 | subs r6, r6, #256 |
| 110 | addlt r6, r6, #1280 |
| 111 | |
| 112 | add r5, r5, #1 |
| 113 | sub r6, r6, #1 |
| 114 | |
| 115 | add r8, r8, #0x04 |
| 116 | mov r8, r8, asr #3 @ FBITS_OUT_QMFS |
| 117 | mov r7, r8, asr #31 |
| 118 | cmp r7, r8, asr #15 |
| 119 | eorne r8, r7, #0x7f00 @ takes 2 instructions for immediate value of 0x7fffffff |
| 120 | eorne r8, r8, #0x00ff |
| 121 | strh r8, [r3, #0] |
| 122 | add r3, r3, r9, lsl #1 |
| 123 | |
| 124 | subs r4, r4, #1 |
| 125 | bne SRC_Loop_Start |
| 126 | |
| 127 | ldmfd sp!, {r4-r11, pc} |
| 128 | |
| 129 | .end |
| 130 | |
| 131 |