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1/******************************************************************************
2 *
3 * Copyright (C) 2009-2012 Broadcom Corporation
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 ******************************************************************************/
18
19/******************************************************************************
20 *
21 * Filename: bt_vendor_brcm.h
22 *
23 * Description: A wrapper header file of bt_vendor_lib.h
24 *
25 * Contains definitions specific for interfacing with Broadcom
26 * Bluetooth chipsets
27 *
28 ******************************************************************************/
29
30#ifndef BT_VENDOR_BRCM_H
31#define BT_VENDOR_BRCM_H
32
33#include "bt_vendor_lib.h"
34#include "vnd_buildcfg.h"
35
36/******************************************************************************
37** Constants & Macros
38******************************************************************************/
39
40#ifndef FALSE
41#define FALSE 0
42#endif
43
44#ifndef TRUE
45#define TRUE (!FALSE)
46#endif
47
48#ifndef VENDOR_LIB_RUNTIME_TUNING_ENABLED
49#define VENDOR_LIB_RUNTIME_TUNING_ENABLED FALSE
50#endif
51
52/* Run-time configuration file */
53#ifndef VENDOR_LIB_CONF_FILE
54#ifdef O_AMLOGIC
55#define VENDOR_LIB_CONF_FILE "/vendor/etc/bluetooth/bt_vendor.conf"
56#else
57#define VENDOR_LIB_CONF_FILE "/etc/bluetooth/bt_vendor.conf"
58#endif
59#endif
60
61/* Device port name where Bluetooth controller attached */
62#ifndef BLUETOOTH_UART_DEVICE_PORT
63#define BLUETOOTH_UART_DEVICE_PORT "/dev/ttyS1" /* maguro */
64#endif
65
66/* Location of firmware patch files */
67#ifndef FW_PATCHFILE_LOCATION
68#define FW_PATCHFILE_LOCATION "/etc/bluetooth/" /* maguro */
69#endif
70
71#ifndef UART_TARGET_BAUD_RATE
72#define UART_TARGET_BAUD_RATE 2000000
73#endif
74
75/* The millisecond delay pauses on HCI transport after firmware patches
76 * were downloaded. This gives some time for firmware to restart with
77 * patches before host attempts to send down any HCI commands.
78 *
79 * Note: It has been discovered that BCM43241B0 needs at least 200ms
80 * settlement delay in here. Without the delay, a Hardware Error event
81 * from BCM43241B0 had been seen in HCI upstream path right after the
82 * host sent the HCI_VSC_SET_BDADDR commad to the controller at higher
83 * baud.
84 */
85#ifndef FW_PATCH_SETTLEMENT_DELAY_MS
86#define FW_PATCH_SETTLEMENT_DELAY_MS 200
87#endif
88
89/* The Bluetooth Device Aaddress source switch:
90 *
91 * -FALSE- (default value)
92 * Get the factory BDADDR from device's file system. Normally the BDADDR is
93 * stored in the location pointed by the PROPERTY_BT_BDADDR_PATH (defined in
94 * btif_common.h file) property.
95 *
96 * -TRUE-
97 * If the Bluetooth Controller has equipped with a non-volatile memory (such
98 * as BCM4330's OTP memory), the factory BDADDR can be stored in there and
99 * retrieved by the stack while enabling BT.
100 * !!! WARNING !!! Make sure that the OTP feature has been enabled in the
101 * firmware patchram (.hcd) file.
102 */
103#ifndef USE_CONTROLLER_BDADDR
104#define USE_CONTROLLER_BDADDR TRUE
105#endif
106
107/* sleep mode
108
109 0: disable
110 1: UART with Host wake/BT wake out of band signals
111*/
112#ifndef LPM_SLEEP_MODE
113#define LPM_SLEEP_MODE 0
114#endif
115
116/* Host Stack Idle Threshold in 300ms or 25ms
117
118 In sleep mode 1, this is the number of firmware loops executed with no
119 activity before the Host wake line is deasserted. Activity includes HCI
120 traffic excluding certain sleep mode commands and the presence of SCO
121 connections if the "Allow Host Sleep During SCO" flag is not set to 1.
122 Each count of this parameter is roughly equivalent to 300ms or 25ms.
123*/
124#ifndef LPM_IDLE_THRESHOLD
125#define LPM_IDLE_THRESHOLD 1
126#endif
127
128/* Host Controller Idle Threshold in 300ms or 25ms
129
130 This is the number of firmware loops executed with no activity before the
131 HC is considered idle. Depending on the mode, HC may then attempt to sleep.
132 Activity includes HCI traffic excluding certain sleep mode commands and
133 the presence of ACL/SCO connections.
134*/
135#ifndef LPM_HC_IDLE_THRESHOLD
136#define LPM_HC_IDLE_THRESHOLD 1
137#endif
138
139/* BT_WAKE Polarity - 0=Active Low, 1= Active High */
140#ifndef LPM_BT_WAKE_POLARITY
141#define LPM_BT_WAKE_POLARITY 1 /* maguro */
142#endif
143
144/* HOST_WAKE Polarity - 0=Active Low, 1= Active High */
145#ifndef LPM_HOST_WAKE_POLARITY
146#define LPM_HOST_WAKE_POLARITY 1 /* maguro */
147#endif
148
149/* LPM_ALLOW_HOST_SLEEP_DURING_SCO
150
151 When this flag is set to 0, the host is not allowed to sleep while
152 an SCO is active. In sleep mode 1, the device will keep the host
153 wake line asserted while an SCO is active.
154 When this flag is set to 1, the host can sleep while an SCO is active.
155 This flag should only be set to 1 if SCO traffic is directed to the PCM
156 interface.
157*/
158#ifndef LPM_ALLOW_HOST_SLEEP_DURING_SCO
159#define LPM_ALLOW_HOST_SLEEP_DURING_SCO 1
160#endif
161
162/* LPM_COMBINE_SLEEP_MODE_AND_LPM
163
164 In Mode 0, always set byte 7 to 0. In sleep mode 1, device always
165 requires permission to sleep between scans / periodic inquiries regardless
166 of the setting of this byte. In sleep mode 1, if byte is set, device must
167 have "permission" to sleep during the low power modes of sniff, hold, and
168 park. If byte is not set, device can sleep without permission during these
169 modes. Permission to sleep in Mode 1 is obtained if the BT_WAKE signal is
170 not asserted.
171*/
172#ifndef LPM_COMBINE_SLEEP_MODE_AND_LPM
173#define LPM_COMBINE_SLEEP_MODE_AND_LPM 1
174#endif
175
176/* LPM_ENABLE_UART_TXD_TRI_STATE
177
178 When set to 0, the device will not tristate its UART TX line before going
179 to sleep.
180 When set to 1, the device will tristate its UART TX line before going to
181 sleep.
182*/
183#ifndef LPM_ENABLE_UART_TXD_TRI_STATE
184#define LPM_ENABLE_UART_TXD_TRI_STATE 0
185#endif
186
187/* LPM_PULSED_HOST_WAKE
188*/
189#ifndef LPM_PULSED_HOST_WAKE
190#define LPM_PULSED_HOST_WAKE 0
191#endif
192
193/* LPM_IDLE_TIMEOUT_MULTIPLE
194
195 The multiple factor of host stack idle threshold in 300ms/25ms
196*/
197#ifndef LPM_IDLE_TIMEOUT_MULTIPLE
198#define LPM_IDLE_TIMEOUT_MULTIPLE 10
199#endif
200
201/* BT_WAKE_VIA_USERIAL_IOCTL
202
203 Use userial ioctl function to control BT_WAKE signal
204*/
205#ifndef BT_WAKE_VIA_USERIAL_IOCTL
206#define BT_WAKE_VIA_USERIAL_IOCTL FALSE
207#endif
208
209/* BT_WAKE_USERIAL_LDISC
210
211 Use line discipline if the BT_WAKE control is in line discipline
212*/
213#ifndef BT_WAKE_USERIAL_LDISC
214#define BT_WAKE_USERIAL_LDISC FALSE
215#endif
216
217/* BT_WAKE_VIA_PROC
218
219 LPM & BT_WAKE control through PROC nodes
220*/
221#ifndef BT_WAKE_VIA_PROC
222#define BT_WAKE_VIA_PROC FALSE
223#endif
224
225#ifndef BT_WAKE_VIA_PROC_NOTIFY_DEASSERT
226#define BT_WAKE_VIA_PROC_NOTIFY_DEASSERT FALSE
227#endif
228
229/* N_BRCM_HCI
230
231 UART ioctl line discipline
232*/
233#ifndef N_BRCM_HCI
234#define N_BRCM_HCI 25
235#endif
236
237/* SCO_CFG_INCLUDED
238
239 Do SCO configuration by default. If the firmware patch had been embedded
240 with desired SCO configuration, set this FALSE to bypass configuration
241 from host software.
242*/
243#ifndef SCO_CFG_INCLUDED
244#define SCO_CFG_INCLUDED TRUE
245#endif
246
247#ifndef SCO_USE_I2S_INTERFACE
248#define SCO_USE_I2S_INTERFACE FALSE
249#endif
250
251#define SCO_I2SPCM_PARAM_SIZE 4
252
253/* SCO_WBS_SAMPLE_RATE
254 0 : 8K
255 1 : 16K
256 2 : 4K
257 This macro is used for setting WBS sampling rate for a SCO connection
258 If the mobile network supports WBS, we need to use 16KHz as default
259 but if the platform doesn't support 16KHz, the sample rate can be
260 overriden to 8KHz by setting this to 0.
261*/
262#ifndef SCO_WBS_SAMPLE_RATE
263#define SCO_WBS_SAMPLE_RATE 1
264#endif
265
266
267/* SCO_I2SPCM_IF_MODE - 0=Disable, 1=Enable */
268#ifndef SCO_I2SPCM_IF_MODE
269#define SCO_I2SPCM_IF_MODE 1
270#endif
271
272/* SCO_I2SPCM_IF_ROLE - 0=Slave, 1=Master */
273#ifndef SCO_I2SPCM_IF_ROLE
274#define SCO_I2SPCM_IF_ROLE 1
275#endif
276
277/* SCO_I2SPCM_IF_SAMPLE_RATE
278
279 0 : 8K
280 1 : 16K
281 2 : 4K
282*/
283#ifndef SCO_I2SPCM_IF_SAMPLE_RATE
284#define SCO_I2SPCM_IF_SAMPLE_RATE 0
285#endif
286
287/* SCO_I2SPCM_IF_CLOCK_RATE
288
289 0 : 128K
290 1 : 256K
291 2 : 512K
292 3 : 1024K
293 4 : 2048K
294*/
295#ifndef SCO_I2SPCM_IF_CLOCK_RATE
296#define SCO_I2SPCM_IF_CLOCK_RATE 1
297#endif
298
299/* SCO_I2SPCM_IF_CLOCK_RATE4WBS
300
301 0 : 128K
302 1 : 256K
303 2 : 512K
304 3 : 1024K
305 4 : 2048K
306*/
307#ifndef SCO_I2SPCM_IF_CLOCK_RATE4WBS
308#define SCO_I2SPCM_IF_CLOCK_RATE4WBS 2
309#endif
310
311
312#define SCO_PCM_PARAM_SIZE 5
313
314/* SCO_PCM_ROUTING
315
316 0 : PCM
317 1 : Transport
318 2 : Codec
319 3 : I2S
320*/
321#ifndef SCO_PCM_ROUTING
322#define SCO_PCM_ROUTING 0
323#endif
324
325/* SCO_PCM_IF_CLOCK_RATE
326
327 NOTICE: suggested to be consistent with SCO_I2SPCM_IF_CLOCK_RATE
328
329 0 : 128K
330 1 : 256K
331 2 : 512K
332 3 : 1024K
333 4 : 2048K
334*/
335#ifndef SCO_PCM_IF_CLOCK_RATE
336#define SCO_PCM_IF_CLOCK_RATE 4
337#endif
338
339/* SCO_PCM_IF_FRAME_TYPE - 0=Short, 1=Long */
340#ifndef SCO_PCM_IF_FRAME_TYPE
341#define SCO_PCM_IF_FRAME_TYPE 1
342#endif
343
344/* SCO_PCM_IF_SYNC_MODE
345
346 NOTICE: in most usage cases the value will be the same as
347 SCO_PCM_IF_CLOCK_MODE setting
348
349 0 : Slave
350 1 : Master
351*/
352#ifndef SCO_PCM_IF_SYNC_MODE
353#define SCO_PCM_IF_SYNC_MODE 0
354#endif
355
356/* SCO_PCM_IF_CLOCK_MODE
357
358 NOTICE: suggested to be consistent with SCO_I2SPCM_IF_ROLE
359
360 0 : Slave
361 1 : Master
362*/
363#ifndef SCO_PCM_IF_CLOCK_MODE
364#define SCO_PCM_IF_CLOCK_MODE 0
365#endif
366
367#define PCM_DATA_FORMAT_PARAM_SIZE 5
368
369/* PCM_DATA_FMT_SHIFT_MODE
370
371 0 : MSB first
372 1 : LSB first
373*/
374#ifndef PCM_DATA_FMT_SHIFT_MODE
375#define PCM_DATA_FMT_SHIFT_MODE 0
376#endif
377
378/* PCM_DATA_FMT_FILL_BITS
379
380 Specifies the value with which to fill unused bits
381 if Fill_Method is set to programmable
382*/
383#ifndef PCM_DATA_FMT_FILL_BITS
384#define PCM_DATA_FMT_FILL_BITS 3
385#endif
386
387/* PCM_DATA_FMT_FILL_METHOD
388
389 0 : 0's
390 1 : 1's
391 2 : Signed
392 3 : Programmable
393*/
394#ifndef PCM_DATA_FMT_FILL_METHOD
395#define PCM_DATA_FMT_FILL_METHOD 3
396#endif
397
398/* PCM_DATA_FMT_FILL_NUM
399
400 Specifies the number of bits to be filled
401*/
402#ifndef PCM_DATA_FMT_FILL_NUM
403#define PCM_DATA_FMT_FILL_NUM 0
404#endif
405
406/* PCM_DATA_FMT_JUSTIFY_MODE
407
408 0 : Left justify (fill data shifted out last)
409 1 : Right justify (fill data shifted out first)
410*/
411#ifndef PCM_DATA_FMT_JUSTIFY_MODE
412#define PCM_DATA_FMT_JUSTIFY_MODE 0
413#endif
414
415/* HW_END_WITH_HCI_RESET
416
417 Sample code implementation of sending a HCI_RESET command during the epilog
418 process. It calls back to the callers after command complete of HCI_RESET
419 is received.
420*/
421#ifndef HW_END_WITH_HCI_RESET
422#define HW_END_WITH_HCI_RESET FALSE
423#endif
424
425/******************************************************************************
426** Extern variables and functions
427******************************************************************************/
428
429extern bt_vendor_callbacks_t *bt_vendor_cbacks;
430
431extern int hw_set_audio_state(bt_vendor_op_audio_state_t *p_state);
432
433#endif /* BT_VENDOR_BRCM_H */
434
435
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