blob: a707053c5acd94b7d36eb1ae4432fa00c7fadd8c
1 | /****************************************************************************** |
2 | * |
3 | * Copyright (C) 2009-2012 Broadcom Corporation |
4 | * |
5 | * Licensed under the Apache License, Version 2.0 (the "License"); |
6 | * you may not use this file except in compliance with the License. |
7 | * You may obtain a copy of the License at: |
8 | * |
9 | * http://www.apache.org/licenses/LICENSE-2.0 |
10 | * |
11 | * Unless required by applicable law or agreed to in writing, software |
12 | * distributed under the License is distributed on an "AS IS" BASIS, |
13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
14 | * See the License for the specific language governing permissions and |
15 | * limitations under the License. |
16 | * |
17 | ******************************************************************************/ |
18 | |
19 | /****************************************************************************** |
20 | * |
21 | * Filename: bt_vendor_brcm.h |
22 | * |
23 | * Description: A wrapper header file of bt_vendor_lib.h |
24 | * |
25 | * Contains definitions specific for interfacing with Broadcom |
26 | * Bluetooth chipsets |
27 | * |
28 | ******************************************************************************/ |
29 | |
30 | #ifndef BT_VENDOR_BRCM_H |
31 | #define BT_VENDOR_BRCM_H |
32 | |
33 | #include "bt_vendor_lib.h" |
34 | #include "vnd_buildcfg.h" |
35 | |
36 | /****************************************************************************** |
37 | ** Constants & Macros |
38 | ******************************************************************************/ |
39 | |
40 | #ifndef FALSE |
41 | #define FALSE 0 |
42 | #endif |
43 | |
44 | #ifndef TRUE |
45 | #define TRUE (!FALSE) |
46 | #endif |
47 | |
48 | #ifndef VENDOR_LIB_RUNTIME_TUNING_ENABLED |
49 | #define VENDOR_LIB_RUNTIME_TUNING_ENABLED FALSE |
50 | #endif |
51 | |
52 | /* Run-time configuration file */ |
53 | #ifndef VENDOR_LIB_CONF_FILE |
54 | #define VENDOR_LIB_CONF_FILE "/etc/bluetooth/bt_vendor.conf" |
55 | #endif |
56 | |
57 | /* Device port name where Bluetooth controller attached */ |
58 | #ifndef BLUETOOTH_UART_DEVICE_PORT |
59 | #define BLUETOOTH_UART_DEVICE_PORT "/dev/ttyS1" /* maguro */ |
60 | #endif |
61 | |
62 | /* Location of firmware patch files */ |
63 | #ifndef FW_PATCHFILE_LOCATION |
64 | #define FW_PATCHFILE_LOCATION "/etc/bluetooth/" /* maguro */ |
65 | #endif |
66 | |
67 | #ifndef UART_TARGET_BAUD_RATE |
68 | #define UART_TARGET_BAUD_RATE 2000000 |
69 | #endif |
70 | |
71 | /* The millisecond delay pauses on HCI transport after firmware patches |
72 | * were downloaded. This gives some time for firmware to restart with |
73 | * patches before host attempts to send down any HCI commands. |
74 | * |
75 | * Note: It has been discovered that BCM43241B0 needs at least 200ms |
76 | * settlement delay in here. Without the delay, a Hardware Error event |
77 | * from BCM43241B0 had been seen in HCI upstream path right after the |
78 | * host sent the HCI_VSC_SET_BDADDR commad to the controller at higher |
79 | * baud. |
80 | */ |
81 | #ifndef FW_PATCH_SETTLEMENT_DELAY_MS |
82 | #define FW_PATCH_SETTLEMENT_DELAY_MS 200 |
83 | #endif |
84 | |
85 | /* The Bluetooth Device Aaddress source switch: |
86 | * |
87 | * -FALSE- (default value) |
88 | * Get the factory BDADDR from device's file system. Normally the BDADDR is |
89 | * stored in the location pointed by the PROPERTY_BT_BDADDR_PATH (defined in |
90 | * btif_common.h file) property. |
91 | * |
92 | * -TRUE- |
93 | * If the Bluetooth Controller has equipped with a non-volatile memory (such |
94 | * as BCM4330's OTP memory), the factory BDADDR can be stored in there and |
95 | * retrieved by the stack while enabling BT. |
96 | * !!! WARNING !!! Make sure that the OTP feature has been enabled in the |
97 | * firmware patchram (.hcd) file. |
98 | */ |
99 | #ifndef USE_CONTROLLER_BDADDR |
100 | #define USE_CONTROLLER_BDADDR FALSE |
101 | #endif |
102 | |
103 | /* sleep mode |
104 | |
105 | 0: disable |
106 | 1: UART with Host wake/BT wake out of band signals |
107 | */ |
108 | #ifndef LPM_SLEEP_MODE |
109 | #define LPM_SLEEP_MODE 0 |
110 | #endif |
111 | |
112 | /* Host Stack Idle Threshold in 300ms or 25ms |
113 | |
114 | In sleep mode 1, this is the number of firmware loops executed with no |
115 | activity before the Host wake line is deasserted. Activity includes HCI |
116 | traffic excluding certain sleep mode commands and the presence of SCO |
117 | connections if the "Allow Host Sleep During SCO" flag is not set to 1. |
118 | Each count of this parameter is roughly equivalent to 300ms or 25ms. |
119 | */ |
120 | #ifndef LPM_IDLE_THRESHOLD |
121 | #define LPM_IDLE_THRESHOLD 1 |
122 | #endif |
123 | |
124 | /* Host Controller Idle Threshold in 300ms or 25ms |
125 | |
126 | This is the number of firmware loops executed with no activity before the |
127 | HC is considered idle. Depending on the mode, HC may then attempt to sleep. |
128 | Activity includes HCI traffic excluding certain sleep mode commands and |
129 | the presence of ACL/SCO connections. |
130 | */ |
131 | #ifndef LPM_HC_IDLE_THRESHOLD |
132 | #define LPM_HC_IDLE_THRESHOLD 1 |
133 | #endif |
134 | |
135 | /* BT_WAKE Polarity - 0=Active Low, 1= Active High */ |
136 | #ifndef LPM_BT_WAKE_POLARITY |
137 | #define LPM_BT_WAKE_POLARITY 1 /* maguro */ |
138 | #endif |
139 | |
140 | /* HOST_WAKE Polarity - 0=Active Low, 1= Active High */ |
141 | #ifndef LPM_HOST_WAKE_POLARITY |
142 | #define LPM_HOST_WAKE_POLARITY 1 /* maguro */ |
143 | #endif |
144 | |
145 | /* LPM_ALLOW_HOST_SLEEP_DURING_SCO |
146 | |
147 | When this flag is set to 0, the host is not allowed to sleep while |
148 | an SCO is active. In sleep mode 1, the device will keep the host |
149 | wake line asserted while an SCO is active. |
150 | When this flag is set to 1, the host can sleep while an SCO is active. |
151 | This flag should only be set to 1 if SCO traffic is directed to the PCM |
152 | interface. |
153 | */ |
154 | #ifndef LPM_ALLOW_HOST_SLEEP_DURING_SCO |
155 | #define LPM_ALLOW_HOST_SLEEP_DURING_SCO 1 |
156 | #endif |
157 | |
158 | /* LPM_COMBINE_SLEEP_MODE_AND_LPM |
159 | |
160 | In Mode 0, always set byte 7 to 0. In sleep mode 1, device always |
161 | requires permission to sleep between scans / periodic inquiries regardless |
162 | of the setting of this byte. In sleep mode 1, if byte is set, device must |
163 | have "permission" to sleep during the low power modes of sniff, hold, and |
164 | park. If byte is not set, device can sleep without permission during these |
165 | modes. Permission to sleep in Mode 1 is obtained if the BT_WAKE signal is |
166 | not asserted. |
167 | */ |
168 | #ifndef LPM_COMBINE_SLEEP_MODE_AND_LPM |
169 | #define LPM_COMBINE_SLEEP_MODE_AND_LPM 1 |
170 | #endif |
171 | |
172 | /* LPM_ENABLE_UART_TXD_TRI_STATE |
173 | |
174 | When set to 0, the device will not tristate its UART TX line before going |
175 | to sleep. |
176 | When set to 1, the device will tristate its UART TX line before going to |
177 | sleep. |
178 | */ |
179 | #ifndef LPM_ENABLE_UART_TXD_TRI_STATE |
180 | #define LPM_ENABLE_UART_TXD_TRI_STATE 0 |
181 | #endif |
182 | |
183 | /* LPM_PULSED_HOST_WAKE |
184 | */ |
185 | #ifndef LPM_PULSED_HOST_WAKE |
186 | #define LPM_PULSED_HOST_WAKE 0 |
187 | #endif |
188 | |
189 | /* LPM_IDLE_TIMEOUT_MULTIPLE |
190 | |
191 | The multiple factor of host stack idle threshold in 300ms/25ms |
192 | */ |
193 | #ifndef LPM_IDLE_TIMEOUT_MULTIPLE |
194 | #define LPM_IDLE_TIMEOUT_MULTIPLE 10 |
195 | #endif |
196 | |
197 | /* BT_WAKE_VIA_USERIAL_IOCTL |
198 | |
199 | Use userial ioctl function to control BT_WAKE signal |
200 | */ |
201 | #ifndef BT_WAKE_VIA_USERIAL_IOCTL |
202 | #define BT_WAKE_VIA_USERIAL_IOCTL FALSE |
203 | #endif |
204 | |
205 | /* BT_WAKE_USERIAL_LDISC |
206 | |
207 | Use line discipline if the BT_WAKE control is in line discipline |
208 | */ |
209 | #ifndef BT_WAKE_USERIAL_LDISC |
210 | #define BT_WAKE_USERIAL_LDISC FALSE |
211 | #endif |
212 | |
213 | /* BT_WAKE_VIA_PROC |
214 | |
215 | LPM & BT_WAKE control through PROC nodes |
216 | */ |
217 | #ifndef BT_WAKE_VIA_PROC |
218 | #define BT_WAKE_VIA_PROC FALSE |
219 | #endif |
220 | |
221 | #ifndef BT_WAKE_VIA_PROC_NOTIFY_DEASSERT |
222 | #define BT_WAKE_VIA_PROC_NOTIFY_DEASSERT FALSE |
223 | #endif |
224 | |
225 | /* N_BRCM_HCI |
226 | |
227 | UART ioctl line discipline |
228 | */ |
229 | #ifndef N_BRCM_HCI |
230 | #define N_BRCM_HCI 25 |
231 | #endif |
232 | |
233 | /* SCO_CFG_INCLUDED |
234 | |
235 | Do SCO configuration by default. If the firmware patch had been embedded |
236 | with desired SCO configuration, set this FALSE to bypass configuration |
237 | from host software. |
238 | */ |
239 | #ifndef SCO_CFG_INCLUDED |
240 | #define SCO_CFG_INCLUDED TRUE |
241 | #endif |
242 | |
243 | #ifndef SCO_USE_I2S_INTERFACE |
244 | #define SCO_USE_I2S_INTERFACE FALSE |
245 | #endif |
246 | |
247 | #define SCO_I2SPCM_PARAM_SIZE 4 |
248 | |
249 | /* SCO_WBS_SAMPLE_RATE |
250 | 0 : 8K |
251 | 1 : 16K |
252 | 2 : 4K |
253 | This macro is used for setting WBS sampling rate for a SCO connection |
254 | If the mobile network supports WBS, we need to use 16KHz as default |
255 | but if the platform doesn't support 16KHz, the sample rate can be |
256 | overriden to 8KHz by setting this to 0. |
257 | */ |
258 | #ifndef SCO_WBS_SAMPLE_RATE |
259 | #define SCO_WBS_SAMPLE_RATE 1 |
260 | #endif |
261 | |
262 | |
263 | /* SCO_I2SPCM_IF_MODE - 0=Disable, 1=Enable */ |
264 | #ifndef SCO_I2SPCM_IF_MODE |
265 | #define SCO_I2SPCM_IF_MODE 1 |
266 | #endif |
267 | |
268 | /* SCO_I2SPCM_IF_ROLE - 0=Slave, 1=Master */ |
269 | #ifndef SCO_I2SPCM_IF_ROLE |
270 | #define SCO_I2SPCM_IF_ROLE 1 |
271 | #endif |
272 | |
273 | /* SCO_I2SPCM_IF_SAMPLE_RATE |
274 | |
275 | 0 : 8K |
276 | 1 : 16K |
277 | 2 : 4K |
278 | */ |
279 | #ifndef SCO_I2SPCM_IF_SAMPLE_RATE |
280 | #define SCO_I2SPCM_IF_SAMPLE_RATE 0 |
281 | #endif |
282 | |
283 | /* SCO_I2SPCM_IF_CLOCK_RATE |
284 | |
285 | 0 : 128K |
286 | 1 : 256K |
287 | 2 : 512K |
288 | 3 : 1024K |
289 | 4 : 2048K |
290 | */ |
291 | #ifndef SCO_I2SPCM_IF_CLOCK_RATE |
292 | #define SCO_I2SPCM_IF_CLOCK_RATE 1 |
293 | #endif |
294 | |
295 | /* SCO_I2SPCM_IF_CLOCK_RATE4WBS |
296 | |
297 | 0 : 128K |
298 | 1 : 256K |
299 | 2 : 512K |
300 | 3 : 1024K |
301 | 4 : 2048K |
302 | */ |
303 | #ifndef SCO_I2SPCM_IF_CLOCK_RATE4WBS |
304 | #define SCO_I2SPCM_IF_CLOCK_RATE4WBS 2 |
305 | #endif |
306 | |
307 | |
308 | #define SCO_PCM_PARAM_SIZE 5 |
309 | |
310 | /* SCO_PCM_ROUTING |
311 | |
312 | 0 : PCM |
313 | 1 : Transport |
314 | 2 : Codec |
315 | 3 : I2S |
316 | */ |
317 | #ifndef SCO_PCM_ROUTING |
318 | #define SCO_PCM_ROUTING 0 |
319 | #endif |
320 | |
321 | /* SCO_PCM_IF_CLOCK_RATE |
322 | |
323 | NOTICE: suggested to be consistent with SCO_I2SPCM_IF_CLOCK_RATE |
324 | |
325 | 0 : 128K |
326 | 1 : 256K |
327 | 2 : 512K |
328 | 3 : 1024K |
329 | 4 : 2048K |
330 | */ |
331 | #ifndef SCO_PCM_IF_CLOCK_RATE |
332 | #define SCO_PCM_IF_CLOCK_RATE 4 |
333 | #endif |
334 | |
335 | /* SCO_PCM_IF_FRAME_TYPE - 0=Short, 1=Long */ |
336 | #ifndef SCO_PCM_IF_FRAME_TYPE |
337 | #define SCO_PCM_IF_FRAME_TYPE 1 |
338 | #endif |
339 | |
340 | /* SCO_PCM_IF_SYNC_MODE |
341 | |
342 | NOTICE: in most usage cases the value will be the same as |
343 | SCO_PCM_IF_CLOCK_MODE setting |
344 | |
345 | 0 : Slave |
346 | 1 : Master |
347 | */ |
348 | #ifndef SCO_PCM_IF_SYNC_MODE |
349 | #define SCO_PCM_IF_SYNC_MODE 0 |
350 | #endif |
351 | |
352 | /* SCO_PCM_IF_CLOCK_MODE |
353 | |
354 | NOTICE: suggested to be consistent with SCO_I2SPCM_IF_ROLE |
355 | |
356 | 0 : Slave |
357 | 1 : Master |
358 | */ |
359 | #ifndef SCO_PCM_IF_CLOCK_MODE |
360 | #define SCO_PCM_IF_CLOCK_MODE 0 |
361 | #endif |
362 | |
363 | #define PCM_DATA_FORMAT_PARAM_SIZE 5 |
364 | |
365 | /* PCM_DATA_FMT_SHIFT_MODE |
366 | |
367 | 0 : MSB first |
368 | 1 : LSB first |
369 | */ |
370 | #ifndef PCM_DATA_FMT_SHIFT_MODE |
371 | #define PCM_DATA_FMT_SHIFT_MODE 0 |
372 | #endif |
373 | |
374 | /* PCM_DATA_FMT_FILL_BITS |
375 | |
376 | Specifies the value with which to fill unused bits |
377 | if Fill_Method is set to programmable |
378 | */ |
379 | #ifndef PCM_DATA_FMT_FILL_BITS |
380 | #define PCM_DATA_FMT_FILL_BITS 3 |
381 | #endif |
382 | |
383 | /* PCM_DATA_FMT_FILL_METHOD |
384 | |
385 | 0 : 0's |
386 | 1 : 1's |
387 | 2 : Signed |
388 | 3 : Programmable |
389 | */ |
390 | #ifndef PCM_DATA_FMT_FILL_METHOD |
391 | #define PCM_DATA_FMT_FILL_METHOD 3 |
392 | #endif |
393 | |
394 | /* PCM_DATA_FMT_FILL_NUM |
395 | |
396 | Specifies the number of bits to be filled |
397 | */ |
398 | #ifndef PCM_DATA_FMT_FILL_NUM |
399 | #define PCM_DATA_FMT_FILL_NUM 0 |
400 | #endif |
401 | |
402 | /* PCM_DATA_FMT_JUSTIFY_MODE |
403 | |
404 | 0 : Left justify (fill data shifted out last) |
405 | 1 : Right justify (fill data shifted out first) |
406 | */ |
407 | #ifndef PCM_DATA_FMT_JUSTIFY_MODE |
408 | #define PCM_DATA_FMT_JUSTIFY_MODE 0 |
409 | #endif |
410 | |
411 | /* HW_END_WITH_HCI_RESET |
412 | |
413 | Sample code implementation of sending a HCI_RESET command during the epilog |
414 | process. It calls back to the callers after command complete of HCI_RESET |
415 | is received. |
416 | */ |
417 | #ifndef HW_END_WITH_HCI_RESET |
418 | #define HW_END_WITH_HCI_RESET TRUE |
419 | #endif |
420 | |
421 | /****************************************************************************** |
422 | ** Extern variables and functions |
423 | ******************************************************************************/ |
424 | |
425 | extern bt_vendor_callbacks_t *bt_vendor_cbacks; |
426 | |
427 | extern int hw_set_audio_state(bt_vendor_op_audio_state_t *p_state); |
428 | |
429 | #endif /* BT_VENDOR_BRCM_H */ |
430 | |
431 |