| author | Yuxi Sun <yuxi.sun@amlogic.com> | 2017-04-24 03:27:15 (GMT) |
|---|---|---|
| committer | Yuxi Sun <yuxi.sun@amlogic.com> | 2017-04-24 05:32:14 (GMT) |
| commit | 8c84791e239180e1d5a7cfb7c8303a2e7408568e (patch) | |
| tree | a98db52f27e26522f11701149cba6ac611455711 | |
| parent | 42044dd898bd9d81a6dc2690ebafcb84d0d789a8 (diff) | |
| download | media-8c84791e239180e1d5a7cfb7c8303a2e7408568e.zip media-8c84791e239180e1d5a7cfb7c8303a2e7408568e.tar.gz media-8c84791e239180e1d5a7cfb7c8303a2e7408568e.tar.bz2 | |
Port h264 encoder CBR code to kernel 4.9
Change-Id: Ieb5fe3b3f33f0e4f4717f498faeb3d7a324fdf1b
Signed-off-by: Yuxi Sun <yuxi.sun@amlogic.com>
| -rw-r--r-- | drivers/common/firmware/firmware_cfg.h | 1 | ||||
| -rw-r--r-- | drivers/frame_sink/encoder/h264/encoder.c | 2735 | ||||
| -rw-r--r-- | drivers/frame_sink/encoder/h264/encoder.h | 498 |
3 files changed, 977 insertions, 2257 deletions
diff --git a/drivers/common/firmware/firmware_cfg.h b/drivers/common/firmware/firmware_cfg.h index c2caf9f..be919ff 100644 --- a/drivers/common/firmware/firmware_cfg.h +++ b/drivers/common/firmware/firmware_cfg.h @@ -27,5 +27,6 @@ {MESON_CPU_MAJOR_ID_GXL, VIDEO_DEC_H264, "h264.bin"}, {MESON_CPU_MAJOR_ID_GXL, VIDEO_DEC_H264_MULTI, "h264_multi.bin"}, {MESON_CPU_MAJOR_ID_GXM, VIDEO_ENC_H264, "gx_h264_enc.bin"}, +{MESON_CPU_MAJOR_ID_GXL, VIDEO_ENC_H264, "gx_h264_enc.bin"}, diff --git a/drivers/frame_sink/encoder/h264/encoder.c b/drivers/frame_sink/encoder/h264/encoder.c index 1ce9caf..1cd3524 100644 --- a/drivers/frame_sink/encoder/h264/encoder.c +++ b/drivers/frame_sink/encoder/h264/encoder.c @@ -33,8 +33,8 @@ #include <linux/amlogic/media/canvas/canvas_mgr.h> #include <linux/amlogic/media/codec_mm/codec_mm.h> -#include "linux/amlogic/media/utils/vdec_reg.h" -#include "../../../frame_provider/decoder/utils/vdec.h" +#include <linux/amlogic/media/utils/vdec_reg.h> +#include <../../../frame_provider/decoder/utils/vdec.h> #include <linux/delay.h> #include <linux/poll.h> #include <linux/of.h> @@ -42,7 +42,7 @@ #include <linux/dma-contiguous.h> #include <linux/kthread.h> #include <linux/sched/rt.h> -#include "linux/amlogic/media/utils/amports_config.h" +#include <linux/amlogic/media/utils/amports_config.h> #include "encoder.h" #include "../../../frame_provider/decoder/utils/amvdec.h" #include <linux/amlogic/media/utils/amlog.h> @@ -56,9 +56,8 @@ #define AMVENC_CANVAS_INDEX 0xE4 #define AMVENC_CANVAS_MAX_INDEX 0xEF -#define MIN_SIZE 20 +#define MIN_SIZE amvenc_buffspec[0].min_buffsize #define DUMP_INFO_BYTES_PER_MB 80 -/* #define USE_OLD_DUMP_MC */ #define ADJUSTED_QP_FLAG 64 @@ -71,34 +70,26 @@ static struct device *amvenc_avc_dev; static struct encode_manager_s encode_manager; #define MULTI_SLICE_MC -/*same as INIT_ENCODER*/ -#define INTRA_IN_P_TOP +#define H264_ENC_CBR +/* #define MORE_MODULE_PARAM */ #define ENC_CANVAS_OFFSET AMVENC_CANVAS_INDEX #define UCODE_MODE_FULL 0 -#define UCODE_MODE_SW_MIX 1 - -#ifdef USE_VDEC2 -#define STREAM_WR_PTR DOS_SCRATCH20 -#define DECODABLE_MB_Y DOS_SCRATCH21 -#define DECODED_MB_Y DOS_SCRATCH22 -#endif /* #define ENABLE_IGNORE_FUNCTION */ -static u32 anc0_buffer_id; static u32 ie_me_mb_type; static u32 ie_me_mode; static u32 ie_pippeline_block = 3; static u32 ie_cur_ref_sel; -static u32 avc_endian = 6; -static u32 clock_level = 1; -static u32 enable_dblk = 1; /* 0 disable, 1 vdec 2 hdec */ +/* static u32 avc_endian = 6; */ +static u32 clock_level = 5; static u32 encode_print_level = LOG_DEBUG; static u32 no_timeout; static int nr_mode = -1; +static u32 qp_table_debug; static u32 me_mv_merge_ctl = (0x1 << 31) | /* [31] me_merge_mv_en_16 */ @@ -131,25 +122,6 @@ static u32 me_f_skip_weight; static u32 me_sad_enough_01;/* 0x00018010; */ static u32 me_sad_enough_23;/* 0x00000020; */ -static u32 p_intra_config = (30 << 16) | (0xffff << 0); - -/* [31:16] TARGET_BITS_PER_MB */ -/* [15:8] MIN_QUANT */ -/* [7:0] MAX_QUANT */ -static u32 p_mb_quant_config = (20 << 16) | (24 << 8) | (24 << 0); - -/* [31:24] INC_4_BITS */ -/* [23:16] INC_3_BITS */ -/* [15:8] INC_2_BITS */ -/* [7:0] INC_1_BITS */ -static u32 p_mb_quant_inc_cfg = (20 << 24) | (15 << 16) | (10 << 8) | (5 << 0); - -/* [31:24] DEC_4_BITS */ -/* [23:16] DEC_3_BITS */ -/* [15:8] DEC_2_BITS */ -/* [7:0] DEC_1_BITS */ -static u32 p_mb_quant_dec_cfg = (60 << 24) | (40 << 16) | (30 << 8) | (20 << 0); - /* [31:0] NUM_ROWS_PER_SLICE_P */ /* [15:0] NUM_ROWS_PER_SLICE_I */ static u32 fixed_slice_cfg; @@ -308,8 +280,14 @@ static DEFINE_SPINLOCK(lock); #define v5_simple_dq_setting 0x43210fed #define v5_simple_me_weight_setting 0 -#ifndef USE_OLD_DUMP_MC -static u32 qp_table_pr; +#ifdef H264_ENC_CBR +#define CBR_TABLE_SIZE 0x800 +#define CBR_SHORT_SHIFT 12 /* same as disable */ +#define CBR_LONG_MB_NUM 2 +#define START_TABLE_ID 8 +#define CBR_LONG_THRESH 4 +#endif + static u32 v3_mv_sad[64] = { /* For step0 */ 0x00000004, @@ -380,210 +358,60 @@ static u32 v3_mv_sad[64] = { 0x003e0006, 0x003f0006 }; -#endif static struct BuffInfo_s amvenc_buffspec[] = { { - .lev_id = AMVENC_BUFFER_LEVEL_480P, - .max_width = 640, - .max_height = 480, - .min_buffsize = 0x580000, - .dct = { - .buf_start = 0, - .buf_size = 0xfe000, - }, - .dec0_y = { - .buf_start = 0x100000, - .buf_size = 0x80000, - }, - .dec1_y = { - .buf_start = 0x180000, - .buf_size = 0x80000, - }, - .assit = { - .buf_start = 0x240000, - .buf_size = 0xc0000, - }, - .bitstream = { - .buf_start = 0x300000, - .buf_size = 0x100000, - }, - .inter_bits_info = { - .buf_start = 0x400000, - .buf_size = 0x2000, - }, - .inter_mv_info = { - .buf_start = 0x402000, - .buf_size = 0x13000, - }, - .intra_bits_info = { - .buf_start = 0x420000, - .buf_size = 0x2000, - }, - .intra_pred_info = { - .buf_start = 0x422000, - .buf_size = 0x13000, - }, - .qp_info = { - .buf_start = 0x438000, - .buf_size = 0x8000, - }, - .scale_buff = { - .buf_start = 0, - .buf_size = 0, - } -#ifdef USE_VDEC2 - , - .vdec2_info = { - .buf_start = 0x440000, - .buf_size = 0x13e000, - } -#endif - }, { - .lev_id = AMVENC_BUFFER_LEVEL_720P, - .max_width = 1280, - .max_height = 720, - .min_buffsize = 0x9e0000, - .dct = { - .buf_start = 0, - .buf_size = 0x2f8000, - }, - .dec0_y = { - .buf_start = 0x300000, - .buf_size = 0x180000, - }, - .dec1_y = { - .buf_start = 0x480000, - .buf_size = 0x180000, - }, - .assit = { - .buf_start = 0x640000, - .buf_size = 0xc0000, - }, - .bitstream = { - .buf_start = 0x700000, - .buf_size = 0x100000, - }, - .inter_bits_info = { - .buf_start = 0x800000, - .buf_size = 0x4000, - }, - .inter_mv_info = { - .buf_start = 0x804000, - .buf_size = 0x40000, - }, - .intra_bits_info = { - .buf_start = 0x848000, - .buf_size = 0x4000, - }, - .intra_pred_info = { - .buf_start = 0x84c000, - .buf_size = 0x40000, - }, - .qp_info = { - .buf_start = 0x890000, - .buf_size = 0x8000, - }, - .scale_buff = { - .buf_start = 0, - .buf_size = 0, - } -#ifdef USE_VDEC2 - , - .vdec2_info = { - .buf_start = 0x8a0000, - .buf_size = 0x13e000, - } -#endif - }, { - .lev_id = AMVENC_BUFFER_LEVEL_1080P, + .lev_id = 0, .max_width = 1920, .max_height = 1088, - .min_buffsize = 0x1370000, + .min_buffsize = 0x1400000, .dct = { .buf_start = 0, - .buf_size = 0x6ba000, + .buf_size = 0x800000, /* 1920x1088x4 */ }, .dec0_y = { - .buf_start = 0x6d0000, + .buf_start = 0x800000, .buf_size = 0x300000, }, .dec1_y = { - .buf_start = 0x9d0000, + .buf_start = 0xb00000, .buf_size = 0x300000, }, .assit = { - .buf_start = 0xd10000, + .buf_start = 0xe10000, .buf_size = 0xc0000, }, .bitstream = { - .buf_start = 0xe00000, + .buf_start = 0xf00000, .buf_size = 0x100000, }, .scale_buff = { - .buf_start = 0xf00000, + .buf_start = 0x1000000, .buf_size = 0x300000, }, - .inter_bits_info = { - .buf_start = 0x1200000, - .buf_size = 0x8000, - }, - .inter_mv_info = { - .buf_start = 0x1208000, - .buf_size = 0x80000, - }, - .intra_bits_info = { - .buf_start = 0x1288000, - .buf_size = 0x8000, - }, - .intra_pred_info = { - .buf_start = 0x1290000, - .buf_size = 0x80000, + .dump_info = { + .buf_start = 0x1300000, + .buf_size = 0xa0000, /* (1920x1088/256)x80 */ }, - .qp_info = { - .buf_start = 0x1310000, - .buf_size = 0x8000, - } -#ifdef USE_VDEC2 - , - .vdec2_info = { - .buf_start = 0x12b0000, - .buf_size = 0x13e000, + .cbr_info = { + .buf_start = 0x13b0000, + .buf_size = 0x2000, } -#endif } }; enum ucode_type_e { - UCODE_DUMP = 0, - UCODE_DUMP_DBLK, - UCODE_DUMP_M2_DBLK, - UCODE_DUMP_GX_DBLK, - UCODE_SW, - UCODE_SW_HDEC_DBLK, - UCODE_SW_VDEC2_DBLK, - UCODE_SW_HDEC_M2_DBLK, - UCODE_SW_HDEC_GX_DBLK, - UCODE_VDEC2, UCODE_GX, UCODE_GXTV, + UCODE_GXL, UCODE_TXL, UCODE_MAX }; const char *ucode_name[] = { - "mix_dump_mc", - "mix_dump_mc_dblk", - "mix_dump_mc_m2_dblk", - "mix_dump_mc_gx_dblk", - "mix_sw_mc", - "mix_sw_mc_hdec_dblk", - "mix_sw_mc_vdec2_dblk", - "mix_sw_mc_hdec_m2_dblk", - "mix_sw_mc_hdec_gx_dblk", - "vdec2_encoder_mc", - "gx_h264_enc", + "h264_enc_mc_gx", "h264_enc_mc_gxtv", + "gx_h264_enc", "h264_enc_mc_txl", }; @@ -592,74 +420,25 @@ static void cache_flush(u32 buf_start , u32 buf_size); static const char *select_ucode(u32 ucode_index) { - enum ucode_type_e ucode = UCODE_DUMP; + enum ucode_type_e ucode = UCODE_GX; switch (ucode_index) { case UCODE_MODE_FULL: - if (get_cpu_type() >= MESON_CPU_MAJOR_ID_TXL) { -#ifndef USE_OLD_DUMP_MC + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_TXL) ucode = UCODE_TXL; -#else - ucode = UCODE_DUMP_GX_DBLK; -#endif - } else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL) { -#ifndef USE_OLD_DUMP_MC - ucode = UCODE_GX; -#else - ucode = UCODE_DUMP_GX_DBLK; -#endif - } else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB) { -#ifndef USE_OLD_DUMP_MC + else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL) + ucode = UCODE_GXL; + else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB) ucode = UCODE_GXTV; -#else - ucode = UCODE_DUMP_GX_DBLK; -#endif - } else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) { -#ifndef USE_OLD_DUMP_MC + else /* if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) */ ucode = UCODE_GX; -#else - ucode = UCODE_DUMP_GX_DBLK; -#endif - } else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_MG9TV) { - ucode = UCODE_DUMP_M2_DBLK; - } else { - if (enable_dblk) - ucode = UCODE_DUMP_DBLK; - else - ucode = UCODE_DUMP; - } break; - case UCODE_MODE_SW_MIX: - if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) { - ucode = UCODE_SW_HDEC_GX_DBLK; - } else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_MG9TV) { - ucode = UCODE_SW_HDEC_M2_DBLK; - } else if (get_cpu_type() == MESON_CPU_MAJOR_ID_M8B) { - if (enable_dblk) - ucode = UCODE_SW_HDEC_DBLK; - else - ucode = UCODE_SW; - } else { - if (enable_dblk == 1) - ucode = UCODE_SW_HDEC_DBLK; - else if (enable_dblk == 2) - ucode = UCODE_SW_VDEC2_DBLK; - else - ucode = UCODE_SW; - } break; default: break; } - - if (get_cpu_type() >= MESON_CPU_MAJOR_ID_MG9TV) - encode_manager.dblk_fix_flag = - (ucode_index == UCODE_MODE_SW_MIX); - else - encode_manager.dblk_fix_flag = false; return (const char *)ucode_name[ucode]; } -#ifndef USE_OLD_DUMP_MC static void hcodec_prog_qtbl(struct encode_wq_s *wq) { WRITE_HREG(HCODEC_Q_QUANT_CONTROL, @@ -667,66 +446,65 @@ static void hcodec_prog_qtbl(struct encode_wq_s *wq) (1 << 22)); /* quant_table_addr_update */ WRITE_HREG(HCODEC_QUANT_TABLE_DATA, - wq->quant_tbl_i4[wq->qp_table_id][0]); + wq->quant_tbl_i4[0]); WRITE_HREG(HCODEC_QUANT_TABLE_DATA, - wq->quant_tbl_i4[wq->qp_table_id][1]); + wq->quant_tbl_i4[1]); WRITE_HREG(HCODEC_QUANT_TABLE_DATA, - wq->quant_tbl_i4[wq->qp_table_id][2]); + wq->quant_tbl_i4[2]); WRITE_HREG(HCODEC_QUANT_TABLE_DATA, - wq->quant_tbl_i4[wq->qp_table_id][3]); + wq->quant_tbl_i4[3]); WRITE_HREG(HCODEC_QUANT_TABLE_DATA, - wq->quant_tbl_i4[wq->qp_table_id][4]); + wq->quant_tbl_i4[4]); WRITE_HREG(HCODEC_QUANT_TABLE_DATA, - wq->quant_tbl_i4[wq->qp_table_id][5]); + wq->quant_tbl_i4[5]); WRITE_HREG(HCODEC_QUANT_TABLE_DATA, - wq->quant_tbl_i4[wq->qp_table_id][6]); + wq->quant_tbl_i4[6]); WRITE_HREG(HCODEC_QUANT_TABLE_DATA, - wq->quant_tbl_i4[wq->qp_table_id][7]); + wq->quant_tbl_i4[7]); WRITE_HREG(HCODEC_Q_QUANT_CONTROL, (8 << 23) | /* quant_table_addr */ (1 << 22)); /* quant_table_addr_update */ WRITE_HREG(HCODEC_QUANT_TABLE_DATA, - wq->quant_tbl_i16[wq->qp_table_id][0]); + wq->quant_tbl_i16[0]); WRITE_HREG(HCODEC_QUANT_TABLE_DATA, - wq->quant_tbl_i16[wq->qp_table_id][1]); + wq->quant_tbl_i16[1]); WRITE_HREG(HCODEC_QUANT_TABLE_DATA, - wq->quant_tbl_i16[wq->qp_table_id][2]); + wq->quant_tbl_i16[2]); WRITE_HREG(HCODEC_QUANT_TABLE_DATA, - wq->quant_tbl_i16[wq->qp_table_id][3]); + wq->quant_tbl_i16[3]); WRITE_HREG(HCODEC_QUANT_TABLE_DATA, - wq->quant_tbl_i16[wq->qp_table_id][4]); + wq->quant_tbl_i16[4]); WRITE_HREG(HCODEC_QUANT_TABLE_DATA, - wq->quant_tbl_i16[wq->qp_table_id][5]); + wq->quant_tbl_i16[5]); WRITE_HREG(HCODEC_QUANT_TABLE_DATA, - wq->quant_tbl_i16[wq->qp_table_id][6]); + wq->quant_tbl_i16[6]); WRITE_HREG(HCODEC_QUANT_TABLE_DATA, - wq->quant_tbl_i16[wq->qp_table_id][7]); + wq->quant_tbl_i16[7]); WRITE_HREG(HCODEC_Q_QUANT_CONTROL, (16 << 23) | /* quant_table_addr */ (1 << 22)); /* quant_table_addr_update */ WRITE_HREG(HCODEC_QUANT_TABLE_DATA, - wq->quant_tbl_me[wq->qp_table_id][0]); + wq->quant_tbl_me[0]); WRITE_HREG(HCODEC_QUANT_TABLE_DATA, - wq->quant_tbl_me[wq->qp_table_id][1]); + wq->quant_tbl_me[1]); WRITE_HREG(HCODEC_QUANT_TABLE_DATA, - wq->quant_tbl_me[wq->qp_table_id][2]); + wq->quant_tbl_me[2]); WRITE_HREG(HCODEC_QUANT_TABLE_DATA, - wq->quant_tbl_me[wq->qp_table_id][3]); + wq->quant_tbl_me[3]); WRITE_HREG(HCODEC_QUANT_TABLE_DATA, - wq->quant_tbl_me[wq->qp_table_id][4]); + wq->quant_tbl_me[4]); WRITE_HREG(HCODEC_QUANT_TABLE_DATA, - wq->quant_tbl_me[wq->qp_table_id][5]); + wq->quant_tbl_me[5]); WRITE_HREG(HCODEC_QUANT_TABLE_DATA, - wq->quant_tbl_me[wq->qp_table_id][6]); + wq->quant_tbl_me[6]); WRITE_HREG(HCODEC_QUANT_TABLE_DATA, - wq->quant_tbl_me[wq->qp_table_id][7]); + wq->quant_tbl_me[7]); return; } -#endif static void InitEncodeWeight(void) { @@ -749,74 +527,60 @@ static void InitEncodeWeight(void) /* [11:0] me_merge_min_sad - SAD >= 0x180 can be merged with other MV */ - /* need add a condition for ucode mode */ - if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) { - me_mv_weight_01 = (ME_MV_STEP_WEIGHT_1 << 24) | - (ME_MV_PRE_WEIGHT_1 << 16) | - (ME_MV_STEP_WEIGHT_0 << 8) | - (ME_MV_PRE_WEIGHT_0 << 0); - - me_mv_weight_23 = (ME_MV_STEP_WEIGHT_3 << 24) | - (ME_MV_PRE_WEIGHT_3 << 16) | - (ME_MV_STEP_WEIGHT_2 << 8) | - (ME_MV_PRE_WEIGHT_2 << 0); - - me_sad_range_inc = (ME_SAD_RANGE_3 << 24) | - (ME_SAD_RANGE_2 << 16) | - (ME_SAD_RANGE_1 << 8) | - (ME_SAD_RANGE_0 << 0); - - me_step0_close_mv = (0x100 << 10) | - /* me_step0_big_sad -- two MV sad - diff bigger will use use 1 */ - (2 << 5) | /* me_step0_close_mv_y */ - (2 << 0); /* me_step0_close_mv_x */ - - me_f_skip_sad = (0x00 << 24) | /* force_skip_sad_3 */ - (STEP_2_SKIP_SAD << 16) | /* force_skip_sad_2 */ - (STEP_1_SKIP_SAD << 8) | /* force_skip_sad_1 */ - (STEP_0_SKIP_SAD << 0); /* force_skip_sad_0 */ - - me_f_skip_weight = (0x00 << 24) | /* force_skip_weight_3 */ - /* force_skip_weight_2 */ - (STEP_2_SKIP_WEIGHT << 16) | - /* force_skip_weight_1 */ - (STEP_1_SKIP_WEIGHT << 8) | - /* force_skip_weight_0 */ - (STEP_0_SKIP_WEIGHT << 0); - -#ifndef USE_OLD_DUMP_MC - if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB) { - me_f_skip_sad = 0; - me_f_skip_weight = 0; - me_mv_weight_01 = 0; - me_mv_weight_23 = 0; - } -#endif - me_sad_enough_01 = (ME_SAD_ENOUGH_1_DATA << 12) | - /* me_sad_enough_1 */ - (ME_SAD_ENOUGH_0_DATA << 0) | - /* me_sad_enough_0 */ - (0 << 12) | /* me_sad_enough_1 */ - (0 << 0); /* me_sad_enough_0 */ - - me_sad_enough_23 = (ADV_MV_8x8_ENOUGH_DATA << 12) | - /* adv_mv_8x8_enough */ - (ME_SAD_ENOUGH_2_DATA << 0) | - /* me_sad_enough_2 */ - (0 << 12) | /* me_sad_enough_3 */ - (0 << 0); /* me_sad_enough_2 */ - } else { - me_mv_weight_01 = (0x40 << 24) | (0x30 << 16) | - (0x20 << 8) | 0x30; - me_mv_weight_23 = (0x40 << 8) | 0x30; - me_sad_range_inc = 0x01010101; /* 0x03030303; */ - me_step0_close_mv = 0x0000ac21; /* 0x003ffc21; */ - me_f_skip_sad = 0x18181818; - me_f_skip_weight = 0x12121212; - me_sad_enough_01 = 0; - me_sad_enough_23 = 0; + me_mv_weight_01 = (ME_MV_STEP_WEIGHT_1 << 24) | + (ME_MV_PRE_WEIGHT_1 << 16) | + (ME_MV_STEP_WEIGHT_0 << 8) | + (ME_MV_PRE_WEIGHT_0 << 0); + + me_mv_weight_23 = (ME_MV_STEP_WEIGHT_3 << 24) | + (ME_MV_PRE_WEIGHT_3 << 16) | + (ME_MV_STEP_WEIGHT_2 << 8) | + (ME_MV_PRE_WEIGHT_2 << 0); + + me_sad_range_inc = (ME_SAD_RANGE_3 << 24) | + (ME_SAD_RANGE_2 << 16) | + (ME_SAD_RANGE_1 << 8) | + (ME_SAD_RANGE_0 << 0); + + me_step0_close_mv = (0x100 << 10) | + /* me_step0_big_sad -- two MV sad + diff bigger will use use 1 */ + (2 << 5) | /* me_step0_close_mv_y */ + (2 << 0); /* me_step0_close_mv_x */ + + me_f_skip_sad = (0x00 << 24) | /* force_skip_sad_3 */ + (STEP_2_SKIP_SAD << 16) | /* force_skip_sad_2 */ + (STEP_1_SKIP_SAD << 8) | /* force_skip_sad_1 */ + (STEP_0_SKIP_SAD << 0); /* force_skip_sad_0 */ + + me_f_skip_weight = (0x00 << 24) | /* force_skip_weight_3 */ + /* force_skip_weight_2 */ + (STEP_2_SKIP_WEIGHT << 16) | + /* force_skip_weight_1 */ + (STEP_1_SKIP_WEIGHT << 8) | + /* force_skip_weight_0 */ + (STEP_0_SKIP_WEIGHT << 0); + + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB) { + me_f_skip_sad = 0; + me_f_skip_weight = 0; + me_mv_weight_01 = 0; + me_mv_weight_23 = 0; } + + me_sad_enough_01 = (ME_SAD_ENOUGH_1_DATA << 12) | + /* me_sad_enough_1 */ + (ME_SAD_ENOUGH_0_DATA << 0) | + /* me_sad_enough_0 */ + (0 << 12) | /* me_sad_enough_1 */ + (0 << 0); /* me_sad_enough_0 */ + + me_sad_enough_23 = (ADV_MV_8x8_ENOUGH_DATA << 12) | + /* adv_mv_8x8_enough */ + (ME_SAD_ENOUGH_2_DATA << 0) | + /* me_sad_enough_2 */ + (0 << 12) | /* me_sad_enough_3 */ + (0 << 0); /* me_sad_enough_2 */ } /*output stream buffer setting*/ @@ -878,54 +642,22 @@ static void avc_init_encoder(struct encode_wq_s *wq, bool idr) WRITE_HREG(HCODEC_VLC_TOTAL_BYTES, 0); WRITE_HREG(HCODEC_VLC_CONFIG, 0x07); WRITE_HREG(HCODEC_VLC_INT_CONTROL, 0); -#ifndef USE_OLD_DUMP_MC - if ((get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) && - (encode_manager.ucode_index == UCODE_MODE_FULL)) { - WRITE_HREG(HCODEC_ASSIST_AMR1_INT0, 0x15); - WRITE_HREG(HCODEC_ASSIST_AMR1_INT1, 0x8); - WRITE_HREG(HCODEC_ASSIST_AMR1_INT3, 0x14); - } else -#endif - { - WRITE_HREG(HCODEC_ASSIST_AMR1_INT0, 0x15); -#ifdef MULTI_SLICE_MC - if (encode_manager.dblk_fix_flag) { - WRITE_HREG(HCODEC_ASSIST_AMR1_INT2, 0x19); - WRITE_HREG(HCODEC_ASSIST_AMR1_INT1, 0x8); - } else { - WRITE_HREG(HCODEC_ASSIST_AMR1_INT1, 0x19); - WRITE_HREG(HCODEC_ASSIST_AMR1_INT2, 0x8); - } -#else - if (encode_manager.dblk_fix_flag) - WRITE_HREG(HCODEC_ASSIST_AMR1_INT1, 0x8); - else - WRITE_HREG(HCODEC_ASSIST_AMR1_INT2, 0x8); -#endif - WRITE_HREG(HCODEC_ASSIST_AMR1_INT3, 0x14); -#ifdef INTRA_IN_P_TOP - WRITE_HREG(HCODEC_ASSIST_DMA_INT_MSK, 0xfd); - WRITE_HREG(HCODEC_ASSIST_DMA_INT_MSK2, 0xff); - WRITE_HREG(HCODEC_ASSIST_AMR1_INT4, 0x18); - /* mtspi 0xfd, HCODEC_ASSIST_DMA_INT_MSK - enable lmem_mpeg_dma_int */ - /* mtspi 0xff, HCODEC_ASSIST_DMA_INT_MSK2 - disable cpu19_int */ - /* mtspi 0x18, HCODEC_ASSIST_AMR1_INT4 // lmem_dma_isr */ -#else - WRITE_HREG(HCODEC_ASSIST_DMA_INT_MSK, 0xff); - WRITE_HREG(HCODEC_ASSIST_DMA_INT_MSK2, 0xff); -#endif - } + + WRITE_HREG(HCODEC_ASSIST_AMR1_INT0, 0x15); + WRITE_HREG(HCODEC_ASSIST_AMR1_INT1, 0x8); + WRITE_HREG(HCODEC_ASSIST_AMR1_INT3, 0x14); + WRITE_HREG(IDR_PIC_ID, wq->pic.idr_pic_id); - WRITE_HREG(FRAME_NUMBER, (idr == true) ? 0 : wq->pic.frame_number); + WRITE_HREG(FRAME_NUMBER, + (idr == true) ? 0 : wq->pic.frame_number); WRITE_HREG(PIC_ORDER_CNT_LSB, - (idr == true) ? 0 : wq->pic.pic_order_cnt_lsb); + (idr == true) ? 0 : wq->pic.pic_order_cnt_lsb); WRITE_HREG(LOG2_MAX_PIC_ORDER_CNT_LSB, - wq->pic.log2_max_pic_order_cnt_lsb); - WRITE_HREG(LOG2_MAX_FRAME_NUM, wq->pic.log2_max_frame_num); - WRITE_HREG(ANC0_BUFFER_ID, anc0_buffer_id); + wq->pic.log2_max_pic_order_cnt_lsb); + WRITE_HREG(LOG2_MAX_FRAME_NUM, + wq->pic.log2_max_frame_num); + WRITE_HREG(ANC0_BUFFER_ID, 0); WRITE_HREG(QPPICTURE, wq->pic.init_qppicture); } @@ -938,46 +670,47 @@ static void avc_canvas_init(struct encode_wq_s *wq) canvas_height = ((wq->pic.encoder_height + 15) >> 4) << 4; canvas_config(ENC_CANVAS_OFFSET, - start_addr + wq->mem.bufspec.dec0_y.buf_start, - canvas_width, canvas_height, - CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR); + start_addr + wq->mem.bufspec.dec0_y.buf_start, + canvas_width, canvas_height, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR); canvas_config(1 + ENC_CANVAS_OFFSET, - start_addr + wq->mem.bufspec.dec0_uv.buf_start, - canvas_width, canvas_height / 2, - CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR); + start_addr + wq->mem.bufspec.dec0_uv.buf_start, + canvas_width, canvas_height / 2, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR); /*here the third plane use the same address as the second plane*/ canvas_config(2 + ENC_CANVAS_OFFSET, - start_addr + wq->mem.bufspec.dec0_uv.buf_start, - canvas_width, canvas_height / 2, - CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR); + start_addr + wq->mem.bufspec.dec0_uv.buf_start, + canvas_width, canvas_height / 2, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR); canvas_config(3 + ENC_CANVAS_OFFSET, - start_addr + wq->mem.bufspec.dec1_y.buf_start, - canvas_width, canvas_height, - CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR); + start_addr + wq->mem.bufspec.dec1_y.buf_start, + canvas_width, canvas_height, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR); canvas_config(4 + ENC_CANVAS_OFFSET, - start_addr + wq->mem.bufspec.dec1_uv.buf_start, - canvas_width, canvas_height / 2, - CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR); + start_addr + wq->mem.bufspec.dec1_uv.buf_start, + canvas_width, canvas_height / 2, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR); /*here the third plane use the same address as the second plane*/ canvas_config(5 + ENC_CANVAS_OFFSET, - start_addr + wq->mem.bufspec.dec1_uv.buf_start, - canvas_width, canvas_height / 2, - CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR); + start_addr + wq->mem.bufspec.dec1_uv.buf_start, + canvas_width, canvas_height / 2, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR); } static void avc_buffspec_init(struct encode_wq_s *wq) { u32 canvas_width, canvas_height; u32 start_addr = wq->mem.buf_start; + u32 mb_w = (wq->pic.encoder_width + 15) >> 4; + u32 mb_h = (wq->pic.encoder_height + 15) >> 4; + u32 mbs = mb_w * mb_h; canvas_width = ((wq->pic.encoder_width + 31) >> 5) << 5; canvas_height = ((wq->pic.encoder_height + 15) >> 4) << 4; - /*input dct buffer config */ - /* (w>>4)*(h>>4)*864 */ wq->mem.dct_buff_start_addr = start_addr + - wq->mem.bufspec.dct.buf_start; + wq->mem.bufspec.dct.buf_start; wq->mem.dct_buff_end_addr = wq->mem.dct_buff_start_addr + wq->mem.bufspec.dct.buf_size - 1; @@ -1002,114 +735,59 @@ static void avc_buffspec_init(struct encode_wq_s *wq) wq->mem.BitstreamEnd = wq->mem.BitstreamStart + wq->mem.bufspec.bitstream.buf_size - 1; - -#ifndef USE_OLD_DUMP_MC - if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) { - u32 mb_w = (wq->pic.encoder_width + 15) >> 4; - u32 mb_h = (wq->pic.encoder_height + 15) >> 4; - u32 mbs = mb_w * mb_h; - wq->mem.dump_info_ddr_size = - DUMP_INFO_BYTES_PER_MB * mbs; - wq->mem.dump_info_ddr_size = - (wq->mem.dump_info_ddr_size + PAGE_SIZE - 1) - & ~(PAGE_SIZE - 1); - } else { - wq->mem.dump_info_ddr_start_addr = 0; - wq->mem.dump_info_ddr_size = 0; - } -#else - wq->mem.dump_info_ddr_start_addr = 0; - wq->mem.dump_info_ddr_size = 0; -#endif - enc_pr(LOG_INFO, "BitstreamStart is 0x%x, wq: %p.\n", wq->mem.BitstreamStart, (void *)wq); - wq->mem.dblk_buf_canvas = ((ENC_CANVAS_OFFSET + 2) << 16) | - ((ENC_CANVAS_OFFSET + 1) << 8) | - (ENC_CANVAS_OFFSET); - wq->mem.ref_buf_canvas = ((ENC_CANVAS_OFFSET + 5) << 16) | - ((ENC_CANVAS_OFFSET + 4) << 8) | - (ENC_CANVAS_OFFSET + 3); -} - -#ifdef USE_VDEC2 -static s32 abort_vdec2_flag; -void AbortEncodeWithVdec2(s32 abort) -{ - abort_vdec2_flag = abort; + wq->mem.scaler_buff_start_addr = + wq->mem.buf_start + wq->mem.bufspec.scale_buff.buf_start; + wq->mem.dump_info_ddr_start_addr = + wq->mem.buf_start + wq->mem.bufspec.dump_info.buf_start; +enc_pr(LOG_INFO, "CBR: dump_info_ddr_start_addr:%x.\n", wq->mem.dump_info_ddr_start_addr); +enc_pr(LOG_INFO, "CBR: buf_start :%d.\n", wq->mem.buf_start); +enc_pr(LOG_INFO, "CBR: dump_info.buf_start :%d.\n", wq->mem.bufspec.dump_info.buf_start); + wq->mem.dump_info_ddr_size = + DUMP_INFO_BYTES_PER_MB * mbs; + wq->mem.dump_info_ddr_size = + (wq->mem.dump_info_ddr_size + PAGE_SIZE - 1) + & ~(PAGE_SIZE - 1); + wq->mem.cbr_info_ddr_start_addr = + wq->mem.buf_start + wq->mem.bufspec.cbr_info.buf_start; + wq->mem.cbr_info_ddr_size = + wq->mem.bufspec.cbr_info.buf_size; + + wq->mem.dblk_buf_canvas = + ((ENC_CANVAS_OFFSET + 2) << 16) | + ((ENC_CANVAS_OFFSET + 1) << 8) | + (ENC_CANVAS_OFFSET); + wq->mem.ref_buf_canvas = + ((ENC_CANVAS_OFFSET + 5) << 16) | + ((ENC_CANVAS_OFFSET + 4) << 8) | + (ENC_CANVAS_OFFSET + 3); } -#endif static void avc_init_ie_me_parameter(struct encode_wq_s *wq, u32 quant) { -#ifndef USE_OLD_DUMP_MC - if ((get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) && - (encode_manager.ucode_index == UCODE_MODE_FULL)) { - ie_cur_ref_sel = 0; - ie_pippeline_block = 12; - /* currently disable half and sub pixel */ - ie_me_mode |= (ie_pippeline_block & IE_PIPPELINE_BLOCK_MASK) << - IE_PIPPELINE_BLOCK_SHIFT; - } else -#endif - { - ie_pippeline_block = 3; - if (ie_pippeline_block == 3) - ie_cur_ref_sel = ((1 << 13) | (1 << 12) | - (1 << 9) | (1 << 8)); - else if (ie_pippeline_block == 0) - ie_cur_ref_sel = 0xffffffff; - else { - enc_pr(LOG_ERROR, - "Error : Please calculate IE_CUR_REF_SEL for IE_PIPPELINE_BLOCK. wq:%p\n", - (void *)wq); - } - /* currently disable half and sub pixel */ - ie_me_mode |= (ie_pippeline_block & IE_PIPPELINE_BLOCK_MASK) << - IE_PIPPELINE_BLOCK_SHIFT; - } + ie_cur_ref_sel = 0; + ie_pippeline_block = 12; + /* currently disable half and sub pixel */ + ie_me_mode = + (ie_pippeline_block & IE_PIPPELINE_BLOCK_MASK) << + IE_PIPPELINE_BLOCK_SHIFT; WRITE_HREG(IE_ME_MODE, ie_me_mode); WRITE_HREG(IE_REF_SEL, ie_cur_ref_sel); WRITE_HREG(IE_ME_MB_TYPE, ie_me_mb_type); - -#ifndef USE_OLD_DUMP_MC - if ((get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) && - (encode_manager.ucode_index == UCODE_MODE_FULL)) { - if (fixed_slice_cfg) - WRITE_HREG(FIXED_SLICE_CFG, fixed_slice_cfg); - else if (wq->pic.rows_per_slice != - (wq->pic.encoder_height + 15) >> 4) { - u32 mb_per_slice = (wq->pic.encoder_height + 15) >> 4; - mb_per_slice = mb_per_slice * wq->pic.rows_per_slice; - WRITE_HREG(FIXED_SLICE_CFG, mb_per_slice); - } else - WRITE_HREG(FIXED_SLICE_CFG, 0); +#ifdef MULTI_SLICE_MC + if (fixed_slice_cfg) + WRITE_HREG(FIXED_SLICE_CFG, fixed_slice_cfg); + else if (wq->pic.rows_per_slice != + (wq->pic.encoder_height + 15) >> 4) { + u32 mb_per_slice = (wq->pic.encoder_height + 15) >> 4; + mb_per_slice = mb_per_slice * wq->pic.rows_per_slice; + WRITE_HREG(FIXED_SLICE_CFG, mb_per_slice); } else -#endif - { - if (fixed_slice_cfg) - WRITE_HREG(FIXED_SLICE_CFG, fixed_slice_cfg); - else if (wq->pic.rows_per_slice != - (wq->pic.encoder_height + 15) >> 4) - WRITE_HREG(FIXED_SLICE_CFG, - (wq->pic.rows_per_slice << 16) | - wq->pic.rows_per_slice); - else - WRITE_HREG(FIXED_SLICE_CFG, 0); - WRITE_HREG(P_INTRA_CONFIG, p_intra_config); - WRITE_HREG(P_MB_QUANT_CONFIG, p_mb_quant_config); - if (encode_manager.ucode_index != UCODE_MODE_SW_MIX) { - p_mb_quant_config = (20 << 16) | - (quant << 8) | - (quant << 0); - WRITE_HREG(P_MB_QUANT_CONFIG, p_mb_quant_config); - } - WRITE_HREG(P_MB_QUANT_INC_CFG, p_mb_quant_inc_cfg); - WRITE_HREG(P_MB_QUANT_DEC_CFG, p_mb_quant_dec_cfg); - } -#ifndef MULTI_SLICE_MC + WRITE_HREG(FIXED_SLICE_CFG, 0); +#else WRITE_HREG(FIXED_SLICE_CFG, 0); #endif } @@ -1128,8 +806,8 @@ static void avc_init_ie_me_parameter(struct encode_wq_s *wq, u32 quant) #define HCODEC_MFDIN_REG16 (HCODEC_MFDIN_REGB_AMPC + 0xb) static void mfdin_basic(u32 input, u8 iformat, - u8 oformat, u32 picsize_x, u32 picsize_y, - u8 r2y_en, u8 nr, u8 ifmt_extra) + u8 oformat, u32 picsize_x, u32 picsize_y, + u8 r2y_en, u8 nr, u8 ifmt_extra) { u8 dsample_en; /* Downsample Enable */ u8 interp_en; /* Interpolation Enable */ @@ -1174,19 +852,21 @@ static void mfdin_basic(u32 input, u8 iformat, ifmt_extra = 0; ifmt444 = ((iformat == 1) || (iformat == 5) || (iformat == 8) || - (iformat == 9) || (iformat == 12)) ? 1 : 0; + (iformat == 9) || (iformat == 12)) ? 1 : 0; if (iformat == 7 && ifmt_extra == 1) ifmt444 = 1; ifmt422 = ((iformat == 0) || (iformat == 10)) ? 1 : 0; if (iformat == 7 && ifmt_extra != 1) ifmt422 = 1; ifmt420 = ((iformat == 2) || (iformat == 3) || (iformat == 4) || - (iformat == 11)) ? 1 : 0; + (iformat == 11)) ? 1 : 0; dsample_en = ((ifmt444 && (oformat != 2)) || - (ifmt422 && (oformat == 0))) ? 1 : 0; + (ifmt422 && (oformat == 0))) ? 1 : 0; interp_en = ((ifmt422 && (oformat == 2)) || - (ifmt420 && (oformat != 0))) ? 1 : 0; + (ifmt420 && (oformat != 0))) ? 1 : 0; y_size = (oformat != 0) ? 1 : 0; + if (iformat == 12) + y_size = 0; r2y_mode = (r2y_en == 1) ? 1 : 0; /* Fixed to 1 (TODO) */ canv_idx0_bppx = (iformat == 1) ? 3 : (iformat == 0) ? 2 : 1; canv_idx1_bppx = (iformat == 4) ? 0 : 1; @@ -1201,7 +881,10 @@ static void mfdin_basic(u32 input, u8 iformat, linear_bytes4p = 1; else linear_bytes4p = 0; - linear_bytesperline = picsize_x * linear_bytes4p; + if (iformat == 12) + linear_bytesperline = picsize_x * 4; + else + linear_bytesperline = picsize_x * linear_bytes4p; if (iformat < 8) linear_enable = false; @@ -1326,10 +1009,16 @@ static void mfdin_basic(u32 input, u8 iformat, WRITE_HREG((HCODEC_MFDIN_REG5_LNR1 + reg_offset), input); } - WRITE_HREG((HCODEC_MFDIN_REG9_ENDN + reg_offset), - (7 << 0) | (6 << 3) | (5 << 6) | - (4 << 9) | (3 << 12) | (2 << 15) | - (1 << 18) | (0 << 21)); + if (iformat == 12) + WRITE_HREG((HCODEC_MFDIN_REG9_ENDN + reg_offset), + (2 << 0) | (1 << 3) | (0 << 6) | + (3 << 9) | (6 << 12) | (5 << 15) | + (4 << 18) | (7 << 21)); + else + WRITE_HREG((HCODEC_MFDIN_REG9_ENDN + reg_offset), + (7 << 0) | (6 << 3) | (5 << 6) | + (4 << 9) | (3 << 12) | (2 << 15) | + (1 << 18) | (0 << 21)); } #ifdef CONFIG_AM_GE2D @@ -1481,7 +1170,7 @@ static s32 set_input_format(struct encode_wq_s *wq, { s32 ret = 0; u8 iformat = MAX_FRAME_FMT, oformat = MAX_FRAME_FMT, r2y_en = 0; - u32 picsize_x, picsize_y; + u32 picsize_x, picsize_y, src_addr; u32 canvas_w = 0; u32 input = request->src; u8 ifmt_extra = 0; @@ -1494,67 +1183,39 @@ static s32 set_input_format(struct encode_wq_s *wq, oformat = 0; if ((request->type == LOCAL_BUFF) || (request->type == PHYSICAL_BUFF)) { + if ((request->type == LOCAL_BUFF) && + (request->flush_flag & AMVENC_FLUSH_FLAG_INPUT)) + dma_flush(wq->mem.dct_buff_start_addr, + request->framesize); if (request->type == LOCAL_BUFF) { - if (request->flush_flag & AMVENC_FLUSH_FLAG_INPUT) - dma_flush(wq->mem.dct_buff_start_addr, - request->framesize); - if (request->scale_enable) { -#ifdef CONFIG_AM_GE2D - struct config_para_ex_s ge2d_config; - u32 src_addr = - wq->mem.dct_buff_start_addr; - memset(&ge2d_config, 0, - sizeof(struct config_para_ex_s)); - if (request->flush_flag & - AMVENC_FLUSH_FLAG_INPUT) { - int scale_size = - scale_frame( - wq, request, - &ge2d_config, - src_addr, - false); - if (scale_size > 0) - cache_flush( - wq->mem.scaler_buff_start_addr, - scale_size); - } -#else - enc_pr(LOG_ERROR, - "Warning: need enable ge2d for scale frame!\n"); - return -1; -#endif - iformat = 2; - r2y_en = 0; - input = ((ENC_CANVAS_OFFSET + 7) << 8) | - (ENC_CANVAS_OFFSET + 6); - ret = 0; - goto MFDIN; - } else { - input = wq->mem.dct_buff_start_addr; - } + input = wq->mem.dct_buff_start_addr; + src_addr = + wq->mem.dct_buff_start_addr; } else { + src_addr = input; picsize_y = wq->pic.encoder_height; - if (request->scale_enable) { + } + if (request->scale_enable) { #ifdef CONFIG_AM_GE2D - struct config_para_ex_s ge2d_config; - memset(&ge2d_config, 0, - sizeof(struct config_para_ex_s)); - scale_frame( - wq, request, - &ge2d_config, - input, false); - iformat = 2; - r2y_en = 0; - input = ((ENC_CANVAS_OFFSET + 7) << 8) | - (ENC_CANVAS_OFFSET + 6); - ret = 0; - goto MFDIN; + struct config_para_ex_s ge2d_config; + memset(&ge2d_config, 0, + sizeof(struct config_para_ex_s)); + scale_frame( + wq, request, + &ge2d_config, + src_addr, + false); + iformat = 2; + r2y_en = 0; + input = ((ENC_CANVAS_OFFSET + 7) << 8) | + (ENC_CANVAS_OFFSET + 6); + ret = 0; + goto MFDIN; #else - enc_pr(LOG_ERROR, - "Warning: need enable ge2d for scale frame!\n"); - return -1; + enc_pr(LOG_ERROR, + "Warning: need enable ge2d for scale frame!\n"); + return -1; #endif - } } if ((request->fmt <= FMT_YUV444_PLANE) || (request->fmt >= FMT_YUV422_12BIT)) @@ -1667,7 +1328,7 @@ static s32 set_input_format(struct encode_wq_s *wq, struct config_para_ex_s ge2d_config; memset(&ge2d_config, 0, sizeof(struct config_para_ex_s)); - scale_frame( + scale_frame( wq, request, &ge2d_config, input, true); @@ -1711,16 +1372,39 @@ static s32 set_input_format(struct encode_wq_s *wq, } else ret = -1; } -MFDIN: + if (ret == 0) mfdin_basic(input, iformat, oformat, picsize_x, picsize_y, r2y_en, - (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) ? - request->nr_mode : 0, ifmt_extra); - wq->control.finish = true; + request->nr_mode, ifmt_extra); return ret; } +#ifdef H264_ENC_CBR +static void ConvertTable2Risc(void *table, u32 len) +{ + u32 i, j; + u16 temp; + u16 *tbl = (u16 *)table; + if ((len < 8) || (len % 8) || (!table)) { + enc_pr(LOG_ERROR, "ConvertTable2Risc tbl %p, len %d error\n", + table, len); + return; + } + for (i = 0; i < len / 8; i++) { + j = i << 2; + temp = tbl[j]; + tbl[j] = tbl[j + 3]; + tbl[j + 3] = temp; + + temp = tbl[j + 1]; + tbl[j + 1] = tbl[j + 2]; + tbl[j + 2] = temp; + } + +} +#endif + static void avc_prot_init(struct encode_wq_s *wq, struct encode_request_s *request, u32 quant, bool IDR) { @@ -1730,6 +1414,8 @@ static void avc_prot_init(struct encode_wq_s *wq, u32 pic_mbx, pic_mby; u32 i_pic_qp, p_pic_qp; u32 i_pic_qp_c, p_pic_qp_c; + u32 pic_width_in_mb; + u32 slice_qp; pic_width = wq->pic.encoder_width; pic_height = wq->pic.encoder_height; pic_mb_nr = 0; @@ -1738,170 +1424,177 @@ static void avc_prot_init(struct encode_wq_s *wq, i_pic_qp = quant; p_pic_qp = quant; -#ifndef USE_OLD_DUMP_MC - if ((get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) && - (encode_manager.ucode_index == UCODE_MODE_FULL)) { - u32 pic_width_in_mb; - u32 slice_qp; - pic_width_in_mb = (pic_width + 15) / 16; - WRITE_HREG(HCODEC_HDEC_MC_OMEM_AUTO, - (1 << 31) | /* use_omem_mb_xy */ - ((pic_width_in_mb - 1) << 16)); /* omem_max_mb_x */ - - WRITE_HREG(HCODEC_VLC_ADV_CONFIG, - /* early_mix_mc_hcmd -- will enable in P Picture */ - (0 << 10) | - (1 << 9) | /* update_top_left_mix */ - (1 << 8) | /* p_top_left_mix */ - /* mv_cal_mixed_type -- will enable in P Picture */ - (0 << 7) | - /* mc_hcmd_mixed_type -- will enable in P Picture */ - (0 << 6) | - (1 << 5) | /* use_seperate_int_control */ - (1 << 4) | /* hcmd_intra_use_q_info */ - (1 << 3) | /* hcmd_left_use_prev_info */ - (1 << 2) | /* hcmd_use_q_info */ - (1 << 1) | /* use_q_delta_quant */ - /* detect_I16_from_I4 use qdct detected mb_type */ - (0 << 0)); - - WRITE_HREG(HCODEC_QDCT_ADV_CONFIG, - (1 << 29) | /* mb_info_latch_no_I16_pred_mode */ - (1 << 28) | /* ie_dma_mbxy_use_i_pred */ - (1 << 27) | /* ie_dma_read_write_use_ip_idx */ - (1 << 26) | /* ie_start_use_top_dma_count */ - (1 << 25) | /* i_pred_top_dma_rd_mbbot */ - (1 << 24) | /* i_pred_top_dma_wr_disable */ - /* i_pred_mix -- will enable in P Picture */ - (0 << 23) | - (1 << 22) | /* me_ab_rd_when_intra_in_p */ - (1 << 21) | /* force_mb_skip_run_when_intra */ - /* mc_out_mixed_type -- will enable in P Picture */ - (0 << 20) | - (1 << 19) | /* ie_start_when_quant_not_full */ - (1 << 18) | /* mb_info_state_mix */ - /* mb_type_use_mix_result -- will enable in P Picture */ - (0 << 17) | - /* me_cb_ie_read_enable -- will enable in P Picture */ - (0 << 16) | - /* ie_cur_data_from_me -- will enable in P Picture */ - (0 << 15) | - (1 << 14) | /* rem_per_use_table */ - (0 << 13) | /* q_latch_int_enable */ - (1 << 12) | /* q_use_table */ - (0 << 11) | /* q_start_wait */ - (1 << 10) | /* LUMA_16_LEFT_use_cur */ - (1 << 9) | /* DC_16_LEFT_SUM_use_cur */ - (1 << 8) | /* c_ref_ie_sel_cur */ - (0 << 7) | /* c_ipred_perfect_mode */ - (1 << 6) | /* ref_ie_ul_sel */ - (1 << 5) | /* mb_type_use_ie_result */ - (1 << 4) | /* detect_I16_from_I4 */ - (1 << 3) | /* ie_not_wait_ref_busy */ - (1 << 2) | /* ie_I16_enable */ - (3 << 0)); /* ie_done_sel // fastest when waiting */ - - if (request != NULL) { - WRITE_HREG(HCODEC_IE_WEIGHT, - (request->i16_weight << 16) | - (request->i4_weight << 0)); - - WRITE_HREG(HCODEC_ME_WEIGHT, (request->me_weight << 0)); - - WRITE_HREG(HCODEC_SAD_CONTROL_0, - /* ie_sad_offset_I16 */ - (request->i16_weight << 16) | - /* ie_sad_offset_I4 */ - (request->i4_weight << 0)); - - WRITE_HREG(HCODEC_SAD_CONTROL_1, - /* ie_sad_shift_I16 */ - (IE_SAD_SHIFT_I16 << 24) | - /* ie_sad_shift_I4 */ - (IE_SAD_SHIFT_I4 << 20) | - /* me_sad_shift_INTER */ - (ME_SAD_SHIFT_INTER << 16) | - /* me_sad_offset_INTER */ - (request->me_weight << 0)); - } else { - WRITE_HREG(HCODEC_IE_WEIGHT, - (I16MB_WEIGHT_OFFSET << 16) | - (I4MB_WEIGHT_OFFSET << 0)); - - WRITE_HREG(HCODEC_ME_WEIGHT, (ME_WEIGHT_OFFSET << 0)); - - WRITE_HREG(HCODEC_SAD_CONTROL_0, - /* ie_sad_offset_I16 */ - (I16MB_WEIGHT_OFFSET << 16) | - /* ie_sad_offset_I4 */ - (I4MB_WEIGHT_OFFSET << 0)); - - WRITE_HREG(HCODEC_SAD_CONTROL_1, - /* ie_sad_shift_I16 */ - (IE_SAD_SHIFT_I16 << 24) | - /* ie_sad_shift_I4 */ - (IE_SAD_SHIFT_I4 << 20) | - /* me_sad_shift_INTER */ - (ME_SAD_SHIFT_INTER << 16) | - /* me_sad_offset_INTER */ - (ME_WEIGHT_OFFSET << 0)); - } - - WRITE_HREG(HCODEC_ADV_MV_CTL0, - (ADV_MV_LARGE_16x8 << 31) | - (ADV_MV_LARGE_8x16 << 30) | - (ADV_MV_8x8_WEIGHT << 16) | /* adv_mv_8x8_weight */ - /* adv_mv_4x4x4_weight should be set bigger */ - (ADV_MV_4x4x4_WEIGHT << 0)); - - WRITE_HREG(HCODEC_ADV_MV_CTL1, - /* adv_mv_16x16_weight */ - (ADV_MV_16x16_WEIGHT << 16) | - (ADV_MV_LARGE_16x16 << 15) | - (ADV_MV_16_8_WEIGHT << 0)); /* adv_mv_16_8_weight */ - - hcodec_prog_qtbl(wq); - if (IDR) { - i_pic_qp = - wq->quant_tbl_i4[wq->qp_table_id][0] & 0xff; - i_pic_qp += - wq->quant_tbl_i16[wq->qp_table_id][0] & 0xff; - i_pic_qp /= 2; - p_pic_qp = i_pic_qp; - } else { - i_pic_qp = - wq->quant_tbl_i4[wq->qp_table_id][0] & 0xff; - i_pic_qp += - wq->quant_tbl_i16[wq->qp_table_id][0] & 0xff; - p_pic_qp = wq->quant_tbl_me[wq->qp_table_id][0] & 0xff; - slice_qp = (i_pic_qp + p_pic_qp) / 3; - i_pic_qp = slice_qp; - p_pic_qp = i_pic_qp; - } - - WRITE_HREG(HCODEC_QDCT_VLC_QUANT_CTL_0, - (0 << 19) | /* vlc_delta_quant_1 */ - (i_pic_qp << 13) | /* vlc_quant_1 */ - (0 << 6) | /* vlc_delta_quant_0 */ - (i_pic_qp << 0)); /* vlc_quant_0 */ - - WRITE_HREG(HCODEC_QDCT_VLC_QUANT_CTL_1, - (26 << 6) | /* vlc_max_delta_q_neg */ - (25 << 0)); /* vlc_max_delta_q_pos */ + pic_width_in_mb = (pic_width + 15) / 16; + WRITE_HREG(HCODEC_HDEC_MC_OMEM_AUTO, + (1 << 31) | /* use_omem_mb_xy */ + ((pic_width_in_mb - 1) << 16)); /* omem_max_mb_x */ + + WRITE_HREG(HCODEC_VLC_ADV_CONFIG, + /* early_mix_mc_hcmd -- will enable in P Picture */ + (0 << 10) | + (1 << 9) | /* update_top_left_mix */ + (1 << 8) | /* p_top_left_mix */ + /* mv_cal_mixed_type -- will enable in P Picture */ + (0 << 7) | + /* mc_hcmd_mixed_type -- will enable in P Picture */ + (0 << 6) | + (1 << 5) | /* use_seperate_int_control */ + (1 << 4) | /* hcmd_intra_use_q_info */ + (1 << 3) | /* hcmd_left_use_prev_info */ + (1 << 2) | /* hcmd_use_q_info */ + (1 << 1) | /* use_q_delta_quant */ + /* detect_I16_from_I4 use qdct detected mb_type */ + (0 << 0)); + + WRITE_HREG(HCODEC_QDCT_ADV_CONFIG, + (1 << 29) | /* mb_info_latch_no_I16_pred_mode */ + (1 << 28) | /* ie_dma_mbxy_use_i_pred */ + (1 << 27) | /* ie_dma_read_write_use_ip_idx */ + (1 << 26) | /* ie_start_use_top_dma_count */ + (1 << 25) | /* i_pred_top_dma_rd_mbbot */ + (1 << 24) | /* i_pred_top_dma_wr_disable */ + /* i_pred_mix -- will enable in P Picture */ + (0 << 23) | + (1 << 22) | /* me_ab_rd_when_intra_in_p */ + (1 << 21) | /* force_mb_skip_run_when_intra */ + /* mc_out_mixed_type -- will enable in P Picture */ + (0 << 20) | + (1 << 19) | /* ie_start_when_quant_not_full */ + (1 << 18) | /* mb_info_state_mix */ + /* mb_type_use_mix_result -- will enable in P Picture */ + (0 << 17) | + /* me_cb_ie_read_enable -- will enable in P Picture */ + (0 << 16) | + /* ie_cur_data_from_me -- will enable in P Picture */ + (0 << 15) | + (1 << 14) | /* rem_per_use_table */ + (0 << 13) | /* q_latch_int_enable */ + (1 << 12) | /* q_use_table */ + (0 << 11) | /* q_start_wait */ + (1 << 10) | /* LUMA_16_LEFT_use_cur */ + (1 << 9) | /* DC_16_LEFT_SUM_use_cur */ + (1 << 8) | /* c_ref_ie_sel_cur */ + (0 << 7) | /* c_ipred_perfect_mode */ + (1 << 6) | /* ref_ie_ul_sel */ + (1 << 5) | /* mb_type_use_ie_result */ + (1 << 4) | /* detect_I16_from_I4 */ + (1 << 3) | /* ie_not_wait_ref_busy */ + (1 << 2) | /* ie_I16_enable */ + (3 << 0)); /* ie_done_sel // fastest when waiting */ + + if (request != NULL) { + WRITE_HREG(HCODEC_IE_WEIGHT, + (request->i16_weight << 16) | + (request->i4_weight << 0)); + WRITE_HREG(HCODEC_ME_WEIGHT, + (request->me_weight << 0)); + WRITE_HREG(HCODEC_SAD_CONTROL_0, + /* ie_sad_offset_I16 */ + (request->i16_weight << 16) | + /* ie_sad_offset_I4 */ + (request->i4_weight << 0)); + WRITE_HREG(HCODEC_SAD_CONTROL_1, + /* ie_sad_shift_I16 */ + (IE_SAD_SHIFT_I16 << 24) | + /* ie_sad_shift_I4 */ + (IE_SAD_SHIFT_I4 << 20) | + /* me_sad_shift_INTER */ + (ME_SAD_SHIFT_INTER << 16) | + /* me_sad_offset_INTER */ + (request->me_weight << 0)); + wq->me_weight = request->me_weight; + wq->i4_weight = request->i4_weight; + wq->i16_weight = request->i16_weight; + } else { + WRITE_HREG(HCODEC_IE_WEIGHT, + (I16MB_WEIGHT_OFFSET << 16) | + (I4MB_WEIGHT_OFFSET << 0)); + WRITE_HREG(HCODEC_ME_WEIGHT, + (ME_WEIGHT_OFFSET << 0)); + WRITE_HREG(HCODEC_SAD_CONTROL_0, + /* ie_sad_offset_I16 */ + (I16MB_WEIGHT_OFFSET << 16) | + /* ie_sad_offset_I4 */ + (I4MB_WEIGHT_OFFSET << 0)); + WRITE_HREG(HCODEC_SAD_CONTROL_1, + /* ie_sad_shift_I16 */ + (IE_SAD_SHIFT_I16 << 24) | + /* ie_sad_shift_I4 */ + (IE_SAD_SHIFT_I4 << 20) | + /* me_sad_shift_INTER */ + (ME_SAD_SHIFT_INTER << 16) | + /* me_sad_offset_INTER */ + (ME_WEIGHT_OFFSET << 0)); + } - if (request != NULL) { - wq->me_weight = request->me_weight; - wq->i4_weight = request->i4_weight; - wq->i16_weight = request->i16_weight; - } + WRITE_HREG(HCODEC_ADV_MV_CTL0, + (ADV_MV_LARGE_16x8 << 31) | + (ADV_MV_LARGE_8x16 << 30) | + (ADV_MV_8x8_WEIGHT << 16) | /* adv_mv_8x8_weight */ + /* adv_mv_4x4x4_weight should be set bigger */ + (ADV_MV_4x4x4_WEIGHT << 0)); + WRITE_HREG(HCODEC_ADV_MV_CTL1, + /* adv_mv_16x16_weight */ + (ADV_MV_16x16_WEIGHT << 16) | + (ADV_MV_LARGE_16x16 << 15) | + (ADV_MV_16_8_WEIGHT << 0)); /* adv_mv_16_8_weight */ + + hcodec_prog_qtbl(wq); + if (IDR) { + i_pic_qp = + wq->quant_tbl_i4[0] & 0xff; + i_pic_qp += + wq->quant_tbl_i16[0] & 0xff; + i_pic_qp /= 2; + p_pic_qp = i_pic_qp; + } else { + i_pic_qp = + wq->quant_tbl_i4[0] & 0xff; + i_pic_qp += + wq->quant_tbl_i16[0] & 0xff; + p_pic_qp = wq->quant_tbl_me[0] & 0xff; + slice_qp = (i_pic_qp + p_pic_qp) / 3; + i_pic_qp = slice_qp; + p_pic_qp = i_pic_qp; + } +#ifdef H264_ENC_CBR + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB) { + data32 = READ_HREG(HCODEC_SAD_CONTROL_1); + data32 = data32 & 0xffff; /* remove sad shift */ + WRITE_HREG(HCODEC_SAD_CONTROL_1, data32); + WRITE_HREG(H264_ENC_CBR_TABLE_ADDR, + wq->mem.cbr_info_ddr_start_addr); + WRITE_HREG(H264_ENC_CBR_MB_SIZE_ADDR, + wq->mem.cbr_info_ddr_start_addr + + CBR_TABLE_SIZE); + WRITE_HREG(H264_ENC_CBR_CTL, + (wq->cbr_info.start_tbl_id << 28) | + (wq->cbr_info.short_shift << 24) | + (wq->cbr_info.long_mb_num << 16) | + (wq->cbr_info.long_th << 0)); + WRITE_HREG(H264_ENC_CBR_REGION_SIZE, + (wq->cbr_info.block_w << 16) | + (wq->cbr_info.block_h << 0)); } #endif - WRITE_HREG(HCODEC_VLC_PIC_SIZE, pic_width | (pic_height << 16)); + WRITE_HREG(HCODEC_QDCT_VLC_QUANT_CTL_0, + (0 << 19) | /* vlc_delta_quant_1 */ + (i_pic_qp << 13) | /* vlc_quant_1 */ + (0 << 6) | /* vlc_delta_quant_0 */ + (i_pic_qp << 0)); /* vlc_quant_0 */ + WRITE_HREG(HCODEC_QDCT_VLC_QUANT_CTL_1, + (14 << 6) | /* vlc_max_delta_q_neg */ + (13 << 0)); /* vlc_max_delta_q_pos */ + WRITE_HREG(HCODEC_VLC_PIC_SIZE, + pic_width | (pic_height << 16)); WRITE_HREG(HCODEC_VLC_PIC_POSITION, - (pic_mb_nr << 16) | (pic_mby << 8) | (pic_mbx << 0)); + (pic_mb_nr << 16) | + (pic_mby << 8) | + (pic_mbx << 0)); - switch (i_pic_qp) { /* synopsys parallel_case full_case */ + /* synopsys parallel_case full_case */ + switch (i_pic_qp) { case 0: i_pic_qp_c = 0; break; @@ -2060,7 +1753,8 @@ static void avc_prot_init(struct encode_wq_s *wq, break; } - switch (p_pic_qp) { /* synopsys parallel_case full_case */ + /* synopsys parallel_case full_case */ + switch (p_pic_qp) { case 0: p_pic_qp_c = 0; break; @@ -2219,33 +1913,32 @@ static void avc_prot_init(struct encode_wq_s *wq, break; } WRITE_HREG(HCODEC_QDCT_Q_QUANT_I, - (i_pic_qp_c << 22) | - (i_pic_qp << 16) | - ((i_pic_qp_c % 6) << 12) | - ((i_pic_qp_c / 6) << 8) | - ((i_pic_qp % 6) << 4) | - ((i_pic_qp / 6) << 0)); + (i_pic_qp_c << 22) | + (i_pic_qp << 16) | + ((i_pic_qp_c % 6) << 12) | + ((i_pic_qp_c / 6) << 8) | + ((i_pic_qp % 6) << 4) | + ((i_pic_qp / 6) << 0)); WRITE_HREG(HCODEC_QDCT_Q_QUANT_P, - (p_pic_qp_c << 22) | - (p_pic_qp << 16) | - ((p_pic_qp_c % 6) << 12) | - ((p_pic_qp_c / 6) << 8) | - ((p_pic_qp % 6) << 4) | - ((p_pic_qp / 6) << 0)); + (p_pic_qp_c << 22) | + (p_pic_qp << 16) | + ((p_pic_qp_c % 6) << 12) | + ((p_pic_qp_c / 6) << 8) | + ((p_pic_qp % 6) << 4) | + ((p_pic_qp / 6) << 0)); #ifdef ENABLE_IGNORE_FUNCTION WRITE_HREG(HCODEC_IGNORE_CONFIG, - (1 << 31) | /* ignore_lac_coeff_en */ - (1 << 26) | /* ignore_lac_coeff_else (<1) */ - (1 << 21) | /* ignore_lac_coeff_2 (<1) */ - (2 << 16) | /* ignore_lac_coeff_1 (<2) */ - (1 << 15) | /* ignore_cac_coeff_en */ - (1 << 10) | /* ignore_cac_coeff_else (<1) */ - (1 << 5) | /* ignore_cac_coeff_2 (<1) */ - (3 << 0)); /* ignore_cac_coeff_1 (<2) */ - -#ifndef USE_OLD_DUMP_MC + (1 << 31) | /* ignore_lac_coeff_en */ + (1 << 26) | /* ignore_lac_coeff_else (<1) */ + (1 << 21) | /* ignore_lac_coeff_2 (<1) */ + (2 << 16) | /* ignore_lac_coeff_1 (<2) */ + (1 << 15) | /* ignore_cac_coeff_en */ + (1 << 10) | /* ignore_cac_coeff_else (<1) */ + (1 << 5) | /* ignore_cac_coeff_2 (<1) */ + (3 << 0)); /* ignore_cac_coeff_1 (<2) */ + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB) WRITE_HREG(HCODEC_IGNORE_CONFIG_2, (1 << 31) | /* ignore_t_lac_coeff_en */ @@ -2270,7 +1963,6 @@ static void avc_prot_init(struct encode_wq_s *wq, /* ignore_cdc_abs_max_intra 0-1, 1-2, 2-3, 3-4 */ (0<<0)); else -#endif WRITE_HREG(HCODEC_IGNORE_CONFIG_2, (1 << 31) | /* ignore_t_lac_coeff_en */ (1 << 26) | /* ignore_t_lac_coeff_else (<1) */ @@ -2283,285 +1975,204 @@ static void avc_prot_init(struct encode_wq_s *wq, #endif WRITE_HREG(HCODEC_QDCT_MB_CONTROL, - (1 << 9) | /* mb_info_soft_reset */ - (1 << 0)); /* mb read buffer soft reset */ - - if (encode_manager.ucode_index != UCODE_MODE_SW_MIX) { - u32 me_mode = (ie_me_mode >> ME_PIXEL_MODE_SHIFT) & - ME_PIXEL_MODE_MASK; - WRITE_HREG(HCODEC_QDCT_MB_CONTROL, - (1 << 28) | /* ignore_t_p8x8 */ - (0 << 27) | /* zero_mc_out_null_non_skipped_mb */ - (0 << 26) | /* no_mc_out_null_non_skipped_mb */ - (0 << 25) | /* mc_out_even_skipped_mb */ - (0 << 24) | /* mc_out_wait_cbp_ready */ - (0 << 23) | /* mc_out_wait_mb_type_ready */ - (1 << 29) | /* ie_start_int_enable */ - (1 << 19) | /* i_pred_enable */ - (1 << 20) | /* ie_sub_enable */ - (1 << 18) | /* iq_enable */ - (1 << 17) | /* idct_enable */ - (1 << 14) | /* mb_pause_enable */ - (1 << 13) | /* q_enable */ - (1 << 12) | /* dct_enable */ - (1 << 10) | /* mb_info_en */ - (0 << 3) | /* endian */ - (0 << 1) | /* mb_read_en */ - (0 << 0)); /* soft reset */ - - WRITE_HREG(HCODEC_SAD_CONTROL, - (0 << 3) | /* ie_result_buff_enable */ - (1 << 2) | /* ie_result_buff_soft_reset */ - (0 << 1) | /* sad_enable */ - (1 << 0)); /* sad soft reset */ - - WRITE_HREG(HCODEC_IE_RESULT_BUFFER, 0); - - WRITE_HREG(HCODEC_SAD_CONTROL, - (1 << 3) | /* ie_result_buff_enable */ - (0 << 2) | /* ie_result_buff_soft_reset */ - (1 << 1) | /* sad_enable */ - (0 << 0)); /* sad soft reset */ - -#ifndef USE_OLD_DUMP_MC - if ((get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) && - (encode_manager.ucode_index == UCODE_MODE_FULL)) { - WRITE_HREG(HCODEC_IE_CONTROL, - (1 << 30) | /* active_ul_block */ - (0 << 1) | /* ie_enable */ - (1 << 0)); /* ie soft reset */ - - WRITE_HREG(HCODEC_IE_CONTROL, - (1 << 30) | /* active_ul_block */ - (0 << 1) | /* ie_enable */ - (0 << 0)); /* ie soft reset */ - - WRITE_HREG(HCODEC_ME_SKIP_LINE, - (8 << 24) | /* step_3_skip_line */ - (8 << 18) | /* step_2_skip_line */ - (2 << 12) | /* step_1_skip_line */ - (0 << 6) | /* step_0_skip_line */ - (0 << 0)); + (1 << 9) | /* mb_info_soft_reset */ + (1 << 0)); /* mb read buffer soft reset */ - } else -#endif - { - WRITE_HREG(HCODEC_IE_CONTROL, - (0 << 1) | /* ie_enable */ - (1 << 0)); /* ie soft reset */ - - WRITE_HREG(HCODEC_IE_CONTROL, - (0 << 1) | /* ie_enable */ - (0 << 0)); /* ie soft reset */ - if (me_mode == 3) { - WRITE_HREG(HCODEC_ME_SKIP_LINE, - (8 << 24) | /* step_3_skip_line */ - (8 << 18) | /* step_2_skip_line */ - (2 << 12) | /* step_1_skip_line */ - (0 << 6) | /* step_0_skip_line */ - (0 << 0)); - } else { - WRITE_HREG(HCODEC_ME_SKIP_LINE, - (4 << 24) | /* step_3_skip_line */ - (4 << 18) | /* step_2_skip_line */ - (2 << 12) | /* step_1_skip_line */ - (0 << 6) | /* step_0_skip_line */ - (0 << 0)); - } - } + WRITE_HREG(HCODEC_QDCT_MB_CONTROL, + (1 << 28) | /* ignore_t_p8x8 */ + (0 << 27) | /* zero_mc_out_null_non_skipped_mb */ + (0 << 26) | /* no_mc_out_null_non_skipped_mb */ + (0 << 25) | /* mc_out_even_skipped_mb */ + (0 << 24) | /* mc_out_wait_cbp_ready */ + (0 << 23) | /* mc_out_wait_mb_type_ready */ + (1 << 29) | /* ie_start_int_enable */ + (1 << 19) | /* i_pred_enable */ + (1 << 20) | /* ie_sub_enable */ + (1 << 18) | /* iq_enable */ + (1 << 17) | /* idct_enable */ + (1 << 14) | /* mb_pause_enable */ + (1 << 13) | /* q_enable */ + (1 << 12) | /* dct_enable */ + (1 << 10) | /* mb_info_en */ + (0 << 3) | /* endian */ + (0 << 1) | /* mb_read_en */ + (0 << 0)); /* soft reset */ + + WRITE_HREG(HCODEC_SAD_CONTROL, + (0 << 3) | /* ie_result_buff_enable */ + (1 << 2) | /* ie_result_buff_soft_reset */ + (0 << 1) | /* sad_enable */ + (1 << 0)); /* sad soft reset */ + WRITE_HREG(HCODEC_IE_RESULT_BUFFER, 0); + + WRITE_HREG(HCODEC_SAD_CONTROL, + (1 << 3) | /* ie_result_buff_enable */ + (0 << 2) | /* ie_result_buff_soft_reset */ + (1 << 1) | /* sad_enable */ + (0 << 0)); /* sad soft reset */ + + WRITE_HREG(HCODEC_IE_CONTROL, + (1 << 30) | /* active_ul_block */ + (0 << 1) | /* ie_enable */ + (1 << 0)); /* ie soft reset */ + + WRITE_HREG(HCODEC_IE_CONTROL, + (1 << 30) | /* active_ul_block */ + (0 << 1) | /* ie_enable */ + (0 << 0)); /* ie soft reset */ + + WRITE_HREG(HCODEC_ME_SKIP_LINE, + (8 << 24) | /* step_3_skip_line */ + (8 << 18) | /* step_2_skip_line */ + (2 << 12) | /* step_1_skip_line */ + (0 << 6) | /* step_0_skip_line */ + (0 << 0)); + + WRITE_HREG(HCODEC_ME_MV_MERGE_CTL, me_mv_merge_ctl); + WRITE_HREG(HCODEC_ME_STEP0_CLOSE_MV, me_step0_close_mv); + WRITE_HREG(HCODEC_ME_SAD_ENOUGH_01, me_sad_enough_01); + WRITE_HREG(HCODEC_ME_SAD_ENOUGH_23, me_sad_enough_23); + WRITE_HREG(HCODEC_ME_F_SKIP_SAD, me_f_skip_sad); + WRITE_HREG(HCODEC_ME_F_SKIP_WEIGHT, me_f_skip_weight); + WRITE_HREG(HCODEC_ME_MV_WEIGHT_01, me_mv_weight_01); + WRITE_HREG(HCODEC_ME_MV_WEIGHT_23, me_mv_weight_23); + WRITE_HREG(HCODEC_ME_SAD_RANGE_INC, me_sad_range_inc); - WRITE_HREG(HCODEC_ME_MV_MERGE_CTL, me_mv_merge_ctl); - WRITE_HREG(HCODEC_ME_STEP0_CLOSE_MV, me_step0_close_mv); - - WRITE_HREG(HCODEC_ME_SAD_ENOUGH_01, me_sad_enough_01); - /* (0x18<<12) | // me_sad_enough_1 */ - /* (0x10<<0)); // me_sad_enough_0 */ - - WRITE_HREG(HCODEC_ME_SAD_ENOUGH_23, me_sad_enough_23); - /* (0x20<<0) | // me_sad_enough_2 */ - /* (0<<12)); // me_sad_enough_3 */ - - WRITE_HREG(HCODEC_ME_F_SKIP_SAD, me_f_skip_sad); - WRITE_HREG(HCODEC_ME_F_SKIP_WEIGHT, me_f_skip_weight); - WRITE_HREG(HCODEC_ME_MV_WEIGHT_01, me_mv_weight_01); - WRITE_HREG(HCODEC_ME_MV_WEIGHT_23, me_mv_weight_23); - WRITE_HREG(HCODEC_ME_SAD_RANGE_INC, me_sad_range_inc); - -#ifndef USE_OLD_DUMP_MC - if (get_cpu_type() >= MESON_CPU_MAJOR_ID_TXL) { - WRITE_HREG(HCODEC_V5_SIMPLE_MB_CTL, 0); - WRITE_HREG(HCODEC_V5_SIMPLE_MB_CTL, - (v5_use_small_diff_cnt << 7) | - (v5_simple_mb_inter_all_en << 6) | - (v5_simple_mb_inter_8x8_en << 5) | - (v5_simple_mb_inter_16_8_en << 4) | - (v5_simple_mb_inter_16x16_en << 3) | - (v5_simple_mb_intra_en << 2) | - (v5_simple_mb_C_en << 1) | - (v5_simple_mb_Y_en << 0)); - WRITE_HREG(HCODEC_V5_MB_DIFF_SUM, 0); - WRITE_HREG(HCODEC_V5_SMALL_DIFF_CNT, - (v5_small_diff_C<<16) | - (v5_small_diff_Y<<0)); - WRITE_HREG(HCODEC_V5_SIMPLE_MB_DQUANT, - v5_simple_dq_setting); - WRITE_HREG(HCODEC_V5_SIMPLE_MB_ME_WEIGHT, - v5_simple_me_weight_setting); - WRITE_HREG(HCODEC_QDCT_CONFIG, 1 << 0); - } + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_TXL) { + WRITE_HREG(HCODEC_V5_SIMPLE_MB_CTL, 0); + WRITE_HREG(HCODEC_V5_SIMPLE_MB_CTL, + (v5_use_small_diff_cnt << 7) | + (v5_simple_mb_inter_all_en << 6) | + (v5_simple_mb_inter_8x8_en << 5) | + (v5_simple_mb_inter_16_8_en << 4) | + (v5_simple_mb_inter_16x16_en << 3) | + (v5_simple_mb_intra_en << 2) | + (v5_simple_mb_C_en << 1) | + (v5_simple_mb_Y_en << 0)); + WRITE_HREG(HCODEC_V5_MB_DIFF_SUM, 0); + WRITE_HREG(HCODEC_V5_SMALL_DIFF_CNT, + (v5_small_diff_C<<16) | + (v5_small_diff_Y<<0)); + WRITE_HREG(HCODEC_V5_SIMPLE_MB_DQUANT, + v5_simple_dq_setting); + WRITE_HREG(HCODEC_V5_SIMPLE_MB_ME_WEIGHT, + v5_simple_me_weight_setting); + /* txlx can remove it */ + WRITE_HREG(HCODEC_QDCT_CONFIG, 1 << 0); + } - if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL) { - WRITE_HREG(HCODEC_V4_FORCE_SKIP_CFG, - (i_pic_qp << 26) | /* v4_force_q_r_intra */ - (i_pic_qp << 20) | /* v4_force_q_r_inter */ - (0 << 19) | /* v4_force_q_y_enable */ - (5 << 16) | /* v4_force_qr_y */ - (6 << 12) | /* v4_force_qp_y */ - (0 << 0)); /* v4_force_skip_sad */ - - /* V3 Force skip */ - WRITE_HREG(HCODEC_V3_SKIP_CONTROL, - (1 << 31) | /* v3_skip_enable */ - (0 << 30) | /* v3_step_1_weight_enable */ - (1 << 28) | /* v3_mv_sad_weight_enable */ - (1 << 27) | /* v3_ipred_type_enable */ - (V3_FORCE_SKIP_SAD_1 << 12) | - (V3_FORCE_SKIP_SAD_0 << 0)); - WRITE_HREG(HCODEC_V3_SKIP_WEIGHT, - (V3_SKIP_WEIGHT_1 << 16) | - (V3_SKIP_WEIGHT_0 << 0)); - WRITE_HREG(HCODEC_V3_L1_SKIP_MAX_SAD, - (V3_LEVEL_1_F_SKIP_MAX_SAD << 16) | - (V3_LEVEL_1_SKIP_MAX_SAD << 0)); - WRITE_HREG(HCODEC_V3_L2_SKIP_WEIGHT, - (V3_FORCE_SKIP_SAD_2 << 16) | - (V3_SKIP_WEIGHT_2 << 0)); - if (request != NULL) { - unsigned int off1, off2; - off1 = V3_IE_F_ZERO_SAD_I4 - I4MB_WEIGHT_OFFSET; - off2 = V3_IE_F_ZERO_SAD_I16 - - I16MB_WEIGHT_OFFSET; - WRITE_HREG(HCODEC_V3_F_ZERO_CTL_0, - ((request->i16_weight + off2) << 16) | - ((request->i4_weight + off1) << 0)); - off1 = V3_ME_F_ZERO_SAD - ME_WEIGHT_OFFSET; - WRITE_HREG(HCODEC_V3_F_ZERO_CTL_1, - (0 << 25) | - /* v3_no_ver_when_top_zero_en */ - (0 << 24) | - /* v3_no_hor_when_left_zero_en */ - (3 << 16) | /* type_hor break */ - ((request->me_weight + off1) << 0)); - } else { - WRITE_HREG(HCODEC_V3_F_ZERO_CTL_0, - (V3_IE_F_ZERO_SAD_I16 << 16) | - (V3_IE_F_ZERO_SAD_I4 << 0)); - WRITE_HREG(HCODEC_V3_F_ZERO_CTL_1, - (0 << 25) | - /* v3_no_ver_when_top_zero_en */ - (0 << 24) | - /* v3_no_hor_when_left_zero_en */ - (3 << 16) | /* type_hor break */ - (V3_ME_F_ZERO_SAD << 0)); - } - } else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB) { - /* V3 Force skip */ - WRITE_HREG(HCODEC_V3_SKIP_CONTROL, - (1 << 31) | /* v3_skip_enable */ - (0 << 30) | /* v3_step_1_weight_enable */ - (1 << 28) | /* v3_mv_sad_weight_enable */ - (1 << 27) | /* v3_ipred_type_enable */ - (0 << 12) | /* V3_FORCE_SKIP_SAD_1 */ - (0 << 0)); /* V3_FORCE_SKIP_SAD_0 */ - WRITE_HREG(HCODEC_V3_SKIP_WEIGHT, - (V3_SKIP_WEIGHT_1 << 16) | - (V3_SKIP_WEIGHT_0 << 0)); - WRITE_HREG(HCODEC_V3_L1_SKIP_MAX_SAD, - (V3_LEVEL_1_F_SKIP_MAX_SAD << 16) | - (V3_LEVEL_1_SKIP_MAX_SAD << 0)); - WRITE_HREG(HCODEC_V3_L2_SKIP_WEIGHT, - (0 << 16) | /* V3_FORCE_SKIP_SAD_2 */ - (V3_SKIP_WEIGHT_2 << 0)); + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL) { + WRITE_HREG(HCODEC_V4_FORCE_SKIP_CFG, + (i_pic_qp << 26) | /* v4_force_q_r_intra */ + (i_pic_qp << 20) | /* v4_force_q_r_inter */ + (0 << 19) | /* v4_force_q_y_enable */ + (5 << 16) | /* v4_force_qr_y */ + (6 << 12) | /* v4_force_qp_y */ + (0 << 0)); /* v4_force_skip_sad */ + + /* V3 Force skip */ + WRITE_HREG(HCODEC_V3_SKIP_CONTROL, + (1 << 31) | /* v3_skip_enable */ + (0 << 30) | /* v3_step_1_weight_enable */ + (1 << 28) | /* v3_mv_sad_weight_enable */ + (1 << 27) | /* v3_ipred_type_enable */ + (V3_FORCE_SKIP_SAD_1 << 12) | + (V3_FORCE_SKIP_SAD_0 << 0)); + WRITE_HREG(HCODEC_V3_SKIP_WEIGHT, + (V3_SKIP_WEIGHT_1 << 16) | + (V3_SKIP_WEIGHT_0 << 0)); + WRITE_HREG(HCODEC_V3_L1_SKIP_MAX_SAD, + (V3_LEVEL_1_F_SKIP_MAX_SAD << 16) | + (V3_LEVEL_1_SKIP_MAX_SAD << 0)); + WRITE_HREG(HCODEC_V3_L2_SKIP_WEIGHT, + (V3_FORCE_SKIP_SAD_2 << 16) | + (V3_SKIP_WEIGHT_2 << 0)); + if (request != NULL) { + unsigned int off1, off2; + off1 = V3_IE_F_ZERO_SAD_I4 - I4MB_WEIGHT_OFFSET; + off2 = V3_IE_F_ZERO_SAD_I16 + - I16MB_WEIGHT_OFFSET; WRITE_HREG(HCODEC_V3_F_ZERO_CTL_0, - (0 << 16) | /* V3_IE_F_ZERO_SAD_I16 */ - (0 << 0)); /* V3_IE_F_ZERO_SAD_I4 */ + ((request->i16_weight + off2) << 16) | + ((request->i4_weight + off1) << 0)); + off1 = V3_ME_F_ZERO_SAD - ME_WEIGHT_OFFSET; WRITE_HREG(HCODEC_V3_F_ZERO_CTL_1, - (0 << 25) | /* v3_no_ver_when_top_zero_en */ - (0 << 24) | /* v3_no_hor_when_left_zero_en */ + (0 << 25) | + /* v3_no_ver_when_top_zero_en */ + (0 << 24) | + /* v3_no_hor_when_left_zero_en */ (3 << 16) | /* type_hor break */ - (0 << 0)); /* V3_ME_F_ZERO_SAD */ - } - if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB) { - int i; - /* MV SAD Table */ - for (i = 0; i < 64; i++) - WRITE_HREG(HCODEC_V3_MV_SAD_TABLE, - v3_mv_sad[i]); - - /* IE PRED SAD Table*/ - WRITE_HREG(HCODEC_V3_IPRED_TYPE_WEIGHT_0, - (C_ipred_weight_H << 24) | - (C_ipred_weight_V << 16) | - (I4_ipred_weight_else << 8) | - (I4_ipred_weight_most << 0)); - WRITE_HREG(HCODEC_V3_IPRED_TYPE_WEIGHT_1, - (I16_ipred_weight_DC << 24) | - (I16_ipred_weight_H << 16) | - (I16_ipred_weight_V << 8) | - (C_ipred_weight_DC << 0)); - WRITE_HREG(HCODEC_V3_LEFT_SMALL_MAX_SAD, - (v3_left_small_max_me_sad << 16) | - (v3_left_small_max_ie_sad << 0)); + ((request->me_weight + off1) << 0)); + } else { + WRITE_HREG(HCODEC_V3_F_ZERO_CTL_0, + (V3_IE_F_ZERO_SAD_I16 << 16) | + (V3_IE_F_ZERO_SAD_I4 << 0)); + WRITE_HREG(HCODEC_V3_F_ZERO_CTL_1, + (0 << 25) | + /* v3_no_ver_when_top_zero_en */ + (0 << 24) | + /* v3_no_hor_when_left_zero_en */ + (3 << 16) | /* type_hor break */ + (V3_ME_F_ZERO_SAD << 0)); } -#endif - WRITE_HREG(HCODEC_IE_DATA_FEED_BUFF_INFO, 0); - } else { - WRITE_HREG(HCODEC_QDCT_MB_CONTROL, - (0 << 28) | /* ignore_t_p8x8 */ - (0 << 27) | /* zero_mc_out_null_non_skipped_mb */ - (0 << 26) | /* no_mc_out_null_non_skipped_mb */ - (0 << 25) | /* mc_out_even_skipped_mb */ - (0 << 24) | /* mc_out_wait_cbp_ready */ - (0 << 23) | /* mc_out_wait_mb_type_ready */ - (1 << 22) | /* i_pred_int_enable */ - (1 << 19) | /* i_pred_enable */ - (1 << 20) | /* ie_sub_enable */ - (1 << 18) | /* iq_enable */ - (1 << 17) | /* idct_enable */ - (1 << 14) | /* mb_pause_enable */ - (1 << 13) | /* q_enable */ - (1 << 12) | /* dct_enable */ - (1 << 10) | /* mb_info_en */ - (avc_endian << 3) | /* endian */ - (1 << 1) | /* mb_read_en */ - (0 << 0)); /* soft reset */ + } else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB) { + /* V3 Force skip */ + WRITE_HREG(HCODEC_V3_SKIP_CONTROL, + (1 << 31) | /* v3_skip_enable */ + (0 << 30) | /* v3_step_1_weight_enable */ + (1 << 28) | /* v3_mv_sad_weight_enable */ + (1 << 27) | /* v3_ipred_type_enable */ + (0 << 12) | /* V3_FORCE_SKIP_SAD_1 */ + (0 << 0)); /* V3_FORCE_SKIP_SAD_0 */ + WRITE_HREG(HCODEC_V3_SKIP_WEIGHT, + (V3_SKIP_WEIGHT_1 << 16) | + (V3_SKIP_WEIGHT_0 << 0)); + WRITE_HREG(HCODEC_V3_L1_SKIP_MAX_SAD, + (V3_LEVEL_1_F_SKIP_MAX_SAD << 16) | + (V3_LEVEL_1_SKIP_MAX_SAD << 0)); + WRITE_HREG(HCODEC_V3_L2_SKIP_WEIGHT, + (0 << 16) | /* V3_FORCE_SKIP_SAD_2 */ + (V3_SKIP_WEIGHT_2 << 0)); + WRITE_HREG(HCODEC_V3_F_ZERO_CTL_0, + (0 << 16) | /* V3_IE_F_ZERO_SAD_I16 */ + (0 << 0)); /* V3_IE_F_ZERO_SAD_I4 */ + WRITE_HREG(HCODEC_V3_F_ZERO_CTL_1, + (0 << 25) | /* v3_no_ver_when_top_zero_en */ + (0 << 24) | /* v3_no_hor_when_left_zero_en */ + (3 << 16) | /* type_hor break */ + (0 << 0)); /* V3_ME_F_ZERO_SAD */ + } + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB) { + int i; + /* MV SAD Table */ + for (i = 0; i < 64; i++) + WRITE_HREG(HCODEC_V3_MV_SAD_TABLE, + v3_mv_sad[i]); + + /* IE PRED SAD Table*/ + WRITE_HREG(HCODEC_V3_IPRED_TYPE_WEIGHT_0, + (C_ipred_weight_H << 24) | + (C_ipred_weight_V << 16) | + (I4_ipred_weight_else << 8) | + (I4_ipred_weight_most << 0)); + WRITE_HREG(HCODEC_V3_IPRED_TYPE_WEIGHT_1, + (I16_ipred_weight_DC << 24) | + (I16_ipred_weight_H << 16) | + (I16_ipred_weight_V << 8) | + (C_ipred_weight_DC << 0)); + WRITE_HREG(HCODEC_V3_LEFT_SMALL_MAX_SAD, + (v3_left_small_max_me_sad << 16) | + (v3_left_small_max_ie_sad << 0)); } + WRITE_HREG(HCODEC_IE_DATA_FEED_BUFF_INFO, 0); + WRITE_HREG(HCODEC_CURR_CANVAS_CTRL, 0); data32 = READ_HREG(HCODEC_VLC_CONFIG); data32 = data32 | (1 << 0); /* set pop_coeff_even_all_zero */ WRITE_HREG(HCODEC_VLC_CONFIG, data32); - if (encode_manager.ucode_index == UCODE_MODE_SW_MIX) - WRITE_HREG(SW_CTL_INFO_DDR_START, - wq->mem.sw_ctl_info_start_addr); -#ifndef USE_OLD_DUMP_MC - else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) - WRITE_HREG(INFO_DUMP_START_ADDR, - wq->mem.dump_info_ddr_start_addr); -#endif - else { - if (IDR) { - WRITE_HREG(BITS_INFO_DDR_START, - wq->mem.intra_bits_info_ddr_start_addr); - WRITE_HREG(MV_INFO_DDR_START, - wq->mem.intra_pred_info_ddr_start_addr); - } else { - WRITE_HREG(BITS_INFO_DDR_START, - wq->mem.inter_bits_info_ddr_start_addr); - WRITE_HREG(MV_INFO_DDR_START, - wq->mem.inter_mv_info_ddr_start_addr); - } - } + WRITE_HREG(INFO_DUMP_START_ADDR, + wq->mem.dump_info_ddr_start_addr); /* clear mailbox interrupt */ WRITE_HREG(HCODEC_IRQ_MBOX_CLR, 1); @@ -2575,16 +2186,11 @@ void amvenc_reset(void) READ_VREG(DOS_SW_RESET1); READ_VREG(DOS_SW_RESET1); READ_VREG(DOS_SW_RESET1); - if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) - WRITE_VREG(DOS_SW_RESET1, - (1 << 2) | (1 << 6) | - (1 << 7) | (1 << 8) | - (1 << 14) | (1 << 16) | - (1 << 17)); - else - WRITE_VREG(DOS_SW_RESET1, - (1 << 2) | (1 << 6) | (1 << 7) | - (1 << 8) | (1 << 16) | (1 << 17)); + WRITE_VREG(DOS_SW_RESET1, + (1 << 2) | (1 << 6) | + (1 << 7) | (1 << 8) | + (1 << 14) | (1 << 16) | + (1 << 17)); WRITE_VREG(DOS_SW_RESET1, 0); READ_VREG(DOS_SW_RESET1); READ_VREG(DOS_SW_RESET1); @@ -2596,7 +2202,8 @@ void amvenc_start(void) READ_VREG(DOS_SW_RESET1); READ_VREG(DOS_SW_RESET1); READ_VREG(DOS_SW_RESET1); - WRITE_VREG(DOS_SW_RESET1, (1 << 12) | (1 << 11)); + WRITE_VREG(DOS_SW_RESET1, + (1 << 12) | (1 << 11)); WRITE_VREG(DOS_SW_RESET1, 0); READ_VREG(DOS_SW_RESET1); @@ -2620,20 +2227,12 @@ void amvenc_stop(void) READ_VREG(DOS_SW_RESET1); READ_VREG(DOS_SW_RESET1); - if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) - WRITE_VREG(DOS_SW_RESET1, - (1 << 12) | (1 << 11) | - (1 << 2) | (1 << 6) | - (1 << 7) | (1 << 8) | - (1 << 14) | (1 << 16) | - (1 << 17)); - else - WRITE_VREG(DOS_SW_RESET1, - (1 << 12) | (1 << 11) | - (1 << 2) | (1 << 6) | - (1 << 7) | (1 << 8) | - (1 << 16) | (1 << 17)); - + WRITE_VREG(DOS_SW_RESET1, + (1 << 12) | (1 << 11) | + (1 << 2) | (1 << 6) | + (1 << 7) | (1 << 8) | + (1 << 14) | (1 << 16) | + (1 << 17)); WRITE_VREG(DOS_SW_RESET1, 0); @@ -2644,7 +2243,7 @@ void amvenc_stop(void) static void __iomem *mc_addr; static u32 mc_addr_map; -#define MC_SIZE (4096 * 16) +#define MC_SIZE (4096 * 8) s32 amvenc_loadmc(const char *p, struct encode_wq_s *wq) { ulong timeout; @@ -2777,16 +2376,14 @@ static s32 avc_poweron(u32 clock) spin_lock_irqsave(&lock, flags); - if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M8) { - WRITE_AOREG(AO_RTI_PWR_CNTL_REG0, - (READ_AOREG(AO_RTI_PWR_CNTL_REG0) & (~0x18))); - udelay(10); - /* Powerup HCODEC */ - /* [1:0] HCODEC */ - WRITE_AOREG(AO_RTI_GEN_PWR_SLEEP0, - (READ_AOREG(AO_RTI_GEN_PWR_SLEEP0) & (~0x3))); - udelay(10); - } + WRITE_AOREG(AO_RTI_PWR_CNTL_REG0, + (READ_AOREG(AO_RTI_PWR_CNTL_REG0) & (~0x18))); + udelay(10); + /* Powerup HCODEC */ + /* [1:0] HCODEC */ + WRITE_AOREG(AO_RTI_GEN_PWR_SLEEP0, + (READ_AOREG(AO_RTI_GEN_PWR_SLEEP0) & (~0x3))); + udelay(10); WRITE_VREG(DOS_SW_RESET1, 0xffffffff); WRITE_VREG(DOS_SW_RESET1, 0); @@ -2794,27 +2391,18 @@ static s32 avc_poweron(u32 clock) /* Enable Dos internal clock gating */ hvdec_clock_enable(clock); - if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M8) { - /* Powerup HCODEC memories */ - WRITE_VREG(DOS_MEM_PD_HCODEC, 0x0); + /* Powerup HCODEC memories */ + WRITE_VREG(DOS_MEM_PD_HCODEC, 0x0); - /* Remove HCODEC ISO */ - WRITE_AOREG(AO_RTI_GEN_PWR_ISO0, - (READ_AOREG(AO_RTI_GEN_PWR_ISO0) & (~0x30))); - udelay(10); - } + /* Remove HCODEC ISO */ + WRITE_AOREG(AO_RTI_GEN_PWR_ISO0, + (READ_AOREG(AO_RTI_GEN_PWR_ISO0) & (~0x30))); + udelay(10); /* Disable auto-clock gate */ - WRITE_VREG(DOS_GEN_CTRL0, (READ_VREG(DOS_GEN_CTRL0) | 0x1)); - WRITE_VREG(DOS_GEN_CTRL0, (READ_VREG(DOS_GEN_CTRL0) & 0xFFFFFFFE)); - -#ifdef USE_VDEC2 - if (get_cpu_type() == MESON_CPU_MAJOR_ID_M8) { - if (!vdec_on(VDEC_2) && get_vdec2_usage() == USAGE_NONE) { - set_vdec2_usage(USAGE_ENCODE); - vdec_poweron(VDEC_2); - } - } -#endif + WRITE_VREG(DOS_GEN_CTRL0, + (READ_VREG(DOS_GEN_CTRL0) | 0x1)); + WRITE_VREG(DOS_GEN_CTRL0, + (READ_VREG(DOS_GEN_CTRL0) & 0xFFFFFFFE)); spin_unlock_irqrestore(&lock, flags); @@ -2828,29 +2416,18 @@ static s32 avc_poweroff(void) spin_lock_irqsave(&lock, flags); - if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M8) { - /* enable HCODEC isolation */ - WRITE_AOREG(AO_RTI_GEN_PWR_ISO0, - READ_AOREG(AO_RTI_GEN_PWR_ISO0) | 0x30); - /* power off HCODEC memories */ - WRITE_VREG(DOS_MEM_PD_HCODEC, 0xffffffffUL); - } + /* enable HCODEC isolation */ + WRITE_AOREG(AO_RTI_GEN_PWR_ISO0, + READ_AOREG(AO_RTI_GEN_PWR_ISO0) | 0x30); + /* power off HCODEC memories */ + WRITE_VREG(DOS_MEM_PD_HCODEC, 0xffffffffUL); + /* disable HCODEC clock */ hvdec_clock_disable(); - if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M8) { - /* HCODEC power off */ - WRITE_AOREG(AO_RTI_GEN_PWR_SLEEP0, - READ_AOREG(AO_RTI_GEN_PWR_SLEEP0) | 0x3); - } -#ifdef USE_VDEC2 - if (get_cpu_type() == MESON_CPU_MAJOR_ID_M8) { - if (vdec_on(VDEC_2) && get_vdec2_usage() != USAGE_DEC_4K2K) { - vdec_poweroff(VDEC_2); - set_vdec2_usage(USAGE_NONE); - } - } -#endif + /* HCODEC power off */ + WRITE_AOREG(AO_RTI_GEN_PWR_SLEEP0, + READ_AOREG(AO_RTI_GEN_PWR_SLEEP0) | 0x3); spin_unlock_irqrestore(&lock, flags); @@ -2870,11 +2447,7 @@ static s32 reload_mc(struct encode_wq_s *wq) udelay(10); - if (get_cpu_type() >= MESON_CPU_MAJOR_ID_MG9TV) - WRITE_HREG(HCODEC_ASSIST_MMC_CTRL1, 0x32); - else - WRITE_HREG(HCODEC_ASSIST_MMC_CTRL1, 0x2); - + WRITE_HREG(HCODEC_ASSIST_MMC_CTRL1, 0x32); enc_pr(LOG_INFO, "reload microcode\n"); if (amvenc_loadmc(p, wq) < 0) @@ -2887,17 +2460,10 @@ static void encode_isr_tasklet(ulong data) struct encode_manager_s *manager = (struct encode_manager_s *)data; enc_pr(LOG_INFO, "encoder is done %d\n", manager->encode_hw_status); if (((manager->encode_hw_status == ENCODER_IDR_DONE) - || (manager->encode_hw_status == ENCODER_NON_IDR_DONE) - || (manager->encode_hw_status == ENCODER_SEQUENCE_DONE) - || (manager->encode_hw_status == ENCODER_PICTURE_DONE)) - && (manager->process_irq)) { -#ifdef USE_VDEC2 - if (get_cpu_type() == MESON_CPU_MAJOR_ID_M8) { - if ((abort_vdec2_flag) && - (get_vdec2_usage() == USAGE_ENCODE)) - set_vdec2_usage(USAGE_NONE); - } -#endif + || (manager->encode_hw_status == ENCODER_NON_IDR_DONE) + || (manager->encode_hw_status == ENCODER_SEQUENCE_DONE) + || (manager->encode_hw_status == ENCODER_PICTURE_DONE)) + && (manager->process_irq)) { wake_up_interruptible(&manager->event.hw_complete); } } @@ -2908,30 +2474,20 @@ static irqreturn_t enc_isr(s32 irq_number, void *para) struct encode_manager_s *manager = (struct encode_manager_s *)para; WRITE_HREG(HCODEC_IRQ_MBOX_CLR, 1); -#ifdef DEBUG_UCODE - /* rain */ - if (READ_HREG(DEBUG_REG) != 0) { - enc_pr(LOG_DEBUG, "dbg%x: %x\n", READ_HREG(DEBUG_REG), - READ_HREG(HCODEC_HENC_SCRATCH_1)); - WRITE_HREG(DEBUG_REG, 0); - return IRQ_HANDLED; - } -#endif - manager->encode_hw_status = READ_HREG(ENCODER_STATUS); if ((manager->encode_hw_status == ENCODER_IDR_DONE) - || (manager->encode_hw_status == ENCODER_NON_IDR_DONE) - || (manager->encode_hw_status == ENCODER_SEQUENCE_DONE) - || (manager->encode_hw_status == ENCODER_PICTURE_DONE)) { + || (manager->encode_hw_status == ENCODER_NON_IDR_DONE) + || (manager->encode_hw_status == ENCODER_SEQUENCE_DONE) + || (manager->encode_hw_status == ENCODER_PICTURE_DONE)) { enc_pr(LOG_ALL, "encoder stage is %d\n", manager->encode_hw_status); } if (((manager->encode_hw_status == ENCODER_IDR_DONE) - || (manager->encode_hw_status == ENCODER_NON_IDR_DONE) - || (manager->encode_hw_status == ENCODER_SEQUENCE_DONE) - || (manager->encode_hw_status == ENCODER_PICTURE_DONE)) - && (!manager->process_irq)) { + || (manager->encode_hw_status == ENCODER_NON_IDR_DONE) + || (manager->encode_hw_status == ENCODER_SEQUENCE_DONE) + || (manager->encode_hw_status == ENCODER_PICTURE_DONE)) + && (!manager->process_irq)) { manager->process_irq = true; if (manager->encode_hw_status != ENCODER_SEQUENCE_DONE) manager->need_reset = true; @@ -2940,38 +2496,11 @@ static irqreturn_t enc_isr(s32 irq_number, void *para) return IRQ_HANDLED; } -static struct class *avc_enc_class; - -static ssize_t dg_manual_store(struct class *cls, struct class_attribute *attr, - const char *buf, size_t len) -{ - int ret = 0; - ret = sscanf(buf, "%x", (unsigned int *)&qp_table_pr); - if (ret < 0) - enc_pr(LOG_INFO, "set encoder table failed\n"); - else - enc_pr(LOG_INFO, "set encoder table print = %d\n", qp_table_pr); - - return len; -} - -static ssize_t dg_manual_show(struct class *cls, struct class_attribute *attr, - char *buf) -{ - size_t len = 0; - enc_pr(LOG_INFO, "encoder table print = %d\n", qp_table_pr); - return len; -} - -static CLASS_ATTR(encode_tbl_debug, 0664, dg_manual_show, dg_manual_store); - - static s32 convert_request(struct encode_wq_s *wq, u32 *cmd_info) { int i = 0; - u8 *qp_tb; u8 *ptr; - u32 weight_offset; + u32 data_offset; u32 cmd = cmd_info[0]; if (!wq) return -1; @@ -2990,92 +2519,85 @@ static s32 convert_request(struct encode_wq_s *wq, u32 *cmd_info) } else if ((cmd == ENCODER_IDR) || (cmd == ENCODER_NON_IDR)) { wq->request.cmd = cmd; wq->request.ucode_mode = cmd_info[1]; - if (wq->request.ucode_mode == UCODE_MODE_FULL) { - wq->request.type = cmd_info[2]; - wq->request.fmt = cmd_info[3]; - wq->request.src = cmd_info[4]; - wq->request.framesize = cmd_info[5]; - wq->request.quant = cmd_info[6]; - wq->request.flush_flag = cmd_info[7]; - wq->request.timeout = cmd_info[8]; - wq->request.crop_top = cmd_info[9]; - wq->request.crop_bottom = cmd_info[10]; - wq->request.crop_left = cmd_info[11]; - wq->request.crop_right = cmd_info[12]; - wq->request.src_w = cmd_info[13]; - wq->request.src_h = cmd_info[14]; - wq->request.scale_enable = cmd_info[15]; - - if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) { - wq->request.nr_mode = - (nr_mode > 0) ? nr_mode : cmd_info[16]; - if (cmd == ENCODER_IDR) - wq->request.nr_mode = 0; - } - - if (wq->request.quant == ADJUSTED_QP_FLAG) { - ptr = (u8 *) &cmd_info[17]; - memcpy(wq->quant_tbl_i4[1], ptr, - sizeof(wq->quant_tbl_i4[1])); - ptr += sizeof(wq->quant_tbl_i4[1]); - memcpy(wq->quant_tbl_i16[1], ptr, - sizeof(wq->quant_tbl_i16[1])); - ptr += sizeof(wq->quant_tbl_i16[1]); - memcpy(wq->quant_tbl_me[1], ptr, - sizeof(wq->quant_tbl_me[1])); - - weight_offset = 17 + - (sizeof(wq->quant_tbl_i4[1]) - + sizeof(wq->quant_tbl_i16[1]) - + sizeof(wq->quant_tbl_me[1])) / 4; - - wq->request.i4_weight -= - cmd_info[weight_offset]; - wq->request.i16_weight -= - cmd_info[weight_offset + 1]; - wq->request.me_weight -= - cmd_info[weight_offset + 2]; - - /* switch to 1 qp table */ - wq->qp_table_id = 1; - if (qp_table_pr != 0) { - qp_tb = (u8 *)(&wq->quant_tbl_i4[1][0]); - for (i = 0; i < 32; i++) { - enc_pr(LOG_INFO, "%d ", *qp_tb); - qp_tb++; - } - enc_pr(LOG_INFO, "\n"); + wq->request.type = cmd_info[2]; + wq->request.fmt = cmd_info[3]; + wq->request.src = cmd_info[4]; + wq->request.framesize = cmd_info[5]; + wq->request.quant = cmd_info[6]; + wq->request.flush_flag = cmd_info[7]; + wq->request.timeout = cmd_info[8]; + wq->request.crop_top = cmd_info[9]; + wq->request.crop_bottom = cmd_info[10]; + wq->request.crop_left = cmd_info[11]; + wq->request.crop_right = cmd_info[12]; + wq->request.src_w = cmd_info[13]; + wq->request.src_h = cmd_info[14]; + wq->request.scale_enable = cmd_info[15]; + wq->request.nr_mode = + (nr_mode > 0) ? nr_mode : cmd_info[16]; + if (cmd == ENCODER_IDR) + wq->request.nr_mode = 0; + + data_offset = 17 + + (sizeof(wq->quant_tbl_i4) + + sizeof(wq->quant_tbl_i16) + + sizeof(wq->quant_tbl_me)) / 4; + + if (wq->request.quant == ADJUSTED_QP_FLAG) { + ptr = (u8 *) &cmd_info[17]; + memcpy(wq->quant_tbl_i4, ptr, + sizeof(wq->quant_tbl_i4)); + ptr += sizeof(wq->quant_tbl_i4); + memcpy(wq->quant_tbl_i16, ptr, + sizeof(wq->quant_tbl_i16)); + ptr += sizeof(wq->quant_tbl_i16); + memcpy(wq->quant_tbl_me, ptr, + sizeof(wq->quant_tbl_me)); + wq->request.i4_weight -= + cmd_info[data_offset++]; + wq->request.i16_weight -= + cmd_info[data_offset++]; + wq->request.me_weight -= + cmd_info[data_offset++]; + if (qp_table_debug) { + u8 *qp_tb = (u8 *)(&wq->quant_tbl_i4[0]); + for (i = 0; i < 32; i++) { + enc_pr(LOG_INFO, "%d ", *qp_tb); + qp_tb++; + } + enc_pr(LOG_INFO, "\n"); - qp_tb = (u8 *) - (&wq->quant_tbl_i16[1][0]); - for (i = 0; i < 32; i++) { - enc_pr(LOG_INFO, "%d ", *qp_tb); - qp_tb++; - } - enc_pr(LOG_INFO, "\n"); + qp_tb = (u8 *)(&wq->quant_tbl_i16[0]); + for (i = 0; i < 32; i++) { + enc_pr(LOG_INFO, "%d ", *qp_tb); + qp_tb++; + } + enc_pr(LOG_INFO, "\n"); - qp_tb = (u8 *)(&wq->quant_tbl_me[1][0]); - for (i = 0; i < 32; i++) { - enc_pr(LOG_INFO, "%d ", *qp_tb); - qp_tb++; - } - enc_pr(LOG_INFO, "\n"); + qp_tb = (u8 *)(&wq->quant_tbl_me[0]); + for (i = 0; i < 32; i++) { + enc_pr(LOG_INFO, "%d ", *qp_tb); + qp_tb++; } - } else { - wq->qp_table_id = 0; - memset(wq->quant_tbl_me[0], wq->request.quant, - sizeof(wq->quant_tbl_me[0])); - memset(wq->quant_tbl_i4[0], wq->request.quant, - sizeof(wq->quant_tbl_i4[0])); - memset(wq->quant_tbl_i16[0], wq->request.quant, - sizeof(wq->quant_tbl_i16[0])); + enc_pr(LOG_INFO, "\n"); } } else { - wq->request.quant = cmd_info[2]; - wq->request.qp_info_size = cmd_info[3]; - wq->request.flush_flag = cmd_info[4]; - wq->request.timeout = cmd_info[5]; + memset(wq->quant_tbl_me, wq->request.quant, + sizeof(wq->quant_tbl_me)); + memset(wq->quant_tbl_i4, wq->request.quant, + sizeof(wq->quant_tbl_i4)); + memset(wq->quant_tbl_i16, wq->request.quant, + sizeof(wq->quant_tbl_i16)); + data_offset += 3; } +#ifdef H264_ENC_CBR + wq->cbr_info.block_w = cmd_info[data_offset++]; + wq->cbr_info.block_h = cmd_info[data_offset++]; + wq->cbr_info.long_th = cmd_info[data_offset++]; + wq->cbr_info.start_tbl_id = cmd_info[data_offset++]; + wq->cbr_info.short_shift = CBR_SHORT_SHIFT; + wq->cbr_info.long_mb_num = CBR_LONG_MB_NUM; +#endif } else { enc_pr(LOG_ERROR, "error cmd = %d, wq: %p.\n", cmd, (void *)wq); @@ -3089,32 +2611,6 @@ void amvenc_avc_start_cmd(struct encode_wq_s *wq, struct encode_request_s *request) { u32 reload_flag = 0; -#ifdef USE_VDEC2 - if (get_cpu_type() == MESON_CPU_MAJOR_ID_M8) { - if ((request->ucode_mode == UCODE_MODE_SW_MIX) && - (enable_dblk > 0)) { - if ((get_vdec2_usage() == USAGE_DEC_4K2K) - || (abort_vdec2_flag)) { - enable_dblk = 2; - if ((abort_vdec2_flag) && - (get_vdec2_usage() == USAGE_ENCODE)) { - enc_pr(LOG_DEBUG, - "switch encode ucode, wq:%p\n", - (void *)wq); - set_vdec2_usage(USAGE_NONE); - } - } else { - if (get_vdec2_usage() == USAGE_NONE) - set_vdec2_usage(USAGE_ENCODE); - if (!vdec_on(VDEC_2)) { - vdec_poweron(VDEC_2); - mdelay(10); - } - enable_dblk = 1; - } - } - } -#endif if (request->ucode_mode != encode_manager.ucode_index) { encode_manager.ucode_index = request->ucode_mode; if (reload_mc(wq)) { @@ -3124,35 +2620,13 @@ void amvenc_avc_start_cmd(struct encode_wq_s *wq, } reload_flag = 1; encode_manager.need_reset = true; - } else if ((request->parent != encode_manager.last_wq) - && (request->ucode_mode == UCODE_MODE_SW_MIX)) { - /* walk around to reset the armrisc */ - if (reload_mc(wq)) { - enc_pr(LOG_ERROR, - "reload mc fail, wq:%p\n", (void *)wq); - return; - } - reload_flag = 1; - encode_manager.need_reset = true; } wq->hw_status = 0; wq->output_size = 0; wq->ucode_index = encode_manager.ucode_index; - if ((request->cmd == ENCODER_SEQUENCE) || - (request->cmd == ENCODER_PICTURE)) - wq->control.finish = true; -#if 0 - if (encode_manager.ucode_index == UCODE_MODE_SW_MIX) - ie_me_mode = (0 & ME_PIXEL_MODE_MASK) << ME_PIXEL_MODE_SHIFT; - else if ((get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) && - (encode_manager.ucode_index == UCODE_MODE_FULL)) { - ie_me_mode = (0 & ME_PIXEL_MODE_MASK) << ME_PIXEL_MODE_SHIFT; - } else - ie_me_mode = (3 & ME_PIXEL_MODE_MASK) << ME_PIXEL_MODE_SHIFT; -#else + ie_me_mode = (0 & ME_PIXEL_MODE_MASK) << ME_PIXEL_MODE_SHIFT; -#endif if (encode_manager.need_reset) { encode_manager.need_reset = false; encode_manager.encode_hw_status = ENCODER_IDLE; @@ -3174,137 +2648,30 @@ void amvenc_avc_start_cmd(struct encode_wq_s *wq, avc_init_dblk_buffer(wq->mem.dblk_buf_canvas); avc_init_reference_buffer(wq->mem.ref_buf_canvas); } - if (encode_manager.ucode_index != UCODE_MODE_SW_MIX) { - if ((request->cmd == ENCODER_IDR) || - (request->cmd == ENCODER_NON_IDR)) - set_input_format(wq, request); - if (request->cmd == ENCODER_IDR) - ie_me_mb_type = HENC_MB_Type_I4MB; - else if (request->cmd == ENCODER_NON_IDR) - ie_me_mb_type = (HENC_SKIP_RUN_AUTO << 16) | - (HENC_MB_Type_AUTO << 4) | - (HENC_MB_Type_AUTO << 0); - else - ie_me_mb_type = 0; - avc_init_ie_me_parameter(wq, request->quant); - } else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M8) { - if ((wq->mem.dblk_buf_canvas & 0xff) == ENC_CANVAS_OFFSET) { - WRITE_HREG(CURRENT_Y_CANVAS_START, - wq->mem.buf_start + - wq->mem.bufspec.dec0_y.buf_start); - WRITE_HREG(CURRENT_C_CANVAS_START, - wq->mem.buf_start + - wq->mem.bufspec.dec0_uv.buf_start); - } else { - WRITE_HREG(CURRENT_Y_CANVAS_START, - wq->mem.buf_start + - wq->mem.bufspec.dec1_y.buf_start); - WRITE_HREG(CURRENT_C_CANVAS_START, - wq->mem.buf_start + - wq->mem.bufspec.dec1_uv.buf_start); - } - WRITE_HREG(CANVAS_ROW_SIZE, - (((wq->pic.encoder_width + 31) >> 5) << 5)); - -#ifdef USE_VDEC2 - if ((enable_dblk == 1) && - ((get_cpu_type() == MESON_CPU_MAJOR_ID_M8))) { - amvdec2_stop(); - WRITE_VREG(VDEC2_AV_SCRATCH_2, 0xffff); - /* set vdec2 input, clone hcodec input - buffer and set to manual mode */ - WRITE_VREG(VDEC2_VLD_MEM_VIFIFO_CONTROL, 0); - - WRITE_VREG(DOS_SW_RESET2, (1 << 4)); - WRITE_VREG(DOS_SW_RESET2, 0); - (void)READ_VREG(DOS_SW_RESET2); - (void)READ_VREG(DOS_SW_RESET2); - WRITE_VREG(VDEC2_POWER_CTL_VLD, - (1 << 4) | (1 << 6) | (1 << 9)); - - WRITE_VREG(VDEC2_VLD_MEM_VIFIFO_START_PTR, - wq->mem.BitstreamStart); - WRITE_VREG(VDEC2_VLD_MEM_VIFIFO_END_PTR, - wq->mem.BitstreamEnd); - WRITE_VREG(VDEC2_VLD_MEM_VIFIFO_CURR_PTR, - wq->mem.BitstreamStart); - - SET_VREG_MASK(VDEC2_VLD_MEM_VIFIFO_CONTROL, 1); - CLEAR_VREG_MASK(VDEC2_VLD_MEM_VIFIFO_CONTROL, 1); - - WRITE_VREG(VDEC2_VLD_MEM_VIFIFO_BUF_CNTL, 2); - WRITE_VREG(VDEC2_VLD_MEM_VIFIFO_WP, - wq->mem.BitstreamStart); - - SET_VREG_MASK(VDEC2_VLD_MEM_VIFIFO_BUF_CNTL, 1); - CLEAR_VREG_MASK(VDEC2_VLD_MEM_VIFIFO_BUF_CNTL, 1); - - WRITE_VREG(VDEC2_VLD_MEM_VIFIFO_CONTROL, - (0x11 << 16) | (1 << 10) | - (7 << 3) | (1 << 2) | (1 << 1)); - - amvdec2_loadmc_ex(ucode_name[UCODE_VDEC2]); - - WRITE_VREG(VDEC2_AV_SCRATCH_1, - wq->mem.vdec2_start_addr - - VDEC2_DEF_BUF_START_ADDR); - WRITE_VREG(VDEC2_AV_SCRATCH_8, - wq->pic.log2_max_pic_order_cnt_lsb); - WRITE_VREG(VDEC2_AV_SCRATCH_9, - wq->pic.log2_max_frame_num); - WRITE_VREG(VDEC2_AV_SCRATCH_B, wq->pic.init_qppicture); - WRITE_VREG(VDEC2_AV_SCRATCH_A, - (((wq->pic.encoder_height + 15) / 16) << 16) | - ((wq->pic.encoder_width + 15) / 16)); - - /* Input/Output canvas */ - WRITE_VREG(VDEC2_ANC0_CANVAS_ADDR, - wq->mem.ref_buf_canvas); - WRITE_VREG(VDEC2_ANC1_CANVAS_ADDR, - wq->mem.dblk_buf_canvas); - - WRITE_VREG(DECODED_MB_Y, 0); - /* MBY limit */ - WRITE_VREG(DECODABLE_MB_Y, 0); - /* VB WP */ - WRITE_VREG(STREAM_WR_PTR, wq->mem.BitstreamStart); - /* NV21 */ - SET_VREG_MASK(VDEC2_MDEC_PIC_DC_CTRL, 1 << 17); - - WRITE_VREG(VDEC2_M4_CONTROL_REG, 1 << 13); - WRITE_VREG(VDEC2_MDEC_PIC_DC_THRESH, 0x404038aa); - - amvdec2_start(); - } -#endif - } + if ((request->cmd == ENCODER_IDR) || + (request->cmd == ENCODER_NON_IDR)) + set_input_format(wq, request); + if (request->cmd == ENCODER_IDR) + ie_me_mb_type = HENC_MB_Type_I4MB; + else if (request->cmd == ENCODER_NON_IDR) + ie_me_mb_type = + (HENC_SKIP_RUN_AUTO << 16) | + (HENC_MB_Type_AUTO << 4) | + (HENC_MB_Type_AUTO << 0); + else + ie_me_mb_type = 0; + avc_init_ie_me_parameter(wq, request->quant); #ifdef MULTI_SLICE_MC -#ifndef USE_OLD_DUMP_MC - if ((get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) && - (encode_manager.ucode_index == UCODE_MODE_FULL)) { - if (fixed_slice_cfg) - WRITE_HREG(FIXED_SLICE_CFG, fixed_slice_cfg); - else if (wq->pic.rows_per_slice != - (wq->pic.encoder_height + 15) >> 4) { - u32 mb_per_slice = (wq->pic.encoder_height + 15) >> 4; - mb_per_slice = mb_per_slice * wq->pic.rows_per_slice; - WRITE_HREG(FIXED_SLICE_CFG, mb_per_slice); - } else - WRITE_HREG(FIXED_SLICE_CFG, 0); + if (fixed_slice_cfg) + WRITE_HREG(FIXED_SLICE_CFG, fixed_slice_cfg); + else if (wq->pic.rows_per_slice != + (wq->pic.encoder_height + 15) >> 4) { + u32 mb_per_slice = (wq->pic.encoder_height + 15) >> 4; + mb_per_slice = mb_per_slice * wq->pic.rows_per_slice; + WRITE_HREG(FIXED_SLICE_CFG, mb_per_slice); } else -#endif - { - if (fixed_slice_cfg) - WRITE_HREG(FIXED_SLICE_CFG, fixed_slice_cfg); - else if (wq->pic.rows_per_slice != - (wq->pic.encoder_height + 15) >> 4) - WRITE_HREG(FIXED_SLICE_CFG, - (wq->pic.rows_per_slice << 16) | - wq->pic.rows_per_slice); - else - WRITE_HREG(FIXED_SLICE_CFG, 0); - } + WRITE_HREG(FIXED_SLICE_CFG, 0); #else WRITE_HREG(FIXED_SLICE_CFG, 0); #endif @@ -3312,32 +2679,33 @@ void amvenc_avc_start_cmd(struct encode_wq_s *wq, encode_manager.encode_hw_status = request->cmd; wq->hw_status = request->cmd; WRITE_HREG(ENCODER_STATUS , request->cmd); - if ((request->cmd == ENCODER_IDR) || (request->cmd == ENCODER_NON_IDR) - || (request->cmd == ENCODER_SEQUENCE) + if ((request->cmd == ENCODER_IDR) + || (request->cmd == ENCODER_NON_IDR) + || (request->cmd == ENCODER_SEQUENCE) || (request->cmd == ENCODER_PICTURE)) encode_manager.process_irq = false; if (reload_flag) amvenc_start(); - if ((encode_manager.ucode_index == UCODE_MODE_SW_MIX) && - ((request->cmd == ENCODER_IDR) || - (request->cmd == ENCODER_NON_IDR))) - wq->control.can_update = true; enc_pr(LOG_ALL, "amvenc_avc_start cmd, wq:%p.\n", (void *)wq); } static void dma_flush(u32 buf_start , u32 buf_size) { + if ((buf_start == 0) || (buf_size == 0)) + return; dma_sync_single_for_device( - &encode_manager.this_pdev->dev, buf_start, + &encode_manager.this_pdev->dev, buf_start, buf_size, DMA_TO_DEVICE); } static void cache_flush(u32 buf_start , u32 buf_size) { + if ((buf_start == 0) || (buf_size == 0)) + return; dma_sync_single_for_cpu( - &encode_manager.this_pdev->dev, buf_start, - buf_size, DMA_FROM_DEVICE); + &encode_manager.this_pdev->dev, buf_start, + buf_size, DMA_FROM_DEVICE); } static u32 getbuffer(struct encode_wq_s *wq, u32 type) @@ -3359,28 +2727,11 @@ static u32 getbuffer(struct encode_wq_s *wq, u32 type) case ENCODER_BUFFER_OUTPUT: ret = wq->mem.BitstreamStart; break; - case ENCODER_BUFFER_INTER_INFO: -#ifndef USE_OLD_DUMP_MC - if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) - ret = wq->mem.dump_info_ddr_start_addr; - else - ret = wq->mem.inter_bits_info_ddr_start_addr; -#else - ret = wq->mem.inter_bits_info_ddr_start_addr; -#endif - break; - case ENCODER_BUFFER_INTRA_INFO: -#ifndef USE_OLD_DUMP_MC - if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) - ret = wq->mem.dump_info_ddr_start_addr; - else - ret = wq->mem.intra_bits_info_ddr_start_addr; -#else - ret = wq->mem.intra_bits_info_ddr_start_addr; -#endif + case ENCODER_BUFFER_DUMP: + ret = wq->mem.dump_info_ddr_start_addr; break; - case ENCODER_BUFFER_QP: - ret = wq->mem.sw_ctl_info_start_addr; + case ENCODER_BUFFER_CBR: + ret = wq->mem.cbr_info_ddr_start_addr; break; default: break; @@ -3395,10 +2746,7 @@ s32 amvenc_avc_start(struct encode_wq_s *wq, u32 clock) avc_poweron(clock); avc_canvas_init(wq); - if (get_cpu_type() >= MESON_CPU_MAJOR_ID_MG9TV) - WRITE_HREG(HCODEC_ASSIST_MMC_CTRL1, 0x32); - else - WRITE_HREG(HCODEC_ASSIST_MMC_CTRL1, 0x2); + WRITE_HREG(HCODEC_ASSIST_MMC_CTRL1, 0x32); if (amvenc_loadmc(p, wq) < 0) return -EBUSY; @@ -3411,20 +2759,10 @@ s32 amvenc_avc_start(struct encode_wq_s *wq, u32 clock) avc_init_input_buffer(wq); /* dct buffer setting */ avc_init_output_buffer(wq); /* output stream buffer */ -#if 0 - if (encode_manager.ucode_index == UCODE_MODE_SW_MIX) - ie_me_mode = (0 & ME_PIXEL_MODE_MASK) << ME_PIXEL_MODE_SHIFT; - else if ((get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) && - (encode_manager.ucode_index == UCODE_MODE_FULL)) { - ie_me_mode = (0 & ME_PIXEL_MODE_MASK) << ME_PIXEL_MODE_SHIFT; - } else - ie_me_mode = (3 & ME_PIXEL_MODE_MASK) << ME_PIXEL_MODE_SHIFT; -#else ie_me_mode = (0 & ME_PIXEL_MODE_MASK) << ME_PIXEL_MODE_SHIFT; -#endif avc_prot_init(wq, NULL, wq->pic.init_qppicture, true); if (request_irq(encode_manager.irq_num, enc_isr, IRQF_SHARED, - "enc-irq", (void *)&encode_manager) == 0) + "enc-irq", (void *)&encode_manager) == 0) encode_manager.irq_requested = true; else encode_manager.irq_requested = false; @@ -3434,56 +2772,20 @@ s32 amvenc_avc_start(struct encode_wq_s *wq, u32 clock) /* reference buffer , need set before each frame start */ avc_init_reference_buffer(wq->mem.ref_buf_canvas); avc_init_assit_buffer(wq); /* assitant buffer for microcode */ - if (encode_manager.ucode_index != UCODE_MODE_SW_MIX) { - ie_me_mb_type = 0; - avc_init_ie_me_parameter(wq, wq->pic.init_qppicture); - } else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M8) { - if ((wq->mem.dblk_buf_canvas & 0xff) == ENC_CANVAS_OFFSET) { - WRITE_HREG(CURRENT_Y_CANVAS_START, - wq->mem.buf_start + - wq->mem.bufspec.dec0_y.buf_start); - WRITE_HREG(CURRENT_C_CANVAS_START, - wq->mem.buf_start + - wq->mem.bufspec.dec0_uv.buf_start); - } else { - WRITE_HREG(CURRENT_Y_CANVAS_START, - wq->mem.buf_start + - wq->mem.bufspec.dec1_y.buf_start); - WRITE_HREG(CURRENT_C_CANVAS_START, - wq->mem.buf_start + - wq->mem.bufspec.dec1_uv.buf_start); - } - WRITE_HREG(CANVAS_ROW_SIZE, - (((wq->pic.encoder_width + 31) >> 5) << 5)); - } + ie_me_mb_type = 0; + avc_init_ie_me_parameter(wq, wq->pic.init_qppicture); WRITE_HREG(ENCODER_STATUS , ENCODER_IDLE); #ifdef MULTI_SLICE_MC -#ifndef USE_OLD_DUMP_MC - if ((get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) && - (encode_manager.ucode_index == UCODE_MODE_FULL)) { - if (fixed_slice_cfg) - WRITE_HREG(FIXED_SLICE_CFG, fixed_slice_cfg); - else if (wq->pic.rows_per_slice != - (wq->pic.encoder_height + 15) >> 4) { - u32 mb_per_slice = (wq->pic.encoder_height + 15) >> 4; - mb_per_slice = mb_per_slice * wq->pic.rows_per_slice; - WRITE_HREG(FIXED_SLICE_CFG, mb_per_slice); - } else - WRITE_HREG(FIXED_SLICE_CFG, 0); + if (fixed_slice_cfg) + WRITE_HREG(FIXED_SLICE_CFG, fixed_slice_cfg); + else if (wq->pic.rows_per_slice != + (wq->pic.encoder_height + 15) >> 4) { + u32 mb_per_slice = (wq->pic.encoder_height + 15) >> 4; + mb_per_slice = mb_per_slice * wq->pic.rows_per_slice; + WRITE_HREG(FIXED_SLICE_CFG, mb_per_slice); } else -#endif - { - if (fixed_slice_cfg) - WRITE_HREG(FIXED_SLICE_CFG, fixed_slice_cfg); - else if (wq->pic.rows_per_slice != - (wq->pic.encoder_height + 15) >> 4) - WRITE_HREG(FIXED_SLICE_CFG, - (wq->pic.rows_per_slice << 16) | - wq->pic.rows_per_slice); - else - WRITE_HREG(FIXED_SLICE_CFG, 0); - } + WRITE_HREG(FIXED_SLICE_CFG, 0); #else WRITE_HREG(FIXED_SLICE_CFG, 0); #endif @@ -3494,16 +2796,10 @@ s32 amvenc_avc_start(struct encode_wq_s *wq, u32 clock) void amvenc_avc_stop(void) { if ((encode_manager.irq_num >= 0) && - (encode_manager.irq_requested == true)) { + (encode_manager.irq_requested == true)) { free_irq(encode_manager.irq_num, &encode_manager); encode_manager.irq_requested = false; } -#ifdef USE_VDEC2 - if (get_cpu_type() == MESON_CPU_MAJOR_ID_M8) { - if ((get_vdec2_usage() != USAGE_DEC_4K2K) && (vdec_on(VDEC_2))) - amvdec2_stop(); - } -#endif amvenc_stop(); avc_poweroff(); } @@ -3543,7 +2839,7 @@ static u32 checkCMA(void) { u32 ret; if (encode_manager.cma_pool_size > 0) { - ret = encode_manager.cma_pool_size / SZ_1M; + ret = encode_manager.cma_pool_size; ret = ret / MIN_SIZE; } else ret = 0; @@ -3556,7 +2852,6 @@ static s32 amvenc_avc_open(struct inode *inode, struct file *file) { s32 r = 0; struct encode_wq_s *wq = NULL; - u8 cur_lev; file->private_data = NULL; enc_pr(LOG_DEBUG, "avc open\n"); #ifdef CONFIG_AM_JPEG_ENCODER @@ -3592,10 +2887,10 @@ static s32 amvenc_avc_open(struct inode *inode, struct file *file) #ifdef CONFIG_CMA if (encode_manager.use_reserve == false) { wq->mem.buf_start = codec_mm_alloc_for_dma(ENCODE_NAME, - (MIN_SIZE * SZ_1M) >> PAGE_SHIFT, 0, + MIN_SIZE >> PAGE_SHIFT, 0, CODEC_MM_FLAGS_CPU); if (wq->mem.buf_start) { - wq->mem.buf_size = MIN_SIZE * SZ_1M; + wq->mem.buf_size = MIN_SIZE; enc_pr(LOG_DEBUG, "allocating phys 0x%x, size %dk, wq:%p.\n", wq->mem.buf_start, @@ -3611,9 +2906,8 @@ static s32 amvenc_avc_open(struct inode *inode, struct file *file) } #endif - cur_lev = wq->mem.cur_buf_lev; - if ((wq->mem.buf_start == 0) || - (wq->mem.buf_size < amvenc_buffspec[cur_lev].min_buffsize)) { + if (wq->mem.buf_start == 0 || + wq->mem.buf_size < MIN_SIZE) { enc_pr(LOG_ERROR, "alloc mem failed, start: 0x%x, size:0x%x, wq:%p.\n", wq->mem.buf_start, @@ -3622,38 +2916,9 @@ static s32 amvenc_avc_open(struct inode *inode, struct file *file) return -ENOMEM; } - wq->mem.cur_buf_lev = AMVENC_BUFFER_LEVEL_1080P; - memcpy(&wq->mem.bufspec, &amvenc_buffspec[wq->mem.cur_buf_lev], + memcpy(&wq->mem.bufspec, &amvenc_buffspec[0], sizeof(struct BuffInfo_s)); - wq->mem.inter_bits_info_ddr_start_addr = - wq->mem.buf_start + wq->mem.bufspec.inter_bits_info.buf_start; - wq->mem.inter_mv_info_ddr_start_addr = - wq->mem.buf_start + wq->mem.bufspec.inter_mv_info.buf_start; - wq->mem.intra_bits_info_ddr_start_addr = - wq->mem.buf_start + wq->mem.bufspec.intra_bits_info.buf_start; - wq->mem.intra_pred_info_ddr_start_addr = - wq->mem.buf_start + wq->mem.bufspec.intra_pred_info.buf_start; - wq->mem.sw_ctl_info_start_addr = - wq->mem.buf_start + wq->mem.bufspec.qp_info.buf_start; - wq->mem.scaler_buff_start_addr = - wq->mem.buf_start + wq->mem.bufspec.scale_buff.buf_start; -#ifdef USE_VDEC2 - wq->mem.vdec2_start_addr = - wq->mem.buf_start + wq->mem.bufspec.vdec2_info.buf_start; -#endif -#ifndef USE_OLD_DUMP_MC - if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) { - wq->mem.dump_info_ddr_start_addr = - wq->mem.inter_bits_info_ddr_start_addr; - } else { - wq->mem.dump_info_ddr_start_addr = 0; - wq->mem.dump_info_ddr_size = 0; - } -#else - wq->mem.dump_info_ddr_start_addr = 0; - wq->mem.dump_info_ddr_size = 0; -#endif enc_pr(LOG_DEBUG, "amvenc_avc memory config sucess, buff start:0x%x, size is 0x%x, wq:%p.\n", wq->mem.buf_start, wq->mem.buf_size, (void *)wq); @@ -3691,34 +2956,10 @@ static long amvenc_avc_ioctl(struct file *file, u32 cmd, ulong arg) put_user(2, (u32 *)arg); break; case AMVENC_AVC_IOC_INPUT_UPDATE: - if (copy_from_user(addr_info, (void *)arg, - MAX_ADDR_INFO_SIZE * sizeof(u32))) { - enc_pr(LOG_ERROR, - "avc update input ptr error, wq: %p.\n", - (void *)wq); - return -1; - } - - wq->control.dct_buffer_write_ptr = addr_info[2]; - if ((encode_manager.current_wq == wq) && - (wq->control.can_update == true)) { - buf_start = getbuffer(wq, addr_info[0]); - if (buf_start) - dma_flush(buf_start + - wq->control.dct_flush_start, - wq->control.dct_buffer_write_ptr - - wq->control.dct_flush_start); - WRITE_HREG(HCODEC_QDCT_MB_WR_PTR, - (wq->mem.dct_buff_start_addr + - wq->control.dct_buffer_write_ptr)); - wq->control.dct_flush_start = - wq->control.dct_buffer_write_ptr; - } - wq->control.finish = (addr_info[3] == 1) ? true : false; break; case AMVENC_AVC_IOC_NEW_CMD: if (copy_from_user(addr_info, (void *)arg, - MAX_ADDR_INFO_SIZE * sizeof(u32))) { + MAX_ADDR_INFO_SIZE * sizeof(u32))) { enc_pr(LOG_ERROR, "avc get new cmd error, wq:%p.\n", (void *)wq); return -1; @@ -3736,37 +2977,21 @@ static long amvenc_avc_ioctl(struct file *file, u32 cmd, ulong arg) put_user(wq->hw_status, (u32 *)arg); break; case AMVENC_AVC_IOC_GET_OUTPUT_SIZE: - if ((get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) - && (wq->ucode_index == UCODE_MODE_FULL)) { -#ifndef USE_OLD_DUMP_MC - addr_info[0] = wq->output_size; - addr_info[1] = wq->me_weight; - addr_info[2] = wq->i4_weight; - addr_info[3] = wq->i16_weight; - r = copy_to_user((u32 *)arg, - addr_info , 4 * sizeof(u32)); -#else - put_user(wq->output_size, (u32 *)arg); -#endif - } else { - put_user(wq->output_size, (u32 *)arg); - } + addr_info[0] = wq->output_size; + addr_info[1] = wq->me_weight; + addr_info[2] = wq->i4_weight; + addr_info[3] = wq->i16_weight; + r = copy_to_user((u32 *)arg, + addr_info , 4 * sizeof(u32)); break; case AMVENC_AVC_IOC_CONFIG_INIT: if (copy_from_user(addr_info, (void *)arg, - MAX_ADDR_INFO_SIZE * sizeof(u32))) { + MAX_ADDR_INFO_SIZE * sizeof(u32))) { enc_pr(LOG_ERROR, "avc config init error, wq:%p.\n", (void *)wq); return -1; } - if (addr_info[0] <= UCODE_MODE_SW_MIX) - wq->ucode_index = addr_info[0]; - else - wq->ucode_index = UCODE_MODE_FULL; - - if (get_cpu_type() < MESON_CPU_MAJOR_ID_M8) - wq->ucode_index = UCODE_MODE_FULL; - + wq->ucode_index = UCODE_MODE_FULL; #ifdef MULTI_SLICE_MC wq->pic.rows_per_slice = addr_info[1]; enc_pr(LOG_DEBUG, @@ -3777,8 +3002,8 @@ static long amvenc_avc_ioctl(struct file *file, u32 cmd, ulong arg) "avc init as mode %d, wq: %p.\n", wq->ucode_index, (void *)wq); - if ((addr_info[2] > wq->mem.bufspec.max_width) || - (addr_info[3] > wq->mem.bufspec.max_height)) { + if (addr_info[2] > wq->mem.bufspec.max_width || + addr_info[3] > wq->mem.bufspec.max_height) { enc_pr(LOG_ERROR, "avc config init- encode size %dx%d is larger than supported (%dx%d). wq:%p.\n", addr_info[2], addr_info[3], @@ -3788,49 +3013,24 @@ static long amvenc_avc_ioctl(struct file *file, u32 cmd, ulong arg) } wq->pic.encoder_width = addr_info[2]; wq->pic.encoder_height = addr_info[3]; - + if (wq->pic.encoder_width * + wq->pic.encoder_height >= 1280 * 720) + clock_level = 6; + else + clock_level = 5; avc_buffspec_init(wq); complete(&encode_manager.event.request_in_com); addr_info[1] = wq->mem.bufspec.dct.buf_start; addr_info[2] = wq->mem.bufspec.dct.buf_size; - addr_info[3] = wq->mem.bufspec.dec0_y.buf_start; - addr_info[4] = wq->mem.bufspec.dec0_y.buf_size; - addr_info[5] = wq->mem.bufspec.dec0_uv.buf_start; - addr_info[6] = wq->mem.bufspec.dec0_uv.buf_size; - addr_info[7] = wq->mem.bufspec.dec1_y.buf_start; - addr_info[8] = wq->mem.bufspec.dec1_y.buf_size; - addr_info[9] = wq->mem.bufspec.dec1_uv.buf_start; - addr_info[10] = wq->mem.bufspec.dec1_uv.buf_size; - addr_info[11] = wq->mem.bufspec.bitstream.buf_start; - addr_info[12] = wq->mem.bufspec.bitstream.buf_size; -#ifndef USE_OLD_DUMP_MC - if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) { - /* new dump info addr same as inter_bits_info address */ - addr_info[13] = - wq->mem.bufspec.inter_bits_info.buf_start; - addr_info[14] = - wq->mem.dump_info_ddr_size; - } else { - addr_info[13] = - wq->mem.bufspec.inter_bits_info.buf_start; - addr_info[14] = - wq->mem.bufspec.inter_bits_info.buf_size; - } -#else - addr_info[13] = wq->mem.bufspec.inter_bits_info.buf_start; - addr_info[14] = wq->mem.bufspec.inter_bits_info.buf_size; -#endif - addr_info[15] = wq->mem.bufspec.inter_mv_info.buf_start; - addr_info[16] = wq->mem.bufspec.inter_mv_info.buf_size; - addr_info[17] = wq->mem.bufspec.intra_bits_info.buf_start; - addr_info[18] = wq->mem.bufspec.intra_bits_info.buf_size; - addr_info[19] = wq->mem.bufspec.intra_pred_info.buf_start; - addr_info[20] = wq->mem.bufspec.intra_pred_info.buf_size; - addr_info[21] = wq->mem.bufspec.qp_info.buf_start; - addr_info[22] = wq->mem.bufspec.qp_info.buf_size; - addr_info[23] = wq->mem.bufspec.scale_buff.buf_start; - addr_info[24] = wq->mem.bufspec.scale_buff.buf_size; - r = copy_to_user((u32 *)arg, addr_info , 25*sizeof(u32)); + addr_info[3] = wq->mem.bufspec.bitstream.buf_start; + addr_info[4] = wq->mem.bufspec.bitstream.buf_size; + addr_info[5] = wq->mem.bufspec.scale_buff.buf_start; + addr_info[6] = wq->mem.bufspec.scale_buff.buf_size; + addr_info[7] = wq->mem.bufspec.dump_info.buf_start; + addr_info[8] = wq->mem.bufspec.dump_info.buf_size; + addr_info[9] = wq->mem.bufspec.cbr_info.buf_start; + addr_info[10] = wq->mem.bufspec.cbr_info.buf_size; + r = copy_to_user((u32 *)arg, addr_info , 11*sizeof(u32)); break; case AMVENC_AVC_IOC_FLUSH_CACHE: if (copy_from_user(addr_info, (void *)arg, @@ -3840,9 +3040,8 @@ static long amvenc_avc_ioctl(struct file *file, u32 cmd, ulong arg) return -1; } buf_start = getbuffer(wq, addr_info[0]); - if (buf_start) - dma_flush(buf_start + addr_info[1], - addr_info[2] - addr_info[1]); + dma_flush(buf_start + addr_info[1], + addr_info[2] - addr_info[1]); break; case AMVENC_AVC_IOC_FLUSH_DMA: if (copy_from_user(addr_info, (void *)arg, @@ -3852,9 +3051,8 @@ static long amvenc_avc_ioctl(struct file *file, u32 cmd, ulong arg) return -1; } buf_start = getbuffer(wq, addr_info[0]); - if (buf_start) - cache_flush(buf_start + addr_info[1], - addr_info[2] - addr_info[1]); + cache_flush(buf_start + addr_info[1], + addr_info[2] - addr_info[1]); break; case AMVENC_AVC_IOC_GET_BUFFINFO: put_user(wq->mem.buf_size, (u32 *)arg); @@ -3928,7 +3126,7 @@ static long amvenc_avc_ioctl(struct file *file, u32 cmd, ulong arg) #ifdef CONFIG_COMPAT static long amvenc_avc_compat_ioctl(struct file *filp, - unsigned int cmd, unsigned long args) + unsigned int cmd, unsigned long args) { unsigned long ret; @@ -3951,12 +3149,12 @@ static s32 avc_mmap(struct file *filp, struct vm_area_struct *vma) if (!off) off += wq->mem.buf_start; enc_pr(LOG_ALL, - "vma_size is %ld , off is %ld, wq:%p.\n", - vma_size , off, (void *)wq); + "vma_size is %ld , off is %ld, wq:%p.\n", + vma_size , off, (void *)wq); vma->vm_flags |= VM_DONTEXPAND | VM_DONTDUMP | VM_IO; /* vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); */ if (remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT, - vma->vm_end - vma->vm_start, vma->vm_page_prot)) { + vma->vm_end - vma->vm_start, vma->vm_page_prot)) { enc_pr(LOG_ERROR, "set_cached: failed remap_pfn_range, wq:%p.\n", (void *)wq); @@ -3991,7 +3189,7 @@ static const struct file_operations amvenc_avc_fops = { /* work queue function */ static s32 encode_process_request(struct encode_manager_s *manager, - struct encode_queue_item_s *pitem) + struct encode_queue_item_s *pitem) { s32 ret = 0; struct encode_wq_s *wq = pitem->request.parent; @@ -4003,35 +3201,22 @@ static s32 encode_process_request(struct encode_manager_s *manager, u32 flush_size = ((wq->pic.encoder_width + 31) >> 5 << 5) * ((wq->pic.encoder_height + 15) >> 4 << 4) * 3 / 2; - if (((request->cmd == ENCODER_IDR) || (request->cmd == ENCODER_NON_IDR)) - && (request->ucode_mode == UCODE_MODE_SW_MIX)) { - if (request->flush_flag & AMVENC_FLUSH_FLAG_QP) { - buf_start = getbuffer(wq, ENCODER_BUFFER_QP); - if ((buf_start) && (request->qp_info_size > 0)) - dma_flush(buf_start, request->qp_info_size); +#ifdef H264_ENC_CBR + if (request->cmd == ENCODER_IDR || request->cmd == ENCODER_NON_IDR) { + if (request->flush_flag & AMVENC_FLUSH_FLAG_CBR + && get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB) { + void *vaddr = + phys_to_virt(wq->mem.cbr_info_ddr_start_addr); + ConvertTable2Risc(vaddr, 0xa00); + buf_start = getbuffer(wq, ENCODER_BUFFER_CBR); + dma_flush(buf_start, wq->mem.cbr_info_ddr_size); } } +#endif Again: amvenc_avc_start_cmd(wq, request); - while (wq->control.finish == 0) - wait_event_interruptible_timeout(manager->event.hw_complete, - (wq->control.finish == true), msecs_to_jiffies(1)); - - if ((wq->control.finish == true) && - (wq->control.dct_flush_start < wq->control.dct_buffer_write_ptr)) { - buf_start = getbuffer(wq, ENCODER_BUFFER_INPUT); - if (buf_start) - dma_flush(buf_start + wq->control.dct_flush_start, - wq->control.dct_buffer_write_ptr - - wq->control.dct_flush_start); - WRITE_HREG(HCODEC_QDCT_MB_WR_PTR, - (wq->mem.dct_buff_start_addr + - wq->control.dct_buffer_write_ptr)); - wq->control.dct_flush_start = wq->control.dct_buffer_write_ptr; - } - if (no_timeout) { wait_event_interruptible(manager->event.hw_complete, (manager->encode_hw_status == ENCODER_IDR_DONE @@ -4060,9 +3245,8 @@ Again: wq->hw_status = manager->encode_hw_status; if (request->flush_flag & AMVENC_FLUSH_FLAG_OUTPUT) { buf_start = getbuffer(wq, ENCODER_BUFFER_OUTPUT); - if (buf_start) - cache_flush(buf_start, - wq->sps_size + wq->pps_size); + cache_flush(buf_start, + wq->sps_size + wq->pps_size); } wq->output_size = (wq->sps_size << 16) | wq->pps_size; } else { @@ -4073,36 +3257,15 @@ Again: if (request->flush_flag & AMVENC_FLUSH_FLAG_OUTPUT) { buf_start = getbuffer(wq, ENCODER_BUFFER_OUTPUT); - if (buf_start) - cache_flush(buf_start, wq->output_size); + cache_flush(buf_start, wq->output_size); } if (request->flush_flag & - AMVENC_FLUSH_FLAG_INTER_INFO) { + AMVENC_FLUSH_FLAG_DUMP) { buf_start = getbuffer(wq, - ENCODER_BUFFER_INTER_INFO); - size = wq->mem.inter_mv_info_ddr_start_addr - - wq->mem.inter_bits_info_ddr_start_addr + - wq->mem.bufspec.inter_mv_info.buf_size; -#ifndef USE_OLD_DUMP_MC - if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) - size = wq->mem.dump_info_ddr_size; -#endif - if (buf_start) - cache_flush(buf_start, size); - } - if (request->flush_flag & - AMVENC_FLUSH_FLAG_INTRA_INFO) { - buf_start = getbuffer(wq, - ENCODER_BUFFER_INTRA_INFO); - size = wq->mem.intra_pred_info_ddr_start_addr - - wq->mem.intra_bits_info_ddr_start_addr + - wq->mem.bufspec.intra_pred_info.buf_size; -#ifndef USE_OLD_DUMP_MC - if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) - size = wq->mem.dump_info_ddr_size; -#endif - if (buf_start) - cache_flush(buf_start, size); + ENCODER_BUFFER_DUMP); + size = wq->mem.dump_info_ddr_size; + cache_flush(buf_start, size); + enc_pr(LOG_DEBUG, "CBR flush dump_info done--- "); } if (request->flush_flag & AMVENC_FLUSH_FLAG_REFERENCE) { @@ -4113,8 +3276,7 @@ Again: else ref_id = ENCODER_BUFFER_REF1; buf_start = getbuffer(wq, ref_id); - if (buf_start) - cache_flush(buf_start, flush_size); + cache_flush(buf_start, flush_size); } } else { manager->encode_hw_status = ENCODER_ERROR; @@ -4130,18 +3292,14 @@ Again: READ_HREG(ENCODER_STATUS), READ_HREG(HCODEC_QDCT_STATUS_CTRL)); enc_pr(LOG_DEBUG, - "vlc status: 0x%x, me status: 0x%x, risc pc:0x%x\n", + "vlc status: 0x%x, me status: 0x%x, risc pc:0x%x, debug:0x%x\n", READ_HREG(HCODEC_VLC_STATUS_CTRL), READ_HREG(HCODEC_ME_STATUS), - READ_HREG(HCODEC_MPC_E)); + READ_HREG(HCODEC_MPC_E), + READ_HREG(DEBUG_REG)); amvenc_avc_light_reset(wq, 30); } } - - wq->control.can_update = false; - wq->control.dct_buffer_write_ptr = 0; - wq->control.dct_flush_start = 0; - wq->control.finish = false; atomic_inc(&wq->request_ready); wake_up_interruptible(&wq->request_complete); return ret; @@ -4177,7 +3335,7 @@ s32 encode_wq_add_request(struct encode_wq_s *wq) } pitem = list_entry(encode_manager.free_queue.next, - struct encode_queue_item_s, list); + struct encode_queue_item_s, list); if (IS_ERR(pitem)) goto error; @@ -4185,10 +3343,6 @@ s32 encode_wq_add_request(struct encode_wq_s *wq) memset(&wq->request, 0, sizeof(struct encode_request_s)); wq->hw_status = 0; wq->output_size = 0; - wq->control.dct_buffer_write_ptr = 0; - wq->control.dct_flush_start = 0; - wq->control.finish = false; - wq->control.can_update = false; pitem->request.parent = wq; list_move_tail(&pitem->list, &encode_manager.process_queue); spin_unlock(&encode_manager.event.sem_lock); @@ -4224,6 +3378,15 @@ struct encode_wq_s *create_encode_work_queue(void) encode_work_queue->pic.frame_number = 0; encode_work_queue->pic.pic_order_cnt_lsb = 0; encode_work_queue->ucode_index = UCODE_MODE_FULL; + +#ifdef H264_ENC_CBR + encode_work_queue->cbr_info.block_w = 16; + encode_work_queue->cbr_info.block_h = 9; + encode_work_queue->cbr_info.long_th = CBR_LONG_THRESH; + encode_work_queue->cbr_info.start_tbl_id = START_TABLE_ID; + encode_work_queue->cbr_info.short_shift = CBR_SHORT_SHIFT; + encode_work_queue->cbr_info.long_mb_num = CBR_LONG_MB_NUM; +#endif init_waitqueue_head(&encode_work_queue->request_complete); atomic_set(&encode_work_queue->request_ready, 0); spin_lock(&encode_manager.event.sem_lock); @@ -4256,9 +3419,9 @@ struct encode_wq_s *create_encode_work_queue(void) } static void _destroy_encode_work_queue(struct encode_manager_s *manager, - struct encode_wq_s **wq, - struct encode_wq_s *encode_work_queue, - bool *find) + struct encode_wq_s **wq, + struct encode_wq_s *encode_work_queue, + bool *find) { struct list_head *head; struct encode_wq_s *wp_tmp = NULL; @@ -4315,26 +3478,24 @@ s32 destroy_encode_work_queue(struct encode_wq_s *encode_work_queue) head = &encode_manager.process_queue; list_for_each_entry_safe(pitem, tmp, head, list) { - if (pitem) { - if (pitem->request.parent == - encode_work_queue) { - pitem->request.parent = NULL; - enc_pr(LOG_DEBUG, - "warning--remove not process request, should not be here.\n"); - list_move_tail(&pitem->list, - &encode_manager.free_queue); - } + if (pitem && pitem->request.parent == + encode_work_queue) { + pitem->request.parent = NULL; + enc_pr(LOG_DEBUG, + "warning--remove not process request, should not be here.\n"); + list_move_tail(&pitem->list, + &encode_manager.free_queue); } } _destroy_encode_work_queue(&encode_manager, &wq, - encode_work_queue, &find); + encode_work_queue, &find); spin_unlock(&encode_manager.event.sem_lock); #ifdef CONFIG_CMA if (encode_work_queue->mem.buf_start) { codec_mm_free_for_dma( - ENCODE_NAME, - encode_work_queue->mem.buf_start); + ENCODE_NAME, + encode_work_queue->mem.buf_start); encode_work_queue->mem.buf_start = 0; } @@ -4414,7 +3575,7 @@ static s32 encode_monitor_thread(void *data) continue; } else if (!list_empty(&manager->process_queue)) { pitem = list_entry(manager->process_queue.next, - struct encode_queue_item_s, list); + struct encode_queue_item_s, list); list_del(&pitem->list); manager->current_item = pitem; manager->current_wq = pitem->request.parent; @@ -4446,13 +3607,6 @@ static s32 encode_start_monitor(void) { s32 ret = 0; - if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) - clock_level = 5; - else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M8M2) - clock_level = 3; - else - clock_level = 1; - if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB) { y_tnr_mot2alp_nrm_gain = 216; y_tnr_mot2alp_dis_gain = 144; @@ -4469,7 +3623,7 @@ static s32 encode_start_monitor(void) enc_pr(LOG_DEBUG, "encode start monitor.\n"); encode_manager.process_queue_state = ENCODE_PROCESS_QUEUE_START; encode_manager.encode_thread = kthread_run(encode_monitor_thread, - &encode_manager, "encode_monitor"); + &encode_manager, "encode_monitor"); if (IS_ERR(encode_manager.encode_thread)) { ret = PTR_ERR(encode_manager.encode_thread); encode_manager.process_queue_state = ENCODE_PROCESS_QUEUE_STOP; @@ -4521,13 +3675,13 @@ static s32 encode_wq_init(void) INIT_LIST_HEAD(&encode_manager.wq); tasklet_init(&encode_manager.encode_tasklet, - encode_isr_tasklet, - (ulong)&encode_manager); + encode_isr_tasklet, + (ulong)&encode_manager); for (i = 0; i < MAX_ENCODE_REQUEST; i++) { pitem = kcalloc(1, - sizeof(struct encode_queue_item_s), - GFP_KERNEL); + sizeof(struct encode_queue_item_s), + GFP_KERNEL); if (IS_ERR(pitem)) { enc_pr(LOG_ERROR, "can't request queue item memory.\n"); return -1; @@ -4713,8 +3867,8 @@ s32 init_avc_device(void) } amvenc_avc_dev = device_create(&amvenc_avc_class, NULL, - MKDEV(avc_device_major, 0), NULL, - DEVICE_NAME); + MKDEV(avc_device_major, 0), NULL, + DEVICE_NAME); if (IS_ERR(amvenc_avc_dev)) { enc_pr(LOG_ERROR, "create amvenc_avc device error.\n"); @@ -4751,10 +3905,10 @@ static s32 avc_mem_device_init(struct reserved_mem *rmem, struct device *dev) encode_manager.reserve_mem.buf_size = res.end - res.start + 1; if (encode_manager.reserve_mem.buf_size >= - amvenc_buffspec[AMVENC_BUFFER_LEVEL_1080P].min_buffsize) { + amvenc_buffspec[0].min_buffsize) { encode_manager.max_instance = encode_manager.reserve_mem.buf_size / - amvenc_buffspec[AMVENC_BUFFER_LEVEL_1080P].min_buffsize; + amvenc_buffspec[0].min_buffsize; if (encode_manager.max_instance > MAX_ENCODE_INSTANCE) encode_manager.max_instance = MAX_ENCODE_INSTANCE; encode_manager.reserve_buff = kzalloc( @@ -4768,8 +3922,7 @@ static s32 avc_mem_device_init(struct reserved_mem *rmem, struct device *dev) reserve_buff = &encode_manager.reserve_buff[i]; reserve_buff->buf_start = i * - amvenc_buffspec - [AMVENC_BUFFER_LEVEL_1080P] + amvenc_buffspec[0] .min_buffsize + encode_manager.reserve_mem.buf_start; reserve_buff->buf_size = @@ -4796,7 +3949,7 @@ static s32 avc_mem_device_init(struct reserved_mem *rmem, struct device *dev) enc_pr(LOG_ERROR, "amvenc_avc memory resource too small, size is 0x%x. Need 0x%x bytes at least.\n", encode_manager.reserve_mem.buf_size, - amvenc_buffspec[AMVENC_BUFFER_LEVEL_1080P] + amvenc_buffspec[0] .min_buffsize); encode_manager.reserve_mem.buf_start = 0; encode_manager.reserve_mem.buf_size = 0; @@ -4837,8 +3990,8 @@ static s32 amvenc_avc_probe(struct platform_device *pdev) return -EFAULT; #else encode_manager.cma_pool_size = - (codec_mm_get_total_size() > (40 * SZ_1M)) ? - (40 * SZ_1M) : codec_mm_get_total_size(); + (codec_mm_get_total_size() > (MIN_SIZE * 2)) ? + (MIN_SIZE * 2) : codec_mm_get_total_size(); enc_pr(LOG_DEBUG, "amvenc_avc - cma memory pool size: %d MB\n", (u32)encode_manager.cma_pool_size / SZ_1M); @@ -4861,12 +4014,6 @@ static s32 amvenc_avc_probe(struct platform_device *pdev) r = init_avc_device(); enc_pr(LOG_INFO, "amvenc_avc probe end.\n"); - - avc_enc_class = class_create(THIS_MODULE, "avc_enc_debug"); - if (IS_ERR(avc_enc_class)) - return PTR_ERR(avc_enc_class); - r = class_create_file(avc_enc_class, &class_attr_encode_tbl_debug); - return r; } @@ -4879,10 +4026,6 @@ static s32 amvenc_avc_remove(struct platform_device *pdev) } uninit_avc_device(); enc_pr(LOG_INFO, "amvenc_avc remove.\n"); - - class_remove_file(avc_enc_class, &class_attr_encode_tbl_debug); - class_destroy(avc_enc_class); - return 0; } @@ -4938,6 +4081,25 @@ static s32 __init avc_mem_setup(struct reserved_mem *rmem) return 0; } +module_param(fixed_slice_cfg, uint, 0664); +MODULE_PARM_DESC(fixed_slice_cfg, "\n fixed_slice_cfg\n"); + +module_param(clock_level, uint, 0664); +MODULE_PARM_DESC(clock_level, "\n clock_level\n"); + +module_param(encode_print_level, uint, 0664); +MODULE_PARM_DESC(encode_print_level, "\n encode_print_level\n"); + +module_param(no_timeout, uint, 0664); +MODULE_PARM_DESC(no_timeout, "\n no_timeout flag for process request\n"); + +module_param(nr_mode, int, 0664); +MODULE_PARM_DESC(nr_mode, "\n nr_mode option\n"); + +module_param(qp_table_debug, uint, 0664); +MODULE_PARM_DESC(qp_table_debug, "\n print qp table\n"); + +#ifdef MORE_MODULE_PARAM module_param(me_mv_merge_ctl, uint, 0664); MODULE_PARM_DESC(me_mv_merge_ctl, "\n me_mv_merge_ctl\n"); @@ -4965,24 +4127,6 @@ MODULE_PARM_DESC(me_sad_enough_01, "\n me_sad_enough_01\n"); module_param(me_sad_enough_23, uint, 0664); MODULE_PARM_DESC(me_sad_enough_23, "\n me_sad_enough_23\n"); -module_param(fixed_slice_cfg, uint, 0664); -MODULE_PARM_DESC(fixed_slice_cfg, "\n fixed_slice_cfg\n"); - -module_param(enable_dblk, uint, 0664); -MODULE_PARM_DESC(enable_dblk, "\n enable_dblk\n"); - -module_param(clock_level, uint, 0664); -MODULE_PARM_DESC(clock_level, "\n clock_level\n"); - -module_param(encode_print_level, uint, 0664); -MODULE_PARM_DESC(encode_print_level, "\n encode_print_level\n"); - -module_param(no_timeout, uint, 0664); -MODULE_PARM_DESC(no_timeout, "\n no_timeout flag for process request\n"); - -module_param(nr_mode, int, 0664); -MODULE_PARM_DESC(nr_mode, "\n nr_mode option\n"); - module_param(y_tnr_mc_en, uint, 0664); MODULE_PARM_DESC(y_tnr_mc_en, "\n y_tnr_mc_en option\n"); module_param(y_tnr_txt_mode, uint, 0664); @@ -5082,6 +4226,7 @@ module_param(c_bld_beta_min, uint, 0664); MODULE_PARM_DESC(c_bld_beta_min, "\n c_bld_beta_min option\n"); module_param(c_bld_beta_max, uint, 0664); MODULE_PARM_DESC(c_bld_beta_max, "\n c_bld_beta_max option\n"); +#endif module_init(amvenc_avc_driver_init_module); module_exit(amvenc_avc_driver_remove_module); diff --git a/drivers/frame_sink/encoder/h264/encoder.h b/drivers/frame_sink/encoder/h264/encoder.h index db01573..db4f255 100644 --- a/drivers/frame_sink/encoder/h264/encoder.h +++ b/drivers/frame_sink/encoder/h264/encoder.h @@ -93,14 +93,6 @@ WRITE_HHI_REG_BITS(HHI_VDEC_CLK_CNTL, 0, 24, 1); \ } while (0) -#if 0/* MESON_CPU_TYPE == MESON_CPU_TYPE_MESON8 */ -#define USE_VDEC2 -#endif - -#ifdef USE_VDEC2 -#define VDEC2_DEF_BUF_START_ADDR 0x01000000 -#endif - #define LOG_ALL 0 #define LOG_INFO 1 #define LOG_DEBUG 2 @@ -159,10 +151,6 @@ enum amvenc_frame_fmt_e { MAX_FRAME_FMT }; -#define AMVENC_BUFFER_LEVEL_480P 0 -#define AMVENC_BUFFER_LEVEL_720P 1 -#define AMVENC_BUFFER_LEVEL_1080P 2 - #define MAX_ENCODE_REQUEST 8 /* 64 */ #define MAX_ENCODE_INSTANCE 8 /* 64 */ @@ -176,14 +164,18 @@ enum amvenc_frame_fmt_e { #define AMVENC_FLUSH_FLAG_INTRA_INFO 0x8 #define AMVENC_FLUSH_FLAG_INTER_INFO 0x10 #define AMVENC_FLUSH_FLAG_QP 0x20 +#define AMVENC_FLUSH_FLAG_DUMP 0x40 +#define AMVENC_FLUSH_FLAG_CBR 0x80 #define ENCODER_BUFFER_INPUT 0 #define ENCODER_BUFFER_REF0 1 #define ENCODER_BUFFER_REF1 2 #define ENCODER_BUFFER_OUTPUT 3 -#define ENCODER_BUFFER_INTER_INFO 4 -#define ENCODER_BUFFER_INTRA_INFO 5 -#define ENCODER_BUFFER_QP 6 +#define ENCODER_BUFFER_INTER_INFO 4 +#define ENCODER_BUFFER_INTRA_INFO 5 +#define ENCODER_BUFFER_QP 6 +#define ENCODER_BUFFER_DUMP 7 +#define ENCODER_BUFFER_CBR 8 struct encode_wq_s; @@ -195,7 +187,6 @@ struct encode_request_s { u32 src; u32 framesize; - u32 qp_info_size; u32 me_weight; u32 i4_weight; @@ -240,21 +231,14 @@ struct BuffInfo_s { struct Buff_s dec1_uv; struct Buff_s assit; struct Buff_s bitstream; - struct Buff_s inter_bits_info; - struct Buff_s inter_mv_info; - struct Buff_s intra_bits_info; - struct Buff_s intra_pred_info; - struct Buff_s qp_info; struct Buff_s scale_buff; -#ifdef USE_VDEC2 - struct Buff_s vdec2_info; -#endif + struct Buff_s dump_info; + struct Buff_s cbr_info; }; struct encode_meminfo_s { u32 buf_start; u32 buf_size; - u8 cur_buf_lev; u32 BitstreamStart; u32 BitstreamEnd; @@ -266,19 +250,14 @@ struct encode_meminfo_s { /*microcode assitant buffer*/ u32 assit_buffer_offset; - u32 inter_bits_info_ddr_start_addr; - u32 inter_mv_info_ddr_start_addr; - u32 intra_bits_info_ddr_start_addr; - u32 intra_pred_info_ddr_start_addr; - u32 sw_ctl_info_start_addr; u32 scaler_buff_start_addr; -#ifdef USE_VDEC2 - u32 vdec2_start_addr; -#endif u32 dump_info_ddr_start_addr; u32 dump_info_ddr_size; + u32 cbr_info_ddr_start_addr; + u32 cbr_info_ddr_size; + s32 dblk_buf_canvas; s32 ref_buf_canvas; struct BuffInfo_s bufspec; @@ -303,11 +282,13 @@ struct encode_picinfo_s { u32 init_qppicture; }; -struct encode_control_s { - u32 dct_buffer_write_ptr; - u32 dct_flush_start; - bool can_update; - bool finish; +struct encode_cbr_s { + u16 block_w; + u16 block_h; + u16 long_th; + u8 start_tbl_id; + u8 short_shift; + u8 long_mb_num; }; struct encode_wq_s { @@ -325,15 +306,14 @@ struct encode_wq_s { u32 i4_weight; u32 i16_weight; - u32 quant_tbl_i4[2][8]; - u32 quant_tbl_i16[2][8]; - u32 quant_tbl_me[2][8]; - u32 qp_table_id; + u32 quant_tbl_i4[8]; + u32 quant_tbl_i16[8]; + u32 quant_tbl_me[8]; struct encode_meminfo_s mem; struct encode_picinfo_s pic; - struct encode_control_s control; struct encode_request_s request; + struct encode_cbr_s cbr_info; atomic_t request_ready; wait_queue_head_t request_complete; }; @@ -360,7 +340,6 @@ struct encode_manager_s { struct ge2d_context_s *context; #endif bool irq_requested; - bool dblk_fix_flag; bool need_reset; bool process_irq; bool inited; /* power on encode */ @@ -387,185 +366,20 @@ extern s32 encode_wq_add_request(struct encode_wq_s *wq); extern struct encode_wq_s *create_encode_work_queue(void); extern s32 destroy_encode_work_queue(struct encode_wq_s *encode_work_queue); -/* Memory Address */ -/* ///////////////////////////////////////////////////////////////////////// */ -#define MicrocodeStart 0x0000 -#define MicrocodeEnd 0x3fff /* 4kx32bits */ -#define HencTopStart 0x4000 -#define HencTopEnd 0x4fff /* 128*32 = 0x1000 */ -#define PredTopStart 0x5000 -#define PredTopEnd 0x5fff /* 128x32 = 0x1000 */ -#define MBBOT_START_0 0x6000 -#define MBBOT_START_1 0x8000 - -/* 256 Lmem can hold MB_PER_DMA TOP Info */ - -#define MB_PER_DMA (256*16/64) -#define MB_PER_DMA_COUNT_I (MB_PER_DMA*(64/16)) -/* 256 Lmem can hold MB_PER_DMA TOP Info */ -#define MB_PER_DMA_P (256*16/160) -#define MB_PER_DMA_COUNT_P (MB_PER_DMA_P*(160/16)) - -/******************************************** - * Interrupt -********************************************/ -#define VB_FULL_REQ 0x01 -#define MAIN_REQ 0x02 -#define VLC_REQ 0x04 -#define QDCT_REQ 0x08 -#define LDMA_REQ 0x10 - -/******************************************** - * Regsiter -********************************************/ -#define COMMON_REG_0 r0 -#define COMMON_REG_1 r1 - -#define VB_FULL_REG_0 r2 - -#define PROCESS_VLC_REG r3 -#define PROCESS_QDCT_REG r4 - -#define MAIN_REG_0 r8 -#define MAIN_REG_1 r9 -#define MAIN_REG_2 r10 -#define MAIN_REG_3 r11 -#define MAIN_REG_4 r12 -#define MAIN_REG_5 r13 -#define MAIN_REG_6 r14 -#define MAIN_REG_7 r15 - -#define VLC_REG_0 r8 -#define VLC_REG_1 r9 -#define VLC_REG_2 r10 -#define VLC_REG_3 r11 -#define VLC_REG_4 r12 -#define VLC_REG_5 r13 -#define VLC_REG_6 r14 -#define VLC_REG_7 r15 -#define VLC_REG_8 r16 -#define VLC_REG_9 r17 -#define VLC_REG_10 r18 -#define VLC_REG_11 r19 -#define VLC_REG_12 r20 - -#define QDCT_REG_0 r8 -#define QDCT_REG_1 r9 -#define QDCT_REG_2 r10 -#define QDCT_REG_3 r11 -#define QDCT_REG_4 r12 -#define QDCT_REG_5 r13 -#define QDCT_REG_6 r14 -#define QDCT_REG_7 r15 - -#ifdef USE_SW_IF -#else -#define MB_QUANT_CHANGED r21 -#endif -#define LAST_MB_MV_BITS r22 -#define LAST_MB_COEFF_BITS r23 - -#define TOP_INFO_0 r24 -#define TOP_INFO_1 r25 -#define TOP_INFO_1_NEXT r26 -#define TOP_MV_0 r27 -#define TOP_MV_1 r28 -#define TOP_MV_2 r29 -#define TOP_MV_3 r30 - -#define vr00 r8 -#define vr01 r9 -#define vr02 r10 -#define vr03 r11 - -#define MEM_OFFSET r31 - - -#ifdef INTRA_IN_P_TOP -#define TOP_Y_DDR_SWAP_LEFT_REG r32 -#define CURRENT_SLICE_QUANT r33 -#define TOP_C_DDR_SWAP_LEFT_REG r34 - -#define CURRENT_INTRA_REG r35 -#define TOP_INFO_0_NEXT r36 -#define TOP_INFO_0_READ r37 -#define SW_IF_REG_0 r38 -#define SW_IF_REG_1 r39 -/* bit[31:1] top */ -/* bit[0] left */ -#define INTRA_STATUS_REG r40 -/* bit[1] next_top */ -/* bit[0] next_left */ -#define NEXT_INTRA_STATUS_REG r41 - -#define PRED_U r42 -#define PRED_UR r43 -#define PRED_L r44 - -#define TOP_Y_DDR_ADDR r45 -#ifdef DBLK_FIX -#define T_L_INFO_REG r46 -#else -#define TOP_C_DDR_ADDR r46 -#endif -#define TOP_W_DDR_ADDR r47 -#define NEXT_TOP_CONTROL_REG r48 -#define TOP_MV_0_d1 r49 -#define TOP_MV_0_d2 r50 -#else -#define TOTAL_BITS_REG r32 -#define CURRENT_SLICE_QUANT r33 -#define SUM_BITS_8 r34 -#define I4x4_MODE_HI_REG r35 -#define I4x4_MODE_LO_REG r36 -#define C_PRED_MODE_REG r37 - -#define MV_0_REG r35 -#define MV_1_REG r36 -#define MV_2_REG r37 -#define MV_3_REG r38 -#define MV_4_REG r39 -#define MV_5_REG r40 -#define MV_6_REG r41 -#define MV_7_REG r42 -#define MV_8_REG r43 -#define MV_9_REG r44 -#define MV_A_REG r45 -#define MV_B_REG r46 -#define MV_C_REG r47 -#define MV_D_REG r48 -#define MV_E_REG r49 -#define MV_F_REG r50 -#endif -#define VLC_MB_INFO_REG r51 - - -#define MAIN_LOOP_REG_0 r52 -#define MAIN_LOOP_REG_1 r53 - -#define dbg_r0 r54 -#define dbg_r1 r55 -#define dbg_r2 r56 - /******************************************** * AV Scratch Register Re-Define ********************************************/ #define ENCODER_STATUS HCODEC_HENC_SCRATCH_0 #define MEM_OFFSET_REG HCODEC_HENC_SCRATCH_1 #define DEBUG_REG HCODEC_HENC_SCRATCH_2 -/* #define MB_COUNT HENC_SCRATCH_3 */ -/* #define IDR_INIT_COUNT HENC_SCRATCH_4 */ - #define IDR_PIC_ID HCODEC_HENC_SCRATCH_5 #define FRAME_NUMBER HCODEC_HENC_SCRATCH_6 #define PIC_ORDER_CNT_LSB HCODEC_HENC_SCRATCH_7 - #define LOG2_MAX_PIC_ORDER_CNT_LSB HCODEC_HENC_SCRATCH_8 #define LOG2_MAX_FRAME_NUM HCODEC_HENC_SCRATCH_9 #define ANC0_BUFFER_ID HCODEC_HENC_SCRATCH_A #define QPPICTURE HCODEC_HENC_SCRATCH_B -/* #define START_POSITION HCODEC_HENC_SCRATCH_C */ #define IE_ME_MB_TYPE HCODEC_HENC_SCRATCH_D /* bit 0-4, IE_PIPPELINE_BLOCK @@ -577,56 +391,26 @@ extern s32 destroy_encode_work_queue(struct encode_wq_s *encode_work_queue); #define IE_ME_MODE HCODEC_HENC_SCRATCH_E #define IE_REF_SEL HCODEC_HENC_SCRATCH_F - -/* [21:16] P_INTRA_QUANT */ -/* [15:0] INTRA_MIN_BITS */ -#define P_INTRA_CONFIG HCODEC_HENC_SCRATCH_G - -/* [31:16] TARGET_BITS_PER_MB */ -/* [15:8] MIN_QUANT */ -/* [7:0] MAX_QUANT */ -#define P_MB_QUANT_CONFIG HCODEC_HENC_SCRATCH_I -/* [31:24] INC_4_BITS */ -/* [23:16] INC_3_BITS */ -/* [15:8] INC_2_BITS */ -/* [7:0] INC_1_BITS */ -#define P_MB_QUANT_INC_CFG HCODEC_HENC_SCRATCH_J -/* [31:24] DEC_4_BITS */ -/* [23:16] DEC_3_BITS */ -/* [15:8] DEC_2_BITS */ -/* [7:0] DEC_1_BITS */ -#define P_MB_QUANT_DEC_CFG HCODEC_HENC_SCRATCH_K - /* [31:0] NUM_ROWS_PER_SLICE_P */ /* [15:0] NUM_ROWS_PER_SLICE_I */ #define FIXED_SLICE_CFG HCODEC_HENC_SCRATCH_L -/* Each MB have 32 bits : */ -/* 12-bits MV_BITS, 4-bits MB_TYPE, and 16-bits COEFF_BITS */ -#define BITS_INFO_DDR_START HCODEC_HENC_SCRATCH_M -/* Each MV has 16 x 32 bits */ -#define MV_INFO_DDR_START HCODEC_HENC_SCRATCH_N -/* Each I4x4 has 64 bits */ -/* shared will not dump I4x4 and MV at same time */ -#define I4x4_INFO_DDR_START MV_INFO_DDR_START - -/* can be shared by BITS_INFO_DDR_START */ -/* bit[7] - 0-same slice, 1-new slice */ -/* bit[6] - 0-inter, 1-intra */ -/* bit[5:0] - quant */ -#define SW_CTL_INFO_DDR_START BITS_INFO_DDR_START - -#define CURRENT_Y_CANVAS_START HCODEC_HENC_SCRATCH_3 -#define CURRENT_C_CANVAS_START HCODEC_HENC_SCRATCH_4 -/* For Block Mode 1 - 32x32 */ -/* If CAVAS width = 1920, then row_size = 1920/32 * 32 * 32 = 61440 (0xf000) */ -#define CANVAS_ROW_SIZE HCODEC_HENC_SCRATCH_C - /* For GX */ #define INFO_DUMP_START_ADDR HCODEC_HENC_SCRATCH_I -#define LOW_LATENCY_EN_REG DOS_SCRATCH9 -#define PREVIOUS_FNUM_REG DOS_SCRATCH10 +/* For CBR */ +#define H264_ENC_CBR_TABLE_ADDR HCODEC_HENC_SCRATCH_3 +#define H264_ENC_CBR_MB_SIZE_ADDR HCODEC_HENC_SCRATCH_4 +/* Bytes(Float) * 256 */ +#define H264_ENC_CBR_CTL HCODEC_HENC_SCRATCH_G +/* [31:28] : init qp table idx */ +/* [27:24] : short_term adjust shift */ +/* [23:16] : Long_term MB_Number between adjust, */ +/* [15:0] Long_term adjust threshold(Bytes) */ +#define H264_ENC_CBR_TARGET_SIZE HCODEC_HENC_SCRATCH_H +/* Bytes(Float) * 256 */ +#define H264_ENC_CBR_PREV_BYTES HCODEC_HENC_SCRATCH_J +#define H264_ENC_CBR_REGION_SIZE HCODEC_HENC_SCRATCH_J /* --------------------------------------------------- */ /* ENCODER_STATUS define */ @@ -651,161 +435,6 @@ extern s32 destroy_encode_work_queue(struct encode_wq_s *encode_work_queue); #define ENCODER_ERROR 0xff -/* --------------------------------------------------- */ -/* NAL start code define */ -/* --------------------------------------------------- */ -/* defines for H.264 */ -#define Coded_slice_of_a_non_IDR_picture 1 -#define Coded_slice_of_an_IDR_picture 5 -#define Supplemental_enhancement_information 6 -#define Sequence_parameter_set 7 -#define Picture_parameter_set 8 - -/* defines for H.264 slice_type */ -#define I_Slice 2 -#define P_Slice 5 -#define B_Slice 6 - -#define P_Slice_0 0 -#define B_Slice_1 1 -#define I_Slice_7 7 - -#define nal_reference_idc_idr 3 -#define nal_reference_idc_non_idr 2 - -#define SEQUENCE_NAL ((nal_reference_idc_idr<<5) | Sequence_parameter_set) -#define PICTURE_NAL ((nal_reference_idc_idr<<5) | Picture_parameter_set) -#define IDR_NAL ((nal_reference_idc_idr<<5) | \ - Coded_slice_of_an_IDR_picture) -#define NON_IDR_NAL ((nal_reference_idc_non_idr<<5) | \ - Coded_slice_of_a_non_IDR_picture) - -/* --------------------------------------------------- */ -/* I_IN_P TOP Status */ -/* --------------------------------------------------- */ -#define I_IN_P_TOP_STATUS_IDLE 0 -#define I_IN_P_TOP_STATUS_READ_Y 1 -#define I_IN_P_TOP_STATUS_READ_C 2 -#define I_IN_P_TOP_STATUS_WRITE 3 -/******************************************** - * Local Memory -********************************************/ -/* #define INTR_MSK_SAVE 0x000 */ -/* #define QPPicture 0x001 */ -/* #define i_pred_mbx 0x002 */ -/* #define i_pred_mby 0x003 */ -/* #define log2_max_pic_order_cnt_lsb 0x004 */ -/* #define log2_max_frame_num 0x005 */ -/* #define frame_num 0x006 */ -/* #define idr_pic_id 0x007 */ -/* #define pic_order_cnt_lsb 0x008 */ -/* #define picture_type 0x009 */ -/* #define top_mb_begin 0x00a */ -/* #define top_mb_end 0x00b */ -/* #define pic_width_in_mbs_minus1 0x00c */ -/* #define pic_height_in_map_units_minus1 0x00d */ -/* #define anc0_buffer_id 0x00e */ - -/* #define enc_header_ready 0x00f */ - - -/* #define cur_mv_bits 0x010 */ -/* #define cur_coeff_bits 0x011 */ -/* #define slice_mb_num 0x012 */ -/* #define current_slice_quant 0x013 */ - -/* #define insert_slice_header 0x014 */ - -/* #define Quant_change_bits 0x015 */ - -/* #define prev_mb_quant 0x016 */ -/* #define current_mb_quant 0x017 */ -/* #define next_mb_quant 0x018 */ -/* #define delta_qp_data 0x019 */ -/* #define qp_change_mbx 0x01a */ - -/* #define process_vlc_mbx 0x01b */ -/* #define process_vlc_mby 0x01c */ -/* #define big_delta_qp 0x01d */ - -/* #define current_mb_type 0x01e */ -/* #define next_mb_type 0x01f */ - -/* #define T_BITS_0 0x020 */ -/* #define T_BITS_1 0x021 */ -/* #define T_BITS_2 0x022 */ -/* #define T_BITS_3 0x023 */ -/* #define T_BITS_4 0x024 */ -/* #define T_BITS_5 0x025 */ -/* #define T_BITS_6 0x026 */ - -/* #define just_changed_status 0x027 */ -/* #define mb_type 0x028 */ -/* #define top_store_intra 0x029 */ -/* #define MB_SKIP_RUN_I_IN_P 0x02a */ -/* #define I_IN_P_TOP_STATUS 0x02b */ -/* #define WAIT_I_IN_P_TOP_STATUS 0x02c */ -/* #define top_pre_load_times 0x02d */ - -/* #define MB_INC_1_BITS 0x030 */ -/* #define MB_INC_2_BITS 0x031 */ -/* #define MB_INC_3_BITS 0x032 */ -/* #define MB_INC_4_BITS 0x033 */ -/* #define MB_DEC_1_BITS 0x034 */ -/* #define MB_DEC_2_BITS 0x035 */ -/* #define MB_DEC_3_BITS 0x036 */ -/* #define MB_DEC_4_BITS 0x037 */ -/* #define MB_MIN_QUANT 0x038 */ -/* #define MB_MAX_QUANT 0x039 */ - -/* #define ie_me_mode 0x040 */ - -/* there are 32 bits BITS_INFO Per MB */ -/* 12-bits MV_BITS, 4-bits MB_TYPE, and 16-bits COEFF_BITS */ -/* #define BITS_INFO_START 0x100 */ - -/* #ifdef HDEC_BLK_MODE_LINEAR */ -/* #define INTRA_LEFT_START 0x200 */ -/* #define INTRA_LEFT_YC_START 0x280 */ -/* #define INTRA_TOP_START 0x200 */ -/* #define INTRA_TOP_Y_START 0x220 */ -/* #define INTRA_TOP_C_START 0x240 */ -/* #else */ -/* #define INTRA_LEFT_C_START 0x180 */ -/* #define INTRA_LEFT_START 0x200 */ -/* #define INTRA_LEFT_Y_START 0x200 */ -/* #endif */ - - -/* #define SW_CTL_INFO_START BITS_INFO_START */ - -/* there are 64 bits I4x4_INFO per MB */ -/* #define I4x4_INFO_START 0x200 */ - -/* there are 16x32 bits MV_INFO per MB */ -/* #define MV_INFO_START 0x200 */ - -/* #define HENC_TOP_LMEM_BEGIN 0x300 */ - -/******************************************** -* defines for HENC command -********************************************/ -#define HENC_SEND_MB_TYPE_COMMAND 1 -#define HENC_SEND_I_PRED_MODE_COMMAND 2 -#define HENC_SEND_C_I_PRED_MODE_COMMAND 3 -#define HENC_SEND_CBP_COMMAND 4 -#define HENC_SEND_DELTA_QP_COMMAND 5 -#define HENC_SEND_COEFF_COMMAND 6 -#define HENC_SEND_SKIP_COMMAND 7 -#define HENC_SEND_B8_MODE_COMMAND 8 -#define HENC_SEND_MVD_COMMAND 9 -#define HENC_SEND_MB_DONE_COMMAND 15 - -/* defines for picture type*/ -#define HENC_I_PICTURE 0 -#define HENC_P_PICTURE 1 -#define HENC_B_PICTURE 2 - /******************************************** * defines for H.264 mb_type ********************************************/ @@ -832,60 +461,5 @@ extern s32 destroy_encode_work_queue(struct encode_wq_s *encode_work_queue); #define HENC_SKIP_RUN_AUTO 0xffff -/* ///////////////////////////////////////////////////////////////////////// */ -/* TOP/LEFT INFO Define */ -/* ///////////////////////////////////////////////////////////////////////// */ - -/* For I Slice */ -#define DEFAULT_INTRA_TYPE 0xffff -#define DEFAULT_CBP_BLK 0x0000 -#define DEFAULT_C_NNZ 0x0000 -#define DEFAULT_Y_NNZ 0x0000 - -#define DEFAULT_MVX 0x8000 -#define DEFAULT_MVY 0x4000 - -/* For I Slice */ -/* Bit[31:20] Reserved */ -/* Bit[19:16] cbp */ -/* Bit[15:0] IntraType */ -/* `define HENC_TOP_INFO_0 8'h37 */ -/* `define HENC_LEFT_INFO_0 8'h38 */ - -/* For I Slice and Intra/Inter Mixed Slice */ -/* Bit[31:24] V_nnz */ -/* Bit[23:16] U_nnz */ -/* Bit[15:0] Y_nnz */ -/* `define HENC_TOP_INFO_1 8'h39 */ -/* `define HENC_LEFT_INFO_1 8'h3a */ - -/* For Intra/Inter Mixed Slice */ -/* */ -/* bit[31] - cbp[3] */ -/* bit[30:16] - MVY ( 0x3fff Means Intra MB) */ -/* bit[15:0] - MVX ( IntraType for Intra MB) */ -/* `define HENC_TOP_MV_0 */ -/* bit[31] - cbp[2] */ -/* bit[30:16] - MVY */ -/* bit[15:0] - MVX */ -/* `define HENC_TOP_MV_1 */ -/* bit[31] - cbp[1] */ -/* bit[30:16] - MVY */ -/* bit[15:0] - MVX */ -/* `define HENC_TOP_MV_2 */ -/* bit[31] - cbp[0] */ -/* bit[30:16] - MVY */ -/* bit[15:0] - MVX */ -/* `define HENC_TOP_MV_3 */ - -/* `define HENC_LEFT_MV_0 */ -/* `define HENC_LEFT_MV_1 */ -/* `define HENC_LEFT_MV_2 */ -/* `define HENC_LEFT_MV_3 */ - -/* ///////////////////////////////////////////////////////////////////////// */ -/* */ -/* ///////////////////////////////////////////////////////////////////////// */ - extern bool amvenc_avc_on(void); #endif |