v4l: fixed some issues for v4l codec. [1/1]

PD#SWPL-5313

Problem:
Decoder V4L2 interface Phase3(AFBC&MMU Support)

Solution:
1. add the limit of vdec input frames.
2. add config parms canvas_mode and endian.

Verify:
U212

Change-Id: Ib3365cd1a09fac7c029bba64c70a3ed40bbd8e3f
Signed-off-by: Nanxin Qin <nanxin.qin@amlogic.com>

12 files changed, 101 insertions, 59 deletions

diff --git a/drivers/amvdec_ports/aml_vcodec_adapt.c b/drivers/amvdec_ports/aml_vcodec_adapt.c
index 367da7a..f7293f6 100644
--- a/drivers/amvdec_ports/aml_vcodec_adapt.c
+++ b/drivers/amvdec_ports/aml_vcodec_adapt.c
@@ -665,14 +665,11 @@ int vdec_vbuf_write(struct aml_vdec_adapt *ada_ctx,
 	return ret;
 }
 
-int is_need_to_buf(struct aml_vdec_adapt *ada_ctx)
+bool vdec_input_full(struct aml_vdec_adapt *ada_ctx)
 {
 	struct vdec_s *vdec = ada_ctx->vdec;
 
-	if (vdec->input.have_frame_num > 8)
-		return 0;
-	else
-		return 1;
+	return (vdec->input.have_frame_num > 60) ? true : false;
 }
 
 int vdec_vframe_write(struct aml_vdec_adapt *ada_ctx,
diff --git a/drivers/amvdec_ports/aml_vcodec_adapt.h b/drivers/amvdec_ports/aml_vcodec_adapt.h
index dad2fe4..1f8afdd 100644
--- a/drivers/amvdec_ports/aml_vcodec_adapt.h
+++ b/drivers/amvdec_ports/aml_vcodec_adapt.h
@@ -54,7 +54,7 @@ int vdec_vbuf_write(struct aml_vdec_adapt *ada_ctx,
 int vdec_vframe_write(struct aml_vdec_adapt *ada_ctx,
 	const char *buf, unsigned int count, u64 timestamp);
 
-int is_need_to_buf(struct aml_vdec_adapt *ada_ctx);
+bool vdec_input_full(struct aml_vdec_adapt *ada_ctx);
 
 void aml_decoder_flush(struct aml_vdec_adapt *ada_ctx);
 
diff --git a/drivers/amvdec_ports/aml_vcodec_dec.c b/drivers/amvdec_ports/aml_vcodec_dec.c
index e516c4b..d8671ab 100644
--- a/drivers/amvdec_ports/aml_vcodec_dec.c
+++ b/drivers/amvdec_ports/aml_vcodec_dec.c
@@ -971,7 +971,7 @@ static int vidioc_decoder_cmd(struct file *file, void *priv,
 				aml_vdec_dispatch_event(ctx, V4L2_EVENT_REQUEST_EXIT);
 				aml_v4l2_debug(1, "[%d] %s() vcodec state (AML_STATE_ABORT)",
 					ctx->id, __func__);
-				return -1;
+				return 0;
 			}
 		}
 
@@ -1496,22 +1496,18 @@ static int vidioc_enum_fmt(struct v4l2_fmtdesc *f, bool output_queue)
 	for (i = 0; i < NUM_FORMATS; i++) {
 		if (output_queue && (aml_video_formats[i].type != AML_FMT_DEC))
 			continue;
-		if (!output_queue &&
-			(aml_video_formats[i].type != AML_FMT_FRAME))
+		if (!output_queue && (aml_video_formats[i].type != AML_FMT_FRAME))
 			continue;
 
-		if (j == f->index)
-			break;
+		if (j == f->index) {
+			fmt = &aml_video_formats[i];
+			f->pixelformat = fmt->fourcc;
+			return 0;
+		}
 		++j;
 	}
 
-	if (i == NUM_FORMATS)
-		return -EINVAL;
-
-	fmt = &aml_video_formats[i];
-	f->pixelformat = fmt->fourcc;
-
-	return 0;
+	return -EINVAL;
 }
 
 static int vidioc_vdec_enum_fmt_vid_cap_mplane(struct file *file, void *pirv,
diff --git a/drivers/amvdec_ports/aml_vcodec_drv.h b/drivers/amvdec_ports/aml_vcodec_drv.h
index 23cf08d..eff017f 100644
--- a/drivers/amvdec_ports/aml_vcodec_drv.h
+++ b/drivers/amvdec_ports/aml_vcodec_drv.h
@@ -265,7 +265,8 @@ struct aml_vdec_cfg_infos {
 	u32 init_width;
 	u32 init_height;
 	u32 ref_buf_margin;
-	u32 block_mode;
+	u32 canvas_mem_mode;
+	u32 canvas_mem_endian;
 };
 
 struct aml_vdec_hdr_infos {
diff --git a/drivers/amvdec_ports/decoder/aml_h264_parser.c b/drivers/amvdec_ports/decoder/aml_h264_parser.c
index 8963afd..602633b 100644
--- a/drivers/amvdec_ports/decoder/aml_h264_parser.c
+++ b/drivers/amvdec_ports/decoder/aml_h264_parser.c
@@ -624,6 +624,7 @@ static int decode_extradata_ps(u8 *data, int size, struct h264_param_sets *ps)
 		goto out;
 
 	if (get_bits1(&gb) != 0) {
+		ret = -1;
 		pr_err("invalid h264 data,return!\n");
 		goto out;
 	}
@@ -674,6 +675,10 @@ int h264_decode_extradata_ps(u8 *buf, int size, struct h264_param_sets *ps)
 				pr_err("parse extra data failed. err: %d\n", ret);
 				return ret;
 			}
+
+			if (ps->sps_parsed)
+				break;
+
 			p += j;
 		}
 		p++;
diff --git a/drivers/amvdec_ports/decoder/aml_hevc_parser.c b/drivers/amvdec_ports/decoder/aml_hevc_parser.c
index 33d44f1..03b8356 100644
--- a/drivers/amvdec_ports/decoder/aml_hevc_parser.c
+++ b/drivers/amvdec_ports/decoder/aml_hevc_parser.c
@@ -1204,6 +1204,7 @@ static int decode_extradata_ps(u8 *data, int size, struct h265_param_sets *ps)
 		goto out;
 
 	if (get_bits1(&gb) != 0) {
+		ret = -1;
 		pr_err("invalid data, return!\n");
 		goto out;
 	}
@@ -1211,8 +1212,10 @@ static int decode_extradata_ps(u8 *data, int size, struct h265_param_sets *ps)
 	nal_type	= get_bits(&gb, 6);
 	nuh_layer_id	= get_bits(&gb, 6);
 	temporal_id	= get_bits(&gb, 3) - 1;
-	if (temporal_id < 0)
+	if (temporal_id < 0) {
+		ret = -1;
 		goto out;
+	}
 
 	/*pr_info("nal_unit_type: %d(%s), nuh_layer_id: %d, temporal_id: %d\n",
 		nal_type, hevc_nal_unit_name(nal_type),
@@ -1246,7 +1249,7 @@ static int decode_extradata_ps(u8 *data, int size, struct h265_param_sets *ps)
 out:
 	vfree(rbsp_buf);
 
-	return 0;
+	return ret;
 }
 
 int h265_decode_extradata_ps(u8 *buf, int size, struct h265_param_sets *ps)
@@ -1264,6 +1267,10 @@ int h265_decode_extradata_ps(u8 *buf, int size, struct h265_param_sets *ps)
 				pr_err("parse extra data failed. err: %d\n", ret);
 				return ret;
 			}
+
+			if (ps->sps_parsed)
+				break;
+
 			p += j;
 		}
 		p++;
diff --git a/drivers/amvdec_ports/decoder/vdec_h264_if.c b/drivers/amvdec_ports/decoder/vdec_h264_if.c
index ea1d0f8..3f2f2a2 100644
--- a/drivers/amvdec_ports/decoder/vdec_h264_if.c
+++ b/drivers/amvdec_ports/decoder/vdec_h264_if.c
@@ -253,6 +253,8 @@ static u32 vdec_config_default_parms(u8 *parm)
 	pbuf += sprintf(pbuf, "parm_v4l_codec_enable:1;");
 	pbuf += sprintf(pbuf, "mh264_double_write_mode:16;");
 	pbuf += sprintf(pbuf, "parm_v4l_buffer_margin:7;");
+	pbuf += sprintf(pbuf, "parm_v4l_canvas_mem_mode:0;");
+	pbuf += sprintf(pbuf, "parm_v4l_canvas_mem_endian:0;");
 
 	return parm - pbuf;
 }
@@ -270,6 +272,10 @@ static void vdec_parser_parms(struct vdec_h264_inst *inst)
 			ctx->config.parm.dec.cfg.double_write_mode);
 		pbuf += sprintf(pbuf, "parm_v4l_buffer_margin:%d;",
 			ctx->config.parm.dec.cfg.ref_buf_margin);
+		pbuf += sprintf(pbuf, "parm_v4l_canvas_mem_mode:%d;",
+			ctx->config.parm.dec.cfg.canvas_mem_mode);
+		pbuf += sprintf(pbuf, "parm_v4l_canvas_mem_endian:%d;",
+			ctx->config.parm.dec.cfg.canvas_mem_endian);
 		ctx->config.length = pbuf - ctx->config.buf;
 	} else {
 		ctx->config.parm.dec.cfg.double_write_mode = 16;
@@ -819,10 +825,12 @@ static int vdec_h264_decode(unsigned long h_vdec, struct aml_vcodec_mem *bs,
 	u32 size;
 	int ret = -1;
 
-	/* bs NULL means flush decoder */
 	if (bs == NULL)
 		return -1;
 
+	if (vdec_input_full(vdec))
+		return -EAGAIN;
+
 	buf = (u8 *)bs->vaddr;
 	size = bs->size;
 	st = (struct stream_info *)buf;
diff --git a/drivers/amvdec_ports/decoder/vdec_hevc_if.c b/drivers/amvdec_ports/decoder/vdec_hevc_if.c
index 1b06d77..bc04176 100644
--- a/drivers/amvdec_ports/decoder/vdec_hevc_if.c
+++ b/drivers/amvdec_ports/decoder/vdec_hevc_if.c
@@ -156,6 +156,8 @@ static u32 vdec_config_default_parms(u8 *parm)
 	pbuf += sprintf(pbuf, "hevc_buf_width:4096;");
 	pbuf += sprintf(pbuf, "hevc_buf_height:2304;");
 	pbuf += sprintf(pbuf, "save_buffer_mode:0;");
+	pbuf += sprintf(pbuf, "parm_v4l_canvas_mem_mode:0;");
+	pbuf += sprintf(pbuf, "parm_v4l_canvas_mem_endian:0;");
 
 	return parm - pbuf;
 }
@@ -176,6 +178,10 @@ static void vdec_parser_parms(struct vdec_hevc_inst *inst)
 		pbuf += sprintf(pbuf, "hevc_buf_width:4096;");
 		pbuf += sprintf(pbuf, "hevc_buf_height:2304;");
 		pbuf += sprintf(pbuf, "save_buffer_mode:0;");
+		pbuf += sprintf(pbuf, "parm_v4l_canvas_mem_mode:%d;",
+			ctx->config.parm.dec.cfg.canvas_mem_mode);
+		pbuf += sprintf(pbuf, "parm_v4l_canvas_mem_endian:%d;",
+			ctx->config.parm.dec.cfg.canvas_mem_endian);
 		ctx->config.length = pbuf - ctx->config.buf;
 	} else {
 		ctx->config.parm.dec.cfg.double_write_mode = 16;
@@ -588,10 +594,12 @@ static int vdec_hevc_decode(unsigned long h_vdec, struct aml_vcodec_mem *bs,
 	u32 size;
 	int ret = -1;
 
-	/* bs NULL means flush decoder */
 	if (bs == NULL)
 		return -1;
 
+	if (vdec_input_full(vdec))
+		return -EAGAIN;
+
 	buf = (u8 *)bs->vaddr;
 	size = bs->size;
 	st = (struct stream_info *)buf;
diff --git a/drivers/amvdec_ports/decoder/vdec_vp9_if.c b/drivers/amvdec_ports/decoder/vdec_vp9_if.c
index 54a6e17..4091500 100644
--- a/drivers/amvdec_ports/decoder/vdec_vp9_if.c
+++ b/drivers/amvdec_ports/decoder/vdec_vp9_if.c
@@ -170,6 +170,8 @@ static u32 vdec_config_default_parms(u8 *parm)
 	pbuf += sprintf(pbuf, "vp9_max_pic_h:2304;");
 	pbuf += sprintf(pbuf, "save_buffer_mode:0;");
 	pbuf += sprintf(pbuf, "no_head:0;");
+	pbuf += sprintf(pbuf, "parm_v4l_canvas_mem_mode:0;");
+	pbuf += sprintf(pbuf, "parm_v4l_canvas_mem_endian:0;");
 
 	return parm - pbuf;
 }
@@ -193,6 +195,10 @@ static void vdec_parser_parms(struct vdec_vp9_inst *inst)
 			ctx->config.parm.dec.cfg.init_height);
 		pbuf += sprintf(pbuf, "save_buffer_mode:0;");
 		pbuf += sprintf(pbuf, "no_head:0;");
+		pbuf += sprintf(pbuf, "parm_v4l_canvas_mem_mode:%d;",
+			ctx->config.parm.dec.cfg.canvas_mem_mode);
+		pbuf += sprintf(pbuf, "parm_v4l_canvas_mem_endian:%d;",
+			ctx->config.parm.dec.cfg.canvas_mem_endian);
 		ctx->config.length = pbuf - ctx->config.buf;
 	} else {
 		ctx->config.parm.dec.cfg.double_write_mode = 16;
@@ -698,10 +704,12 @@ static int vdec_vp9_decode(unsigned long h_vdec, struct aml_vcodec_mem *bs,
 	u32 size;
 	int ret = -1;
 
-	/* bs NULL means flush decoder */
 	if (bs == NULL)
 		return -1;
 
+	if (vdec_input_full(vdec))
+		return -EAGAIN;
+
 	buf = (u8 *)bs->vaddr;
 	size = bs->size;
 	st = (struct stream_info *)buf;
diff --git a/drivers/frame_provider/decoder/h264_multi/vmh264.c b/drivers/frame_provider/decoder/h264_multi/vmh264.c
index ddae0c4..7a3acbd 100644
--- a/drivers/frame_provider/decoder/h264_multi/vmh264.c
+++ b/drivers/frame_provider/decoder/h264_multi/vmh264.c
@@ -1063,7 +1063,7 @@ static void hevc_mcr_config_canv2axitbl(struct vdec_h264_hw_s *hw, int restore)
 	int     num_buff = hw->dpb.mDPB.size;
 	int dw_size = 0;
 	u32 dw_buffer_size_u_v_h;
-	u32 blkmode = mem_map_mode;
+	u32 blkmode = hw->canvas_mode;
 	int dw_mode =  hw->double_write_mode;
 
 	canvas_addr = ANC0_CANVAS_ADDR;
@@ -1117,7 +1117,7 @@ static void hevc_mcr_config_canv2axitbl(struct vdec_h264_hw_s *hw, int restore)
 			canvas_h = hw->frame_height /
 				get_double_write_ratio(hw);
 
-			if (mem_map_mode == 0)
+			if (hw->canvas_mode == 0)
 				canvas_w = ALIGN(canvas_w, 32);
 			else
 				canvas_w = ALIGN(canvas_w, 64);
@@ -1317,7 +1317,7 @@ static void  hevc_mcr_sao_global_hw_init(struct vdec_h264_hw_s *hw,
 #endif
 	data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
 	data32 &= (~0x30);
-	data32 |= (mem_map_mode << 4);
+	data32 |= (hw->canvas_mode << 4);
 	WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
 
 	WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,
@@ -1362,9 +1362,9 @@ static void  hevc_mcr_sao_global_hw_init(struct vdec_h264_hw_s *hw,
 	data32 |= endian;	/* Big-Endian per 64-bit */
 
 	if (hw->mmu_enable && dw_mode)
-		data32 |= ((mem_map_mode << 12));
+		data32 |= ((hw->canvas_mode << 12));
 	else
-		data32 |= ((mem_map_mode << 12)|2);
+		data32 |= ((hw->canvas_mode << 12)|2);
 
 	WRITE_VREG(HEVC_SAO_CTRL1, data32);
 
@@ -1839,7 +1839,7 @@ static int alloc_one_buf_spec_from_queue(struct vdec_h264_hw_s *hw, int idx)
 	y_canvas_cfg->phy_addr	= y_addr;
 	y_canvas_cfg->width	= hw->mb_width << 4;
 	y_canvas_cfg->height	= hw->mb_height << 4;
-	y_canvas_cfg->block_mode = CANVAS_BLKMODE_LINEAR;
+	y_canvas_cfg->block_mode = hw->canvas_mode;
 	//fb->m.mem[0].bytes_used = y_canvas_cfg->width * y_canvas_cfg->height;
 	dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
 		"[%d] %s(), y_w: %d, y_h: %d\n", ctx->id, __func__,
@@ -1848,7 +1848,7 @@ static int alloc_one_buf_spec_from_queue(struct vdec_h264_hw_s *hw, int idx)
 	c_canvas_cfg->phy_addr	= c_addr;
 	c_canvas_cfg->width	= hw->mb_width << 4;
 	c_canvas_cfg->height	= hw->mb_height << 3;
-	c_canvas_cfg->block_mode = CANVAS_BLKMODE_LINEAR;
+	c_canvas_cfg->block_mode = hw->canvas_mode;
 	//fb->m.mem[1].bytes_used = c_canvas_cfg->width * c_canvas_cfg->height;
 	dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
 		"[%d] %s(), c_w: %d, c_h: %d\n", ctx->id, __func__,
@@ -1862,24 +1862,18 @@ static int alloc_one_buf_spec_from_queue(struct vdec_h264_hw_s *hw, int idx)
 
 static void config_decode_canvas(struct vdec_h264_hw_s *hw, int i)
 {
-	struct aml_vcodec_ctx * v4l2_ctx = hw->v4l2_ctx;
-	int blkmode = CANVAS_BLKMODE_32X32;
+	int blkmode = hw->canvas_mode;
 	int endian = 0;
 
-	if (hw->canvas_mode == CANVAS_BLKMODE_LINEAR) {
-		blkmode = CANVAS_BLKMODE_LINEAR;
+	if (blkmode == CANVAS_BLKMODE_LINEAR) {
 		if ((h264_debug_flag & IGNORE_PARAM_FROM_CONFIG) == 0)
 			endian = 7;
 		else
 			endian = 0;
 	}
 
-	if (hw->is_used_v4l) {
-		blkmode = CANVAS_BLKMODE_LINEAR;
-		if (v4l2_ctx->ada_ctx->vfm_path
-			!= FRAME_BASE_PATH_V4L_VIDEO)
+	if (hw->is_used_v4l)
 		endian = 7;
-	}
 
 	canvas_config_ex(hw->buffer_spec[i].
 		y_canvas_index,
@@ -1992,7 +1986,7 @@ static void config_decode_canvas(struct vdec_h264_hw_s *hw, int i)
 
 static void config_decode_canvas_ex(struct vdec_h264_hw_s *hw, int i)
 {
-	u32 blkmode = mem_map_mode;
+	u32 blkmode = hw->canvas_mode;
 	int canvas_w;
 	int canvas_h;
 
@@ -2001,7 +1995,7 @@ static void config_decode_canvas_ex(struct vdec_h264_hw_s *hw, int i)
 	canvas_h = hw->frame_height /
 		get_double_write_ratio(hw);
 
-	if (mem_map_mode == 0)
+	if (hw->canvas_mode == 0)
 		canvas_w = ALIGN(canvas_w, 32);
 	else
 		canvas_w = ALIGN(canvas_w, 64);
@@ -6798,9 +6792,6 @@ static void vh264_local_init(struct vdec_h264_hw_s *hw)
 
 	hw->first_i_policy = first_i_policy;
 
-	if (hw->is_used_v4l)
-		mem_map_mode = CANVAS_BLKMODE_LINEAR;
-
 	pr_info("H264 sysinfo: %dx%d duration=%d, pts_outside=%d\n",
 		hw->frame_width, hw->frame_height, hw->frame_dur, hw->pts_outside);
 	pr_debug("sync_outside=%d, use_idr_framerate=%d, is_used_v4l: %d\n",
@@ -8799,11 +8790,6 @@ static int ammvdec_h264_probe(struct platform_device *pdev)
 	/* the ctx from v4l2 driver. */
 	hw->v4l2_ctx = pdata->private;
 
-	if ((h264_debug_flag & IGNORE_PARAM_FROM_CONFIG) == 0)
-		hw->canvas_mode = pdata->canvas_mode;
-	else
-		hw->canvas_mode = mem_map_mode;
-
 	platform_set_drvdata(pdev, pdata);
 
 	hw->mmu_enable = 0;
@@ -8852,11 +8838,21 @@ static int ammvdec_h264_probe(struct platform_device *pdev)
 			"parm_v4l_buffer_margin",
 			&config_val) == 0)
 			hw->reorder_dpb_size_margin = config_val;
+
+		if (get_config_int(pdata->config,
+			"parm_v4l_canvas_mem_mode",
+			&config_val) == 0)
+			hw->canvas_mode = config_val;
 	} else
 		hw->double_write_mode = double_write_mode;
 
-	if (!hw->is_used_v4l)
+	if (!hw->is_used_v4l) {
 		hw->reorder_dpb_size_margin = reorder_dpb_size_margin;
+		hw->canvas_mode = mem_map_mode;
+
+		if ((h264_debug_flag & IGNORE_PARAM_FROM_CONFIG) == 0)
+			hw->canvas_mode = pdata->canvas_mode;
+	}
 
 	if (hw->mmu_enable)
 			hw->double_write_mode &= 0xffff;
diff --git a/drivers/frame_provider/decoder/h265/vh265.c b/drivers/frame_provider/decoder/h265/vh265.c
index 9189564..0f5ca8b 100644
--- a/drivers/frame_provider/decoder/h265/vh265.c
+++ b/drivers/frame_provider/decoder/h265/vh265.c
@@ -1732,6 +1732,7 @@ struct hevc_state_s {
 	bool is_used_v4l;
 	void *v4l2_ctx;
 	bool v4l_params_parsed;
+	u32 mem_map_mode;
 } /*hevc_stru_t */;
 
 #ifdef AGAIN_HAS_THRESHOLD
@@ -5258,7 +5259,7 @@ static void config_sao_hw(struct hevc_state_s *hevc, union param_u *params)
 #if 0
 	data32 = READ_VREG(HEVC_SAO_CTRL1);
 	data32 &= (~0x3000);
-	data32 |= (mem_map_mode <<
+	data32 |= (hevc->mem_map_mode <<
 			12);
 
 /*  [13:12] axi_aformat,
@@ -5268,7 +5269,7 @@ static void config_sao_hw(struct hevc_state_s *hevc, union param_u *params)
 
 	data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
 	data32 &= (~0x30);
-	data32 |= (mem_map_mode <<
+	data32 |= (hevc->mem_map_mode <<
 			   4);
 
 /*  [5:4]    -- address_format
@@ -5279,7 +5280,7 @@ static void config_sao_hw(struct hevc_state_s *hevc, union param_u *params)
 	/* m8baby test1902 */
 	data32 = READ_VREG(HEVC_SAO_CTRL1);
 	data32 &= (~0x3000);
-	data32 |= (mem_map_mode <<
+	data32 |= (hevc->mem_map_mode <<
 			   12);
 
 /*  [13:12] axi_aformat, 0-Linear,
@@ -5350,7 +5351,7 @@ static void config_sao_hw(struct hevc_state_s *hevc, union param_u *params)
 	data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
 	data32 &= (~0x30);
 	/* [5:4]    -- address_format 00:linear 01:32x32 10:64x32 */
-	data32 |= (mem_map_mode <<
+	data32 |= (hevc->mem_map_mode <<
 			   4);
 	data32 &= (~0xF);
 	data32 |= 0xf;  /* valid only when double write only */
@@ -7470,7 +7471,7 @@ static void set_canvas(struct hevc_state_s *hevc, struct PIC_s *pic)
 	struct vdec_s *vdec = hw_to_vdec(hevc);
 	int canvas_w = ALIGN(pic->width, 64)/4;
 	int canvas_h = ALIGN(pic->height, 32)/4;
-	int blkmode = mem_map_mode;
+	int blkmode = hevc->mem_map_mode;
 
 	/*CANVAS_BLKMODE_64X32*/
 #ifdef SUPPORT_10BIT
@@ -7480,7 +7481,7 @@ static void set_canvas(struct hevc_state_s *hevc, struct PIC_s *pic)
 		canvas_h = pic->height /
 			get_double_write_ratio(hevc, pic->double_write_mode);
 
-		if (mem_map_mode == 0)
+		if (hevc->mem_map_mode == 0)
 			canvas_w = ALIGN(canvas_w, 32);
 		else
 			canvas_w = ALIGN(canvas_w, 64);
@@ -12879,6 +12880,11 @@ static int ammvdec_h265_probe(struct platform_device *pdev)
 			"parm_v4l_buffer_margin",
 			&config_val) == 0)
 			hevc->dynamic_buf_num_margin = config_val;
+
+		if (get_config_int(pdata->config,
+			"parm_v4l_canvas_mem_mode",
+			&config_val) == 0)
+			hevc->mem_map_mode = config_val;
 #endif
 	} else {
 		if (pdata->sys_info)
@@ -12895,6 +12901,8 @@ static int ammvdec_h265_probe(struct platform_device *pdev)
 			hevc->dynamic_buf_num_margin = dynamic_buf_num_margin -2;
 		else
 			hevc->dynamic_buf_num_margin = dynamic_buf_num_margin;
+
+		hevc->mem_map_mode = mem_map_mode;
 	}
 
 	if (mmu_enable_force == 0) {
diff --git a/drivers/frame_provider/decoder/vp9/vvp9.c b/drivers/frame_provider/decoder/vp9/vvp9.c
index 3cafea2..79e71d0 100644
--- a/drivers/frame_provider/decoder/vp9/vvp9.c
+++ b/drivers/frame_provider/decoder/vp9/vvp9.c
@@ -6520,8 +6520,6 @@ static int vp9_local_init(struct VP9Decoder_s *pbi)
 		pbi->vvp9_amstream_dec_info.height :
 		pbi->work_space_buf->max_height));
 
-	pbi->mem_map_mode = mem_map_mode ? mem_map_mode : 0;
-
 	/* video is not support unaligned with 64 in tl1
 	** vdec canvas mode will be linear when dump yuv is set
 	*/
@@ -10439,6 +10437,11 @@ static int ammvdec_vp9_probe(struct platform_device *pdev)
 			"parm_v4l_buffer_margin",
 			&config_val) == 0)
 			pbi->dynamic_buf_num_margin = config_val;
+
+		if (get_config_int(pdata->config,
+			"parm_v4l_canvas_mem_mode",
+			&config_val) == 0)
+			pbi->mem_map_mode = config_val;
 #endif
 		if (get_config_int(pdata->config, "HDRStaticInfo",
 				&vf_dp.present_flag) == 0
@@ -10486,6 +10489,11 @@ static int ammvdec_vp9_probe(struct platform_device *pdev)
 		pbi->vvp9_amstream_dec_info.rate = 30;*/
 		pbi->double_write_mode = double_write_mode;
 	}
+
+	if (!pbi->is_used_v4l) {
+		pbi->mem_map_mode = mem_map_mode;
+	}
+
 	if (is_oversize(pbi->max_pic_w, pbi->max_pic_h)) {
 		pr_err("over size: %dx%d, probe failed\n",
 			pbi->max_pic_w, pbi->max_pic_h);