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1/*
2* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
3*
4* This program is free software; you can redistribute it and/or modify
5* it under the terms of the GNU General Public License as published by
6* the Free Software Foundation; either version 2 of the License, or
7* (at your option) any later version.
8*
9* This program is distributed in the hope that it will be useful, but WITHOUT
10* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12* more details.
13*
14* You should have received a copy of the GNU General Public License along
15* with this program; if not, write to the Free Software Foundation, Inc.,
16* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17*
18* Description:
19*/
20#ifndef _AML_VCODEC_DRV_H_
21#define _AML_VCODEC_DRV_H_
22
23#include <linux/platform_device.h>
24#include <linux/videodev2.h>
25#include <media/v4l2-ctrls.h>
26#include <media/v4l2-device.h>
27#include <media/v4l2-ioctl.h>
28#include <media/videobuf2-core.h>
29#include "aml_vcodec_util.h"
30
31#define AML_VCODEC_DRV_NAME "aml_vcodec_drv"
32#define AML_VCODEC_DEC_NAME "aml-vcodec-dec"
33#define AML_VCODEC_ENC_NAME "aml-vcodec-enc"
34#define AML_PLATFORM_STR "platform:amlogic"
35
36#define AML_VCODEC_MAX_PLANES 3
37#define AML_V4L2_BENCHMARK 0
38#define WAIT_INTR_TIMEOUT_MS 1000
39
40/**
41 * enum aml_hw_reg_idx - AML hw register base index
42 */
43enum aml_hw_reg_idx {
44 VDEC_SYS,
45 VDEC_MISC,
46 VDEC_LD,
47 VDEC_TOP,
48 VDEC_CM,
49 VDEC_AD,
50 VDEC_AV,
51 VDEC_PP,
52 VDEC_HWD,
53 VDEC_HWQ,
54 VDEC_HWB,
55 VDEC_HWG,
56 NUM_MAX_VDEC_REG_BASE,
57 /* h264 encoder */
58 VENC_SYS = NUM_MAX_VDEC_REG_BASE,
59 /* vp8 encoder */
60 VENC_LT_SYS,
61 NUM_MAX_VCODEC_REG_BASE
62};
63
64/**
65 * enum aml_instance_type - The type of an AML Vcodec instance.
66 */
67enum aml_instance_type {
68 AML_INST_DECODER = 0,
69 AML_INST_ENCODER = 1,
70};
71
72/**
73 * enum aml_instance_state - The state of an AML Vcodec instance.
74 * @AML_STATE_IDLE - default state when instance is created
75 * @AML_STATE_INIT - vcodec instance is initialized
76 * @AML_STATE_PROBE - vdec/venc had sps/pps header parsed/encoded
77 * @AML_STATE_ACTIVE - vdec is ready for work.
78 * @AML_STATE_FLUSHING - vdec is flushing. Only used by decoder
79 * @AML_STATE_FLUSHED - decoder has transacted the last frame.
80 * @AML_STATE_RESET - decoder has be reset after flush.
81 * @AML_STATE_ABORT - vcodec should be aborted
82 */
83enum aml_instance_state {
84 AML_STATE_IDLE,
85 AML_STATE_INIT,
86 AML_STATE_PROBE,
87 AML_STATE_READY,
88 AML_STATE_ACTIVE,
89 AML_STATE_FLUSHING,
90 AML_STATE_FLUSHED,
91 AML_STATE_RESET,
92 AML_STATE_ABORT,
93};
94
95/**
96 * struct aml_encode_param - General encoding parameters type
97 */
98enum aml_encode_param {
99 AML_ENCODE_PARAM_NONE = 0,
100 AML_ENCODE_PARAM_BITRATE = (1 << 0),
101 AML_ENCODE_PARAM_FRAMERATE = (1 << 1),
102 AML_ENCODE_PARAM_INTRA_PERIOD = (1 << 2),
103 AML_ENCODE_PARAM_FORCE_INTRA = (1 << 3),
104 AML_ENCODE_PARAM_GOP_SIZE = (1 << 4),
105};
106
107enum aml_fmt_type {
108 AML_FMT_DEC = 0,
109 AML_FMT_ENC = 1,
110 AML_FMT_FRAME = 2,
111};
112
113/**
114 * struct aml_video_fmt - Structure used to store information about pixelformats
115 */
116struct aml_video_fmt {
117 u32 fourcc;
118 enum aml_fmt_type type;
119 u32 num_planes;
120};
121
122/**
123 * struct aml_codec_framesizes - Structure used to store information about
124 * framesizes
125 */
126struct aml_codec_framesizes {
127 u32 fourcc;
128 struct v4l2_frmsize_stepwise stepwise;
129};
130
131/**
132 * struct aml_q_type - Type of queue
133 */
134enum aml_q_type {
135 AML_Q_DATA_SRC = 0,
136 AML_Q_DATA_DST = 1,
137};
138
139/**
140 * struct aml_q_data - Structure used to store information about queue
141 */
142struct aml_q_data {
143 unsigned int visible_width;
144 unsigned int visible_height;
145 unsigned int coded_width;
146 unsigned int coded_height;
147 enum v4l2_field field;
148 unsigned int bytesperline[AML_VCODEC_MAX_PLANES];
149 unsigned int sizeimage[AML_VCODEC_MAX_PLANES];
150 struct aml_video_fmt *fmt;
151 bool resolution_changed;
152};
153
154/**
155 * struct aml_enc_params - General encoding parameters
156 * @bitrate: target bitrate in bits per second
157 * @num_b_frame: number of b frames between p-frame
158 * @rc_frame: frame based rate control
159 * @rc_mb: macroblock based rate control
160 * @seq_hdr_mode: H.264 sequence header is encoded separately or joined
161 * with the first frame
162 * @intra_period: I frame period
163 * @gop_size: group of picture size, it's used as the intra frame period
164 * @framerate_num: frame rate numerator. ex: framerate_num=30 and
165 * framerate_denom=1 menas FPS is 30
166 * @framerate_denom: frame rate denominator. ex: framerate_num=30 and
167 * framerate_denom=1 menas FPS is 30
168 * @h264_max_qp: Max value for H.264 quantization parameter
169 * @h264_profile: V4L2 defined H.264 profile
170 * @h264_level: V4L2 defined H.264 level
171 * @force_intra: force/insert intra frame
172 */
173struct aml_enc_params {
174 unsigned int bitrate;
175 unsigned int num_b_frame;
176 unsigned int rc_frame;
177 unsigned int rc_mb;
178 unsigned int seq_hdr_mode;
179 unsigned int intra_period;
180 unsigned int gop_size;
181 unsigned int framerate_num;
182 unsigned int framerate_denom;
183 unsigned int h264_max_qp;
184 unsigned int h264_profile;
185 unsigned int h264_level;
186 unsigned int force_intra;
187};
188
189/**
190 * struct aml_vcodec_pm - Power management data structure
191 */
192struct aml_vcodec_pm {
193 struct clk *vdec_bus_clk_src;
194 struct clk *vencpll;
195
196 struct clk *vcodecpll;
197 struct clk *univpll_d2;
198 struct clk *clk_cci400_sel;
199 struct clk *vdecpll;
200 struct clk *vdec_sel;
201 struct clk *vencpll_d2;
202 struct clk *venc_sel;
203 struct clk *univpll1_d2;
204 struct clk *venc_lt_sel;
205 struct device *larbvdec;
206 struct device *larbvenc;
207 struct device *larbvenclt;
208 struct device *dev;
209 struct aml_vcodec_dev *amldev;
210};
211
212/**
213 * struct vdec_pic_info - picture size information
214 * @visible_width: picture width
215 * @visible_height: picture height
216 * @coded_width: picture buffer width (64 aligned up from pic_w)
217 * @coded_height: picture buffer heiht (64 aligned up from pic_h)
218 * @y_bs_sz: Y bitstream size
219 * @c_bs_sz: CbCr bitstream size
220 * @y_len_sz: additional size required to store decompress information for y
221 * plane
222 * @c_len_sz: additional size required to store decompress information for cbcr
223 * plane
224 * E.g. suppose picture size is 176x144,
225 * buffer size will be aligned to 176x160.
226 */
227struct vdec_pic_info {
228 unsigned int visible_width;
229 unsigned int visible_height;
230 unsigned int coded_width;
231 unsigned int coded_height;
232 unsigned int y_bs_sz;
233 unsigned int c_bs_sz;
234 unsigned int y_len_sz;
235 unsigned int c_len_sz;
236};
237
238enum aml_thread_type {
239 AML_THREAD_OUTPUT,
240 AML_THREAD_CAPTURE,
241};
242
243typedef void (*aml_thread_func)(struct aml_vcodec_ctx *ctx);
244
245struct aml_vdec_thread {
246 struct list_head node;
247 spinlock_t lock;
248 struct semaphore sem;
249 struct task_struct *task;
250 enum aml_thread_type type;
251 void *priv;
252 int stop;
253
254 aml_thread_func func;
255};
256
257/**
258 * struct aml_vcodec_ctx - Context (instance) private data.
259 *
260 * @type: type of the instance - decoder or encoder
261 * @dev: pointer to the aml_vcodec_dev of the device
262 * @list: link to ctx_list of aml_vcodec_dev
263 * @fh: struct v4l2_fh
264 * @m2m_ctx: pointer to the v4l2_m2m_ctx of the context
265 * @q_data: store information of input and output queue
266 * of the context
267 * @id: index of the context that this structure describes
268 * @state: state of the context
269 * @param_change: indicate encode parameter type
270 * @enc_params: encoding parameters
271 * @dec_if: hooked decoder driver interface
272 * @enc_if: hoooked encoder driver interface
273 * @drv_handle: driver handle for specific decode/encode instance
274 *
275 * @picinfo: store picture info after header parsing
276 * @dpb_size: store dpb count after header parsing
277 * @int_cond: variable used by the waitqueue
278 * @int_type: type of the last interrupt
279 * @queue: waitqueue that can be used to wait for this context to
280 * finish
281 * @irq_status: irq status
282 *
283 * @ctrl_hdl: handler for v4l2 framework
284 * @decode_work: worker for the decoding
285 * @encode_work: worker for the encoding
286 * @last_decoded_picinfo: pic information get from latest decode
287 * @empty_flush_buf: a fake size-0 capture buffer that indicates flush
288 *
289 * @colorspace: enum v4l2_colorspace; supplemental to pixelformat
290 * @ycbcr_enc: enum v4l2_ycbcr_encoding, Y'CbCr encoding
291 * @quantization: enum v4l2_quantization, colorspace quantization
292 * @xfer_func: enum v4l2_xfer_func, colorspace transfer function
293 * @lock: protect variables accessed by V4L2 threads and worker thread such as
294 * aml_video_dec_buf.
295 */
296struct aml_vcodec_ctx {
297 enum aml_instance_type type;
298 struct aml_vcodec_dev *dev;
299 struct list_head list;
300
301 struct v4l2_fh fh;
302 struct v4l2_m2m_ctx *m2m_ctx;
303 struct aml_vdec_adapt *ada_ctx;
304 struct aml_q_data q_data[2];
305 int id;
306 struct mutex state_lock;
307 enum aml_instance_state state;
308 enum aml_encode_param param_change;
309 struct aml_enc_params enc_params;
310
311 const struct vdec_common_if *dec_if;
312 const struct venc_common_if *enc_if;
313 unsigned long drv_handle;
314
315 struct vdec_pic_info picinfo;
316 int dpb_size;
317
318 int int_cond;
319 int int_type;
320 wait_queue_head_t queue;
321 unsigned int irq_status;
322
323 struct v4l2_ctrl_handler ctrl_hdl;
324 struct work_struct decode_work;
325 struct work_struct encode_work;
326 struct vdec_pic_info last_decoded_picinfo;
327 struct aml_video_dec_buf *empty_flush_buf;
328
329 enum v4l2_colorspace colorspace;
330 enum v4l2_ycbcr_encoding ycbcr_enc;
331 enum v4l2_quantization quantization;
332 enum v4l2_xfer_func xfer_func;
333
334 int decoded_frame_cnt;
335 struct mutex lock;
336 struct completion comp;
337 bool has_receive_eos;
338 struct list_head capture_list;
339 struct list_head vdec_thread_list;
340 bool is_drm_mode;
341 bool is_stream_mode;
342 int buf_used_count;
343 bool receive_cmd_stop;
344 bool scatter_mem_enable;
345 bool param_sets_from_ucode;
346 bool v4l_codec_ready;
347 wait_queue_head_t wq;
348 spinlock_t slock;
349};
350
351/**
352 * struct aml_vcodec_dev - driver data
353 * @v4l2_dev: V4L2 device to register video devices for.
354 * @vfd_dec: Video device for decoder
355 * @vfd_enc: Video device for encoder.
356 *
357 * @m2m_dev_dec: m2m device for decoder
358 * @m2m_dev_enc: m2m device for encoder.
359 * @plat_dev: platform device
360 * @vpu_plat_dev: aml vpu platform device
361 * @alloc_ctx: VB2 allocator context
362 * (for allocations without kernel mapping).
363 * @ctx_list: list of struct aml_vcodec_ctx
364 * @irqlock: protect data access by irq handler and work thread
365 * @curr_ctx: The context that is waiting for codec hardware
366 *
367 * @reg_base: Mapped address of AML Vcodec registers.
368 *
369 * @id_counter: used to identify current opened instance
370 *
371 * @encode_workqueue: encode work queue
372 *
373 * @int_cond: used to identify interrupt condition happen
374 * @int_type: used to identify what kind of interrupt condition happen
375 * @dev_mutex: video_device lock
376 * @queue: waitqueue for waiting for completion of device commands
377 *
378 * @dec_irq: decoder irq resource
379 * @enc_irq: h264 encoder irq resource
380 * @enc_lt_irq: vp8 encoder irq resource
381 *
382 * @dec_mutex: decoder hardware lock
383 * @enc_mutex: encoder hardware lock.
384 *
385 * @pm: power management control
386 * @dec_capability: used to identify decode capability, ex: 4k
387 * @enc_capability: used to identify encode capability
388 */
389struct aml_vcodec_dev {
390 struct v4l2_device v4l2_dev;
391 struct video_device *vfd_dec;
392 struct video_device *vfd_enc;
393 struct file *filp;
394
395 struct v4l2_m2m_dev *m2m_dev_dec;
396 struct v4l2_m2m_dev *m2m_dev_enc;
397 struct platform_device *plat_dev;
398 struct platform_device *vpu_plat_dev;//??
399 struct vb2_alloc_ctx *alloc_ctx;//??
400 struct list_head ctx_list;
401 spinlock_t irqlock;
402 struct aml_vcodec_ctx *curr_ctx;
403 void __iomem *reg_base[NUM_MAX_VCODEC_REG_BASE];
404
405 unsigned long id_counter;
406
407 struct workqueue_struct *decode_workqueue;
408 struct workqueue_struct *encode_workqueue;
409 int int_cond;
410 int int_type;
411 struct mutex dev_mutex;
412 wait_queue_head_t queue;
413
414 int dec_irq;
415 int enc_irq;
416 int enc_lt_irq;
417
418 struct mutex dec_mutex;
419 struct mutex enc_mutex;
420
421 struct aml_vcodec_pm pm;
422 unsigned int dec_capability;
423 unsigned int enc_capability;
424};
425
426static inline struct aml_vcodec_ctx *fh_to_ctx(struct v4l2_fh *fh)
427{
428 return container_of(fh, struct aml_vcodec_ctx, fh);
429}
430
431static inline struct aml_vcodec_ctx *ctrl_to_ctx(struct v4l2_ctrl *ctrl)
432{
433 return container_of(ctrl->handler, struct aml_vcodec_ctx, ctrl_hdl);
434}
435
436#endif /* _AML_VCODEC_DRV_H_ */
437
generated by cgit at 2024-05-17 11:37:17 (GMT)