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path: root/drivers/amvdec_ports/aml_vcodec_drv.h (plain)
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1/*
2* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
3*
4* This program is free software; you can redistribute it and/or modify
5* it under the terms of the GNU General Public License as published by
6* the Free Software Foundation; either version 2 of the License, or
7* (at your option) any later version.
8*
9* This program is distributed in the hope that it will be useful, but WITHOUT
10* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12* more details.
13*
14* You should have received a copy of the GNU General Public License along
15* with this program; if not, write to the Free Software Foundation, Inc.,
16* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17*
18* Description:
19*/
20#ifndef _AML_VCODEC_DRV_H_
21#define _AML_VCODEC_DRV_H_
22
23#include <linux/platform_device.h>
24#include <linux/videodev2.h>
25#include <media/v4l2-ctrls.h>
26#include <media/v4l2-device.h>
27#include <media/v4l2-ioctl.h>
28#include <media/videobuf2-core.h>
29#include <linux/amlogic/media/vfm/vframe.h>
30#include "aml_vcodec_util.h"
31
32#define AML_VCODEC_DRV_NAME "aml_vcodec_drv"
33#define AML_VCODEC_DEC_NAME "aml-vcodec-dec"
34#define AML_VCODEC_ENC_NAME "aml-vcodec-enc"
35#define AML_PLATFORM_STR "platform:amlogic"
36
37#define AML_VCODEC_MAX_PLANES 3
38#define AML_V4L2_BENCHMARK 0
39#define WAIT_INTR_TIMEOUT_MS 1000
40
41/**
42 * enum aml_hw_reg_idx - AML hw register base index
43 */
44enum aml_hw_reg_idx {
45 VDEC_SYS,
46 VDEC_MISC,
47 VDEC_LD,
48 VDEC_TOP,
49 VDEC_CM,
50 VDEC_AD,
51 VDEC_AV,
52 VDEC_PP,
53 VDEC_HWD,
54 VDEC_HWQ,
55 VDEC_HWB,
56 VDEC_HWG,
57 NUM_MAX_VDEC_REG_BASE,
58 /* h264 encoder */
59 VENC_SYS = NUM_MAX_VDEC_REG_BASE,
60 /* vp8 encoder */
61 VENC_LT_SYS,
62 NUM_MAX_VCODEC_REG_BASE
63};
64
65/**
66 * enum aml_instance_type - The type of an AML Vcodec instance.
67 */
68enum aml_instance_type {
69 AML_INST_DECODER = 0,
70 AML_INST_ENCODER = 1,
71};
72
73/**
74 * enum aml_instance_state - The state of an AML Vcodec instance.
75 * @AML_STATE_IDLE - default state when instance is created
76 * @AML_STATE_INIT - vcodec instance is initialized
77 * @AML_STATE_PROBE - vdec/venc had sps/pps header parsed/encoded
78 * @AML_STATE_ACTIVE - vdec is ready for work.
79 * @AML_STATE_FLUSHING - vdec is flushing. Only used by decoder
80 * @AML_STATE_FLUSHED - decoder has transacted the last frame.
81 * @AML_STATE_RESET - decoder has be reset after flush.
82 * @AML_STATE_ABORT - vcodec should be aborted
83 */
84enum aml_instance_state {
85 AML_STATE_IDLE,
86 AML_STATE_INIT,
87 AML_STATE_PROBE,
88 AML_STATE_READY,
89 AML_STATE_ACTIVE,
90 AML_STATE_FLUSHING,
91 AML_STATE_FLUSHED,
92 AML_STATE_RESET,
93 AML_STATE_ABORT,
94};
95
96/**
97 * struct aml_encode_param - General encoding parameters type
98 */
99enum aml_encode_param {
100 AML_ENCODE_PARAM_NONE = 0,
101 AML_ENCODE_PARAM_BITRATE = (1 << 0),
102 AML_ENCODE_PARAM_FRAMERATE = (1 << 1),
103 AML_ENCODE_PARAM_INTRA_PERIOD = (1 << 2),
104 AML_ENCODE_PARAM_FORCE_INTRA = (1 << 3),
105 AML_ENCODE_PARAM_GOP_SIZE = (1 << 4),
106};
107
108enum aml_fmt_type {
109 AML_FMT_DEC = 0,
110 AML_FMT_ENC = 1,
111 AML_FMT_FRAME = 2,
112};
113
114/**
115 * struct aml_video_fmt - Structure used to store information about pixelformats
116 */
117struct aml_video_fmt {
118 u32 fourcc;
119 enum aml_fmt_type type;
120 u32 num_planes;
121};
122
123/**
124 * struct aml_codec_framesizes - Structure used to store information about
125 * framesizes
126 */
127struct aml_codec_framesizes {
128 u32 fourcc;
129 struct v4l2_frmsize_stepwise stepwise;
130};
131
132/**
133 * struct aml_q_type - Type of queue
134 */
135enum aml_q_type {
136 AML_Q_DATA_SRC = 0,
137 AML_Q_DATA_DST = 1,
138};
139
140/**
141 * struct aml_q_data - Structure used to store information about queue
142 */
143struct aml_q_data {
144 unsigned int visible_width;
145 unsigned int visible_height;
146 unsigned int coded_width;
147 unsigned int coded_height;
148 enum v4l2_field field;
149 unsigned int bytesperline[AML_VCODEC_MAX_PLANES];
150 unsigned int sizeimage[AML_VCODEC_MAX_PLANES];
151 struct aml_video_fmt *fmt;
152 bool resolution_changed;
153};
154
155/**
156 * struct aml_enc_params - General encoding parameters
157 * @bitrate: target bitrate in bits per second
158 * @num_b_frame: number of b frames between p-frame
159 * @rc_frame: frame based rate control
160 * @rc_mb: macroblock based rate control
161 * @seq_hdr_mode: H.264 sequence header is encoded separately or joined
162 * with the first frame
163 * @intra_period: I frame period
164 * @gop_size: group of picture size, it's used as the intra frame period
165 * @framerate_num: frame rate numerator. ex: framerate_num=30 and
166 * framerate_denom=1 menas FPS is 30
167 * @framerate_denom: frame rate denominator. ex: framerate_num=30 and
168 * framerate_denom=1 menas FPS is 30
169 * @h264_max_qp: Max value for H.264 quantization parameter
170 * @h264_profile: V4L2 defined H.264 profile
171 * @h264_level: V4L2 defined H.264 level
172 * @force_intra: force/insert intra frame
173 */
174struct aml_enc_params {
175 unsigned int bitrate;
176 unsigned int num_b_frame;
177 unsigned int rc_frame;
178 unsigned int rc_mb;
179 unsigned int seq_hdr_mode;
180 unsigned int intra_period;
181 unsigned int gop_size;
182 unsigned int framerate_num;
183 unsigned int framerate_denom;
184 unsigned int h264_max_qp;
185 unsigned int h264_profile;
186 unsigned int h264_level;
187 unsigned int force_intra;
188};
189
190/**
191 * struct aml_vcodec_pm - Power management data structure
192 */
193struct aml_vcodec_pm {
194 struct clk *vdec_bus_clk_src;
195 struct clk *vencpll;
196
197 struct clk *vcodecpll;
198 struct clk *univpll_d2;
199 struct clk *clk_cci400_sel;
200 struct clk *vdecpll;
201 struct clk *vdec_sel;
202 struct clk *vencpll_d2;
203 struct clk *venc_sel;
204 struct clk *univpll1_d2;
205 struct clk *venc_lt_sel;
206 struct device *larbvdec;
207 struct device *larbvenc;
208 struct device *larbvenclt;
209 struct device *dev;
210 struct aml_vcodec_dev *amldev;
211};
212
213/**
214 * struct vdec_pic_info - picture size information
215 * @visible_width: picture width
216 * @visible_height: picture height
217 * @coded_width: picture buffer width (64 aligned up from pic_w)
218 * @coded_height: picture buffer heiht (64 aligned up from pic_h)
219 * @y_bs_sz: Y bitstream size
220 * @c_bs_sz: CbCr bitstream size
221 * @y_len_sz: additional size required to store decompress information for y
222 * plane
223 * @c_len_sz: additional size required to store decompress information for cbcr
224 * plane
225 * E.g. suppose picture size is 176x144,
226 * buffer size will be aligned to 176x160.
227 */
228struct vdec_pic_info {
229 unsigned int visible_width;
230 unsigned int visible_height;
231 unsigned int coded_width;
232 unsigned int coded_height;
233 unsigned int y_bs_sz;
234 unsigned int c_bs_sz;
235 unsigned int y_len_sz;
236 unsigned int c_len_sz;
237};
238
239struct aml_vdec_pic_infos {
240 u32 visible_width;
241 u32 visible_height;
242 u32 coded_width;
243 u32 coded_height;
244 u32 dpb_size;
245};
246
247struct aml_vdec_hdr_infos {
248 /*
249 * bit 29 : present_flag
250 * bit 28-26: video_format "component", "PAL", "NTSC", "SECAM", "MAC", "unspecified"
251 * bit 25 : range "limited", "full_range"
252 * bit 24 : color_description_present_flag
253 * bit 23-16: color_primaries "unknown", "bt709", "undef", "bt601",
254 * "bt470m", "bt470bg", "smpte170m", "smpte240m", "film", "bt2020"
255 * bit 15-8 : transfer_characteristic unknown", "bt709", "undef", "bt601",
256 * "bt470m", "bt470bg", "smpte170m", "smpte240m",
257 * "linear", "log100", "log316", "iec61966-2-4",
258 * "bt1361e", "iec61966-2-1", "bt2020-10", "bt2020-12",
259 * "smpte-st-2084", "smpte-st-428"
260 * bit 7-0 : matrix_coefficient "GBR", "bt709", "undef", "bt601",
261 * "fcc", "bt470bg", "smpte170m", "smpte240m",
262 * "YCgCo", "bt2020nc", "bt2020c"
263 */
264 u32 signal_type;
265 struct vframe_master_display_colour_s color_parms;
266};
267
268struct aml_dec_params {
269 u32 dec_parms_status;
270 u32 es_need_header;
271 u32 double_write_mode;
272 u32 buffer_mode;
273 u32 buffer_width;
274 u32 buffer_height;
275 u32 buffer_margin;
276 struct aml_vdec_pic_infos pic;
277 struct aml_vdec_hdr_infos hdr;
278};
279
280struct v4l2_config_parm {
281 u32 type;
282 u32 length;
283 union {
284 struct aml_dec_params dec;
285 struct aml_enc_params enc;
286 u8 data[200];
287 } parm;
288 u8 buf[4096];
289};
290
291enum aml_thread_type {
292 AML_THREAD_OUTPUT,
293 AML_THREAD_CAPTURE,
294};
295
296typedef void (*aml_thread_func)(struct aml_vcodec_ctx *ctx);
297
298struct aml_vdec_thread {
299 struct list_head node;
300 spinlock_t lock;
301 struct semaphore sem;
302 struct task_struct *task;
303 enum aml_thread_type type;
304 void *priv;
305 int stop;
306
307 aml_thread_func func;
308};
309
310/**
311 * struct aml_vcodec_ctx - Context (instance) private data.
312 *
313 * @type: type of the instance - decoder or encoder
314 * @dev: pointer to the aml_vcodec_dev of the device
315 * @list: link to ctx_list of aml_vcodec_dev
316 * @fh: struct v4l2_fh
317 * @m2m_ctx: pointer to the v4l2_m2m_ctx of the context
318 * @q_data: store information of input and output queue
319 * of the context
320 * @id: index of the context that this structure describes
321 * @state: state of the context
322 * @param_change: indicate encode parameter type
323 * @enc_params: encoding parameters
324 * @dec_if: hooked decoder driver interface
325 * @enc_if: hoooked encoder driver interface
326 * @drv_handle: driver handle for specific decode/encode instance
327 *
328 * @picinfo: store picture info after header parsing
329 * @dpb_size: store dpb count after header parsing
330 * @int_cond: variable used by the waitqueue
331 * @int_type: type of the last interrupt
332 * @queue: waitqueue that can be used to wait for this context to
333 * finish
334 * @irq_status: irq status
335 *
336 * @ctrl_hdl: handler for v4l2 framework
337 * @decode_work: worker for the decoding
338 * @encode_work: worker for the encoding
339 * @last_decoded_picinfo: pic information get from latest decode
340 * @empty_flush_buf: a fake size-0 capture buffer that indicates flush
341 *
342 * @colorspace: enum v4l2_colorspace; supplemental to pixelformat
343 * @ycbcr_enc: enum v4l2_ycbcr_encoding, Y'CbCr encoding
344 * @quantization: enum v4l2_quantization, colorspace quantization
345 * @xfer_func: enum v4l2_xfer_func, colorspace transfer function
346 * @lock: protect variables accessed by V4L2 threads and worker thread such as
347 * aml_video_dec_buf.
348 */
349struct aml_vcodec_ctx {
350 enum aml_instance_type type;
351 struct aml_vcodec_dev *dev;
352 struct list_head list;
353
354 struct v4l2_fh fh;
355 struct v4l2_m2m_ctx *m2m_ctx;
356 struct aml_vdec_adapt *ada_ctx;
357 struct aml_q_data q_data[2];
358 int id;
359 struct mutex state_lock;
360 enum aml_instance_state state;
361 enum aml_encode_param param_change;
362 struct aml_enc_params enc_params;
363
364 const struct vdec_common_if *dec_if;
365 const struct venc_common_if *enc_if;
366 unsigned long drv_handle;
367
368 struct vdec_pic_info picinfo;
369 int dpb_size;
370
371 int int_cond;
372 int int_type;
373 wait_queue_head_t queue;
374 unsigned int irq_status;
375
376 struct v4l2_ctrl_handler ctrl_hdl;
377 struct work_struct decode_work;
378 struct work_struct encode_work;
379 struct vdec_pic_info last_decoded_picinfo;
380 struct aml_video_dec_buf *empty_flush_buf;
381
382 enum v4l2_colorspace colorspace;
383 enum v4l2_ycbcr_encoding ycbcr_enc;
384 enum v4l2_quantization quantization;
385 enum v4l2_xfer_func xfer_func;
386
387 int decoded_frame_cnt;
388 struct mutex lock;
389 struct completion comp;
390 bool has_receive_eos;
391 struct list_head vdec_thread_list;
392 bool is_drm_mode;
393 bool is_stream_mode;
394 int buf_used_count;
395 bool receive_cmd_stop;
396 bool scatter_mem_enable;
397 bool param_sets_from_ucode;
398 bool v4l_codec_ready;
399 bool v4l_codec_dpb_ready;
400 wait_queue_head_t wq;
401 spinlock_t slock;
402 struct v4l2_config_parm config;
403 bool is_stream_off;
404};
405
406/**
407 * struct aml_vcodec_dev - driver data
408 * @v4l2_dev: V4L2 device to register video devices for.
409 * @vfd_dec: Video device for decoder
410 * @vfd_enc: Video device for encoder.
411 *
412 * @m2m_dev_dec: m2m device for decoder
413 * @m2m_dev_enc: m2m device for encoder.
414 * @plat_dev: platform device
415 * @vpu_plat_dev: aml vpu platform device
416 * @alloc_ctx: VB2 allocator context
417 * (for allocations without kernel mapping).
418 * @ctx_list: list of struct aml_vcodec_ctx
419 * @irqlock: protect data access by irq handler and work thread
420 * @curr_ctx: The context that is waiting for codec hardware
421 *
422 * @reg_base: Mapped address of AML Vcodec registers.
423 *
424 * @id_counter: used to identify current opened instance
425 *
426 * @encode_workqueue: encode work queue
427 *
428 * @int_cond: used to identify interrupt condition happen
429 * @int_type: used to identify what kind of interrupt condition happen
430 * @dev_mutex: video_device lock
431 * @queue: waitqueue for waiting for completion of device commands
432 *
433 * @dec_irq: decoder irq resource
434 * @enc_irq: h264 encoder irq resource
435 * @enc_lt_irq: vp8 encoder irq resource
436 *
437 * @dec_mutex: decoder hardware lock
438 * @enc_mutex: encoder hardware lock.
439 *
440 * @pm: power management control
441 * @dec_capability: used to identify decode capability, ex: 4k
442 * @enc_capability: used to identify encode capability
443 */
444struct aml_vcodec_dev {
445 struct v4l2_device v4l2_dev;
446 struct video_device *vfd_dec;
447 struct video_device *vfd_enc;
448 struct file *filp;
449
450 struct v4l2_m2m_dev *m2m_dev_dec;
451 struct v4l2_m2m_dev *m2m_dev_enc;
452 struct platform_device *plat_dev;
453 struct platform_device *vpu_plat_dev;//??
454 struct vb2_alloc_ctx *alloc_ctx;//??
455 struct list_head ctx_list;
456 spinlock_t irqlock;
457 struct aml_vcodec_ctx *curr_ctx;
458 void __iomem *reg_base[NUM_MAX_VCODEC_REG_BASE];
459
460 unsigned long id_counter;
461
462 struct workqueue_struct *decode_workqueue;
463 struct workqueue_struct *encode_workqueue;
464 int int_cond;
465 int int_type;
466 struct mutex dev_mutex;
467 wait_queue_head_t queue;
468
469 int dec_irq;
470 int enc_irq;
471 int enc_lt_irq;
472
473 struct mutex dec_mutex;
474 struct mutex enc_mutex;
475
476 struct aml_vcodec_pm pm;
477 unsigned int dec_capability;
478 unsigned int enc_capability;
479};
480
481static inline struct aml_vcodec_ctx *fh_to_ctx(struct v4l2_fh *fh)
482{
483 return container_of(fh, struct aml_vcodec_ctx, fh);
484}
485
486static inline struct aml_vcodec_ctx *ctrl_to_ctx(struct v4l2_ctrl *ctrl)
487{
488 return container_of(ctrl->handler, struct aml_vcodec_ctx, ctrl_hdl);
489}
490
491#endif /* _AML_VCODEC_DRV_H_ */
492
generated by cgit at 2024-05-17 09:31:36 (GMT)