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1/*
2* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
3*
4* This program is free software; you can redistribute it and/or modify
5* it under the terms of the GNU General Public License as published by
6* the Free Software Foundation; either version 2 of the License, or
7* (at your option) any later version.
8*
9* This program is distributed in the hope that it will be useful, but WITHOUT
10* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12* more details.
13*
14* You should have received a copy of the GNU General Public License along
15* with this program; if not, write to the Free Software Foundation, Inc.,
16* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17*
18* Description:
19*/
20#ifndef _AML_VCODEC_DRV_H_
21#define _AML_VCODEC_DRV_H_
22
23#include <linux/platform_device.h>
24#include <linux/videodev2.h>
25#include <media/v4l2-ctrls.h>
26#include <media/v4l2-device.h>
27#include <media/v4l2-ioctl.h>
28#include <media/videobuf2-core.h>
29#include <linux/amlogic/media/vfm/vframe.h>
30#include "aml_vcodec_util.h"
31
32#define AML_VCODEC_DRV_NAME "aml_vcodec_drv"
33#define AML_VCODEC_DEC_NAME "aml-vcodec-dec"
34#define AML_VCODEC_ENC_NAME "aml-vcodec-enc"
35#define AML_PLATFORM_STR "platform:amlogic"
36
37#define AML_VCODEC_MAX_PLANES 3
38#define AML_V4L2_BENCHMARK 0
39#define WAIT_INTR_TIMEOUT_MS 1000
40
41/* codec types of get/set parms. */
42#define V4L2_CONFIG_PARM_ENCODE (0)
43#define V4L2_CONFIG_PARM_DECODE (1)
44
45/* types of decode parms. */
46#define V4L2_CONFIG_PARM_DECODE_CFGINFO (1 << 0)
47#define V4L2_CONFIG_PARM_DECODE_PSINFO (1 << 1)
48#define V4L2_CONFIG_PARM_DECODE_HDRINFO (1 << 2)
49#define V4L2_CONFIG_PARM_DECODE_CNTINFO (1 << 3)
50
51/* amlogic event define. */
52/* #define V4L2_EVENT_SRC_CH_RESOLUTION (1 << 0) */
53#define V4L2_EVENT_SRC_CH_HDRINFO (1 << 1)
54#define V4L2_EVENT_SRC_CH_PSINFO (1 << 2)
55#define V4L2_EVENT_SRC_CH_CNTINFO (1 << 3)
56
57/* exception handing */
58#define V4L2_EVENT_REQUEST_RESET (1 << 8)
59#define V4L2_EVENT_REQUEST_EXIT (1 << 9)
60
61/**
62 * enum aml_hw_reg_idx - AML hw register base index
63 */
64enum aml_hw_reg_idx {
65 VDEC_SYS,
66 VDEC_MISC,
67 VDEC_LD,
68 VDEC_TOP,
69 VDEC_CM,
70 VDEC_AD,
71 VDEC_AV,
72 VDEC_PP,
73 VDEC_HWD,
74 VDEC_HWQ,
75 VDEC_HWB,
76 VDEC_HWG,
77 NUM_MAX_VDEC_REG_BASE,
78 /* h264 encoder */
79 VENC_SYS = NUM_MAX_VDEC_REG_BASE,
80 /* vp8 encoder */
81 VENC_LT_SYS,
82 NUM_MAX_VCODEC_REG_BASE
83};
84
85/**
86 * enum aml_instance_type - The type of an AML Vcodec instance.
87 */
88enum aml_instance_type {
89 AML_INST_DECODER = 0,
90 AML_INST_ENCODER = 1,
91};
92
93/**
94 * enum aml_instance_state - The state of an AML Vcodec instance.
95 * @AML_STATE_IDLE - default state when instance is created
96 * @AML_STATE_INIT - vcodec instance is initialized
97 * @AML_STATE_PROBE - vdec/venc had sps/pps header parsed/encoded
98 * @AML_STATE_ACTIVE - vdec is ready for work.
99 * @AML_STATE_FLUSHING - vdec is flushing. Only used by decoder
100 * @AML_STATE_FLUSHED - decoder has transacted the last frame.
101 * @AML_STATE_RESET - decoder has be reset after flush.
102 * @AML_STATE_ABORT - vcodec should be aborted
103 */
104enum aml_instance_state {
105 AML_STATE_IDLE,
106 AML_STATE_INIT,
107 AML_STATE_PROBE,
108 AML_STATE_READY,
109 AML_STATE_ACTIVE,
110 AML_STATE_FLUSHING,
111 AML_STATE_FLUSHED,
112 AML_STATE_RESET,
113 AML_STATE_ABORT,
114};
115
116/**
117 * struct aml_encode_param - General encoding parameters type
118 */
119enum aml_encode_param {
120 AML_ENCODE_PARAM_NONE = 0,
121 AML_ENCODE_PARAM_BITRATE = (1 << 0),
122 AML_ENCODE_PARAM_FRAMERATE = (1 << 1),
123 AML_ENCODE_PARAM_INTRA_PERIOD = (1 << 2),
124 AML_ENCODE_PARAM_FORCE_INTRA = (1 << 3),
125 AML_ENCODE_PARAM_GOP_SIZE = (1 << 4),
126};
127
128enum aml_fmt_type {
129 AML_FMT_DEC = 0,
130 AML_FMT_ENC = 1,
131 AML_FMT_FRAME = 2,
132};
133
134/**
135 * struct aml_video_fmt - Structure used to store information about pixelformats
136 */
137struct aml_video_fmt {
138 u32 fourcc;
139 enum aml_fmt_type type;
140 u32 num_planes;
141};
142
143/**
144 * struct aml_codec_framesizes - Structure used to store information about
145 * framesizes
146 */
147struct aml_codec_framesizes {
148 u32 fourcc;
149 struct v4l2_frmsize_stepwise stepwise;
150};
151
152/**
153 * struct aml_q_type - Type of queue
154 */
155enum aml_q_type {
156 AML_Q_DATA_SRC = 0,
157 AML_Q_DATA_DST = 1,
158};
159
160/**
161 * struct aml_q_data - Structure used to store information about queue
162 */
163struct aml_q_data {
164 unsigned int visible_width;
165 unsigned int visible_height;
166 unsigned int coded_width;
167 unsigned int coded_height;
168 enum v4l2_field field;
169 unsigned int bytesperline[AML_VCODEC_MAX_PLANES];
170 unsigned int sizeimage[AML_VCODEC_MAX_PLANES];
171 struct aml_video_fmt *fmt;
172 bool resolution_changed;
173};
174
175/**
176 * struct aml_enc_params - General encoding parameters
177 * @bitrate: target bitrate in bits per second
178 * @num_b_frame: number of b frames between p-frame
179 * @rc_frame: frame based rate control
180 * @rc_mb: macroblock based rate control
181 * @seq_hdr_mode: H.264 sequence header is encoded separately or joined
182 * with the first frame
183 * @intra_period: I frame period
184 * @gop_size: group of picture size, it's used as the intra frame period
185 * @framerate_num: frame rate numerator. ex: framerate_num=30 and
186 * framerate_denom=1 menas FPS is 30
187 * @framerate_denom: frame rate denominator. ex: framerate_num=30 and
188 * framerate_denom=1 menas FPS is 30
189 * @h264_max_qp: Max value for H.264 quantization parameter
190 * @h264_profile: V4L2 defined H.264 profile
191 * @h264_level: V4L2 defined H.264 level
192 * @force_intra: force/insert intra frame
193 */
194struct aml_enc_params {
195 unsigned int bitrate;
196 unsigned int num_b_frame;
197 unsigned int rc_frame;
198 unsigned int rc_mb;
199 unsigned int seq_hdr_mode;
200 unsigned int intra_period;
201 unsigned int gop_size;
202 unsigned int framerate_num;
203 unsigned int framerate_denom;
204 unsigned int h264_max_qp;
205 unsigned int h264_profile;
206 unsigned int h264_level;
207 unsigned int force_intra;
208};
209
210/**
211 * struct aml_vcodec_pm - Power management data structure
212 */
213struct aml_vcodec_pm {
214 struct clk *vdec_bus_clk_src;
215 struct clk *vencpll;
216
217 struct clk *vcodecpll;
218 struct clk *univpll_d2;
219 struct clk *clk_cci400_sel;
220 struct clk *vdecpll;
221 struct clk *vdec_sel;
222 struct clk *vencpll_d2;
223 struct clk *venc_sel;
224 struct clk *univpll1_d2;
225 struct clk *venc_lt_sel;
226 struct device *larbvdec;
227 struct device *larbvenc;
228 struct device *larbvenclt;
229 struct device *dev;
230 struct aml_vcodec_dev *amldev;
231};
232
233/**
234 * struct vdec_pic_info - picture size information
235 * @visible_width: picture width
236 * @visible_height: picture height
237 * @coded_width: picture buffer width (64 aligned up from pic_w)
238 * @coded_height: picture buffer heiht (64 aligned up from pic_h)
239 * @y_bs_sz: Y bitstream size
240 * @c_bs_sz: CbCr bitstream size
241 * @y_len_sz: additional size required to store decompress information for y
242 * plane
243 * @c_len_sz: additional size required to store decompress information for cbcr
244 * plane
245 * E.g. suppose picture size is 176x144,
246 * buffer size will be aligned to 176x160.
247 */
248struct vdec_pic_info {
249 unsigned int visible_width;
250 unsigned int visible_height;
251 unsigned int coded_width;
252 unsigned int coded_height;
253 unsigned int y_bs_sz;
254 unsigned int c_bs_sz;
255 unsigned int y_len_sz;
256 unsigned int c_len_sz;
257 int profile_idc;
258};
259
260struct aml_vdec_cfg_infos {
261 u32 double_write_mode;
262 u32 init_width;
263 u32 init_height;
264 u32 ref_buf_margin;
265 u32 block_mode;
266};
267
268struct aml_vdec_hdr_infos {
269 /*
270 * bit 29 : present_flag
271 * bit 28-26: video_format "component", "PAL", "NTSC", "SECAM", "MAC", "unspecified"
272 * bit 25 : range "limited", "full_range"
273 * bit 24 : color_description_present_flag
274 * bit 23-16: color_primaries "unknown", "bt709", "undef", "bt601",
275 * "bt470m", "bt470bg", "smpte170m", "smpte240m", "film", "bt2020"
276 * bit 15-8 : transfer_characteristic unknown", "bt709", "undef", "bt601",
277 * "bt470m", "bt470bg", "smpte170m", "smpte240m",
278 * "linear", "log100", "log316", "iec61966-2-4",
279 * "bt1361e", "iec61966-2-1", "bt2020-10", "bt2020-12",
280 * "smpte-st-2084", "smpte-st-428"
281 * bit 7-0 : matrix_coefficient "GBR", "bt709", "undef", "bt601",
282 * "fcc", "bt470bg", "smpte170m", "smpte240m",
283 * "YCgCo", "bt2020nc", "bt2020c"
284 */
285 u32 signal_type;
286 struct vframe_master_display_colour_s color_parms;
287};
288
289struct aml_vdec_ps_infos {
290 u32 visible_width;
291 u32 visible_height;
292 u32 coded_width;
293 u32 coded_height;
294 u32 profile;
295 u32 mb_width;
296 u32 mb_height;
297 u32 dpb_size;
298 u32 ref_frames;
299 u32 reorder_frames;
300};
301
302struct aml_vdec_cnt_infos {
303 u32 bit_rate;
304 u32 frame_count;
305 u32 error_frame_count;
306 u32 drop_frame_count;
307 u32 total_data;
308};
309
310struct aml_dec_params {
311 u32 parms_status;
312 struct aml_vdec_cfg_infos cfg;
313 struct aml_vdec_ps_infos ps;
314 struct aml_vdec_hdr_infos hdr;
315 struct aml_vdec_cnt_infos cnt;
316};
317
318struct v4l2_config_parm {
319 u32 type;
320 u32 length;
321 union {
322 struct aml_dec_params dec;
323 struct aml_enc_params enc;
324 u8 data[200];
325 } parm;
326 u8 buf[4096];
327};
328
329enum aml_thread_type {
330 AML_THREAD_OUTPUT,
331 AML_THREAD_CAPTURE,
332};
333
334typedef void (*aml_thread_func)(struct aml_vcodec_ctx *ctx);
335
336struct aml_vdec_thread {
337 struct list_head node;
338 spinlock_t lock;
339 struct semaphore sem;
340 struct task_struct *task;
341 enum aml_thread_type type;
342 void *priv;
343 int stop;
344
345 aml_thread_func func;
346};
347
348/**
349 * struct aml_vcodec_ctx - Context (instance) private data.
350 *
351 * @type: type of the instance - decoder or encoder
352 * @dev: pointer to the aml_vcodec_dev of the device
353 * @list: link to ctx_list of aml_vcodec_dev
354 * @fh: struct v4l2_fh
355 * @m2m_ctx: pointer to the v4l2_m2m_ctx of the context
356 * @q_data: store information of input and output queue
357 * of the context
358 * @id: index of the context that this structure describes
359 * @state: state of the context
360 * @param_change: indicate encode parameter type
361 * @enc_params: encoding parameters
362 * @dec_if: hooked decoder driver interface
363 * @enc_if: hoooked encoder driver interface
364 * @drv_handle: driver handle for specific decode/encode instance
365 *
366 * @picinfo: store picture info after header parsing
367 * @dpb_size: store dpb count after header parsing
368 * @int_cond: variable used by the waitqueue
369 * @int_type: type of the last interrupt
370 * @queue: waitqueue that can be used to wait for this context to
371 * finish
372 * @irq_status: irq status
373 *
374 * @ctrl_hdl: handler for v4l2 framework
375 * @decode_work: worker for the decoding
376 * @encode_work: worker for the encoding
377 * @last_decoded_picinfo: pic information get from latest decode
378 * @empty_flush_buf: a fake size-0 capture buffer that indicates flush
379 *
380 * @colorspace: enum v4l2_colorspace; supplemental to pixelformat
381 * @ycbcr_enc: enum v4l2_ycbcr_encoding, Y'CbCr encoding
382 * @quantization: enum v4l2_quantization, colorspace quantization
383 * @xfer_func: enum v4l2_xfer_func, colorspace transfer function
384 * @lock: protect variables accessed by V4L2 threads and worker thread such as
385 * aml_video_dec_buf.
386 */
387struct aml_vcodec_ctx {
388 enum aml_instance_type type;
389 struct aml_vcodec_dev *dev;
390 struct list_head list;
391
392 struct v4l2_fh fh;
393 struct v4l2_m2m_ctx *m2m_ctx;
394 struct aml_vdec_adapt *ada_ctx;
395 struct aml_q_data q_data[2];
396 int id;
397 struct mutex state_lock;
398 enum aml_instance_state state;
399 enum aml_encode_param param_change;
400 struct aml_enc_params enc_params;
401
402 const struct vdec_common_if *dec_if;
403 const struct venc_common_if *enc_if;
404 unsigned long drv_handle;
405
406 struct vdec_pic_info picinfo;
407 int dpb_size;
408
409 int int_cond;
410 int int_type;
411 wait_queue_head_t queue;
412 unsigned int irq_status;
413
414 struct v4l2_ctrl_handler ctrl_hdl;
415 struct work_struct decode_work;
416 struct work_struct encode_work;
417 struct vdec_pic_info last_decoded_picinfo;
418 struct aml_video_dec_buf *empty_flush_buf;
419
420 enum v4l2_colorspace colorspace;
421 enum v4l2_ycbcr_encoding ycbcr_enc;
422 enum v4l2_quantization quantization;
423 enum v4l2_xfer_func xfer_func;
424
425 int decoded_frame_cnt;
426 struct mutex lock;
427 struct completion comp;
428 bool has_receive_eos;
429 struct list_head vdec_thread_list;
430 bool is_drm_mode;
431 bool is_stream_mode;
432 int buf_used_count;
433 bool receive_cmd_stop;
434 bool scatter_mem_enable;
435 bool param_sets_from_ucode;
436 bool v4l_codec_ready;
437 bool v4l_codec_dpb_ready;
438 wait_queue_head_t wq;
439 spinlock_t slock;
440 struct v4l2_config_parm config;
441 bool is_stream_off;
442};
443
444/**
445 * struct aml_vcodec_dev - driver data
446 * @v4l2_dev: V4L2 device to register video devices for.
447 * @vfd_dec: Video device for decoder
448 * @vfd_enc: Video device for encoder.
449 *
450 * @m2m_dev_dec: m2m device for decoder
451 * @m2m_dev_enc: m2m device for encoder.
452 * @plat_dev: platform device
453 * @vpu_plat_dev: aml vpu platform device
454 * @alloc_ctx: VB2 allocator context
455 * (for allocations without kernel mapping).
456 * @ctx_list: list of struct aml_vcodec_ctx
457 * @irqlock: protect data access by irq handler and work thread
458 * @curr_ctx: The context that is waiting for codec hardware
459 *
460 * @reg_base: Mapped address of AML Vcodec registers.
461 *
462 * @id_counter: used to identify current opened instance
463 *
464 * @encode_workqueue: encode work queue
465 *
466 * @int_cond: used to identify interrupt condition happen
467 * @int_type: used to identify what kind of interrupt condition happen
468 * @dev_mutex: video_device lock
469 * @queue: waitqueue for waiting for completion of device commands
470 *
471 * @dec_irq: decoder irq resource
472 * @enc_irq: h264 encoder irq resource
473 * @enc_lt_irq: vp8 encoder irq resource
474 *
475 * @dec_mutex: decoder hardware lock
476 * @enc_mutex: encoder hardware lock.
477 *
478 * @pm: power management control
479 * @dec_capability: used to identify decode capability, ex: 4k
480 * @enc_capability: used to identify encode capability
481 */
482struct aml_vcodec_dev {
483 struct v4l2_device v4l2_dev;
484 struct video_device *vfd_dec;
485 struct video_device *vfd_enc;
486 struct file *filp;
487
488 struct v4l2_m2m_dev *m2m_dev_dec;
489 struct v4l2_m2m_dev *m2m_dev_enc;
490 struct platform_device *plat_dev;
491 struct platform_device *vpu_plat_dev;//??
492 struct vb2_alloc_ctx *alloc_ctx;//??
493 struct list_head ctx_list;
494 spinlock_t irqlock;
495 struct aml_vcodec_ctx *curr_ctx;
496 void __iomem *reg_base[NUM_MAX_VCODEC_REG_BASE];
497
498 unsigned long id_counter;
499
500 struct workqueue_struct *decode_workqueue;
501 struct workqueue_struct *encode_workqueue;
502 int int_cond;
503 int int_type;
504 struct mutex dev_mutex;
505 wait_queue_head_t queue;
506
507 int dec_irq;
508 int enc_irq;
509 int enc_lt_irq;
510
511 struct mutex dec_mutex;
512 struct mutex enc_mutex;
513
514 struct aml_vcodec_pm pm;
515 unsigned int dec_capability;
516 unsigned int enc_capability;
517};
518
519static inline struct aml_vcodec_ctx *fh_to_ctx(struct v4l2_fh *fh)
520{
521 return container_of(fh, struct aml_vcodec_ctx, fh);
522}
523
524static inline struct aml_vcodec_ctx *ctrl_to_ctx(struct v4l2_ctrl *ctrl)
525{
526 return container_of(ctrl->handler, struct aml_vcodec_ctx, ctrl_hdl);
527}
528
529#endif /* _AML_VCODEC_DRV_H_ */
530
generated by cgit at 2024-05-17 07:56:14 (GMT)