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1/*
2* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
3*
4* This program is free software; you can redistribute it and/or modify
5* it under the terms of the GNU General Public License as published by
6* the Free Software Foundation; either version 2 of the License, or
7* (at your option) any later version.
8*
9* This program is distributed in the hope that it will be useful, but WITHOUT
10* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12* more details.
13*
14* You should have received a copy of the GNU General Public License along
15* with this program; if not, write to the Free Software Foundation, Inc.,
16* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17*
18* Description:
19*/
20#ifndef _AML_VCODEC_DRV_H_
21#define _AML_VCODEC_DRV_H_
22
23#include <linux/platform_device.h>
24#include <linux/videodev2.h>
25#include <media/v4l2-ctrls.h>
26#include <media/v4l2-device.h>
27#include <media/v4l2-ioctl.h>
28#include <media/videobuf2-core.h>
29#include <linux/amlogic/media/vfm/vframe.h>
30#include "aml_vcodec_util.h"
31
32#define AML_VCODEC_DRV_NAME "aml_vcodec_drv"
33#define AML_VCODEC_DEC_NAME "aml-vcodec-dec"
34#define AML_VCODEC_ENC_NAME "aml-vcodec-enc"
35#define AML_PLATFORM_STR "platform:amlogic"
36
37#define AML_VCODEC_MAX_PLANES 3
38#define AML_V4L2_BENCHMARK 0
39#define WAIT_INTR_TIMEOUT_MS 1000
40
41/* codec types of get/set parms. */
42#define V4L2_CONFIG_PARM_ENCODE (0)
43#define V4L2_CONFIG_PARM_DECODE (1)
44
45/* types of decode parms. */
46#define V4L2_CONFIG_PARM_DECODE_CFGINFO (1 << 0)
47#define V4L2_CONFIG_PARM_DECODE_PSINFO (1 << 1)
48#define V4L2_CONFIG_PARM_DECODE_HDRINFO (1 << 2)
49#define V4L2_CONFIG_PARM_DECODE_CNTINFO (1 << 3)
50
51/* amlogic event define. */
52/* #define V4L2_EVENT_SRC_CH_RESOLUTION (1 << 0) */
53#define V4L2_EVENT_SRC_CH_HDRINFO (1 << 1)
54#define V4L2_EVENT_SRC_CH_PSINFO (1 << 2)
55#define V4L2_EVENT_SRC_CH_CNTINFO (1 << 3)
56
57/* exception handing */
58#define V4L2_EVENT_REQUEST_RESET (1 << 8)
59#define V4L2_EVENT_REQUEST_EXIT (1 << 9)
60
61/* v4l buffer pool */
62#define V4L_CAP_BUFF_MAX (32)
63#define V4L_CAP_BUFF_INVALID (0)
64#define V4L_CAP_BUFF_IN_M2M (1)
65#define V4L_CAP_BUFF_IN_DEC (2)
66
67/* v4l reset mode */
68#define V4L_RESET_MODE_NORMAL (1 << 0) /* reset vdec_input and decoder. */
69#define V4L_RESET_MODE_LIGHT (1 << 1) /* just only reset decoder. */
70
71/**
72 * enum aml_hw_reg_idx - AML hw register base index
73 */
74enum aml_hw_reg_idx {
75 VDEC_SYS,
76 VDEC_MISC,
77 VDEC_LD,
78 VDEC_TOP,
79 VDEC_CM,
80 VDEC_AD,
81 VDEC_AV,
82 VDEC_PP,
83 VDEC_HWD,
84 VDEC_HWQ,
85 VDEC_HWB,
86 VDEC_HWG,
87 NUM_MAX_VDEC_REG_BASE,
88 /* h264 encoder */
89 VENC_SYS = NUM_MAX_VDEC_REG_BASE,
90 /* vp8 encoder */
91 VENC_LT_SYS,
92 NUM_MAX_VCODEC_REG_BASE
93};
94
95/**
96 * enum aml_instance_type - The type of an AML Vcodec instance.
97 */
98enum aml_instance_type {
99 AML_INST_DECODER = 0,
100 AML_INST_ENCODER = 1,
101};
102
103/**
104 * enum aml_instance_state - The state of an AML Vcodec instance.
105 * @AML_STATE_IDLE - default state when instance is created
106 * @AML_STATE_INIT - vcodec instance is initialized
107 * @AML_STATE_PROBE - vdec/venc had sps/pps header parsed/encoded
108 * @AML_STATE_ACTIVE - vdec is ready for work.
109 * @AML_STATE_FLUSHING - vdec is flushing. Only used by decoder
110 * @AML_STATE_FLUSHED - decoder has transacted the last frame.
111 * @AML_STATE_RESET - decoder has be reset after flush.
112 * @AML_STATE_ABORT - vcodec should be aborted
113 */
114enum aml_instance_state {
115 AML_STATE_IDLE,
116 AML_STATE_INIT,
117 AML_STATE_PROBE,
118 AML_STATE_READY,
119 AML_STATE_ACTIVE,
120 AML_STATE_FLUSHING,
121 AML_STATE_FLUSHED,
122 AML_STATE_RESET,
123 AML_STATE_ABORT,
124};
125
126/**
127 * struct aml_encode_param - General encoding parameters type
128 */
129enum aml_encode_param {
130 AML_ENCODE_PARAM_NONE = 0,
131 AML_ENCODE_PARAM_BITRATE = (1 << 0),
132 AML_ENCODE_PARAM_FRAMERATE = (1 << 1),
133 AML_ENCODE_PARAM_INTRA_PERIOD = (1 << 2),
134 AML_ENCODE_PARAM_FORCE_INTRA = (1 << 3),
135 AML_ENCODE_PARAM_GOP_SIZE = (1 << 4),
136};
137
138enum aml_fmt_type {
139 AML_FMT_DEC = 0,
140 AML_FMT_ENC = 1,
141 AML_FMT_FRAME = 2,
142};
143
144/**
145 * struct aml_video_fmt - Structure used to store information about pixelformats
146 */
147struct aml_video_fmt {
148 u32 fourcc;
149 enum aml_fmt_type type;
150 u32 num_planes;
151};
152
153/**
154 * struct aml_codec_framesizes - Structure used to store information about
155 * framesizes
156 */
157struct aml_codec_framesizes {
158 u32 fourcc;
159 struct v4l2_frmsize_stepwise stepwise;
160};
161
162/**
163 * struct aml_q_type - Type of queue
164 */
165enum aml_q_type {
166 AML_Q_DATA_SRC = 0,
167 AML_Q_DATA_DST = 1,
168};
169
170
171/**
172 * struct aml_q_data - Structure used to store information about queue
173 */
174struct aml_q_data {
175 unsigned int visible_width;
176 unsigned int visible_height;
177 unsigned int coded_width;
178 unsigned int coded_height;
179 enum v4l2_field field;
180 unsigned int bytesperline[AML_VCODEC_MAX_PLANES];
181 unsigned int sizeimage[AML_VCODEC_MAX_PLANES];
182 struct aml_video_fmt *fmt;
183 bool resolution_changed;
184};
185
186/**
187 * struct aml_enc_params - General encoding parameters
188 * @bitrate: target bitrate in bits per second
189 * @num_b_frame: number of b frames between p-frame
190 * @rc_frame: frame based rate control
191 * @rc_mb: macroblock based rate control
192 * @seq_hdr_mode: H.264 sequence header is encoded separately or joined
193 * with the first frame
194 * @intra_period: I frame period
195 * @gop_size: group of picture size, it's used as the intra frame period
196 * @framerate_num: frame rate numerator. ex: framerate_num=30 and
197 * framerate_denom=1 menas FPS is 30
198 * @framerate_denom: frame rate denominator. ex: framerate_num=30 and
199 * framerate_denom=1 menas FPS is 30
200 * @h264_max_qp: Max value for H.264 quantization parameter
201 * @h264_profile: V4L2 defined H.264 profile
202 * @h264_level: V4L2 defined H.264 level
203 * @force_intra: force/insert intra frame
204 */
205struct aml_enc_params {
206 unsigned int bitrate;
207 unsigned int num_b_frame;
208 unsigned int rc_frame;
209 unsigned int rc_mb;
210 unsigned int seq_hdr_mode;
211 unsigned int intra_period;
212 unsigned int gop_size;
213 unsigned int framerate_num;
214 unsigned int framerate_denom;
215 unsigned int h264_max_qp;
216 unsigned int h264_profile;
217 unsigned int h264_level;
218 unsigned int force_intra;
219};
220
221/**
222 * struct aml_vcodec_pm - Power management data structure
223 */
224struct aml_vcodec_pm {
225 struct clk *vdec_bus_clk_src;
226 struct clk *vencpll;
227
228 struct clk *vcodecpll;
229 struct clk *univpll_d2;
230 struct clk *clk_cci400_sel;
231 struct clk *vdecpll;
232 struct clk *vdec_sel;
233 struct clk *vencpll_d2;
234 struct clk *venc_sel;
235 struct clk *univpll1_d2;
236 struct clk *venc_lt_sel;
237 struct device *larbvdec;
238 struct device *larbvenc;
239 struct device *larbvenclt;
240 struct device *dev;
241 struct aml_vcodec_dev *amldev;
242};
243
244/**
245 * struct vdec_pic_info - picture size information
246 * @visible_width: picture width
247 * @visible_height: picture height
248 * @coded_width: picture buffer width (64 aligned up from pic_w)
249 * @coded_height: picture buffer heiht (64 aligned up from pic_h)
250 * @y_bs_sz: Y bitstream size
251 * @c_bs_sz: CbCr bitstream size
252 * @y_len_sz: additional size required to store decompress information for y
253 * plane
254 * @c_len_sz: additional size required to store decompress information for cbcr
255 * plane
256 * E.g. suppose picture size is 176x144,
257 * buffer size will be aligned to 176x160.
258 */
259struct vdec_pic_info {
260 unsigned int visible_width;
261 unsigned int visible_height;
262 unsigned int coded_width;
263 unsigned int coded_height;
264 unsigned int y_bs_sz;
265 unsigned int c_bs_sz;
266 unsigned int y_len_sz;
267 unsigned int c_len_sz;
268 int profile_idc;
269};
270
271struct aml_vdec_cfg_infos {
272 u32 double_write_mode;
273 u32 init_width;
274 u32 init_height;
275 u32 ref_buf_margin;
276 u32 canvas_mem_mode;
277 u32 canvas_mem_endian;
278};
279
280struct aml_vdec_hdr_infos {
281 /*
282 * bit 29 : present_flag
283 * bit 28-26: video_format "component", "PAL", "NTSC", "SECAM", "MAC", "unspecified"
284 * bit 25 : range "limited", "full_range"
285 * bit 24 : color_description_present_flag
286 * bit 23-16: color_primaries "unknown", "bt709", "undef", "bt601",
287 * "bt470m", "bt470bg", "smpte170m", "smpte240m", "film", "bt2020"
288 * bit 15-8 : transfer_characteristic unknown", "bt709", "undef", "bt601",
289 * "bt470m", "bt470bg", "smpte170m", "smpte240m",
290 * "linear", "log100", "log316", "iec61966-2-4",
291 * "bt1361e", "iec61966-2-1", "bt2020-10", "bt2020-12",
292 * "smpte-st-2084", "smpte-st-428"
293 * bit 7-0 : matrix_coefficient "GBR", "bt709", "undef", "bt601",
294 * "fcc", "bt470bg", "smpte170m", "smpte240m",
295 * "YCgCo", "bt2020nc", "bt2020c"
296 */
297 u32 signal_type;
298 struct vframe_master_display_colour_s color_parms;
299};
300
301struct aml_vdec_ps_infos {
302 u32 visible_width;
303 u32 visible_height;
304 u32 coded_width;
305 u32 coded_height;
306 u32 profile;
307 u32 mb_width;
308 u32 mb_height;
309 u32 dpb_size;
310 u32 ref_frames;
311 u32 reorder_frames;
312};
313
314struct aml_vdec_cnt_infos {
315 u32 bit_rate;
316 u32 frame_count;
317 u32 error_frame_count;
318 u32 drop_frame_count;
319 u32 total_data;
320};
321
322struct aml_dec_params {
323 u32 parms_status;
324 struct aml_vdec_cfg_infos cfg;
325 struct aml_vdec_ps_infos ps;
326 struct aml_vdec_hdr_infos hdr;
327 struct aml_vdec_cnt_infos cnt;
328};
329
330struct v4l2_config_parm {
331 u32 type;
332 u32 length;
333 union {
334 struct aml_dec_params dec;
335 struct aml_enc_params enc;
336 u8 data[200];
337 } parm;
338 u8 buf[4096];
339};
340
341struct v4l_buff_pool {
342 /*
343 * bit 31-16: buffer state
344 * bit 15- 0: buffer index
345 */
346 u32 seq[V4L_CAP_BUFF_MAX];
347 u32 in, out;
348};
349
350enum aml_thread_type {
351 AML_THREAD_OUTPUT,
352 AML_THREAD_CAPTURE,
353};
354
355typedef void (*aml_thread_func)(struct aml_vcodec_ctx *ctx);
356
357struct aml_vdec_thread {
358 struct list_head node;
359 spinlock_t lock;
360 struct semaphore sem;
361 struct task_struct *task;
362 enum aml_thread_type type;
363 void *priv;
364 int stop;
365
366 aml_thread_func func;
367};
368
369/**
370 * struct aml_vcodec_ctx - Context (instance) private data.
371 *
372 * @type: type of the instance - decoder or encoder
373 * @dev: pointer to the aml_vcodec_dev of the device
374 * @list: link to ctx_list of aml_vcodec_dev
375 * @fh: struct v4l2_fh
376 * @m2m_ctx: pointer to the v4l2_m2m_ctx of the context
377 * @q_data: store information of input and output queue
378 * of the context
379 * @id: index of the context that this structure describes
380 * @state: state of the context
381 * @param_change: indicate encode parameter type
382 * @enc_params: encoding parameters
383 * @dec_if: hooked decoder driver interface
384 * @enc_if: hoooked encoder driver interface
385 * @drv_handle: driver handle for specific decode/encode instance
386 *
387 * @picinfo: store picture info after header parsing
388 * @dpb_size: store dpb count after header parsing
389 * @int_cond: variable used by the waitqueue
390 * @int_type: type of the last interrupt
391 * @queue: waitqueue that can be used to wait for this context to
392 * finish
393 * @irq_status: irq status
394 *
395 * @ctrl_hdl: handler for v4l2 framework
396 * @decode_work: worker for the decoding
397 * @encode_work: worker for the encoding
398 * @last_decoded_picinfo: pic information get from latest decode
399 * @empty_flush_buf: a fake size-0 capture buffer that indicates flush
400 *
401 * @colorspace: enum v4l2_colorspace; supplemental to pixelformat
402 * @ycbcr_enc: enum v4l2_ycbcr_encoding, Y'CbCr encoding
403 * @quantization: enum v4l2_quantization, colorspace quantization
404 * @xfer_func: enum v4l2_xfer_func, colorspace transfer function
405 * @lock: protect variables accessed by V4L2 threads and worker thread such as
406 * aml_video_dec_buf.
407 */
408struct aml_vcodec_ctx {
409 enum aml_instance_type type;
410 struct aml_vcodec_dev *dev;
411 struct list_head list;
412
413 struct v4l2_fh fh;
414 struct v4l2_m2m_ctx *m2m_ctx;
415 struct aml_vdec_adapt *ada_ctx;
416 struct aml_q_data q_data[2];
417 int id;
418 struct mutex state_lock;
419 enum aml_instance_state state;
420 enum aml_encode_param param_change;
421 struct aml_enc_params enc_params;
422
423 const struct vdec_common_if *dec_if;
424 const struct venc_common_if *enc_if;
425 unsigned long drv_handle;
426
427 struct vdec_pic_info picinfo;
428 int dpb_size;
429
430 int int_cond;
431 int int_type;
432 wait_queue_head_t queue;
433 unsigned int irq_status;
434
435 struct v4l2_ctrl_handler ctrl_hdl;
436 struct work_struct decode_work;
437 struct work_struct encode_work;
438 struct vdec_pic_info last_decoded_picinfo;
439 struct aml_video_dec_buf *empty_flush_buf;
440
441 enum v4l2_colorspace colorspace;
442 enum v4l2_ycbcr_encoding ycbcr_enc;
443 enum v4l2_quantization quantization;
444 enum v4l2_xfer_func xfer_func;
445
446 int decoded_frame_cnt;
447 struct mutex lock;
448 struct completion comp;
449 bool has_receive_eos;
450 struct list_head vdec_thread_list;
451 bool is_drm_mode;
452 bool is_stream_mode;
453 int buf_used_count;
454 bool receive_cmd_stop;
455 bool scatter_mem_enable;
456 bool param_sets_from_ucode;
457 bool v4l_codec_ready;
458 bool v4l_codec_dpb_ready;
459 wait_queue_head_t wq;
460 spinlock_t slock;
461 struct v4l2_config_parm config;
462 bool is_stream_off;
463 int reset_flag;
464 int stop_cmd;
465 u32 display_count;
466 struct v4l_buff_pool cap_pool;
467};
468
469/**
470 * struct aml_vcodec_dev - driver data
471 * @v4l2_dev: V4L2 device to register video devices for.
472 * @vfd_dec: Video device for decoder
473 * @vfd_enc: Video device for encoder.
474 *
475 * @m2m_dev_dec: m2m device for decoder
476 * @m2m_dev_enc: m2m device for encoder.
477 * @plat_dev: platform device
478 * @vpu_plat_dev: aml vpu platform device
479 * @alloc_ctx: VB2 allocator context
480 * (for allocations without kernel mapping).
481 * @ctx_list: list of struct aml_vcodec_ctx
482 * @irqlock: protect data access by irq handler and work thread
483 * @curr_ctx: The context that is waiting for codec hardware
484 *
485 * @reg_base: Mapped address of AML Vcodec registers.
486 *
487 * @id_counter: used to identify current opened instance
488 *
489 * @encode_workqueue: encode work queue
490 *
491 * @int_cond: used to identify interrupt condition happen
492 * @int_type: used to identify what kind of interrupt condition happen
493 * @dev_mutex: video_device lock
494 * @queue: waitqueue for waiting for completion of device commands
495 *
496 * @dec_irq: decoder irq resource
497 * @enc_irq: h264 encoder irq resource
498 * @enc_lt_irq: vp8 encoder irq resource
499 *
500 * @dec_mutex: decoder hardware lock
501 * @enc_mutex: encoder hardware lock.
502 *
503 * @pm: power management control
504 * @dec_capability: used to identify decode capability, ex: 4k
505 * @enc_capability: used to identify encode capability
506 */
507struct aml_vcodec_dev {
508 struct v4l2_device v4l2_dev;
509 struct video_device *vfd_dec;
510 struct video_device *vfd_enc;
511 struct file *filp;
512
513 struct v4l2_m2m_dev *m2m_dev_dec;
514 struct v4l2_m2m_dev *m2m_dev_enc;
515 struct platform_device *plat_dev;
516 struct platform_device *vpu_plat_dev;//??
517 struct vb2_alloc_ctx *alloc_ctx;//??
518 struct list_head ctx_list;
519 spinlock_t irqlock;
520 struct aml_vcodec_ctx *curr_ctx;
521 void __iomem *reg_base[NUM_MAX_VCODEC_REG_BASE];
522
523 unsigned long id_counter;
524
525 struct workqueue_struct *decode_workqueue;
526 struct workqueue_struct *encode_workqueue;
527 int int_cond;
528 int int_type;
529 struct mutex dev_mutex;
530 wait_queue_head_t queue;
531
532 int dec_irq;
533 int enc_irq;
534 int enc_lt_irq;
535
536 struct mutex dec_mutex;
537 struct mutex enc_mutex;
538
539 struct aml_vcodec_pm pm;
540 unsigned int dec_capability;
541 unsigned int enc_capability;
542};
543
544static inline struct aml_vcodec_ctx *fh_to_ctx(struct v4l2_fh *fh)
545{
546 return container_of(fh, struct aml_vcodec_ctx, fh);
547}
548
549static inline struct aml_vcodec_ctx *ctrl_to_ctx(struct v4l2_ctrl *ctrl)
550{
551 return container_of(ctrl->handler, struct aml_vcodec_ctx, ctrl_hdl);
552}
553
554#endif /* _AML_VCODEC_DRV_H_ */
555
generated by cgit at 2024-05-17 09:55:01 (GMT)