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1/*
2 * drivers/amvdec_ports/decoder/aml_hevc_parser.h
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17
18
19#ifndef AML_HEVC_PARSER_H
20#define AML_HEVC_PARSER_H
21
22#include "../utils/common.h"
23
24#define MAX_DPB_SIZE 16 // A.4.1
25#define MAX_REFS 16
26
27#define MAX_NB_THREADS 16
28#define SHIFT_CTB_WPP 2
29
30/**
31 * 7.4.2.1
32 */
33#define MAX_SUB_LAYERS 7
34#define MAX_VPS_COUNT 16
35#define MAX_SPS_COUNT 32
36#define MAX_PPS_COUNT 256
37#define MAX_SHORT_TERM_RPS_COUNT 64
38#define MAX_CU_SIZE 128
39
40//TODO: check if this is really the maximum
41#define MAX_TRANSFORM_DEPTH 5
42
43#define MAX_TB_SIZE 32
44#define MAX_PB_SIZE 64
45#define MAX_LOG2_CTB_SIZE 6
46#define MAX_QP 51
47#define DEFAULT_INTRA_TC_OFFSET 2
48
49#define HEVC_CONTEXTS 183
50
51#define MRG_MAX_NUM_CANDS 5
52
53#define L0 0
54#define L1 1
55
56#define EPEL_EXTRA_BEFORE 1
57#define EPEL_EXTRA_AFTER 2
58#define EPEL_EXTRA 3
59
60#define FF_PROFILE_HEVC_MAIN 1
61#define FF_PROFILE_HEVC_MAIN_10 2
62#define FF_PROFILE_HEVC_MAIN_STILL_PICTURE 3
63#define FF_PROFILE_HEVC_REXT 4
64
65/**
66 * Value of the luma sample at position (x, y) in the 2D array tab.
67 */
68#define SAMPLE(tab, x, y) ((tab)[(y) * s->sps->width + (x)])
69#define SAMPLE_CTB(tab, x, y) ((tab)[(y) * min_cb_width + (x)])
70#define SAMPLE_CBF(tab, x, y) ((tab)[((y) & ((1<<log2_trafo_size)-1)) * MAX_CU_SIZE + ((x) & ((1<<log2_trafo_size)-1))])
71
72#define IS_IDR(s) (s->nal_unit_type == NAL_IDR_W_RADL || s->nal_unit_type == NAL_IDR_N_LP)
73#define IS_BLA(s) (s->nal_unit_type == NAL_BLA_W_RADL || s->nal_unit_type == NAL_BLA_W_LP || \
74 s->nal_unit_type == NAL_BLA_N_LP)
75#define IS_IRAP(s) (s->nal_unit_type >= 16 && s->nal_unit_type <= 23)
76
77/**
78 * Table 7-3: NAL unit type codes
79 */
80enum HEVCNALUnitType {
81 HEVC_NAL_TRAIL_N = 0,
82 HEVC_NAL_TRAIL_R = 1,
83 HEVC_NAL_TSA_N = 2,
84 HEVC_NAL_TSA_R = 3,
85 HEVC_NAL_STSA_N = 4,
86 HEVC_NAL_STSA_R = 5,
87 HEVC_NAL_RADL_N = 6,
88 HEVC_NAL_RADL_R = 7,
89 HEVC_NAL_RASL_N = 8,
90 HEVC_NAL_RASL_R = 9,
91 HEVC_NAL_VCL_N10 = 10,
92 HEVC_NAL_VCL_R11 = 11,
93 HEVC_NAL_VCL_N12 = 12,
94 HEVC_NAL_VCL_R13 = 13,
95 HEVC_NAL_VCL_N14 = 14,
96 HEVC_NAL_VCL_R15 = 15,
97 HEVC_NAL_BLA_W_LP = 16,
98 HEVC_NAL_BLA_W_RADL = 17,
99 HEVC_NAL_BLA_N_LP = 18,
100 HEVC_NAL_IDR_W_RADL = 19,
101 HEVC_NAL_IDR_N_LP = 20,
102 HEVC_NAL_CRA_NUT = 21,
103 HEVC_NAL_IRAP_VCL22 = 22,
104 HEVC_NAL_IRAP_VCL23 = 23,
105 HEVC_NAL_RSV_VCL24 = 24,
106 HEVC_NAL_RSV_VCL25 = 25,
107 HEVC_NAL_RSV_VCL26 = 26,
108 HEVC_NAL_RSV_VCL27 = 27,
109 HEVC_NAL_RSV_VCL28 = 28,
110 HEVC_NAL_RSV_VCL29 = 29,
111 HEVC_NAL_RSV_VCL30 = 30,
112 HEVC_NAL_RSV_VCL31 = 31,
113 HEVC_NAL_VPS = 32,
114 HEVC_NAL_SPS = 33,
115 HEVC_NAL_PPS = 34,
116 HEVC_NAL_AUD = 35,
117 HEVC_NAL_EOS_NUT = 36,
118 HEVC_NAL_EOB_NUT = 37,
119 HEVC_NAL_FD_NUT = 38,
120 HEVC_NAL_SEI_PREFIX = 39,
121 HEVC_NAL_SEI_SUFFIX = 40,
122};
123
124enum HEVCSliceType {
125 HEVC_SLICE_B = 0,
126 HEVC_SLICE_P = 1,
127 HEVC_SLICE_I = 2,
128};
129
130enum {
131 // 7.4.3.1: vps_max_layers_minus1 is in [0, 62].
132 HEVC_MAX_LAYERS = 63,
133 // 7.4.3.1: vps_max_sub_layers_minus1 is in [0, 6].
134 HEVC_MAX_SUB_LAYERS = 7,
135 // 7.4.3.1: vps_num_layer_sets_minus1 is in [0, 1023].
136 HEVC_MAX_LAYER_SETS = 1024,
137
138 // 7.4.2.1: vps_video_parameter_set_id is u(4).
139 HEVC_MAX_VPS_COUNT = 16,
140 // 7.4.3.2.1: sps_seq_parameter_set_id is in [0, 15].
141 HEVC_MAX_SPS_COUNT = 16,
142 // 7.4.3.3.1: pps_pic_parameter_set_id is in [0, 63].
143 HEVC_MAX_PPS_COUNT = 64,
144
145 // A.4.2: MaxDpbSize is bounded above by 16.
146 HEVC_MAX_DPB_SIZE = 16,
147 // 7.4.3.1: vps_max_dec_pic_buffering_minus1[i] is in [0, MaxDpbSize - 1].
148 HEVC_MAX_REFS = HEVC_MAX_DPB_SIZE,
149
150 // 7.4.3.2.1: num_short_term_ref_pic_sets is in [0, 64].
151 HEVC_MAX_SHORT_TERM_REF_PIC_SETS = 64,
152 // 7.4.3.2.1: num_long_term_ref_pics_sps is in [0, 32].
153 HEVC_MAX_LONG_TERM_REF_PICS = 32,
154
155 // A.3: all profiles require that CtbLog2SizeY is in [4, 6].
156 HEVC_MIN_LOG2_CTB_SIZE = 4,
157 HEVC_MAX_LOG2_CTB_SIZE = 6,
158
159 // E.3.2: cpb_cnt_minus1[i] is in [0, 31].
160 HEVC_MAX_CPB_CNT = 32,
161
162 // A.4.1: in table A.6 the highest level allows a MaxLumaPs of 35 651 584.
163 HEVC_MAX_LUMA_PS = 35651584,
164 // A.4.1: pic_width_in_luma_samples and pic_height_in_luma_samples are
165 // constrained to be not greater than sqrt(MaxLumaPs * 8). Hence height/
166 // width are bounded above by sqrt(8 * 35651584) = 16888.2 samples.
167 HEVC_MAX_WIDTH = 16888,
168 HEVC_MAX_HEIGHT = 16888,
169
170 // A.4.1: table A.6 allows at most 22 tile rows for any level.
171 HEVC_MAX_TILE_ROWS = 22,
172 // A.4.1: table A.6 allows at most 20 tile columns for any level.
173 HEVC_MAX_TILE_COLUMNS = 20,
174
175 // 7.4.7.1: in the worst case (tiles_enabled_flag and
176 // entropy_coding_sync_enabled_flag are both set), entry points can be
177 // placed at the beginning of every Ctb row in every tile, giving an
178 // upper bound of (num_tile_columns_minus1 + 1) * PicHeightInCtbsY - 1.
179 // Only a stream with very high resolution and perverse parameters could
180 // get near that, though, so set a lower limit here with the maximum
181 // possible value for 4K video (at most 135 16x16 Ctb rows).
182 HEVC_MAX_ENTRY_POINT_OFFSETS = HEVC_MAX_TILE_COLUMNS * 135,
183};
184
185struct ShortTermRPS {
186 u32 num_negative_pics;
187 int num_delta_pocs;
188 int rps_idx_num_delta_pocs;
189 int delta_poc[32];
190 u8 used[32];
191};
192
193struct LongTermRPS {
194 int poc[32];
195 u8 used[32];
196 u8 nb_refs;
197};
198
199struct SliceHeader {
200 u32 pps_id;
201
202 ///< address (in raster order) of the first block in the current slice segment
203 u32 slice_segment_addr;
204 ///< address (in raster order) of the first block in the current slice
205 u32 slice_addr;
206
207 enum HEVCSliceType slice_type;
208
209 int pic_order_cnt_lsb;
210
211 u8 first_slice_in_pic_flag;
212 u8 dependent_slice_segment_flag;
213 u8 pic_output_flag;
214 u8 colour_plane_id;
215
216 ///< RPS coded in the slice header itself is stored here
217 int short_term_ref_pic_set_sps_flag;
218 int short_term_ref_pic_set_size;
219 struct ShortTermRPS slice_rps;
220 const struct ShortTermRPS *short_term_rps;
221 int long_term_ref_pic_set_size;
222 struct LongTermRPS long_term_rps;
223 u32 list_entry_lx[2][32];
224
225 u8 rpl_modification_flag[2];
226 u8 no_output_of_prior_pics_flag;
227 u8 slice_temporal_mvp_enabled_flag;
228
229 u32 nb_refs[2];
230
231 u8 slice_sample_adaptive_offset_flag[3];
232 u8 mvd_l1_zero_flag;
233
234 u8 cabac_init_flag;
235 u8 disable_deblocking_filter_flag; ///< slice_header_disable_deblocking_filter_flag
236 u8 slice_loop_filter_across_slices_enabled_flag;
237 u8 collocated_list;
238
239 u32 collocated_ref_idx;
240
241 int slice_qp_delta;
242 int slice_cb_qp_offset;
243 int slice_cr_qp_offset;
244
245 u8 cu_chroma_qp_offset_enabled_flag;
246
247 int beta_offset; ///< beta_offset_div2 * 2
248 int tc_offset; ///< tc_offset_div2 * 2
249
250 u32 max_num_merge_cand; ///< 5 - 5_minus_max_num_merge_cand
251
252 u8 *entry_point_offset;
253 int * offset;
254 int * size;
255 int num_entry_point_offsets;
256
257 char slice_qp;
258
259 u8 luma_log2_weight_denom;
260 s16 chroma_log2_weight_denom;
261
262 s16 luma_weight_l0[16];
263 s16 chroma_weight_l0[16][2];
264 s16 chroma_weight_l1[16][2];
265 s16 luma_weight_l1[16];
266
267 s16 luma_offset_l0[16];
268 s16 chroma_offset_l0[16][2];
269
270 s16 luma_offset_l1[16];
271 s16 chroma_offset_l1[16][2];
272
273 int slice_ctb_addr_rs;
274};
275
276struct HEVCWindow {
277 u32 left_offset;
278 u32 right_offset;
279 u32 top_offset;
280 u32 bottom_offset;
281};
282
283struct VUI {
284 struct AVRational sar;
285
286 int overscan_info_present_flag;
287 int overscan_appropriate_flag;
288
289 int video_signal_type_present_flag;
290 int video_format;
291 int video_full_range_flag;
292 int colour_description_present_flag;
293 u8 colour_primaries;
294 u8 transfer_characteristic;
295 u8 matrix_coeffs;
296
297 int chroma_loc_info_present_flag;
298 int chroma_sample_loc_type_top_field;
299 int chroma_sample_loc_type_bottom_field;
300 int neutra_chroma_indication_flag;
301
302 int field_seq_flag;
303 int frame_field_info_present_flag;
304
305 int default_display_window_flag;
306 struct HEVCWindow def_disp_win;
307
308 int vui_timing_info_present_flag;
309 u32 vui_num_units_in_tick;
310 u32 vui_time_scale;
311 int vui_poc_proportional_to_timing_flag;
312 int vui_num_ticks_poc_diff_one_minus1;
313 int vui_hrd_parameters_present_flag;
314
315 int bitstream_restriction_flag;
316 int tiles_fixed_structure_flag;
317 int motion_vectors_over_pic_boundaries_flag;
318 int restricted_ref_pic_lists_flag;
319 int min_spatial_segmentation_idc;
320 int max_bytes_per_pic_denom;
321 int max_bits_per_min_cu_denom;
322 int log2_max_mv_length_horizontal;
323 int log2_max_mv_length_vertical;
324};
325
326struct PTLCommon {
327 u8 profile_space;
328 u8 tier_flag;
329 u8 profile_idc;
330 u8 profile_compatibility_flag[32];
331 u8 level_idc;
332 u8 progressive_source_flag;
333 u8 interlaced_source_flag;
334 u8 non_packed_constraint_flag;
335 u8 frame_only_constraint_flag;
336};
337
338struct PTL {
339 struct PTLCommon general_ptl;
340 struct PTLCommon sub_layer_ptl[HEVC_MAX_SUB_LAYERS];
341
342 u8 sub_layer_profile_present_flag[HEVC_MAX_SUB_LAYERS];
343 u8 sub_layer_level_present_flag[HEVC_MAX_SUB_LAYERS];
344};
345
346struct h265_VPS_t {
347 u8 vps_temporal_id_nesting_flag;
348 int vps_max_layers;
349 int vps_max_sub_layers; ///< vps_max_temporal_layers_minus1 + 1
350
351 struct PTL ptl;
352 int vps_sub_layer_ordering_info_present_flag;
353 u32 vps_max_dec_pic_buffering[HEVC_MAX_SUB_LAYERS];
354 u32 vps_num_reorder_pics[HEVC_MAX_SUB_LAYERS];
355 u32 vps_max_latency_increase[HEVC_MAX_SUB_LAYERS];
356 int vps_max_layer_id;
357 int vps_num_layer_sets; ///< vps_num_layer_sets_minus1 + 1
358 u8 vps_timing_info_present_flag;
359 u32 vps_num_units_in_tick;
360 u32 vps_time_scale;
361 u8 vps_poc_proportional_to_timing_flag;
362 int vps_num_ticks_poc_diff_one; ///< vps_num_ticks_poc_diff_one_minus1 + 1
363 int vps_num_hrd_parameters;
364};
365
366struct ScalingList {
367 /* This is a little wasteful, since sizeID 0 only needs 8 coeffs,
368 * and size ID 3 only has 2 arrays, not 6. */
369 u8 sl[4][6][64];
370 u8 sl_dc[2][6];
371};
372
373struct h265_SPS_t {
374 u8 vps_id;
375 u8 sps_id;
376 int chroma_format_idc;
377 u8 separate_colour_plane_flag;
378
379 struct HEVCWindow output_window;
380 struct HEVCWindow pic_conf_win;
381
382 int bit_depth;
383 int bit_depth_chroma;
384 int pixel_shift;
385 int pix_fmt;
386
387 u32 log2_max_poc_lsb;
388 int pcm_enabled_flag;
389
390 int max_sub_layers;
391 struct {
392 int max_dec_pic_buffering;
393 int num_reorder_pics;
394 int max_latency_increase;
395 } temporal_layer[HEVC_MAX_SUB_LAYERS];
396 u8 temporal_id_nesting_flag;
397
398 struct VUI vui;
399 struct PTL ptl;
400
401 u8 scaling_list_enable_flag;
402 struct ScalingList scaling_list;
403
404 u32 nb_st_rps;
405 struct ShortTermRPS st_rps[HEVC_MAX_SHORT_TERM_REF_PIC_SETS];
406
407 u8 amp_enabled_flag;
408 u8 sao_enabled;
409
410 u8 long_term_ref_pics_present_flag;
411 u16 lt_ref_pic_poc_lsb_sps[HEVC_MAX_LONG_TERM_REF_PICS];
412 u8 used_by_curr_pic_lt_sps_flag[HEVC_MAX_LONG_TERM_REF_PICS];
413 u8 num_long_term_ref_pics_sps;
414
415 struct {
416 u8 bit_depth;
417 u8 bit_depth_chroma;
418 u32 log2_min_pcm_cb_size;
419 u32 log2_max_pcm_cb_size;
420 u8 loop_filter_disable_flag;
421 } pcm;
422 u8 sps_temporal_mvp_enabled_flag;
423 u8 sps_strong_intra_smoothing_enable_flag;
424
425 u32 log2_min_cb_size;
426 u32 log2_diff_max_min_coding_block_size;
427 u32 log2_min_tb_size;
428 u32 log2_max_trafo_size;
429 u32 log2_ctb_size;
430 u32 log2_min_pu_size;
431
432 int max_transform_hierarchy_depth_inter;
433 int max_transform_hierarchy_depth_intra;
434
435 int sps_range_extension_flag;
436 int transform_skip_rotation_enabled_flag;
437 int transform_skip_context_enabled_flag;
438 int implicit_rdpcm_enabled_flag;
439 int explicit_rdpcm_enabled_flag;
440 int extended_precision_processing_flag;
441 int intra_smoothing_disabled_flag;
442 int high_precision_offsets_enabled_flag;
443 int persistent_rice_adaptation_enabled_flag;
444 int cabac_bypass_alignment_enabled_flag;
445
446 ///< coded frame dimension in various units
447 int width;
448 int height;
449 int ctb_width;
450 int ctb_height;
451 int ctb_size;
452 int min_cb_width;
453 int min_cb_height;
454 int min_tb_width;
455 int min_tb_height;
456 int min_pu_width;
457 int min_pu_height;
458 int tb_mask;
459
460 int hshift[3];
461 int vshift[3];
462
463 int qp_bd_offset;
464
465 u8 data[4096];
466 int data_size;
467};
468
469struct h265_PPS_t {
470 u32 sps_id; ///< seq_parameter_set_id
471
472 u8 sign_data_hiding_flag;
473
474 u8 cabac_init_present_flag;
475
476 int num_ref_idx_l0_default_active; ///< num_ref_idx_l0_default_active_minus1 + 1
477 int num_ref_idx_l1_default_active; ///< num_ref_idx_l1_default_active_minus1 + 1
478 int pic_init_qp_minus26;
479
480 u8 constrained_intra_pred_flag;
481 u8 transform_skip_enabled_flag;
482
483 u8 cu_qp_delta_enabled_flag;
484 int diff_cu_qp_delta_depth;
485
486 int cb_qp_offset;
487 int cr_qp_offset;
488 u8 pic_slice_level_chroma_qp_offsets_present_flag;
489 u8 weighted_pred_flag;
490 u8 weighted_bipred_flag;
491 u8 output_flag_present_flag;
492 u8 transquant_bypass_enable_flag;
493
494 u8 dependent_slice_segments_enabled_flag;
495 u8 tiles_enabled_flag;
496 u8 entropy_coding_sync_enabled_flag;
497
498 int num_tile_columns; ///< num_tile_columns_minus1 + 1
499 int num_tile_rows; ///< num_tile_rows_minus1 + 1
500 u8 uniform_spacing_flag;
501 u8 loop_filter_across_tiles_enabled_flag;
502
503 u8 seq_loop_filter_across_slices_enabled_flag;
504
505 u8 deblocking_filter_control_present_flag;
506 u8 deblocking_filter_override_enabled_flag;
507 u8 disable_dbf;
508 int beta_offset; ///< beta_offset_div2 * 2
509 int tc_offset; ///< tc_offset_div2 * 2
510
511 u8 scaling_list_data_present_flag;
512 struct ScalingList scaling_list;
513
514 u8 lists_modification_present_flag;
515 int log2_parallel_merge_level; ///< log2_parallel_merge_level_minus2 + 2
516 int num_extra_slice_header_bits;
517 u8 slice_header_extension_present_flag;
518 u8 log2_max_transform_skip_block_size;
519 u8 cross_component_prediction_enabled_flag;
520 u8 chroma_qp_offset_list_enabled_flag;
521 u8 diff_cu_chroma_qp_offset_depth;
522 u8 chroma_qp_offset_list_len_minus1;
523 char cb_qp_offset_list[6];
524 char cr_qp_offset_list[6];
525 u8 log2_sao_offset_scale_luma;
526 u8 log2_sao_offset_scale_chroma;
527
528 // Inferred parameters
529 u32 *column_width; ///< ColumnWidth
530 u32 *row_height; ///< RowHeight
531 u32 *col_bd; ///< ColBd
532 u32 *row_bd; ///< RowBd
533 int *col_idxX;
534
535 int *ctb_addr_rs_to_ts; ///< CtbAddrRSToTS
536 int *ctb_addr_ts_to_rs; ///< CtbAddrTSToRS
537 int *tile_id; ///< TileId
538 int *tile_pos_rs; ///< TilePosRS
539 int *min_tb_addr_zs; ///< MinTbAddrZS
540 int *min_tb_addr_zs_tab;///< MinTbAddrZS
541};
542
543struct h265_param_sets {
544 bool vps_parsed;
545 bool sps_parsed;
546 bool pps_parsed;
547 /* currently active parameter sets */
548 struct h265_VPS_t vps;
549 struct h265_SPS_t sps;
550 struct h265_PPS_t pps;
551};
552
553int h265_decode_extradata_ps(u8 *data, int size, struct h265_param_sets *ps);
554
555#endif /* AML_HEVC_PARSER_H */
556
557
generated by cgit at 2024-05-17 11:37:13 (GMT)